* [PATCH v6 7/9] ipic: clean up unsupported ack operations
From: Li Yang @ 2007-10-18 15:04 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
In-Reply-To: <1192719847-25045-6-git-send-email-leoli@freescale.com>
IPIC controller doesn't support ack operations. The pending registers
are read-only. The patch removes ack operations which are not needed.
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/sysdev/ipic.c | 40 ++--------------------------------------
1 files changed, 2 insertions(+), 38 deletions(-)
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index cd8590d..6835c15 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -533,42 +533,7 @@ static void ipic_mask_irq(unsigned int virq)
temp = ipic_read(ipic->regs, ipic_info[src].mask);
temp &= ~(1 << (31 - ipic_info[src].bit));
ipic_write(ipic->regs, ipic_info[src].mask, temp);
-
- spin_unlock_irqrestore(&ipic_lock, flags);
-}
-
-static void ipic_ack_irq(unsigned int virq)
-{
- struct ipic *ipic = ipic_from_irq(virq);
- unsigned int src = ipic_irq_to_hw(virq);
- unsigned long flags;
- u32 temp;
-
- spin_lock_irqsave(&ipic_lock, flags);
-
- temp = ipic_read(ipic->regs, ipic_info[src].pend);
- temp |= (1 << (31 - ipic_info[src].bit));
- ipic_write(ipic->regs, ipic_info[src].pend, temp);
-
- spin_unlock_irqrestore(&ipic_lock, flags);
-}
-
-static void ipic_mask_irq_and_ack(unsigned int virq)
-{
- struct ipic *ipic = ipic_from_irq(virq);
- unsigned int src = ipic_irq_to_hw(virq);
- unsigned long flags;
- u32 temp;
-
- spin_lock_irqsave(&ipic_lock, flags);
-
- temp = ipic_read(ipic->regs, ipic_info[src].mask);
- temp &= ~(1 << (31 - ipic_info[src].bit));
- ipic_write(ipic->regs, ipic_info[src].mask, temp);
-
- temp = ipic_read(ipic->regs, ipic_info[src].pend);
- temp |= (1 << (31 - ipic_info[src].bit));
- ipic_write(ipic->regs, ipic_info[src].pend, temp);
+ mb();
spin_unlock_irqrestore(&ipic_lock, flags);
}
@@ -626,8 +591,7 @@ static struct irq_chip ipic_irq_chip = {
.typename = " IPIC ",
.unmask = ipic_unmask_irq,
.mask = ipic_mask_irq,
- .mask_ack = ipic_mask_irq_and_ack,
- .ack = ipic_ack_irq,
+ .mask_ack = ipic_mask_irq,
.set_type = ipic_set_irq_type,
};
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* [PATCH v6 6/9] add documentation for SerDes nodes
From: Li Yang @ 2007-10-18 15:04 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
In-Reply-To: <1192719847-25045-5-git-send-email-leoli@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
Documentation/powerpc/booting-without-of.txt | 29 ++++++++++++++++++++++++++
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 8d49942..8a9372e 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -2274,6 +2274,35 @@ platforms are moved over to use the flattened-device-tree model.
phy-handle = < &serdes1 >;
};
+ p) SerDes nodes
+
+ SerDes is a serializer/deserializer used by some Freescale SoC.
+
+ Required properties:
+
+ - compatible : Should specify what this SerDes controller is compatible
+ with. Currently, this is most likely to be "fsl,serdes".
+ - reg : Offset and length of the register set for the device.
+ - protocol : Which up layer protocol is running on the serial
+ interface. Could be "sata", "pcie", "sgmii".
+ - clock : Input clock frequency for SerDes in unit of MHz.
+
+ Optional properties:
+
+ - vdd-1v : Define this property when Vdd is 1V.
+ - pcie-x2 : Define this property when using PCI Express x2 interface.
+ Valid only when protocol is set to "pcie".
+
+ Example:
+
+ serdes1:serdes@e3000 {
+ compatible = "fsl,serdes";
+ reg = <e3000 100>;
+ vdd-1v;
+ protocol = "sata";
+ clock = <d#100>;
+ };
+
More devices will be defined as this spec matures.
VII - Specifying interrupt information for devices
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* [PATCH v6 5/9] add documentation for SATA nodes
From: Li Yang @ 2007-10-18 15:04 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
In-Reply-To: <1192719847-25045-4-git-send-email-leoli@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
Documentation/powerpc/booting-without-of.txt | 32 ++++++++++++++++++++++++++
1 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index a96e853..8d49942 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -2242,6 +2242,38 @@ platforms are moved over to use the flattened-device-tree model.
available.
For Axon: 0x0000012a
+ o) SATA nodes
+
+ SATA nodes are defined to describe on-chip Serial ATA controllers.
+
+ Required properties:
+
+ - compatible : Should specify what this SATA controller is compatible
+ with.
+ - reg : Offset and length of the register set for the device.
+ - interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+
+ Recommended properties :
+
+ - phy-handle : Some SATA controller uses a shared SerDes PHY. This
+ property should specify the phandle of the SerDes node.
+
+ Example:
+
+ sata@19000 {
+ compatible = "fsl,mpc8315-sata";
+ reg = <19000 1000>;
+ interrupts = <2d 8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &serdes1 >;
+ };
+
More devices will be defined as this spec matures.
VII - Specifying interrupt information for devices
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* [PATCH v6 4/9] add platform support for MPC837x MDS board
From: Li Yang @ 2007-10-18 15:04 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
In-Reply-To: <1192719847-25045-3-git-send-email-leoli@freescale.com>
The MPC837x MDS is a new member of Freescale MDS reference system.
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/platforms/83xx/Kconfig | 12 ++++
arch/powerpc/platforms/83xx/Makefile | 1 +
arch/powerpc/platforms/83xx/mpc837x_mds.c | 103 +++++++++++++++++++++++++++++
3 files changed, 116 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/83xx/mpc837x_mds.c
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index ec305f1..0c61e7a 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -50,6 +50,11 @@ config MPC836x_MDS
help
This option enables support for the MPC836x MDS Processor Board.
+config MPC837x_MDS
+ bool "Freescale MPC837x MDS"
+ select DEFAULT_UIMAGE
+ help
+ This option enables support for the MPC837x MDS Processor Board.
endchoice
config PPC_MPC831x
@@ -75,3 +80,10 @@ config PPC_MPC836x
select PPC_UDBG_16550
select PPC_INDIRECT_PCI
default y if MPC836x_MDS
+
+config PPC_MPC837x
+ bool
+ select PPC_UDBG_16550
+ select PPC_INDIRECT_PCI
+ select FSL_SERDES
+ default y if MPC837x_MDS
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index 5a98f88..df46629 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
obj-$(CONFIG_MPC832x_MDS) += mpc832x_mds.o
+obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
new file mode 100644
index 0000000..6f1f9e5
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -0,0 +1,103 @@
+/*
+ * arch/powerpc/platforms/83xx/mpc837x_mds.c
+ *
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * MPC837x MDS board specific routines
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/pci.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/ipic.h>
+#include <asm/udbg.h>
+
+#include "mpc83xx.h"
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init mpc837x_mds_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc837x_mds_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ mpc83xx_add_bridge(np);
+#endif
+}
+
+static struct of_device_id mpc837x_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ {},
+};
+
+static int __init mpc837x_declare_of_platform_devices(void)
+{
+ if (!machine_is(mpc837x_mds))
+ return 0;
+
+ /* Publish of_device */
+ of_platform_bus_probe(NULL, mpc837x_ids, NULL);
+
+ return 0;
+}
+device_initcall(mpc837x_declare_of_platform_devices);
+
+static void __init mpc837x_mds_init_IRQ(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
+ if (!np)
+ return;
+
+ ipic_init(np, 0);
+
+ /* Initialize the default interrupt mapping priorities,
+ * in case the boot rom changed something on us.
+ */
+ ipic_set_default_priority();
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc837x_mds_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "fsl,mpc837xmds");
+}
+
+define_machine(mpc837x_mds) {
+ .name = "MPC837x MDS",
+ .probe = mpc837x_mds_probe,
+ .setup_arch = mpc837x_mds_setup_arch,
+ .init_IRQ = mpc837x_mds_init_IRQ,
+ .get_irq = ipic_get_irq,
+ .restart = mpc83xx_restart,
+ .time_init = mpc83xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* [PATCH v6 3/9] add Freescale SerDes PHY support
From: Li Yang @ 2007-10-18 15:04 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
In-Reply-To: <1192719847-25045-2-git-send-email-leoli@freescale.com>
The SerDes(serializer/deserializer) PHY block is a new SoC block used
in Freescale chips to support multiple serial interfaces, such as PCI
Express, SGMII, SATA.
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/platforms/Kconfig | 3 +
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_serdes.c | 195 ++++++++++++++++++++++++++++++++++++++
3 files changed, 199 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_serdes.c
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 229d355..0719e89 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -315,6 +315,9 @@ config FSL_ULI1575
config CPM
bool
+config FSL_SERDES
+ bool
+
source "arch/powerpc/sysdev/bestcomm/Kconfig"
endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99a77d7..2343ea4 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
mv64x60_udbg.o
obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
obj-$(CONFIG_AXON_RAM) += axonram.o
+obj-$(CONFIG_FSL_SERDES) += fsl_serdes.o
ifeq ($(CONFIG_PPC_MERGE),y)
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
diff --git a/arch/powerpc/sysdev/fsl_serdes.c b/arch/powerpc/sysdev/fsl_serdes.c
new file mode 100644
index 0000000..670015d
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_serdes.c
@@ -0,0 +1,195 @@
+/*
+ * arch/powerpc/sysdev/fsl_serdes.c
+ *
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Li Yang <leoli@freescale.com>
+ *
+ * Freescale SerDes initialization routines
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+
+#define FSL_SRDSCR0_OFFS 0x0
+#define FSL_SRDSCR0_DPP_1V2 0x00008800
+#define FSL_SRDSCR1_OFFS 0x4
+#define FSL_SRDSCR1_PLLBW 0x00000040
+#define FSL_SRDSCR2_OFFS 0x8
+#define FSL_SRDSCR2_VDD_1V2 0x00800000
+#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
+#define FSL_SRDSCR2_SEIC_SATA 0x00001414
+#define FSL_SRDSCR2_SEIC_PEX 0x00001010
+#define FSL_SRDSCR2_SEIC_SGMII 0x00000101
+#define FSL_SRDSCR3_OFFS 0xc
+#define FSL_SRDSCR3_KFR_SATA 0x10100000
+#define FSL_SRDSCR3_KPH_SATA 0x04040000
+#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
+#define FSL_SRDSCR3_SDTXL_SATA 0x00000505
+#define FSL_SRDSCR4_OFFS 0x10
+#define FSL_SRDSCR4_PROT_SATA 0x00000808
+#define FSL_SRDSCR4_PROT_PEX 0x00000101
+#define FSL_SRDSCR4_PROT_SGMII 0x00000505
+#define FSL_SRDSCR4_PLANE_X2 0x01000000
+#define FSL_SRDSCR4_RFCKS_100 0x00000000
+#define FSL_SRDSCR4_RFCKS_125 0x10000000
+#define FSL_SRDSCR4_RFCKS_150 0x30000000
+#define FSL_SRDSRSTCTL_OFFS 0x20
+#define FSL_SRDSRSTCTL_RST 0x80000000
+#define FSL_SRDSRSTCTL_SATA_RESET 0xf
+
+static int fsl_serdes_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct device_node *np = ofdev->node;
+ void __iomem *regs;
+ const char *prot;
+ const unsigned int *freq;
+ u32 rfcks;
+
+ regs = of_iomap(np, 0);
+ if (!regs)
+ return -ENOMEM;
+
+ prot = of_get_property(np, "protocol", NULL);
+ if (!prot)
+ goto out;
+ freq = of_get_property(np, "clock", NULL);
+ if (!freq)
+ goto out;
+ switch (*freq) {
+ case 100:
+ rfcks = FSL_SRDSCR4_RFCKS_100;
+ break;
+ case 125:
+ rfcks = FSL_SRDSCR4_RFCKS_125;
+ break;
+ case 150:
+ rfcks = FSL_SRDSCR4_RFCKS_150;
+ break;
+ default:
+ printk(KERN_ERR "SerDes: Wrong frequency\n");
+ goto out;
+ }
+
+ /* Use default prescale and counter */
+
+ /* 1.0V corevdd */
+ if (of_get_property(np, "vdd-1v", NULL)) {
+ /* DPPE/DPPA = 0 */
+ clrbits32(regs + FSL_SRDSCR0_OFFS, FSL_SRDSCR0_DPP_1V2);
+
+ /* VDD = 0 */
+ clrbits32(regs + FSL_SRDSCR2_OFFS, FSL_SRDSCR2_VDD_1V2);
+ }
+
+ /* protocol specific configuration */
+ if (!strcmp(prot, "sata")) {
+ /* Set and clear reset bits */
+ setbits32(regs + FSL_SRDSRSTCTL_OFFS,
+ FSL_SRDSRSTCTL_SATA_RESET);
+ mdelay(1);
+ clrbits32(regs + FSL_SRDSRSTCTL_OFFS,
+ FSL_SRDSRSTCTL_SATA_RESET);
+
+ /* Configure SRDSCR1 */
+ clrbits32(regs + FSL_SRDSCR1_OFFS, FSL_SRDSCR1_PLLBW);
+
+ /* Configure SRDSCR2 */
+ clrsetbits_be32(regs + FSL_SRDSCR2_OFFS,
+ FSL_SRDSCR2_SEIC_MASK, FSL_SRDSCR2_SEIC_SATA);
+
+ /* Configure SRDSCR3 */
+ out_be32(regs + FSL_SRDSCR3_OFFS, FSL_SRDSCR3_KFR_SATA |
+ FSL_SRDSCR3_KPH_SATA |
+ FSL_SRDSCR3_SDFM_SATA_PEX |
+ FSL_SRDSCR3_SDTXL_SATA);
+
+ /* Configure SRDSCR4 */
+ out_be32(regs + FSL_SRDSCR4_OFFS, rfcks |
+ FSL_SRDSCR4_PROT_SATA);
+
+ } else if (!strcmp(prot, "pcie")) {
+ /* Configure SRDSCR1 */
+ setbits32(regs + FSL_SRDSCR1_OFFS, FSL_SRDSCR1_PLLBW);
+
+ /* Configure SRDSCR2 */
+ clrsetbits_be32(regs + FSL_SRDSCR2_OFFS, FSL_SRDSCR2_SEIC_MASK,
+ FSL_SRDSCR2_SEIC_PEX);
+
+ /* Configure SRDSCR3 */
+ out_be32(regs + FSL_SRDSCR3_OFFS, FSL_SRDSCR3_SDFM_SATA_PEX);
+
+ /* Configure SRDSCR4 */
+ if (of_get_property(np, "pcie-x2", NULL))
+ out_be32(regs + FSL_SRDSCR4_OFFS, rfcks |
+ FSL_SRDSCR4_PROT_PEX | FSL_SRDSCR4_PLANE_X2);
+ else
+ out_be32(regs + FSL_SRDSCR4_OFFS, rfcks |
+ FSL_SRDSCR4_PROT_PEX);
+
+ } else if (!strcmp(prot, "sgmii")) {
+ /* Configure SRDSCR1 */
+ clrbits32(regs + FSL_SRDSCR1_OFFS, FSL_SRDSCR1_PLLBW);
+
+ /* Configure SRDSCR2 */
+ clrsetbits_be32(regs + FSL_SRDSCR2_OFFS, FSL_SRDSCR2_SEIC_MASK,
+ FSL_SRDSCR2_SEIC_SGMII);
+
+ /* Configure SRDSCR3 */
+ out_be32(regs + FSL_SRDSCR3_OFFS, 0);
+
+ /* Configure SRDSCR4 */
+ out_be32(regs + FSL_SRDSCR4_OFFS, rfcks |
+ FSL_SRDSCR4_PROT_SGMII);
+
+ } else {
+ printk(KERN_ERR "SerDes: Wrong protocol\n");
+ goto out;
+ }
+
+ /* Do a software reset */
+ setbits32(regs + FSL_SRDSRSTCTL_OFFS, FSL_SRDSRSTCTL_RST);
+ iounmap(regs);
+
+ dev_printk(KERN_INFO, &ofdev->dev, "Initialized as %s\n", prot);
+
+ return 0;
+out:
+ iounmap(regs);
+ return -EINVAL;
+}
+
+static struct of_device_id fsl_serdes_match[] = {
+ {
+ .compatible = "fsl,serdes",
+ },
+ {},
+};
+
+static struct of_platform_driver fsl_serdes_driver = {
+ .name = "fsl-serdes",
+ .match_table = fsl_serdes_match,
+ .probe = fsl_serdes_probe,
+};
+
+static int __init fsl_serdes_init(void)
+{
+ of_register_platform_driver(&fsl_serdes_driver);
+ return 0;
+}
+device_initcall(fsl_serdes_init);
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* [PATCH v6 2/9] ipic: add new interrupts introduced by new chip
From: Li Yang @ 2007-10-18 15:04 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
In-Reply-To: <1192719847-25045-1-git-send-email-leoli@freescale.com>
These interrupts are introduced by the latest Freescale SoC such as
MPC837x. The patch also adds comment to interrupts.
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/sysdev/ipic.c | 224 ++++++++++++++++++++++++++++++++++----------
arch/powerpc/sysdev/ipic.h | 7 +-
include/asm-powerpc/ipic.h | 12 ++-
3 files changed, 186 insertions(+), 57 deletions(-)
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 05a56e5..cd8590d 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -33,7 +33,31 @@ static struct ipic * primary_ipic;
static DEFINE_SPINLOCK(ipic_lock);
static struct ipic_info ipic_info[] = {
- [9] = {
+ [1] = { /* PEX1 CNT */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_C,
+ .force = IPIC_SIFCR_H,
+ .bit = 16,
+ .prio_mask = 0,
+ },
+ [2] = { /* PEX2 CNT */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_C,
+ .force = IPIC_SIFCR_H,
+ .bit = 17,
+ .prio_mask = 1,
+ },
+ [4] = { /* MSIR1 */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_C,
+ .force = IPIC_SIFCR_H,
+ .bit = 19,
+ .prio_mask = 3,
+ },
+ [9] = { /* UART1 */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_D,
@@ -41,7 +65,7 @@ static struct ipic_info ipic_info[] = {
.bit = 24,
.prio_mask = 0,
},
- [10] = {
+ [10] = { /* UART2 */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_D,
@@ -49,7 +73,7 @@ static struct ipic_info ipic_info[] = {
.bit = 25,
.prio_mask = 1,
},
- [11] = {
+ [11] = { /* SEC */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_D,
@@ -57,7 +81,23 @@ static struct ipic_info ipic_info[] = {
.bit = 26,
.prio_mask = 2,
},
- [14] = {
+ [12] = { /* eTSEC1 1588 */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_D,
+ .force = IPIC_SIFCR_H,
+ .bit = 27,
+ .prio_mask = 3,
+ },
+ [13] = { /* eTSEC2 1588 */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_D,
+ .force = IPIC_SIFCR_H,
+ .bit = 28,
+ .prio_mask = 4,
+ },
+ [14] = { /* I2C1 */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_D,
@@ -65,7 +105,7 @@ static struct ipic_info ipic_info[] = {
.bit = 29,
.prio_mask = 5,
},
- [15] = {
+ [15] = { /* I2C2 */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_D,
@@ -73,7 +113,7 @@ static struct ipic_info ipic_info[] = {
.bit = 30,
.prio_mask = 6,
},
- [16] = {
+ [16] = { /* SPI */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_D,
@@ -81,7 +121,7 @@ static struct ipic_info ipic_info[] = {
.bit = 31,
.prio_mask = 7,
},
- [17] = {
+ [17] = { /* IRQ1 */
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
@@ -89,7 +129,7 @@ static struct ipic_info ipic_info[] = {
.bit = 1,
.prio_mask = 5,
},
- [18] = {
+ [18] = { /* IRQ2 */
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
@@ -97,7 +137,7 @@ static struct ipic_info ipic_info[] = {
.bit = 2,
.prio_mask = 6,
},
- [19] = {
+ [19] = { /* IRQ3 */
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
@@ -105,7 +145,7 @@ static struct ipic_info ipic_info[] = {
.bit = 3,
.prio_mask = 7,
},
- [20] = {
+ [20] = { /* IRQ4 */
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
@@ -113,7 +153,7 @@ static struct ipic_info ipic_info[] = {
.bit = 4,
.prio_mask = 4,
},
- [21] = {
+ [21] = { /* IRQ5 */
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
@@ -121,7 +161,7 @@ static struct ipic_info ipic_info[] = {
.bit = 5,
.prio_mask = 5,
},
- [22] = {
+ [22] = { /* IRQ 6 */
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
@@ -129,7 +169,7 @@ static struct ipic_info ipic_info[] = {
.bit = 6,
.prio_mask = 6,
},
- [23] = {
+ [23] = { /* IRQ7 */
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
@@ -137,7 +177,7 @@ static struct ipic_info ipic_info[] = {
.bit = 7,
.prio_mask = 7,
},
- [32] = {
+ [32] = { /* TSEC1 Tx/QE High */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_A,
@@ -145,7 +185,7 @@ static struct ipic_info ipic_info[] = {
.bit = 0,
.prio_mask = 0,
},
- [33] = {
+ [33] = { /* TSEC1 Rx/QE Low */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_A,
@@ -153,7 +193,7 @@ static struct ipic_info ipic_info[] = {
.bit = 1,
.prio_mask = 1,
},
- [34] = {
+ [34] = { /* TSEC1 Err */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_A,
@@ -161,7 +201,7 @@ static struct ipic_info ipic_info[] = {
.bit = 2,
.prio_mask = 2,
},
- [35] = {
+ [35] = { /* TSEC2 Tx */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_A,
@@ -169,7 +209,7 @@ static struct ipic_info ipic_info[] = {
.bit = 3,
.prio_mask = 3,
},
- [36] = {
+ [36] = { /* TSEC2 Rx */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_A,
@@ -177,7 +217,7 @@ static struct ipic_info ipic_info[] = {
.bit = 4,
.prio_mask = 4,
},
- [37] = {
+ [37] = { /* TSEC2 Err */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_A,
@@ -185,7 +225,7 @@ static struct ipic_info ipic_info[] = {
.bit = 5,
.prio_mask = 5,
},
- [38] = {
+ [38] = { /* USB DR */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_A,
@@ -193,7 +233,7 @@ static struct ipic_info ipic_info[] = {
.bit = 6,
.prio_mask = 6,
},
- [39] = {
+ [39] = { /* USB MPH */
.pend = IPIC_SIPNR_H,
.mask = IPIC_SIMSR_H,
.prio = IPIC_SIPRR_A,
@@ -201,7 +241,47 @@ static struct ipic_info ipic_info[] = {
.bit = 7,
.prio_mask = 7,
},
- [48] = {
+ [42] = { /* eSDHC */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_B,
+ .force = IPIC_SIFCR_H,
+ .bit = 10,
+ .prio_mask = 2,
+ },
+ [44] = { /* SATA1 */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_B,
+ .force = IPIC_SIFCR_H,
+ .bit = 12,
+ .prio_mask = 4,
+ },
+ [45] = { /* SATA2 */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_B,
+ .force = IPIC_SIFCR_H,
+ .bit = 13,
+ .prio_mask = 5,
+ },
+ [46] = { /* SATA3 */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_B,
+ .force = IPIC_SIFCR_H,
+ .bit = 14,
+ .prio_mask = 6,
+ },
+ [47] = { /* SATA4 */
+ .pend = IPIC_SIPNR_H,
+ .mask = IPIC_SIMSR_H,
+ .prio = IPIC_SIPRR_B,
+ .force = IPIC_SIFCR_H,
+ .bit = 15,
+ .prio_mask = 7,
+ },
+ [48] = { /* IRQ0 */
.pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
@@ -209,7 +289,7 @@ static struct ipic_info ipic_info[] = {
.bit = 0,
.prio_mask = 4,
},
- [64] = {
+ [64] = { /* RTC SEC */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A,
@@ -217,7 +297,7 @@ static struct ipic_info ipic_info[] = {
.bit = 0,
.prio_mask = 0,
},
- [65] = {
+ [65] = { /* PIT */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A,
@@ -225,7 +305,7 @@ static struct ipic_info ipic_info[] = {
.bit = 1,
.prio_mask = 1,
},
- [66] = {
+ [66] = { /* PCI */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A,
@@ -233,7 +313,7 @@ static struct ipic_info ipic_info[] = {
.bit = 2,
.prio_mask = 2,
},
- [67] = {
+ [67] = { /* MSIR0 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_A,
@@ -241,7 +321,7 @@ static struct ipic_info ipic_info[] = {
.bit = 3,
.prio_mask = 3,
},
- [68] = {
+ [68] = { /* RTC ALR */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B,
@@ -249,7 +329,7 @@ static struct ipic_info ipic_info[] = {
.bit = 4,
.prio_mask = 0,
},
- [69] = {
+ [69] = { /* MU */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B,
@@ -257,7 +337,7 @@ static struct ipic_info ipic_info[] = {
.bit = 5,
.prio_mask = 1,
},
- [70] = {
+ [70] = { /* SBA */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B,
@@ -265,7 +345,7 @@ static struct ipic_info ipic_info[] = {
.bit = 6,
.prio_mask = 2,
},
- [71] = {
+ [71] = { /* DMA */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = IPIC_SMPRR_B,
@@ -273,91 +353,133 @@ static struct ipic_info ipic_info[] = {
.bit = 7,
.prio_mask = 3,
},
- [72] = {
+ [72] = { /* GTM4 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 8,
},
- [73] = {
+ [73] = { /* GTM8 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 9,
},
- [74] = {
+ [74] = { /* GPIO1/QE Ports */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 10,
},
- [75] = {
+ [75] = { /* GPIO2/SDDR */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 11,
},
- [76] = {
+ [76] = { /* DDR */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 12,
},
- [77] = {
+ [77] = { /* LBC */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 13,
},
- [78] = {
+ [78] = { /* GTM2 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 14,
},
- [79] = {
+ [79] = { /* GTM6 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 15,
},
- [80] = {
+ [80] = { /* PMC */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 16,
},
- [84] = {
+ [81] = { /* MSIR2 */
+ .pend = IPIC_SIPNR_L,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 17,
+ },
+ [82] = { /* MSIR3 */
+ .pend = IPIC_SIPNR_L,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 18,
+ },
+ [84] = { /* GTM3 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 20,
},
- [85] = {
+ [85] = { /* GTM7 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 21,
},
- [90] = {
+ [86] = { /* MSIR4 */
+ .pend = IPIC_SIPNR_L,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 22,
+ },
+ [87] = { /* MSIR5 */
+ .pend = IPIC_SIPNR_L,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 23,
+ },
+ [88] = { /* MSIR6 */
+ .pend = IPIC_SIPNR_L,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 24,
+ },
+ [89] = { /* MSIR7 */
+ .pend = IPIC_SIPNR_L,
+ .mask = IPIC_SIMSR_L,
+ .prio = 0,
+ .force = IPIC_SIFCR_L,
+ .bit = 25,
+ },
+ [90] = { /* GTM1 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
.force = IPIC_SIFCR_L,
.bit = 26,
},
- [91] = {
+ [91] = { /* GTM5 */
.pend = IPIC_SIPNR_L,
.mask = IPIC_SIMSR_L,
.prio = 0,
@@ -593,6 +715,10 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
* configure SICFR accordingly */
if (flags & IPIC_SPREADMODE_GRP_A)
temp |= SICFR_IPSA;
+ if (flags & IPIC_SPREADMODE_GRP_B)
+ temp |= SICFR_IPSB;
+ if (flags & IPIC_SPREADMODE_GRP_C)
+ temp |= SICFR_IPSC;
if (flags & IPIC_SPREADMODE_GRP_D)
temp |= SICFR_IPSD;
if (flags & IPIC_SPREADMODE_MIX_A)
@@ -600,7 +726,7 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
if (flags & IPIC_SPREADMODE_MIX_B)
temp |= SICFR_MPSB;
- ipic_write(ipic->regs, IPIC_SICNR, temp);
+ ipic_write(ipic->regs, IPIC_SICFR, temp);
/* handle MCP route */
temp = 0;
@@ -672,10 +798,12 @@ void ipic_set_highest_priority(unsigned int virq)
void ipic_set_default_priority(void)
{
- ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT);
- ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT);
- ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT);
- ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT);
+ ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
+ ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
+ ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
+ ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
+ ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
+ ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
}
void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
diff --git a/arch/powerpc/sysdev/ipic.h b/arch/powerpc/sysdev/ipic.h
index bb309a5..1158b8f 100644
--- a/arch/powerpc/sysdev/ipic.h
+++ b/arch/powerpc/sysdev/ipic.h
@@ -23,13 +23,12 @@
#define IPIC_IRQ_EXT7 23
/* Default Priority Registers */
-#define IPIC_SIPRR_A_DEFAULT 0x05309770
-#define IPIC_SIPRR_D_DEFAULT 0x05309770
-#define IPIC_SMPRR_A_DEFAULT 0x05309770
-#define IPIC_SMPRR_B_DEFAULT 0x05309770
+#define IPIC_PRIORITY_DEFAULT 0x05309770
/* System Global Interrupt Configuration Register */
#define SICFR_IPSA 0x00010000
+#define SICFR_IPSB 0x00020000
+#define SICFR_IPSC 0x00040000
#define SICFR_IPSD 0x00080000
#define SICFR_MPSA 0x00200000
#define SICFR_MPSB 0x00400000
diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h
index edec79d..8ff08be 100644
--- a/include/asm-powerpc/ipic.h
+++ b/include/asm-powerpc/ipic.h
@@ -20,11 +20,13 @@
/* Flags when we init the IPIC */
#define IPIC_SPREADMODE_GRP_A 0x00000001
-#define IPIC_SPREADMODE_GRP_D 0x00000002
-#define IPIC_SPREADMODE_MIX_A 0x00000004
-#define IPIC_SPREADMODE_MIX_B 0x00000008
-#define IPIC_DISABLE_MCP_OUT 0x00000010
-#define IPIC_IRQ0_MCP 0x00000020
+#define IPIC_SPREADMODE_GRP_B 0x00000002
+#define IPIC_SPREADMODE_GRP_C 0x00000004
+#define IPIC_SPREADMODE_GRP_D 0x00000008
+#define IPIC_SPREADMODE_MIX_A 0x00000010
+#define IPIC_SPREADMODE_MIX_B 0x00000020
+#define IPIC_DISABLE_MCP_OUT 0x00000040
+#define IPIC_IRQ0_MCP 0x00000080
/* IPIC registers offsets */
#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* [PATCH v6 1/9] add e300c4 entry to cputable
From: Li Yang @ 2007-10-18 15:03 UTC (permalink / raw)
To: galak, paulus, linuxppc-dev; +Cc: Li Yang
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/kernel/cputable.c | 13 ++++++++++++-
1 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index d3fb7d0..03b973f 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -888,7 +888,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_603,
.platform = "ppc603",
},
- { /* e300c3 on 83xx */
+ { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00850000,
.cpu_name = "e300c3",
@@ -899,6 +899,17 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_603,
.platform = "ppc603",
},
+ { /* e300c4 (e300c1, plus one IU) */
+ .pvr_mask = 0x7fff0000,
+ .pvr_value = 0x00860000,
+ .cpu_name = "e300c4",
+ .cpu_features = CPU_FTRS_E300,
+ .cpu_user_features = COMMON_USER,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .cpu_setup = __setup_cpu_603,
+ .platform = "ppc603",
+ },
{ /* default match, we assume split I/D cache & TB (non-601)... */
.pvr_mask = 0x00000000,
.pvr_value = 0x00000000,
--
1.5.3.2.104.g41ef
^ permalink raw reply related
* Re: [PATCH v2 3/4] Implement clockevents driver for powerpc
From: Sergei Shtylyov @ 2007-10-18 14:48 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Thomas Gleixner, Realtime Kernel
In-Reply-To: <18198.43687.44059.477047@cargo.ozlabs.ibm.com>
Paul Mackerras wrote:
>> BTW, while fixing that for classic PPC, but you've broke it for 40x / book
>>E CPU which interrupt at 0. Congratulations. :-)
> What problem do you see arising from this?
Timers firing too early.
> Paul.
WBR, Sergei
^ permalink raw reply
* Re: [PATCH 2.6.21-rt2] PowerPC: decrementer clockevent driver
From: Sergei Shtylyov @ 2007-10-18 14:45 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: linuxppc-dev, tglx, mingo, linux-kernel
In-Reply-To: <200705172142.26739.sshtylyov@ru.mvista.com>
Sergei Shtylyov wrote:
> Add PowerPC decrementer clock event driver.
> Every effort has been made to support the different implementations of the
> decrementer: the classic one (with 970 series variation), 40x and Book E
> specific ones.
> I had to make CONFIG_GENERIC_CLOCKEVENTS option selectable for the
> compatibility reasons -- this option is not compatible with the PPC64
> deterministic time accounting.
> Thanks to Daniel Walker and Thomas Gleixner for the suggestions they made...
> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
> Index: linux-2.6/arch/powerpc/Kconfig
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/Kconfig
> +++ linux-2.6/arch/powerpc/Kconfig
> @@ -317,7 +317,7 @@ config PPC_STD_MMU_32
>
> config VIRT_CPU_ACCOUNTING
> bool "Deterministic task and CPU time accounting"
> - depends on PPC64
> + depends on PPC64 && !GENERIC_CLOCKEVENTS
> default y
> help
> Select this option to enable more accurate task and CPU time
Thomas, that part of the ppc-clockevents.patch (part of the -rt patch) is
now broken, it makes CONFIG_MAX_ZONEORDER dependent on
!CONFIG_GENERIC_CLOCKEVENTS -- this is probably due to patch's fuzzy logic.
Do I need to send a patch to fix this?
WBR, Sergei
^ permalink raw reply
* Re: [PATCH] ppc44x: support for 256K PAGE_SIZE
From: Josh Boyer @ 2007-10-18 14:41 UTC (permalink / raw)
To: Yuri Tikhonov; +Cc: linuxppc-dev
In-Reply-To: <200710181730.17717.yur@emcraft.com>
On Thu, 18 Oct 2007 17:30:17 +0400
Yuri Tikhonov <yur@emcraft.com> wrote:
> On Thursday 18 October 2007 17:25, Josh Boyer wrote:
> > > Understood. The situation here is that the boards, which required these
> > > modifications, have no support in the arch/powerpc branch. So this is
> > > why we made this in arch/ppc.
> >
> > Bit of a dilemma then. What board exactly?
>
> These are the Katmai and Yucca PPC440SPe-based boards (from AMCC).
Hm... We should get those in. At this point in the kernel cycle, your
patch would be 2.6.25 material anyway so perhaps there is some time to
get Katmai and Yucca done by then.
>
> > > > Also, I'd rather see something along the lines of hugetlbfs support instead.
> > >
> > > Here I agree with Benjamin. Furthermore, IIRC the hugetlb file-system is
> > > supported for PPC64 architectures only. Here we have PPC32.
> >
> > Well that needs fixing anyway, but ok. Also, is the modified binutils
> > only required for userspace to take advantage here? Seems so, but I'd
> > just like to be sure.
>
> You are right, for userspace only.
Ok.
josh
^ permalink raw reply
* Freescale Interrupt enabling
From: Alan Bennett @ 2007-10-18 14:41 UTC (permalink / raw)
To: linuxppc-dev
We were developing with Linux 2.6.10 and a Planetcore boot loader,
however, recent work has us up and running with 2.6.23+ and U-boot
1.2.0. However, we are now running into a few challenges regarding
the differences.
Our driver writer's code isn't functioning, but it was with 2.6.10 and
planet core. The best I can tell is that the default interrupt
controller configuration isn't where it was in the planetcore/2.6.10
version.
for example, let's look at enabling timer1 / interrupt number 12
simple description.
timer1 {
name = "timer1";
compatible = "fsl,mpc8248_timer";
interrupts = <c 8>;
interrupt-parent = <&PIC>;
What should be done to consume the above description in the device
tree, program the SIU and configure the irq for request? I'm looking
through the existing drivers to get a feel, but both the enets and the
uarts are overly complex for the simple task of enabling a timer, as
our driver code already works with the irq on other linux
kernels/bootloaders.
-Alan
^ permalink raw reply
* Re: [PATCH] synchronize_irq needs a barrier
From: Herbert Xu @ 2007-10-18 14:35 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev, akpm, torvalds, linux-kernel
In-Reply-To: <1192675254.12879.29.camel@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> Note that some kind of read barrier or compiler barrier should be needed
> regardless, or we are just not sync'ing with anything at all (we may
> have loaded the value ages ago and thus operate on a totally stale
> value). I prefer a full barrier to also ensure all previous stores are
> pushed out.
We already have a compiler barrier there in the form of cpu_relax.
Cheers,
--
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: boards in arch/ppc -> arch/powerpc for 85xx
From: Bruce Ashfield @ 2007-10-18 14:29 UTC (permalink / raw)
To: Kumar Gala; +Cc: David Woodhouse, Stefan Roese, linuxppc-dev list
In-Reply-To: <7DBC0977-0367-40F5-8A30-ACA02FD4E9FA@kernel.crashing.org>
On 10/15/07, Kumar Gala <galak@kernel.crashing.org> wrote:
> Guys,
>
> I was wondering if you cared about the following boards existing in
> arch/powerpc:
>
> * STX GP3
> * TQM 85xx
> * SBC 8560
>
> I'm told WR doesn't care about the SBC 8560, so I'll see if David does.
Sorry for the late reply, this just popped up on my radar this
morning when the 10th or 11th reply came in.
That doesn't reflect our intentions for that board, it is still active
and will continue to be that way for some time. Transition plans
are still in flux.
Bruce
>
> I'm willing to look into doing the port over, but would need some
> help testing.
>
> - k
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
--
"Thou shalt not follow the NULL pointer, for chaos and madness await
thee at its end"
^ permalink raw reply
* RE: [PATCH] Fix ethernet multicast for ucc_geth.
From: Li Yang-r58472 @ 2007-10-18 14:24 UTC (permalink / raw)
To: joakim.tjernlund, Netdev, linuxppc-dev
In-Reply-To: <1192611942.7848.19.camel@gentoo-jocke.transmode.se>
> -----Original Message-----
> From: Joakim Tjernlund [mailto:joakim.tjernlund@transmode.se]=20
> Sent: Wednesday, October 17, 2007 5:06 PM
> To: Netdev; Li Yang-r58472
> Subject: [PATCH] Fix ethernet multicast for ucc_geth.
>=20
> >From 5761a9e5924b34615c748fba2dcb977ed04c1243 Mon Sep 17=20
> 00:00:00 2001
> From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
> Date: Wed, 17 Oct 2007 11:01:44 +0200
> Subject: [PATCH] Fix ethernet multicast for ucc_geth.
> hw_add_addr_in_hash() already swaps byte order, don't do it=20
> in ucc_geth_set_multi() too.
>=20
>=20
> Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Li Yang <leoli@freescale.com>
^ permalink raw reply
* Re: [PATCH v2 1/4] Implement {read,update}_persistent_clock.
From: Sergei Shtylyov @ 2007-10-18 14:18 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linuxppc-dev, Thomas Gleixner, Paul Mackerras, Realtime Kernel
In-Reply-To: <47162B6F.40903@ru.mvista.com>
Hello, I wrote:
>>With these functions implemented we cooperate better with the generic
>>timekeeping code. This obsoletes the need for the timer sysdev as a bonus.
> Aha, I'm seeing it's not merged to mainline yet!
Contrarywise, it's been merged first -- looks like this all happened
because of me not commenting on the patches in time... :-(
Now one can only send incremental patches... sigh...
WBR, Sergei
^ permalink raw reply
* Re: [PATCH v3 0/4] FEC - fast ethernet controller for mpc52xx
From: Grant Likely @ 2007-10-18 14:15 UTC (permalink / raw)
To: Jeff Garzik; +Cc: linuxppc-dev, netdev, Domen Puncer
In-Reply-To: <4713BA1C.2050604@pobox.com>
On 10/15/07, Jeff Garzik <jgarzik@pobox.com> wrote:
> Domen Puncer wrote:
> > Hello!
> >
> > If there are no objections, I would like to get this merged
> > when bestcomm goes in (any time now?).
> >
> > It's split into four parts:
> > 1 - device tree
> > 2 - small bestcomm change
> > 3 - the actual driver
> > 4 - phy part of the driver
>
> patches #3 and #4 need to be combined together.
>
> Are the arch people OK with patches #1 and #2?
Jeff,
The bestcomm patches and patch 1 & 2 from this series are now in
Linus' tree. That clears the way for the FEC driver when Domen
reposts it. (In other words; there is nothing left in arch land
blocking this driver)
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH v5 9/9] add MPC837x MDS board default device tree
From: Kumar Gala @ 2007-10-18 14:04 UTC (permalink / raw)
To: Li Yang-r58472, Kim Phillips; +Cc: linuxppc-dev list, Paul Mackerras
In-Reply-To: <989B956029373F45A0B8AF0297081890019B5BCC@zch01exm26.fsl.freescale.net>
On Oct 18, 2007, at 8:33 AM, Li Yang-r58472 wrote:
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Thursday, October 18, 2007 9:17 PM
>> To: Li Yang-r58472
>> Cc: paulus@samba.org; linuxppc-dev@ozlabs.org
>> Subject: Re: [PATCH v5 9/9] add MPC837x MDS board default device tree
>>
>> is it me or are you just posting the patches you're updating?
>> (this is the only v5 patch I saw in the series)
>
> I'm only posting the patch updated, to prevent spamming the list. If
> you want, I can send the whole series to you.
I think posting the full patchset for v6 would be good since we've
gotten that far.
>> On Oct 18, 2007, at 5:16 AM, Li Yang wrote:
>>
>>> Signed-off-by: Li Yang <leoli@freescale.com>
>>> ---
>>> diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/
>>> boot/dts/mpc8377_mds.dts new file mode 100644 index 0000000..8530de6
>
>>> + memory {
>>> + device_type = "memory";
>>> + reg = <00000000 20000000>; // 512MB at 0
>>> + };
>>> +
>>> + soc837x@e0000000 {
>>
>> soc@e0000000
>
> I can update this now, but the device tree won't be usable by current
> u-boot.
Its my understanding Kim's going to deal with this in the public u-
boot tree.
>>> + spi@7000 {
>>> + compatible = "mpc83xx_spi";
>>> + reg = <7000 1000>;
>>> + interrupts = <10 8>;
>>> + interrupt-parent = < &ipic >;
>>
>> mode = "cpu";
>
> Oh ya, the spec has been changed. I also need to update
> mpc83xx_spi to
> fsl_spi.
>
> - Leo
^ permalink raw reply
* RE: [PATCH v3 9/9] add MPC837x MDS board default device tree
From: Li Yang-r58472 @ 2007-10-18 13:46 UTC (permalink / raw)
To: Kumar Gala, David Gibson; +Cc: linuxppc-dev, paulus
In-Reply-To: <09B82C85-E2DE-46AD-8ABC-B7A261BAFF6D@kernel.crashing.org>
=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
> Sent: Wednesday, October 17, 2007 9:59 PM
> To: David Gibson
> Cc: Li Yang-r58472; paulus@samba.org; linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH v3 9/9] add MPC837x MDS board default device tree
>=20
>=20
> On Oct 14, 2007, at 7:37 PM, David Gibson wrote:
>=20
> > On Fri, Oct 12, 2007 at 09:28:48PM +0800, Li Yang wrote:
> >> Signed-off-by: Li Yang <leoli@freescale.com>
> >> ---
> >> arch/powerpc/boot/dts/mpc8377_mds.dts | 288 +++++++++++++++++++++
> >> +++++++++
> >> arch/powerpc/boot/dts/mpc8378_mds.dts | 268 +++++++++++++++++++++
> >> +++++++
> >> arch/powerpc/boot/dts/mpc8379_mds.dts | 308 +++++++++++++++++++++
> >> ++++++++++++
> >> 3 files changed, 864 insertions(+), 0 deletions(-) create mode=20
> >> 100644 arch/powerpc/boot/dts/mpc8377_mds.dts
> >> create mode 100644 arch/powerpc/boot/dts/mpc8378_mds.dts
> >> create mode 100644 arch/powerpc/boot/dts/mpc8379_mds.dts
> >>
> >> diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts
> >> b/arch/powerpc/boot/dts/mpc8377_mds.dts
> > [snip]
> >> + soc837x@e0000000 {
> >> + #address-cells =3D <1>;
> >> + #size-cells =3D <1>;
> >> + device_type =3D "soc";
> >> + ranges =3D <0 e0000000 00100000>;
> >> + reg =3D <e0000000 00000200>;
> >> + bus-frequency =3D <0>;
> >> +
> >> + wdt@200 {
> >> + device_type =3D "watchdog";
> >
> > Drop this device_type.
> >
> >> + compatible =3D "mpc83xx_wdt";
> >> + reg =3D <200 100>;
> >> + };
> >> +
> >> + i2c@3000 {
> >> + device_type =3D "i2c";
> >
> > And this one.
>=20
> I've asked Leo to leave this one as all other fsl boards do=20
> this and the code depends on it. There was some discussion=20
> about this but I wasn't sure if it was closed or not.
I'm afraid not only i2c but also watchdog and spi need device_type now.
Shall we proceed removing the type check?
- Leo
^ permalink raw reply
* RE: [PATCH v5 9/9] add MPC837x MDS board default device tree
From: Li Yang-r58472 @ 2007-10-18 13:33 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, paulus
In-Reply-To: <9982D235-54B3-4733-8F67-4F75C7D1AFC3@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
> Sent: Thursday, October 18, 2007 9:17 PM
> To: Li Yang-r58472
> Cc: paulus@samba.org; linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH v5 9/9] add MPC837x MDS board default device tree
>=20
> is it me or are you just posting the patches you're updating?=20
> (this is the only v5 patch I saw in the series)
I'm only posting the patch updated, to prevent spamming the list. If
you want, I can send the whole series to you.
>=20
> On Oct 18, 2007, at 5:16 AM, Li Yang wrote:
>=20
> > Signed-off-by: Li Yang <leoli@freescale.com>
> > ---
> > diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/=20
> > boot/dts/mpc8377_mds.dts new file mode 100644 index 0000000..8530de6
> > + memory {
> > + device_type =3D "memory";
> > + reg =3D <00000000 20000000>; // 512MB at 0
> > + };
> > +
> > + soc837x@e0000000 {
>=20
> soc@e0000000
I can update this now, but the device tree won't be usable by current
u-boot.
> > + spi@7000 {
> > + compatible =3D "mpc83xx_spi";
> > + reg =3D <7000 1000>;
> > + interrupts =3D <10 8>;
> > + interrupt-parent =3D < &ipic >;
>=20
> mode =3D "cpu";
Oh ya, the spec has been changed. I also need to update mpc83xx_spi to
fsl_spi.
- Leo
^ permalink raw reply
* Re: [PATCH] ppc44x: support for 256K PAGE_SIZE
From: Yuri Tikhonov @ 2007-10-18 13:30 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20071018082514.2ce1f43b@weaponx.rchland.ibm.com>
On Thursday 18 October 2007 17:25, Josh Boyer wrote:
> > Understood. The situation here is that the boards, which required these
> > modifications, have no support in the arch/powerpc branch. So this is
> > why we made this in arch/ppc.
>
> Bit of a dilemma then. What board exactly?
These are the Katmai and Yucca PPC440SPe-based boards (from AMCC).
> > > Also, I'd rather see something along the lines of hugetlbfs support instead.
> >
> > Here I agree with Benjamin. Furthermore, IIRC the hugetlb file-system is
> > supported for PPC64 architectures only. Here we have PPC32.
>
> Well that needs fixing anyway, but ok. Also, is the modified binutils
> only required for userspace to take advantage here? Seems so, but I'd
> just like to be sure.
You are right, for userspace only.
>
> josh
>
--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com
^ permalink raw reply
* Re: [PATCH] ppc44x: support for 256K PAGE_SIZE
From: Yuri Tikhonov @ 2007-10-18 13:25 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1192709532.12879.61.camel@pasglop>
On Thursday 18 October 2007 16:12, Benjamin Herrenschmidt wrote:
> > I always reserve the right to change my mind. If something makes sense
> > and the code is decent enough then it might very well be acceptable.
> > Requiring a modified binutils makes me a bit nervous though.
>
> From a kernel point of view, I totally don't care about the modified
> binutils to build userspace as long as it's not required to build the
> kernel and that option is not enabled by default (and explicitely
> documented as having that requirement).
>
> If it is necessary for building the kernel, then I'm a bit cooler about
> the whole thing indeed, the max page size needs to be added at least as
> a command line or linker script param so a different build of binutils
> isn't needed.
No, 256K-page-sized kernel is being built using the standard binutils. Modifications
to them are necessary for user-space applications only. And the libraries as well.
--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com
^ permalink raw reply
* Re: [PATCH] ppc44x: support for 256K PAGE_SIZE
From: Josh Boyer @ 2007-10-18 13:25 UTC (permalink / raw)
To: Yuri Tikhonov; +Cc: linuxppc-dev
In-Reply-To: <200710181718.00965.yur@emcraft.com>
On Thu, 18 Oct 2007 17:18:00 +0400
Yuri Tikhonov <yur@emcraft.com> wrote:
>
> On Thursday 18 October 2007 14:44, you wrote:
> > Sorry, this is against arch/ppc which is bug fix only. New features
> > should be done against arch/powerpc.
>
> Understood. The situation here is that the boards, which required these
> modifications, have no support in the arch/powerpc branch. So this is
> why we made this in arch/ppc.
Bit of a dilemma then. What board exactly?
> > Also, I'd rather see something along the lines of hugetlbfs support instead.
>
> Here I agree with Benjamin. Furthermore, IIRC the hugetlb file-system is
> supported for PPC64 architectures only. Here we have PPC32.
Well that needs fixing anyway, but ok. Also, is the modified binutils
only required for userspace to take advantage here? Seems so, but I'd
just like to be sure.
josh
^ permalink raw reply
* Re: [PATCH] ppc44x: support for 256K PAGE_SIZE
From: Yuri Tikhonov @ 2007-10-18 13:20 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1192708038.12879.54.camel@pasglop>
On Thursday 18 October 2007 15:47, Benjamin Herrenschmidt wrote:
>
> > Signed-off-by: Pavel Kolesnikov <concord@emcraft.com>
> > Acked-by: Yuri Tikhonov <yur@emcraft.com>
>
> Small nit...
>
> You are posting the patch, thus you should be signing off, not ack'ing.
>
> Ack'ing means you agree with the patch but you aren't in the handling
> chain for it. In this case, it seems like the author is Pavel and you
> are forwarding it, in wich case, you -are- in the handling chain and
> should should sign it off.
>
> Best would be for Pavel (if he is indeed the author) to submit it
> himself though.
Thanks for the explanations. Will keep this in mind in the future.
>
> Ben.
--
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com
^ permalink raw reply
* Re: 2.6.23-mm1 - powerpc - Build fails at arch/powerpc/boot/inflate.o
From: Kamalesh Babulal @ 2007-10-18 13:20 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Andrew Morton, linux-kernel, imsudhirkumar
In-Reply-To: <18199.20538.594159.877930@cargo.ozlabs.ibm.com>
Paul Mackerras wrote:
> Kamalesh Babulal writes:
>
>> The kernel build fails on the power box
>>
>> INSTALL vdso64.so
>>
>> INSTALL vdso32.so
>>
>> BOOTCC arch/powerpc/boot/inflate.o
>>
>> arch/powerpc/boot/inflate.c:920:19: error: errno.h: No such file or directory
>
> This problem is fixed by d4faaecbcc6d9ea4f7c05f6de6af98e2336a4afb in
> Linus' tree.
>
> Paul.
> -
Hi Paul,
Thanks, we tried it out over the 2.6.23-mm1 and the patch fixes the build failure.
--
Thanks & Regards,
Kamalesh Babulal,
^ permalink raw reply
* Re: [PATCH v5 9/9] add MPC837x MDS board default device tree
From: Kumar Gala @ 2007-10-18 13:17 UTC (permalink / raw)
To: Li Yang; +Cc: linuxppc-dev, paulus
In-Reply-To: <1192702580-6353-1-git-send-email-leoli@freescale.com>
is it me or are you just posting the patches you're updating? (this
is the only v5 patch I saw in the series)
On Oct 18, 2007, at 5:16 AM, Li Yang wrote:
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/
> boot/dts/mpc8377_mds.dts
> new file mode 100644
> index 0000000..8530de6
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
> @@ -0,0 +1,282 @@
> +/*
> + * MPC8377E MDS Device Tree Source
> + *
> + * Copyright 2007 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +/ {
> + model = "fsl,mpc8377emds";
> + compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,837x@0 {
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-line-size = <20>;
> + i-cache-line-size = <20>;
> + d-cache-size = <8000>; // L1, 32K
> + i-cache-size = <8000>; // L1, 32K
> + timebase-frequency = <0>;
> + bus-frequency = <0>;
> + clock-frequency = <0>;
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <00000000 20000000>; // 512MB at 0
> + };
> +
> + soc837x@e0000000 {
soc@e0000000
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + ranges = <0 e0000000 00100000>;
> + reg = <e0000000 00000200>;
> + bus-frequency = <0>;
> +
> + wdt@200 {
> + compatible = "mpc83xx_wdt";
> + reg = <200 100>;
> + };
> +
> + i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
> + device_type = "i2c";
> + compatible = "fsl-i2c";
> + reg = <3000 100>;
> + interrupts = <e 8>;
> + interrupt-parent = < &ipic >;
> + dfsrr;
> + };
> +
> + i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
> + device_type = "i2c";
> + compatible = "fsl-i2c";
> + reg = <3100 100>;
> + interrupts = <f 8>;
> + interrupt-parent = < &ipic >;
> + dfsrr;
> + };
> +
> + spi@7000 {
> + compatible = "mpc83xx_spi";
> + reg = <7000 1000>;
> + interrupts = <10 8>;
> + interrupt-parent = < &ipic >;
mode = "cpu";
> + mode = <0>;
> + };
> +
- k
^ permalink raw reply
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