* Re: [PATCH] powerpc: Add xmon function to dump 44x TLB
From: Benjamin Herrenschmidt @ 2007-11-16 21:03 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <4ccc68f867a65d70f5d1e3ee946de4d1@kernel.crashing.org>
On Fri, 2007-11-16 at 16:54 +0100, Segher Boessenkool wrote:
> > +#ifdef CONFIG_44x
> > +static void dump_tlb_44x(void);
> > +#endif
>
> No need to #ifdef this...
>
> > +#ifdef CONFIG_44x
> > +static void dump_tlb_44x(void)
> > +{
>
> ...or this.
I don't want to require binutils to understand the 44x TLB ops
Ben.
^ permalink raw reply
* Re: 85xx software reset problems from paulus.git
From: robert lazarski @ 2007-11-16 20:44 UTC (permalink / raw)
Cc: linuxppc-embedded
In-Reply-To: <473DB6DF.9010804@anagramm.de>
On Nov 16, 2007 10:27 AM, Clemens Koller <clemens.koller@anagramm.de> wrote:
> Hello, Robert!
>
> robert lazarski schrieb:
> > Hi all, on my custom 85xx board I can't do a soft reset. I'm using
> > u-boot 1.3rc3 that has the latest cpu/mpc85xx/cpu.c patch to fix some
> > type of reset problem. When I press the software reset button on my
> > board after my nfs kernel panic, I get this:
>
> Please define "software reset button" in your case. :-)
> I consider a "button" clearly as hardware.
>
I mean a hardware button that calls SRESET , ie, Soft reset machine check.
<snip>
>
> The SRESET# (pin AF20) is the soft reset input, causes
> an mcp assertion to the core.... (RTFM)
>
That's what we are doing. The 85xx docs say "Soft reset. Causes a
machine check interrupt to the e500 core. Note that if the e500 core
is not configured to process machine check interrupts, the assertion
of SRESET causes a core checkstop. SRESET need not be asserted during
a hard reset."
Is the 85xx kernel "not configured to process machine check
interrupts" ? Do I need to do that myself in my boards restart
function via the special registers? Is there code already for this?
Robert
^ permalink raw reply
* Re: [PATCH] [POWERPC] Add SPRN for Embedded registers specified in PowerISA 2.04
From: Kumar Gala @ 2007-11-16 20:09 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev
In-Reply-To: <20071116200510.GA18481@lixom.net>
On Nov 16, 2007, at 2:05 PM, Olof Johansson wrote:
> Hi,
>
>
> On Fri, Nov 16, 2007 at 01:59:03PM -0600, Kumar Gala wrote:
>> +#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
>> +#define SPRN_SPRG9 0x25D /* Special Purpose Register General 8 */
>
> Cut and paste error in comment :)
thanks, git-commit --amend fixed ;)
- k
^ permalink raw reply
* Re: [PATCH] [POWERPC] Add SPRN for Embedded registers specified in PowerISA 2.04
From: Olof Johansson @ 2007-11-16 20:05 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0711161358280.24588@blarg.am.freescale.net>
Hi,
On Fri, Nov 16, 2007 at 01:59:03PM -0600, Kumar Gala wrote:
> +#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
> +#define SPRN_SPRG9 0x25D /* Special Purpose Register General 8 */
Cut and paste error in comment :)
-Olof
^ permalink raw reply
* [PATCH] [POWERPC] Add SPRN for Embedded registers specified in PowerISA 2.04
From: Kumar Gala @ 2007-11-16 19:59 UTC (permalink / raw)
To: linuxppc-dev
* Added SPRN for new architectural features added for embedded:
- Alternate Time Base (ATB, ATBL, ATBU)
- Doorbell Interrupts (IVOR36, IVOR37)
- SPRG8/9
- External Proxy (EPR)
- External PID load/store (EPLC, EPSC)
* Added BUCSR for Freescale Embedded Processors
* Moved around MAS7 so its in numeric order
---
as normal, this is my git tree for 2.6.25
include/asm-powerpc/reg_booke.h | 13 ++++++++++++-
1 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 8fdc2b4..d596439 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -123,16 +123,23 @@
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
+#define SPRN_ATB 0x20E /* Alternate Time Base */
+#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
+#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
+#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
+#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
#define SPRN_MCSR 0x23C /* Machine Check Status Register */
#define SPRN_MCAR 0x23D /* Machine Check Address Register */
#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
+#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
+#define SPRN_SPRG9 0x25D /* Special Purpose Register General 8 */
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
@@ -140,15 +147,18 @@
#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
-#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27A /* Process ID Register 2 */
#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
+#define SPRN_EPR 0x2BE /* External Proxy Register */
#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
+#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
+#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
+#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
#define SPRN_SLER 0x3BB /* Little-endian real mode */
@@ -159,6 +169,7 @@
#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
+#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
#define SPRN_SVR 0x3FF /* System Version Register */
--
1.5.3.4
^ permalink raw reply related
* Re: [PATCH] [POWERPC] 4xx: Use virtual PVR value to init FPU on arch/ppc 440EP
From: Josh Boyer @ 2007-11-16 19:23 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <96AAE1CB-3F7F-4231-AD52-01F358E01594@kernel.crashing.org>
On Fri, 16 Nov 2007 13:20:09 -0600
Kumar Gala <galak@kernel.crashing.org> wrote:
>
> On Nov 16, 2007, at 11:29 AM, Josh Boyer wrote:
>
> > This fixes arch/ppc 440EP platforms to setup the FPU correctly. A
> > virtual
> > PVR is used, as 440GR platforms share an identical hardware PVR
> > value and do
> > not have an FPU.
> >
> > Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
> > Index: linux-2.6/arch/ppc/kernel/setup.c
> > ===================================================================
> > --- linux-2.6.orig/arch/ppc/kernel/setup.c
> > +++ linux-2.6/arch/ppc/kernel/setup.c
> > @@ -312,7 +312,14 @@ early_init(int r3, int r4, int r5)
> > * Identify the CPU type and fix up code sections
> > * that depend on which cpu we have.
> > */
> > +#if defined(CONFIG_440EP) && defined(CONFIG_PPC_FPU)
> > + /* We pass the virtual PVR here for 440EP as 440EP and 440GR have
> > + * identical PVRs and there is no reliable way to check for the FPU
> > + */
> > + spec = identify_cpu(offset, (mfspr(SPRN_PVR) | 0x8));
> > +#else
> > spec = identify_cpu(offset, mfspr(SPRN_PVR));
> > +#endif
> > do_feature_fixups(spec->cpu_features,
> > PTRRELOC(&__start___ftr_fixup),
> > PTRRELOC(&__stop___ftr_fixup));
>
> Are we really adding support for new processors to arch/ppc?
No. This is to continue to support 440EP FPU in arch/ppc. Commit
d1dfc35d3a62 switched the cputable around for EP(x)/GR(x) and arch/ppc wasn't fixed up. So without the above patch, 440EP gets detected as 440GR and the FPU isn't initialized properly.
josh
^ permalink raw reply
* Re: [PATCH] [POWERPC] 4xx: Use virtual PVR value to init FPU on arch/ppc 440EP
From: Kumar Gala @ 2007-11-16 19:20 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20071116112956.0f1ca5b1@weaponx>
On Nov 16, 2007, at 11:29 AM, Josh Boyer wrote:
> This fixes arch/ppc 440EP platforms to setup the FPU correctly. A
> virtual
> PVR is used, as 440GR platforms share an identical hardware PVR
> value and do
> not have an FPU.
>
> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
> Index: linux-2.6/arch/ppc/kernel/setup.c
> ===================================================================
> --- linux-2.6.orig/arch/ppc/kernel/setup.c
> +++ linux-2.6/arch/ppc/kernel/setup.c
> @@ -312,7 +312,14 @@ early_init(int r3, int r4, int r5)
> * Identify the CPU type and fix up code sections
> * that depend on which cpu we have.
> */
> +#if defined(CONFIG_440EP) && defined(CONFIG_PPC_FPU)
> + /* We pass the virtual PVR here for 440EP as 440EP and 440GR have
> + * identical PVRs and there is no reliable way to check for the FPU
> + */
> + spec = identify_cpu(offset, (mfspr(SPRN_PVR) | 0x8));
> +#else
> spec = identify_cpu(offset, mfspr(SPRN_PVR));
> +#endif
> do_feature_fixups(spec->cpu_features,
> PTRRELOC(&__start___ftr_fixup),
> PTRRELOC(&__stop___ftr_fixup));
Are we really adding support for new processors to arch/ppc?
- k
^ permalink raw reply
* Re: Latest paulus.git PCI broken on mpc8540?
From: Kumar Gala @ 2007-11-16 19:18 UTC (permalink / raw)
To: benh; +Cc: linuxppc-embedded
In-Reply-To: <1195191333.28865.140.camel@pasglop>
On Nov 15, 2007, at 11:35 PM, Benjamin Herrenschmidt wrote:
>
> On Thu, 2007-11-15 at 22:37 -0600, Kumar Gala wrote:
>>> PCI: Probing PCI hardware
>>> PCI: Cannot allocate resource region 0 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 1 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 2 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 3 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 4 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 0 of device 0000:00:14.0
>>> PCI: Cannot allocate resource region 2 of device 0000:00:14.0
>>
>> this isn't really an error. Its more of a warning, the kernel will
>> try and allocate these later and I'm guessing based on what you are
>> seeing it succeeded.
>>
>> Benh, can we possibly change these messages in pci_32.c?
>
> Heh, well, I've been working on 44x PCI lately and got annoyed by the
> exact same messages, though I'm still pondering what would be a better
> replacement.
Well, for one the generic pci code will complain if its not able to
allocate the resource which is the true failure.
I'm thinking maybe we just make these pr_debug() instead of standard
printk?
- k
^ permalink raw reply
* Re: [PATCH] remove dead MAC_ADBKEYCODES
From: Geert Uytterhoeven @ 2007-11-16 15:09 UTC (permalink / raw)
To: Dmitry Torokhov
Cc: Stanislav Brabec, linux-input, Linux/m68k, Linux/PPC Development
In-Reply-To: <d120d5000711160525p225f4b4o30eab6d01b289cda@mail.gmail.com>
On Fri, 16 Nov 2007, Dmitry Torokhov wrote:
> On Nov 16, 2007 4:44 AM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > Wrong mailing list ;-)
> >
> > On Thu, 15 Nov 2007, Stanislav Brabec wrote:
> > > It seems, that current kernel source code contains no traces of
> > > MAC_ADBKEYCODES and no reference to keyboard_sends_linux_keycodes any
> > > more.
> > >
> > > Attached patch removes them from configuration files.
> > >
> > > Signed-off-by: Stanislav Brabec <sbrabec@suse.cz>
> >
> > Acked-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
> >
>
> Geert, are you going to push it through your tree?
Yes, I'll add it to my queue for 2.6.25.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: Kexec on powerpc
From: Dale Farnsworth @ 2007-11-16 18:48 UTC (permalink / raw)
To: marco.stornelli, Linuxppc-embedded
In-Reply-To: <10602.129.192.97.5.1195132467.squirrel@nausicaa2.coritel.it>
On Thu, Nov 15, 2007 at 01:14:27PM +0000, marco.stornelli@coritel.it wrote:
> I'm using the latest kernel and I need the kexec support for 85xx
> processor. When I use the menuconfig with ARCH=ppc and the 85xx and
> e500 support, I have the kexec support, but when I use ARCH=powerpc I
> haven't it, but I'm selecting the same processor!! Is it a bug in
> kconfig? Somebody can explain to me why?
I don't think kexec works for ppc-32 arch/powerpc at the present.
We have been working on kexec/kdump support for 32-bit arch/powerpc.
It requires changes both to the kernel and to the kexec-tools package.
I plan to post a first round of patches to linuxppc-dev early next week.
-Dale Farnsworth
^ permalink raw reply
* Configuration of i2c on 8248 (cpm2) help
From: Alan Bennett @ 2007-11-16 18:44 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 3108 bytes --]
I'm working to adapt some work by Jochen Friedrich to support CPM2 i2c
devices. It appears I have the bus loaded and think I am configuring
it properly, but my results tell me different. I see no messages when
I attach a i2c monitor after u-boot loads.
Can anyone spot what is going wrong based on the following information
and the resulting output? Does this look proper for a successful
configuration of the cpm2 i2c bus?
i2c-cpm: iip e0008afc, dp_addr 0x240
i2c-cpm: iic_tbase 576, iic_rbase 608
Any insight would be greatly appreciated.
-Alan
My Device tree entry:
i2c@11860 {
compatible = "fsl,mpc8248-i2c",
"fsl,cpm2-i2c",
"fsl,cpm-i2c";
reg = <11860 20 8afc 30>;
interrupts = <1 8>;
interrupt-parent = <&PIC>;
fsl,cpm-command = <29600000>;
};
... and then later:
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <80 1f80 9800 800>;
};
};
dump of 0xe0008afc (my immr_base=0xe0000000) at boot
e0008afc : 02600240 10100201 00000000 00000000
e0008b0c : 02600000 00000000 00000000 00000000
e0008b1c : 02400000 00000000 78c7ebaf bdefeab1
Probe debug results:
i2c-cpm: cpm_iic_init()
i2c-cpm: iip e0008afc, dp_addr 0x240
i2c-cpm: iic_tbase 576, iic_rbase 608
Log after modprobe:
modprobe i2c-dev
Jan 1 00:08:02 192 kernel: i2c /dev entries driver
Jan 1 00:08:02 192 kernel: i2c-core: driver [dev_driver] registered
Jan 1 00:08:02 192 kernel: i2c-dev: adapter [i2c-cpm] registered as minor 0
Log entries after trying an i2cset: (NOTE: sometimes it hangs doing this)
i2cset 0 0x41 0x1 0xff b
cpm_xfer:478
cpm_parse_message:329
kernel: i2c-adapter i2c-0: ioctl, cmd=0x720, arg=0xbfecaa0c
kernel: i2c-adapter i2c-0: master_xfer[0] W, addr=0x41, len2
kernel: cpm_xfer:478
kernel: i2c-adapter i2c-0: i2c-algo-cpm.o: R: 0 T: 0
kernel: cpm_parse_message:329
kernel: i2c-adapter i2c-0: cpm_iic_write(abyte=0x82)
kernel: i2c-adapter i2c-0: tx sc 0 bc00
kernel: i2c-adapter i2c-0: test ready.
kernel: i2c-adapter i2c-0: not ready.
cpm_xfer:478
cpm_parse_message:329
cpm_parse_message:329
kernel: i2c-adapter i2c-0: force_close()
kernel: i2c-adapter i2c-0: IIC read: timeout!
kernel: i2c-adapter i2c-0: ioctl, cmd=0x720, arg=0xbfecaa0c
kernel: i2c-adapter i2c-0: master_xfer[0] W, addr=0x41, len1
kernel: i2c-adapter i2c-0: master_xfer[1] R, addr=0x41, len1
kernel: cpm_xfer:478
kernel: i2c-adapter i2c-0: i2c-algo-cpm.o: R: 0 T: 0
kernel: cpm_parse_message:329
kernel: i2c-adapter i2c-0: cpm_iic_write(abyte=0x82)
kernel: i2c-adapter i2c-0: tx sc 0 9400
kernel: i2c-adapter i2c-0: i2c-algo-cpm.o: R: 0 T: 1
kernel: cpm_parse_message:329
kernel: i2c-adapter i2c-0: cpm_iic_read(abyte=0x83)
kernel: i2c-adapter i2c-0: test ready.
kernel: i2c-adapter i2c-0: not ready.
kernel: i2c-adapter i2c-0: force_close()
kernel: i2c-adapter i2c-0: IIC read: timeout!
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: i2c-cpm.c --]
[-- Type: text/x-csrc; name=i2c-cpm.c, Size: 17704 bytes --]
/*
* Freescale CPM1/CPM2 I2C interface.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
*
* moved into proper i2c interface;
* Brad Parker (brad@heeltoe.com)
*
* (C) 2007 Montavista Software, Inc.
* Vitaly Bordug <vitb@kernel.crashing.org>
*
* RPX lite specific parts of the i2c interface
* Update: There actually isn't anything RPXLite-specific about this module.
* This should work for most any CPM board. The console messages have been
* changed to eliminate RPXLite references.
*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* moved into proper i2c interface; separated out platform specific
* parts into i2c-8xx.c
* Brad Parker (brad@heeltoe.com)
*
* Parts from dbox2_i2c.c (cvs.tuxbox.org)
* (C) 2000-2001 Tmbinc, Gillem (htoa@gmx.net)
*
* (C) 2007 Montavista Software, Inc.
* Vitaly Bordug <vitb@kernel.crashing.org>
*
* Converted to of_platform_device. Renamed to i2c-cpm.c.
* (C) 2007 Jochen Friedrich <jochen@scram.de>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/stddef.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/time.h>
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#ifdef CONFIG_CPM2
#include <asm/cpm2.h>
#else
#include <asm/commproc.h>
#endif
/* Try to define this if you have an older CPU (earlier than rev D4) */
/* However, better use a GPIO based bitbang driver in this case :/ */
#undef I2C_CHIP_ERRATA
#define CPM_MAX_READ 513
#define CPM_MAXBD 4
struct cpm_i2c {
char *base;
struct of_device *ofdev;
struct i2c_adapter adap;
uint dp_addr;
int reloc;
int irq;
int cp_command;
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c;
#else
i2c8xx_t __iomem *i2c;
#endif
iic_t __iomem *iip;
wait_queue_head_t iic_wait;
struct mutex iic_mutex; /* Protects I2C CPM */
u_char *txbuf[CPM_MAXBD];
u_char *rxbuf[CPM_MAXBD];
u32 txdma[CPM_MAXBD];
u32 rxdma[CPM_MAXBD];
};
static irqreturn_t cpm_iic_interrupt(int irq, void *dev_id)
{
struct i2c_adapter *adap;
struct cpm_i2c *cpm;
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c;
#else
i2c8xx_t __iomem *i2c;
#endif
int i;
printk ("%s:%d\n", __FUNCTION__,__LINE__);
adap = (struct i2c_adapter *) dev_id;
cpm = i2c_get_adapdata(adap);
i2c = cpm->i2c;
/* Clear interrupt.
*/
i = in_8(&i2c->i2c_i2cer);
out_8(&i2c->i2c_i2cer, i);
dev_dbg(&adap->dev, "Interrupt: %x\n", i);
/* Get 'me going again.
*/
wake_up_interruptible(&cpm->iic_wait);
return i ? IRQ_HANDLED : IRQ_NONE;
}
static void cpm_reset_iic_params(struct cpm_i2c *cpm)
{
iic_t __iomem *iip = cpm->iip;
/* Set up the IIC parameters in the parameter ram.
*/
out_be16(&iip->iic_tbase, cpm->dp_addr);
out_be16(&iip->iic_rbase, cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
#ifdef CONFIG_CPM2
out_8(&iip->iic_tfcr, CPMFCR_EB);
out_8(&iip->iic_rfcr, CPMFCR_EB);
#else
out_8(&iip->iic_tfcr, SMC_EB);
out_8(&iip->iic_rfcr, SMC_EB);
#endif
out_be16(&iip->iic_mrblr, CPM_MAX_READ);
out_be32(&iip->iic_rstate, 0);
out_be32(&iip->iic_rdp, 0);
out_be16(&iip->iic_rbptr, in_be16(&iip->iic_rbase));
out_be16(&iip->iic_rbc, 0);
out_be32(&iip->iic_rxtmp, 0);
out_be32(&iip->iic_tstate, 0);
out_be32(&iip->iic_tdp, 0);
out_be16(&iip->iic_tbptr, in_be16(&iip->iic_tbase));
out_be16(&iip->iic_tbc, 0);
out_be32(&iip->iic_txtmp, 0);
}
static int cpm_iic_init(struct i2c_adapter *adap)
{
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
iic_t __iomem *iip = cpm->iip;
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c = cpm->i2c;
#else
i2c8xx_t __iomem *i2c = cpm->i2c;
#endif
unsigned char brg;
int ret, i, res;
#ifdef CONFIG_CPM2
u32 v;
#else
u16 v;
#endif
printk("i2c-cpm: cpm_iic_init()\n");
ret = 0;
init_waitqueue_head(&cpm->iic_wait);
mutex_init(&cpm->iic_mutex);
/* Initialize Tx/Rx parameters.
*/
cpm_reset_iic_params(cpm);
printk("i2c-cpm: iip %p, dp_addr 0x%x\n", cpm->iip, cpm->dp_addr);
printk("i2c-cpm: iic_tbase %d, iic_rbase %d\n",
in_be16(&iip->iic_tbase), in_be16(&iip->iic_rbase));
v = cpm->cp_command | (CPM_CR_INIT_TRX << 8) | CPM_CR_FLG;
#ifdef CONFIG_CPM2
out_be32(&cpmp->cp_cpcr, v);
res = wait_event_timeout(cpm->iic_wait,
!(in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG), HZ * 10);
#else
out_be16(&cpmp->cp_cpcr, v);
res = wait_event_timeout(cpm->iic_wait,
!(in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG), HZ * 10);
#endif
if (!res)
return -EIO;
/* Select an invalid address. Just make sure we don't use loopback mode
*/
out_8(&i2c->i2c_i2add, 0xfe);
/* Make clock run at 60 kHz.
*/
brg = get_brgfreq() / (32 * 2 * 60000) - 3;
out_8(&i2c->i2c_i2brg, brg);
out_8(&i2c->i2c_i2mod, 0x00);
out_8(&i2c->i2c_i2com, 0x01); /* Master mode */
/* Disable interrupts.
*/
out_8(&i2c->i2c_i2cmr, 0);
out_8(&i2c->i2c_i2cer, 0xff);
/* Allocate TX and RX buffers */
for (i = 0; i < CPM_MAXBD; i++) {
cpm->rxbuf[i] = dma_alloc_coherent(
NULL, CPM_MAX_READ + 1, &cpm->rxdma[i], GFP_KERNEL);
if (!cpm->rxbuf[i]) {
ret = -ENOMEM;
goto out;
}
cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(
NULL, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
if (!cpm->txbuf[i]) {
ret = -ENOMEM;
goto out;
}
}
/* Install interrupt handler.
*/
ret = request_irq(cpm->irq, cpm_iic_interrupt, 0, "cpm_i2c", adap);
if (ret)
goto out;
return 0;
out:
for (i = 0; i < CPM_MAXBD; i++) {
if (cpm->rxbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1,
cpm->rxbuf[i], cpm->rxdma[i]);
if (cpm->txbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1,
cpm->txbuf[i], cpm->txdma[i]);
}
return ret;
}
static int cpm_iic_shutdown(struct i2c_adapter *adap)
{
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
int i;
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c = cpm->i2c;
#else
i2c8xx_t __iomem *i2c = cpm->i2c;
#endif
/* Shut down IIC.
*/
out_8(&i2c->i2c_i2mod, in_8(&i2c->i2c_i2mod) | ~1);
out_8(&i2c->i2c_i2cmr, 0);
out_8(&i2c->i2c_i2cer, 0xff);
for (i = 0; i < CPM_MAXBD; i++) {
if (cpm->rxbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1,
cpm->rxbuf[i], cpm->rxdma[i]);
if (cpm->txbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1,
cpm->txbuf[i], cpm->txdma[i]);
}
free_irq(cpm->irq, adap);
return 0;
}
#define BD_SC_NAK (0x0004) /* NAK - did not respond */
#define BD_SC_OV (0x0002) /* OV - receive overrun */
#define CPM_CR_CLOSE_RXBD (0x0007)
static void force_close(struct i2c_adapter *adap)
{
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c = cpm->i2c;
u32 v;
#else
i2c8xx_t __iomem *i2c = cpm->i2c;
u16 v;
#endif
dev_dbg(&adap->dev, "force_close()\n");
v = cpm->cp_command | (CPM_CR_CLOSE_RXBD << 8) | CPM_CR_FLG;
#ifdef CONFIG_CPM2
out_be32(&cpmp->cp_cpcr, v);
wait_event_timeout(cpm->iic_wait,
!(in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG), HZ * 5);
#else
out_be16(&cpmp->cp_cpcr, v);
wait_event_timeout(cpm->iic_wait,
!(in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG), HZ * 5);
#endif
out_8(&i2c->i2c_i2cmr, 0x00); /* Disable all interrupts */
out_8(&i2c->i2c_i2cer, 0xff);
}
static void cpm_parse_message(struct i2c_adapter *adap, struct i2c_msg *pmsg,
int num, int tx, int rx)
{
cbd_t *tbdf, *rbdf;
u_char addr;
u_char *tb;
u_char *rb;
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
iic_t __iomem *iip = cpm->iip;
int i, dscan;
printk ("%s:%d\n", __FUNCTION__,__LINE__);
tbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_tbase));
rbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_rbase));
/* This chip can't do zero length writes. However, the i2c core uses
them to scan for devices. The best we can do is to convert them
into 1 byte reads */
dscan = ((pmsg->len == 0) && (num == 1));
addr = pmsg->addr << 1;
if ((pmsg->flags & I2C_M_RD) || dscan)
addr |= 1;
tb = cpm->txbuf[tx];
rb = cpm->rxbuf[rx];
/* Align read buffer */
rb = (u_char *) (((ulong) rb + 1) & ~1);
if ((pmsg->flags & I2C_M_RD) || dscan) {
/* To read, we need an empty buffer of the proper length.
* All that is used is the first byte for address, the remainder
* is just used for timing (and doesn't really have to exist).
*/
tb[0] = addr; /* Device address byte w/rw flag */
dev_dbg(&adap->dev, "cpm_iic_read(abyte=0x%x)\n", addr);
tbdf[tx].cbd_bufaddr = cpm->txdma[tx];
if (dscan)
tbdf[tx].cbd_datlen = 2;
else
tbdf[tx].cbd_datlen = pmsg->len + 1;
tbdf[tx].cbd_sc = 0;
if (!(pmsg->flags & I2C_M_NOSTART))
tbdf[tx].cbd_sc |= BD_IIC_START;
if (tx + 1 == num)
tbdf[tx].cbd_sc |= BD_SC_LAST | BD_SC_WRAP;
rbdf[rx].cbd_datlen = 0;
rbdf[rx].cbd_bufaddr = ((cpm->rxdma[rx] + 1) & ~1);
rbdf[rx].cbd_sc = BD_SC_EMPTY | BD_SC_INTRPT;
if (rx + 1 == CPM_MAXBD)
tbdf[rx].cbd_sc |= BD_SC_WRAP;
eieio();
tbdf[tx].cbd_sc |= BD_SC_READY;
} else {
tb[0] = addr; /* Device address byte w/rw flag */
for (i = 0; i < pmsg->len; i++)
tb[i+1] = pmsg->buf[i];
dev_dbg(&adap->dev, "cpm_iic_write(abyte=0x%x)\n", addr);
tbdf[tx].cbd_bufaddr = cpm->txdma[tx];
tbdf[tx].cbd_datlen = pmsg->len + 1;
tbdf[tx].cbd_sc = 0;
if (!(pmsg->flags & I2C_M_NOSTART))
tbdf[tx].cbd_sc |= BD_IIC_START;
if (tx + 1 == num)
tbdf[tx].cbd_sc |= BD_SC_LAST | BD_SC_WRAP;
eieio();
tbdf[tx].cbd_sc |= BD_SC_READY | BD_SC_INTRPT;
dev_dbg(&adap->dev, "tx sc %d %04x\n",
tx, tbdf[tx].cbd_sc);
}
}
static int cpm_check_message(struct i2c_adapter *adap, struct i2c_msg *pmsg,
int tx, int rx)
{
cbd_t *tbdf, *rbdf;
u_char *tb;
u_char *rb;
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
iic_t __iomem *iip = cpm->iip;
int i;
printk ("%s:%d\n", __FUNCTION__,__LINE__);
tbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_tbase));
rbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_rbase));
tb = cpm->txbuf[tx];
rb = cpm->rxbuf[rx];
/* Align read buffer */
rb = (u_char *) (((uint) rb + 1) & ~1);
if (pmsg->flags & I2C_M_RD) {
dev_dbg(&adap->dev, "rx sc %04x, rx sc %04x\n",
tbdf[tx].cbd_sc, rbdf[rx].cbd_sc);
if (tbdf[tx].cbd_sc & BD_SC_NAK) {
dev_dbg(&adap->dev, "IIC read; no ack\n");
if (pmsg->flags & I2C_M_IGNORE_NAK)
return 0;
else
return -EIO;
}
if (rbdf[rx].cbd_sc & BD_SC_EMPTY) {
dev_dbg(&adap->dev,
"IIC read; complete but rbuf empty\n");
return -EREMOTEIO;
}
if (rbdf[rx].cbd_sc & BD_SC_OV) {
dev_dbg(&adap->dev, "IIC read; Overrun\n");
return -EREMOTEIO;
}
for (i = 0; i < pmsg->len; i++)
pmsg->buf[i] = rb[i];
} else {
dev_dbg(&adap->dev, "tx sc %d %04x\n", tx, tbdf[tx].cbd_sc);
if (tbdf[tx].cbd_sc & BD_SC_NAK) {
dev_dbg(&adap->dev, "IIC write; no ack\n");
if (pmsg->flags & I2C_M_IGNORE_NAK)
return 0;
else
return -EIO;
}
}
return 0;
}
static int cpm_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c = cpm->i2c;
#else
i2c8xx_t __iomem *i2c = cpm->i2c;
#endif
iic_t __iomem *iip = cpm->iip;
struct i2c_msg *pmsg, *rmsg;
int ret, i;
int tptr;
int rptr;
cbd_t *tbdf, *rbdf;
printk ("%s:%d\n", __FUNCTION__,__LINE__);
if (num > CPM_MAXBD)
return -EINVAL;
/* Check if we have any oversized READ requests */
for (i = 0; i < num; i++) {
pmsg = &msgs[i];
if (pmsg->len >= CPM_MAX_READ)
return -EINVAL;
}
mutex_lock(&cpm->iic_mutex);
/* Reset to use first buffer */
out_be16(&iip->iic_rbptr, in_be16(&iip->iic_rbase));
out_be16(&iip->iic_tbptr, in_be16(&iip->iic_tbase));
tbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_tbase));
rbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_rbase));
tptr = 0;
rptr = 0;
while (tptr < num) {
pmsg = &msgs[tptr];
dev_dbg(&adap->dev, "i2c-algo-cpm.o: " "R: %d T: %d\n",
rptr, tptr);
cpm_parse_message(adap, pmsg, num, tptr, rptr);
if (pmsg->flags & I2C_M_RD)
rptr++;
tptr++;
}
/* Start transfer now */
/* Chip bug, set enable here */
out_8(&i2c->i2c_i2cmr, 0x13); /* Enable some interupts */
out_8(&i2c->i2c_i2cer, 0xff);
out_8(&i2c->i2c_i2mod, in_8(&i2c->i2c_i2mod) | 1); /* Enable */
/* Begin transmission */
out_8(&i2c->i2c_i2com, in_8(&i2c->i2c_i2com) | 0x80);
tptr = 0;
rptr = 0;
while (tptr < num) {
/* Check for outstanding messages */
dev_dbg(&adap->dev, "test ready.\n");
if (!(tbdf[tptr].cbd_sc & BD_SC_READY)) {
dev_dbg(&adap->dev, "ready.\n");
rmsg = &msgs[tptr];
ret = cpm_check_message(adap, rmsg, tptr, rptr);
tptr++;
if (rmsg->flags & I2C_M_RD)
rptr++;
if (ret) {
force_close(adap);
mutex_unlock(&cpm->iic_mutex);
return ret;
}
} else {
dev_dbg(&adap->dev, "not ready.\n");
ret = wait_event_interruptible_timeout(cpm->iic_wait,
!(tbdf[tptr].cbd_sc & BD_SC_READY), 1 * HZ);
if (ret == 0) {
force_close(adap);
dev_dbg(&adap->dev, "IIC read: timeout!\n");
mutex_unlock(&cpm->iic_mutex);
return -EREMOTEIO;
}
}
}
#ifdef I2C_CHIP_ERRATA
/* Chip errata, clear enable. This is not needed on rev D4 CPUs.
Disabling I2C too early may cause too short stop condition */
udelay(4);
out_8(&i2c->i2c_i2mod, in_8(&i2c->i2c_i2mod) | ~1);
#endif
mutex_unlock(&cpm->iic_mutex);
return (num);
}
static u32 cpm_func(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
/* -----exported algorithm data: ------------------------------------- */
static struct i2c_algorithm cpm_algo = {
.master_xfer = cpm_xfer,
.functionality = cpm_func,
};
/*
* registering functions to load algorithms at runtime
*/
int i2c_cpm_add_bus(struct i2c_adapter *adap)
{
int res;
printk("i2c-cpm: hw routines for %s registered.\n", adap->name);
/* register new adapter to i2c module... */
adap->algo = &cpm_algo;
res = cpm_iic_init(adap);
if (res)
return res;
return i2c_add_adapter(adap);
}
int i2c_cpm_del_bus(struct i2c_adapter *adap)
{
i2c_del_adapter(adap);
return cpm_iic_shutdown(adap);
}
static const struct i2c_adapter cpm_ops = {
.owner = THIS_MODULE,
.name = "i2c-cpm",
.id = I2C_HW_MPC8XX_EPON,
.class = I2C_CLASS_HWMON,
};
static int i2c_cpm_setup(struct cpm_i2c *i2c)
{
struct of_device *ofdev = i2c->ofdev;
const u32 *data;
int len;
/* Pointer to Communication Processor
*/
i2c->irq = of_irq_to_resource(ofdev->node, 0, NULL);
if (i2c->irq == NO_IRQ)
return -EINVAL;
i2c->iip = of_iomap(ofdev->node, 1);
if (i2c->iip == NULL)
return -EINVAL;
#ifndef CONFIG_CPM2
/* Check for and use a microcode relocation patch.
*/
if (of_device_is_compatible(ofdev->node, "fsl,i2c-cpm1"))
i2c->reloc = i2c->iip->iic_rpbase;
/* Maybe should use ioremap instead?
*/
if (i2c->reloc) {
iounmap(i2c->iip);
i2c->iip = cpm_muram_addr(i2c->iip->iic_rpbase);
}
#endif
i2c->i2c = of_iomap(ofdev->node, 0);
if (i2c->i2c == NULL)
return -EINVAL;
/* Allocate space for two transmit and two receive buffer
* descriptors in the DP ram.
*/
i2c->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 4, 8);
if (!i2c->dp_addr)
return -ENOMEM;
data = of_get_property(ofdev->node, "fsl,cpm-command", &len);
if (!data || len != 4)
return -EINVAL;
i2c->cp_command = *data;
return 0;
}
static void i2c_cpm_release(struct cpm_i2c *i2c)
{
if (i2c->dp_addr)
cpm_muram_free(i2c->dp_addr);
if (i2c->i2c)
iounmap(i2c->i2c);
if ((i2c->iip) && (!i2c->reloc))
iounmap(i2c->iip);
return;
}
static int i2c_cpm_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
int result;
struct cpm_i2c *i2c;
i2c = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
if (!i2c)
return -ENOMEM;
i2c->ofdev = ofdev;
result = i2c_cpm_setup(i2c);
if (result) {
printk(KERN_ERR "i2c-cpm: Unable to register resources\n");
goto out;
}
dev_set_drvdata(&ofdev->dev, i2c);
i2c->adap = cpm_ops;
i2c_set_adapdata(&i2c->adap, i2c);
i2c->adap.dev.parent = &ofdev->dev;
result = i2c_cpm_add_bus(&i2c->adap);
if (result < 0) {
printk(KERN_ERR "i2c-cpm: Unable to register with I2C\n");
goto out;
}
return 0;
out:
i2c_cpm_release(i2c);
kfree(i2c);
return result;
}
static int i2c_cpm_remove(struct of_device *ofdev)
{
struct cpm_i2c *i2c = dev_get_drvdata(&ofdev->dev);
i2c_cpm_del_bus(&i2c->adap);
dev_set_drvdata(&ofdev->dev, NULL);
i2c_cpm_release(i2c);
kfree(i2c);
return 0;
}
static struct of_device_id i2c_cpm_match[] = {
{
.compatible = "fsl,cpm-i2c",
},
{},
};
MODULE_DEVICE_TABLE(of, i2c_cpm_match);
static struct of_platform_driver i2c_cpm_driver = {
.name = "fsl-i2c-cpm",
.match_table = i2c_cpm_match,
.probe = i2c_cpm_probe,
.remove = i2c_cpm_remove,
};
static int __init i2c_cpm_init(void)
{
return of_register_platform_driver(&i2c_cpm_driver);
}
static void __exit i2c_cpm_exit(void)
{
of_unregister_platform_driver(&i2c_cpm_driver);
}
module_init(i2c_cpm_init);
module_exit(i2c_cpm_exit);
MODULE_AUTHOR("Dan Malek <dmalek@jlc.net>");
MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
MODULE_LICENSE("GPL");
^ permalink raw reply
* [PATCH] [POWERPC] 4xx: Use virtual PVR value to init FPU on arch/ppc 440EP
From: Josh Boyer @ 2007-11-16 17:29 UTC (permalink / raw)
To: linuxppc-dev
This fixes arch/ppc 440EP platforms to setup the FPU correctly. A virtual
PVR is used, as 440GR platforms share an identical hardware PVR value and do
not have an FPU.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Index: linux-2.6/arch/ppc/kernel/setup.c
===================================================================
--- linux-2.6.orig/arch/ppc/kernel/setup.c
+++ linux-2.6/arch/ppc/kernel/setup.c
@@ -312,7 +312,14 @@ early_init(int r3, int r4, int r5)
* Identify the CPU type and fix up code sections
* that depend on which cpu we have.
*/
+#if defined(CONFIG_440EP) && defined(CONFIG_PPC_FPU)
+ /* We pass the virtual PVR here for 440EP as 440EP and 440GR have
+ * identical PVRs and there is no reliable way to check for the FPU
+ */
+ spec = identify_cpu(offset, (mfspr(SPRN_PVR) | 0x8));
+#else
spec = identify_cpu(offset, mfspr(SPRN_PVR));
+#endif
do_feature_fixups(spec->cpu_features,
PTRRELOC(&__start___ftr_fixup),
PTRRELOC(&__stop___ftr_fixup));
^ permalink raw reply
* [POWERPC] [RFC] Fix 8xx tlbie definition
From: Josh Boyer @ 2007-11-16 17:28 UTC (permalink / raw)
To: vitb, benh; +Cc: linuxppc-dev
Git commit e701d269aa28996f3502780951fe1b12d5d66b49 introduced an incorrect
definition for _tlbie on PowerPC 8xx platforms. Only the address should be
passed to the function. This patch corrects the definition of _tlbie and the
related tlb flushing functions for 8xx.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Index: linux-2.6/include/asm-powerpc/tlbflush.h
===================================================================
--- linux-2.6.orig/include/asm-powerpc/tlbflush.h
+++ linux-2.6/include/asm-powerpc/tlbflush.h
@@ -28,19 +28,33 @@
#include <linux/mm.h>
+#if defined(CONFIG_8xx)
+/* 8xx doesn't use PID for TLB invalidates */
+extern void _tlbie(unsigned address);
+#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
+
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+ unsigned long vmaddr)
+{
+ _tlbie(vmaddr);
+}
+
+static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
+ unsigned long vmaddr)
+{
+ _tlbie(vmaddr);
+}
+
+#else /* 4xx or FSL_BOOKE */
+
extern void _tlbie(unsigned long address, unsigned int pid);
-#if defined(CONFIG_40x) || defined(CONFIG_8xx)
+#if defined(CONFIG_40x)
#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
extern void _tlbia(void);
#endif
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
- _tlbia();
-}
-
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
@@ -53,6 +67,13 @@ static inline void flush_tlb_page_nohash
_tlbie(vmaddr, vma->vm_mm->context.id);
}
+#endif /* CONFIG_8xx */
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+ _tlbia();
+}
+
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
^ permalink raw reply
* [PATCH 5/5] PowerPC 74xx: Katana Qp default config
From: Andrei Dolnikov @ 2007-11-16 16:35 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071107173719.GG16183@ru.mvista.com>
Default kernel config for Emerson Katana Qp board
Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>
---
arch/powerpc/configs/katanaqp_defconfig | 941 ++++++++++++++++++++++++++++++++
1 files changed, 941 insertions(+)
diff --git a/arch/powerpc/configs/katanaqp_defconfig b/arch/powerpc/configs/katanaqp_defconfig
new file mode 100644
index 0000000..7ea32ca
--- /dev/null
+++ b/arch/powerpc/configs/katanaqp_defconfig
@@ -0,0 +1,941 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc2
+# Tue Nov 13 16:02:34 2007
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+CONFIG_ALTIVEC=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_CHECK_CACHE_COHERENCY=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Platform support
+#
+CONFIG_PPC_MULTIPLATFORM=y
+# CONFIG_PPC_82xx is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_86xx is not set
+CONFIG_CLASSIC32=y
+# CONFIG_PPC_CHRP is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_EFIKA is not set
+# CONFIG_PPC_LITE5200 is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_EMBEDDED6xx=y
+# CONFIG_LINKSTATION is not set
+# CONFIG_MPC7448HPC2 is not set
+# CONFIG_PPC_HOLLY is not set
+# CONFIG_PPC_PRPMC2800 is not set
+CONFIG_PPC_KATANAQP=y
+CONFIG_MV64X60=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+# CONFIG_CPM2 is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+# CONFIG_KEXEC is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_HIBERNATION_UP_POSSIBLE=y
+# CONFIG_SECCOMP is not set
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_DEVICE_TREE="katanaqp.dts"
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+# CONFIG_MTD_CFI_I1 is not set
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_IP1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_EEPRO100 is not set
+CONFIG_E100=y
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000_NAPI is not set
+# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
+# CONFIG_E1000E is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_MPSC=y
+CONFIG_SERIAL_MPSC_CONSOLE=y
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+# CONFIG_UCC_SLOW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_INSTRUMENTATION=y
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_SAMPLES is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set
^ permalink raw reply related
* [PATCH 4/5] PowerPC 74xx: Katana Qp base support
From: Andrei Dolnikov @ 2007-11-16 16:31 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071116154344.GA25062@ru.mvista.com>
Emerson Katana Qp platform specific code
Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>
---
arch/powerpc/platforms/embedded6xx/Kconfig | 9 +
arch/powerpc/platforms/embedded6xx/Makefile | 1
arch/powerpc/platforms/embedded6xx/katanaqp.c | 180 ++++++++++++++++++++++++++
3 files changed, 190 insertions(+)
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 8924095..33190bd 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -46,6 +46,15 @@ config PPC_PRPMC2800
help
This option enables support for the Motorola PrPMC2800 board
+config PPC_KATANAQP
+ bool "Emerson-Katana Qp"
+ depends on EMBEDDED6xx
+ select MV64X60
+ select NOT_COHERENT_CACHE
+ select WANT_DEVICE_TREE
+ help
+ This option enables support for the Emerson Katana Qp board
+
config TSI108_BRIDGE
bool
depends on MPC7448HPC2 || PPC_HOLLY
diff --git a/arch/powerpc/platforms/embedded6xx/Makefile b/arch/powerpc/platforms/embedded6xx/Makefile
index 844947c..c83558f 100644
--- a/arch/powerpc/platforms/embedded6xx/Makefile
+++ b/arch/powerpc/platforms/embedded6xx/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_MPC7448HPC2) += mpc7448_hpc2.o
obj-$(CONFIG_LINKSTATION) += linkstation.o ls_uart.o
obj-$(CONFIG_PPC_HOLLY) += holly.o
obj-$(CONFIG_PPC_PRPMC2800) += prpmc2800.o
+obj-$(CONFIG_PPC_KATANAQP) += katanaqp.o
diff --git a/arch/powerpc/platforms/embedded6xx/katanaqp.c b/arch/powerpc/platforms/embedded6xx/katanaqp.c
new file mode 100644
index 0000000..c0a8469
--- /dev/null
+++ b/arch/powerpc/platforms/embedded6xx/katanaqp.c
@@ -0,0 +1,180 @@
+/*
+ * Board setup routines for the Emerson Katana Qp
+ *
+ * Authors: Vladislav Buzov <vbuzov@ru.mvista.com>
+ * Andrei Dolnikov <adolnikov@ru.mvista.com>
+ *
+ * Based on prpmc2800.c by Dale Farnsworth <dale@farnsworth.org>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/seq_file.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/kexec.h>
+
+#include <mm/mmu_decl.h>
+
+#include <sysdev/mv64x60.h>
+
+#define PLATFORM_NAME_MAX 64
+
+/* CPLD registers definitions */
+#define KATANAQP_CPLD_RCR 0x0004 /* Reset command */
+#define KATANAQP_CPLD_RCR_CPUHR (1 << 7)
+
+#define KATANAQP_CPLD_HVR 0x0020
+
+#define KATANAQP_CPLD_PSR 0x0030 /* PCI status */
+#define KATANAQP_CPLD_PSR_PMCM (1 << 1)
+
+#define KATANAQP_CPLD_HCR 0x0044
+
+static char katanaqp_platform_name[PLATFORM_NAME_MAX];
+
+static void __iomem *cpld_base;
+
+int katanaqp_exclude_device(struct pci_controller *hose, u_char bus,
+ u_char devfn)
+{
+ if (bus == 0 && PCI_SLOT(devfn) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ else
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int __init katanaqp_is_monarch(void)
+{
+ return !(in_8((volatile char *)(cpld_base + KATANAQP_CPLD_PSR)) &
+ KATANAQP_CPLD_PSR_PMCM);
+}
+
+static void __init katanaqp_setup_arch(void)
+{
+ struct device_node *cpld;
+ const unsigned int *reg;
+
+ /*
+ * ioremap cpld registers in case they are later
+ * needed by katanaqp_reset_board().
+ */
+ cpld = of_find_node_by_path("/mv64x60@f8100000/cpld@f8200000");
+ reg = of_get_property(cpld, "reg", NULL);
+ of_node_put(cpld);
+ cpld_base = ioremap(reg[0], reg[1]);
+
+#ifdef CONFIG_PCI
+ if (katanaqp_is_monarch()) {
+ mv64x60_pci_init();
+ ppc_md.pci_exclude_device = katanaqp_exclude_device;
+ }
+#endif
+
+ printk("Emerson Network Power %s\n", katanaqp_platform_name);
+}
+
+static void katanaqp_reset_board(void)
+{
+ local_irq_disable();
+
+ /* issue hard reset to the reset command register */
+ out_8((volatile char *)(cpld_base + KATANAQP_CPLD_RCR),
+ KATANAQP_CPLD_RCR_CPUHR);
+ for (;;) ;
+}
+
+static void katanaqp_restart(char *cmd)
+{
+ katanaqp_reset_board();
+}
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+#define KATANAQP_COHERENCY_SETTING "off"
+#else
+#define KATANAQP_COHERENCY_SETTING "on"
+#endif
+
+void katanaqp_show_cpuinfo(struct seq_file *m)
+{
+ uint memsize = total_memory;
+
+ seq_printf(m, "vendor\t\t: Emerson Network Power\n");
+
+ seq_printf(m, "hardware rev\t: %d\n",
+ in_8((volatile char *)(cpld_base + KATANAQP_CPLD_HVR)));
+
+ seq_printf(m, "hardware config\t: %d\n",
+ in_8((volatile char *)(cpld_base + KATANAQP_CPLD_HCR)));
+
+ seq_printf(m, "memory size\t: %d MB\n", memsize / (1024 * 1024));
+
+ seq_printf(m, "voherency\t: %s\n", KATANAQP_COHERENCY_SETTING);
+
+ seq_printf(m, "PCI\t\t: %sMonarch\n",
+ katanaqp_is_monarch() ? "" : "Non-");
+}
+
+static int __init katanaqp_of_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "cfi-flash");
+ if (np)
+ of_platform_device_create(np, "of-flash", NULL);
+
+ return 0;
+}
+
+device_initcall(katanaqp_of_init);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init katanaqp_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+ unsigned long len = PLATFORM_NAME_MAX;
+ void *m;
+
+ if (!of_flat_dt_is_compatible(root, "emerson,Katana-Qp"))
+ return 0;
+
+ /* Update ppc_md.name with name from dt */
+ m = of_get_flat_dt_prop(root, "model", &len);
+ if (m)
+ strncpy(katanaqp_platform_name, m,
+ min((int)len, PLATFORM_NAME_MAX - 1));
+
+ return 1;
+}
+
+define_machine(katanaqp)
+{
+ .name = katanaqp_platform_name,
+ .probe = katanaqp_probe,
+ .setup_arch = katanaqp_setup_arch,
+ .init_early = mv64x60_init_early,
+ .show_cpuinfo = katanaqp_show_cpuinfo,
+ .init_IRQ = mv64x60_init_irq,
+ .get_irq = mv64x60_get_irq,
+ .restart = katanaqp_restart,
+ .calibrate_decr = generic_calibrate_decr,
+#ifdef CONFIG_KEXEC
+ .machine_kexec = default_machine_kexec,
+ .machine_kexec_prepare = default_machine_kexec_prepare,
+ .machine_crash_shutdown = default_machine_crash_shutdown,
+#endif
+};
^ permalink raw reply related
* [PATCH 3/5] PowerPC 74xx: Katana Qp bootwrapper
From: Andrei Dolnikov @ 2007-11-16 16:25 UTC (permalink / raw)
To: linuxppc-dev
Bootwrapper sources for Emerson Katana Qp
Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>
---
arch/powerpc/boot/Makefile | 3
arch/powerpc/boot/cuboot-katanaqp.c | 470 ++++++++++++++++++++++++++++++++++++
2 files changed, 472 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 18e3271..92b8fac 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -56,7 +56,7 @@ src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
- fixed-head.S ep88xc.c cuboot-hpc2.c
+ fixed-head.S ep88xc.c cuboot-hpc2.c cuboot-katanaqp.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -159,6 +159,7 @@ image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo
image-$(CONFIG_SEQUOIA) += cuImage.sequoia
image-$(CONFIG_WALNUT) += treeImage.walnut
+image-$(CONFIG_PPC_KATANAQP) += cuImage.katanaqp
endif
# For 32-bit powermacs, build the COFF and miboot images
diff --git a/arch/powerpc/boot/cuboot-katanaqp.c b/arch/powerpc/boot/cuboot-katanaqp.c
new file mode 100644
index 0000000..905ad6a
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-katanaqp.c
@@ -0,0 +1,470 @@
+/*
+ * Emerson Katana Qp platform code.
+ *
+ * Authors: Vladislav Buzov <buzov@ru.mvista.com>
+ * Andrei Dolnikov <adolnikov@ru.mvista.com>
+ *
+ * Based on prpmc2800.c by Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include "cuboot.h"
+#include "ppcboot.h"
+#include "types.h"
+#include "page.h"
+#include "string.h"
+#include "stdio.h"
+#include "io.h"
+#include "ops.h"
+#include "mv64x60.h"
+
+#define Mb (1024U * 1024U)
+#define Gb (Mb * 1024U)
+
+#define MHz (1000U * 1000U)
+#define GHz (MHz * 1000U)
+
+#define BOARD_MODEL "Katana-Qp"
+#define BOARD_MODEL_MAX 12 /* max strlen(BOARD_MODEL) + 1 */
+#define BOARD_CFG_MAX 28 /* max strlen(BOARD_CFG) + 1 */
+#define BOARD_MODEL_LEN (BOARD_MODEL_MAX + BOARD_CFG_MAX)
+
+#define MTD_PART_NODE "partition"
+#define MTD_PART_NUM 3
+#define MTD_PART_NODE_LEN 20
+#define MTD_PART_MONITOR_SIZE (1*Mb)
+#define MTD_PART_KERNEL_SIZE (2*Mb)
+
+/*
+ * CPLD registers definitions
+ */
+#define KATANAQP_CPLD_RCR 0x0004 /* Reset command */
+#define KATANAQP_CPLD_RCR_CPUHR (1 << 7)
+
+#define KATANAQP_CPLD_JSR 0x0020 /* Jumper settings */
+#define KATANAQP_CPLD_JSR_EBFM (1 << 6)
+
+#define KATANAQP_CPLD_PSR 0x0030 /* PCI status */
+#define KATANAQP_CPLD_PSR_PMCM (1 << 1)
+
+#define KATANAQP_CPLD_HCR 0x0044 /* Hardware config */
+
+static bd_t bd;
+
+static u8 *bridge_base;
+static u8 *cpld_base;
+
+typedef enum {
+ KATANAQP_UNKNOWN,
+ KATANAQP_CFG_PRPMC_SINGLE,
+ KATANAQP_CFG_PRPMC_DUAL,
+ KATANAQP_CFG_PT2CC_SINGLE,
+ KATANAQP_CFG_PT5CC_SINGLE,
+ KATANAQP_CFG_MEDIA_DUAL,
+ KATANAQP_CFG_PT2CC_DUAL,
+ KATANAQP_CFG_PT5CC_DUAL,
+ KATANAQP_CFG_PT5CC_CUSTOM,
+ KATANAQP_CFG_MEDIA_SINGLE,
+ KATANAQP_CFG_UNKNOWN,
+} katanaqp_board_model;
+
+static katanaqp_board_model katanaqp_cfg;
+
+struct katanaqp_board_info {
+ char *cfg_name;
+ char eth_phys[3];
+};
+
+struct katanaqp_mtd_part {
+ char *name;
+ u32 size;
+ u32 ro;
+};
+
+static struct katanaqp_board_info katanaqp_board_info[] = {
+
+ [KATANAQP_CFG_PRPMC_SINGLE] = {
+ .cfg_name = "PrPMC Single Core",
+ .eth_phys = {10, 13, 6},
+ },
+
+ [KATANAQP_CFG_PRPMC_DUAL] = {
+ .cfg_name = "PrPMC Dual Core",
+ .eth_phys = {10, 13, 6}
+ },
+
+ [KATANAQP_CFG_PT2CC_SINGLE] = {
+ .cfg_name = "PT2CC Single Core",
+ .eth_phys = {9, 8, 6},
+ },
+
+ [KATANAQP_CFG_PT5CC_SINGLE] = {
+ .cfg_name = "PT5CC Single Core",
+ .eth_phys = {10, 13, 6},
+ },
+
+ [KATANAQP_CFG_MEDIA_DUAL] = {
+ .cfg_name = "Dual Core Media Blade",
+ .eth_phys = {10, 13, 6},
+ },
+
+ [KATANAQP_CFG_PT2CC_DUAL] = {
+ .cfg_name = "PT2CC Dual Core",
+ .eth_phys = {9, 8, 6},
+ },
+
+ [KATANAQP_CFG_PT5CC_DUAL] = {
+ .cfg_name = "PT5CC Dual Core",
+ .eth_phys = {10, 13, 6},
+ },
+
+ [KATANAQP_CFG_MEDIA_SINGLE] = {
+ .cfg_name = "Single Core Media Blade",
+ .eth_phys = {10, 13, 6},
+ },
+};
+
+/*
+ * Second flash bank partition layout.
+ */
+static struct katanaqp_mtd_part katanaqp_mtd_parts[MTD_PART_NUM] = {
+ {
+ .name = "Secondary Monitor",
+ .size = MTD_PART_MONITOR_SIZE,
+ .ro = 1,
+ },
+
+ {
+ .name = "Secondary Kernel",
+ .size = MTD_PART_KERNEL_SIZE,
+ },
+
+ {
+ /* Size depends on actual flash bank size */
+ .name = "Secondary FS",
+ },
+};
+
+static u8 *katanaqp_get_cpld_base(void)
+{
+ u32 v;
+ void *devp;
+
+ devp = finddevice("/mv64x60/cpld");
+ if (devp == NULL)
+ fatal("Error: Missing CPLD device tree node\n\r");
+
+ if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
+ fatal("Error: Can't get CPLD base address\n\r");
+
+ return (u8 *) v;
+}
+
+static void katanaqp_get_cfg(void)
+{
+ katanaqp_cfg = in_8(cpld_base + KATANAQP_CPLD_HCR) & 0xf;
+
+ if (katanaqp_cfg > 9)
+ katanaqp_cfg = KATANAQP_UNKNOWN;
+}
+
+static int katanaqp_is_monarch(void)
+{
+ return !(in_8(cpld_base + KATANAQP_CPLD_PSR) &
+ KATANAQP_CPLD_PSR_PMCM);
+}
+
+static void katanaqp_bridge_setup(void)
+{
+ u32 i, v[12], enables, acc_bits;
+ u32 pci_base_hi, pci_base_lo, size, buf[2];
+ unsigned long cpu_base;
+ int rc;
+ void *devp;
+ u8 *bridge_pbase, is_coherent;
+ struct mv64x60_cpu2pci_win *tbl;
+
+ bridge_pbase = mv64x60_get_bridge_pbase();
+ is_coherent = mv64x60_is_coherent();
+
+ if (is_coherent)
+ acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
+ | MV64x60_PCI_ACC_CNTL_SWAP_NONE
+ | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
+ | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
+ else
+ acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
+ | MV64x60_PCI_ACC_CNTL_SWAP_NONE
+ | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
+ | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
+
+ /*
+ * MV64x60 boot code expects PCI host bridge to have 0 device
+ * number and access PCI configuration bridge registers by
+ * DEVFN(0, fn). This is not correct for bridges working in PCI-X
+ * mode since by default it has 0x1f device number stored in P2P
+ * configuration register.
+ */
+ mv64x60_set_pci_bus(bridge_base, 1, 0, 0);
+
+ mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
+ mv64x60_config_pci_windows(bridge_base, bridge_pbase, 1, 0, acc_bits);
+
+ /* Get the cpu -> pci i/o & mem mappings from the device tree */
+ devp = finddevice("/mv64x60/pci");
+ if (devp == NULL)
+ fatal("Error: Missing /mv64x60/pci device tree node\n\r");
+
+ rc = getprop(devp, "ranges", v, sizeof(v));
+ if (rc != sizeof(v))
+ fatal("Error: Can't find /mv64x60/pci/ranges property\n\r");
+
+ /* Get the cpu -> pci i/o & mem mappings from the device tree */
+ devp = finddevice("/mv64x60");
+ if (devp == NULL)
+ fatal("Error: Missing /mv64x60 device tree node\n\r");
+
+
+ enables = in_le32((u32 *) (bridge_base + MV64x60_CPU_BAR_ENABLE));
+ enables |= 0x0007fe00; /* Disable all cpu->pci windows */
+ out_le32((u32 *) (bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
+
+ for (i = 0; i < 12; i += 6) {
+ switch (v[i] & 0xff000000) {
+ case 0x01000000: /* PCI I/O Space */
+ tbl = mv64x60_cpu2pci_io;
+ break;
+ case 0x02000000: /* PCI MEM Space */
+ tbl = mv64x60_cpu2pci_mem;
+ break;
+ default:
+ continue;
+ }
+
+ pci_base_hi = v[i + 1];
+ pci_base_lo = v[i + 2];
+ cpu_base = v[i + 3];
+ size = v[i + 5];
+
+ buf[0] = cpu_base;
+ buf[1] = size;
+
+ if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
+ fatal("Error: Can't translate PCI address 0x%x\n\r",
+ (u32) cpu_base);
+
+ mv64x60_config_cpu2pci_window(bridge_base, 1, pci_base_hi,
+ pci_base_lo, cpu_base, size, tbl);
+ }
+
+ /* Enable cpu->pci1 i/o, cpu->pci1 mem0 */
+ enables &= ~0x0000c000;
+ out_le32((u32 *) (bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
+
+}
+
+/*
+ * Different Katana Qp configurations have different flash sizes varying
+ * from 16Mb to 64Mb. This routine determines an exact flash size and
+ * updates the device tree accordingly.
+ */
+static void katanaqp_flash_fixup(void)
+{
+ u32 flash0_size = 0, flash1_size = 0;
+ u32 total_size, size_left;
+ u32 part, part_offset;
+ u32 rc, v[2];
+ void *devp = NULL, *pp = NULL;
+ char part_node[MTD_PART_NODE_LEN];
+
+ devp = finddevice("/mv64x60/flash");
+ if (devp == NULL) {
+ printf("Missing flash device tree node\n\r");
+ return;
+ }
+
+ /*
+ * Get fist flash size: bank0, bank1 and total
+ */
+ flash0_size = mv64x60_get_devcs_size(bridge_base, 0);
+ if (flash0_size == 0)
+ return;
+
+ flash1_size = mv64x60_get_devcs_size(bridge_base, 1);
+ total_size = flash0_size + flash1_size;
+
+ /*
+ * Set total flash size
+ */
+ rc = getprop(devp, "reg", v, sizeof(v));
+ if (rc != sizeof(v))
+ fatal("Error: Can't find /mv64x60/flash/reg property\n\r");
+ v[1] = total_size;
+ setprop(devp, "reg", v, sizeof(v));
+
+ /*
+ * Set Primary FS partition size: up to the end of first flash bank
+ */
+ pp = find_node_by_prop_value_str(NULL, "label", "Primary FS");
+ if (pp == NULL)
+ fatal("Error: Missing flash Primary FS device tree node\n\r");
+
+ rc = getprop(pp, "reg", v, sizeof(v));
+ if (rc != sizeof(v))
+ fatal("Error: Can't find /mv64x60/flash/partition@3000000 "
+ "property\n\r");
+
+ v[1] = flash0_size - MTD_PART_MONITOR_SIZE - MTD_PART_KERNEL_SIZE;
+ setprop(pp, "reg", v, sizeof(v));
+
+ if (flash1_size == 0)
+ /* Only 1 flash bank is presented */
+ return;
+
+ /*
+ * Ok, there is a second flash bank. Let's split it to partitions.
+ */
+
+ part_offset = flash0_size;
+ size_left = flash1_size;
+
+ /* Skip Secondary Monitor if Boot Failover mechanism is disabled */
+ rc = in_8(cpld_base + KATANAQP_CPLD_JSR) & KATANAQP_CPLD_JSR_EBFM;
+ part = rc ? 0 : 1;
+
+ for (; part < MTD_PART_NUM; part++) {
+
+ sprintf(part_node, "%s@%x", MTD_PART_NODE, part_offset);
+ pp = create_node(devp, part_node);
+ if (pp == NULL)
+ fatal("Error: Can't create new partition node\n\r");
+
+ setprop_str(pp, "label", katanaqp_mtd_parts[part].name);
+
+ if (katanaqp_mtd_parts[part].ro)
+ setprop(pp, "read-only", NULL, 0);
+
+ v[0] = part_offset;
+ v[1] = katanaqp_mtd_parts[part].size;
+ if (v[1] == 0)
+ /* Take all remaining space */
+ v[1] = size_left;
+
+ part_offset += v[1];
+ size_left -= v[1];
+
+ setprop(pp, "reg", v, sizeof(v));
+
+ }
+}
+
+static void katanaqp_fixups(void)
+{
+ u32 l, p, pnum;
+ void *devp = NULL;
+ struct katanaqp_board_info katanaqp_bif;
+ char model[BOARD_MODEL_LEN];
+
+ /* Check Katana Qp configuration */
+ katanaqp_get_cfg();
+ if (katanaqp_cfg == KATANAQP_CFG_UNKNOWN)
+ fatal("Error: Unsupported Katana Qp board configuration\n\r");
+
+ if (katanaqp_cfg == KATANAQP_CFG_PT5CC_CUSTOM) {
+ printf("Katana Qp board custom configuration detected, "
+ "using device tree defaults. Please, supply a correct "
+ "device tree\n\r");
+ return;
+ }
+
+ katanaqp_bif = katanaqp_board_info[katanaqp_cfg];
+
+ /*
+ * Set /model appropriately
+ */
+ devp = finddevice("/");
+ if (devp == NULL)
+ fatal("Error: Missing '/' device tree node\n\r");
+
+ /*
+ * Fix Board model name in device tree
+ */
+ memset(model, 0, BOARD_MODEL_LEN);
+
+ strncpy(model, BOARD_MODEL, BOARD_MODEL_MAX - 1);
+ l = strlen(model);
+ model[l++] = ' ';
+
+ strncpy(&model[l], katanaqp_bif.cfg_name, BOARD_CFG_MAX - 1);
+ l += strlen(&model[l]);
+ model[l++] = '\0';
+
+ setprop(devp, "model", model, l);
+
+ /*
+ * Do necessary bridge setup if we are monarch
+ */
+ if (katanaqp_is_monarch())
+ katanaqp_bridge_setup();
+
+ /*
+ * Fix RAM size and setup MV64460 bridge
+ */
+ dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
+
+ /*
+ * Fix flash size and partition layout
+ */
+ katanaqp_flash_fixup();
+
+ /*
+ * Fix clocks
+ */
+ dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
+
+ /*
+ * Fix phy addresses
+ */
+ while ((devp = find_node_by_prop_value_str(devp, "comaptible",
+ "marvell,mv88e1111"))) {
+ getprop(devp, "block-index", &p, sizeof(p));
+ pnum = katanaqp_bif.eth_phys[p];
+ setprop_val(devp, "reg", pnum);
+ }
+}
+
+static void katanaqp_reset(void)
+{
+
+ /* issue hard reset to the reset command register */
+ if (cpld_base)
+ out_8(cpld_base + KATANAQP_CPLD_RCR,
+ KATANAQP_CPLD_RCR_CPUHR);
+
+ for (;;) ;
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+
+ CUBOOT_INIT();
+
+ if (ft_init(_dtb_start, _dtb_end - _dtb_start, 16))
+ exit();
+
+ bridge_base = mv64x60_get_bridge_base();
+ cpld_base = katanaqp_get_cpld_base();
+
+ platform_ops.fixups = katanaqp_fixups;
+ platform_ops.exit = katanaqp_reset;
+
+ if (serial_console_init() < 0)
+ exit();
+}
^ permalink raw reply related
* [PATCH 2/5] PowerPC 74xx: Minor updates to MV64x60 boot code
From: Andrei Dolnikov @ 2007-11-16 16:18 UTC (permalink / raw)
To: linuxppc-dev
This patch adds new functionality to MV64x60 boot code. The changes are required
to access DevCS windows registers and set PCI bus and devfn numbers for MV644x60
PCI/PCI-X interfaces.
Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvista.com>
---
arch/powerpc/boot/mv64x60.c | 74 ++++++++++++++++++++++++++++++++++++++++++++
arch/powerpc/boot/mv64x60.h | 10 +++++
2 files changed, 84 insertions(+)
diff --git a/arch/powerpc/boot/mv64x60.c b/arch/powerpc/boot/mv64x60.c
index d207a0b..787a124 100644
--- a/arch/powerpc/boot/mv64x60.c
+++ b/arch/powerpc/boot/mv64x60.c
@@ -32,6 +32,16 @@
#define MV64x60_CPU2MEM_3_BASE 0x0218
#define MV64x60_CPU2MEM_3_SIZE 0x0220
+#define MV64x60_DEV2MEM_WINDOWS 4
+#define MV64x60_DEV2MEM_0_BASE 0x0028
+#define MV64x60_DEV2MEM_0_SIZE 0x0030
+#define MV64x60_DEV2MEM_1_BASE 0x0228
+#define MV64x60_DEV2MEM_1_SIZE 0x0230
+#define MV64x60_DEV2MEM_2_BASE 0x0248
+#define MV64x60_DEV2MEM_2_SIZE 0x0250
+#define MV64x60_DEV2MEM_3_BASE 0x0038
+#define MV64x60_DEV2MEM_3_SIZE 0x0040
+
#define MV64x60_ENET2MEM_BAR_ENABLE 0x2290
#define MV64x60_ENET2MEM_0_BASE 0x2200
#define MV64x60_ENET2MEM_0_SIZE 0x2204
@@ -219,6 +229,25 @@ static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = {
},
};
+static struct mv64x60_mem_win mv64x60_devcs[MV64x60_DEV2MEM_WINDOWS] = {
+ [0] = {
+ .lo = MV64x60_DEV2MEM_0_BASE,
+ .size = MV64x60_DEV2MEM_0_SIZE,
+ },
+ [1] = {
+ .lo = MV64x60_DEV2MEM_1_BASE,
+ .size = MV64x60_DEV2MEM_1_SIZE,
+ },
+ [2] = {
+ .lo = MV64x60_DEV2MEM_2_BASE,
+ .size = MV64x60_DEV2MEM_2_SIZE,
+ },
+ [3] = {
+ .lo = MV64x60_DEV2MEM_3_BASE,
+ .size = MV64x60_DEV2MEM_3_SIZE,
+ },
+};
+
static struct mv64x60_mem_win mv64x60_enet2mem[MV64x60_CPU2MEM_WINDOWS] = {
[0] = {
.lo = MV64x60_ENET2MEM_0_BASE,
@@ -567,6 +596,36 @@ void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);
}
+/* Set PCI bus number for a PCI interface and force its devnum to 0 */
+void mv64x60_set_pci_bus(u8 *bridge_base, u8 hose, u32 bus, u32 devnum)
+{
+ u8 *pci_mode_reg, *p2p_cfg_reg;
+ u32 pci_mode, p2p_cfg;
+ u32 pci_cfg_offset;
+
+ if (hose == 0) {
+ pci_mode_reg = bridge_base + MV64x60_PCI0_MODE;
+ p2p_cfg_reg = bridge_base + MV64x60_PCI0_P2P_CONF;
+ pci_cfg_offset = 0x64;
+ } else {
+ pci_mode_reg = bridge_base + MV64x60_PCI1_MODE;
+ p2p_cfg_reg = bridge_base + MV64x60_PCI1_P2P_CONF;
+ pci_cfg_offset = 0xe4;
+ }
+
+ pci_mode = in_le32((u32*)pci_mode_reg) & MV64x60_PCI_MODE_MASK;
+ p2p_cfg = in_le32((u32*)p2p_cfg_reg);
+
+ if (pci_mode == MV64x60_PCI_CONVENTIONAL_MODE) {
+ p2p_cfg &= 0xe0000000;
+ p2p_cfg |= (devnum << 24) | (bus << 16) | 0xff;
+ out_le32((u32*)p2p_cfg_reg, p2p_cfg);
+ } else
+ mv64x60_cfg_write(bridge_base, hose, (p2p_cfg >> 16) & 0xff,
+ PCI_DEVFN((p2p_cfg >> 24) & 0x1f, 0),
+ pci_cfg_offset, (devnum << 3) | (bus << 8));
+}
+
/* Read mem ctlr to get the amount of mem in system */
u32 mv64x60_get_mem_size(u8 *bridge_base)
{
@@ -586,6 +645,21 @@ u32 mv64x60_get_mem_size(u8 *bridge_base)
return mem;
}
+/* Read a size of DEV_CS window */
+u32 mv64x60_get_devcs_size(u8 *bridge_base, u32 devcs)
+{
+ u32 enables, size = 0;
+
+ enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf0;
+
+ if (devcs < 4 && !(enables && (0x10 << devcs))) {
+ size = in_le32((u32*)(bridge_base + mv64x60_devcs[devcs].size));
+ size = ((size & 0xffff) + 1) << 16;
+ }
+
+ return size;
+}
+
/* Get physical address of bridge's registers */
u8 *mv64x60_get_bridge_pbase(void)
{
diff --git a/arch/powerpc/boot/mv64x60.h b/arch/powerpc/boot/mv64x60.h
index d0b29a7..a633d2e 100644
--- a/arch/powerpc/boot/mv64x60.h
+++ b/arch/powerpc/boot/mv64x60.h
@@ -12,6 +12,14 @@
#define MV64x60_CPU_BAR_ENABLE 0x0278
+#define MV64x60_PCI0_MODE 0x0d00
+#define MV64x60_PCI1_MODE 0x0d80
+#define MV64x60_PCI0_P2P_CONF 0x1d14
+#define MV64x60_PCI1_P2P_CONF 0x1d94
+
+#define MV64x60_PCI_MODE_MASK 0x00000030
+#define MV64x60_PCI_CONVENTIONAL_MODE 0x00000000
+
#define MV64x60_PCI_ACC_CNTL_ENABLE (1<<0)
#define MV64x60_PCI_ACC_CNTL_REQ64 (1<<1)
#define MV64x60_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
@@ -57,7 +65,9 @@ void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
u32 pci_base_lo, u32 cpu_base, u32 size,
struct mv64x60_cpu2pci_win *offset_tbl);
+void mv64x60_set_pci_bus(u8 *bridge_base, u8 hose, u32 bus, u32 devnum);
u32 mv64x60_get_mem_size(u8 *bridge_base);
+u32 mv64x60_get_devcs_size(u8 *bridge_base, u32 devcs);
u8 *mv64x60_get_bridge_pbase(void);
u8 *mv64x60_get_bridge_base(void);
u8 mv64x60_is_coherent(void);
^ permalink raw reply related
* [PATCH 1/5] PowerPC 74xx: Katana Qp device tree
From: Andrei Dolnikov @ 2007-11-16 16:12 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071116154344.GA25062@ru.mvista.com>
Device tree source file for the Emerson Katana Qp board
Signed-off-by: Andrei Dolnikov <adolnikov@ru.mvisa.com>
---
arch/powerpc/boot/dts/katanaqp.dts | 357 +++++++++++++++++++++++++++++++++++++
1 files changed, 357 insertions(+)
diff --git a/arch/powerpc/boot/dts/katanaqp.dts b/arch/powerpc/boot/dts/katanaqp.dts
new file mode 100644
index 0000000..9273c4e
--- /dev/null
+++ b/arch/powerpc/boot/dts/katanaqp.dts
@@ -0,0 +1,357 @@
+/* Device Tree Source for Emerson Katana Qp
+ *
+ * Authors: Vladislav Buzov <vbuzov@ru.mvista.com>
+ * Andrei Dolnikov <adolnikov@ru.mvista.com>
+ *
+ * Based on prpmc8200.dts by Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "Katana-Qp"; /* Default */
+ compatible = "emerson,Katana-Qp";
+ coherency-off;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,7448@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* From U-boot */
+ bus-frequency = <0>; /* From U-boot */
+ timebase-frequency = <0>; /* From U-boot */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <8000>;
+ d-cache-size = <8000>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; /* Default (512MB) */
+ };
+
+ mv64x60@f8100000 { /* Marvell Discovery */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "mv64460"; /* Default */
+ compatible = "marvell,mv64x60";
+ clock-frequency = <7f28155>; /* 133.333333 MHz */
+ reg = <f8100000 00010000>;
+ virtual-reg = <f8100000>;
+ ranges = <c1000000 c1000000 01000000 /* PCI 1 I/O Space */
+ 90000000 90000000 30000000 /* PCI 1 MEM Space */
+ e8000000 e8000000 04000000 /* User FLASH: Up to 64Mb */
+ 00000000 f8100000 00010000 /* Bridge's regs */
+ f8500000 f8500000 00040000>; /* Integrated SRAM */
+
+ flash@e8000000 {
+ compatible = "cfi-flash";
+ reg = <e8000000 1000000>; /* Default (16MB) */
+ probe-type = "CFI";
+ bank-width = <4>;
+
+ partition@0 {
+ label = "Primary Monitor";
+ reg = <0 100000>; /* 1Mb */
+ read-only;
+ };
+
+ partition@100000 {
+ label = "Primary Kernel";
+ reg = <100000 200000>; /* 2 Mb */
+ };
+
+ partition@300000 {
+ label = "Primary FS";
+ reg = <300000 d00000>; /* 13 Mb */
+ };
+
+ };
+
+ cpld@f8200000 {
+ compatible = "altera,maxii";
+ reg = <f8200000 40000>;
+ virtual-reg = <f8200000>;
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,mv64x60-mdio";
+ ethernet-phy@0 {
+ block-index = <0>;
+ compatible = "marvell,mv88e1111";
+ reg = <a>;
+ };
+ ethernet-phy@1 {
+ compatible = "marvell,mv88e1111";
+ block-index = <1>;
+ reg = <d>;
+ };
+ ethernet-phy@2 {
+ compatible = "marvell,mv88e1111";
+ block-index = <2>;
+ reg = <6>;
+ };
+ };
+
+ ethernet@2000 {
+ reg = <2000 2000>;
+ eth0 {
+ device_type = "network";
+ compatible = "marvell,mv64x60-eth";
+ block-index = <0>;
+ interrupts = <20>;
+ interrupt-parent = <&/mv64x60/pic>;
+ phy = <&/mv64x60/mdio/ethernet-phy@0>;
+ speed = <3e8>;
+ duplex = <1>;
+ tx_queue_size = <320>;
+ rx_queue_size = <190>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ eth1 {
+ device_type = "network";
+ compatible = "marvell,mv64x60-eth";
+ block-index = <1>;
+ interrupts = <21>;
+ interrupt-parent = <&/mv64x60/pic>;
+ phy = <&/mv64x60/mdio/ethernet-phy@1>;
+ speed = <3e8>;
+ duplex = <1>;
+ tx_queue_size = <320>;
+ rx_queue_size = <190>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ eth2 {
+ device_type = "network";
+ compatible = "marvell,mv64x60-eth";
+ block-index = <2>;
+ interrupts = <22>;
+ interrupt-parent = <&/mv64x60/pic>;
+ phy = <&/mv64x60/mdio/ethernet-phy@2>;
+ speed = <3e8>;
+ duplex = <1>;
+ tx_queue_size = <320>;
+ rx_queue_size = <190>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+
+ sdma@4000 {
+ compatible = "marvell,mv64x60-sdma";
+ reg = <4000 c18>;
+ virtual-reg = <f8104000>;
+ interrupt-base = <0>;
+ interrupts = <24>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ sdma@6000 {
+ compatible = "marvell,mv64x60-sdma";
+ reg = <6000 c18>;
+ virtual-reg = <f8106000>;
+ interrupt-base = <0>;
+ interrupts = <26>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ brg@b200 {
+ compatible = "marvell,mv64x60-brg";
+ reg = <b200 8>;
+ clock-src = <8>;
+ clock-frequency = <7ed6b40>;
+ current-speed = <2580>;
+ bcr = <0>;
+ };
+
+ brg@b208 {
+ compatible = "marvell,mv64x60-brg";
+ reg = <b208 8>;
+ clock-src = <8>;
+ clock-frequency = <7ed6b40>;
+ current-speed = <2580>;
+ bcr = <0>;
+ };
+
+ cunit@f200 {
+ reg = <f200 200>;
+ };
+
+ mpscrouting@b400 {
+ reg = <b400 c>;
+ };
+
+ mpscintr@b800 {
+ reg = <b800 100>;
+ virtual-reg = <f810b800>;
+ };
+
+ mpsc@8000 {
+ device_type = "serial";
+ compatible = "marvell,mpsc";
+ reg = <8000 38>;
+ virtual-reg = <f8108000>;
+ sdma = <&/mv64x60/sdma@4000>;
+ brg = <&/mv64x60/brg@b200>;
+ cunit = <&/mv64x60/cunit@f200>;
+ mpscrouting = <&/mv64x60/mpscrouting@b400>;
+ mpscintr = <&/mv64x60/mpscintr@b800>;
+ block-index = <0>;
+ max_idle = <28>;
+ chr_1 = <0>;
+ chr_2 = <0>;
+ chr_10 = <3>;
+ mpcr = <0>;
+ interrupts = <28>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ mpsc@9000 {
+ device_type = "serial";
+ compatible = "marvell,mpsc";
+ reg = <9000 38>;
+ virtual-reg = <f8109000>;
+ sdma = <&/mv64x60/sdma@6000>;
+ brg = <&/mv64x60/brg@b208>;
+ cunit = <&/mv64x60/cunit@f200>;
+ mpscrouting = <&/mv64x60/mpscrouting@b400>;
+ mpscintr = <&/mv64x60/mpscintr@b800>;
+ block-index = <1>;
+ max_idle = <28>;
+ chr_1 = <0>;
+ chr_2 = <0>;
+ chr_10 = <3>;
+ mpcr = <0>;
+ interrupts = <29>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ wdt@b410 { /* watchdog timer */
+ compatible = "marvell,mv64x60-wdt";
+ reg = <b410 8>;
+ timeout = <a>; /* wdt timeout in seconds */
+ };
+
+ i2c@c000 {
+ compatible = "marvell,mv64x60-i2c";
+ reg = <c000 20>;
+ virtual-reg = <f810c000>;
+ freq_m = <8>;
+ freq_n = <3>;
+ timeout = <3e8>; /* 1000 = 1 second */
+ retries = <1>;
+ interrupts = <25>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ pic {
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ compatible = "marvell,mv64x60-pic";
+ reg = <0000 88>;
+ interrupt-controller;
+ };
+
+ mpp@f000 {
+ compatible = "marvell,mv64x60-mpp";
+ reg = <f000 10>;
+ };
+
+ gpp@f100 {
+ compatible = "marvell,mv64x60-gpp";
+ reg = <f100 20>;
+ };
+
+ pci@90000000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ compatible = "marvell,mv64x60-pci";
+ reg = <0c78 8>;
+ ranges = <01000000 0 0 c1000000 0 01000000
+ 02000000 0 90000000 90000000 0 30000000>;
+ bus-range = <0 ff>;
+ clock-frequency = <3EF1480>;
+ interrupt-pci-iack = <0c34>;
+ interrupt-parent = <&/mv64x60/pic>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x1 */
+ 0800 0 0 1 &/mv64x60/pic 5a
+ 0800 0 0 2 &/mv64x60/pic 5b
+ 0800 0 0 3 &/mv64x60/pic 5e
+ 0800 0 0 4 &/mv64x60/pic 5f
+
+ /* IDSEL 0x2 */
+ 1000 0 0 1 &/mv64x60/pic 5b
+ 1000 0 0 2 &/mv64x60/pic 5e
+ 1000 0 0 3 &/mv64x60/pic 5f
+ 1000 0 0 4 &/mv64x60/pic 5a
+
+ /* IDSEL 0x3 */
+ 1800 0 0 1 &/mv64x60/pic 5e
+ 1800 0 0 2 &/mv64x60/pic 5f
+ 1800 0 0 3 &/mv64x60/pic 5a
+ 1800 0 0 4 &/mv64x60/pic 5b
+
+ /* IDSEL 0x4 */
+ 2000 0 0 1 &/mv64x60/pic 5f
+ 2000 0 0 2 &/mv64x60/pic 5a
+ 2000 0 0 3 &/mv64x60/pic 5b
+ 2000 0 0 4 &/mv64x60/pic 5e
+
+ /* IDSEL 0x6 */
+ 3000 0 0 1 &/mv64x60/pic 5b
+ 3000 0 0 2 &/mv64x60/pic 5e
+ 3000 0 0 3 &/mv64x60/pic 5f
+ 3000 0 0 4 &/mv64x60/pic 5a
+ >;
+ };
+
+ cpu-error@0070 {
+ compatible = "marvell,mv64x60-cpu-error";
+ reg = <0070 10 0128 28>;
+ interrupts = <03>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ sram-ctrl@0380 {
+ compatible = "marvell,mv64x60-sram-ctrl";
+ reg = <0380 80>;
+ interrupts = <0d>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ pci-error@1d40 {
+ compatible = "marvell,mv64x60-pci-error";
+ reg = <1d40 40 0c28 4>;
+ interrupts = <0c>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+
+ mem-ctrl@1400 {
+ compatible = "marvell,mv64x60-mem-ctrl";
+ reg = <1400 60>;
+ interrupts = <11>;
+ interrupt-parent = <&/mv64x60/pic>;
+ };
+ };
+
+ chosen {
+ bootargs = "ip=on";
+ linux,stdout-path = "/mv64x60@f8100000/mpsc@8000";
+ };
+};
^ permalink raw reply related
* Re: [PATCH] powerpc: Add xmon function to dump 44x TLB
From: Segher Boessenkool @ 2007-11-16 16:09 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <4ccc68f867a65d70f5d1e3ee946de4d1@kernel.crashing.org>
>> +#ifdef CONFIG_44x
>> +static void dump_tlb_44x(void);
>> +#endif
>
> No need to #ifdef this...
>
>> +#ifdef CONFIG_44x
>> +static void dump_tlb_44x(void)
>> +{
>
> ...or this.
Erm actually, that last one would give you a compiler warning ("function
defined but not used"), unless you convert the point where it is used to
a plain "if" too -- probably not worth it until we have 32-bit
multiplatform
support :-)
Segher
^ permalink raw reply
* [PATCH 0/1] PowerPC 74xx: Add Emerson Katana Qp support
From: Andrei Dolnikov @ 2007-11-16 15:43 UTC (permalink / raw)
To: linuxppc-dev
Hello folks,
The following patch sequence is intended to add support for the Emerson
Katana Qp ATCA board based on MPC7448 CPU and Marvell 64460 chipset.
The patches are incremental to minor mv64x60 code fixups sent by
Mark A. Greer on 11/08/07.
Thanks,
Andrei.
^ permalink raw reply
* Re: [PATCH] powerpc: Add xmon function to dump 44x TLB
From: Segher Boessenkool @ 2007-11-16 15:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20071116072415.95082DDDF2@ozlabs.org>
> +#ifdef CONFIG_44x
> +static void dump_tlb_44x(void);
> +#endif
No need to #ifdef this...
> +#ifdef CONFIG_44x
> +static void dump_tlb_44x(void)
> +{
...or this.
Segher
^ permalink raw reply
* Re: 85xx software reset problems from paulus.git
From: Clemens Koller @ 2007-11-16 15:27 UTC (permalink / raw)
To: robert lazarski; +Cc: linuxppc-embedded
In-Reply-To: <f87675ee0711160700m17122edcv51b55f4a0cbe38b1@mail.gmail.com>
Hello, Robert!
robert lazarski schrieb:
> Hi all, on my custom 85xx board I can't do a soft reset. I'm using
> u-boot 1.3rc3 that has the latest cpu/mpc85xx/cpu.c patch to fix some
> type of reset problem. When I press the software reset button on my
> board after my nfs kernel panic, I get this:
Please define "software reset button" in your case. :-)
I consider a "button" clearly as hardware.
In my case (my button) asserts the HRESET# CPU pin low.
As far as I understood the details (not verified again):
To trigger a hard reset via software, the CPU (8540 at least)
should assert the HRESET_REQ# (Pin AG20) low (which needs
to be triggered in software, somehow).
Some external glue logic should then issue the HRESET#
(pin AH16) low to reset the CPU (hard, Power On Reset).
The SRESET# (pin AF20) is the soft reset input, causes
an mcp assertion to the core.... (RTFM)
So, the detailed explanation seems to be implementation
specific (if HRESET_REQ# can get triggered and if HRESET_REQ#
assertion is glued to assert HRESET# from the HW guys).
> Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0)
> Rebooting in 10 seconds..Machine check in kernel mode.
> Caused by (from MCSR=80000000): Machine Check Signal
> Oops: Machine check, sig: 7 [#1]
> MPC85xx CDS
> NIP: c00131f8 LR: c0014060 CTR: c00230dc
> REGS: c0289f50 TRAP: 0202 Not tainted (2.6.24-rc2-ge6a5c27f-dirty)
> MSR: 00021000 <ME> CR: 24000028 XER: 20000000
> TASK = c1020000[1] 'swapper' THREAD: c1022000
> GPR00: 00000002 c1023e30 c1020000 00000000 00000686 00000047 c1023e38 00000000
> GPR08: 7e58da6f f10000b0 003d0900 c0281ec8 44000088 7fffa7e3 3ffefb00 00800000
> GPR16: ffffffff 00000000 007fff00 c0220000 c0260000 c0260000 00000000 3ffeb254
> GPR24: c0260000 00000000 c0280000 c0219f84 c0290000 00002710 c0260000 00000000
> NIP [c00131f8] fsl_rstcr_restart+0x20/0x24
> LR [c0014060] mpc85xx_cds_restart+0x78/0x8c
> Call Trace:
> [c1023e30] [c0014008] mpc85xx_cds_restart+0x20/0x8c (unreliable)
> [c1023e50] [c000c894] machine_restart+0x34/0x48
> [c1023e60] [c0031f9c] emergency_restart+0x14/0x24
> [c1023e70] [c00234e8] panic+0x134/0x174
> [c1023f00] [c0242d5c] mount_block_root+0x108/0x24c
> [c1023f50] [c02431c0] prepare_namespace+0xd0/0x210
> [c1023f70] [c0242938] kernel_init+0x170/0x290
> [c1023ff0] [c000d2dc] kernel_thread+0x44/0x60
> Instruction dump:
> 80010014 38210010 7c0803a6 4e800020 7c000146 3d20c029 8129821c 2f890000
> 419e0010 38000002 7c0004ac 90090000 <48000000> 81230044 8009003c 70090008
> Kernel panic - not syncing: Attempted to kill init!
> Rebooting in 10 seconds..
>
> I believe Clemens recently confirmed the same issue. Any ideas?
> Robert
Not really. I just can confirm that the a $shutdown -r now doesn't
reboot my board anymore whereas 2.6.21-rc4 did.
IIRC, I've seen a patch which changed some instructions in some reboot()
function some time ago.
(Please note, I'm using the mpc8540_ads which might be slightly different
from the *_cds.)
Regards,
Clemens Koller
__________________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Straße 45/1
Linhof Werksgelände
D-81379 München
Tel.089-741518-50
Fax 089-741518-19
http://www.anagramm-technology.com
^ permalink raw reply
* 85xx software reset problems from paulus.git
From: robert lazarski @ 2007-11-16 15:00 UTC (permalink / raw)
To: linuxppc-embedded
Hi all, on my custom 85xx board I can't do a soft reset. I'm using
u-boot 1.3rc3 that has the latest cpu/mpc85xx/cpu.c patch to fix some
type of reset problem. When I press the software reset button on my
board after my nfs kernel panic, I get this:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0)
Rebooting in 10 seconds..Machine check in kernel mode.
Caused by (from MCSR=80000000): Machine Check Signal
Oops: Machine check, sig: 7 [#1]
MPC85xx CDS
NIP: c00131f8 LR: c0014060 CTR: c00230dc
REGS: c0289f50 TRAP: 0202 Not tainted (2.6.24-rc2-ge6a5c27f-dirty)
MSR: 00021000 <ME> CR: 24000028 XER: 20000000
TASK = c1020000[1] 'swapper' THREAD: c1022000
GPR00: 00000002 c1023e30 c1020000 00000000 00000686 00000047 c1023e38 00000000
GPR08: 7e58da6f f10000b0 003d0900 c0281ec8 44000088 7fffa7e3 3ffefb00 00800000
GPR16: ffffffff 00000000 007fff00 c0220000 c0260000 c0260000 00000000 3ffeb254
GPR24: c0260000 00000000 c0280000 c0219f84 c0290000 00002710 c0260000 00000000
NIP [c00131f8] fsl_rstcr_restart+0x20/0x24
LR [c0014060] mpc85xx_cds_restart+0x78/0x8c
Call Trace:
[c1023e30] [c0014008] mpc85xx_cds_restart+0x20/0x8c (unreliable)
[c1023e50] [c000c894] machine_restart+0x34/0x48
[c1023e60] [c0031f9c] emergency_restart+0x14/0x24
[c1023e70] [c00234e8] panic+0x134/0x174
[c1023f00] [c0242d5c] mount_block_root+0x108/0x24c
[c1023f50] [c02431c0] prepare_namespace+0xd0/0x210
[c1023f70] [c0242938] kernel_init+0x170/0x290
[c1023ff0] [c000d2dc] kernel_thread+0x44/0x60
Instruction dump:
80010014 38210010 7c0803a6 4e800020 7c000146 3d20c029 8129821c 2f890000
419e0010 38000002 7c0004ac 90090000 <48000000> 81230044 8009003c 70090008
Kernel panic - not syncing: Attempted to kill init!
Rebooting in 10 seconds..
I believe Clemens recently confirmed the same issue. Any ideas?
Robert
^ permalink raw reply
* Re: [PATCH] powerpc: Fix 44x Machine Check handling
From: Josh Boyer @ 2007-11-16 14:58 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev
In-Reply-To: <20071116074025.GA4741@lixom.net>
On Fri, 16 Nov 2007 01:40:25 -0600
Olof Johansson <olof@lixom.net> wrote:
> On Fri, Nov 16, 2007 at 06:21:06PM +1100, Benjamin Herrenschmidt wrote:
> > This removes the old CONFIG_440A which was a pain for multiplatform
> > kernel and wasn't set properly by default and replaces it with a
> > CPU feature. This makes Machine Check reporting work correctly on
> > my Ebony (440GP) board.
>
> I'm not sure I like this. It introduces another cpu feature flag,
> that we'll soon run out of if it's used to signify version info per
> implementation like this.
>
> 1) The SET_IVOR could be done from the cpu_setups for 440A instead
> (i.e. introduce one).
Yeah, that might work. I'm wondering if either method needs to take
arch/ppc into account, as the cputable is shared.
> 2) Please just move the machine check handlers out to individual ones
> instead of using the generic one. That way you don't need runtime checks
> between the two (they don't seem to share much of it as-is anyway).
Anton pinged me about cleaning that up a couple months ago. I have a
half-baked patch for it somewhere, but I agree having 4xx set a ppc_md
specific handler would be a good idea.
josh
^ permalink raw reply
* [BUG] 2.6.24-rc2-mm1 - kernel bug on nfs v4
From: Kamalesh Babulal @ 2007-11-16 14:15 UTC (permalink / raw)
To: Andrew Morton, LKML, linuxppc-dev, nfs, Andy Whitcroft,
Balbir Singh
Hi Andrew,
The kernel enters the xmon state while running the file system
stress on nfs v4 mounted partition.
0:mon> e
cpu 0x0: Vector: 300 (Data Access) at [c0000000dbd4f820]
pc: c000000000065be4: .__wake_up_common+0x44/0xe8
lr: c000000000069768: .__wake_up+0x54/0x88
sp: c0000000dbd4faa0
msr: 8000000000001032
dar: 0
dsisr: 40010000
current = 0xc0000000dfb6f680
paca = 0xc000000000574580
pid = 1865, comm = rpciod/0
0:mon> t
[c0000000dbd4fb50] c000000000069768 .__wake_up+0x54/0x88
[c0000000dbd4fc00] d00000000086b890 .nfs_sb_deactive+0x44/0x58 [nfs]
[c0000000dbd4fc80] d000000000872658 .nfs_free_unlinkdata+0x2c/0x74 [nfs]
[c0000000dbd4fd10] d000000000598510 .rpc_release_calldata+0x50/0x74 [sunrpc]
[c0000000dbd4fda0] c00000000008d960 .run_workqueue+0x10c/0x1f4
[c0000000dbd4fe50] c00000000008ec70 .worker_thread+0x118/0x138
[c0000000dbd4ff00] c0000000000939f4 .kthread+0x78/0xc4
[c0000000dbd4ff90] c00000000002b060 .kernel_thread+0x4c/0x68
0:mon> r
R00 = c000000000069768 R16 = 4000000001c00000
R01 = c0000000dbd4faa0 R17 = c0000000004410c0
R02 = c0000000006752d8 R18 = 0000000000000000
R03 = c0000000ace4ffc0 R19 = 000000000019c000
R04 = 0000000000000003 R20 = c00000000050af08
R05 = 0000000000000001 R21 = 000000000210af08
R06 = 0000000000000000 R22 = 000000000210b178
R07 = 0000000000000000 R23 = c00000000050b178
R08 = 0000000000000000 R24 = 0000000000000003
R09 = 0000000000000000 R25 = 0000000000000000
R10 = 0000000000000001 R26 = 0000000000000000
R11 = ffffffffffffffe8 R27 = c0000000ace4ffc0
R12 = 0000000000004000 R28 = 0000000000000001
R13 = c000000000574580 R29 = 0000000000000003
R14 = 0000000000000000 R30 = c00000000061bad8
R15 = c000000000442888 R31 = d0000000008baa50
pc = c000000000065be4 .__wake_up_common+0x44/0xe8
lr = c000000000069768 .__wake_up+0x54/0x88
msr = 8000000000001032 cr = 24000022
ctr = 80000000001af404 xer = 0000000000000002 trap = 300
dar = 0000000000000000 dsisr = 40010000
0:mon>
--
Thanks & Regards,
Kamalesh Babulal,
Linux Technology Center,
IBM, ISTL.
^ permalink raw reply
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