* Re: [PATCH] powerpc: Fix 44x Machine Check handling
From: Kumar Gala @ 2007-11-16 21:55 UTC (permalink / raw)
To: benh; +Cc: Olof Johansson, linuxppc-dev
In-Reply-To: <1195199141.28865.144.camel@pasglop>
On Nov 16, 2007, at 1:45 AM, Benjamin Herrenschmidt wrote:
>
> On Fri, 2007-11-16 at 18:41 +1100, Benjamin Herrenschmidt wrote:
>> On Fri, 2007-11-16 at 01:40 -0600, Olof Johansson wrote:
>>> I'm not sure I like this. It introduces another cpu feature flag,
>>> that we'll soon run out of if it's used to signify version info per
>>> implementation like this.
>>>
>>> 1) The SET_IVOR could be done from the cpu_setups for 440A instead
>>> (i.e. introduce one).
>>>
>>> 2) Please just move the machine check handlers out to individual
>>> ones
>>> instead of using the generic one. That way you don't need runtime
>>> checks
>>> between the two (they don't seem to share much of it as-is anyway).
>>>
>>> With the above two changes, you shouldn't need the feature bit any
>>> more.
>>
>> We can easily make the cpu features bigger ... But ok, I'll have a
>> look
>> at doing it the way you suggest.
>
> Note that first, I'd like to figure out if there are other relevant
> differences with 440A ... arch/ppc didn't list any and diff'ing PDFs
> is
> not fun but if people around here know, please speak up
I think it added isel support.
- k
^ permalink raw reply
* Re: [PATCH] powerpc: Fix 44x Machine Check handling
From: Kumar Gala @ 2007-11-16 21:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20071116072149.350ADDDDF4@ozlabs.org>
On Nov 16, 2007, at 1:21 AM, Benjamin Herrenschmidt wrote:
> This removes the old CONFIG_440A which was a pain for multiplatform
> kernel and wasn't set properly by default and replaces it with a
> CPU feature. This makes Machine Check reporting work correctly on
> my Ebony (440GP) board.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>
> Note: I'm only setting it for 440GX and EPx as the old code did,
> I haven't checked whether other new 440 chips such as SPe also
> need that bit set.
>
> arch/powerpc/kernel/cputable.c | 10 +++++-----
> arch/powerpc/kernel/head_44x.S | 11 ++++++-----
> arch/powerpc/kernel/traps.c | 19 ++++++++-----------
> arch/powerpc/platforms/44x/Kconfig | 5 -----
> include/asm-powerpc/cputable.h | 3 ++-
> include/asm-powerpc/reg_booke.h | 2 +-
> 6 files changed, 22 insertions(+), 28 deletions(-)
>
[snip]
> Index: linux-work/include/asm-powerpc/cputable.h
> ===================================================================
> --- linux-work.orig/include/asm-powerpc/cputable.h 2007-11-16
> 16:14:29.000000000 +1100
> +++ linux-work/include/asm-powerpc/cputable.h 2007-11-16
> 16:19:35.000000000 +1100
> @@ -138,6 +138,7 @@ extern void do_feature_fixups(unsigned l
> #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
> #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
> #define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
> +#define CPU_FTR_440A ASM_CONST(0x0000000004000000)
Can we be more specific about what this feature really means.
How about something like CPU_FTR_ENH_MCHCK or something like that.
- k
^ permalink raw reply
* Re: 85xx software reset problems from paulus.git
From: Kumar Gala @ 2007-11-16 21:46 UTC (permalink / raw)
To: robert lazarski; +Cc: linuxppc-embedded
In-Reply-To: <f87675ee0711161328u3127de3bjdd6341cdf11cd626@mail.gmail.com>
On Nov 16, 2007, at 3:28 PM, robert lazarski wrote:
> On Nov 16, 2007 3:44 PM, robert lazarski <robertlazarski@gmail.com>
> wrote:
>> On Nov 16, 2007 10:27 AM, Clemens Koller
>> <clemens.koller@anagramm.de> wrote:
>>> The SRESET# (pin AF20) is the soft reset input, causes
>>> an mcp assertion to the core.... (RTFM)
>>>
>>
>> That's what we are doing. The 85xx docs say "Soft reset. Causes a
>> machine check interrupt to the e500 core. Note that if the e500 core
>> is not configured to process machine check interrupts, the assertion
>> of SRESET causes a core checkstop. SRESET need not be asserted during
>> a hard reset."
>>
>
> Sorry for replying to myself, but thought I'd mention SRESET works
> fine on 85xx 2.6.23 , ie, the board resets after kernel panic. It
> doesn't work for me on 2.6.24rc2 .
What actual 85xx are you using?
- k
^ permalink raw reply
* Re: Latest paulus.git PCI broken on mpc8540?
From: Kumar Gala @ 2007-11-16 21:45 UTC (permalink / raw)
To: benh; +Cc: linuxppc-embedded
In-Reply-To: <1195247357.28865.178.camel@pasglop>
On Nov 16, 2007, at 3:09 PM, Benjamin Herrenschmidt wrote:
>
> On Fri, 2007-11-16 at 13:18 -0600, Kumar Gala wrote:
>>
>>
>> Well, for one the generic pci code will complain if its not able to
>> allocate the resource which is the true failure.
>>
>> I'm thinking maybe we just make these pr_debug() instead of standard
>> printk?
>
> I was thinking about changing the message to "cannot allocate initial
> resource, will reallocate" or something like that. That is, make it
> clear it's non fatal.
Yeah, something that on those lines would be good, and maybe mark them
KERN_WARNING instead of KERN_ERR.
- k
^ permalink raw reply
* Re: [POWERPC] [RFC] Fix 8xx tlbie definition
From: Kumar Gala @ 2007-11-16 21:29 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1195247189.28865.174.camel@pasglop>
On Nov 16, 2007, at 3:06 PM, Benjamin Herrenschmidt wrote:
>
> On Fri, 2007-11-16 at 11:28 -0600, Josh Boyer wrote:
>> Git commit e701d269aa28996f3502780951fe1b12d5d66b49 introduced an
>> incorrect
>> definition for _tlbie on PowerPC 8xx platforms. Only the address
>> should be
>> passed to the function. This patch corrects the definition of
>> _tlbie and the
>> related tlb flushing functions for 8xx.
>>
>> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
>
> That conflicts with the patch I posted to fix it differently (I kept
> the
> additional argument).
>
> Which one do we take ?
Let's make _tlbia/_tlbie consistent on all archs.
- k
^ permalink raw reply
* Re: 85xx software reset problems from paulus.git
From: robert lazarski @ 2007-11-16 21:28 UTC (permalink / raw)
Cc: linuxppc-embedded
In-Reply-To: <f87675ee0711161244h46c23d8byadaf1abb923b3971@mail.gmail.com>
On Nov 16, 2007 3:44 PM, robert lazarski <robertlazarski@gmail.com> wrote:
> On Nov 16, 2007 10:27 AM, Clemens Koller <clemens.koller@anagramm.de> wrote:
> > The SRESET# (pin AF20) is the soft reset input, causes
> > an mcp assertion to the core.... (RTFM)
> >
>
> That's what we are doing. The 85xx docs say "Soft reset. Causes a
> machine check interrupt to the e500 core. Note that if the e500 core
> is not configured to process machine check interrupts, the assertion
> of SRESET causes a core checkstop. SRESET need not be asserted during
> a hard reset."
>
Sorry for replying to myself, but thought I'd mention SRESET works
fine on 85xx 2.6.23 , ie, the board resets after kernel panic. It
doesn't work for me on 2.6.24rc2 .
Robert
^ permalink raw reply
* Re: Latest paulus.git PCI broken on mpc8540?
From: Benjamin Herrenschmidt @ 2007-11-16 21:20 UTC (permalink / raw)
To: Clemens Koller; +Cc: linuxppc-embedded
In-Reply-To: <473E084B.4080703@anagramm.de>
>
> I don't know much of the code, so, propably a stupid question:
> Can we avoid to do the initial resource allocation, when it's known to fail?
>
> It seems to me like things are done twice here:
> 1. try
> 2. reallocate
> 3. retry
Well, we don't know it's going to fail until we try :-)
Ben.
^ permalink raw reply
* Re: Latest paulus.git PCI broken on mpc8540?
From: Clemens Koller @ 2007-11-16 21:14 UTC (permalink / raw)
To: benh; +Cc: linuxppc-embedded
In-Reply-To: <1195247357.28865.178.camel@pasglop>
Hi, Ben!
Benjamin Herrenschmidt schrieb:
> On Fri, 2007-11-16 at 13:18 -0600, Kumar Gala wrote:
>>
>> Well, for one the generic pci code will complain if its not able to
>> allocate the resource which is the true failure.
>>
>> I'm thinking maybe we just make these pr_debug() instead of standard
>> printk?
>
> I was thinking about changing the message to "cannot allocate initial
> resource, will reallocate" or something like that. That is, make it
> clear it's non fatal.
I don't know much of the code, so, propably a stupid question:
Can we avoid to do the initial resource allocation, when it's known to fail?
It seems to me like things are done twice here:
1. try
2. reallocate
3. retry
Regards,
--
Clemens Koller
_______________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Str. 45/1
81379 Muenchen
Germany
http://www.anagramm-technology.com
Phone: +49-89-741518-50
Fax: +49-89-741518-19
^ permalink raw reply
* Re: [POWERPC] [RFC] Fix 8xx tlbie definition
From: Benjamin Herrenschmidt @ 2007-11-16 21:06 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20071116112822.37a238c0@weaponx>
On Fri, 2007-11-16 at 11:28 -0600, Josh Boyer wrote:
> Git commit e701d269aa28996f3502780951fe1b12d5d66b49 introduced an incorrect
> definition for _tlbie on PowerPC 8xx platforms. Only the address should be
> passed to the function. This patch corrects the definition of _tlbie and the
> related tlb flushing functions for 8xx.
>
> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
That conflicts with the patch I posted to fix it differently (I kept the
additional argument).
Which one do we take ?
Ben.
^ permalink raw reply
* Re: Latest paulus.git PCI broken on mpc8540?
From: Benjamin Herrenschmidt @ 2007-11-16 21:09 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-embedded
In-Reply-To: <A4E1A594-5A31-4EFE-B4F9-E4B24F9207F7@kernel.crashing.org>
On Fri, 2007-11-16 at 13:18 -0600, Kumar Gala wrote:
>
>
> Well, for one the generic pci code will complain if its not able to
> allocate the resource which is the true failure.
>
> I'm thinking maybe we just make these pr_debug() instead of standard
> printk?
I was thinking about changing the message to "cannot allocate initial
resource, will reallocate" or something like that. That is, make it
clear it's non fatal.
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Fix 44x Machine Check handling
From: Benjamin Herrenschmidt @ 2007-11-16 21:03 UTC (permalink / raw)
To: Josh Boyer; +Cc: Olof Johansson, linuxppc-dev
In-Reply-To: <20071116085813.3cebed79@weaponx>
On Fri, 2007-11-16 at 08:58 -0600, Josh Boyer wrote:
> > 2) Please just move the machine check handlers out to individual
> ones
> > instead of using the generic one. That way you don't need runtime
> checks
> > between the two (they don't seem to share much of it as-is anyway).
>
> Anton pinged me about cleaning that up a couple months ago. I have a
> half-baked patch for it somewhere, but I agree having 4xx set a ppc_md
> specific handler would be a good idea.
No need. The 2 asm implementation can branch to 2 different C functions
and the IVOR will be set to the right one.
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Add xmon function to dump 44x TLB
From: Benjamin Herrenschmidt @ 2007-11-16 21:04 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <5581b33006faf83955d35e9e9a091272@kernel.crashing.org>
On Fri, 2007-11-16 at 17:09 +0100, Segher Boessenkool wrote:
> >> +#ifdef CONFIG_44x
> >> +static void dump_tlb_44x(void);
> >> +#endif
> >
> > No need to #ifdef this...
> >
> >> +#ifdef CONFIG_44x
> >> +static void dump_tlb_44x(void)
> >> +{
> >
> > ...or this.
>
> Erm actually, that last one would give you a compiler warning ("function
> defined but not used"), unless you convert the point where it is used to
> a plain "if" too -- probably not worth it until we have 32-bit
> multiplatform
> support :-)
We do have multiplatform support but not accross CPU families :-)
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Add xmon function to dump 44x TLB
From: Benjamin Herrenschmidt @ 2007-11-16 21:03 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: linuxppc-dev
In-Reply-To: <4ccc68f867a65d70f5d1e3ee946de4d1@kernel.crashing.org>
On Fri, 2007-11-16 at 16:54 +0100, Segher Boessenkool wrote:
> > +#ifdef CONFIG_44x
> > +static void dump_tlb_44x(void);
> > +#endif
>
> No need to #ifdef this...
>
> > +#ifdef CONFIG_44x
> > +static void dump_tlb_44x(void)
> > +{
>
> ...or this.
I don't want to require binutils to understand the 44x TLB ops
Ben.
^ permalink raw reply
* Re: 85xx software reset problems from paulus.git
From: robert lazarski @ 2007-11-16 20:44 UTC (permalink / raw)
Cc: linuxppc-embedded
In-Reply-To: <473DB6DF.9010804@anagramm.de>
On Nov 16, 2007 10:27 AM, Clemens Koller <clemens.koller@anagramm.de> wrote:
> Hello, Robert!
>
> robert lazarski schrieb:
> > Hi all, on my custom 85xx board I can't do a soft reset. I'm using
> > u-boot 1.3rc3 that has the latest cpu/mpc85xx/cpu.c patch to fix some
> > type of reset problem. When I press the software reset button on my
> > board after my nfs kernel panic, I get this:
>
> Please define "software reset button" in your case. :-)
> I consider a "button" clearly as hardware.
>
I mean a hardware button that calls SRESET , ie, Soft reset machine check.
<snip>
>
> The SRESET# (pin AF20) is the soft reset input, causes
> an mcp assertion to the core.... (RTFM)
>
That's what we are doing. The 85xx docs say "Soft reset. Causes a
machine check interrupt to the e500 core. Note that if the e500 core
is not configured to process machine check interrupts, the assertion
of SRESET causes a core checkstop. SRESET need not be asserted during
a hard reset."
Is the 85xx kernel "not configured to process machine check
interrupts" ? Do I need to do that myself in my boards restart
function via the special registers? Is there code already for this?
Robert
^ permalink raw reply
* Re: [PATCH] [POWERPC] Add SPRN for Embedded registers specified in PowerISA 2.04
From: Kumar Gala @ 2007-11-16 20:09 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev
In-Reply-To: <20071116200510.GA18481@lixom.net>
On Nov 16, 2007, at 2:05 PM, Olof Johansson wrote:
> Hi,
>
>
> On Fri, Nov 16, 2007 at 01:59:03PM -0600, Kumar Gala wrote:
>> +#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
>> +#define SPRN_SPRG9 0x25D /* Special Purpose Register General 8 */
>
> Cut and paste error in comment :)
thanks, git-commit --amend fixed ;)
- k
^ permalink raw reply
* Re: [PATCH] [POWERPC] Add SPRN for Embedded registers specified in PowerISA 2.04
From: Olof Johansson @ 2007-11-16 20:05 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0711161358280.24588@blarg.am.freescale.net>
Hi,
On Fri, Nov 16, 2007 at 01:59:03PM -0600, Kumar Gala wrote:
> +#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
> +#define SPRN_SPRG9 0x25D /* Special Purpose Register General 8 */
Cut and paste error in comment :)
-Olof
^ permalink raw reply
* [PATCH] [POWERPC] Add SPRN for Embedded registers specified in PowerISA 2.04
From: Kumar Gala @ 2007-11-16 19:59 UTC (permalink / raw)
To: linuxppc-dev
* Added SPRN for new architectural features added for embedded:
- Alternate Time Base (ATB, ATBL, ATBU)
- Doorbell Interrupts (IVOR36, IVOR37)
- SPRG8/9
- External Proxy (EPR)
- External PID load/store (EPLC, EPSC)
* Added BUCSR for Freescale Embedded Processors
* Moved around MAS7 so its in numeric order
---
as normal, this is my git tree for 2.6.25
include/asm-powerpc/reg_booke.h | 13 ++++++++++++-
1 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 8fdc2b4..d596439 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -123,16 +123,23 @@
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
+#define SPRN_ATB 0x20E /* Alternate Time Base */
+#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
+#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
+#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
+#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
#define SPRN_MCSR 0x23C /* Machine Check Status Register */
#define SPRN_MCAR 0x23D /* Machine Check Address Register */
#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
+#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
+#define SPRN_SPRG9 0x25D /* Special Purpose Register General 8 */
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
@@ -140,15 +147,18 @@
#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
-#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27A /* Process ID Register 2 */
#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
+#define SPRN_EPR 0x2BE /* External Proxy Register */
#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
+#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
+#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
+#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
#define SPRN_SLER 0x3BB /* Little-endian real mode */
@@ -159,6 +169,7 @@
#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
+#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
#define SPRN_SVR 0x3FF /* System Version Register */
--
1.5.3.4
^ permalink raw reply related
* Re: [PATCH] [POWERPC] 4xx: Use virtual PVR value to init FPU on arch/ppc 440EP
From: Josh Boyer @ 2007-11-16 19:23 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <96AAE1CB-3F7F-4231-AD52-01F358E01594@kernel.crashing.org>
On Fri, 16 Nov 2007 13:20:09 -0600
Kumar Gala <galak@kernel.crashing.org> wrote:
>
> On Nov 16, 2007, at 11:29 AM, Josh Boyer wrote:
>
> > This fixes arch/ppc 440EP platforms to setup the FPU correctly. A
> > virtual
> > PVR is used, as 440GR platforms share an identical hardware PVR
> > value and do
> > not have an FPU.
> >
> > Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
> > Index: linux-2.6/arch/ppc/kernel/setup.c
> > ===================================================================
> > --- linux-2.6.orig/arch/ppc/kernel/setup.c
> > +++ linux-2.6/arch/ppc/kernel/setup.c
> > @@ -312,7 +312,14 @@ early_init(int r3, int r4, int r5)
> > * Identify the CPU type and fix up code sections
> > * that depend on which cpu we have.
> > */
> > +#if defined(CONFIG_440EP) && defined(CONFIG_PPC_FPU)
> > + /* We pass the virtual PVR here for 440EP as 440EP and 440GR have
> > + * identical PVRs and there is no reliable way to check for the FPU
> > + */
> > + spec = identify_cpu(offset, (mfspr(SPRN_PVR) | 0x8));
> > +#else
> > spec = identify_cpu(offset, mfspr(SPRN_PVR));
> > +#endif
> > do_feature_fixups(spec->cpu_features,
> > PTRRELOC(&__start___ftr_fixup),
> > PTRRELOC(&__stop___ftr_fixup));
>
> Are we really adding support for new processors to arch/ppc?
No. This is to continue to support 440EP FPU in arch/ppc. Commit
d1dfc35d3a62 switched the cputable around for EP(x)/GR(x) and arch/ppc wasn't fixed up. So without the above patch, 440EP gets detected as 440GR and the FPU isn't initialized properly.
josh
^ permalink raw reply
* Re: [PATCH] [POWERPC] 4xx: Use virtual PVR value to init FPU on arch/ppc 440EP
From: Kumar Gala @ 2007-11-16 19:20 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20071116112956.0f1ca5b1@weaponx>
On Nov 16, 2007, at 11:29 AM, Josh Boyer wrote:
> This fixes arch/ppc 440EP platforms to setup the FPU correctly. A
> virtual
> PVR is used, as 440GR platforms share an identical hardware PVR
> value and do
> not have an FPU.
>
> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
> Index: linux-2.6/arch/ppc/kernel/setup.c
> ===================================================================
> --- linux-2.6.orig/arch/ppc/kernel/setup.c
> +++ linux-2.6/arch/ppc/kernel/setup.c
> @@ -312,7 +312,14 @@ early_init(int r3, int r4, int r5)
> * Identify the CPU type and fix up code sections
> * that depend on which cpu we have.
> */
> +#if defined(CONFIG_440EP) && defined(CONFIG_PPC_FPU)
> + /* We pass the virtual PVR here for 440EP as 440EP and 440GR have
> + * identical PVRs and there is no reliable way to check for the FPU
> + */
> + spec = identify_cpu(offset, (mfspr(SPRN_PVR) | 0x8));
> +#else
> spec = identify_cpu(offset, mfspr(SPRN_PVR));
> +#endif
> do_feature_fixups(spec->cpu_features,
> PTRRELOC(&__start___ftr_fixup),
> PTRRELOC(&__stop___ftr_fixup));
Are we really adding support for new processors to arch/ppc?
- k
^ permalink raw reply
* Re: Latest paulus.git PCI broken on mpc8540?
From: Kumar Gala @ 2007-11-16 19:18 UTC (permalink / raw)
To: benh; +Cc: linuxppc-embedded
In-Reply-To: <1195191333.28865.140.camel@pasglop>
On Nov 15, 2007, at 11:35 PM, Benjamin Herrenschmidt wrote:
>
> On Thu, 2007-11-15 at 22:37 -0600, Kumar Gala wrote:
>>> PCI: Probing PCI hardware
>>> PCI: Cannot allocate resource region 0 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 1 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 2 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 3 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 4 of device 0000:00:12.0
>>> PCI: Cannot allocate resource region 0 of device 0000:00:14.0
>>> PCI: Cannot allocate resource region 2 of device 0000:00:14.0
>>
>> this isn't really an error. Its more of a warning, the kernel will
>> try and allocate these later and I'm guessing based on what you are
>> seeing it succeeded.
>>
>> Benh, can we possibly change these messages in pci_32.c?
>
> Heh, well, I've been working on 44x PCI lately and got annoyed by the
> exact same messages, though I'm still pondering what would be a better
> replacement.
Well, for one the generic pci code will complain if its not able to
allocate the resource which is the true failure.
I'm thinking maybe we just make these pr_debug() instead of standard
printk?
- k
^ permalink raw reply
* Re: [PATCH] remove dead MAC_ADBKEYCODES
From: Geert Uytterhoeven @ 2007-11-16 15:09 UTC (permalink / raw)
To: Dmitry Torokhov
Cc: Stanislav Brabec, linux-input, Linux/m68k, Linux/PPC Development
In-Reply-To: <d120d5000711160525p225f4b4o30eab6d01b289cda@mail.gmail.com>
On Fri, 16 Nov 2007, Dmitry Torokhov wrote:
> On Nov 16, 2007 4:44 AM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > Wrong mailing list ;-)
> >
> > On Thu, 15 Nov 2007, Stanislav Brabec wrote:
> > > It seems, that current kernel source code contains no traces of
> > > MAC_ADBKEYCODES and no reference to keyboard_sends_linux_keycodes any
> > > more.
> > >
> > > Attached patch removes them from configuration files.
> > >
> > > Signed-off-by: Stanislav Brabec <sbrabec@suse.cz>
> >
> > Acked-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
> >
>
> Geert, are you going to push it through your tree?
Yes, I'll add it to my queue for 2.6.25.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: Kexec on powerpc
From: Dale Farnsworth @ 2007-11-16 18:48 UTC (permalink / raw)
To: marco.stornelli, Linuxppc-embedded
In-Reply-To: <10602.129.192.97.5.1195132467.squirrel@nausicaa2.coritel.it>
On Thu, Nov 15, 2007 at 01:14:27PM +0000, marco.stornelli@coritel.it wrote:
> I'm using the latest kernel and I need the kexec support for 85xx
> processor. When I use the menuconfig with ARCH=ppc and the 85xx and
> e500 support, I have the kexec support, but when I use ARCH=powerpc I
> haven't it, but I'm selecting the same processor!! Is it a bug in
> kconfig? Somebody can explain to me why?
I don't think kexec works for ppc-32 arch/powerpc at the present.
We have been working on kexec/kdump support for 32-bit arch/powerpc.
It requires changes both to the kernel and to the kexec-tools package.
I plan to post a first round of patches to linuxppc-dev early next week.
-Dale Farnsworth
^ permalink raw reply
* Configuration of i2c on 8248 (cpm2) help
From: Alan Bennett @ 2007-11-16 18:44 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 3108 bytes --]
I'm working to adapt some work by Jochen Friedrich to support CPM2 i2c
devices. It appears I have the bus loaded and think I am configuring
it properly, but my results tell me different. I see no messages when
I attach a i2c monitor after u-boot loads.
Can anyone spot what is going wrong based on the following information
and the resulting output? Does this look proper for a successful
configuration of the cpm2 i2c bus?
i2c-cpm: iip e0008afc, dp_addr 0x240
i2c-cpm: iic_tbase 576, iic_rbase 608
Any insight would be greatly appreciated.
-Alan
My Device tree entry:
i2c@11860 {
compatible = "fsl,mpc8248-i2c",
"fsl,cpm2-i2c",
"fsl,cpm-i2c";
reg = <11860 20 8afc 30>;
interrupts = <1 8>;
interrupt-parent = <&PIC>;
fsl,cpm-command = <29600000>;
};
... and then later:
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <80 1f80 9800 800>;
};
};
dump of 0xe0008afc (my immr_base=0xe0000000) at boot
e0008afc : 02600240 10100201 00000000 00000000
e0008b0c : 02600000 00000000 00000000 00000000
e0008b1c : 02400000 00000000 78c7ebaf bdefeab1
Probe debug results:
i2c-cpm: cpm_iic_init()
i2c-cpm: iip e0008afc, dp_addr 0x240
i2c-cpm: iic_tbase 576, iic_rbase 608
Log after modprobe:
modprobe i2c-dev
Jan 1 00:08:02 192 kernel: i2c /dev entries driver
Jan 1 00:08:02 192 kernel: i2c-core: driver [dev_driver] registered
Jan 1 00:08:02 192 kernel: i2c-dev: adapter [i2c-cpm] registered as minor 0
Log entries after trying an i2cset: (NOTE: sometimes it hangs doing this)
i2cset 0 0x41 0x1 0xff b
cpm_xfer:478
cpm_parse_message:329
kernel: i2c-adapter i2c-0: ioctl, cmd=0x720, arg=0xbfecaa0c
kernel: i2c-adapter i2c-0: master_xfer[0] W, addr=0x41, len2
kernel: cpm_xfer:478
kernel: i2c-adapter i2c-0: i2c-algo-cpm.o: R: 0 T: 0
kernel: cpm_parse_message:329
kernel: i2c-adapter i2c-0: cpm_iic_write(abyte=0x82)
kernel: i2c-adapter i2c-0: tx sc 0 bc00
kernel: i2c-adapter i2c-0: test ready.
kernel: i2c-adapter i2c-0: not ready.
cpm_xfer:478
cpm_parse_message:329
cpm_parse_message:329
kernel: i2c-adapter i2c-0: force_close()
kernel: i2c-adapter i2c-0: IIC read: timeout!
kernel: i2c-adapter i2c-0: ioctl, cmd=0x720, arg=0xbfecaa0c
kernel: i2c-adapter i2c-0: master_xfer[0] W, addr=0x41, len1
kernel: i2c-adapter i2c-0: master_xfer[1] R, addr=0x41, len1
kernel: cpm_xfer:478
kernel: i2c-adapter i2c-0: i2c-algo-cpm.o: R: 0 T: 0
kernel: cpm_parse_message:329
kernel: i2c-adapter i2c-0: cpm_iic_write(abyte=0x82)
kernel: i2c-adapter i2c-0: tx sc 0 9400
kernel: i2c-adapter i2c-0: i2c-algo-cpm.o: R: 0 T: 1
kernel: cpm_parse_message:329
kernel: i2c-adapter i2c-0: cpm_iic_read(abyte=0x83)
kernel: i2c-adapter i2c-0: test ready.
kernel: i2c-adapter i2c-0: not ready.
kernel: i2c-adapter i2c-0: force_close()
kernel: i2c-adapter i2c-0: IIC read: timeout!
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: i2c-cpm.c --]
[-- Type: text/x-csrc; name=i2c-cpm.c, Size: 17704 bytes --]
/*
* Freescale CPM1/CPM2 I2C interface.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
*
* moved into proper i2c interface;
* Brad Parker (brad@heeltoe.com)
*
* (C) 2007 Montavista Software, Inc.
* Vitaly Bordug <vitb@kernel.crashing.org>
*
* RPX lite specific parts of the i2c interface
* Update: There actually isn't anything RPXLite-specific about this module.
* This should work for most any CPM board. The console messages have been
* changed to eliminate RPXLite references.
*
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* moved into proper i2c interface; separated out platform specific
* parts into i2c-8xx.c
* Brad Parker (brad@heeltoe.com)
*
* Parts from dbox2_i2c.c (cvs.tuxbox.org)
* (C) 2000-2001 Tmbinc, Gillem (htoa@gmx.net)
*
* (C) 2007 Montavista Software, Inc.
* Vitaly Bordug <vitb@kernel.crashing.org>
*
* Converted to of_platform_device. Renamed to i2c-cpm.c.
* (C) 2007 Jochen Friedrich <jochen@scram.de>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/stddef.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/time.h>
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#ifdef CONFIG_CPM2
#include <asm/cpm2.h>
#else
#include <asm/commproc.h>
#endif
/* Try to define this if you have an older CPU (earlier than rev D4) */
/* However, better use a GPIO based bitbang driver in this case :/ */
#undef I2C_CHIP_ERRATA
#define CPM_MAX_READ 513
#define CPM_MAXBD 4
struct cpm_i2c {
char *base;
struct of_device *ofdev;
struct i2c_adapter adap;
uint dp_addr;
int reloc;
int irq;
int cp_command;
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c;
#else
i2c8xx_t __iomem *i2c;
#endif
iic_t __iomem *iip;
wait_queue_head_t iic_wait;
struct mutex iic_mutex; /* Protects I2C CPM */
u_char *txbuf[CPM_MAXBD];
u_char *rxbuf[CPM_MAXBD];
u32 txdma[CPM_MAXBD];
u32 rxdma[CPM_MAXBD];
};
static irqreturn_t cpm_iic_interrupt(int irq, void *dev_id)
{
struct i2c_adapter *adap;
struct cpm_i2c *cpm;
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c;
#else
i2c8xx_t __iomem *i2c;
#endif
int i;
printk ("%s:%d\n", __FUNCTION__,__LINE__);
adap = (struct i2c_adapter *) dev_id;
cpm = i2c_get_adapdata(adap);
i2c = cpm->i2c;
/* Clear interrupt.
*/
i = in_8(&i2c->i2c_i2cer);
out_8(&i2c->i2c_i2cer, i);
dev_dbg(&adap->dev, "Interrupt: %x\n", i);
/* Get 'me going again.
*/
wake_up_interruptible(&cpm->iic_wait);
return i ? IRQ_HANDLED : IRQ_NONE;
}
static void cpm_reset_iic_params(struct cpm_i2c *cpm)
{
iic_t __iomem *iip = cpm->iip;
/* Set up the IIC parameters in the parameter ram.
*/
out_be16(&iip->iic_tbase, cpm->dp_addr);
out_be16(&iip->iic_rbase, cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
#ifdef CONFIG_CPM2
out_8(&iip->iic_tfcr, CPMFCR_EB);
out_8(&iip->iic_rfcr, CPMFCR_EB);
#else
out_8(&iip->iic_tfcr, SMC_EB);
out_8(&iip->iic_rfcr, SMC_EB);
#endif
out_be16(&iip->iic_mrblr, CPM_MAX_READ);
out_be32(&iip->iic_rstate, 0);
out_be32(&iip->iic_rdp, 0);
out_be16(&iip->iic_rbptr, in_be16(&iip->iic_rbase));
out_be16(&iip->iic_rbc, 0);
out_be32(&iip->iic_rxtmp, 0);
out_be32(&iip->iic_tstate, 0);
out_be32(&iip->iic_tdp, 0);
out_be16(&iip->iic_tbptr, in_be16(&iip->iic_tbase));
out_be16(&iip->iic_tbc, 0);
out_be32(&iip->iic_txtmp, 0);
}
static int cpm_iic_init(struct i2c_adapter *adap)
{
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
iic_t __iomem *iip = cpm->iip;
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c = cpm->i2c;
#else
i2c8xx_t __iomem *i2c = cpm->i2c;
#endif
unsigned char brg;
int ret, i, res;
#ifdef CONFIG_CPM2
u32 v;
#else
u16 v;
#endif
printk("i2c-cpm: cpm_iic_init()\n");
ret = 0;
init_waitqueue_head(&cpm->iic_wait);
mutex_init(&cpm->iic_mutex);
/* Initialize Tx/Rx parameters.
*/
cpm_reset_iic_params(cpm);
printk("i2c-cpm: iip %p, dp_addr 0x%x\n", cpm->iip, cpm->dp_addr);
printk("i2c-cpm: iic_tbase %d, iic_rbase %d\n",
in_be16(&iip->iic_tbase), in_be16(&iip->iic_rbase));
v = cpm->cp_command | (CPM_CR_INIT_TRX << 8) | CPM_CR_FLG;
#ifdef CONFIG_CPM2
out_be32(&cpmp->cp_cpcr, v);
res = wait_event_timeout(cpm->iic_wait,
!(in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG), HZ * 10);
#else
out_be16(&cpmp->cp_cpcr, v);
res = wait_event_timeout(cpm->iic_wait,
!(in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG), HZ * 10);
#endif
if (!res)
return -EIO;
/* Select an invalid address. Just make sure we don't use loopback mode
*/
out_8(&i2c->i2c_i2add, 0xfe);
/* Make clock run at 60 kHz.
*/
brg = get_brgfreq() / (32 * 2 * 60000) - 3;
out_8(&i2c->i2c_i2brg, brg);
out_8(&i2c->i2c_i2mod, 0x00);
out_8(&i2c->i2c_i2com, 0x01); /* Master mode */
/* Disable interrupts.
*/
out_8(&i2c->i2c_i2cmr, 0);
out_8(&i2c->i2c_i2cer, 0xff);
/* Allocate TX and RX buffers */
for (i = 0; i < CPM_MAXBD; i++) {
cpm->rxbuf[i] = dma_alloc_coherent(
NULL, CPM_MAX_READ + 1, &cpm->rxdma[i], GFP_KERNEL);
if (!cpm->rxbuf[i]) {
ret = -ENOMEM;
goto out;
}
cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(
NULL, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
if (!cpm->txbuf[i]) {
ret = -ENOMEM;
goto out;
}
}
/* Install interrupt handler.
*/
ret = request_irq(cpm->irq, cpm_iic_interrupt, 0, "cpm_i2c", adap);
if (ret)
goto out;
return 0;
out:
for (i = 0; i < CPM_MAXBD; i++) {
if (cpm->rxbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1,
cpm->rxbuf[i], cpm->rxdma[i]);
if (cpm->txbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1,
cpm->txbuf[i], cpm->txdma[i]);
}
return ret;
}
static int cpm_iic_shutdown(struct i2c_adapter *adap)
{
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
int i;
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c = cpm->i2c;
#else
i2c8xx_t __iomem *i2c = cpm->i2c;
#endif
/* Shut down IIC.
*/
out_8(&i2c->i2c_i2mod, in_8(&i2c->i2c_i2mod) | ~1);
out_8(&i2c->i2c_i2cmr, 0);
out_8(&i2c->i2c_i2cer, 0xff);
for (i = 0; i < CPM_MAXBD; i++) {
if (cpm->rxbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1,
cpm->rxbuf[i], cpm->rxdma[i]);
if (cpm->txbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1,
cpm->txbuf[i], cpm->txdma[i]);
}
free_irq(cpm->irq, adap);
return 0;
}
#define BD_SC_NAK (0x0004) /* NAK - did not respond */
#define BD_SC_OV (0x0002) /* OV - receive overrun */
#define CPM_CR_CLOSE_RXBD (0x0007)
static void force_close(struct i2c_adapter *adap)
{
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c = cpm->i2c;
u32 v;
#else
i2c8xx_t __iomem *i2c = cpm->i2c;
u16 v;
#endif
dev_dbg(&adap->dev, "force_close()\n");
v = cpm->cp_command | (CPM_CR_CLOSE_RXBD << 8) | CPM_CR_FLG;
#ifdef CONFIG_CPM2
out_be32(&cpmp->cp_cpcr, v);
wait_event_timeout(cpm->iic_wait,
!(in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG), HZ * 5);
#else
out_be16(&cpmp->cp_cpcr, v);
wait_event_timeout(cpm->iic_wait,
!(in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG), HZ * 5);
#endif
out_8(&i2c->i2c_i2cmr, 0x00); /* Disable all interrupts */
out_8(&i2c->i2c_i2cer, 0xff);
}
static void cpm_parse_message(struct i2c_adapter *adap, struct i2c_msg *pmsg,
int num, int tx, int rx)
{
cbd_t *tbdf, *rbdf;
u_char addr;
u_char *tb;
u_char *rb;
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
iic_t __iomem *iip = cpm->iip;
int i, dscan;
printk ("%s:%d\n", __FUNCTION__,__LINE__);
tbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_tbase));
rbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_rbase));
/* This chip can't do zero length writes. However, the i2c core uses
them to scan for devices. The best we can do is to convert them
into 1 byte reads */
dscan = ((pmsg->len == 0) && (num == 1));
addr = pmsg->addr << 1;
if ((pmsg->flags & I2C_M_RD) || dscan)
addr |= 1;
tb = cpm->txbuf[tx];
rb = cpm->rxbuf[rx];
/* Align read buffer */
rb = (u_char *) (((ulong) rb + 1) & ~1);
if ((pmsg->flags & I2C_M_RD) || dscan) {
/* To read, we need an empty buffer of the proper length.
* All that is used is the first byte for address, the remainder
* is just used for timing (and doesn't really have to exist).
*/
tb[0] = addr; /* Device address byte w/rw flag */
dev_dbg(&adap->dev, "cpm_iic_read(abyte=0x%x)\n", addr);
tbdf[tx].cbd_bufaddr = cpm->txdma[tx];
if (dscan)
tbdf[tx].cbd_datlen = 2;
else
tbdf[tx].cbd_datlen = pmsg->len + 1;
tbdf[tx].cbd_sc = 0;
if (!(pmsg->flags & I2C_M_NOSTART))
tbdf[tx].cbd_sc |= BD_IIC_START;
if (tx + 1 == num)
tbdf[tx].cbd_sc |= BD_SC_LAST | BD_SC_WRAP;
rbdf[rx].cbd_datlen = 0;
rbdf[rx].cbd_bufaddr = ((cpm->rxdma[rx] + 1) & ~1);
rbdf[rx].cbd_sc = BD_SC_EMPTY | BD_SC_INTRPT;
if (rx + 1 == CPM_MAXBD)
tbdf[rx].cbd_sc |= BD_SC_WRAP;
eieio();
tbdf[tx].cbd_sc |= BD_SC_READY;
} else {
tb[0] = addr; /* Device address byte w/rw flag */
for (i = 0; i < pmsg->len; i++)
tb[i+1] = pmsg->buf[i];
dev_dbg(&adap->dev, "cpm_iic_write(abyte=0x%x)\n", addr);
tbdf[tx].cbd_bufaddr = cpm->txdma[tx];
tbdf[tx].cbd_datlen = pmsg->len + 1;
tbdf[tx].cbd_sc = 0;
if (!(pmsg->flags & I2C_M_NOSTART))
tbdf[tx].cbd_sc |= BD_IIC_START;
if (tx + 1 == num)
tbdf[tx].cbd_sc |= BD_SC_LAST | BD_SC_WRAP;
eieio();
tbdf[tx].cbd_sc |= BD_SC_READY | BD_SC_INTRPT;
dev_dbg(&adap->dev, "tx sc %d %04x\n",
tx, tbdf[tx].cbd_sc);
}
}
static int cpm_check_message(struct i2c_adapter *adap, struct i2c_msg *pmsg,
int tx, int rx)
{
cbd_t *tbdf, *rbdf;
u_char *tb;
u_char *rb;
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
iic_t __iomem *iip = cpm->iip;
int i;
printk ("%s:%d\n", __FUNCTION__,__LINE__);
tbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_tbase));
rbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_rbase));
tb = cpm->txbuf[tx];
rb = cpm->rxbuf[rx];
/* Align read buffer */
rb = (u_char *) (((uint) rb + 1) & ~1);
if (pmsg->flags & I2C_M_RD) {
dev_dbg(&adap->dev, "rx sc %04x, rx sc %04x\n",
tbdf[tx].cbd_sc, rbdf[rx].cbd_sc);
if (tbdf[tx].cbd_sc & BD_SC_NAK) {
dev_dbg(&adap->dev, "IIC read; no ack\n");
if (pmsg->flags & I2C_M_IGNORE_NAK)
return 0;
else
return -EIO;
}
if (rbdf[rx].cbd_sc & BD_SC_EMPTY) {
dev_dbg(&adap->dev,
"IIC read; complete but rbuf empty\n");
return -EREMOTEIO;
}
if (rbdf[rx].cbd_sc & BD_SC_OV) {
dev_dbg(&adap->dev, "IIC read; Overrun\n");
return -EREMOTEIO;
}
for (i = 0; i < pmsg->len; i++)
pmsg->buf[i] = rb[i];
} else {
dev_dbg(&adap->dev, "tx sc %d %04x\n", tx, tbdf[tx].cbd_sc);
if (tbdf[tx].cbd_sc & BD_SC_NAK) {
dev_dbg(&adap->dev, "IIC write; no ack\n");
if (pmsg->flags & I2C_M_IGNORE_NAK)
return 0;
else
return -EIO;
}
}
return 0;
}
static int cpm_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
struct cpm_i2c *cpm = i2c_get_adapdata(adap);
#ifdef CONFIG_CPM2
i2c_cpm2_t __iomem *i2c = cpm->i2c;
#else
i2c8xx_t __iomem *i2c = cpm->i2c;
#endif
iic_t __iomem *iip = cpm->iip;
struct i2c_msg *pmsg, *rmsg;
int ret, i;
int tptr;
int rptr;
cbd_t *tbdf, *rbdf;
printk ("%s:%d\n", __FUNCTION__,__LINE__);
if (num > CPM_MAXBD)
return -EINVAL;
/* Check if we have any oversized READ requests */
for (i = 0; i < num; i++) {
pmsg = &msgs[i];
if (pmsg->len >= CPM_MAX_READ)
return -EINVAL;
}
mutex_lock(&cpm->iic_mutex);
/* Reset to use first buffer */
out_be16(&iip->iic_rbptr, in_be16(&iip->iic_rbase));
out_be16(&iip->iic_tbptr, in_be16(&iip->iic_tbase));
tbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_tbase));
rbdf = (cbd_t *) cpm_muram_addr(in_be16(&iip->iic_rbase));
tptr = 0;
rptr = 0;
while (tptr < num) {
pmsg = &msgs[tptr];
dev_dbg(&adap->dev, "i2c-algo-cpm.o: " "R: %d T: %d\n",
rptr, tptr);
cpm_parse_message(adap, pmsg, num, tptr, rptr);
if (pmsg->flags & I2C_M_RD)
rptr++;
tptr++;
}
/* Start transfer now */
/* Chip bug, set enable here */
out_8(&i2c->i2c_i2cmr, 0x13); /* Enable some interupts */
out_8(&i2c->i2c_i2cer, 0xff);
out_8(&i2c->i2c_i2mod, in_8(&i2c->i2c_i2mod) | 1); /* Enable */
/* Begin transmission */
out_8(&i2c->i2c_i2com, in_8(&i2c->i2c_i2com) | 0x80);
tptr = 0;
rptr = 0;
while (tptr < num) {
/* Check for outstanding messages */
dev_dbg(&adap->dev, "test ready.\n");
if (!(tbdf[tptr].cbd_sc & BD_SC_READY)) {
dev_dbg(&adap->dev, "ready.\n");
rmsg = &msgs[tptr];
ret = cpm_check_message(adap, rmsg, tptr, rptr);
tptr++;
if (rmsg->flags & I2C_M_RD)
rptr++;
if (ret) {
force_close(adap);
mutex_unlock(&cpm->iic_mutex);
return ret;
}
} else {
dev_dbg(&adap->dev, "not ready.\n");
ret = wait_event_interruptible_timeout(cpm->iic_wait,
!(tbdf[tptr].cbd_sc & BD_SC_READY), 1 * HZ);
if (ret == 0) {
force_close(adap);
dev_dbg(&adap->dev, "IIC read: timeout!\n");
mutex_unlock(&cpm->iic_mutex);
return -EREMOTEIO;
}
}
}
#ifdef I2C_CHIP_ERRATA
/* Chip errata, clear enable. This is not needed on rev D4 CPUs.
Disabling I2C too early may cause too short stop condition */
udelay(4);
out_8(&i2c->i2c_i2mod, in_8(&i2c->i2c_i2mod) | ~1);
#endif
mutex_unlock(&cpm->iic_mutex);
return (num);
}
static u32 cpm_func(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}
/* -----exported algorithm data: ------------------------------------- */
static struct i2c_algorithm cpm_algo = {
.master_xfer = cpm_xfer,
.functionality = cpm_func,
};
/*
* registering functions to load algorithms at runtime
*/
int i2c_cpm_add_bus(struct i2c_adapter *adap)
{
int res;
printk("i2c-cpm: hw routines for %s registered.\n", adap->name);
/* register new adapter to i2c module... */
adap->algo = &cpm_algo;
res = cpm_iic_init(adap);
if (res)
return res;
return i2c_add_adapter(adap);
}
int i2c_cpm_del_bus(struct i2c_adapter *adap)
{
i2c_del_adapter(adap);
return cpm_iic_shutdown(adap);
}
static const struct i2c_adapter cpm_ops = {
.owner = THIS_MODULE,
.name = "i2c-cpm",
.id = I2C_HW_MPC8XX_EPON,
.class = I2C_CLASS_HWMON,
};
static int i2c_cpm_setup(struct cpm_i2c *i2c)
{
struct of_device *ofdev = i2c->ofdev;
const u32 *data;
int len;
/* Pointer to Communication Processor
*/
i2c->irq = of_irq_to_resource(ofdev->node, 0, NULL);
if (i2c->irq == NO_IRQ)
return -EINVAL;
i2c->iip = of_iomap(ofdev->node, 1);
if (i2c->iip == NULL)
return -EINVAL;
#ifndef CONFIG_CPM2
/* Check for and use a microcode relocation patch.
*/
if (of_device_is_compatible(ofdev->node, "fsl,i2c-cpm1"))
i2c->reloc = i2c->iip->iic_rpbase;
/* Maybe should use ioremap instead?
*/
if (i2c->reloc) {
iounmap(i2c->iip);
i2c->iip = cpm_muram_addr(i2c->iip->iic_rpbase);
}
#endif
i2c->i2c = of_iomap(ofdev->node, 0);
if (i2c->i2c == NULL)
return -EINVAL;
/* Allocate space for two transmit and two receive buffer
* descriptors in the DP ram.
*/
i2c->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 4, 8);
if (!i2c->dp_addr)
return -ENOMEM;
data = of_get_property(ofdev->node, "fsl,cpm-command", &len);
if (!data || len != 4)
return -EINVAL;
i2c->cp_command = *data;
return 0;
}
static void i2c_cpm_release(struct cpm_i2c *i2c)
{
if (i2c->dp_addr)
cpm_muram_free(i2c->dp_addr);
if (i2c->i2c)
iounmap(i2c->i2c);
if ((i2c->iip) && (!i2c->reloc))
iounmap(i2c->iip);
return;
}
static int i2c_cpm_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
int result;
struct cpm_i2c *i2c;
i2c = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
if (!i2c)
return -ENOMEM;
i2c->ofdev = ofdev;
result = i2c_cpm_setup(i2c);
if (result) {
printk(KERN_ERR "i2c-cpm: Unable to register resources\n");
goto out;
}
dev_set_drvdata(&ofdev->dev, i2c);
i2c->adap = cpm_ops;
i2c_set_adapdata(&i2c->adap, i2c);
i2c->adap.dev.parent = &ofdev->dev;
result = i2c_cpm_add_bus(&i2c->adap);
if (result < 0) {
printk(KERN_ERR "i2c-cpm: Unable to register with I2C\n");
goto out;
}
return 0;
out:
i2c_cpm_release(i2c);
kfree(i2c);
return result;
}
static int i2c_cpm_remove(struct of_device *ofdev)
{
struct cpm_i2c *i2c = dev_get_drvdata(&ofdev->dev);
i2c_cpm_del_bus(&i2c->adap);
dev_set_drvdata(&ofdev->dev, NULL);
i2c_cpm_release(i2c);
kfree(i2c);
return 0;
}
static struct of_device_id i2c_cpm_match[] = {
{
.compatible = "fsl,cpm-i2c",
},
{},
};
MODULE_DEVICE_TABLE(of, i2c_cpm_match);
static struct of_platform_driver i2c_cpm_driver = {
.name = "fsl-i2c-cpm",
.match_table = i2c_cpm_match,
.probe = i2c_cpm_probe,
.remove = i2c_cpm_remove,
};
static int __init i2c_cpm_init(void)
{
return of_register_platform_driver(&i2c_cpm_driver);
}
static void __exit i2c_cpm_exit(void)
{
of_unregister_platform_driver(&i2c_cpm_driver);
}
module_init(i2c_cpm_init);
module_exit(i2c_cpm_exit);
MODULE_AUTHOR("Dan Malek <dmalek@jlc.net>");
MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
MODULE_LICENSE("GPL");
^ permalink raw reply
* [PATCH] [POWERPC] 4xx: Use virtual PVR value to init FPU on arch/ppc 440EP
From: Josh Boyer @ 2007-11-16 17:29 UTC (permalink / raw)
To: linuxppc-dev
This fixes arch/ppc 440EP platforms to setup the FPU correctly. A virtual
PVR is used, as 440GR platforms share an identical hardware PVR value and do
not have an FPU.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Index: linux-2.6/arch/ppc/kernel/setup.c
===================================================================
--- linux-2.6.orig/arch/ppc/kernel/setup.c
+++ linux-2.6/arch/ppc/kernel/setup.c
@@ -312,7 +312,14 @@ early_init(int r3, int r4, int r5)
* Identify the CPU type and fix up code sections
* that depend on which cpu we have.
*/
+#if defined(CONFIG_440EP) && defined(CONFIG_PPC_FPU)
+ /* We pass the virtual PVR here for 440EP as 440EP and 440GR have
+ * identical PVRs and there is no reliable way to check for the FPU
+ */
+ spec = identify_cpu(offset, (mfspr(SPRN_PVR) | 0x8));
+#else
spec = identify_cpu(offset, mfspr(SPRN_PVR));
+#endif
do_feature_fixups(spec->cpu_features,
PTRRELOC(&__start___ftr_fixup),
PTRRELOC(&__stop___ftr_fixup));
^ permalink raw reply
* [POWERPC] [RFC] Fix 8xx tlbie definition
From: Josh Boyer @ 2007-11-16 17:28 UTC (permalink / raw)
To: vitb, benh; +Cc: linuxppc-dev
Git commit e701d269aa28996f3502780951fe1b12d5d66b49 introduced an incorrect
definition for _tlbie on PowerPC 8xx platforms. Only the address should be
passed to the function. This patch corrects the definition of _tlbie and the
related tlb flushing functions for 8xx.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Index: linux-2.6/include/asm-powerpc/tlbflush.h
===================================================================
--- linux-2.6.orig/include/asm-powerpc/tlbflush.h
+++ linux-2.6/include/asm-powerpc/tlbflush.h
@@ -28,19 +28,33 @@
#include <linux/mm.h>
+#if defined(CONFIG_8xx)
+/* 8xx doesn't use PID for TLB invalidates */
+extern void _tlbie(unsigned address);
+#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
+
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+ unsigned long vmaddr)
+{
+ _tlbie(vmaddr);
+}
+
+static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
+ unsigned long vmaddr)
+{
+ _tlbie(vmaddr);
+}
+
+#else /* 4xx or FSL_BOOKE */
+
extern void _tlbie(unsigned long address, unsigned int pid);
-#if defined(CONFIG_40x) || defined(CONFIG_8xx)
+#if defined(CONFIG_40x)
#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
extern void _tlbia(void);
#endif
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
- _tlbia();
-}
-
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
@@ -53,6 +67,13 @@ static inline void flush_tlb_page_nohash
_tlbie(vmaddr, vma->vm_mm->context.id);
}
+#endif /* CONFIG_8xx */
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+ _tlbia();
+}
+
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
^ permalink raw reply
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