* Re: [PATCH] Add MPC837xEMDS PCIE RC mode support
From: Li Li @ 2007-11-30 9:37 UTC (permalink / raw)
To: Gala Kumar; +Cc: linuxppc-dev, Li Tony
In-Reply-To: <7DF684FC-A53A-4F4D-903F-D50F1E0A486A@freescale.com>
On Fri, 2007-11-30 at 17:05 +0800, Gala Kumar wrote:
> >>> +
> >>> + pci2@e0009000 {
> >>
> >> I agree w/Olof. This should be pcie@e0009000
> >>>
> >>> + interrupt-map-mask = <f800 0 0 7>;
> >>> + msi-available-ranges = <43 4 51 52 56 57 58 59>;
> >>> + interrupt-map = <
> >>> + 0000 0 0 1 &ipic 1 8
> >>> + 0000 0 0 2 &ipic 1 8
> >>> + 0000 0 0 3 &ipic 1 8
> >>> + 0000 0 0 4 &ipic 1 8
> >>> + >;
> >>> + interrupt-parent = < &ipic >;
> >>> + interrupts = <1 8>;
> >>> + bus-range = <0 0>;
> >>> + ranges = <02000000 0 A8000000 A8000000 0 10000000
> >>> + 01000000 0 00000000 B8000000 0 00800000>;
> >>> + clock-frequency = <0>;
> >>> + #interrupt-cells = <1>;
> >>> + #size-cells = <2>;
> >>> + #address-cells = <3>;
> >>> + reg = <e0009000 00001000
> >>> + a0000000 08000000>;
> >>
> >> Shouldn't the reg size for the cfg space be 256M?
> >
> > 256M is a little too big for kernel.
>
> what do you mean too big? Aren't you losing access to some
> bus/dev/fn
> than?
If do it standard, a 256M config space, at least 256M mem space and 16M
io space are needed for each PCIE controller.
To allocate PCIE window, the window size only can be 512M or 1G.
If we choose 1G space, two PCIE controller needs 2G space.
We do not have 2G free physical space now. Usually, we use upper 128M
configure space. So, we have to cut down the config space.
>
> >>> diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/
> >>> platforms/83xx/Kconfig
> >>> index 0c61e7a..00154c5 100644
> >>> --- a/arch/powerpc/platforms/83xx/Kconfig
> >>> +++ b/arch/powerpc/platforms/83xx/Kconfig
> >>> @@ -87,3 +87,10 @@ config PPC_MPC837x
> >>> select PPC_INDIRECT_PCI
> >>> select FSL_SERDES
> >>> default y if MPC837x_MDS
> >>> +
> >>> +config PPC_MPC83XX_PCIE
> >>> + bool "MPC837X PCI Express support"
> >>> + depends on PCIEPORTBUS && PPC_MPC837x
> >>> + default n
> >>> + help
> >>> + Enables MPC837x PCI express RC mode
> >>
> >> This should be a hidden config that is just selected by
> PPC_MPC837x
> >> instead of a choice. Also drop the depends on.
> >>
> >
> > In the dts file, the PCIE is default enabled. So, we should provide
> > another way to disable the PCIE.
> > Modify and recompile the dts is a little unkind to user.
>
> Why do you something beyond CONFIG_PCI. if you don't want PCIe but
> do
> want PCI the extra code for PCIe isn't going to kill you.
>
Here is a little complex. The MPC837xE board needs a carrier board to
extend PCIE slot. If user does not populate carrier board onto MPC837xE
board and do PCIE scan, the system will halt.
I just want to provide a easy way to disable the PCIe other than modify
and recompile the dts.
> >>> diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h
> b/arch/powerpc/
> >>> platforms/83xx/mpc83xx.h
> >>> index b778cb4..2078da7 100644
> >>> --- a/arch/powerpc/platforms/83xx/mpc83xx.h
> >>> +++ b/arch/powerpc/platforms/83xx/mpc83xx.h
> >>> @@ -43,12 +43,18 @@
> >>> #define PORTSCX_PTS_UTMI 0x00000000
> >>> #define PORTSCX_PTS_ULPI 0x80000000
> >>>
> >>> +/* PCIE Registers */
> >>> +#define PEX_LTSSM_STAT 0x404
> >>> +#define PEX_LTSSM_STAT_L0 0x16
> >>> +#define PEX_GCLK_RATIO 0x440
> >>> +
> >>
> >> just move these into the .c file.
ok.
> >>
> >>>
> >>> /*
> >>> * Declaration for the various functions exported by the
> >>> * mpc83xx_* files. Mostly for use by mpc83xx_setup
> >>> */
> >>> -
> >>> -extern int mpc83xx_add_bridge(struct device_node *dev);
> >>> +#define PPC_83XX_PCI 0x1
> >>> +#define PPC_83XX_PCIE 0x2
> >>> +extern int mpc83xx_add_bridge(struct device_node *dev, int
> flags);
> >>> extern void mpc83xx_restart(char *cmd);
> >>> extern long mpc83xx_time_init(void);
> >>> extern int mpc834x_usb_cfg(void);
> >>> diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/
> >>> platforms/83xx/pci.c
> >>> index 80425d7..0b52b2e 100644
> >>> --- a/arch/powerpc/platforms/83xx/pci.c
> >>> +++ b/arch/powerpc/platforms/83xx/pci.c
> >>> @@ -25,6 +25,8 @@
> >>> #include <asm/prom.h>
> >>> #include <sysdev/fsl_soc.h>
> >>>
> >>> +#include "mpc83xx.h"
> >>> +
> >>> #undef DEBUG
> >>>
> >>> #ifdef DEBUG
> >>> @@ -33,13 +35,157 @@
> >>> #define DBG(x...)
> >>> #endif
> >>>
> >>> -int __init mpc83xx_add_bridge(struct device_node *dev)
> >>> +#if defined(CONFIG_PPC_MPC83XX_PCIE)
> >>> +
> >>> +/* PCIE config space Read/Write routines */
> >>
> >> should really be called something like mpc83xx_pciex_read_config
> >>>
> >>> +static int direct_read_config_pcie(struct pci_bus *bus,
> >>> + uint devfn, int offset, int len, u32 *val)
> >>> +{
> >>> + struct pci_controller *hose = bus->sysdata;
> >>> + void __iomem *cfg_addr;
> >>> + u32 bus_no;
> >>> +
> >>> + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
> >>> + return PCIBIOS_DEVICE_NOT_FOUND;
> >>> +
> >>> + if (ppc_md.pci_exclude_device)
> >>> + if (ppc_md.pci_exclude_device(hose, bus->number,
> >> devfn))
> >>> + return PCIBIOS_DEVICE_NOT_FOUND;
> >>> +
> >>> + switch (len) {
> >>> + case 2:
> >>> + if (offset & 1)
> >>> + return -EINVAL;
> >>> + break;
> >>> + case 4:
> >>> + if (offset & 3)
> >>> + return -EINVAL;
> >>> + break;
> >>> + }
> >>
> >> fix formatting.
> >>
> >>>
> >>> +
> >>> + pr_debug("_read_cfg_pcie: bus=%d devfn=%x off=%x len=%x\n",
> >>> + bus->number, devfn, offset, len);
> >>> +
> >>> + if (bus->number == hose->first_busno) {
> >>> + if (devfn & 0xf8)
> >>> + return PCIBIOS_DEVICE_NOT_FOUND;
> >>
> >> what is the 0xf8 all about?
> >>
> >
> > The pcie only have one link, so the dev number only can be 0, as
> well
> > the function number can be 0 ~ 7.
>
> I don't follow what the number of links has to do with dev number.
The PCIE only have one link that mean one PCIE bus only can have one
device populate on it. The dev number of this device must be 0. If the
device number is not 0, we consider it is a error.
>
> >>> + addr = mbase + (cfg_addr & ~PAGE_MASK);
> >>> + hose->cfg_addr = addr;
> >>> + hose->ops = &direct_pcie_ops;
> >>
> >> what's the point of this function, why not just fold it into
> >> mpc83xx_setup_pcie
> >>
> >>>
> >>> +}
> >>> +
> >>> +static void __init mpc83xx_setup_pcie(struct pci_controller
> *hose,
> >>> + struct resource *reg, struct resource
> >> *cfg_space)
> >>> +{
> >>> + void __iomem *hose_cfg_base;
> >>> + u32 val;
> >>> +
> >>> + hose_cfg_base = ioremap(reg->start, reg->end - reg->start +
> >> 1);
> >>> +
> >>> + val = in_le32(hose_cfg_base + PEX_LTSSM_STAT);
> >>> + if (val < PEX_LTSSM_STAT_L0)
> >>> + hose->indirect_type |=
> >> PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >>> +
> >>> + setup_direct_pcie(hose, cfg_space->start,
> >>> + cfg_space->end - cfg_space->start + 1);
> >>> +}
> >>> +#endif /* CONFIG_PPC_MPC83XX_PCIE */
> >>> +
> >>
> >> We should do the same think fsl_pci does for primary, its passed
> >> into
> >> _add_bridge. Also, can we not do what fsl_pci does and use PCI
> >> capabilities to determine we are a PCIe controller (and drop
> passing
> >> it in via flags).
> >>
> >
> > The mpc837x PCIE controller is a little different from mpc85xx.
> > It can not be access via PCI configure read/write. It only can be
> > accessed via memory-mapped read/write from core.
>
> You don't have access to your own config space?
>
I can access it but can not via standard pci configure routine.
So, we use different way to access PCI and PCIE. If we want access PCI
capabilities, we must know it is PCI controller or PCIE controller
first.
- Tony
> - k
>
^ permalink raw reply
* Re: Init hangs on Xilinx4
From: David H. Lynch Jr. @ 2007-11-30 9:27 UTC (permalink / raw)
To: schardt, linuxppc-embedded
In-Reply-To: <474ED262.5010408@fz-juelich.de>
schardt wrote:
> Hi David,
>
> thanks for your help.
>
>>>
>>>
>>>
>> I am presuming you are using PK's UartLite driver.
>>
>>
> I use the Kernel from Grant's git server, and let me look... yes its
> from Peter Korsgaard :)
>
>
>> Try printing out membase some time possibly in ulite_console_setup.
>> If the value of membase is 0x406000000 that is your problem.
>> It should be something like 0xfdxxxxxxxx I think.
>>
>>
> Mmmh, my EDK Project maps the uartlite to 0x40600000, so i think its
> okay. but i can try it at a higher adress
>
> it is very strange. i use the same hardware setup and boot from
> system-ace without any problems.
Another posibility that I thought of since you are using Peter K's
driver.
If you have any interrupt problems I think you could get your
current behavior.
During boot console I/O is not interrupt driven. When the OS sends a
string the whole string gets sent and then the console write exits,
but very close to running init, the console switches to using the
full driver. PK's driver is interrupt driven. If the UartLite TX FIFO
empty interrupt
is broke in anyway, it will send until the first time the FIFO fills
and then stop. The interrupt could be broken in firmware - not properly
connected to the PIC, or it could be broken in software - however your
driver is receiving its interrupt configuration, the driver may be
receiving the incorrect intterrupt #.
At one point I tried to add timer driven polling to PK's driver
similar to that in the 8250 and others - we have clients that run
without any PIC,
but trying to figure out what was going on proved sufficiently
difficult I just went back to my own driver.
>
>
>
> Regards
> Georg
>
>
> -------------------------------------------------------------------
> -------------------------------------------------------------------
> Forschungszentrum Jülich GmbH
> 52425 Jülich
>
> Sitz der Gesellschaft: Jülich
> Eingetragen im Handelsregister des Amtsgerichts Düren Nr. HR B 3498
> Vorsitzende des Aufsichtsrats: MinDirig'in Bärbel Brumme-Bothe
> Geschäftsführung: Prof. Dr. Achim Bachem (Vorsitzender),
> Dr. Ulrich Krafft (stellv. Vorsitzender), Dr. Sebastian M. Schmidt
> -------------------------------------------------------------------
> -------------------------------------------------------------------
>
--
Dave Lynch DLA Systems
Software Development: Embedded Linux
717.627.3770 dhlii@dlasys.net http://www.dlasys.net
fax: 1.253.369.9244 Cell: 1.717.587.7774
Over 25 years' experience in platforms, languages, and technologies too numerous to list.
"Any intelligent fool can make things bigger and more complex... It takes a touch of genius - and a lot of courage to move in the opposite direction."
Albert Einstein
^ permalink raw reply
* Re: [PATCH 12/24] powerpc: 4xx PLB to PCI Express support
From: Benjamin Herrenschmidt @ 2007-11-30 9:26 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <0472C239-D0C8-43FE-9996-1C28584EFBAD@kernel.crashing.org>
> Is it intentional that you dont support ppc_md.pci_exclude_device()?
More like I didn't have a need for it... that can easily be fixed when
it arises.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 12/24] powerpc: 4xx PLB to PCI Express support
From: Kumar Gala @ 2007-11-30 9:18 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20071130061155.41D71DDF5F@ozlabs.org>
On Nov 30, 2007, at 12:10 AM, Benjamin Herrenschmidt wrote:
> This adds to the previous 2 patches the support for the 4xx PCI
> Express
> cells as found in the 440SPe revA, revB and 405EX.
>
> Unfortunately, due to significant differences between these, and other
> interesting "features" of those pieces of HW, the code isn't as simple
> as it is for PCI and PCI-X and some of the functions differ
> significantly
> between the 3 implementations. Thus, not only this code can only
> support
> those 3 implementations for now and will refuse to operate on any
> other,
> but there are added ifdef's to avoid the bloat of building a fairly
> large
> amount of code on platforms that don't need it.
>
> Also, this code currently only supports fully initializing root
> complex
> nodes, not endpoint. Some more code will have to be lifted from the
> arch/ppc implementation to add the endpoint support, though it's
> mostly
> differences in memory mapping, and the question on how to represent
> endpoint mode PCI in the device-tree is thus open.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>
> 440SPeA is untested, 440SPeB is slightly tested (with a sky2 network
> card on
> port 0 only for now) and 405EX is untested.
>
> arch/powerpc/Kconfig | 1
> arch/powerpc/sysdev/Kconfig | 8
> arch/powerpc/sysdev/ppc4xx_pci.c | 927 +++++++++++++++++++++++++++++
> +++++++++-
> arch/powerpc/sysdev/ppc4xx_pci.h | 237 +++++++++
> 4 files changed, 1172 insertions(+), 1 deletion(-)
Is it intentional that you dont support ppc_md.pci_exclude_device()?
- k
^ permalink raw reply
* [RFC][PATCH] [POWERPC] Allow caching of kmap_atomic page
From: Kumar Gala @ 2007-11-30 9:14 UTC (permalink / raw)
To: Paul Mackerras, Benjamin Herrenschmidt; +Cc: linuxppc-dev
Skip updating the kmap_pte and flushing the TLB if the pte we
are about to write is the same as the one we wrote last time we
called kmap_atomic for this km_type.
Also expose the flags to allow a caller to specify their own
flags for things like non-cacheable IO memory.
---
This is the starts of some work Ben and I were discussion to allow us to
use kmap_atomic to access a page size region of PCI CFG space when its
provided as direct MMIO.
We also intend to provide a means to preload the TLB for SW managed TLB
machines.
- k
include/asm-powerpc/highmem.h | 16 +++++++++++++---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/include/asm-powerpc/highmem.h b/include/asm-powerpc/highmem.h
index f7b21ee..a50bb00 100644
--- a/include/asm-powerpc/highmem.h
+++ b/include/asm-powerpc/highmem.h
@@ -73,10 +73,12 @@ static inline void kunmap(struct page *page)
* be used in IRQ contexts, so in some (very limited) cases we need
* it.
*/
-static inline void *kmap_atomic(struct page *page, enum km_type type)
+static inline void *__kmap_atomic(struct page *page,
+ enum km_type type, unsigned long flags)
{
unsigned int idx;
unsigned long vaddr;
+ pte_t pte;
/* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
pagefault_disable();
@@ -88,12 +90,20 @@ static inline void *kmap_atomic(struct page *page, enum km_type type)
#ifdef HIGHMEM_DEBUG
BUG_ON(!pte_none(*(kmap_pte+idx)));
#endif
- set_pte_at(&init_mm, vaddr, kmap_pte+idx, mk_pte(page, kmap_prot));
- flush_tlb_page(NULL, vaddr);
+ pte = mk_pte(page, flags);
+ if (!pte_same(kmap_pte[idx], pte)) {
+ set_pte_at(&init_mm, vaddr, kmap_pte+idx, pte);
+ flush_tlb_page(NULL, vaddr);
+ }
return (void*) vaddr;
}
+static inline void *kmap_atomic(struct page *page, enum km_type type)
+{
+ return __kmap_atomic(page, type, kmap_prot);
+}
+
static inline void kunmap_atomic(void *kvaddr, enum km_type type)
{
#ifdef HIGHMEM_DEBUG
--
1.5.3.4
^ permalink raw reply related
* Re: [PATCH] Add MPC837xEMDS PCIE RC mode support
From: Kumar Gala @ 2007-11-30 9:05 UTC (permalink / raw)
To: Li Li; +Cc: linuxppc-dev, Li Tony
In-Reply-To: <1196412491.31962.9.camel@Guyver>
>>> +
>>> + pci2@e0009000 {
>>
>> I agree w/Olof. This should be pcie@e0009000
>>>
>>> + interrupt-map-mask = <f800 0 0 7>;
>>> + msi-available-ranges = <43 4 51 52 56 57 58 59>;
>>> + interrupt-map = <
>>> + 0000 0 0 1 &ipic 1 8
>>> + 0000 0 0 2 &ipic 1 8
>>> + 0000 0 0 3 &ipic 1 8
>>> + 0000 0 0 4 &ipic 1 8
>>> + >;
>>> + interrupt-parent = < &ipic >;
>>> + interrupts = <1 8>;
>>> + bus-range = <0 0>;
>>> + ranges = <02000000 0 A8000000 A8000000 0 10000000
>>> + 01000000 0 00000000 B8000000 0 00800000>;
>>> + clock-frequency = <0>;
>>> + #interrupt-cells = <1>;
>>> + #size-cells = <2>;
>>> + #address-cells = <3>;
>>> + reg = <e0009000 00001000
>>> + a0000000 08000000>;
>>
>> Shouldn't the reg size for the cfg space be 256M?
>
> 256M is a little too big for kernel.
what do you mean too big? Aren't you losing access to some bus/dev/fn
than?
>>> diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/
>>> platforms/83xx/Kconfig
>>> index 0c61e7a..00154c5 100644
>>> --- a/arch/powerpc/platforms/83xx/Kconfig
>>> +++ b/arch/powerpc/platforms/83xx/Kconfig
>>> @@ -87,3 +87,10 @@ config PPC_MPC837x
>>> select PPC_INDIRECT_PCI
>>> select FSL_SERDES
>>> default y if MPC837x_MDS
>>> +
>>> +config PPC_MPC83XX_PCIE
>>> + bool "MPC837X PCI Express support"
>>> + depends on PCIEPORTBUS && PPC_MPC837x
>>> + default n
>>> + help
>>> + Enables MPC837x PCI express RC mode
>>
>> This should be a hidden config that is just selected by PPC_MPC837x
>> instead of a choice. Also drop the depends on.
>>
>
> In the dts file, the PCIE is default enabled. So, we should provide
> another way to disable the PCIE.
> Modify and recompile the dts is a little unkind to user.
Why do you something beyond CONFIG_PCI. if you don't want PCIe but do
want PCI the extra code for PCIe isn't going to kill you.
>>> diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/
>>> platforms/83xx/mpc83xx.h
>>> index b778cb4..2078da7 100644
>>> --- a/arch/powerpc/platforms/83xx/mpc83xx.h
>>> +++ b/arch/powerpc/platforms/83xx/mpc83xx.h
>>> @@ -43,12 +43,18 @@
>>> #define PORTSCX_PTS_UTMI 0x00000000
>>> #define PORTSCX_PTS_ULPI 0x80000000
>>>
>>> +/* PCIE Registers */
>>> +#define PEX_LTSSM_STAT 0x404
>>> +#define PEX_LTSSM_STAT_L0 0x16
>>> +#define PEX_GCLK_RATIO 0x440
>>> +
>>
>> just move these into the .c file.
>>
>>>
>>> /*
>>> * Declaration for the various functions exported by the
>>> * mpc83xx_* files. Mostly for use by mpc83xx_setup
>>> */
>>> -
>>> -extern int mpc83xx_add_bridge(struct device_node *dev);
>>> +#define PPC_83XX_PCI 0x1
>>> +#define PPC_83XX_PCIE 0x2
>>> +extern int mpc83xx_add_bridge(struct device_node *dev, int flags);
>>> extern void mpc83xx_restart(char *cmd);
>>> extern long mpc83xx_time_init(void);
>>> extern int mpc834x_usb_cfg(void);
>>> diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/
>>> platforms/83xx/pci.c
>>> index 80425d7..0b52b2e 100644
>>> --- a/arch/powerpc/platforms/83xx/pci.c
>>> +++ b/arch/powerpc/platforms/83xx/pci.c
>>> @@ -25,6 +25,8 @@
>>> #include <asm/prom.h>
>>> #include <sysdev/fsl_soc.h>
>>>
>>> +#include "mpc83xx.h"
>>> +
>>> #undef DEBUG
>>>
>>> #ifdef DEBUG
>>> @@ -33,13 +35,157 @@
>>> #define DBG(x...)
>>> #endif
>>>
>>> -int __init mpc83xx_add_bridge(struct device_node *dev)
>>> +#if defined(CONFIG_PPC_MPC83XX_PCIE)
>>> +
>>> +/* PCIE config space Read/Write routines */
>>
>> should really be called something like mpc83xx_pciex_read_config
>>>
>>> +static int direct_read_config_pcie(struct pci_bus *bus,
>>> + uint devfn, int offset, int len, u32 *val)
>>> +{
>>> + struct pci_controller *hose = bus->sysdata;
>>> + void __iomem *cfg_addr;
>>> + u32 bus_no;
>>> +
>>> + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
>>> + return PCIBIOS_DEVICE_NOT_FOUND;
>>> +
>>> + if (ppc_md.pci_exclude_device)
>>> + if (ppc_md.pci_exclude_device(hose, bus->number,
>> devfn))
>>> + return PCIBIOS_DEVICE_NOT_FOUND;
>>> +
>>> + switch (len) {
>>> + case 2:
>>> + if (offset & 1)
>>> + return -EINVAL;
>>> + break;
>>> + case 4:
>>> + if (offset & 3)
>>> + return -EINVAL;
>>> + break;
>>> + }
>>
>> fix formatting.
>>
>>>
>>> +
>>> + pr_debug("_read_cfg_pcie: bus=%d devfn=%x off=%x len=%x\n",
>>> + bus->number, devfn, offset, len);
>>> +
>>> + if (bus->number == hose->first_busno) {
>>> + if (devfn & 0xf8)
>>> + return PCIBIOS_DEVICE_NOT_FOUND;
>>
>> what is the 0xf8 all about?
>>
>
> The pcie only have one link, so the dev number only can be 0, as well
> the function number can be 0 ~ 7.
I don't follow what the number of links has to do with dev number.
>>> + addr = mbase + (cfg_addr & ~PAGE_MASK);
>>> + hose->cfg_addr = addr;
>>> + hose->ops = &direct_pcie_ops;
>>
>> what's the point of this function, why not just fold it into
>> mpc83xx_setup_pcie
>>
>>>
>>> +}
>>> +
>>> +static void __init mpc83xx_setup_pcie(struct pci_controller *hose,
>>> + struct resource *reg, struct resource
>> *cfg_space)
>>> +{
>>> + void __iomem *hose_cfg_base;
>>> + u32 val;
>>> +
>>> + hose_cfg_base = ioremap(reg->start, reg->end - reg->start +
>> 1);
>>> +
>>> + val = in_le32(hose_cfg_base + PEX_LTSSM_STAT);
>>> + if (val < PEX_LTSSM_STAT_L0)
>>> + hose->indirect_type |=
>> PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>>> +
>>> + setup_direct_pcie(hose, cfg_space->start,
>>> + cfg_space->end - cfg_space->start + 1);
>>> +}
>>> +#endif /* CONFIG_PPC_MPC83XX_PCIE */
>>> +
>>
>> We should do the same think fsl_pci does for primary, its passed
>> into
>> _add_bridge. Also, can we not do what fsl_pci does and use PCI
>> capabilities to determine we are a PCIe controller (and drop passing
>> it in via flags).
>>
>
> The mpc837x PCIE controller is a little different from mpc85xx.
> It can not be access via PCI configure read/write. It only can be
> accessed via memory-mapped read/write from core.
You don't have access to your own config space?
- k
^ permalink raw reply
* Re: [PATCH] Add MPC837xEMDS PCIE RC mode support
From: Li Li @ 2007-11-30 8:48 UTC (permalink / raw)
To: Gala Kumar; +Cc: linuxppc-dev, Li Tony
In-Reply-To: <4544168D-5E95-44E8-9128-6F343283EC82@freescale.com>
On Fri, 2007-11-30 at 15:37 +0800, Gala Kumar wrote:
>
> On Nov 29, 2007, at 9:45 PM, Li Li wrote:
>
> > The PCIE controller is initiated in u-boot.
> >
> > This patch is based on Leo`s mpc837xe patches.
> >
> >
> > Signed-off-by: Tony Li <tony.li@freescale.com>
> > ---
> > arch/powerpc/boot/dts/mpc8377_mds.dts | 56 ++++++++--
> > arch/powerpc/boot/dts/mpc8378_mds.dts | 56 ++++++++--
> > arch/powerpc/platforms/83xx/Kconfig | 7 ++
> > arch/powerpc/platforms/83xx/mpc8313_rdb.c | 2 +-
> > arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 +-
> > arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +-
> > arch/powerpc/platforms/83xx/mpc834x_itx.c | 2 +-
> > arch/powerpc/platforms/83xx/mpc834x_mds.c | 2 +-
> > arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
> > arch/powerpc/platforms/83xx/mpc837x_mds.c | 7 +-
> > arch/powerpc/platforms/83xx/mpc83xx.h | 10 ++-
> > arch/powerpc/platforms/83xx/pci.c | 166
> ++++++++++++++++++++
> > +++++++-
> > 12 files changed, 283 insertions(+), 31 deletions(-)
> >
> > diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/
> > boot/dts/mpc8377_mds.dts
> > index 4402e39..1f7819e 100644
>
> >
> > +
> > + pci2@e0009000 {
>
> I agree w/Olof. This should be pcie@e0009000
> >
> > + interrupt-map-mask = <f800 0 0 7>;
> > + msi-available-ranges = <43 4 51 52 56 57 58 59>;
> > + interrupt-map = <
> > + 0000 0 0 1 &ipic 1 8
> > + 0000 0 0 2 &ipic 1 8
> > + 0000 0 0 3 &ipic 1 8
> > + 0000 0 0 4 &ipic 1 8
> > + >;
> > + interrupt-parent = < &ipic >;
> > + interrupts = <1 8>;
> > + bus-range = <0 0>;
> > + ranges = <02000000 0 A8000000 A8000000 0 10000000
> > + 01000000 0 00000000 B8000000 0 00800000>;
> > + clock-frequency = <0>;
> > + #interrupt-cells = <1>;
> > + #size-cells = <2>;
> > + #address-cells = <3>;
> > + reg = <e0009000 00001000
> > + a0000000 08000000>;
>
> Shouldn't the reg size for the cfg space be 256M?
256M is a little too big for kernel.
>
>
> > diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/
> > platforms/83xx/Kconfig
> > index 0c61e7a..00154c5 100644
> > --- a/arch/powerpc/platforms/83xx/Kconfig
> > +++ b/arch/powerpc/platforms/83xx/Kconfig
> > @@ -87,3 +87,10 @@ config PPC_MPC837x
> > select PPC_INDIRECT_PCI
> > select FSL_SERDES
> > default y if MPC837x_MDS
> > +
> > +config PPC_MPC83XX_PCIE
> > + bool "MPC837X PCI Express support"
> > + depends on PCIEPORTBUS && PPC_MPC837x
> > + default n
> > + help
> > + Enables MPC837x PCI express RC mode
>
> This should be a hidden config that is just selected by PPC_MPC837x
> instead of a choice. Also drop the depends on.
>
In the dts file, the PCIE is default enabled. So, we should provide
another way to disable the PCIE.
Modify and recompile the dts is a little unkind to user.
> > diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/
> > platforms/83xx/mpc83xx.h
> > index b778cb4..2078da7 100644
> > --- a/arch/powerpc/platforms/83xx/mpc83xx.h
> > +++ b/arch/powerpc/platforms/83xx/mpc83xx.h
> > @@ -43,12 +43,18 @@
> > #define PORTSCX_PTS_UTMI 0x00000000
> > #define PORTSCX_PTS_ULPI 0x80000000
> >
> > +/* PCIE Registers */
> > +#define PEX_LTSSM_STAT 0x404
> > +#define PEX_LTSSM_STAT_L0 0x16
> > +#define PEX_GCLK_RATIO 0x440
> > +
>
> just move these into the .c file.
>
> >
> > /*
> > * Declaration for the various functions exported by the
> > * mpc83xx_* files. Mostly for use by mpc83xx_setup
> > */
> > -
> > -extern int mpc83xx_add_bridge(struct device_node *dev);
> > +#define PPC_83XX_PCI 0x1
> > +#define PPC_83XX_PCIE 0x2
> > +extern int mpc83xx_add_bridge(struct device_node *dev, int flags);
> > extern void mpc83xx_restart(char *cmd);
> > extern long mpc83xx_time_init(void);
> > extern int mpc834x_usb_cfg(void);
> > diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/
> > platforms/83xx/pci.c
> > index 80425d7..0b52b2e 100644
> > --- a/arch/powerpc/platforms/83xx/pci.c
> > +++ b/arch/powerpc/platforms/83xx/pci.c
> > @@ -25,6 +25,8 @@
> > #include <asm/prom.h>
> > #include <sysdev/fsl_soc.h>
> >
> > +#include "mpc83xx.h"
> > +
> > #undef DEBUG
> >
> > #ifdef DEBUG
> > @@ -33,13 +35,157 @@
> > #define DBG(x...)
> > #endif
> >
> > -int __init mpc83xx_add_bridge(struct device_node *dev)
> > +#if defined(CONFIG_PPC_MPC83XX_PCIE)
> > +
> > +/* PCIE config space Read/Write routines */
>
> should really be called something like mpc83xx_pciex_read_config
> >
> > +static int direct_read_config_pcie(struct pci_bus *bus,
> > + uint devfn, int offset, int len, u32 *val)
> > +{
> > + struct pci_controller *hose = bus->sysdata;
> > + void __iomem *cfg_addr;
> > + u32 bus_no;
> > +
> > + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > + if (ppc_md.pci_exclude_device)
> > + if (ppc_md.pci_exclude_device(hose, bus->number,
> devfn))
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > + switch (len) {
> > + case 2:
> > + if (offset & 1)
> > + return -EINVAL;
> > + break;
> > + case 4:
> > + if (offset & 3)
> > + return -EINVAL;
> > + break;
> > + }
>
> fix formatting.
>
> >
> > +
> > + pr_debug("_read_cfg_pcie: bus=%d devfn=%x off=%x len=%x\n",
> > + bus->number, devfn, offset, len);
> > +
> > + if (bus->number == hose->first_busno) {
> > + if (devfn & 0xf8)
> > + return PCIBIOS_DEVICE_NOT_FOUND;
>
> what is the 0xf8 all about?
>
The pcie only have one link, so the dev number only can be 0, as well
the function number can be 0 ~ 7.
> >
> > + bus_no = hose->self_busno;
> > + } else
> > + bus_no = bus->number;
> > +
> > + cfg_addr = (void __iomem *)((ulong) hose->cfg_addr +
> > + ((bus_no << 20) | (devfn << 12) | (offset & 0xfff)));
> > +
> > + switch (len) {
> > + case 1:
> > + *val = in_8(cfg_addr);
> > + break;
> > + case 2:
> > + *val = in_le16(cfg_addr);
> > + break;
> > + default:
> > + *val = in_le32(cfg_addr);
> > + break;
> > + }
> > + pr_debug("_read_cfg_pcie: val=%x cfg_addr=%p\n", *val,
> cfg_addr);
> > +
> > + return PCIBIOS_SUCCESSFUL;
> > +}
> > +
> > +static int direct_write_config_pcie(struct pci_bus *bus,
> > + uint devfn, int offset, int len, u32 val)
> > +{
> > + struct pci_controller *hose = bus->sysdata;
> > + void __iomem *cfg_addr;
> > + u32 bus_no;
> > +
> > + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > + if (ppc_md.pci_exclude_device)
> > + if (ppc_md.pci_exclude_device(hose, bus->number,
> devfn))
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > +
> > + switch (len) {
> > + case 2:
> > + if (offset & 1)
> > + return -EINVAL;
> > + break;
> > + case 4:
> > + if (offset & 3)
> > + return -EINVAL;
> > + break;
> > + }
> > +
> > + if (bus->number == hose->first_busno) {
> > + if (devfn & 0xf8)
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > + bus_no = hose->self_busno;
> > + } else
> > + bus_no = bus->number;
> > +
> > + cfg_addr = (void __iomem *)((ulong) hose->cfg_addr +
> > + ((bus_no << 20) | (devfn << 12) | (offset & 0xfff)));
> > +
> > + switch (len) {
> > + case 1:
> > + out_8(cfg_addr, val);
> > + break;
> > + case 2:
> > + out_le16(cfg_addr, val);
> > + break;
> > + default:
> > + out_le32(cfg_addr, val);
> > + break;
> > + }
> > +
> > + return PCIBIOS_SUCCESSFUL;
> > +}
> > +
> > +static struct pci_ops direct_pcie_ops = {
> > + direct_read_config_pcie,
> > + direct_write_config_pcie
> > +};
> > +
> > +void __init setup_direct_pcie(struct pci_controller *hose, u32
> > cfg_addr, u32 cfg_size)
> > +{
> > + ulong base = cfg_addr & PAGE_MASK;
> > + void __iomem *mbase, *addr;
> > +
> > + mbase = ioremap(base, cfg_size);
>
> this ioremap is going to be problematic in that cfg_size is going to
> be 256M. and we will not have enough kernel virtual address space to
> deal with it.
>
I agree.
> > + addr = mbase + (cfg_addr & ~PAGE_MASK);
> > + hose->cfg_addr = addr;
> > + hose->ops = &direct_pcie_ops;
>
> what's the point of this function, why not just fold it into
> mpc83xx_setup_pcie
>
> >
> > +}
> > +
> > +static void __init mpc83xx_setup_pcie(struct pci_controller *hose,
> > + struct resource *reg, struct resource
> *cfg_space)
> > +{
> > + void __iomem *hose_cfg_base;
> > + u32 val;
> > +
> > + hose_cfg_base = ioremap(reg->start, reg->end - reg->start +
> 1);
> > +
> > + val = in_le32(hose_cfg_base + PEX_LTSSM_STAT);
> > + if (val < PEX_LTSSM_STAT_L0)
> > + hose->indirect_type |=
> PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> > +
> > + setup_direct_pcie(hose, cfg_space->start,
> > + cfg_space->end - cfg_space->start + 1);
> > +}
> > +#endif /* CONFIG_PPC_MPC83XX_PCIE */
> > +
>
> We should do the same think fsl_pci does for primary, its passed
> into
> _add_bridge. Also, can we not do what fsl_pci does and use PCI
> capabilities to determine we are a PCIe controller (and drop passing
> it in via flags).
>
The mpc837x PCIE controller is a little different from mpc85xx.
It can not be access via PCI configure read/write. It only can be
accessed via memory-mapped read/write from core.
> > +int __init mpc83xx_add_bridge(struct device_node *dev, int flags)
> > {
> > int len;
> > struct pci_controller *hose;
> > struct resource rsrc;
> > +#if defined(CONFIG_PPC_MPC83XX_PCIE)
> > + struct resource cfg_space;
> > +#endif
> > const int *bus_range;
> > - int primary = 1, has_address = 0;
> > + static int primary = 1;
> > + int has_address = 0;
> > phys_addr_t immr = get_immrbase();
> >
> > DBG("Adding PCI host bridge %s\n", dev->full_name);
> > @@ -66,14 +212,21 @@ int __init mpc83xx_add_bridge(struct
> > device_node *dev)
> > * the other at 0x8600, we consider the 0x8500 the primary
> controller
> > */
> > /* PCI 1 */
> > - if ((rsrc.start & 0xfffff) == 0x8500) {
> > + if ((rsrc.start & 0xfffff) == 0x8500)
> > setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304,
> 0);
> > - }
> > /* PCI 2 */
> > - if ((rsrc.start & 0xfffff) == 0x8600) {
> > + if ((rsrc.start & 0xfffff) == 0x8600)
> > setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384,
> 0);
> > - primary = 0;
> > +
> > +#if defined(CONFIG_PPC_MPC83XX_PCIE)
> > + if (flags & PPC_83XX_PCIE) {
> > + if (of_address_to_resource(dev, 1, &cfg_space)) {
> > + printk("PCIE RC losts configure space. Skip it
> \n");
> > + return 1;
> > + }
> > + mpc83xx_setup_pcie(hose, &rsrc, &cfg_space);
> > }
> > +#endif
> >
> > printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx.
> "
> > "Firmware bus number: %d->%d\n",
> > @@ -86,6 +239,7 @@ int __init mpc83xx_add_bridge(struct
> device_node
> > *dev)
> > /* Interpret the "ranges" property */
> > /* This also maps the I/O region and sets isa_io/mem_base */
> > pci_process_bridge_OF_ranges(hose, dev, primary);
> > + primary = 0;
> >
> > return 0;
> > }
> > --
> > 1.5.2
> >
> >
> >
> > _______________________________________________
> > Linuxppc-dev mailing list
> > Linuxppc-dev@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH 1/11] ibm_newemac: Add BCM5248 and Marvell 88E1111 PHY support
From: Benjamin Herrenschmidt @ 2007-11-30 8:03 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: netdev, jgarzik, linuxppc-dev
In-Reply-To: <20071130075641.GA16650@infradead.org>
On Fri, 2007-11-30 at 07:56 +0000, Christoph Hellwig wrote:
> >
> > This patch adds BCM5248 and Marvell 88E1111 PHY support to NEW EMAC
> driver.
> > These PHY chips are used on PowerPC 440EPx boards.
> > The PHY code is based on the previous work by Stefan Roese
> <sr@denx.de>
>
> Is there a reason the emac driver isn't using the generic phy code?
Yes. First, the emac PHY code predates the generic one, and mostly,
in its current shape, the generic PHY code does too violent locking
for me.
I need to be able to use mutexes in the low level PHY read/write, and
the current phylib doesn't allow that as it uses spinlocks all over.
However, I do plan to fix that. I haven't had time yet, but I plan to
convert PHY lib to more task-level operations, which would be a good
thing anyway since PHY communication is fairly slow and some chips can
do it interrupt driven rather than polling loops (and even polling loops
could be preemptible).
So the answer is "not yet" basically.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 24/24] powerpc: Base support for 440SPe "Katmai" eval board
From: Benjamin Herrenschmidt @ 2007-11-30 7:59 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20071130061209.497F3DE03A@ozlabs.org>
On Fri, 2007-11-30 at 17:11 +1100, Benjamin Herrenschmidt wrote:
> This adds base support for the Katmai board, including PCI-X and
> PCI-Express (but no RTC, nvram, etc... yet).
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>
> As for Taishan, the bootwrapper code can be simplified. In fact,
> we probably don't need to probe clocks & memsize off the chip and
> just trust what uboot tells us.
This misses a select CONFIG_PPC4xx_PCI_EXPRESS in Kconfig, I added
that thing at the last minute and forgot to refresh the Katmai patch.
Without it, PCIe will not be probed.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 1/11] ibm_newemac: Add BCM5248 and Marvell 88E1111 PHY support
From: Christoph Hellwig @ 2007-11-30 7:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: netdev, jgarzik, linuxppc-dev
In-Reply-To: <20071130054126.39BDCDDE0A@ozlabs.org>
On Fri, Nov 30, 2007 at 04:40:23PM +1100, Benjamin Herrenschmidt wrote:
> From: Stefan Roese <sr@denx.de>
>
> This patch adds BCM5248 and Marvell 88E1111 PHY support to NEW EMAC driver.
> These PHY chips are used on PowerPC 440EPx boards.
> The PHY code is based on the previous work by Stefan Roese <sr@denx.de>
Is there a reason the emac driver isn't using the generic phy code?
^ permalink raw reply
* Re: [PATCH] Add MPC837xEMDS PCIE RC mode support
From: Kumar Gala @ 2007-11-30 7:37 UTC (permalink / raw)
To: Li Li; +Cc: linuxppc-dev
In-Reply-To: <1196394334.29683.5.camel@Guyver>
On Nov 29, 2007, at 9:45 PM, Li Li wrote:
> The PCIE controller is initiated in u-boot.
>
> This patch is based on Leo`s mpc837xe patches.
>
>
> Signed-off-by: Tony Li <tony.li@freescale.com>
> ---
> arch/powerpc/boot/dts/mpc8377_mds.dts | 56 ++++++++--
> arch/powerpc/boot/dts/mpc8378_mds.dts | 56 ++++++++--
> arch/powerpc/platforms/83xx/Kconfig | 7 ++
> arch/powerpc/platforms/83xx/mpc8313_rdb.c | 2 +-
> arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 +-
> arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +-
> arch/powerpc/platforms/83xx/mpc834x_itx.c | 2 +-
> arch/powerpc/platforms/83xx/mpc834x_mds.c | 2 +-
> arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
> arch/powerpc/platforms/83xx/mpc837x_mds.c | 7 +-
> arch/powerpc/platforms/83xx/mpc83xx.h | 10 ++-
> arch/powerpc/platforms/83xx/pci.c | 166 ++++++++++++++++++++
> +++++++-
> 12 files changed, 283 insertions(+), 31 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/
> boot/dts/mpc8377_mds.dts
> index 4402e39..1f7819e 100644
>
> +
> + pci2@e0009000 {
I agree w/Olof. This should be pcie@e0009000
>
> + interrupt-map-mask = <f800 0 0 7>;
> + msi-available-ranges = <43 4 51 52 56 57 58 59>;
> + interrupt-map = <
> + 0000 0 0 1 &ipic 1 8
> + 0000 0 0 2 &ipic 1 8
> + 0000 0 0 3 &ipic 1 8
> + 0000 0 0 4 &ipic 1 8
> + >;
> + interrupt-parent = < &ipic >;
> + interrupts = <1 8>;
> + bus-range = <0 0>;
> + ranges = <02000000 0 A8000000 A8000000 0 10000000
> + 01000000 0 00000000 B8000000 0 00800000>;
> + clock-frequency = <0>;
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <e0009000 00001000
> + a0000000 08000000>;
Shouldn't the reg size for the cfg space be 256M?
> diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/
> platforms/83xx/Kconfig
> index 0c61e7a..00154c5 100644
> --- a/arch/powerpc/platforms/83xx/Kconfig
> +++ b/arch/powerpc/platforms/83xx/Kconfig
> @@ -87,3 +87,10 @@ config PPC_MPC837x
> select PPC_INDIRECT_PCI
> select FSL_SERDES
> default y if MPC837x_MDS
> +
> +config PPC_MPC83XX_PCIE
> + bool "MPC837X PCI Express support"
> + depends on PCIEPORTBUS && PPC_MPC837x
> + default n
> + help
> + Enables MPC837x PCI express RC mode
This should be a hidden config that is just selected by PPC_MPC837x
instead of a choice. Also drop the depends on.
> diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/
> platforms/83xx/mpc83xx.h
> index b778cb4..2078da7 100644
> --- a/arch/powerpc/platforms/83xx/mpc83xx.h
> +++ b/arch/powerpc/platforms/83xx/mpc83xx.h
> @@ -43,12 +43,18 @@
> #define PORTSCX_PTS_UTMI 0x00000000
> #define PORTSCX_PTS_ULPI 0x80000000
>
> +/* PCIE Registers */
> +#define PEX_LTSSM_STAT 0x404
> +#define PEX_LTSSM_STAT_L0 0x16
> +#define PEX_GCLK_RATIO 0x440
> +
just move these into the .c file.
>
> /*
> * Declaration for the various functions exported by the
> * mpc83xx_* files. Mostly for use by mpc83xx_setup
> */
> -
> -extern int mpc83xx_add_bridge(struct device_node *dev);
> +#define PPC_83XX_PCI 0x1
> +#define PPC_83XX_PCIE 0x2
> +extern int mpc83xx_add_bridge(struct device_node *dev, int flags);
> extern void mpc83xx_restart(char *cmd);
> extern long mpc83xx_time_init(void);
> extern int mpc834x_usb_cfg(void);
> diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/
> platforms/83xx/pci.c
> index 80425d7..0b52b2e 100644
> --- a/arch/powerpc/platforms/83xx/pci.c
> +++ b/arch/powerpc/platforms/83xx/pci.c
> @@ -25,6 +25,8 @@
> #include <asm/prom.h>
> #include <sysdev/fsl_soc.h>
>
> +#include "mpc83xx.h"
> +
> #undef DEBUG
>
> #ifdef DEBUG
> @@ -33,13 +35,157 @@
> #define DBG(x...)
> #endif
>
> -int __init mpc83xx_add_bridge(struct device_node *dev)
> +#if defined(CONFIG_PPC_MPC83XX_PCIE)
> +
> +/* PCIE config space Read/Write routines */
should really be called something like mpc83xx_pciex_read_config
>
> +static int direct_read_config_pcie(struct pci_bus *bus,
> + uint devfn, int offset, int len, u32 *val)
> +{
> + struct pci_controller *hose = bus->sysdata;
> + void __iomem *cfg_addr;
> + u32 bus_no;
> +
> + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +
> + if (ppc_md.pci_exclude_device)
> + if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +
> + switch (len) {
> + case 2:
> + if (offset & 1)
> + return -EINVAL;
> + break;
> + case 4:
> + if (offset & 3)
> + return -EINVAL;
> + break;
> + }
fix formatting.
>
> +
> + pr_debug("_read_cfg_pcie: bus=%d devfn=%x off=%x len=%x\n",
> + bus->number, devfn, offset, len);
> +
> + if (bus->number == hose->first_busno) {
> + if (devfn & 0xf8)
> + return PCIBIOS_DEVICE_NOT_FOUND;
what is the 0xf8 all about?
>
> + bus_no = hose->self_busno;
> + } else
> + bus_no = bus->number;
> +
> + cfg_addr = (void __iomem *)((ulong) hose->cfg_addr +
> + ((bus_no << 20) | (devfn << 12) | (offset & 0xfff)));
> +
> + switch (len) {
> + case 1:
> + *val = in_8(cfg_addr);
> + break;
> + case 2:
> + *val = in_le16(cfg_addr);
> + break;
> + default:
> + *val = in_le32(cfg_addr);
> + break;
> + }
> + pr_debug("_read_cfg_pcie: val=%x cfg_addr=%p\n", *val, cfg_addr);
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static int direct_write_config_pcie(struct pci_bus *bus,
> + uint devfn, int offset, int len, u32 val)
> +{
> + struct pci_controller *hose = bus->sysdata;
> + void __iomem *cfg_addr;
> + u32 bus_no;
> +
> + if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +
> + if (ppc_md.pci_exclude_device)
> + if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +
> + switch (len) {
> + case 2:
> + if (offset & 1)
> + return -EINVAL;
> + break;
> + case 4:
> + if (offset & 3)
> + return -EINVAL;
> + break;
> + }
> +
> + if (bus->number == hose->first_busno) {
> + if (devfn & 0xf8)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> + bus_no = hose->self_busno;
> + } else
> + bus_no = bus->number;
> +
> + cfg_addr = (void __iomem *)((ulong) hose->cfg_addr +
> + ((bus_no << 20) | (devfn << 12) | (offset & 0xfff)));
> +
> + switch (len) {
> + case 1:
> + out_8(cfg_addr, val);
> + break;
> + case 2:
> + out_le16(cfg_addr, val);
> + break;
> + default:
> + out_le32(cfg_addr, val);
> + break;
> + }
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static struct pci_ops direct_pcie_ops = {
> + direct_read_config_pcie,
> + direct_write_config_pcie
> +};
> +
> +void __init setup_direct_pcie(struct pci_controller *hose, u32
> cfg_addr, u32 cfg_size)
> +{
> + ulong base = cfg_addr & PAGE_MASK;
> + void __iomem *mbase, *addr;
> +
> + mbase = ioremap(base, cfg_size);
this ioremap is going to be problematic in that cfg_size is going to
be 256M. and we will not have enough kernel virtual address space to
deal with it.
> + addr = mbase + (cfg_addr & ~PAGE_MASK);
> + hose->cfg_addr = addr;
> + hose->ops = &direct_pcie_ops;
what's the point of this function, why not just fold it into
mpc83xx_setup_pcie
>
> +}
> +
> +static void __init mpc83xx_setup_pcie(struct pci_controller *hose,
> + struct resource *reg, struct resource *cfg_space)
> +{
> + void __iomem *hose_cfg_base;
> + u32 val;
> +
> + hose_cfg_base = ioremap(reg->start, reg->end - reg->start + 1);
> +
> + val = in_le32(hose_cfg_base + PEX_LTSSM_STAT);
> + if (val < PEX_LTSSM_STAT_L0)
> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> +
> + setup_direct_pcie(hose, cfg_space->start,
> + cfg_space->end - cfg_space->start + 1);
> +}
> +#endif /* CONFIG_PPC_MPC83XX_PCIE */
> +
We should do the same think fsl_pci does for primary, its passed into
_add_bridge. Also, can we not do what fsl_pci does and use PCI
capabilities to determine we are a PCIe controller (and drop passing
it in via flags).
> +int __init mpc83xx_add_bridge(struct device_node *dev, int flags)
> {
> int len;
> struct pci_controller *hose;
> struct resource rsrc;
> +#if defined(CONFIG_PPC_MPC83XX_PCIE)
> + struct resource cfg_space;
> +#endif
> const int *bus_range;
> - int primary = 1, has_address = 0;
> + static int primary = 1;
> + int has_address = 0;
> phys_addr_t immr = get_immrbase();
>
> DBG("Adding PCI host bridge %s\n", dev->full_name);
> @@ -66,14 +212,21 @@ int __init mpc83xx_add_bridge(struct
> device_node *dev)
> * the other at 0x8600, we consider the 0x8500 the primary controller
> */
> /* PCI 1 */
> - if ((rsrc.start & 0xfffff) == 0x8500) {
> + if ((rsrc.start & 0xfffff) == 0x8500)
> setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
> - }
> /* PCI 2 */
> - if ((rsrc.start & 0xfffff) == 0x8600) {
> + if ((rsrc.start & 0xfffff) == 0x8600)
> setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
> - primary = 0;
> +
> +#if defined(CONFIG_PPC_MPC83XX_PCIE)
> + if (flags & PPC_83XX_PCIE) {
> + if (of_address_to_resource(dev, 1, &cfg_space)) {
> + printk("PCIE RC losts configure space. Skip it\n");
> + return 1;
> + }
> + mpc83xx_setup_pcie(hose, &rsrc, &cfg_space);
> }
> +#endif
>
> printk(KERN_INFO "Found MPC83xx PCI host bridge at 0x%016llx. "
> "Firmware bus number: %d->%d\n",
> @@ -86,6 +239,7 @@ int __init mpc83xx_add_bridge(struct device_node
> *dev)
> /* Interpret the "ranges" property */
> /* This also maps the I/O region and sets isa_io/mem_base */
> pci_process_bridge_OF_ranges(hose, dev, primary);
> + primary = 0;
>
> return 0;
> }
> --
> 1.5.2
>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [BUG] 2.6.24-rc3-git2 softlockup detected
From: Kamalesh Babulal @ 2007-11-30 7:28 UTC (permalink / raw)
To: Andrew Morton
Cc: Rafael J. Wysocki, linux-scsi, Matthew Wilcox, LKML,
Kyle McMartin, linuxppc-dev, Balbir Singh
In-Reply-To: <20071129230204.8698f47e.akpm@linux-foundation.org>
Andrew Morton wrote:
> On Thu, 29 Nov 2007 23:00:47 -0800 Andrew Morton <akpm@linux-foundation.org> wrote:
>
>> On Fri, 30 Nov 2007 01:39:29 -0500 Kyle McMartin <kyle@mcmartin.ca> wrote:
>>
>>> On Thu, Nov 29, 2007 at 12:35:33AM -0800, Andrew Morton wrote:
>>>> ten million is close enough to infinity for me to assume that we broke the
>>>> driver and that's never going to terminate.
>>>>
>>> how about this? doesn't break things on my pa8800:
>>>
>>> diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.c b/drivers/scsi/sym53c8xx_2/sym_hipd.c
>>> index 463f119..ef01cb1 100644
>>> --- a/drivers/scsi/sym53c8xx_2/sym_hipd.c
>>> +++ b/drivers/scsi/sym53c8xx_2/sym_hipd.c
>>> @@ -1037,10 +1037,13 @@ restart_test:
>>> /*
>>> * Wait 'til done (with timeout)
>>> */
>>> - for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
>>> + do {
>>> if (INB(np, nc_istat) & (INTF|SIP|DIP))
>>> break;
>>> - if (i>=SYM_SNOOP_TIMEOUT) {
>>> + msleep(10);
>>> + } while (i++ < SYM_SNOOP_TIMEOUT);
>>> +
>>> + if (i >= SYM_SNOOP_TIMEOUT) {
>>> printf ("CACHE TEST FAILED: timeout.\n");
>>> return (0x20);
>>> }
>>> diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.h b/drivers/scsi/sym53c8xx_2/sym_hipd.h
>>> index ad07880..85c483b 100644
>>> --- a/drivers/scsi/sym53c8xx_2/sym_hipd.h
>>> +++ b/drivers/scsi/sym53c8xx_2/sym_hipd.h
>>> @@ -339,7 +339,7 @@
>>> /*
>>> * Misc.
>>> */
>>> -#define SYM_SNOOP_TIMEOUT (10000000)
>>> +#define SYM_SNOOP_TIMEOUT (1000)
>>> #define BUS_8_BIT 0
>>> #define BUS_16_BIT 1
>>>
>> That might be the fix, but do we know what we're actually fixing? afaik
>> 2.6.24-rc3 doesn't get this timeout, 2.6.24-rc3-mm2 does get it and we
>> don't know why?
>>
>
> <looks at Subject:>
>
> <Checks that Rafael was cc'ed>
>
> So 2.6.24-rc3 was OK and 2.6.24-rc3-git2 is not?
Yes, the 2.6.24-rc3 was Ok and this is seen from 2.6.24-rc3-git2/3/4.
--
Thanks & Regards,
Kamalesh Babulal,
Linux Technology Center,
IBM, ISTL.
^ permalink raw reply
* Re: [BUG] 2.6.24-rc3-git2 softlockup detected
From: Andrew Morton @ 2007-11-30 7:02 UTC (permalink / raw)
To: Kyle McMartin, Kamalesh Babulal, LKML, linuxppc-dev,
Andy Whitcroft, Balbir Singh, linux-scsi, Rafael J. Wysocki,
Matthew Wilcox
In-Reply-To: <20071129230047.1b482562.akpm@linux-foundation.org>
On Thu, 29 Nov 2007 23:00:47 -0800 Andrew Morton <akpm@linux-foundation.org> wrote:
> On Fri, 30 Nov 2007 01:39:29 -0500 Kyle McMartin <kyle@mcmartin.ca> wrote:
>
> > On Thu, Nov 29, 2007 at 12:35:33AM -0800, Andrew Morton wrote:
> > > ten million is close enough to infinity for me to assume that we broke the
> > > driver and that's never going to terminate.
> > >
> >
> > how about this? doesn't break things on my pa8800:
> >
> > diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.c b/drivers/scsi/sym53c8xx_2/sym_hipd.c
> > index 463f119..ef01cb1 100644
> > --- a/drivers/scsi/sym53c8xx_2/sym_hipd.c
> > +++ b/drivers/scsi/sym53c8xx_2/sym_hipd.c
> > @@ -1037,10 +1037,13 @@ restart_test:
> > /*
> > * Wait 'til done (with timeout)
> > */
> > - for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
> > + do {
> > if (INB(np, nc_istat) & (INTF|SIP|DIP))
> > break;
> > - if (i>=SYM_SNOOP_TIMEOUT) {
> > + msleep(10);
> > + } while (i++ < SYM_SNOOP_TIMEOUT);
> > +
> > + if (i >= SYM_SNOOP_TIMEOUT) {
> > printf ("CACHE TEST FAILED: timeout.\n");
> > return (0x20);
> > }
> > diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.h b/drivers/scsi/sym53c8xx_2/sym_hipd.h
> > index ad07880..85c483b 100644
> > --- a/drivers/scsi/sym53c8xx_2/sym_hipd.h
> > +++ b/drivers/scsi/sym53c8xx_2/sym_hipd.h
> > @@ -339,7 +339,7 @@
> > /*
> > * Misc.
> > */
> > -#define SYM_SNOOP_TIMEOUT (10000000)
> > +#define SYM_SNOOP_TIMEOUT (1000)
> > #define BUS_8_BIT 0
> > #define BUS_16_BIT 1
> >
>
> That might be the fix, but do we know what we're actually fixing? afaik
> 2.6.24-rc3 doesn't get this timeout, 2.6.24-rc3-mm2 does get it and we
> don't know why?
>
<looks at Subject:>
<Checks that Rafael was cc'ed>
So 2.6.24-rc3 was OK and 2.6.24-rc3-git2 is not?
^ permalink raw reply
* Re: [BUG] 2.6.24-rc3-git2 softlockup detected
From: Andrew Morton @ 2007-11-30 7:00 UTC (permalink / raw)
To: Kyle McMartin
Cc: linux-scsi, Matthew, Wilcox, LKML, Kamalesh Babulal,
Rafael J. Wysocki, linuxppc-dev, Balbir Singh
In-Reply-To: <20071130063929.GD2754@fattire.cabal.ca>
On Fri, 30 Nov 2007 01:39:29 -0500 Kyle McMartin <kyle@mcmartin.ca> wrote:
> On Thu, Nov 29, 2007 at 12:35:33AM -0800, Andrew Morton wrote:
> > ten million is close enough to infinity for me to assume that we broke the
> > driver and that's never going to terminate.
> >
>
> how about this? doesn't break things on my pa8800:
>
> diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.c b/drivers/scsi/sym53c8xx_2/sym_hipd.c
> index 463f119..ef01cb1 100644
> --- a/drivers/scsi/sym53c8xx_2/sym_hipd.c
> +++ b/drivers/scsi/sym53c8xx_2/sym_hipd.c
> @@ -1037,10 +1037,13 @@ restart_test:
> /*
> * Wait 'til done (with timeout)
> */
> - for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
> + do {
> if (INB(np, nc_istat) & (INTF|SIP|DIP))
> break;
> - if (i>=SYM_SNOOP_TIMEOUT) {
> + msleep(10);
> + } while (i++ < SYM_SNOOP_TIMEOUT);
> +
> + if (i >= SYM_SNOOP_TIMEOUT) {
> printf ("CACHE TEST FAILED: timeout.\n");
> return (0x20);
> }
> diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.h b/drivers/scsi/sym53c8xx_2/sym_hipd.h
> index ad07880..85c483b 100644
> --- a/drivers/scsi/sym53c8xx_2/sym_hipd.h
> +++ b/drivers/scsi/sym53c8xx_2/sym_hipd.h
> @@ -339,7 +339,7 @@
> /*
> * Misc.
> */
> -#define SYM_SNOOP_TIMEOUT (10000000)
> +#define SYM_SNOOP_TIMEOUT (1000)
> #define BUS_8_BIT 0
> #define BUS_16_BIT 1
>
That might be the fix, but do we know what we're actually fixing? afaik
2.6.24-rc3 doesn't get this timeout, 2.6.24-rc3-mm2 does get it and we
don't know why?
^ permalink raw reply
* Re: [BUG] 2.6.24-rc3-git2 softlockup detected
From: Kyle McMartin @ 2007-11-30 6:39 UTC (permalink / raw)
To: Andrew Morton
Cc: linux-scsi, Matthew Wilcox, LKML, Kamalesh Babulal,
Rafael J. Wysocki, linuxppc-dev, Balbir Singh
In-Reply-To: <20071129003533.54b4b20e.akpm@linux-foundation.org>
On Thu, Nov 29, 2007 at 12:35:33AM -0800, Andrew Morton wrote:
> ten million is close enough to infinity for me to assume that we broke the
> driver and that's never going to terminate.
>
how about this? doesn't break things on my pa8800:
diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.c b/drivers/scsi/sym53c8xx_2/sym_hipd.c
index 463f119..ef01cb1 100644
--- a/drivers/scsi/sym53c8xx_2/sym_hipd.c
+++ b/drivers/scsi/sym53c8xx_2/sym_hipd.c
@@ -1037,10 +1037,13 @@ restart_test:
/*
* Wait 'til done (with timeout)
*/
- for (i=0; i<SYM_SNOOP_TIMEOUT; i++)
+ do {
if (INB(np, nc_istat) & (INTF|SIP|DIP))
break;
- if (i>=SYM_SNOOP_TIMEOUT) {
+ msleep(10);
+ } while (i++ < SYM_SNOOP_TIMEOUT);
+
+ if (i >= SYM_SNOOP_TIMEOUT) {
printf ("CACHE TEST FAILED: timeout.\n");
return (0x20);
}
diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.h b/drivers/scsi/sym53c8xx_2/sym_hipd.h
index ad07880..85c483b 100644
--- a/drivers/scsi/sym53c8xx_2/sym_hipd.h
+++ b/drivers/scsi/sym53c8xx_2/sym_hipd.h
@@ -339,7 +339,7 @@
/*
* Misc.
*/
-#define SYM_SNOOP_TIMEOUT (10000000)
+#define SYM_SNOOP_TIMEOUT (1000)
#define BUS_8_BIT 0
#define BUS_16_BIT 1
^ permalink raw reply related
* [PATCH 24/24] powerpc: Base support for 440SPe "Katmai" eval board
From: Benjamin Herrenschmidt @ 2007-11-30 6:11 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
This adds base support for the Katmai board, including PCI-X and
PCI-Express (but no RTC, nvram, etc... yet).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
As for Taishan, the bootwrapper code can be simplified. In fact,
we probably don't need to probe clocks & memsize off the chip and
just trust what uboot tells us.
arch/powerpc/boot/44x.h | 1
arch/powerpc/boot/Makefile | 7
arch/powerpc/boot/cuboot-katmai.c | 35 +++
arch/powerpc/boot/dts/katmai.dts | 392 ++++++++++++++++++++++++++++++++++++
arch/powerpc/boot/katmai.c | 64 +++++
arch/powerpc/platforms/44x/Kconfig | 12 +
arch/powerpc/platforms/44x/Makefile | 3
arch/powerpc/platforms/44x/katmai.c | 63 +++++
8 files changed, 574 insertions(+), 3 deletions(-)
Index: linux-work/arch/powerpc/platforms/44x/Kconfig
===================================================================
--- linux-work.orig/arch/powerpc/platforms/44x/Kconfig 2007-11-30 13:51:48.000000000 +1100
+++ linux-work/arch/powerpc/platforms/44x/Kconfig 2007-11-30 13:51:48.000000000 +1100
@@ -30,6 +30,14 @@ config TAISHAN
help
This option enables support for the IBM PPC440GX "Taishan" evaluation board.
+config KATMAI
+ bool "Katmai"
+ depends on 44x
+ default n
+ select 440SPe
+ help
+ This option enables support for the AMCC PPC440SPe evaluation board.
+
#config LUAN
# bool "Luan"
# depends on 44x
@@ -74,6 +82,10 @@ config 440GX
config 440SP
bool
+config 440SPe
+ select IBM_NEW_EMAC_EMAC4
+ bool
+
# 44x errata/workaround config symbols, selected by the CPU models above
config IBM440EP_ERR42
bool
Index: linux-work/arch/powerpc/platforms/44x/Makefile
===================================================================
--- linux-work.orig/arch/powerpc/platforms/44x/Makefile 2007-11-30 13:51:48.000000000 +1100
+++ linux-work/arch/powerpc/platforms/44x/Makefile 2007-11-30 13:51:48.000000000 +1100
@@ -1,5 +1,6 @@
obj-$(CONFIG_44x) := misc_44x.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_TAISHAN) += taishan.o
-obj-$(CONFIG_BAMBOO) += bamboo.o
+obj-$(CONFIG_BAMBOO) += bamboo.o
obj-$(CONFIG_SEQUOIA) += sequoia.o
+obj-$(CONFIG_KATMAI) += katmai.o
Index: linux-work/arch/powerpc/boot/dts/katmai.dts
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/boot/dts/katmai.dts 2007-11-30 14:46:02.000000000 +1100
@@ -0,0 +1,392 @@
+/*
+ * Device Tree Source for AMCC Bamboo
+ *
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *
+ * Copyright (c) 2006, 2007 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * FIXME: Draft only!
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "amcc,katmai";
+ compatible = "amcc,katmai";
+ dcr-parent = <&/cpus/PowerPC,440SPe@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,440SPe@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <20000>;
+ d-cache-size = <20000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-440spe","ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-440spe","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-440spe","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0e0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <a 4 b 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = "ibm,uic-440spe","ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0f0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <10 4 11 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ SDR0: sdr {
+ compatible = "ibm,sdr-440spe";
+ dcr-reg = <00e 002>;
+ };
+
+ CPR0: cpr {
+ compatible = "ibm,cpr-440spe";
+ dcr-reg = <00c 002>;
+ };
+
+ plb {
+ compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: sdram {
+ compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
+ dcr-reg = <180 62>;
+ num-tx-chans = <2>;
+ num-rx-chans = <1>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*TXEOB*/ 0 &UIC1 6 4
+ /*RXEOB*/ 1 &UIC1 7 4
+ /*SERR*/ 2 &UIC1 1 4
+ /*TXDE*/ 3 &UIC1 2 4
+ /*RXDE*/ 4 &UIC1 3 4>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <00000000 4 e0000000 20000000>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ ranges;
+ interrupts = <5 1>;
+ interrupt-parent = <&UIC1>;
+ };
+
+ UART0: serial@10000200 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <10000200 8>;
+ virtual-reg = <a0000200>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <1c200>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@10000300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <10000300 8>;
+ virtual-reg = <a0000300>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+
+ UART2: serial@10000600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <10000600 8>;
+ virtual-reg = <a0000600>;
+ clock-frequency = <0>;
+ current-speed = <0>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <5 4>;
+ };
+
+ IIC0: i2c@10000400 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
+ reg = <10000400 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@10000500 {
+ device_type = "i2c";
+ compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
+ reg = <10000500 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <3 4>;
+ };
+
+ EMAC0: ethernet@10000800 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-440spe", "ibm,emac4";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1c 4 1d 4>;
+ reg = <10000800 70>;
+ local-mac-address = [000000000000];
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "gmii";
+ phy-map = <00000000>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ };
+ };
+
+ PCIX0: pci@c0ec00000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
+ primary;
+ large-inbound-windows;
+ enable-msi-hole;
+ reg = <c 0ec00000 8 /* Config space access */
+ 0 0 0 /* no IACK cycles */
+ c 0ed00000 4 /* Special cycles */
+ c 0ec80000 100 /* Internal registers */
+ c 0ec80100 fc>; /* Internal messaging registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
+ 01000000 0 00000000 0000000c 08000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 0 to 0xf */
+ bus-range = <0 f>;
+
+ /*
+ * On Katmai, the following PCI-X interrupts signals
+ * have to be enabled via jumpers (only INTA is
+ * enabled per default):
+ *
+ * INTB: J3: 1-2
+ * INTC: J2: 1-2
+ * INTD: J1: 1-2
+ */
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 1 */
+ 0800 0 0 1 &UIC1 14 8
+ 0800 0 0 2 &UIC1 13 8
+ 0800 0 0 3 &UIC1 12 8
+ 0800 0 0 4 &UIC1 11 8
+ >;
+ };
+
+ PCIE0: pciex@d00000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
+ primary;
+ port = <0>; /* port number */
+ reg = <d 00000000 20000000 /* Config space access */
+ c 10000000 00001000>; /* Registers */
+ dcr-reg = <100 020>;
+ sdr-base = <300>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
+ 01000000 0 00000000 0000000f 80000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 10 to 0x1f */
+ bus-range = <10 1f>;
+
+ /* Legacy interrupts (note the weird polarity). We are
+ * de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers. The real slot is
+ * on idsel 1, so the swizzling is new_pin = (pin % 4) + 1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 2 &UIC3 0 4 /* swizzled int A */
+ 0000 0 0 3 &UIC3 1 4 /* swizzled int B */
+ 0000 0 0 4 &UIC3 2 4 /* swizzled int C */
+ 0000 0 0 1 &UIC3 3 4 /* swizzled int D */>;
+ };
+
+ PCIE1: pciex@d20000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
+ primary;
+ port = <0>; /* port number */
+ reg = <d 20000000 20000000 /* Config space access */
+ c 10001000 00001000>; /* Registers */
+ dcr-reg = <120 020>;
+ sdr-base = <340>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
+ 01000000 0 00000000 0000000f 80010000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 10 to 0x1f */
+ bus-range = <20 2f>;
+
+ /* Legacy interrupts (note the weird polarity). We are
+ * de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers. The real slot is
+ * on idsel 1, so the swizzling is new_pin = (pin % 4) + 1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 2 &UIC3 4 4 /* swizzled int A */
+ 0000 0 0 3 &UIC3 5 4 /* swizzled int B */
+ 0000 0 0 4 &UIC3 6 4 /* swizzled int C */
+ 0000 0 0 1 &UIC3 7 4 /* swizzled int D */>;
+ };
+
+ PCIE2: pciex@d40000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
+ primary;
+ port = <0>; /* port number */
+ reg = <d 40000000 20000000 /* Config space access */
+ c 10002000 00001000>; /* Registers */
+ dcr-reg = <140 020>;
+ sdr-base = <370>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 0000000f 00000000 0 80000000
+ 01000000 0 00000000 0000000f 80020000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* This drives busses 10 to 0x1f */
+ bus-range = <30 3f>;
+
+ /* Legacy interrupts (note the weird polarity). We are
+ * de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers. The real slot is
+ * on idsel 1, so the swizzling is new_pin = (pin % 4) + 1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 2 &UIC3 8 4 /* swizzled int A */
+ 0000 0 0 3 &UIC3 9 4 /* swizzled int B */
+ 0000 0 0 4 &UIC3 a 4 /* swizzled int C */
+ 0000 0 0 1 &UIC3 b 4 /* swizzled int D */>;
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@10000200";
+ };
+};
Index: linux-work/arch/powerpc/platforms/44x/katmai.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/platforms/44x/katmai.c 2007-11-30 13:51:48.000000000 +1100
@@ -0,0 +1,63 @@
+/*
+ * Katmai board specific routines
+ *
+ * Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ * Copyright 2007 IBM Corp.
+ *
+ * Based on the Bamboo code by
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ * Copyright 2007 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/time.h>
+#include <asm/uic.h>
+
+#include "44x.h"
+
+static struct of_device_id katmai_of_bus[] = {
+ { .compatible = "ibm,plb4", },
+ { .compatible = "ibm,opb", },
+ { .compatible = "ibm,ebc", },
+ {},
+};
+
+static int __init katmai_device_probe(void)
+{
+ if (!machine_is(katmai))
+ return 0;
+
+ of_platform_bus_probe(NULL, katmai_of_bus, NULL);
+
+ return 0;
+}
+device_initcall(katmai_device_probe);
+
+static int __init katmai_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (!of_flat_dt_is_compatible(root, "amcc,katmai"))
+ return 0;
+
+ return 1;
+}
+
+define_machine(katmai) {
+ .name = "Katmai",
+ .probe = katmai_probe,
+ .progress = udbg_progress,
+ .init_IRQ = uic_init_tree,
+ .get_irq = uic_get_irq,
+ .restart = ppc44x_reset_system,
+ .calibrate_decr = generic_calibrate_decr,
+};
Index: linux-work/arch/powerpc/boot/44x.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/44x.h 2007-11-30 13:51:48.000000000 +1100
+++ linux-work/arch/powerpc/boot/44x.h 2007-11-30 13:51:48.000000000 +1100
@@ -13,5 +13,6 @@
void ebony_init(void *mac0, void *mac1);
void bamboo_init(void *mac0, void *mac1);
void taishan_init(void *mac0, void *mac1);
+void katmai_init(void *mac);
#endif /* _PPC_BOOT_44X_H_ */
Index: linux-work/arch/powerpc/boot/cuboot-katmai.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/boot/cuboot-katmai.c 2007-11-30 13:51:48.000000000 +1100
@@ -0,0 +1,35 @@
+/*
+ * Old U-boot compatibility for Katmai
+ *
+ * Author: Hugh Blemings <hugh@au.ibm.com>
+ *
+ * Copyright 2007 Hugh Blemings, IBM Corporation.
+ * Based on cuboot-ebony.c which is:
+ * Copyright 2007 David Gibson, IBM Corporation.
+ * Based on cuboot-83xx.c, which is:
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_44x
+#include "ppcboot.h"
+
+static bd_t bd;
+
+BSS_STACK(4096);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+
+ katmai_init(&bd.bi_enetaddr);
+}
Index: linux-work/arch/powerpc/boot/katmai.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/boot/katmai.c 2007-11-30 13:51:48.000000000 +1100
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2007 David Gibson, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (C) Paul Mackerras 1997.
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "string.h"
+#include "stdio.h"
+#include "page.h"
+#include "ops.h"
+#include "reg.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "44x.h"
+
+
+extern char _dtb_start[];
+extern char _dtb_end[];
+
+static u8 *katmai_mac;
+
+
+
+static void katmai_fixups(void)
+{
+ unsigned long sysclk = 33333000;
+
+ printf("Boo !\n");
+
+ /* 440SP Clock logic is all but identical to 440GX
+ * so we just use that code for now at least
+ */
+ ibm440spe_fixup_clocks(sysclk, 6 * 1843200, 0);
+
+ ibm440spe_fixup_memsize();
+
+ dt_fixup_mac_address(0, katmai_mac);
+
+ ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
+}
+
+void katmai_init(void *mac)
+{
+ platform_ops.fixups = katmai_fixups;
+// platform_ops.exit = ibm44x_dbcr_reset; **FIXME**
+ katmai_mac = mac;
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+ serial_console_init();
+}
Index: linux-work/arch/powerpc/boot/Makefile
===================================================================
--- linux-work.orig/arch/powerpc/boot/Makefile 2007-11-30 13:51:48.000000000 +1100
+++ linux-work/arch/powerpc/boot/Makefile 2007-11-30 13:51:48.000000000 +1100
@@ -38,6 +38,7 @@ BOOTCFLAGS += -I$(obj) -I$(srctree)/$(ob
$(obj)/4xx.o: BOOTCFLAGS += -mcpu=440
$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440
$(obj)/taishan.o: BOOTCFLAGS += -mcpu=440
+$(obj)/katmai.o: BOOTCFLAGS += -mcpu=440
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
@@ -53,12 +54,13 @@ src-wlib := string.S crt0.S stdio.c main
gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
- fsl-soc.c mpc8xx.c pq2.c taishan.c
+ fsl-soc.c mpc8xx.c pq2.c taishan.c katmai.c
src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
- fixed-head.S ep88xc.c cuboot-hpc2.c ep405.c cuboot-taishan.c
+ fixed-head.S ep88xc.c cuboot-hpc2.c ep405.c cuboot-taishan.c \
+ cuboot-katmai.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -163,6 +165,7 @@ image-$(CONFIG_BAMBOO) += treeImage.ba
#image-$(CONFIG_SEQUOIA) += cuImage.sequoia
image-$(CONFIG_WALNUT) += treeImage.walnut
image-$(CONFIG_TAISHAN) += cuImage.taishan
+image-$(CONFIG_KATMAI) += cuImage.katmai
endif
# For 32-bit powermacs, build the COFF and miboot images
^ permalink raw reply
* [PATCH 23/24] powerpc: Rework 4xx clock probing in boot wrapper
From: Benjamin Herrenschmidt @ 2007-11-30 6:11 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
This reworks the boot wrapper library function that probes
the chip clocks. Better separate the base function that is
used on 440GX,SPe,EP,... from the uart fixups as those need
different device-tree path on different processors.
Also, rework the function itself based on the arch/ppc code
from Eugene Surovegin which I find more readable, and which
handles one more bypass case.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/boot/4xx.c | 272 +++++++++++++++++++++++++++----------
arch/powerpc/boot/4xx.h | 11 +
arch/powerpc/boot/bamboo.c | 2
arch/powerpc/boot/cuboot-sequoia.c | 4
arch/powerpc/boot/dcr.h | 17 ++
arch/powerpc/boot/ebony.c | 60 --------
arch/powerpc/boot/reg.h | 8 +
arch/powerpc/boot/taishan.c | 4
8 files changed, 242 insertions(+), 136 deletions(-)
Index: linux-work/arch/powerpc/boot/4xx.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/4xx.c 2007-11-27 18:11:36.000000000 +1100
+++ linux-work/arch/powerpc/boot/4xx.c 2007-11-27 18:19:21.000000000 +1100
@@ -275,89 +275,225 @@ void ibm4xx_fixup_ebc_ranges(const char
setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
}
-#define SPRN_CCR1 0x378
-void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
+/* Calculate 440GP clocks */
+void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
{
- u32 cpu, plb, opb, ebc, tb, uart0, m, vco;
- u32 reg;
- u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp;
-
- mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0);
- reg = mfdcr(DCRN_CPR0_DATA);
- tmp = (reg & 0x000F0000) >> 16;
- fwdva = tmp ? tmp : 16;
- tmp = (reg & 0x00000700) >> 8;
- fwdvb = tmp ? tmp : 8;
- tmp = (reg & 0x1F000000) >> 24;
- fbdv = tmp ? tmp : 32;
- lfbdv = (reg & 0x0000007F);
-
- mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0);
- reg = mfdcr(DCRN_CPR0_DATA);
- tmp = (reg & 0x03000000) >> 24;
- opbdv0 = tmp ? tmp : 4;
-
- mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0);
- reg = mfdcr(DCRN_CPR0_DATA);
- tmp = (reg & 0x07000000) >> 24;
- perdv0 = tmp ? tmp : 8;
-
- mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0);
- reg = mfdcr(DCRN_CPR0_DATA);
- tmp = (reg & 0x07000000) >> 24;
- prbdv0 = tmp ? tmp : 8;
-
- mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID);
- reg = mfdcr(DCRN_CPR0_DATA);
- tmp = (reg & 0x03000000) >> 24;
- spcid0 = tmp ? tmp : 4;
-
- /* Calculate M */
- mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0);
- reg = mfdcr(DCRN_CPR0_DATA);
- tmp = (reg & 0x03000000) >> 24;
- if (tmp == 0) { /* PLL output */
- tmp = (reg & 0x20000000) >> 29;
- if (!tmp) /* PLLOUTA */
- m = fbdv * lfbdv * fwdva;
+ u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
+ u32 cr0 = mfdcr(DCRN_CPC0_CR0);
+ u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
+ u32 opdv = CPC0_SYS0_OPDV(sys0);
+ u32 epdv = CPC0_SYS0_EPDV(sys0);
+
+ if (sys0 & CPC0_SYS0_BYPASS) {
+ /* Bypass system PLL */
+ cpu = plb = sys_clk;
+ } else {
+ if (sys0 & CPC0_SYS0_EXTSL)
+ /* PerClk */
+ m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
else
- m = fbdv * lfbdv * fwdvb;
+ /* CPU clock */
+ m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
+ cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0);
+ plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0);
}
- else if (tmp == 1) /* CPU output */
- m = fbdv * fwdva;
+
+ opb = plb / opdv;
+ ebc = opb / epdv;
+
+ /* FIXME: Check if this is for all 440GP, or just Ebony */
+ if ((mfpvr() & 0xf0000fff) == 0x40000440)
+ /* Rev. B 440GP, use external system clock */
+ tb = sys_clk;
else
- m = perdv0 * opbdv0 * fwdvb;
+ /* Rev. C 440GP, errata force us to use internal clock */
+ tb = cpu;
- vco = (m * sysclk) + (m >> 1);
- cpu = vco / fwdva;
- plb = vco / fwdvb / prbdv0;
- opb = plb / opbdv0;
- ebc = plb / perdv0;
+ if (cr0 & CPC0_CR0_U0EC)
+ /* External UART clock */
+ uart0 = ser_clk;
+ else
+ /* Internal UART clock */
+ uart0 = plb / CPC0_CR0_UDIV(cr0);
- /* FIXME */
- uart0 = ser_clk;
+ if (cr0 & CPC0_CR0_U1EC)
+ /* External UART clock */
+ uart1 = ser_clk;
+ else
+ /* Internal UART clock */
+ uart1 = plb / CPC0_CR0_UDIV(cr0);
+
+ printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
+ (sys_clk + 500000) / 1000000, sys_clk);
+
+ dt_fixup_cpu_clocks(cpu, tb, 0);
+
+ dt_fixup_clock("/plb", plb);
+ dt_fixup_clock("/plb/opb", opb);
+ dt_fixup_clock("/plb/opb/ebc", ebc);
+ dt_fixup_clock("/plb/opb/serial@40000200", uart0);
+ dt_fixup_clock("/plb/opb/serial@40000300", uart1);
+}
+
+#define SPRN_CCR1 0x378
+
+static inline u32 __fix_zero(u32 v, u32 def)
+{
+ return v ? v : def;
+}
+
+static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk,
+ unsigned int tmr_clk)
+{
+ /* PLL config */
+ u32 pllc = CPR0_READ(DCRN_CPR0_PLLC);
+ u32 plld = CPR0_READ(DCRN_CPR0_PLLD);
+
+ /* Dividers */
+ u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32);
+ u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16);
+ u32 fwdvb = __fix_zero((plld >> 8) & 7, 8);
+ u32 lfbdv = __fix_zero(plld & 0x3f, 64);
+ u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8);
+ u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8);
+ u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4);
+ u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4);
+
+ /* Input clocks for primary dividers */
+ u32 clk_a, clk_b;
+
+ /* Resulting clocks */
+ u32 cpu, plb, opb, ebc, vco;
+
+ /* Timebase */
+ u32 ccr1, tb = tmr_clk;
+
+ if (pllc & 0x40000000){
+ u32 m;
+
+ /* Feedback path */
+ switch ((pllc >> 24) & 7){
+ case 0:
+ /* PLLOUTx */
+ m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
+ break;
+ case 1:
+ /* CPU */
+ m = fwdva * pradv0;
+ break;
+ case 5:
+ /* PERClk */
+ m = fwdvb * prbdv0 * opbdv0 * perdv0;
+ break;
+ default:
+ printf("WARNING ! Invalid PLL feedback source !\n");
+ goto bypass;
+ }
+ m *= fbdv;
+ vco = sys_clk * m;
+ clk_a = vco / fwdva;
+ clk_b = vco / fwdvb;
+ }
+ else {
+bypass:
+ /* Bypass system PLL */
+ vco = 0;
+ clk_a = clk_b = sys_clk;
+ }
+
+ cpu = clk_a / pradv0;
+ plb = clk_b / prbdv0;
+ opb = plb / opbdv0;
+ ebc = opb / perdv0;
/* Figure out timebase. Either CPU or default TmrClk */
- asm volatile (
- "mfspr %0,%1\n"
- :
- "=&r"(reg) : "i"(SPRN_CCR1));
- if (reg & 0x0080)
- tb = 25000000; /* TmrClk is 25MHz */
- else
+ ccr1 = mfspr(SPRN_CCR1);
+
+ /* If passed a 0 tmr_clk, force CPU clock */
+ if (tb == 0) {
+ ccr1 &= ~0x80u;
+ mtspr(SPRN_CCR1, ccr1);
+ }
+ if ((ccr1 & 0x0080) == 0)
tb = cpu;
dt_fixup_cpu_clocks(cpu, tb, 0);
dt_fixup_clock("/plb", plb);
dt_fixup_clock("/plb/opb", opb);
dt_fixup_clock("/plb/opb/ebc", ebc);
- dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
- dt_fixup_clock("/plb/opb/serial@ef600400", uart0);
- dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
- dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
+
+ return plb;
+}
+
+static void eplike_fixup_uart_clk(int index, const char *path,
+ unsigned int ser_clk,
+ unsigned int plb_clk)
+{
+ unsigned int sdr;
+ unsigned int clock;
+
+ switch(index) {
+ case 0:
+ sdr = SDR0_READ(DCRN_SDR0_UART0);
+ break;
+ case 1:
+ sdr = SDR0_READ(DCRN_SDR0_UART1);
+ break;
+ case 2:
+ sdr = SDR0_READ(DCRN_SDR0_UART2);
+ break;
+ case 3:
+ sdr = SDR0_READ(DCRN_SDR0_UART3);
+ break;
+ default:
+ return;
+ }
+
+ if (sdr & 0x00800000u)
+ clock = ser_clk;
+ else
+ clock = plb_clk / __fix_zero(sdr & 0xff, 256);
+
+ dt_fixup_clock(path, clock);
+}
+
+void ibm440ep_fixup_clocks(unsigned int sys_clk,
+ unsigned int ser_clk,
+ unsigned int tmr_clk)
+{
+ unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk);
+
+ /* serial clocks beed fixup based on int/ext */
+ eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
+}
+
+void ibm440gx_fixup_clocks(unsigned int sys_clk,
+ unsigned int ser_clk,
+ unsigned int tmr_clk)
+{
+ unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk);
+
+ /* serial clocks beed fixup based on int/ext */
+ eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
+}
+
+void ibm440spe_fixup_clocks(unsigned int sys_clk,
+ unsigned int ser_clk,
+ unsigned int tmr_clk)
+{
+ unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk);
+
+ /* serial clocks beed fixup based on int/ext */
+ eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk);
+ eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk);
}
-void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
+void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
{
u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
@@ -374,7 +510,7 @@ void ibm405gp_fixup_clocks(unsigned int
m = fwdv * fbdv * cbdv;
- cpu = sysclk * m / fwdv;
+ cpu = sys_clk * m / fwdv;
plb = cpu / cbdv;
opb = plb / opdv;
ebc = plb / epdv;
Index: linux-work/arch/powerpc/boot/4xx.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/4xx.h 2007-11-27 18:12:01.000000000 +1100
+++ linux-work/arch/powerpc/boot/4xx.h 2007-11-27 18:19:54.000000000 +1100
@@ -18,7 +18,14 @@ void ibm44x_dbcr_reset(void);
void ibm40x_dbcr_reset(void);
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
void ibm4xx_fixup_ebc_ranges(const char *ebc);
-void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
-void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
+
+void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
+void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk);
+void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
+ unsigned int tmr_clk);
+void ibm440gx_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
+ unsigned int tmr_clk);
+void ibm440spe_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk,
+ unsigned int tmr_clk);
#endif /* _POWERPC_BOOT_4XX_H_ */
Index: linux-work/arch/powerpc/boot/ebony.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/ebony.c 2007-11-27 18:12:22.000000000 +1100
+++ linux-work/arch/powerpc/boot/ebony.c 2007-11-27 18:19:21.000000000 +1100
@@ -31,66 +31,6 @@
static u8 *ebony_mac0, *ebony_mac1;
-/* Calculate 440GP clocks */
-void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
-{
- u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
- u32 cr0 = mfdcr(DCRN_CPC0_CR0);
- u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
- u32 opdv = CPC0_SYS0_OPDV(sys0);
- u32 epdv = CPC0_SYS0_EPDV(sys0);
-
- if (sys0 & CPC0_SYS0_BYPASS) {
- /* Bypass system PLL */
- cpu = plb = sysclk;
- } else {
- if (sys0 & CPC0_SYS0_EXTSL)
- /* PerClk */
- m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
- else
- /* CPU clock */
- m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
- cpu = sysclk * m / CPC0_SYS0_FWDVA(sys0);
- plb = sysclk * m / CPC0_SYS0_FWDVB(sys0);
- }
-
- opb = plb / opdv;
- ebc = opb / epdv;
-
- /* FIXME: Check if this is for all 440GP, or just Ebony */
- if ((mfpvr() & 0xf0000fff) == 0x40000440)
- /* Rev. B 440GP, use external system clock */
- tb = sysclk;
- else
- /* Rev. C 440GP, errata force us to use internal clock */
- tb = cpu;
-
- if (cr0 & CPC0_CR0_U0EC)
- /* External UART clock */
- uart0 = ser_clk;
- else
- /* Internal UART clock */
- uart0 = plb / CPC0_CR0_UDIV(cr0);
-
- if (cr0 & CPC0_CR0_U1EC)
- /* External UART clock */
- uart1 = ser_clk;
- else
- /* Internal UART clock */
- uart1 = plb / CPC0_CR0_UDIV(cr0);
-
- printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
- (sysclk + 500000) / 1000000, sysclk);
-
- dt_fixup_cpu_clocks(cpu, tb, 0);
-
- dt_fixup_clock("/plb", plb);
- dt_fixup_clock("/plb/opb", opb);
- dt_fixup_clock("/plb/opb/ebc", ebc);
- dt_fixup_clock("/plb/opb/serial@40000200", uart0);
- dt_fixup_clock("/plb/opb/serial@40000300", uart1);
-}
-
#define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
#define EBONY_FPGA_FLASH_SEL 0x01
#define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
Index: linux-work/arch/powerpc/boot/taishan.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/taishan.c 2007-11-27 18:12:35.000000000 +1100
+++ linux-work/arch/powerpc/boot/taishan.c 2007-11-27 18:20:37.000000000 +1100
@@ -42,9 +42,7 @@ static void taishan_fixups(void)
registers */
unsigned long sysclk = 33000000;
- /* 440EP Clock logic is all but identical to 440GX
- so we just use that code for now at least */
- ibm440ep_fixup_clocks(sysclk, 6 * 1843200);
+ ibm440gx_fixup_clocks(sysclk, 6 * 1843200, 25000000);
ibm4xx_sdram_fixup_memsize();
Index: linux-work/arch/powerpc/boot/dcr.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/dcr.h 2007-11-27 18:13:45.000000000 +1100
+++ linux-work/arch/powerpc/boot/dcr.h 2007-11-27 18:19:21.000000000 +1100
@@ -165,6 +165,23 @@ static const unsigned long sdram_bxcr[]
//#define CPC0_SYS0_FWDVA_MASK 0x00038000
+#define DCRN_SDR0_CONFIG_ADDR 0xe
+#define DCRN_SDR0_CONFIG_DATA 0xf
+
+/* SDR read/write helper macros */
+#define SDR0_READ(offset) ({\
+ mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
+ mfdcr(DCRN_SDR0_CONFIG_DATA);})
+#define SDR0_WRITE(offset, data) ({\
+ mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
+ mtdcr(DCRN_SDR0_CONFIG_DATA,data);})
+
+#define DCRN_SDR0_UART0 0x0120
+#define DCRN_SDR0_UART1 0x0121
+#define DCRN_SDR0_UART2 0x0122
+#define DCRN_SDR0_UART3 0x0123
+
+
/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
#define DCRN_CPR0_CFGADDR 0xc
Index: linux-work/arch/powerpc/boot/reg.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/reg.h 2007-11-27 18:18:15.000000000 +1100
+++ linux-work/arch/powerpc/boot/reg.h 2007-11-27 18:19:21.000000000 +1100
@@ -24,6 +24,14 @@ static inline u32 mfpvr(void)
: "=r" (rval)); rval;})
#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
+#define __stringify_1(x) #x
+#define __stringify(x) __stringify_1(x)
+
+#define mfspr(rn) ({unsigned long rval; \
+ asm volatile("mfspr %0," __stringify(rn) \
+ : "=r" (rval)); rval;})
+#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
+
register void *__stack_pointer asm("r1");
#define get_sp() (__stack_pointer)
Index: linux-work/arch/powerpc/boot/bamboo.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/bamboo.c 2007-11-27 18:14:36.000000000 +1100
+++ linux-work/arch/powerpc/boot/bamboo.c 2007-11-27 18:21:00.000000000 +1100
@@ -30,7 +30,7 @@ static void bamboo_fixups(void)
{
unsigned long sysclk = 33333333;
- ibm440ep_fixup_clocks(sysclk, 11059200);
+ ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
ibm4xx_sdram_fixup_memsize();
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
Index: linux-work/arch/powerpc/boot/cuboot-sequoia.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/cuboot-sequoia.c 2007-11-27 18:07:50.000000000 +1100
+++ linux-work/arch/powerpc/boot/cuboot-sequoia.c 2007-11-27 18:21:16.000000000 +1100
@@ -39,8 +39,8 @@ static void sequoia_fixups(void)
{
unsigned long sysclk = 33333333;
- ibm440ep_fixup_clocks(sysclk, 11059200);
- ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
+ ibm440ep_fixup_clocks(sysclk, 11059200, 25000000);
+ ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
ibm4xx_denali_fixup_memsize();
dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
}
^ permalink raw reply
* [PATCH 22/24] powerpc: Add mfspr/mtspr inline macros to 4xx bootwrapper
From: Benjamin Herrenschmidt @ 2007-11-30 6:11 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
The 4xx bootwrapper occasionally needs to access SPR registers,
this adds mfspr/mtspr wrappers to it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
===================================================================
--- linux-work.orig/arch/powerpc/boot/reg.h 2007-11-27 14:37:00.000000000 +1100
+++ linux-work/arch/powerpc/boot/reg.h 2007-11-27 14:37:58.000000000 +1100
@@ -16,6 +16,14 @@ static inline u32 mfpvr(void)
return pvr;
}
+#define __stringify_1(x) #x
+#define __stringify(x) __stringify_1(x)
+
+#define mfspr(rn) ({unsigned long rval; \
+ asm volatile("mfspr %0," __stringify(rn) \
+ : "=r" (rval)); rval;})
+#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
+
register void *__stack_pointer asm("r1");
#define get_sp() (__stack_pointer)
^ permalink raw reply
* [PATCH 21/24] powerpc: Adds decoding of 440SPE memory size to boot wrapper library
From: Benjamin Herrenschmidt @ 2007-11-30 6:11 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
This adds a function to the bootwrapper 4xx library to decode memory
size on 440SPE processors.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/boot/4xx.c | 85 +++++++++++++++++++++++++++++-------
arch/powerpc/boot/4xx.h | 3 -
arch/powerpc/boot/bamboo.c | 2
arch/powerpc/boot/dcr.h | 10 +++-
arch/powerpc/boot/ebony.c | 2
arch/powerpc/boot/taishan.c | 2
arch/powerpc/boot/treeboot-walnut.c | 2
7 files changed, 85 insertions(+), 21 deletions(-)
Index: linux-work/arch/powerpc/boot/4xx.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/4xx.c 2007-11-27 18:07:50.000000000 +1100
+++ linux-work/arch/powerpc/boot/4xx.c 2007-11-27 18:11:36.000000000 +1100
@@ -22,16 +22,14 @@
#include "dcr.h"
/* Read the 4xx SDRAM controller to get size of system memory. */
-void ibm4xx_fixup_memsize(void)
+void ibm4xx_sdram_fixup_memsize(void)
{
int i;
unsigned long memsize, bank_config;
memsize = 0;
for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
- mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
- bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
-
+ bank_config = SDRAM0_READ(sdram_bxcr[i]);
if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
}
@@ -39,6 +37,69 @@ void ibm4xx_fixup_memsize(void)
dt_fixup_memory(0, memsize);
}
+/* Read the 440SPe MQ controller to get size of system memory. */
+#define DCRN_MQ0_B0BAS 0x40
+#define DCRN_MQ0_B1BAS 0x41
+#define DCRN_MQ0_B2BAS 0x42
+#define DCRN_MQ0_B3BAS 0x43
+
+static u64 ibm440spe_decode_bas(u32 bas)
+{
+ u64 base = ((u64)(bas & 0xFFE00000u)) << 2;
+
+ /* open coded because I'm paranoid about invalid values */
+ switch((bas >> 4) & 0xFFF) {
+ case 0:
+ return 0;
+ case 0xffc:
+ return base + 0x000800000ull;
+ case 0xff8:
+ return base + 0x001000000ull;
+ case 0xff0:
+ return base + 0x002000000ull;
+ case 0xfe0:
+ return base + 0x004000000ull;
+ case 0xfc0:
+ return base + 0x008000000ull;
+ case 0xf80:
+ return base + 0x010000000ull;
+ case 0xf00:
+ return base + 0x020000000ull;
+ case 0xe00:
+ return base + 0x040000000ull;
+ case 0xc00:
+ return base + 0x080000000ull;
+ case 0x800:
+ return base + 0x100000000ull;
+ }
+ printf("Memory BAS value 0x%08x unsupported !\n", bas);
+ return 0;
+}
+
+void ibm440spe_fixup_memsize(void)
+{
+ u64 banktop, memsize = 0;
+
+ /* Ultimately, we should directly construct the memory node
+ * so we are able to handle holes in the memory address space
+ */
+ banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));
+ if (banktop > memsize)
+ memsize = banktop;
+ banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));
+ if (banktop > memsize)
+ memsize = banktop;
+ banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));
+ if (banktop > memsize)
+ memsize = banktop;
+ banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));
+ if (banktop > memsize)
+ memsize = banktop;
+
+ dt_fixup_memory(0, memsize);
+}
+
+
/* 4xx DDR1/2 Denali memory controller support */
/* DDR0 registers */
#define DDR0_02 2
@@ -77,19 +138,13 @@ void ibm4xx_fixup_memsize(void)
#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
-static inline u32 mfdcr_sdram0(u32 reg)
-{
- mtdcr(DCRN_SDRAM0_CFGADDR, reg);
- return mfdcr(DCRN_SDRAM0_CFGDATA);
-}
-
void ibm4xx_denali_fixup_memsize(void)
{
u32 val, max_cs, max_col, max_row;
u32 cs, col, row, bank, dpath;
unsigned long memsize;
- val = mfdcr_sdram0(DDR0_02);
+ val = SDRAM0_READ(DDR0_02);
if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
fatal("DDR controller is not initialized\n");
@@ -99,7 +154,7 @@ void ibm4xx_denali_fixup_memsize(void)
max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
/* get CS value */
- val = mfdcr_sdram0(DDR0_10);
+ val = SDRAM0_READ(DDR0_10);
val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
cs = 0;
@@ -115,7 +170,7 @@ void ibm4xx_denali_fixup_memsize(void)
fatal("DDR wrong CS configuration\n");
/* get data path bytes */
- val = mfdcr_sdram0(DDR0_14);
+ val = SDRAM0_READ(DDR0_14);
if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
dpath = 8; /* 64 bits */
@@ -123,7 +178,7 @@ void ibm4xx_denali_fixup_memsize(void)
dpath = 4; /* 32 bits */
/* get adress pins (rows) */
- val = mfdcr_sdram0(DDR0_42);
+ val = SDRAM0_READ(DDR0_42);
row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
if (row > max_row)
@@ -131,7 +186,7 @@ void ibm4xx_denali_fixup_memsize(void)
row = max_row - row;
/* get collomn size and banks */
- val = mfdcr_sdram0(DDR0_43);
+ val = SDRAM0_READ(DDR0_43);
col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
if (col > max_col)
Index: linux-work/arch/powerpc/boot/4xx.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/4xx.h 2007-11-27 18:11:57.000000000 +1100
+++ linux-work/arch/powerpc/boot/4xx.h 2007-11-27 18:12:01.000000000 +1100
@@ -11,7 +11,8 @@
#ifndef _POWERPC_BOOT_4XX_H_
#define _POWERPC_BOOT_4XX_H_
-void ibm4xx_fixup_memsize(void);
+void ibm4xx_sdram_fixup_memsize(void);
+void ibm440spe_fixup_memsize(void);
void ibm4xx_denali_fixup_memsize(void);
void ibm44x_dbcr_reset(void);
void ibm40x_dbcr_reset(void);
Index: linux-work/arch/powerpc/boot/bamboo.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/bamboo.c 2007-11-27 18:14:29.000000000 +1100
+++ linux-work/arch/powerpc/boot/bamboo.c 2007-11-27 18:14:36.000000000 +1100
@@ -31,7 +31,7 @@ static void bamboo_fixups(void)
unsigned long sysclk = 33333333;
ibm440ep_fixup_clocks(sysclk, 11059200);
- ibm4xx_fixup_memsize();
+ ibm4xx_sdram_fixup_memsize();
ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00);
dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1);
}
Index: linux-work/arch/powerpc/boot/dcr.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/dcr.h 2007-11-27 18:13:12.000000000 +1100
+++ linux-work/arch/powerpc/boot/dcr.h 2007-11-27 18:13:45.000000000 +1100
@@ -14,12 +14,20 @@
#define DCRN_SDRAM0_CFGADDR 0x010
#define DCRN_SDRAM0_CFGDATA 0x011
+#define SDRAM0_READ(offset) ({\
+ mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
+ mfdcr(DCRN_SDRAM0_CFGDATA);})
+#define SDRAM0_WRITE(offset, data) ({\
+ mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
+ mtdcr(DCRN_SDRAM0_CFGDATA, data);})
+
#define SDRAM0_B0CR 0x40
#define SDRAM0_B1CR 0x44
#define SDRAM0_B2CR 0x48
#define SDRAM0_B3CR 0x4c
-static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR };
+static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
+ SDRAM0_B2CR, SDRAM0_B3CR };
#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
Index: linux-work/arch/powerpc/boot/ebony.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/ebony.c 2007-11-27 18:12:20.000000000 +1100
+++ linux-work/arch/powerpc/boot/ebony.c 2007-11-27 18:12:22.000000000 +1100
@@ -134,7 +134,7 @@ static void ebony_fixups(void)
unsigned long sysclk = 33000000;
ibm440gp_fixup_clocks(sysclk, 6 * 1843200);
- ibm4xx_fixup_memsize();
+ ibm4xx_sdram_fixup_memsize();
dt_fixup_mac_addresses(ebony_mac0, ebony_mac1);
ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
ebony_flashsel_fixup();
Index: linux-work/arch/powerpc/boot/taishan.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/taishan.c 2007-11-27 18:12:31.000000000 +1100
+++ linux-work/arch/powerpc/boot/taishan.c 2007-11-27 18:12:35.000000000 +1100
@@ -46,7 +46,7 @@ static void taishan_fixups(void)
so we just use that code for now at least */
ibm440ep_fixup_clocks(sysclk, 6 * 1843200);
- ibm4xx_fixup_memsize();
+ ibm4xx_sdram_fixup_memsize();
dt_fixup_mac_addresses(taishan_mac0, taishan_mac1);
Index: linux-work/arch/powerpc/boot/treeboot-walnut.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/treeboot-walnut.c 2007-11-27 18:14:55.000000000 +1100
+++ linux-work/arch/powerpc/boot/treeboot-walnut.c 2007-11-27 18:15:02.000000000 +1100
@@ -63,7 +63,7 @@ static void walnut_flashsel_fixup(void)
#define WALNUT_OPENBIOS_MAC_OFF 0xfffffe0b
static void walnut_fixups(void)
{
- ibm4xx_fixup_memsize();
+ ibm4xx_sdram_fixup_memsize();
ibm405gp_fixup_clocks(33330000, 0xa8c000);
ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
ibm4xx_fixup_ebc_ranges("/plb/ebc");
^ permalink raw reply
* [PATCH 20/24] powerpc: Wire up 440EP USB controlle support to Bamboo board
From: Benjamin Herrenschmidt @ 2007-11-30 6:11 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
This adds the definition of the on-chip OHCI controller to the
Bamboo board's device-tree. This is enough to get it probed and
working, though a separate patch fixing a bug in the OHCI driver
is needed to make it reliable.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/boot/dts/bamboo.dts | 7 +++++++
1 file changed, 7 insertions(+)
Index: linux-work/arch/powerpc/boot/dts/bamboo.dts
===================================================================
--- linux-work.orig/arch/powerpc/boot/dts/bamboo.dts 2007-11-26 10:11:09.000000000 +1100
+++ linux-work/arch/powerpc/boot/dts/bamboo.dts 2007-11-27 14:37:50.000000000 +1100
@@ -238,6 +238,13 @@
zmii-device = <&ZMII0>;
zmii-channel = <1>;
};
+
+ usb@ef601000 {
+ compatible = "ohci-be";
+ reg = <ef601000 80>;
+ interrupts = <8 1 9 1>;
+ interrupt-parent = < &UIC1 >;
+ };
};
PCI0: pci@ec000000 {
^ permalink raw reply
* [PATCH 19/24] powerpc: Wire up PCI on Bamboo board
From: Benjamin Herrenschmidt @ 2007-11-30 6:11 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
This adds the device-tree bits & call to ppc4xx_pci_find_bridges()
to make PCI work on the Bamboo board
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/boot/dts/bamboo.dts | 40 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
Index: linux-work/arch/powerpc/boot/dts/bamboo.dts
===================================================================
--- linux-work.orig/arch/powerpc/boot/dts/bamboo.dts 2007-11-30 13:40:21.000000000 +1100
+++ linux-work/arch/powerpc/boot/dts/bamboo.dts 2007-11-30 13:40:45.000000000 +1100
@@ -239,10 +239,48 @@
zmii-channel = <1>;
};
};
+
+ PCI0: pci@ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440ep-pci", "ibm,plb-pci";
+ primary;
+ reg = <0 eec00000 8 /* Config space access */
+ 0 eed80000 4 /* IACK */
+ 0 eed80000 4 /* Special cycle */
+ 0 ef480000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 a0000000 0 a0000000 0 20000000
+ 01000000 0 00000000 0 e8000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* Walnut has all 4 IRQ pins tied together per slot */
+ interrupt-map-mask = <f800 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 1 */
+ 0800 0 0 0 &UIC0 1c 8
+
+ /* IDSEL 2 */
+ 1000 0 0 0 &UIC0 1b 8
+
+ /* IDSEL 3 */
+ 1800 0 0 0 &UIC0 1a 8
+
+ /* IDSEL 4 */
+ 2000 0 0 0 &UIC0 19 8
+ >;
+ };
};
chosen {
linux,stdout-path = "/plb/opb/serial@ef600300";
- bootargs = "console=ttyS0,115200";
};
};
^ permalink raw reply
* [PATCH 18/24] powerpc: Base support for 440GX Taishan eval board
From: Benjamin Herrenschmidt @ 2007-11-30 6:11 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
From: Hugh Blemings <hugh@blemings.org>
Signed-off-by: Hugh Blemings <hugh@blemings.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
This needs a bit of cleanup still, probably not to be merged as-is
just yet (like using mtdcri/mfdcri for CPR access).
arch/powerpc/Kconfig.debug | 6
arch/powerpc/boot/44x.h | 1
arch/powerpc/boot/Makefile | 7
arch/powerpc/boot/cuboot-taishan.c | 35 ++
arch/powerpc/boot/dcr.h | 32 ++
arch/powerpc/boot/dts/taishan.dts | 414 +++++++++++++++++++++++++++++++++++
arch/powerpc/boot/taishan.c | 64 +++++
arch/powerpc/platforms/44x/Kconfig | 12 +
arch/powerpc/platforms/44x/Makefile | 1
arch/powerpc/platforms/44x/taishan.c | 74 ++++++
10 files changed, 643 insertions(+), 3 deletions(-)
Index: linux-work/arch/powerpc/boot/44x.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/44x.h 2007-11-30 13:27:01.000000000 +1100
+++ linux-work/arch/powerpc/boot/44x.h 2007-11-30 13:39:18.000000000 +1100
@@ -12,5 +12,6 @@
void ebony_init(void *mac0, void *mac1);
void bamboo_init(void *mac0, void *mac1);
+void taishan_init(void *mac0, void *mac1);
#endif /* _PPC_BOOT_44X_H_ */
Index: linux-work/arch/powerpc/boot/dcr.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/dcr.h 2007-11-30 13:27:01.000000000 +1100
+++ linux-work/arch/powerpc/boot/dcr.h 2007-11-30 13:39:18.000000000 +1100
@@ -139,4 +139,36 @@ static const unsigned long sdram_bxcr[]
#define DCRN_405_CPC0_CR0 0xb1
#define DCRN_405_CPC0_CR1 0xb2
+
+/* 440GX Clock control etc */
+
+
+#define DCRN_CPR0_CLKUPD 0x020
+#define DCRN_CPR0_PLLC 0x040
+#define DCRN_CPR0_PLLD 0x060
+#define DCRN_CPR0_PRIMAD 0x080
+#define DCRN_CPR0_PRIMBD 0x0a0
+#define DCRN_CPR0_OPBD 0x0c0
+#define DCRN_CPR0_PERD 0x0e0
+#define DCRN_CPR0_MALD 0x100
+
+//#define CPC0_SYS0_TUNE 0xffc00000
+//#define CPC0_SYS0_FBDV_MASK 0x003c0000
+//#define CPC0_SYS0_FWDVA_MASK 0x00038000
+
+
+/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
+
+#define DCRN_CPR0_CFGADDR 0xc
+#define DCRN_CPR0_CFGDATA 0xd
+
+#define CPR0_READ(offset) ({\
+ mtdcr(DCRN_CPR0_CFGADDR, offset); \
+ mfdcr(DCRN_CPR0_CFGDATA);})
+#define CPR0_WRITE(offset, data) ({\
+ mtdcr(DCRN_CPR0_CFGADDR, offset); \
+ mtdcr(DCRN_CPR0_CFGDATA, data);})
+
+
+
#endif /* _PPC_BOOT_DCR_H_ */
Index: linux-work/arch/powerpc/boot/Makefile
===================================================================
--- linux-work.orig/arch/powerpc/boot/Makefile 2007-11-30 13:38:25.000000000 +1100
+++ linux-work/arch/powerpc/boot/Makefile 2007-11-30 13:39:18.000000000 +1100
@@ -37,8 +37,10 @@ BOOTCFLAGS += -I$(obj) -I$(srctree)/$(ob
$(obj)/4xx.o: BOOTCFLAGS += -mcpu=440
$(obj)/ebony.o: BOOTCFLAGS += -mcpu=440
+$(obj)/taishan.o: BOOTCFLAGS += -mcpu=440
$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
+
zlib := inffast.c inflate.c inftrees.c
zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h
zliblinuxheader := zlib.h zconf.h zutil.h
@@ -51,12 +53,12 @@ src-wlib := string.S crt0.S stdio.c main
gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
- fsl-soc.c mpc8xx.c pq2.c
+ fsl-soc.c mpc8xx.c pq2.c taishan.c
src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
- fixed-head.S ep88xc.c cuboot-hpc2.c ep405.c
+ fixed-head.S ep88xc.c cuboot-hpc2.c ep405.c cuboot-taishan.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -160,6 +162,7 @@ image-$(CONFIG_EBONY) += treeImage.ebo
image-$(CONFIG_BAMBOO) += treeImage.bamboo #cuImage.bamboo
#image-$(CONFIG_SEQUOIA) += cuImage.sequoia
image-$(CONFIG_WALNUT) += treeImage.walnut
+image-$(CONFIG_TAISHAN) += cuImage.taishan
endif
# For 32-bit powermacs, build the COFF and miboot images
Index: linux-work/arch/powerpc/Kconfig.debug
===================================================================
--- linux-work.orig/arch/powerpc/Kconfig.debug 2007-11-30 13:38:22.000000000 +1100
+++ linux-work/arch/powerpc/Kconfig.debug 2007-11-30 13:39:18.000000000 +1100
@@ -218,7 +218,8 @@ config PPC_EARLY_DEBUG_44x
depends on 44x
help
Select this to enable early debugging for IBM 44x chips via the
- inbuilt serial port.
+ inbuilt serial port. If you enable this, ensure you set
+ PPC_EARLY_DEBUG_44x_PHYSLOW below to suit your target board.
config PPC_EARLY_DEBUG_40x
bool "Early serial debugging for IBM/AMCC 40x CPUs"
@@ -243,6 +244,9 @@ config PPC_EARLY_DEBUG_44x_PHYSLOW
hex "Low 32 bits of early debug UART physical address"
depends on PPC_EARLY_DEBUG_44x
default "0x40000200"
+ help
+ You probably want 0x40000200 for ebony boards and
+ 0x40000300 for taishan
config PPC_EARLY_DEBUG_44x_PHYSHIGH
hex "EPRN of early debug UART physical address"
Index: linux-work/arch/powerpc/platforms/44x/Kconfig
===================================================================
--- linux-work.orig/arch/powerpc/platforms/44x/Kconfig 2007-11-30 13:29:18.000000000 +1100
+++ linux-work/arch/powerpc/platforms/44x/Kconfig 2007-11-30 13:39:18.000000000 +1100
@@ -22,6 +22,14 @@ config SEQUOIA
help
This option enables support for the AMCC PPC440EPX evaluation board.
+config TAISHAN
+ bool "Taishan"
+ depends on 44x
+ default n
+ select 440GX
+ help
+ This option enables support for the IBM PPC440GX "Taishan" evaluation board.
+
#config LUAN
# bool "Luan"
# depends on 44x
@@ -58,6 +66,10 @@ config 440GP
config 440GX
bool
+ select IBM_NEW_EMAC_EMAC4
+ select IBM_NEW_EMAC_RGMII
+ select IBM_NEW_EMAC_ZMII #test only
+ select IBM_NEW_EMAC_TAH #test only
config 440SP
bool
Index: linux-work/arch/powerpc/platforms/44x/Makefile
===================================================================
--- linux-work.orig/arch/powerpc/platforms/44x/Makefile 2007-11-30 13:27:01.000000000 +1100
+++ linux-work/arch/powerpc/platforms/44x/Makefile 2007-11-30 13:39:18.000000000 +1100
@@ -1,4 +1,5 @@
obj-$(CONFIG_44x) := misc_44x.o
obj-$(CONFIG_EBONY) += ebony.o
+obj-$(CONFIG_TAISHAN) += taishan.o
obj-$(CONFIG_BAMBOO) += bamboo.o
obj-$(CONFIG_SEQUOIA) += sequoia.o
Index: linux-work/arch/powerpc/platforms/44x/taishan.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/platforms/44x/taishan.c 2007-11-30 13:39:37.000000000 +1100
@@ -0,0 +1,74 @@
+/*
+ * Taishan board specific routines based off ebony.c code
+ * original copyrights below
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003-2005 Zultys Technologies
+ *
+ * Rewritten and ported to the merged powerpc tree:
+ * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
+ *
+ * Modified from ebony.c for taishan:
+ * Copyright 2007 Hugh Blemings <hugh@au.ibm.com>, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/time.h>
+#include <asm/uic.h>
+#include <asm/pci-bridge.h>
+
+#include "44x.h"
+
+static struct of_device_id taishan_of_bus[] = {
+ { .compatible = "ibm,plb4", },
+ { .compatible = "ibm,opb", },
+ { .compatible = "ibm,ebc", },
+ {},
+};
+
+static int __init taishan_device_probe(void)
+{
+ if (!machine_is(taishan))
+ return 0;
+
+ of_platform_bus_probe(NULL, taishan_of_bus, NULL);
+
+ return 0;
+}
+device_initcall(taishan_device_probe);
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init taishan_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (!of_flat_dt_is_compatible(root, "ibm,taishan"))
+ return 0;
+
+ return 1;
+}
+
+define_machine(taishan) {
+ .name = "Taishan",
+ .probe = taishan_probe,
+ .progress = udbg_progress,
+ .init_IRQ = uic_init_tree,
+ .get_irq = uic_get_irq,
+ .restart = ppc44x_reset_system,
+ .calibrate_decr = generic_calibrate_decr,
+};
Index: linux-work/arch/powerpc/boot/dts/taishan.dts
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/boot/dts/taishan.dts 2007-11-30 13:39:18.000000000 +1100
@@ -0,0 +1,414 @@
+/*
+ * Device Tree Source for IBM/AMCC Taishan
+ *
+ * Copyright 2007 IBM Corp.
+ * Hugh Blemings <hugh@au.ibm.com> based off code by
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * To build:
+ * dtc -I dts -O asm -o taishan.S -b 0 taishan.dts
+ * dtc -I dts -O dtb -o taishan.dtb -b 0 taishan.dts
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ model = "ibm,taishan";
+ compatible = "ibm,taishan";
+ dcr-parent = <&/cpus/PowerPC,440GX@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,440GX@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <2FAF0800>; // 800MHz
+ timebase-frequency = <0>; // Filled in by zImage
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <8000>; /* 32 kB */
+ d-cache-size = <8000>; /* 32 kB */
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0 0>; // Filled in by zImage
+ };
+
+
+ UICB0: interrupt-controller-base {
+ compatible = "ibm,uic-440gx", "ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <200 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+
+ UIC0: interrupt-controller0 {
+ compatible = "ibm,uic-440gx", "ibm,uic"; /* Should be AMCC ? */
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <01 4 00 4>; /* cascade - first non-critical */
+ interrupt-parent = <&UICB0>;
+
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-440gx", "ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <03 4 02 4>; /* cascade */
+ interrupt-parent = <&UICB0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-440gx", "ibm,uic";
+ interrupt-controller;
+ cell-index = <2>; /* was 1 */
+ dcr-reg = <210 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <05 4 04 4>; /* cascade */
+ interrupt-parent = <&UICB0>;
+ };
+
+
+ CPC0: cpc {
+ compatible = "ibm,cpc-440gp";
+ dcr-reg = <0b0 003 0e0 010>;
+ // FIXME: anything else?
+ };
+
+ plb {
+ compatible = "ibm,plb-440gx", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <9896800>; // 160MHz
+
+ SDRAM0: memory-controller {
+ compatible = "ibm,sdram-440gp";
+ dcr-reg = <010 2>;
+ // FIXME: anything else?
+ };
+
+ SRAM0: sram {
+ compatible = "ibm,sram-440gp";
+ dcr-reg = <020 8 00a 1>;
+ };
+
+ DMA0: dma {
+ // FIXME: ???
+ compatible = "ibm,dma-440gp";
+ dcr-reg = <100 027>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-440gx", "ibm,mcmal2";
+ dcr-reg = <180 62>;
+ num-tx-chans = <4>;
+ num-rx-chans = <4>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+ /*RXEOB*/ 1 &UIC0 b 4
+ /*SERR*/ 2 &UIC1 0 4
+ /*TXDE*/ 3 &UIC1 1 4
+ /*RXDE*/ 4 &UIC1 2 4>;
+ interrupt-map-mask = <ffffffff>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-440gx", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* Wish there was a nicer way of specifying a full 32-bit
+ range */
+ ranges = <00000000 1 00000000 80000000
+ 80000000 1 80000000 80000000>;
+ dcr-reg = <090 00b>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <7 4>;
+ clock-frequency = <4C4B400>; // 80MHz
+
+
+ /* Put EBC0 back **FIXME** */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-440gx", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <4C4B400>; // 80MHz
+ // ranges property is supplied by zImage
+ // based on firmware's configuration of the
+ // EBC bridge
+ interrupts = <5 4>;
+ interrupt-parent = <&UIC1>;
+
+// small-flash@0,80000 {
+// device_type = "rom";
+// compatible = "direct-mapped";
+// probe-type = "JEDEC";
+// bank-width = <1>;
+// partitions = <0 80000>;
+// partition-names = "OpenBIOS";
+// reg = <0 80000 80000>;
+// };
+
+// ds1743@1,0 {
+// /* NVRAM & RTC */
+// compatible = "ds1743";
+// reg = <1 0 2000>;
+// };
+
+// large-flash@2,0 {
+// device_type = "rom";
+// compatible = "direct-mapped";
+// probe-type = "JEDEC";
+// bank-width = <1>;
+// partitions = <0 380000
+// 380000 80000>;
+// partition-names = "fs", "firmware";
+// reg = <2 0 400000>;
+// };
+
+// ir@3,0 {
+// reg = <3 0 10>;
+// };
+
+// fpga@7,0 {
+// compatible = "Ebony-FPGA";
+// reg = <7 0 10>;
+// };
+ };
+
+
+
+ UART0: serial@40000200 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <40000200 8>;
+ virtual-reg = <e0000200>;
+ clock-frequency = <A8C000>;
+ current-speed = <1C200>; /* 115200 */
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@40000300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <40000300 8>;
+ virtual-reg = <e0000300>;
+ clock-frequency = <A8C000>;
+ current-speed = <1C200>; /* 115200 */
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ IIC0: i2c@40000400 {
+ /* FIXME */
+ device_type = "i2c";
+ compatible = "ibm,iic-440gp", "ibm,iic";
+ reg = <40000400 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+ IIC1: i2c@40000500 {
+ /* FIXME */
+ device_type = "i2c";
+ compatible = "ibm,iic-440gp", "ibm,iic";
+ reg = <40000500 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <3 4>;
+ };
+
+ GPIO0: gpio@40000700 {
+ /* FIXME */
+ compatible = "ibm,gpio-440gp";
+ reg = <40000700 20>;
+ };
+
+ ZMII0: emac-zmii@40000780 {
+ device_type = "zgmii-interface";
+ compatible = "ibm,zmii-440gx", "ibm,zmii";
+ reg = <40000780 c>;
+ };
+
+ RGMII0: emac-rgmii@40000790 {
+ device_type = "rgmii-interface";
+ compatible = "ibm,rgmii";
+ reg = <40000790 8>;
+ };
+
+
+ EMAC0: ethernet@40000800 {
+ unused = <1>;
+ linux,network-index = <2>;
+ device_type = "network";
+ compatible = "ibm,emac-440gx", "ibm,emac4";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1c 4 1d 4>;
+ reg = <40000800 70>;
+ local-mac-address = [000000000000]; // Filled in by zImage
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000001>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <0>;
+ };
+ EMAC1: ethernet@40000900 {
+ unused = <1>;
+ linux,network-index = <3>;
+ device_type = "network";
+ compatible = "ibm,emac-440gx", "ibm,emac4";
+ interrupt-parent = <&UIC1>;
+ interrupts = <1e 4 1f 4>;
+ reg = <40000900 70>;
+ local-mac-address = [000000000000]; // Filled in by zImage
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <1>;
+ cell-index = <1>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000001>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <1>;
+ };
+
+ EMAC2: ethernet@40000c00 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-440gx", "ibm,emac4";
+ interrupt-parent = <&UIC2>;
+ interrupts = <0 4 1 4>;
+ reg = <40000c00 70>;
+ local-mac-address = [000000000000]; // Filled in by zImage
+ mal-device = <&MAL0>;
+ mal-tx-channel = <2>;
+ mal-rx-channel = <2>;
+ cell-index = <2>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000001>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <2>;
+ };
+
+ EMAC3: ethernet@40000e00 {
+ linux,network-index = <1>;
+ device_type = "network";
+ compatible = "ibm,emac-440gx", "ibm,emac4";
+ interrupt-parent = <&UIC2>;
+ interrupts = <2 4 3 4>;
+ reg = <40000e00 70>;
+ local-mac-address = [000000000000]; // Filled in by zImage
+ mal-device = <&MAL0>;
+ mal-tx-channel = <3>;
+ mal-rx-channel = <3>;
+ cell-index = <3>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000003>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <1>;
+ zmii-device = <&ZMII0>;
+ zmii-channel = <3>;
+ };
+
+
+ GPT0: gpt@40000a00 {
+ /* FIXME */
+ reg = <40000a00 d4>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <12 4 13 4 14 4 15 4 16 4>;
+ };
+
+ };
+
+ PCIX0: pci@20ec00000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix";
+ primary;
+ large-inbound-windows;
+ enable-msi-hole;
+ reg = <2 0ec00000 8 /* Config space access */
+ 0 0 0 /* no IACK cycles */
+ 2 0ed00000 4 /* Special cycles */
+ 2 0ec80000 100 /* Internal registers */
+ 2 0ec80100 fc>; /* Internal messaging registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 00000003 80000000 0 80000000
+ 01000000 0 00000000 00000002 08000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* Ebony has all 4 IRQ pins tied together per slot */
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 1 */
+ 0800 0 0 1 &UIC0 17 8
+ 0800 0 0 2 &UIC0 18 8
+ 0800 0 0 3 &UIC0 19 8
+ 0800 0 0 4 &UIC0 1a 8
+
+ /* IDSEL 2 */
+ 1000 0 0 1 &UIC0 18 8
+ 1000 0 0 2 &UIC0 19 8
+ 1000 0 0 3 &UIC0 1a 8
+ 1000 0 0 4 &UIC0 17 8
+ >;
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@40000300";
+ };
+};
Index: linux-work/arch/powerpc/boot/taishan.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/boot/taishan.c 2007-11-30 13:39:18.000000000 +1100
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2007 David Gibson, IBM Corporation.
+ *
+ * Based on earlier code:
+ * Copyright (C) Paul Mackerras 1997.
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <stdarg.h>
+#include <stddef.h>
+#include "types.h"
+#include "elf.h"
+#include "string.h"
+#include "stdio.h"
+#include "page.h"
+#include "ops.h"
+#include "reg.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "44x.h"
+
+
+extern char _dtb_start[];
+extern char _dtb_end[];
+
+static u8 *taishan_mac0, *taishan_mac1;
+
+
+
+static void taishan_fixups(void)
+{
+ /* FIXME: sysclk should be derived by reading the FPGA
+ registers */
+ unsigned long sysclk = 33000000;
+
+ /* 440EP Clock logic is all but identical to 440GX
+ so we just use that code for now at least */
+ ibm440ep_fixup_clocks(sysclk, 6 * 1843200);
+
+ ibm4xx_fixup_memsize();
+
+ dt_fixup_mac_addresses(taishan_mac0, taishan_mac1);
+
+ ibm4xx_fixup_ebc_ranges("/plb/opb/ebc");
+}
+
+void taishan_init(void *mac0, void *mac1)
+{
+ platform_ops.fixups = taishan_fixups;
+// platform_ops.exit = ibm44x_dbcr_reset; **FIXME**
+ taishan_mac0 = mac0;
+ taishan_mac1 = mac1;
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+ serial_console_init();
+}
Index: linux-work/arch/powerpc/boot/cuboot-taishan.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/boot/cuboot-taishan.c 2007-11-30 13:39:18.000000000 +1100
@@ -0,0 +1,35 @@
+/*
+ * Old U-boot compatibility for Taishan
+ *
+ * Author: Hugh Blemings <hugh@au.ibm.com>
+ *
+ * Copyright 2007 Hugh Blemings, IBM Corporation.
+ * Based on cuboot-ebony.c which is:
+ * Copyright 2007 David Gibson, IBM Corporation.
+ * Based on cuboot-83xx.c, which is:
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "44x.h"
+#include "cuboot.h"
+
+#define TARGET_44x
+#include "ppcboot.h"
+
+static bd_t bd;
+
+BSS_STACK(4096);
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ CUBOOT_INIT();
+
+ taishan_init(&bd.bi_enetaddr, &bd.bi_enet1addr);
+}
^ permalink raw reply
* [PATCH 17/24] powerpc: Add PCI to Walnut platform
From: Benjamin Herrenschmidt @ 2007-11-30 6:10 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
This wires up the 4xx PCI support & device-tree bits for the
405GP based Walnut platform.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
This one is untested, haven't had time to dig my walnut and put it
back into working condition. Josh, can you verify that IRQs are
working (routing is correct ?) Thanks !
arch/powerpc/boot/dts/walnut.dts | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
Index: linux-work/arch/powerpc/boot/dts/walnut.dts
===================================================================
--- linux-work.orig/arch/powerpc/boot/dts/walnut.dts 2007-11-13 11:39:44.000000000 +1100
+++ linux-work/arch/powerpc/boot/dts/walnut.dts 2007-11-27 18:28:07.000000000 +1100
@@ -190,6 +190,45 @@
virtual-reg = <f0300005>;
};
};
+
+ PCI0: pci@ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
+ primary;
+ reg = <eec00000 8 /* Config space access */
+ eed80000 4 /* IACK */
+ eed80000 4 /* Special cycle */
+ ef480000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e8000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 80000000>;
+
+ /* Walnut has all 4 IRQ pins tied together per slot */
+ interrupt-map-mask = <f800 0 0 0>;
+ interrupt-map = <
+ /* IDSEL 1 */
+ 0800 0 0 0 &UIC0 1c 8
+
+ /* IDSEL 2 */
+ 1000 0 0 0 &UIC0 1d 8
+
+ /* IDSEL 3 */
+ 1800 0 0 0 &UIC0 1e 8
+
+ /* IDSEL 4 */
+ 2000 0 0 0 &UIC0 1f 8
+ >;
+ };
};
chosen {
^ permalink raw reply
* [PATCH 16/24] powerpc: EP405 boards support for arch/powerpc
From: Benjamin Herrenschmidt @ 2007-11-30 6:10 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD
comes from a device-tree property, PCI is working to the point where
I can see the video card, USB device, and south bridge.
This should work with both EP405 and EP405PC.
I've not totally figured out how IRQs are wired on this hardware
though, thus at this stage, expect only USB interrupts working,
pretty much the same as what arch/ppc did.
Also, the flash, nvram, rtc and temp control still have to be wired.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Note about IRQ routing: The doc is very obscure in that area.
I _think_ the SB interrupt on the CPLD is actually the Windond's
8259 output and the NB interrupt is the PCI_A...PCI_D mux in
there (which can be implemented as a cascaded controller) but
I haven't sorted that out yet. If anybody from Embedded Planet
is around, I could use some advice there.
If my deductions are correct, then we would need to wire up the
8259 driver to SB, which should be trivial provided I stick the
windbond bridge in the device-tree, or at least part of it,
and probably implement a cascaded controller for the PCI IRQ
A...D mux thingy, which should also be trivial.
Note also that it tends to lockup during the transition from
the boot wrapper to the kernel, before udbg is started. I didn't
have a RiscWatch at hand so I haven't yet been able to track that
down. It's random though, quite weird. Maybe some stale TLB entries
or cache content that isn't cleared properly...
arch/powerpc/boot/4xx.c | 55 +-
arch/powerpc/boot/4xx.h | 1
arch/powerpc/boot/Makefile | 3
arch/powerpc/boot/dts/ep405.dts | 221 ++++++++
arch/powerpc/boot/ep405.c | 74 ++
arch/powerpc/boot/treeboot-walnut.c | 49 -
arch/powerpc/boot/wrapper | 2
arch/powerpc/configs/ep405_defconfig | 951 +++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/40x/Kconfig | 21
arch/powerpc/platforms/40x/Makefile | 1
arch/powerpc/platforms/40x/ep405.c | 125 ++++
11 files changed, 1437 insertions(+), 66 deletions(-)
Index: linux-work/arch/powerpc/boot/Makefile
===================================================================
--- linux-work.orig/arch/powerpc/boot/Makefile 2007-11-30 13:31:51.000000000 +1100
+++ linux-work/arch/powerpc/boot/Makefile 2007-11-30 13:38:25.000000000 +1100
@@ -56,7 +56,7 @@ src-plat := of.c cuboot-52xx.c cuboot-83
cuboot-ebony.c treeboot-ebony.c prpmc2800.c \
ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \
- fixed-head.S ep88xc.c cuboot-hpc2.c
+ fixed-head.S ep88xc.c cuboot-hpc2.c ep405.c
src-boot := $(src-wlib) $(src-plat) empty.c
src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -150,6 +150,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImag
ifneq ($(CONFIG_DEVICE_TREE),"")
image-$(CONFIG_PPC_8xx) += cuImage.8xx
image-$(CONFIG_PPC_EP88XC) += zImage.ep88xc
+image-$(CONFIG_EP405) += zImage.ep405
image-$(CONFIG_8260) += cuImage.pq2
image-$(CONFIG_PPC_MPC52xx) += cuImage.52xx
image-$(CONFIG_PPC_83xx) += cuImage.83xx
Index: linux-work/arch/powerpc/boot/ep405.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/boot/ep405.c 2007-11-30 13:38:25.000000000 +1100
@@ -0,0 +1,74 @@
+/*
+ * Embedded Planet EP405 with PlanetCore firmware
+ *
+ * (c) Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp,\
+ *
+ * Based on ep88xc.c by
+ *
+ * Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include "ops.h"
+#include "stdio.h"
+#include "planetcore.h"
+#include "dcr.h"
+#include "4xx.h"
+#include "io.h"
+
+static char *table;
+static u64 mem_size;
+
+static void platform_fixups(void)
+{
+ u64 val;
+ void *nvrtc;
+
+ dt_fixup_memory(0, mem_size);
+ planetcore_set_mac_addrs(table);
+
+ if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, &val)) {
+ printf("No PlanetCore crystal frequency key.\r\n");
+ return;
+ }
+ ibm405gp_fixup_clocks(val, 0xa8c000);
+ ibm4xx_quiesce_eth((u32 *)0xef600800, NULL);
+ ibm4xx_fixup_ebc_ranges("/plb/ebc");
+
+ if (!planetcore_get_decimal(table, PLANETCORE_KEY_KB_NVRAM, &val)) {
+ printf("No PlanetCore NVRAM size key.\r\n");
+ return;
+ }
+ nvrtc = finddevice("/plb/ebc/nvrtc@4,200000");
+ if (nvrtc != NULL) {
+ u32 reg[3] = { 4, 0x200000, 0};
+ getprop(nvrtc, "reg", reg, 3);
+ reg[2] = (val << 10) & 0xffffffff;
+ setprop(nvrtc, "reg", reg, 3);
+ }
+}
+
+void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+ unsigned long r6, unsigned long r7)
+{
+ table = (char *)r3;
+ planetcore_prepare_table(table);
+
+ if (!planetcore_get_decimal(table, PLANETCORE_KEY_MB_RAM, &mem_size))
+ return;
+
+ mem_size *= 1024 * 1024;
+ simple_alloc_init(_end, mem_size - (unsigned long)_end, 32, 64);
+
+ ft_init(_dtb_start, _dtb_end - _dtb_start, 32);
+
+ planetcore_set_stdout_path(table);
+
+ serial_console_init();
+ platform_ops.fixups = platform_fixups;
+}
Index: linux-work/arch/powerpc/boot/dts/ep405.dts
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/boot/dts/ep405.dts 2007-11-30 13:38:25.000000000 +1100
@@ -0,0 +1,221 @@
+/*
+ * Device Tree Source for EP405
+ *
+ * Copyright 2007 IBM Corp.
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "ep405";
+ compatible = "ep405";
+ dcr-parent = <&/cpus/PowerPC,405GP@0>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,405GP@0 {
+ device_type = "cpu";
+ reg = <0>;
+ clock-frequency = <bebc200>; /* Filled in by zImage */
+ timebase-frequency = <0>; /* Filled in by zImage */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <4000>;
+ d-cache-size = <4000>;
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>; /* Filled in by zImage */
+ };
+
+ UIC0: interrupt-controller {
+ compatible = "ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 9>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ plb {
+ compatible = "ibm,plb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ SDRAM0: memory-controller {
+ compatible = "ibm,sdram-405gp";
+ dcr-reg = <010 2>;
+ };
+
+ MAL: mcmal {
+ compatible = "ibm,mcmal-405gp", "ibm,mcmal";
+ dcr-reg = <180 62>;
+ num-tx-chans = <1>;
+ num-rx-chans = <1>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <
+ b 4 /* TXEOB */
+ c 4 /* RXEOB */
+ a 4 /* SERR */
+ d 4 /* TXDE */
+ e 4 /* RXDE */>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-405gp", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <ef600000 ef600000 a00000>;
+ dcr-reg = <0a0 5>;
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ UART0: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <2580>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0 4>;
+ };
+
+ UART1: serial@ef600400 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600400 8>;
+ virtual-reg = <ef600400>;
+ clock-frequency = <0>; /* Filled in by zImage */
+ current-speed = <2580>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ IIC: i2c@ef600500 {
+ compatible = "ibm,iic-405gp", "ibm,iic";
+ reg = <ef600500 11>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ GPIO: gpio@ef600700 {
+ compatible = "ibm,gpio-405gp";
+ reg = <ef600700 20>;
+ };
+
+ EMAC: ethernet@ef600800 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-405gp", "ibm,emac";
+ interrupt-parent = <&UIC0>;
+ interrupts = <
+ f 4 /* Ethernet */
+ 9 4 /* Ethernet Wake Up */>;
+ local-mac-address = [000000000000]; /* Filled in by zImage */
+ reg = <ef600800 70>;
+ mal-device = <&MAL>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rmii";
+ phy-map = <00000000>;
+ };
+
+ };
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-405gp", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+
+ /* The ranges property is supplied by the bootwrapper
+ * and is based on the firmware's configuration of the
+ * EBC bridge
+ */
+ clock-frequency = <0>; /* Filled in by zImage */
+
+ /* NVRAM and RTC */
+ nvrtc@4,200000 {
+ compatible = "ds1742";
+ reg = <4 200000 0>; /* size fixed up by zImage */
+ };
+
+ /* "BCSR" CPLD contains a PCI irq controller */
+ bcsr@4,0 {
+ compatible = "ep405-bcsr";
+ reg = <4 0 10>;
+ interrupt-controller;
+ /* Routing table */
+ irq-routing = [ 00 /* SYSERR */
+ 01 /* STTM */
+ 01 /* RTC */
+ 01 /* FENET */
+ 02 /* NB PCIIRQ mux ? */
+ 03 /* SB Winbond 8259 ? */
+ 04 /* Serial Ring */
+ 05 /* USB (ep405pc) */
+ 06 /* XIRQ 0 */
+ 06 /* XIRQ 1 */
+ 06 /* XIRQ 2 */
+ 06 /* XIRQ 3 */
+ 06 /* XIRQ 4 */
+ 06 /* XIRQ 5 */
+ 06 /* XIRQ 6 */
+ 07]; /* Reserved */
+ };
+ };
+
+ PCI0: pci@ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
+ primary;
+ reg = <eec00000 8 /* Config space access */
+ eed80000 4 /* IACK */
+ eed80000 4 /* Special cycle */
+ ef480000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e8000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 80000000>;
+
+ /* That's all I know about IRQs on that thing ... */
+ interrupt-map-mask = <f800 0 0 0>;
+ interrupt-map = <
+ /* USB */
+ 7000 0 0 0 &UIC0 1e 8 /* IRQ5 */
+ >;
+ };
+ };
+
+ chosen {
+ linux,stdout-path = "/plb/opb/serial@ef600300";
+ };
+};
Index: linux-work/arch/powerpc/boot/4xx.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/4xx.c 2007-11-30 13:31:51.000000000 +1100
+++ linux-work/arch/powerpc/boot/4xx.c 2007-11-30 13:38:25.000000000 +1100
@@ -179,13 +179,16 @@ void ibm40x_dbcr_reset(void)
#define EMAC_RESET 0x20000000
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
{
- /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */
+ /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
+ * do this for us
+ */
if (emac0)
*emac0 = EMAC_RESET;
if (emac1)
*emac1 = EMAC_RESET;
mtdcr(DCRN_MAL0_CFG, MAL_RESET);
+ while(mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {};
}
/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
@@ -298,3 +301,53 @@ void ibm440ep_fixup_clocks(unsigned int
dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
}
+
+void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
+{
+ u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
+ u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
+ u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
+ u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
+ u32 fwdv, fbdv, cbdv, opdv, epdv, udiv;
+
+ fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
+ fbdv = (pllmr & 0x1e000000) >> 25;
+ cbdv = ((pllmr & 0x00060000) >> 17) + 1;
+ opdv = ((pllmr & 0x00018000) >> 15) + 1;
+ epdv = ((pllmr & 0x00001800) >> 13) + 2;
+ udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
+
+ m = fwdv * fbdv * cbdv;
+
+ cpu = sysclk * m / fwdv;
+ plb = cpu / cbdv;
+ opb = plb / opdv;
+ ebc = plb / epdv;
+
+ if (cpc0_cr0 & 0x80) {
+ /* uart0 uses the external clock */
+ uart0 = ser_clk;
+ } else {
+ uart0 = cpu / udiv;
+ }
+
+ if (cpc0_cr0 & 0x40) {
+ /* uart1 uses the external clock */
+ uart1 = ser_clk;
+ } else {
+ uart1 = cpu / udiv;
+ }
+
+ /* setup the timebase clock to tick at the cpu frequency */
+ cpc0_cr1 = cpc0_cr1 & ~0x00800000;
+ mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
+ tb = cpu;
+
+ dt_fixup_cpu_clocks(cpu, tb, 0);
+ dt_fixup_clock("/plb", plb);
+ dt_fixup_clock("/plb/opb", opb);
+ dt_fixup_clock("/plb/ebc", ebc);
+ dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
+ dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
+}
+
Index: linux-work/arch/powerpc/boot/treeboot-walnut.c
===================================================================
--- linux-work.orig/arch/powerpc/boot/treeboot-walnut.c 2007-11-30 13:31:51.000000000 +1100
+++ linux-work/arch/powerpc/boot/treeboot-walnut.c 2007-11-30 13:38:25.000000000 +1100
@@ -20,55 +20,6 @@
BSS_STACK(4096);
-void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
-{
- u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
- u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
- u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
- u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
- u32 fwdv, fbdv, cbdv, opdv, epdv, udiv;
-
- fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
- fbdv = (pllmr & 0x1e000000) >> 25;
- cbdv = ((pllmr & 0x00060000) >> 17) + 1;
- opdv = ((pllmr & 0x00018000) >> 15) + 1;
- epdv = ((pllmr & 0x00001800) >> 13) + 2;
- udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
-
- m = fwdv * fbdv * cbdv;
-
- cpu = sysclk * m / fwdv;
- plb = cpu / cbdv;
- opb = plb / opdv;
- ebc = plb / epdv;
-
- if (cpc0_cr0 & 0x80) {
- /* uart0 uses the external clock */
- uart0 = ser_clk;
- } else {
- uart0 = cpu / udiv;
- }
-
- if (cpc0_cr0 & 0x40) {
- /* uart1 uses the external clock */
- uart1 = ser_clk;
- } else {
- uart1 = cpu / udiv;
- }
-
- /* setup the timebase clock to tick at the cpu frequency */
- cpc0_cr1 = cpc0_cr1 & ~0x00800000;
- mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
- tb = cpu;
-
- dt_fixup_cpu_clocks(cpu, tb, 0);
- dt_fixup_clock("/plb", plb);
- dt_fixup_clock("/plb/opb", opb);
- dt_fixup_clock("/plb/ebc", ebc);
- dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
- dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
-}
-
static void walnut_flashsel_fixup(void)
{
void *devp, *sram;
Index: linux-work/arch/powerpc/platforms/40x/Kconfig
===================================================================
--- linux-work.orig/arch/powerpc/platforms/40x/Kconfig 2007-11-30 13:31:51.000000000 +1100
+++ linux-work/arch/powerpc/platforms/40x/Kconfig 2007-11-30 13:38:25.000000000 +1100
@@ -14,20 +14,13 @@
# help
# This option enables support for the CPCI405 board.
-#config EP405
-# bool "EP405/EP405PC"
-# depends on 40x
-# default n
-# select 405GP
-# help
-# This option enables support for the EP405/EP405PC boards.
-
-#config EP405PC
-# bool "EP405PC Support"
-# depends on EP405
-# default y
-# help
-# This option enables support for the extra features of the EP405PC board.
+config EP405
+ bool "EP405/EP405PC"
+ depends on 40x
+ default n
+ select 405GP
+ help
+ This option enables support for the EP405/EP405PC boards.
config KILAUEA
bool "Kilauea"
Index: linux-work/arch/powerpc/platforms/40x/Makefile
===================================================================
--- linux-work.orig/arch/powerpc/platforms/40x/Makefile 2007-11-30 13:31:51.000000000 +1100
+++ linux-work/arch/powerpc/platforms/40x/Makefile 2007-11-30 13:38:25.000000000 +1100
@@ -1,3 +1,4 @@
obj-$(CONFIG_KILAUEA) += kilauea.o
obj-$(CONFIG_WALNUT) += walnut.o
obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o
+obj-$(CONFIG_EP405) += ep405.o
Index: linux-work/arch/powerpc/platforms/40x/ep405.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/platforms/40x/ep405.c 2007-11-30 13:38:50.000000000 +1100
@@ -0,0 +1,125 @@
+/*
+ * Architecture- / platform-specific boot-time initialization code for
+ * IBM PowerPC 4xx based boards. Adapted from original
+ * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
+ * <dan@net4x.com>.
+ *
+ * Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
+ *
+ * Rewritten and ported to the merged powerpc tree:
+ * Copyright 2007 IBM Corporation
+ * Josh Boyer <jwboyer@linux.vnet.ibm.com>
+ *
+ * Adapted to EP405 by Ben. Herrenschmidt <benh@kernel.crashing.org>
+ *
+ * TODO: Wire up the PCI IRQ mux and the southbridge interrupts
+ *
+ * 2002 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/time.h>
+#include <asm/uic.h>
+#include <asm/pci-bridge.h>
+
+static struct device_node *bcsr_node;
+static void __iomem *bcsr_regs;
+
+/* BCSR registers */
+#define BCSR_ID 0
+#define BCSR_PCI_CTRL 1
+#define BCSR_FLASH_NV_POR_CTRL 2
+#define BCSR_FENET_UART_CTRL 3
+#define BCSR_PCI_IRQ 4
+#define BCSR_XIRQ_SELECT 5
+#define BCSR_XIRQ_ROUTING 6
+#define BCSR_XIRQ_STATUS 7
+#define BCSR_XIRQ_STATUS2 8
+#define BCSR_SW_STAT_LED_CTRL 9
+#define BCSR_GPIO_IRQ_PAR_CTRL 10
+/* there's more, can't be bothered typing them tho */
+
+
+static struct of_device_id ep405_of_bus[] = {
+ { .compatible = "ibm,plb3", },
+ { .compatible = "ibm,opb", },
+ { .compatible = "ibm,ebc", },
+ {},
+};
+
+static int __init ep405_device_probe(void)
+{
+ if (!machine_is(ep405))
+ return 0;
+
+ /* FIXME: do bus probe here */
+ of_platform_bus_probe(NULL, ep405_of_bus, NULL);
+
+ return 0;
+}
+device_initcall(ep405_device_probe);
+
+static void __init ep405_init_bcsr(void)
+{
+ const u8 *irq_routing;
+ int i;
+
+ /* Find the bloody thing & map it */
+ bcsr_node = of_find_compatible_node(NULL, NULL, "ep405-bcsr");
+ if (bcsr_node == NULL) {
+ printk(KERN_ERR "EP405 BCSR not found !\n");
+ return;
+ }
+ bcsr_regs = of_iomap(bcsr_node, 0);
+ if (bcsr_regs == NULL) {
+ printk(KERN_ERR "EP405 BCSR failed to map !\n");
+ return;
+ }
+
+ /* Get the irq-routing property and apply the routing to the CPLD */
+ irq_routing = of_get_property(bcsr_node, "irq-routing", NULL);
+ if (irq_routing == NULL)
+ return;
+ for (i = 0; i < 16; i++) {
+ u8 irq = irq_routing[i];
+ out_8(bcsr_regs + BCSR_XIRQ_SELECT, i);
+ out_8(bcsr_regs + BCSR_XIRQ_ROUTING, irq);
+ }
+ in_8(bcsr_regs + BCSR_XIRQ_SELECT);
+ mb();
+ out_8(bcsr_regs + BCSR_GPIO_IRQ_PAR_CTRL, 0xfe);
+}
+
+static void __init ep405_setup_arch(void)
+{
+ /* Find & init the BCSR CPLD */
+ ep405_init_bcsr();
+}
+
+static int __init ep405_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (!of_flat_dt_is_compatible(root, "ep405"))
+ return 0;
+
+ return 1;
+}
+
+define_machine(ep405) {
+ .name = "EP405",
+ .probe = ep405_probe,
+ .setup_arch = ep405_setup_arch,
+ .progress = udbg_progress,
+ .init_IRQ = uic_init_tree,
+ .get_irq = uic_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+};
Index: linux-work/arch/powerpc/boot/4xx.h
===================================================================
--- linux-work.orig/arch/powerpc/boot/4xx.h 2007-11-30 13:31:51.000000000 +1100
+++ linux-work/arch/powerpc/boot/4xx.h 2007-11-30 13:38:25.000000000 +1100
@@ -18,5 +18,6 @@ void ibm40x_dbcr_reset(void);
void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1);
void ibm4xx_fixup_ebc_ranges(const char *ebc);
void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
+void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk);
#endif /* _POWERPC_BOOT_4XX_H_ */
Index: linux-work/arch/powerpc/boot/wrapper
===================================================================
--- linux-work.orig/arch/powerpc/boot/wrapper 2007-11-30 13:31:51.000000000 +1100
+++ linux-work/arch/powerpc/boot/wrapper 2007-11-30 13:38:25.000000000 +1100
@@ -163,7 +163,7 @@ ps3)
ksection=.kernel:vmlinux.bin
isection=.kernel:initrd
;;
-ep88xc)
+ep88xc|ep405)
platformo="$object/fixed-head.o $object/$platform.o"
binary=y
;;
Index: linux-work/arch/powerpc/configs/ep405_defconfig
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/configs/ep405_defconfig 2007-11-30 13:38:25.000000000 +1100
@@ -0,0 +1,951 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc2
+# Wed Nov 21 16:44:30 2007
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+CONFIG_40x=y
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_4xx=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+# CONFIG_DEFAULT_UIMAGE is not set
+CONFIG_PPC_DCR_NATIVE=y
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_PPC_DCR=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_EP405=y
+# CONFIG_KILAUEA is not set
+# CONFIG_WALNUT is not set
+# CONFIG_XILINX_VIRTEX_GENERIC_BOARD is not set
+CONFIG_405GP=y
+CONFIG_IBM405_ERR77=y
+CONFIG_IBM405_ERR51=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPM2 is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_MATH_EMULATION is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_HIBERNATION_UP_POSSIBLE=y
+CONFIG_SECCOMP=y
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_DEVICE_TREE="ep405.dts"
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_BOOT_LOAD=0x00400000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+# CONFIG_MTD_BLOCK_RO is not set
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=35000
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_XILINX_SYSACE is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_IP1000 is not set
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_IBM_NEW_EMAC=y
+CONFIG_IBM_NEW_EMAC_RXB=128
+CONFIG_IBM_NEW_EMAC_TXB=64
+CONFIG_IBM_NEW_EMAC_POLL_WEIGHT=32
+CONFIG_IBM_NEW_EMAC_RX_COPY_THRESHOLD=256
+CONFIG_IBM_NEW_EMAC_RX_SKB_HEADROOM=0
+# CONFIG_IBM_NEW_EMAC_DEBUG is not set
+CONFIG_IBM_NEW_EMAC_ZMII=y
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PPC_OF=y
+CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
+CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+# CONFIG_UCC_SLOW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_INSTRUMENTATION=y
+# CONFIG_PROFILING is not set
+# CONFIG_KPROBES is not set
+# CONFIG_MARKERS is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_DEBUGGER is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_PPC_CLOCK is not set
^ permalink raw reply
* [PATCH 15/24] powerpc: early debug forces console log level to max
From: Benjamin Herrenschmidt @ 2007-11-30 6:10 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <1196403038.569525.367459803520.qpush@grosgo>
This patch makes the early debug option force the console loglevel
to the max. The early debug option is meant to catch messages very
early in the kernel boot process, in many cases, before the kernel
has a chance to parse the "debug" command line argument. Thus it
makes sense when CONFIG_PPC_EARLY_DEBUG is set, to force the console
log level to the max at boot time.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/udbg.c | 4 ++++
1 file changed, 4 insertions(+)
Index: linux-work/arch/powerpc/kernel/udbg.c
===================================================================
--- linux-work.orig/arch/powerpc/kernel/udbg.c 2007-11-30 13:29:51.000000000 +1100
+++ linux-work/arch/powerpc/kernel/udbg.c 2007-11-30 13:29:56.000000000 +1100
@@ -60,6 +60,10 @@ void __init udbg_early_init(void)
#elif defined(CONFIG_PPC_EARLY_DEBUG_CPM)
udbg_init_cpm();
#endif
+
+#ifdef CONFIG_PPC_EARLY_DEBUG
+ console_loglevel = 10;
+#endif
}
/* udbg library, used by xmon et al */
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox