* Re: [FDT][PATCH] Fix padding options
From: Jon Loeliger @ 2007-12-05 14:47 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0712041734580.1979@blarg.am.freescale.net>
So, like, the other day Kumar Gala mumbled:
> "Add an option to pad the blob that is generated" broke the padding
> support. We were updating the fdt header after writing it.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Applied.
jdl
^ permalink raw reply
* Re: dtc: Generate useful error message for properties after subnodes
From: Jon Loeliger @ 2007-12-05 14:41 UTC (permalink / raw)
To: David Gibson; +Cc: linuxppc-dev
In-Reply-To: <20071204232704.GD9487@localhost.localdomain>
So, like, the other day David Gibson mumbled:
> On several occasions, I've accidentally put properties after subnodes
> in a dts file. I've then spent ages thinking that the resulting
> syntax error was because of something else.
>
> This patch arranges for this specific syntax error to generate a more
> specific and useful error message.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Applied.
jdl
^ permalink raw reply
* Re: dtc: Trivial lexer cleanups
From: Jon Loeliger @ 2007-12-05 14:40 UTC (permalink / raw)
To: David Gibson; +Cc: linuxppc-dev
In-Reply-To: <20071204225025.GB9487@localhost.localdomain>
So, like, the other day David Gibson mumbled:
> This patch applies a couple of tiny cleanups to the lexer. The
> not-very-useful 'WS' named pattern is removed, and the debugging
> printf() for single character tokens is moved to the top of the
> action, which results in less confusing output when LEXDEBUG is
> switched on (because it goes before the printf()s for possible
> resulting lexer state changes).
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Applied.
jdl
^ permalink raw reply
* Re: dtc: Convert "name" property checking to new infrastructure
From: Jon Loeliger @ 2007-12-05 14:40 UTC (permalink / raw)
To: David Gibson; +Cc: linuxppc-dev
In-Reply-To: <20071204224023.GA9487@localhost.localdomain>
So, like, the other day David Gibson mumbled:
> This patch removes the old-style checking code for the "name" property
> - i.e. verifying that the "name" property, if present, matches the
> node name. It replaces it with a pair of more-or-less equivalent
> checks in the new checking framework.
>
> This also promotes this check to a "structural" check, or at least an
> error-rather-than-warning test, since the structural/semantic
> distinction doesn't really apply in the new framework.
>
> A testcase for the check is also added.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Applied.
jdl
^ permalink raw reply
* Re: dtc: Fix FAIL() macro varargs
From: Jon Loeliger @ 2007-12-05 14:39 UTC (permalink / raw)
To: David Gibson; +Cc: linuxppc-dev
In-Reply-To: <20071204223453.GA9406@localhost.localdomain>
So, like, the other day David Gibson mumbled:
> The way the checking subsystem FAIL() macro is currently implemented
> it must take at least one paramater after the format string. This
> patch corrects the problem.
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Applied.
jdl
^ permalink raw reply
* Re: [FDT][PATCH] Print out the total size as part of ftdump
From: Jon Loeliger @ 2007-12-05 14:37 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0712041032580.29317@blarg.am.freescale.net>
So, like, the other day Kumar Gala mumbled:
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> ftdump.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
Applied.
jdl
^ permalink raw reply
* Re: [PATCH] [XILINX][HWICAP] Xilinx Internal Configuration Access Port device driver.
From: Peter Korsgaard @ 2007-12-05 12:20 UTC (permalink / raw)
To: Stephen Neuendorffer; +Cc: linuxppc-dev
In-Reply-To: <20071204235725.61AD6A08071@mail81-dub.bigfish.com>
>>>>> "Stephen" == Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> writes:
Hi,
Stephen> Supports static platform_device and static device tree configuration.
Stephen> This is a standalone driver that does not depend on EDK generated
Stephen> files. However, it is also somewhat different in functionality from
Stephen> the standard EDK driver.
Stephen> 1) The EDK driver doesn't support readback, which this driver does.
Stephen> 2) The EDK driver supports fine granularity reading and writing, which
Stephen> this driver does not. The fine granularity support is heavily
Stephen> architecture independent, which makes it difficult to make the driver
Stephen> forward compatible. The fine granularity support is also complex and
Stephen> probably better handled in user space anyway.
Stephen> Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
Stephen> ---
Stephen> Grant,
Stephen> No comments last time... It would be nice if this merged
Stephen> with 2.6.25, I think.
Stephen> Steve
I never used the icap stuff, but here goes ..
Stephen> drivers/char/Kconfig | 5 +
Stephen> drivers/char/Makefile | 1 +
Stephen> drivers/char/xilinx_hwicap/Makefile | 7 +
Stephen> drivers/char/xilinx_hwicap/xhwicap_srp.c | 414 ++++++++++++++++++++
Stephen> drivers/char/xilinx_hwicap/xilinx_hwicap.c | 565 ++++++++++++++++++++++++++++
Stephen> drivers/char/xilinx_hwicap/xilinx_hwicap.h | 539 ++++++++++++++++++++++++++
Stephen> 6 files changed, 1531 insertions(+), 0 deletions(-)
Stephen> create mode 100644 drivers/char/xilinx_hwicap/Makefile
Stephen> create mode 100644 drivers/char/xilinx_hwicap/xhwicap_srp.c
Stephen> create mode 100644 drivers/char/xilinx_hwicap/xilinx_hwicap.c
Stephen> create mode 100644 drivers/char/xilinx_hwicap/xilinx_hwicap.h
> diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
> index bf18d75..72295cc 100644
> --- a/drivers/char/Kconfig
> +++ b/drivers/char/Kconfig
> @@ -573,6 +573,11 @@ config HVC_DRIVER
> It will automatically be selected if one of the back-end console drivers
> is selected.
Please don't put the HWICAP option in the middle of the HVC options.
> +config XILINX_HWICAP
> + tristate "Xilinx OPB HWICAP Support"
> + depends on XILINX_VIRTEX
> + help
> + This option enables support for Xilinx Internal Configuration Access Port (ICAP) driver.
Line too long.
>
> config HVC_CONSOLE
> bool "pSeries Hypervisor Virtual Console support"
> diff --git a/drivers/char/Makefile b/drivers/char/Makefile
> index 07304d5..8cfcbb0 100644
> --- a/drivers/char/Makefile
> +++ b/drivers/char/Makefile
> @@ -76,6 +76,7 @@ obj-$(CONFIG_EFI_RTC) += efirtc.o
> obj-$(CONFIG_SGI_DS1286) += ds1286.o
> obj-$(CONFIG_SGI_IP27_RTC) += ip27-rtc.o
> obj-$(CONFIG_DS1302) += ds1302.o
> +obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap/
> ifeq ($(CONFIG_GENERIC_NVRAM),y)
> obj-$(CONFIG_NVRAM) += generic_nvram.o
> else
> diff --git a/drivers/char/xilinx_hwicap/Makefile b/drivers/char/xilinx_hwicap/Makefile
> new file mode 100644
> index 0000000..818f4e1
> --- /dev/null
> +++ b/drivers/char/xilinx_hwicap/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Makefile for the Xilinx OPB hwicap driver
> +#
> +
> +obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap_m.o
> +
> +xilinx_hwicap_m-y := xilinx_hwicap.o xhwicap_srp.o
Those files are both quite small, couldn't you merge them and get rid
of the global symbols and the xilinx_hwicap directory?
> diff --git a/drivers/char/xilinx_hwicap/xhwicap_srp.c b/drivers/char/xilinx_hwicap/xhwicap_srp.c
> new file mode 100644
> index 0000000..388eefe
> --- /dev/null
> +++ b/drivers/char/xilinx_hwicap/xhwicap_srp.c
> @@ -0,0 +1,414 @@
> +/*****************************************************************************
> + *
> + * Author: Xilinx, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
> + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
> + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
> + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
> + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
> + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
> + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
> + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
> + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
> + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
> + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
> + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
> + * FOR A PARTICULAR PURPOSE.
> + *
> + * Xilinx products are not intended for use in life support appliances,
> + * devices, or systems. Use in such applications is expressly prohibited.
> + *
> + * (c) Copyright 2003-2007 Xilinx Inc.
> + * All rights reserved.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 675 Mass Ave, Cambridge, MA 02139, USA.
> + *
> + * ****************************************************************************/
Could you please you a smaller / standard GPL header instead?
> +
> +#include "xilinx_hwicap.h"
> +
> +#define XHI_BUFFER_START 0
> +
> +/****************************************************************************/
> +/**
> + *
> + * Stores data in the storage buffer at the specified address.
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
> + *
> + * @param Address - bram word address
> + *
> + * @param Data - data to be stored at address
> + *
> + * @return None.
> + *
> + * @note None.
> + *
> +*****************************************************************************/
Please use std kerneldoc format.
> +void XHwIcap_StorageBufferWrite(struct xhwicap_drvdata *InstancePtr,
> + u32 Address, u32 Data)
No CamelCase, Uppercase parameters.
> +{
> + /* Write data to storage buffer. */
> + XHwIcap_mSetBram(InstancePtr->baseAddress, Address, Data);
> +}
> +
> +/****************************************************************************/
> +/**
> + *
> + * Read data from the specified address in the storage buffer..
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
> + *
> + * @param Address - bram word address
> + *
> + * @return Data.
> + *
> + * @note None.
> + *
> +*****************************************************************************/
> +u32 XHwIcap_StorageBufferRead(struct xhwicap_drvdata *InstancePtr, u32 Address)
> +{
> + u32 Data;
> +
> + /* Read data from address. Multiply Address by 4 since 4 bytes per
> + * word.*/
> + Data = XHwIcap_mGetBram(InstancePtr->baseAddress, Address);
> + return Data;
> +
> +}
> +
> +/****************************************************************************/
> +/**
> + *
> + * Reads bytes from the device (ICAP) and puts it in the storage buffer.
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
> + *
> + * @param Offset - The storage buffer start address.
> + *
> + * @param NumInts - The number of words (32 bit) to read from the
> + * device (ICAP).
> + *
> + *@return int - 0 or -EBUSY or -EINVAL
> + *
> + * @note None.
> + *
> +*****************************************************************************/
> +int XHwIcap_DeviceRead(struct xhwicap_drvdata *InstancePtr, u32 Offset,
> + u32 NumInts)
> +{
> +
> + s32 Retries = 0;
> +
> + if (XHwIcap_mGetDoneReg(InstancePtr->baseAddress) == XHI_NOT_FINISHED) {
> + return -EBUSY;
> + }
No curly brackets around single statement. In general, please run the
patch through checkpatch.pl and fixup stuff.
> +
> + if ((Offset + NumInts) <= XHI_MAX_BUFFER_INTS) {
> + /* setSize NumInts*4 to get bytes. */
> + XHwIcap_mSetSizeReg((InstancePtr->baseAddress), (NumInts << 2));
> + XHwIcap_mSetOffsetReg((InstancePtr->baseAddress), Offset);
> + XHwIcap_mSetRncReg((InstancePtr->baseAddress), XHI_READBACK);
> +
> + while (XHwIcap_mGetDoneReg(InstancePtr->baseAddress) ==
> + XHI_NOT_FINISHED) {
> + Retries++;
> + if (Retries > XHI_MAX_RETRIES) {
> + return -EBUSY;
> + }
> + }
> + } else {
> + return -EINVAL;
> + }
> + return 0;
> +
> +};
> +
> +/****************************************************************************/
> +/**
> + *
> + * Writes bytes from the storage buffer and puts it in the device (ICAP).
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
> + *
> + * @param Offset - The storage buffer start address.
> + *
> + * @param NumInts - The number of words (32 bit) to read from the
> + * device (ICAP).
> + *
> + *@return int - 0 or -EBUSY or -EINVAL
> + *
> + * @note None.
> + *
> +*****************************************************************************/
> +int XHwIcap_DeviceWrite(struct xhwicap_drvdata *InstancePtr, u32 Offset,
> + u32 NumInts)
> +{
> +
> + s32 Retries = 0;
> +
> + if (XHwIcap_mGetDoneReg(InstancePtr->baseAddress) == XHI_NOT_FINISHED) {
> + return -EBUSY;
> + }
> +
> + if ((Offset + NumInts) <= XHI_MAX_BUFFER_INTS) {
> + /* setSize NumInts*4 to get bytes. */
> + XHwIcap_mSetSizeReg((InstancePtr->baseAddress), NumInts << 2);
> + XHwIcap_mSetOffsetReg((InstancePtr->baseAddress), Offset);
> + XHwIcap_mSetRncReg((InstancePtr->baseAddress), XHI_CONFIGURE);
> +
> + while (XHwIcap_mGetDoneReg(InstancePtr->baseAddress) ==
> + XHI_NOT_FINISHED) {
> + Retries++;
> + if (Retries > XHI_MAX_RETRIES) {
> + return -EBUSY;
> + }
> + }
> + } else {
> + return -EINVAL;
> + }
> + return 0;
> +
> +};
> +
> +/****************************************************************************/
> +/**
> + *
> + * Sends a DESYNC command to the ICAP port.
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
> + *
> + *@return int - 0 or -EBUSY or -EINVAL
> + *
> + * @note None.
> + *
> +*****************************************************************************/
> +int XHwIcap_CommandDesync(struct xhwicap_drvdata *InstancePtr)
> +{
> + int status;
> +
> + XHwIcap_StorageBufferWrite(InstancePtr, 0,
> + (XHwIcap_Type1Write(XHI_CMD) | 1));
> + XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_CMD_DESYNCH);
> + XHwIcap_StorageBufferWrite(InstancePtr, 2, XHI_NOOP_PACKET);
> + XHwIcap_StorageBufferWrite(InstancePtr, 3, XHI_NOOP_PACKET);
> +
> + /* send four words */
> + status = XHwIcap_DeviceWrite(InstancePtr, 0, 4);
> + if (status) {
> + return status;
> + }
> +
> + return 0;
> +}
> +
> +/****************************************************************************/
> +/**
> + *
> + * Sends a CAPTURE command to the ICAP port. This command caputres all
> + * of the flip flop states so they will be available during readback.
> + * One can use this command instead of enabling the CAPTURE block in the
> + * design.
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
> + *
> + * @return int - 0 or -EBUSY or -EINVAL
> + *
> + * @note None.
> + *
> +*****************************************************************************/
> +int XHwIcap_CommandCapture(struct xhwicap_drvdata *InstancePtr)
> +{
> + int status;
> +
> + /* DUMMY and SYNC */
> + XHwIcap_StorageBufferWrite(InstancePtr, 0, XHI_DUMMY_PACKET);
> + XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_SYNC_PACKET);
> + XHwIcap_StorageBufferWrite(InstancePtr, 2,
> + (XHwIcap_Type1Write(XHI_CMD) | 1));
> + XHwIcap_StorageBufferWrite(InstancePtr, 3, XHI_CMD_GCAPTURE);
> + XHwIcap_StorageBufferWrite(InstancePtr, 4, XHI_DUMMY_PACKET);
> + XHwIcap_StorageBufferWrite(InstancePtr, 5, XHI_DUMMY_PACKET);
> +
> + /* send six words */
> + status = XHwIcap_DeviceWrite(InstancePtr, 0, 6);
> + if (status) { /* send six words */
> + return status;
> + }
> +
> + return 0;
> +}
> +
> +/****************************************************************************/
> +/**
> + *
> + * This function returns the value of the specified configuration
> + * register.
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked
> + * on.
> + *
> + * @param ConfigReg - A constant which represents the configuration
> + * register value to be returned. Constants specified in xhwicap_i.h. Examples:
> + * XHI_IDCODE, XHI_FLR.
> + *
> + * @return The value of the specified configuration register.
> + *
> + *
> +*****************************************************************************/
> +
> +u32 XHwIcap_GetConfigReg(struct xhwicap_drvdata *InstancePtr, u32 ConfigReg)
> +{
> + u32 Packet;
> + int status;
> +
> + /* Write bitstream to bram */
> + Packet = XHwIcap_Type1Read(ConfigReg) | 1;
> + XHwIcap_StorageBufferWrite(InstancePtr, 0, XHI_DUMMY_PACKET);
> + XHwIcap_StorageBufferWrite(InstancePtr, 1, XHI_SYNC_PACKET);
> + XHwIcap_StorageBufferWrite(InstancePtr, 2, Packet);
> + XHwIcap_StorageBufferWrite(InstancePtr, 3, XHI_NOOP_PACKET);
> + XHwIcap_StorageBufferWrite(InstancePtr, 4, XHI_NOOP_PACKET);
> +
> + /* Transfer Bitstream from Bram to ICAP */
> + status = XHwIcap_DeviceWrite(InstancePtr, 0, 5);
> + if (status) {
> + return status;
> + }
> +
> + /* Now readback one word into bram position
> + * XHI_EX_BITSTREAM_LENGTH*/
> + status = XHwIcap_DeviceRead(InstancePtr, 5, 1);
> + if (status) {
> + return status;
> + }
> +
> + /* Return the Register value */
> + return XHwIcap_StorageBufferRead(InstancePtr, 5);
> +}
> +
> +/****************************************************************************
> + *
> + * Loads a partial bitstream from system memory.
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
> + *
> + * @param Data - Address of the data representing the partial bitstream
> + *
> + * @param Size - the size of the partial bitstream in 32 bit words.
> + *
> + * @return 0, -EFBIG or -EINVAL.
> + *
> + * @note None.
> + *
> +*****************************************************************************/
> +int XHwIcap_SetConfiguration(struct xhwicap_drvdata *InstancePtr, u32 *Data,
> + u32 Size)
> +{
> + int status;
> + s32 BufferCount = 0;
> + s32 NumWrites = 0;
> + bool Dirty = 0;
> + u32 I;
> +
> + /* Loop through all the data */
> + for (I = 0, BufferCount = 0; I < Size; I++) {
> +
> + /* Copy data to bram */
> + XHwIcap_StorageBufferWrite(InstancePtr, BufferCount, Data[I]);
> + Dirty = 1;
> +
> + if (BufferCount == XHI_MAX_BUFFER_INTS - 1) {
> + /* Write data to ICAP */
> + status = XHwIcap_DeviceWrite(InstancePtr, XHI_BUFFER_START,
> + XHI_MAX_BUFFER_INTS);
> + if (status != 0) {
> + /* abort. */
> + XHwIcap_mReset(InstancePtr->baseAddress); return status;
> + }
> +
> + BufferCount = 0;
> + NumWrites++;
> + Dirty = 0;
> + } else {
> + BufferCount++;
> + }
> + }
> +
> + /* Write unwritten data to ICAP */
> + if (Dirty) {
> + /* Write data to ICAP */
> + status = XHwIcap_DeviceWrite(InstancePtr, XHI_BUFFER_START,
> + BufferCount);
> + if (status != 0) {
> + /* abort. */
> + XHwIcap_mReset(InstancePtr->baseAddress);
> + }
> + return status;
> + }
> +
> + return 0;
> +};
> +
> +/****************************************************************************
> + *
> + * Reads Configuration Data from the device.
> + *
> + * @param InstancePtr - a pointer to the XHwIcap instance to be worked on.
> + *
> + * @param Data - Address of the data representing the partial bitstream
> + *
> + * @param Size - the size of the partial bitstream in 32 bit words.
> + *
> + * @return 0, -EFBIG or -EINVAL.
> + *
> + * @note None.
> + *
> +*****************************************************************************/
> +int XHwIcap_GetConfiguration(struct xhwicap_drvdata *InstancePtr, u32 *Data,
> + u32 Size)
> +{
> + int status;
> + s32 BufferCount = 0;
> + s32 NumReads = 0;
> + u32 I;
> +
> + /* Loop through all the data */
> + for (I = 0, BufferCount = XHI_MAX_BUFFER_INTS; I < Size; I++) {
> + if (BufferCount == XHI_MAX_BUFFER_INTS) {
> + u32 intsRemaining = Size - I;
> + u32 intsToRead =
> + intsRemaining <
> + XHI_MAX_BUFFER_INTS ? intsRemaining :
> + XHI_MAX_BUFFER_INTS;
> +
> + /* Read data from ICAP */
> +
> + status =
> + XHwIcap_DeviceRead(InstancePtr, XHI_BUFFER_START,
> + intsToRead);
> + if (status != 0) {
> + /* abort. */
> + XHwIcap_mReset(InstancePtr->baseAddress);
> + return status;
> + }
> +
> + BufferCount = 0;
> + NumReads++;
> + }
> +
> + /* Copy data from bram */
> + Data[I] = XHwIcap_StorageBufferRead(InstancePtr, BufferCount);
> + BufferCount++;
> + }
> +
> + return 0;
> +};
> diff --git a/drivers/char/xilinx_hwicap/xilinx_hwicap.c b/drivers/char/xilinx_hwicap/xilinx_hwicap.c
> new file mode 100644
> index 0000000..d42538e
> --- /dev/null
> +++ b/drivers/char/xilinx_hwicap/xilinx_hwicap.c
> @@ -0,0 +1,565 @@
> +/*****************************************************************************
> + *
> + * Author: Xilinx, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
> + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
> + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
> + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
> + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
> + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
> + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
> + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
> + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
> + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
> + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
> + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
> + * FOR A PARTICULAR PURPOSE.
> + *
> + * Xilinx products are not intended for use in life support appliances,
> + * devices, or systems. Use in such applications is expressly prohibited.
> + *
> + * (c) Copyright 2002 Xilinx Inc., Systems Engineering Group
> + * (c) Copyright 2004 Xilinx Inc., Systems Engineering Group
> + * (c) Copyright 2007 Xilinx Inc.
> + * All rights reserved.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 675 Mass Ave, Cambridge, MA 02139, USA.
> + *
> + *****************************************************************************/
> +
> +/*
> + * xilinx_hwicap.c
> + *
> + * This is the code behind /dev/xilinx_icap/'x' -- it allows a user-space
> + * application to use the Xilinx ICAP subsystem.
> + *
> + * A /dev/xilinx_icap/'x' device node represents an arbitrary device
> + * on port 'x'. The following operations are possible:
> + *
> + * open do nothing, set up default IEEE 1284 protocol to be COMPAT
> + * release release port and unregister device (if necessary)
> + * write Write a bitstream to the configuration processor.
> + * read Read a data stream from the configuration processor.
> + *
> + * Note that in order to use the read interface, it is first necessary
> + * to write a request packet to the write interface. i.e., it is not
> + * possible to simply readback the bitstream (or any configuration
> + * bits) from a device without specifically requesting them first.
> + * The code to craft such packets is intended to be part of the
> + * user-space application code that uses this device. The simplest
> + * way to use this interface is simply:
> + *
> + * cp foo.bit /dev/xilinx_icap
> + *
> + * Note that unless foo.bit is an appropriately constructed partial
> + * bitstream, this has a high likelyhood of overwriting the design
> + * currently programmed in the FPGA.
> + */
> +
> +#include <linux/version.h>
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/ioport.h>
> +#include <linux/interrupt.h>
> +#include <linux/fcntl.h>
> +#include <linux/init.h>
> +#include <linux/poll.h>
> +#include <linux/proc_fs.h>
> +#include <linux/spinlock.h>
> +#include <linux/sysctl.h>
> +#include <linux/version.h>
> +#include <linux/fs.h>
> +#include <linux/cdev.h>
> +#include <linux/platform_device.h>
> +
> +#include <asm/io.h>
> +#include <asm/uaccess.h>
> +#include <asm/system.h>
> +
> +#ifdef CONFIG_OF
> +/* For open firmware. */
> +#include <linux/of_device.h>
> +#include <linux/of_platform.h>
> +#endif
> +
> +#include "xilinx_hwicap.h"
> +
> +#define DRIVER_NAME "xilinx_icap"
> +
> +#define XHWICAP_REGS (0x10000)
> +
> +/* dynamically allocate device number */
> +static int xhwicap_major = 0;
> +static int xhwicap_minor = 0;
> +static int xhwicap_no_minors = 4;
> +module_param(xhwicap_major, int, S_IRUGO);
> +module_param(xhwicap_minor, int, S_IRUGO);
> +module_param(xhwicap_no_minors, int, S_IRUGO);
Why don't you request official major/minor numbers?
(Documentation/devices.txt)
> +
> +static struct class *icap_class;
> +
> +int xhwicap_initialize_xhwicap(struct xhwicap_drvdata *drvdata)
> +{
> +
> + u32 DeviceIdCode;
> + u32 Packet;
> + int Status;
> +
> + dev_dbg(drvdata->dev, "Reset...\n");
> +
> + /* Abort any current transaction, to make sure we have the ICAP in */
> + /* a good state. */
> + XHwIcap_mReset(drvdata->baseAddress);
> +
> + /* Read the IDCODE from ICAP if specified. */
> + {
> + dev_dbg(drvdata->dev, "Reading IDCODE...\n");
> +
> + /* Write bitstream to bram */
> + Packet = XHwIcap_Type1Read(XHI_IDCODE) | 1;
> + XHwIcap_StorageBufferWrite(drvdata, 0, XHI_DUMMY_PACKET);
> + XHwIcap_StorageBufferWrite(drvdata, 1, XHI_SYNC_PACKET);
> + XHwIcap_StorageBufferWrite(drvdata, 2, Packet);
> + XHwIcap_StorageBufferWrite(drvdata, 3, XHI_NOOP_PACKET);
> + XHwIcap_StorageBufferWrite(drvdata, 4, XHI_NOOP_PACKET);
> +
> + /* Transfer Bitstream from Bram to ICAP */
> + Status = XHwIcap_DeviceWrite(drvdata, 0, 5);
> + if (Status) {
> + return Status;
> + }
> +
> + /* Now readback one word into bram position
> + * XHI_EX_BITSTREAM_LENGTH*/
> + Status = XHwIcap_DeviceRead(drvdata, 5, 1);
> + if (Status) {
> + return Status;
> + }
> +
> + /* Return the Register value */
> + DeviceIdCode = XHwIcap_StorageBufferRead(drvdata, 5);
> +
> + /* Mask out the version section of the DeviceIdCode */
> + DeviceIdCode = DeviceIdCode & 0x0FFFFFFF;
> +
> + dev_dbg(drvdata->dev, "Desync...\n");
> + Status = XHwIcap_CommandDesync(drvdata);
> +
> + if (Status) {
> + return Status;
> + }
> + }
> +
> + /* Abort any current transaction, to make sure we have the ICAP in */
> + /* a good state. */
> + XHwIcap_mReset(drvdata->baseAddress);
> +
> + dev_info(drvdata->dev, "Device IDCODE = %x\n", DeviceIdCode);
> +
> + return 0;
> +}
> +
> +static ssize_t
> +xhwicap_read(struct file *file, char *buf, size_t count, loff_t *ppos)
> +{
> + struct xhwicap_drvdata *drvdata = file->private_data;
> + ssize_t bytes_to_read = 0;
> + u32 *kbuf;
> + u32 words;
> + u32 bytes_remaining;
> + int Status;
> +
> + if (drvdata->read_buffer_in_use) {
> + /* If there are leftover bytes in the buffer, just */
> + /* return them and don't try to read more from the */
> + /* ICAP device. */
> + bytes_to_read =
> + (count <
> + drvdata->read_buffer_in_use) ? count : drvdata->
> + read_buffer_in_use;
> +
> + /* Return the data currently in the read buffer. */
> + if (copy_to_user(buf, drvdata->read_buffer, bytes_to_read)) {
> + return -EFAULT;
> + }
> + drvdata->read_buffer_in_use -= bytes_to_read;
> + memcpy(drvdata->read_buffer + bytes_to_read,
> + drvdata->read_buffer, 4 - bytes_to_read);
> + } else {
> + /* Get new data from the ICAP, and return was was requested. */
> + kbuf = (u32 *) get_zeroed_page(GFP_KERNEL);
> + if (!kbuf)
> + return -ENOMEM;
> +
> + /* The ICAP device is only able to read complete */
> + /* words. If a number of bytes that do not correspond */
> + /* to complete words is requested, then we read enough */
> + /* words to get the required number of bytes, and then */
> + /* save the remaining bytes for the next read. */
> +
> + /* Determine the number of words to read, rounding up */
> + /* if necessary. */
> + words = ((count + 3) >> 2);
> + bytes_to_read = words << 2;
> +
> + if (bytes_to_read > PAGE_SIZE) {
> + bytes_to_read = PAGE_SIZE;
> + }
> + /* Ensure we only read a complete number of words. */
> + /* BUG: should be count & 3? */
> + bytes_remaining = bytes_to_read & 3;
> + bytes_to_read &= ~3;
> + words = bytes_to_read >> 2;
> +
> + Status = XHwIcap_GetConfiguration(drvdata, kbuf, words);
> + /* If we didn't read correctly, then bail out. */
> + if (Status) {
> + free_page((unsigned long)kbuf);
> + return -EFAULT;
> + }
> + /* If we fail to return the data to the user, then bail out. */
> + if (copy_to_user(buf, kbuf, bytes_to_read)) {
> + free_page((unsigned long)kbuf);
> + return -EFAULT;
> + }
> + memcpy(kbuf, drvdata->read_buffer, bytes_remaining);
> + drvdata->read_buffer_in_use = bytes_remaining;
> + free_page((unsigned long)kbuf);
> + }
> + return bytes_to_read;
> +}
> +
> +static ssize_t xhwicap_write(struct file *file, const char *buf,
> + size_t count, loff_t *ppos)
> +{
> + struct xhwicap_drvdata *drvdata = file->private_data;
> + ssize_t written = 0;
> + ssize_t left = count;
> + u32 *kbuf;
> + int len;
> + int Status;
> +
> + left += drvdata->write_buffer_in_use;
> +
> + /* only write multiples of 4 bytes. */
> + if (left < 4)
> + return 0;
> +
> + kbuf = (u32 *) __get_free_page(GFP_KERNEL);
> + if (!kbuf)
> + return -ENOMEM;
> +
> + while (left > 3) {
> + /* only write multiples of 4 bytes, so there might */
> + /* be as many as 3 bytes left (at the end). */
> + len = left;
> +
> + if (len > PAGE_SIZE)
> + len = PAGE_SIZE;
> + len &= ~3;
> +
> + if (drvdata->write_buffer_in_use) {
> + memcpy(kbuf, drvdata->write_buffer,
> + drvdata->write_buffer_in_use);
> + if (copy_from_user
> + ((((char *)kbuf) + (drvdata->write_buffer_in_use)),
> + buf + written,
> + len - (drvdata->write_buffer_in_use))) {
> + free_page((unsigned long)kbuf);
> + return -EFAULT;
> + }
> + } else {
> + if (copy_from_user(kbuf, buf + written, len)) {
> + free_page((unsigned long)kbuf);
> + return -EFAULT;
> + }
> + }
> +
> + Status = XHwIcap_SetConfiguration(drvdata, kbuf, len >> 2);
> +
> + if (Status) {
> + free_page((unsigned long)kbuf);
> + return -EFAULT;
> + }
> + if (drvdata->write_buffer_in_use) {
> + len -= drvdata->write_buffer_in_use;
> + left -= drvdata->write_buffer_in_use;
> + drvdata->write_buffer_in_use = 0;
> + }
> + written += len;
> + left -= len;
> + }
> + if ((left > 0) && (left < 4)) {
> + if (!copy_from_user(drvdata->write_buffer, buf + written, left)) {
> + drvdata->write_buffer_in_use = left;
> + written += left;
> + left = 0;
> + }
> + }
> +
> + free_page((unsigned long)kbuf);
> + return written;
> +}
> +
> +static int xhwicap_open(struct inode *inode, struct file *file)
> +{
> + struct xhwicap_drvdata *drvdata;
> + int status;
> +
> + drvdata = container_of(inode->i_cdev, struct xhwicap_drvdata, cdev);
> +
> + status = xhwicap_initialize_xhwicap(drvdata);
> + if (status) {
> + dev_err(drvdata->dev, "Failed to open file");
> + return -status;
> + }
> +
> + drvdata->flags = 0;
> + file->private_data = drvdata;
> + drvdata->write_buffer_in_use = 0;
> + drvdata->read_buffer_in_use = 0;
> +
> + return 0;
> +}
> +
> +static int xhwicap_release(struct inode *inode, struct file *file)
> +{
> + struct xhwicap_drvdata *drvdata = file->private_data;
> + int i;
> + int Status;
> +
> + if (drvdata->write_buffer_in_use) {
> + /* Flush write buffer. */
> + for (i = drvdata->write_buffer_in_use; i < 4; i++) {
> + drvdata->write_buffer[i] = 0;
> + }
> + Status =
> + XHwIcap_SetConfiguration(drvdata,
> + (u32 *) drvdata->write_buffer, 1);
> + if (Status) {
> + return Status;
> + }
> + }
> +
> + Status = XHwIcap_CommandDesync(drvdata);
> + if (Status) {
> + return Status;
> + }
> +
> + return 0;
> +}
> +
> +static struct file_operations xhwicap_fops = {
> + .owner = THIS_MODULE,
> + .write = xhwicap_write,
> + .read = xhwicap_read,
> + .open = xhwicap_open,
> + .release = xhwicap_release,
> +};
> +
> +static int __init xhwicap_drv_probe(struct device *dev)
> +{
> + dev_t devt;
> + struct platform_device *pdev = to_platform_device(dev);
> + struct xhwicap_drvdata *drvdata = NULL;
> + struct resource *regs_res;
> + int retval = 0;
> +
> + if (!dev) {
> + return -EINVAL;
> + }
> +
> + dev_info(dev, "Xilinx icap port driver\n");
> +
> + devt = MKDEV(xhwicap_major, xhwicap_minor + pdev->id);
> +
> + drvdata = kmalloc(sizeof(struct xhwicap_drvdata), GFP_KERNEL);
> + if (!drvdata) {
> + dev_err(dev, "Couldn't allocate device private record\n");
> + return -ENOMEM;
> + }
> + memset((void *)drvdata, 0, sizeof(struct xhwicap_drvdata));
> + dev_set_drvdata(dev, (void *)drvdata);
> +
> + /* Map the control registers in */
> + regs_res = platform_get_resource(to_platform_device(dev),
> + IORESOURCE_MEM, 0);
> + if (!regs_res) {
> + dev_err(dev, "Couldn't get registers resource\n");
> + retval = -EFAULT;
> + goto failed1;
> + }
> +
> + drvdata->mem_start = regs_res->start;
> + drvdata->mem_end = regs_res->end;
> + drvdata->mem_size = regs_res->end - regs_res->start + 1;
> +
> + if (drvdata->mem_size < XHWICAP_REGS) {
> + dev_err(dev, "Couldn't get registers resource\n");
> + retval = -EFAULT;
> + goto failed1;
> + }
> +
> + if (!request_mem_region(drvdata->mem_start, drvdata->mem_size, DRIVER_NAME)) {
> + dev_err(dev, "Couldn't lock memory region at %p\n",
> + (void *)regs_res->start);
> + retval = -EBUSY;
> + goto failed1;
> + }
> +
> + drvdata->devt = devt;
> + drvdata->dev = dev;
> + drvdata->baseAddress = ioremap(drvdata->mem_start, drvdata->mem_size);
> + if (!drvdata->baseAddress) {
> + dev_err(dev, "ioremap() failed\n");
> + goto failed2;
> + }
> +
> + dev_info(dev, "ioremap %lx to %p with size %x\n",
> + (unsigned long int)drvdata->mem_start,
> + drvdata->baseAddress, drvdata->mem_size);
> +
> + cdev_init(&drvdata->cdev, &xhwicap_fops);
> + drvdata->cdev.owner = THIS_MODULE;
> + retval = cdev_add(&drvdata->cdev, devt, 1);
> + if (retval) {
> + dev_err(dev, "cdev_add() failed\n");
> + goto failed3;
> + }
> + /* devfs_mk_cdev(devt, S_IFCHR|S_IRUGO|S_IWUGO, DRIVER_NAME); */
> + class_device_create(icap_class, NULL, devt, NULL, DRIVER_NAME);
> + return 0; /* success */
> +
> + failed3:
> + iounmap(drvdata->baseAddress);
> +
> + failed2:
> + release_mem_region(regs_res->start, drvdata->mem_size);
> +
> + failed1:
> + kfree(drvdata);
> +
> + return retval;
> +}
> +
> +static int __exit xhwicap_drv_remove(struct device *dev)
> +{
> + struct xhwicap_drvdata *drvdata;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + drvdata = (struct xhwicap_drvdata *)dev_get_drvdata(dev);
> +
> + class_device_destroy(icap_class, drvdata->devt);
> + cdev_del(&drvdata->cdev);
> + iounmap(drvdata->baseAddress);
> + release_mem_region(drvdata->mem_start, drvdata->mem_size);
> + kfree(drvdata);
> + dev_set_drvdata(dev, NULL);
> +
> + return 0; /* success */
> +}
> +
> +static struct device_driver xhwicap_module_driver = {
> + .name = DRIVER_NAME,
> + .bus = &platform_bus_type,
> +
> + .probe = xhwicap_drv_probe,
> + .remove = xhwicap_drv_remove,
> +};
Please use struct platform_driver instead.
> +
> +static int __init xhwicap_module_init(void)
> +{
> + dev_t devt;
> + int retval;
> +
> + icap_class = class_create(THIS_MODULE, "xilinx_config");
What's that for?
> +
> + if (xhwicap_major) {
> + devt = MKDEV(xhwicap_major, xhwicap_minor);
> + retval = register_chrdev_region(devt, xhwicap_no_minors,
> + DRIVER_NAME);
> + } else {
> + retval =
> + alloc_chrdev_region(&devt, xhwicap_minor, xhwicap_no_minors,
> + DRIVER_NAME);
> + xhwicap_major = MAJOR(devt);
> + }
> + if (retval < 0) {
> + xhwicap_major = 0;
> + return retval;
> + }
> +
> + retval = driver_register(&xhwicap_module_driver);
> +
> + if (retval) {
> + unregister_chrdev_region(devt, xhwicap_no_minors);
> + }
> +
> + return retval;
> +}
> +
> +static void __exit xhwicap_module_cleanup(void)
> +{
> + dev_t devt = MKDEV(xhwicap_major, xhwicap_minor);
> +
> + class_destroy(icap_class);
> +
> + driver_unregister(&xhwicap_module_driver);
> +
> + unregister_chrdev_region(devt, xhwicap_no_minors);
> +}
> +
> +module_init(xhwicap_module_init);
> +module_exit(xhwicap_module_cleanup);
> +
> +#ifdef CONFIG_OF
> +
> +static int __init xilinx_hwicap_of_init(void)
> +{
> + struct device_node *np;
> + unsigned int i;
> + struct platform_device *pdev;
> + int ret;
> +
> + for (np = NULL, i = 0;
> + (np = of_find_compatible_node(np, NULL, "xlnx,opb-hwicap")) != NULL;
> + i++) {
> + struct resource r;
> +
> + memset(&r, 0, sizeof(r));
> +
> + ret = of_address_to_resource(np, 0, &r);
> + if (ret)
> + goto err;
> + pdev =
> + platform_device_register_simple(DRIVER_NAME, i, &r, 1);
> +
> + if (IS_ERR(pdev)) {
> + ret = PTR_ERR(pdev);
> + goto err;
> + }
> + }
> +
> + return 0;
> +err:
> + return ret;
> +}
> +
> +module_init(xilinx_hwicap_of_init);
> +
> +#endif
> +
> +MODULE_AUTHOR("Xilinx, Inc; Xilinx Research Labs Group");
> +MODULE_DESCRIPTION("Xilinx ICAP Port Driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/char/xilinx_hwicap/xilinx_hwicap.h b/drivers/char/xilinx_hwicap/xilinx_hwicap.h
> new file mode 100644
> index 0000000..80e3fe0
> --- /dev/null
> +++ b/drivers/char/xilinx_hwicap/xilinx_hwicap.h
> @@ -0,0 +1,539 @@
> +/*****************************************************************************
> + *
> + * Author: Xilinx, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
> + * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
> + * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
> + * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
> + * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
> + * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
> + * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
> + * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
> + * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
> + * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
> + * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
> + * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
> + * FOR A PARTICULAR PURPOSE.
> + *
> + * Xilinx products are not intended for use in life support appliances,
> + * devices, or systems. Use in such applications is expressly prohibited.
> + *
> + * (c) Copyright 2003-2007 Xilinx Inc.
> + * All rights reserved.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, write to the Free Software Foundation, Inc.,
> + * 675 Mass Ave, Cambridge, MA 02139, USA.
> + *
> + *****************************************************************************/
> +
> +#ifndef XILINX_HWICAP_H_ /* prevent circular inclusions */
> +#define XILINX_HWICAP_H_ /* by using protection macros */
> +
> +#include <linux/types.h>
> +#include <linux/cdev.h>
> +#include <linux/version.h>
> +#include <linux/platform_device.h>
> +
> +#include <asm/io.h>
> +
> +struct xhwicap_drvdata {
> + u32 flags;
> + u32 write_buffer_in_use; /* Always in [0,3] */
> + u8 write_buffer[4];
> + u32 read_buffer_in_use; /* Always in [0,3] */
> + u8 read_buffer[4];
> + u32 mem_start; /* phys. address of the control registers */
> + u32 mem_end; /* phys. address of the control registers */
> + u32 mem_size;
> + void __iomem *baseAddress;/* virt. address of the control registers */
> +
> + struct device *dev;
> + struct cdev cdev; /* Char device structure */
> + dev_t devt;
> +};
> +
> +/***************************** Include Files ********************************/
> +
> +#define virtex2 0
> +#define virtex4 1
> +
> +#ifdef CONFIG_XILINX_VIRTEX_4_FX
> +#define XHI_FAMILY virtex4
> +#else
> +#define XHI_FAMILY virtex2
> +#endif
So having a single kernel with v2p/v4 support is not an option?
> +
> +/************************** Constant Definitions ****************************/
> +
> +#define XHI_PAD_FRAMES 0x1
> +
> +/* Mask for calculating configuration packet headers */
> +#define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL
> +#define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL
> +#define XHI_TYPE_MASK 0x7
> +#define XHI_REGISTER_MASK 0xF
> +#define XHI_OP_MASK 0x3
> +
> +#define XHI_TYPE_SHIFT 29
> +#define XHI_REGISTER_SHIFT 13
> +#define XHI_OP_SHIFT 27
> +
> +#define XHI_TYPE_1 1
> +#define XHI_TYPE_2 2
> +#define XHI_OP_WRITE 2
> +#define XHI_OP_READ 1
> +
> +/* Address Block Types */
> +#define XHI_FAR_CLB_BLOCK 0
> +#define XHI_FAR_BRAM_BLOCK 1
> +#define XHI_FAR_BRAM_INT_BLOCK 2
> +
> +/* Addresses of the Configuration Registers */
> +#define XHI_CRC 0
> +#define XHI_FAR 1
> +#define XHI_FDRI 2
> +#define XHI_FDRO 3
> +#define XHI_CMD 4
> +#define XHI_CTL 5
> +#define XHI_MASK 6
> +#define XHI_STAT 7
> +#define XHI_LOUT 8
> +#define XHI_COR 9
> +#define XHI_MFWR 10
> +
> +#if XHI_FAMILY == virtex4
> +
> +#define XHI_CBC 11
> +#define XHI_IDCODE 12
> +#define XHI_AXSS 13
> +#define XHI_NUM_REGISTERS 14
> +
> +#else
> +
> +#define XHI_FLR 11
> +#define XHI_KEY 12
> +#define XHI_CBC 13
> +#define XHI_IDCODE 14
> +#define XHI_NUM_REGISTERS 15
> +
> +#endif
> +
> +/* Configuration Commands */
> +#define XHI_CMD_NULL 0
> +#define XHI_CMD_WCFG 1
> +#define XHI_CMD_MFW 2
> +#define XHI_CMD_DGHIGH 3
> +#define XHI_CMD_RCFG 4
> +#define XHI_CMD_START 5
> +#define XHI_CMD_RCAP 6
> +#define XHI_CMD_RCRC 7
> +#define XHI_CMD_AGHIGH 8
> +#define XHI_CMD_SWITCH 9
> +#define XHI_CMD_GRESTORE 10
> +#define XHI_CMD_SHUTDOWN 11
> +#define XHI_CMD_GCAPTURE 12
> +#define XHI_CMD_DESYNCH 13
> +
> +/* Packet constants */
> +#define XHI_SYNC_PACKET 0xAA995566UL
> +#define XHI_DUMMY_PACKET 0xFFFFFFFFUL
> +#define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT)
> +#define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
> + (XHI_OP_READ << XHI_OP_SHIFT))
> +
> +#define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
> + (XHI_OP_WRITE << XHI_OP_SHIFT))
> +
> +#define XHI_TYPE2_CNT_MASK 0x07FFFFFF
> +
> +#define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL
> +#define XHI_TYPE_1_HEADER_BYTES 4
> +#define XHI_TYPE_2_HEADER_BYTES 8
> +
> +/* Indicates how many bytes will fit in a buffer. (1 BRAM) */
> +#define XHI_MAX_BUFFER_BYTES 2048
> +#define XHI_MAX_BUFFER_INTS 512
> +
> +/* Number of frames in different tile types */
> +#if XHI_FAMILY == virtex4
> +
> +#define XHI_GCLK_FRAMES 3
> +#define XHI_IOB_FRAMES 30
> +#define XHI_DSP_FRAMES 21
> +#define XHI_CLB_FRAMES 22
> +#define XHI_BRAM_FRAMES 64
> +#define XHI_BRAM_INT_FRAMES 20
> +
> +#else
> +
> +#define XHI_GCLK_FRAMES 4
> +#define XHI_IOB_FRAMES 4
> +#define XHI_IOI_FRAMES 22
> +#define XHI_CLB_FRAMES 22
> +#define XHI_BRAM_FRAMES 64
> +#define XHI_BRAM_INT_FRAMES 22
> +
> +#endif
> +
> +/* Device Resources */
> +#define CLB 0
> +#define DSP 1
> +#define BRAM 2
> +#define BRAM_INT 3
> +#define IOB 4
> +#define IOI 5
> +#define CLK 6
> +#define MGT 7
> +
> +#define BLOCKTYPE0 0
> +#define BLOCKTYPE1 1
> +#define BLOCKTYPE2 2
> +
> +/* The number of words reserved for the header in the storage buffer. */
> +/* MAY CHANGE FOR V4 */
> +#define XHI_HEADER_BUFFER_WORDS 20
> +#define XHI_HEADER_BUFFER_BYTES (XHI_HEADER_BUFFER_WORDS << 2)
> +
> +/* CLB major frames start at 3 for the first column (since we are using
> + * column numbers that start at 1, when the column is added to this offset,
> + * that first one will be 3 as required. */
> +#define XHI_CLB_MAJOR_FRAME_OFFSET 2
> +
> +/* File access and error constants */
> +#define XHI_DEVICE_READ_ERROR -1
> +#define XHI_DEVICE_WRITE_ERROR -2
> +#define XHI_BUFFER_OVERFLOW_ERROR -3
> +
> +#define XHI_DEVICE_READ 0x1
> +#define XHI_DEVICE_WRITE 0x0
> +
> +/* Constants for checking transfer status */
> +#define XHI_CYCLE_DONE 0
> +#define XHI_CYCLE_EXECUTING 1
> +
> +/* Constant to use for CRC check when CRC has been disabled */
> +#define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL
> +
> +/* Major Row Offset */
> +#define XHI_CLB_MAJOR_ROW_OFFSET 96+(32*XHI_HEADER_BUFFER_WORDS)-1
> +
> +/* Number of times to poll the done regsiter */
> +#define XHI_MAX_RETRIES 1000
> +
> +/************************** Constant Definitions ****************************/
> +
> +/* XHwIcap register offsets */
> +
> +/* Size of transfer, read & write */
> +#define XHI_SIZE_REG_OFFSET 0x800L
> +/* Offset into bram, read & write */
> +#define XHI_BRAM_OFFSET_REG_OFFSET 0x804L
> +/* Read not Configure, direction of transfer. Write only */
> +#define XHI_RNC_REG_OFFSET 0x808L
> +/* Indicates transfer complete. Read only */
> +#define XHI_STATUS_REG_OFFSET 0x80CL
> +
> +/* Constants for setting the RNC register */
> +#define XHI_CONFIGURE 0x0UL
> +#define XHI_READBACK 0x1UL
> +
> +/* Constants for the Done register */
> +#define XHI_NOT_FINISHED 0x0UL
> +#define XHI_FINISHED 0x1UL
> +
> +/**************************** Type Definitions ******************************/
> +
> +/***************** Macros (Inline Functions) Definitions ********************/
> +
> +/****************************************************************************/
> +/**
> +*
> +* Get the contents of the size register.
> +*
> +* The size register holds the number of 32 bit words to transfer between
> +* bram and the icap (or icap to bram).
> +*
> +* @param BaseAddress is the base address of the device
> +*
> +* @return A 32-bit value representing the contents of the size
> +* register.
> +*
> +* @note
> +*
> +* u32 XHwIcap_mGetSizeReg(u32 BaseAddress);
> +*
> +*****************************************************************************/
> +#define XHwIcap_mGetSizeReg(BaseAddress) \
> + (in_be32((u32 *)((BaseAddress) + XHI_SIZE_REG_OFFSET)))
> +
> +/****************************************************************************/
Why not a single getter with a offset/register parameter instead of
all these? And use inline functions instead of macros.
> +/**
> +*
> +* Get the contents of the bram offset register.
> +*
> +* The bram offset register holds the starting bram address to transfer
> +* data from during configuration or write data to during readback.
> +*
> +* @param BaseAddress is the base address of the device
> +*
> +* @return A 32-bit value representing the contents of the bram offset
> +* register.
> +*
> +* @note
> +*
> +* u32 XHwIcap_mGetOffsetReg(u32 BaseAddress);
> +*
> +*****************************************************************************/
> +#define XHwIcap_mGetOffsetReg(BaseAddress) \
> + (in_be32((u32 *)((BaseAddress + XHI_BRAM_OFFSET_REG_OFFSET))))
> +
> +/****************************************************************************/
> +/**
> +*
> +* Get the contents of the done register.
> +*
> +* The done register is set to zero during configuration or readback.
> +* When the current configuration or readback completes the done register
> +* is set to one.
> +*
> +* @param BaseAddress is the base address of the device
> +*
> +* @return A 32-bit value with bit 1 representing done or not
> +*
> +* @note
> +*
> +* u32 XHwIcap_mGetDoneReg(u32 BaseAddress);
> +*
> +*****************************************************************************/
> +
> +#define XHwIcap_mGetDoneReg(BaseAddress) \
> + (in_be32((u32 *)((BaseAddress + XHI_STATUS_REG_OFFSET))) & 1)
> +
> +/****************************************************************************/
> +/**
> +*
> +* Get the contents of the status register.
> +*
> +* The status register contains the ICAP status and the done bit.
> +*
> +* D8 - cfgerr
> +* D7 - dalign
> +* D6 - rip
> +* D5 - in_abort_l
> +* D4 - Always 1
> +* D3 - Always 1
> +* D2 - Always 1
> +* D1 - Always 1
> +* D0 - Done bit
> +*
> +* @param BaseAddress is the base address of the device
> +*
> +* @return A 32-bit value representing the contents of the status register
> +*
> +* @note
> +*
> +* u32 XHwIcap_mGetStatusReg(u32 BaseAddress);
> +*
> +*****************************************************************************/
> +
> +#define XHwIcap_mGetStatusReg(BaseAddress) \
> + (in_be32((u32 *)((BaseAddress + XHI_STATUS_REG_OFFSET))))
> +
> +#define XHwIcap_mReset(BaseAddress) \
> + (out_be32((u32 *)((BaseAddress + XHI_STATUS_REG_OFFSET)), 0xFEFE))
> +
> +/****************************************************************************/
> +/**
> +* Reads data from the storage buffer bram.
> +*
> +* A bram is used as a configuration memory cache. One frame of data can
> +* be stored in this "storage buffer".
> +*
> +* @param BaseAddress - contains the base address of the component.
> +*
> +* @param Offset - The offset into which the data should be read.
> +*
> +* @return The value of the specified offset in the bram.
> +*
> +* @note
> +*
> +* u32 XHwIcap_mGetBram(u32 BaseAddress, u32 Offset);
> +*
> +*****************************************************************************/
> +#define XHwIcap_mGetBram(BaseAddress, Offset) \
> + (in_be32((u32 *)((BaseAddress+(Offset<<2)))))
> +
> +/****************************************************************************/
> +/**
> +* Set the size register.
> +*
> +* The size register holds the number of 8 bit bytes to transfer between
> +* bram and the icap (or icap to bram).
> +*
> +* @param BaseAddress - contains the base address of the device.
> +*
> +* @param Data - The size in bytes.
> +*
> +* @return None.
> +*
> +* @note
> +*
> +* void XHwIcap_mSetSizeReg(u32 BaseAddress, u32 Data);
> +*
> +*****************************************************************************/
> +#define XHwIcap_mSetSizeReg(BaseAddress, Data) \
> + (out_be32((u32 *)((BaseAddress) + XHI_SIZE_REG_OFFSET), (Data)))
> +
> +/****************************************************************************/
> +/**
> +* Set the bram offset register.
> +*
> +* The bram offset register holds the starting bram address to transfer
> +* data from during configuration or write data to during readback.
> +*
> +* @param BaseAddress contains the base address of the device.
> +*
> +* @param Data is the value to be written to the data register.
> +*
> +* @return None.
> +*
> +* @note
> +*
> +* void XHwIcap_mSetOffsetReg(u32 BaseAddress, u32 Data);
> +*
> +*****************************************************************************/
> +#define XHwIcap_mSetOffsetReg(BaseAddress, Data) \
> + (out_be32((u32 *)((BaseAddress) + XHI_BRAM_OFFSET_REG_OFFSET), (Data)))
> +
> +/****************************************************************************/
> +/**
> +* Set the RNC (Readback not Configure) register.
> +*
> +* The RNC register determines the direction of the data transfer. It
> +* controls whether a configuration or readback take place. Writing to
> +* this register initiates the transfer. A value of 1 initiates a
> +* readback while writing a value of 0 initiates a configuration.
> +*
> +* @param BaseAddress contains the base address of the device.
> +*
> +* @param Data is the value to be written to the data register.
> +*
> +* @return None.
> +*
> +* @note
> +*
> +* void XHwIcap_mSetRncReg(u32 BaseAddress, u32 Data);
> +*
> +*****************************************************************************/
> +#define XHwIcap_mSetRncReg(BaseAddress, Data) \
> + (out_be32((u32 *)((BaseAddress) + XHI_RNC_REG_OFFSET), (Data)))
> +
> +/****************************************************************************/
> +/**
> +* Write data to the storage buffer bram.
> +*
> +* A bram is used as a configuration memory cache. One frame of data can
> +* be stored in this "storage buffer".
> +*
> +* @param BaseAddress - contains the base address of the component.
> +*
> +* @param Offset - The offset into which the data should be written.
> +*
> +* @param Data - The value to be written to the bram offset.
> +*
> +* @return None.
> +*
> +* @note
> +*
> +* void XHwIcap_mSetBram(u32 BaseAddress, u32 Offset, u32 Data);
> +*
> +*****************************************************************************/
> +#define XHwIcap_mSetBram(BaseAddress, Offset, Data) \
> + (out_be32((u32 *)((BaseAddress+(Offset<<2))), (Data)))
> +
> +/****************************************************************************/
> +/**
> +*
> +* Generates a Type 1 packet header that reads back the requested configuration
> +* register.
> +*
> +* @param Register is the address of the register to be read back.
> +* Register constants are defined in this file.
> +*
> +* @return Type 1 packet header to read the specified register
> +*
> +* @note None.
> +*
> +*****************************************************************************/
> +#define XHwIcap_Type1Read(Register) \
> + ((XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
> + (XHI_OP_READ << XHI_OP_SHIFT))
> +
> +/****************************************************************************/
> +/**
> +*
> +* Generates a Type 1 packet header that writes to the requested
> +* configuration register.
> +*
> +* @param Register is the address of the register to be written to.
> +* Register constants are defined in this file.
> +*
> +* @return Type 1 packet header to write the specified register
> +*
> +* @note None.
> +*
> +*****************************************************************************/
> +#define XHwIcap_Type1Write(Register) \
> + ((XHI_TYPE_1 << XHI_TYPE_SHIFT) | (Register << XHI_REGISTER_SHIFT) | \
> + (XHI_OP_WRITE << XHI_OP_SHIFT))
> +
> +/************************** Function Prototypes *****************************/
> +
> +/* These functions are the ones defined in the lower level
> + * Self-Reconfiguration Platform (SRP) API.
> + */
> +
> +/* Initializes a XHwIcap instance.. */
> +int XHwIcap_Initialize(struct xhwicap_drvdata *InstancePtr, u16 DeviceId,
> + u32 DeviceIdCode);
> +
> +/* Reads integers from the device into the storage buffer. */
> +int XHwIcap_DeviceRead(struct xhwicap_drvdata *InstancePtr, u32 Offset,
> + u32 NumInts);
> +
> +/* Writes integers to the device from the storage buffer. */
> +int XHwIcap_DeviceWrite(struct xhwicap_drvdata *InstancePtr, u32 Offset,
> + u32 NumInts);
> +
> +/* Writes word to the storage buffer. */
> +void XHwIcap_StorageBufferWrite(struct xhwicap_drvdata *InstancePtr,
> + u32 Address, u32 Data);
> +
> +/* Reads word from the storage buffer. */
> +u32 XHwIcap_StorageBufferRead(struct xhwicap_drvdata *InstancePtr, u32 Address);
> +
> +/* Loads a partial bitstream from system memory. */
> +int XHwIcap_SetConfiguration(struct xhwicap_drvdata *InstancePtr, u32 *Data,
> + u32 Size);
> +
> +/* Loads a partial bitstream from system memory. */
> +int XHwIcap_GetConfiguration(struct xhwicap_drvdata *InstancePtr, u32 *Data,
> + u32 Size);
> +
> +/* Sends a DESYNC command to the ICAP */
> +int XHwIcap_CommandDesync(struct xhwicap_drvdata *InstancePtr);
> +
> +/* Sends a CAPTURE command to the ICAP */
> +int XHwIcap_CommandCapture(struct xhwicap_drvdata *InstancePtr);
> +
> +/* Returns the value of the specified configuration register */
> +u32 XHwIcap_GetConfigReg(struct xhwicap_drvdata *InstancePtr, u32 ConfigReg);
> +
> +#endif
> --
> 1.5.3.4-dirty
>
--
Bye, Peter Korsgaard
^ permalink raw reply
* Re: [PATCH v2] Fix hardware IRQ time accounting problem.
From: Frederik Himpe @ 2007-12-05 11:39 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel, linux-usb-devel
In-Reply-To: <20071204055144.GR24243@bakeyournoodle.com>
On Tue, 04 Dec 2007 16:51:44 +1100, Tony Breeds wrote:
> The commit fa13a5a1f25f671d084d8884be96fc48d9b68275 (sched: restore
> deterministic CPU accounting on powerpc), unconditionally calls
> update_process_tick() in system context. In the deterministic
> accounting case this is the correct thing to do. However, in the
> non-deterministic accounting case we need to not do this, and results in
> the time accounted as hardware irq time being artificially elevated.
>
> Also this patch collapses 2 consecutive '#ifdef
> CONFIG_VIRT_CPU_ACCOUNTING' checks in time.h into one for neatness.
I can confirm this patch fixed the problem for me. Thank you!
--
Frederik Himpe
^ permalink raw reply
* Re: drivers/net/iseries_veth.c dubious sysfs usage
From: Michael Ellerman @ 2007-12-05 11:10 UTC (permalink / raw)
To: Greg KH; +Cc: linuxppc-dev, Kyle A. Lucke, paulus, linux-kernel, David Gibson
In-Reply-To: <20071205093054.GA23229@kroah.com>
[-- Attachment #1: Type: text/plain, Size: 1087 bytes --]
On Wed, 2007-12-05 at 01:30 -0800, Greg KH wrote:
> In doing a massive kobject cleanup of the kernel tree, I ran across the
> iseries_veth.c driver.
>
> It looks like the driver is creating a number of subdirectories under
> the driver sysfs directory. This is odd and probably wrong. You want
> these virtual connections to show up in the main sysfs device tree, not
> under the driver directory.
>
> I'll be glad to totally guess and try to move it around in the sysfs
> tree, but odds are I'll get it all wrong as I can't really test this
> out :)
>
> Any hints on what this driver is trying to do in this sysfs directories?
I wrote the code, I think, but it's been a while - I'll have a look at
it tomorrow.
Why is it "odd and probably wrong" to create subdirectories under the
driver in sysfs?
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
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^ permalink raw reply
* Re: OT: Re: solved: Re: [rtc-linux] Re: DS1337 RTC on I2C broken.
From: Clemens Koller @ 2007-12-05 10:30 UTC (permalink / raw)
To: Jon Smirl; +Cc: Alessandro Zummo, rtc-linux, linuxppc-embedded
In-Reply-To: <9e4733910712040919v6208c5a3o1afd456c86a37589@mail.gmail.com>
Jon Smirl schrieb:
> On 12/4/07, Clemens Koller <clemens.koller@anagramm.de> wrote:
>> That was discussed already in detail in several threads and there
>> were already decisions made that the DT went into the kernel - no problem
>> with that.
>> I just don't see that it 'really does help' in it's current state if
>> things are broken in a way they are hard to fix for non DT-familiar
>> developers, almost impossible to fix for users which just need to
>> compile their own kernel to achieve their project goal.
>>
>> Well... let's take it easy. I'll dig into the pcf8563 code now.
>
> Most of this is addressed in the patch series starting with this message:
> http://ozlabs.org/pipermail/linuxppc-dev/2007-December/047382.html
>
> The pcf8563 driver is converted to the new format and is modified to
> pick up it's address from the device tree.
>
> This patch series is being held waiting for an ok on the low level
> changes to the i2c subsystem. Hopefully it will go into 2.6.25
Thanks Jon, thanks Scott for the pointers, this works for me.
(Patches have some whitespace damage, you propably want to run
it thru checkpatch.pl before pushing upstream.)
Regards,
--
Clemens Koller
__________________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Straße 45/1
Linhof Werksgelände
D-81379 München
Tel.089-741518-50
Fax 089-741518-19
http://www.anagramm-technology.com
^ permalink raw reply
* [PATCH] add MPC837x MDS board default device tree
From: Li Yang @ 2007-12-05 10:37 UTC (permalink / raw)
To: galak, linuxppc-dev; +Cc: Li Yang
Signed-off-by: Li Yang <leoli@freescale.com>
---
Update SATA nodes; remove serdes nodes; add aliases and labels.
arch/powerpc/boot/dts/mpc8377_mds.dts | 270 +++++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8378_mds.dts | 256 +++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8379_mds.dts | 284 +++++++++++++++++++++++++++++++++
3 files changed, 810 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc8377_mds.dts
create mode 100644 arch/powerpc/boot/dts/mpc8378_mds.dts
create mode 100644 arch/powerpc/boot/dts/mpc8379_mds.dts
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
new file mode 100644
index 0000000..919ffd0
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -0,0 +1,270 @@
+/*
+ * MPC8377E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8377emds";
+ compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = "/soc@e0000000/ethernet@24000";
+ ethernet1 = "/soc@e0000000/ethernet@25000";
+ serial0 = "/soc@e0000000/serial@4500";
+ serial1 = "/soc@e0000000/serial@4600";
+ pci0 = "/pci@e0008500";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "fsl_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = "cpu";
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet0: ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ enet1: ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial0: serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial1:serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000001fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@18000 {
+ compatible = "fsl,mpc8379-sata", "fsl,pq2pro-sata";
+ reg = <18000 1000>;
+ interrupts = <2c 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@19000 {
+ compatible = "fsl,mpc8379-sata", "fsl,pq2pro-sata";
+ reg = <19000 1000>;
+ interrupts = <2d 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci0: pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e0300000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
new file mode 100644
index 0000000..9208f62
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -0,0 +1,256 @@
+/*
+ * MPC8378E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8378emds";
+ compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = "/soc@e0000000/ethernet@24000";
+ ethernet1 = "/soc@e0000000/ethernet@25000";
+ serial0 = "/soc@e0000000/serial@4500";
+ serial1 = "/soc@e0000000/serial@4600";
+ pci0 = "/pci@e0008500";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "fsl_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = "cpu";
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet0: ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ enet1: ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial0: serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial1:serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000001fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci0: pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e0300000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+};
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
new file mode 100644
index 0000000..ad4876c
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -0,0 +1,284 @@
+/*
+ * MPC8379E MDS Device Tree Source
+ *
+ * Copyright 2007 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/ {
+ model = "fsl,mpc8379emds";
+ compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = "/soc@e0000000/ethernet@24000";
+ ethernet1 = "/soc@e0000000/ethernet@25000";
+ serial0 = "/soc@e0000000/serial@4500";
+ serial1 = "/soc@e0000000/serial@4600";
+ pci0 = "/pci@e0008500";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,837x@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 20000000>; // 512MB at 0
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = < &ipic >;
+ dfsrr;
+ };
+
+ spi@7000 {
+ compatible = "fsl_spi";
+ reg = <7000 1000>;
+ interrupts = <10 8>;
+ interrupt-parent = < &ipic >;
+ mode = "cpu";
+ };
+
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = < &ipic >;
+ interrupts = <26 8>;
+ phy_type = "utmi_wide";
+ };
+
+ mdio@24520 {
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy2: ethernet-phy@2 {
+ interrupt-parent = < &ipic >;
+ interrupts = <11 8>;
+ reg = <2>;
+ device_type = "ethernet-phy";
+ };
+ phy3: ethernet-phy@3 {
+ interrupt-parent = < &ipic >;
+ interrupts = <12 8>;
+ reg = <3>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet0: ethernet@24000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8 21 8 22 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy2 >;
+ };
+
+ enet1: ethernet@25000 {
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 8 24 8 25 8>;
+ phy-connection-type = "mii";
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy3 >;
+ };
+
+ serial0: serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <0>;
+ interrupts = <9 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ serial1:serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <0>;
+ interrupts = <a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ crypto@30000 {
+ model = "SEC3";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = < &ipic >;
+ /* Rev. 3.0 geometry */
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <000001fe>;
+ descriptor-types-mask = <03ab0ebf>;
+ };
+
+ sdhc@2e000 {
+ model = "eSDHC";
+ compatible = "fsl,esdhc";
+ reg = <2e000 1000>;
+ interrupts = <2a 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@18000 {
+ compatible = "fsl,mpc8379-sata", "fsl,pq2pro-sata";
+ reg = <18000 1000>;
+ interrupts = <2c 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@19000 {
+ compatible = "fsl,mpc8379-sata", "fsl,pq2pro-sata";
+ reg = <19000 1000>;
+ interrupts = <2d 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@1a000 {
+ compatible = "fsl,mpc8379-sata", "fsl,pq2pro-sata";
+ reg = <1a000 1000>;
+ interrupts = <2e 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ sata@1b000 {
+ compatible = "fsl,mpc8379-sata", "fsl,pq2pro-sata";
+ reg = <1b000 1000>;
+ interrupts = <2f 8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ compatible = "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ };
+ };
+
+ pci0: pci@e0008500 {
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 8800 0 0 1 &ipic 14 8
+ 8800 0 0 2 &ipic 15 8
+ 8800 0 0 3 &ipic 16 8
+ 8800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x12 */
+ 9000 0 0 1 &ipic 16 8
+ 9000 0 0 2 &ipic 17 8
+ 9000 0 0 3 &ipic 14 8
+ 9000 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x13 */
+ 9800 0 0 1 &ipic 17 8
+ 9800 0 0 2 &ipic 14 8
+ 9800 0 0 3 &ipic 15 8
+ 9800 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 &ipic 14 8
+ a800 0 0 2 &ipic 15 8
+ a800 0 0 3 &ipic 16 8
+ a800 0 0 4 &ipic 17 8
+
+ /* IDSEL 0x16 */
+ b000 0 0 1 &ipic 17 8
+ b000 0 0 2 &ipic 14 8
+ b000 0 0 3 &ipic 15 8
+ b000 0 0 4 &ipic 16 8
+
+ /* IDSEL 0x17 */
+ b800 0 0 1 &ipic 16 8
+ b800 0 0 2 &ipic 17 8
+ b800 0 0 3 &ipic 14 8
+ b800 0 0 4 &ipic 15 8
+
+ /* IDSEL 0x18 */
+ c000 0 0 1 &ipic 15 8
+ c000 0 0 2 &ipic 16 8
+ c000 0 0 3 &ipic 17 8
+ c000 0 0 4 &ipic 14 8>;
+ interrupt-parent = < &ipic >;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 90000000 90000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e0300000 0 00100000>;
+ clock-frequency = <0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008500 100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+};
--
1.5.3.5.643.g40e25
^ permalink raw reply related
* Re: OT: Re: solved: Re: [rtc-linux] Re: DS1337 RTC on I2C broken.
From: Clemens Koller @ 2007-12-05 10:27 UTC (permalink / raw)
To: Scott Wood; +Cc: Alessandro Zummo, rtc-linux, linuxppc-embedded
In-Reply-To: <47557B6B.9020105@freescale.com>
Hi, Scott!
>> Well, the subject is about RTCs.
>
> Not really, it's about a change in the i2c subsystem (I noticed you
> didn't include the i2c list or linuxppc-dev... you'd get a larger
> audience of the people that actually made the change that way). That it
> happens to be an RTC chip you're using on the i2c bus is an
> inconsequential detail.
Looks like I wasn't subscribed to the list anymore, so I
missed lots of DT related discussions - my bad. :-(
>> Well... let's take it easy. I'll dig into the pcf8563 code now.
>
> BTW, there were patches posted recently by Jon Smirl to convert that
> driver to new-style, and to change the i2c subsystem to have the OF
> matches in the driver itself.
That looks promising. I really didn't expect to find rtc driver names
in fsl_soc.c...
Regards,
--
Clemens Koller
__________________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Straße 45/1
Linhof Werksgelände
D-81379 München
Tel.089-741518-50
Fax 089-741518-19
http://www.anagramm-technology.com
^ permalink raw reply
* RE: Maximum ioremap size for ppc arch?
From: michael.firth @ 2007-12-05 9:50 UTC (permalink / raw)
To: mporter; +Cc: linuxppc-embedded
In-Reply-To: <20071203153009.GA30746@gate.crashing.org>
> -----Original Message-----
> From: Matt Porter [mailto:mporter@kernel.crashing.org]=20
> Sent: 03 December 2007 15:30
> To: Firth,MJC,Michael,DMM R
> Cc: linuxppc-embedded@ozlabs.org
> Subject: Re: Maximum ioremap size for ppc arch?
>=20
> On Mon, Dec 03, 2007 at 09:22:06AM -0000, michael.firth@bt.com wrote:
> > I'm trying to get am MPC834x system running that has=20
> 256MBytes of NOR=20
> > flash connected.
> >=20
> > The physmap flash driver is failing to ioremap() that=20
> amount of space,=20
> > while on a similar system with 128Mbytes of flash, there are no=20
> > problems.
> >=20
> > Is this a known limitation of ioremap() on the ppc architecture, or=20
> > specifically the MPC834x family, and is there any=20
> (hopefully easy) way=20
> > to increase this limit?
>=20
> The answer is "it depends". It depends on the amount of=20
> system memory you have. By default, your system memory is=20
> mapped at 0xc0000000, leaving not enough space for vmalloc=20
> allocations to grab 256MB for the ioremap (and avoid the=20
> fixed virtual mapping in the high virtual address area).
>=20
> See the "Advanced setup" menu. Normally, you can set "Set=20
> custom kernel base address" to 0xa0000000 safely. That will=20
> give you an additional 256MB of vmalloc space. On=20
> arch/powerpc, you'll also have to set "Size of user task=20
> space" to 0x80000000 or 0xa0000000.
>=20
> -Matt
>=20
I've solved my problem for now, but I'm not sure I'm that happy that
it's a scalable solution.
I tried moving the kernel base address to 0x80000000, but the system
became very unstable - in particular, though it detected the flash
partitions, as soon as I tried to write to them the system spontaneously
rebooted - not even a kernel panic, just a straight reboot.
As I'm using arch/ppc, it seems that the default user task space is
0x80000000 which shouldn't have conflicted with this.
It seemed that the bottom of the vmalloc space is defined as 'start of
kernel + amount of physical RAM', which in the case of our board becomes
'0xc0000000 + 0x10000000', as there is 256MB of RAM present. The top of
vmalloc space was being limited by the CPU registers, mapped by IMMRBAR.
This was configured to 0xe0000000, which left only 256MB of vmalloc
space.
I've got things working by moving IMMRBAR up to 0xeff00000, which gives
nearly 256MB more vmalloc space.
My main queries are:
1) Why did changing the kernel base address to 0x80000000 make the
system unstable? Would 0xa0000000 as suggested not have caused this
problem?
2) Currently IMMRBAR has the same physical and virtual address. Does
this need to be the case? If this is a restriction, it seems to mean
that the top 256MB of the virtual address space becomes unusable.
3) Why the kernel is designed to run at 0xc0000000? This seems to leave
only 1GB of addressing space for all the physically addressable memory
(RAM + ioremapped + registers), while reserving 3GB of space for user
processes. The 3GB is presumably mostly unusable on a system without a
large amount of swap, as the 1GB limit on memory will prevent much more
than that being available for user space.
Thanks for the assistance so far, the pointer to the definition of
VMALLOC_START and VMALLOC_END gave me the hook in I needed to work out
where the limitation was coming from. I would suggest that its also
worth changing at the error message that's generated when the vmalloc
space is exhausted:
"allocation failed: out of vmalloc space - use vmalloc=3D<size> to
increase size."
>From my understanding of the code so far, it seems that the 'vmalloc'
command line option is only available on the x86 architecture.
What is the process for getting a concensus on this, and getting the
message changed?
Thanks again
Michael
^ permalink raw reply
* drivers/net/iseries_veth.c dubious sysfs usage
From: Greg KH @ 2007-12-05 9:30 UTC (permalink / raw)
To: Kyle A. Lucke, David Gibson; +Cc: linuxppc-dev, paulus, linux-kernel
In doing a massive kobject cleanup of the kernel tree, I ran across the
iseries_veth.c driver.
It looks like the driver is creating a number of subdirectories under
the driver sysfs directory. This is odd and probably wrong. You want
these virtual connections to show up in the main sysfs device tree, not
under the driver directory.
I'll be glad to totally guess and try to move it around in the sysfs
tree, but odds are I'll get it all wrong as I can't really test this
out :)
Any hints on what this driver is trying to do in this sysfs directories?
thanks,
greg k-h
^ permalink raw reply
* Regarding MPC8641D
From: sivaji @ 2007-12-05 7:51 UTC (permalink / raw)
To: linuxppc-dev
Hai,
We have designed a MPC8641D based AMC card. We are using the
kernel (2.6.23-rc4) and uboot (1.2.0). When we disable the core1 Low Memory
offset mode the kernel was up and when we enable this core1 Low Memory
offset mode kernel was not up, It was hang after MPIC initialization.
Kerenl dump :
# Booting image at 00200000 ...
Image Name: Linux-2.6.23-rc4-g5326152f-dirty
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 4544816 Bytes = 4.3 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
Booting using flat device tree at 0x700000
data:0
Probing machine type ...
MPC86xx HPCN ...start c05d1e10 end c05d1ee0 <6>Using MPC86xx HPCN machine
description
Total memory = 600MB; using 2048kB for hash table (at cfe00000)
Linux version 2.6.23-rc4-g5326152f-dirty (root@sivaji) (gcc version 4.0.2
20060628 (Wasabi)) #45 SMP Wed Dec 5 12:01:58 IST 2007
console [udbg0] enabled
setup_arch: bootmem
mpc86xx_hpcn_setup_arch()
Found FSL PCI host bridge at 0x00000000f8008000.Firmware bus number: 0->254
MPC86xx HPCN board from Freescale Semiconductor
arch: exit
Zone PFN ranges:
DMA 0 -> 153600
Normal 153600 -> 153600
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
0: 0 -> 153600
Built 1 zonelists in Zone order. Total pages: 152400
Kernel command line: root=/dev/ram console=ttyS0,115200 mem=600M
mpic: Setting up MPIC " MPIC " version 1.2 at f8040000, max 2 CPUs
mpic: ISU size: 88, shift: 7, mask: 7f
mpic: Initializing for 88 sources
PID hash table entries: 4096 (order: 12, 16384 bytes)
Console: colour dummy device 80x25
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 600064k/614400k available (5832k kernel code, 14096k reserved, 116k
data, 233k bss, 3244k init)
SLUB: Genslabs=22, HWalign=32, Order=0-1, MinObjects=4, CPUs=2, Nodes=1
Security Framework v1.0.0 initialized
SELinux: Initializing.
selinux_register_security: Registering secondary module capability
Capability LSM initialized as secondary
Mount-cache hash table entries: 512
mpic: requesting IPIs ...
After this the kernel was hang, i want to know why
kernel was hang when we enalbe Low memory Offset mode. Please help me to fix
this issue.
Thanks and Regards
Sivaji
--
View this message in context: http://www.nabble.com/Regarding-MPC8641D-tf4948004.html#a14166848
Sent from the linuxppc-dev mailing list archive at Nabble.com.
^ permalink raw reply
* [PATCH 7/7] Remove bogus comment in dma_direct_alloc_coherent()
From: Michael Ellerman @ 2007-12-05 7:21 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <ac4252cfbaa0c1a3534443007417dfc43b597eb5.1196839256.git.michael@ellerman.id.au>
Since commit c80d9133e99de1af607314107910a2a1645efb17 (Make direct DMA use
node local allocations) went in this comment makes no sense.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/kernel/dma_64.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/dma_64.c b/arch/powerpc/kernel/dma_64.c
index 26c0d8c..1ef919d 100644
--- a/arch/powerpc/kernel/dma_64.c
+++ b/arch/powerpc/kernel/dma_64.c
@@ -137,7 +137,6 @@ static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
void *ret;
int node = dev->archdata.numa_node;
- /* TODO: Maybe use the numa node here too ? */
page = alloc_pages_node(node, flag, get_order(size));
if (page == NULL)
return NULL;
--
1.5.3.7.1.g4e596e
^ permalink raw reply related
* [PATCH 6/7] Remove the global dma_direct_offset
From: Michael Ellerman @ 2007-12-05 7:21 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <ac4252cfbaa0c1a3534443007417dfc43b597eb5.1196839256.git.michael@ellerman.id.au>
We no longer need the global dma_direct_offset, update the comment to
reflect the new reality.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/kernel/dma_64.c | 7 ++++---
include/asm-powerpc/dma-mapping.h | 2 --
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/dma_64.c b/arch/powerpc/kernel/dma_64.c
index 19d5fb0..26c0d8c 100644
--- a/arch/powerpc/kernel/dma_64.c
+++ b/arch/powerpc/kernel/dma_64.c
@@ -112,10 +112,11 @@ EXPORT_SYMBOL(dma_iommu_ops);
/*
* Generic direct DMA implementation
*
- * This implementation supports a global offset that can be applied if
- * the address at which memory is visible to devices is not 0.
+ * This implementation supports a per-device offset that can be applied if
+ * the address at which memory is visible to devices is not 0. Platform code
+ * can point archdata.dma_data at an unsigned long holding the offset. By
+ * default no offset is used.
*/
-unsigned long dma_direct_offset;
static unsigned long get_dma_direct_offset(struct device *dev)
{
diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index ff52013..d9b429a 100644
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -186,8 +186,6 @@ static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
extern struct dma_mapping_ops dma_iommu_ops;
extern struct dma_mapping_ops dma_direct_ops;
-extern unsigned long dma_direct_offset;
-
#else /* CONFIG_PPC64 */
#define dma_supported(dev, mask) (1)
--
1.5.3.7.1.g4e596e
^ permalink raw reply related
* [PATCH 5/7] Have celleb use its own dma_direct_offset variable
From: Michael Ellerman @ 2007-12-05 7:21 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <ac4252cfbaa0c1a3534443007417dfc43b597eb5.1196839256.git.michael@ellerman.id.au>
Rather than using the global variable, have celleb use its own variable to
store the direct DMA offset.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/platforms/celleb/iommu.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/celleb/iommu.c b/arch/powerpc/platforms/celleb/iommu.c
index 04d5678..85af76f 100644
--- a/arch/powerpc/platforms/celleb/iommu.c
+++ b/arch/powerpc/platforms/celleb/iommu.c
@@ -51,6 +51,8 @@ static int __init find_dma_window(u64 *io_space_id, u64 *ioid,
return 0;
}
+static unsigned long celleb_dma_direct_offset;
+
static void __init celleb_init_direct_mapping(void)
{
u64 lpar_addr, io_addr;
@@ -68,13 +70,13 @@ static void __init celleb_init_direct_mapping(void)
ioid, DMA_FLAGS);
}
- dma_direct_offset = dma_base;
+ celleb_dma_direct_offset = dma_base;
}
static void celleb_dma_dev_setup(struct device *dev)
{
dev->archdata.dma_ops = get_pci_dma_ops();
- dev->archdata.dma_data = &dma_direct_offset;
+ dev->archdata.dma_data = &celleb_dma_direct_offset;
}
static void celleb_pci_dma_dev_setup(struct pci_dev *pdev)
--
1.5.3.7.1.g4e596e
^ permalink raw reply related
* [PATCH 4/7] Have cell use its own dma_direct_offset variable
From: Michael Ellerman @ 2007-12-05 7:21 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <ac4252cfbaa0c1a3534443007417dfc43b597eb5.1196839256.git.michael@ellerman.id.au>
Rather than using the global variable, have cell use its own variable to
store the direct DMA offset.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/platforms/cell/iommu.c | 10 ++++++----
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index 2edb1ad..d2f9242 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -489,6 +489,8 @@ static struct cbe_iommu *cell_iommu_for_node(int nid)
return NULL;
}
+static unsigned long cell_dma_direct_offset;
+
static void cell_dma_dev_setup(struct device *dev)
{
struct iommu_window *window;
@@ -496,7 +498,7 @@ static void cell_dma_dev_setup(struct device *dev)
struct dev_archdata *archdata = &dev->archdata;
if (get_pci_dma_ops() == &dma_direct_ops) {
- archdata->dma_data = &dma_direct_offset;
+ archdata->dma_data = &cell_dma_direct_offset;
return;
}
@@ -654,7 +656,7 @@ static int __init cell_iommu_init_disabled(void)
/* If we have no Axon, we set up the spider DMA magic offset */
if (of_find_node_by_name(NULL, "axon") == NULL)
- dma_direct_offset = SPIDER_DMA_OFFSET;
+ cell_dma_direct_offset = SPIDER_DMA_OFFSET;
/* Now we need to check to see where the memory is mapped
* in PCI space. We assume that all busses use the same dma
@@ -688,10 +690,10 @@ static int __init cell_iommu_init_disabled(void)
return -ENODEV;
}
- dma_direct_offset += base;
+ cell_dma_direct_offset += base;
printk("iommu: disabled, direct DMA offset is 0x%lx\n",
- dma_direct_offset);
+ cell_dma_direct_offset);
return 0;
}
--
1.5.3.7.1.g4e596e
^ permalink raw reply related
* [PATCH 3/7] Use archdata.dma_data in dma_direct_ops
From: Michael Ellerman @ 2007-12-05 7:21 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <ac4252cfbaa0c1a3534443007417dfc43b597eb5.1196839256.git.michael@ellerman.id.au>
Now that all platforms using dma_direct_offset setup the archdata.dma_data
correctly, we can change the dma_direct_ops to retrieve the offset from
the dma_data, rather than directly from the global.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/kernel/dma_64.c | 18 +++++++++++++++---
1 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/dma_64.c b/arch/powerpc/kernel/dma_64.c
index 14206e3..19d5fb0 100644
--- a/arch/powerpc/kernel/dma_64.c
+++ b/arch/powerpc/kernel/dma_64.c
@@ -117,6 +117,18 @@ EXPORT_SYMBOL(dma_iommu_ops);
*/
unsigned long dma_direct_offset;
+static unsigned long get_dma_direct_offset(struct device *dev)
+{
+ unsigned long *offset;
+
+ offset = dev->archdata.dma_data;
+
+ if (offset)
+ return *offset;
+
+ return 0;
+}
+
static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag)
{
@@ -130,7 +142,7 @@ static void *dma_direct_alloc_coherent(struct device *dev, size_t size,
return NULL;
ret = page_address(page);
memset(ret, 0, size);
- *dma_handle = virt_to_abs(ret) | dma_direct_offset;
+ *dma_handle = virt_to_abs(ret) | get_dma_direct_offset(dev);
return ret;
}
@@ -145,7 +157,7 @@ static dma_addr_t dma_direct_map_single(struct device *dev, void *ptr,
size_t size,
enum dma_data_direction direction)
{
- return virt_to_abs(ptr) | dma_direct_offset;
+ return virt_to_abs(ptr) | get_dma_direct_offset(dev);
}
static void dma_direct_unmap_single(struct device *dev, dma_addr_t dma_addr,
@@ -161,7 +173,7 @@ static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
int i;
for_each_sg(sgl, sg, nents, i) {
- sg->dma_address = sg_phys(sg) | dma_direct_offset;
+ sg->dma_address = sg_phys(sg) | get_dma_direct_offset(dev);
sg->dma_length = sg->length;
}
--
1.5.3.7.1.g4e596e
^ permalink raw reply related
* [PATCH 2/7] Add celleb_dma_dev_setup()
From: Michael Ellerman @ 2007-12-05 7:20 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <ac4252cfbaa0c1a3534443007417dfc43b597eb5.1196839256.git.michael@ellerman.id.au>
Celleb always uses dma_direct_ops, and sets dma_direct_offset, so it too
should set dma_data to dma_direct_offset.
Currently there's no pci_dma_dev_setup() routine for Celleb so add one.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/platforms/celleb/iommu.c | 14 +++++++++++++-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/celleb/iommu.c b/arch/powerpc/platforms/celleb/iommu.c
index 755d869..04d5678 100644
--- a/arch/powerpc/platforms/celleb/iommu.c
+++ b/arch/powerpc/platforms/celleb/iommu.c
@@ -71,6 +71,17 @@ static void __init celleb_init_direct_mapping(void)
dma_direct_offset = dma_base;
}
+static void celleb_dma_dev_setup(struct device *dev)
+{
+ dev->archdata.dma_ops = get_pci_dma_ops();
+ dev->archdata.dma_data = &dma_direct_offset;
+}
+
+static void celleb_pci_dma_dev_setup(struct pci_dev *pdev)
+{
+ celleb_dma_dev_setup(&pdev->dev);
+}
+
static int celleb_of_bus_notify(struct notifier_block *nb,
unsigned long action, void *data)
{
@@ -80,7 +91,7 @@ static int celleb_of_bus_notify(struct notifier_block *nb,
if (action != BUS_NOTIFY_ADD_DEVICE)
return 0;
- dev->archdata.dma_ops = get_pci_dma_ops();
+ celleb_dma_dev_setup(dev);
return 0;
}
@@ -96,6 +107,7 @@ static int __init celleb_init_iommu(void)
celleb_init_direct_mapping();
set_pci_dma_ops(&dma_direct_ops);
+ ppc_md.pci_dma_dev_setup = celleb_pci_dma_dev_setup;
bus_register_notifier(&of_platform_bus_type, &celleb_of_bus_notifier);
return 0;
--
1.5.3.7.1.g4e596e
^ permalink raw reply related
* [PATCH 1/7] Set archdata.dma_data for direct DMA in cell_dma_dev_setup()
From: Michael Ellerman @ 2007-12-05 7:20 UTC (permalink / raw)
To: linuxppc-dev
Store a pointer to the direct_dma_offset in each device's dma_data
in the case where we're using the direct DMA ops.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/platforms/cell/iommu.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index faabc3f..2edb1ad 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -495,9 +495,10 @@ static void cell_dma_dev_setup(struct device *dev)
struct cbe_iommu *iommu;
struct dev_archdata *archdata = &dev->archdata;
- /* If we run without iommu, no need to do anything */
- if (get_pci_dma_ops() == &dma_direct_ops)
+ if (get_pci_dma_ops() == &dma_direct_ops) {
+ archdata->dma_data = &dma_direct_offset;
return;
+ }
/* Current implementation uses the first window available in that
* node's iommu. We -might- do something smarter later though it may
--
1.5.3.7.1.g4e596e
^ permalink raw reply related
* PS3: Update ps3_defconfig
From: Geoff Levand @ 2007-12-05 7:13 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev@ozlabs.org
Update ps3_defconfig.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
arch/powerpc/configs/ps3_defconfig | 177 ++++++++++++++++++-------------------
1 file changed, 89 insertions(+), 88 deletions(-)
--- a/arch/powerpc/configs/ps3_defconfig
+++ b/arch/powerpc/configs/ps3_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23-rc2
-# Tue Aug 7 19:17:26 2007
+# Linux kernel version: 2.6.24-rc4
+# Tue Dec 4 22:49:57 2007
#
CONFIG_PPC64=y
@@ -11,6 +11,7 @@ CONFIG_PPC64=y
# CONFIG_POWER4_ONLY is not set
CONFIG_POWER3=y
CONFIG_POWER4=y
+CONFIG_TUNE_CELL=y
CONFIG_PPC_FPU=y
CONFIG_ALTIVEC=y
CONFIG_PPC_STD_MMU=y
@@ -19,8 +20,13 @@ CONFIG_VIRT_CPU_ACCOUNTING=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_64BIT=y
+CONFIG_WORD_SIZE=64
CONFIG_PPC_MERGE=y
CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_IRQ_PER_CPU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
@@ -59,14 +65,18 @@ CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_CPUSETS is not set
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
@@ -87,13 +97,11 @@ CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
@@ -108,6 +116,7 @@ CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
# CONFIG_BLK_DEV_IO_TRACE is not set
CONFIG_BLK_DEV_BSG=y
+CONFIG_BLOCK_COMPAT=y
#
# IO Schedulers
@@ -126,7 +135,6 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# Platform support
#
CONFIG_PPC_MULTIPLATFORM=y
-# CONFIG_EMBEDDED6xx is not set
# CONFIG_PPC_82xx is not set
# CONFIG_PPC_83xx is not set
# CONFIG_PPC_86xx is not set
@@ -176,10 +184,15 @@ CONFIG_SPU_BASE=y
# CONFIG_GENERIC_IOMAP is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_CPM2 is not set
+# CONFIG_FSL_ULI1575 is not set
#
# Kernel options
#
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
@@ -211,6 +224,8 @@ CONFIG_SPARSEMEM=y
CONFIG_HAVE_MEMORY_PRESENT=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSEMEM_VMEMMAP=y
CONFIG_MEMORY_HOTPLUG=y
CONFIG_MEMORY_HOTPLUG_SPARSE=y
CONFIG_SPLIT_PTLOCK_CPUS=4
@@ -237,10 +252,6 @@ CONFIG_GENERIC_ISA_DMA=y
# CONFIG_PCI_DOMAINS is not set
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
# CONFIG_PCCARD is not set
CONFIG_KERNEL_START=0xc000000000000000
@@ -280,6 +291,7 @@ CONFIG_INET_TUNNEL=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
@@ -318,10 +330,6 @@ CONFIG_IPV6_SIT=y
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
#
@@ -330,26 +338,7 @@ CONFIG_IPV6_SIT=y
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-# CONFIG_BT_BNEP is not set
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIUSB=m
-CONFIG_BT_HCIUSB_SCO=y
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
@@ -358,7 +347,13 @@ CONFIG_BT_HCIUART_BCSP=y
# CONFIG_CFG80211 is not set
CONFIG_WIRELESS_EXT=y
# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
@@ -369,9 +364,10 @@ CONFIG_WIRELESS_EXT=y
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=m
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
@@ -434,6 +430,7 @@ CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
# CONFIG_SCSI_LOWLEVEL is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
@@ -445,8 +442,15 @@ CONFIG_NETDEVICES=y
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-# CONFIG_NET_ETHERNET is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
CONFIG_MII=m
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
CONFIG_GELIC_NET=y
# CONFIG_NETDEV_10000 is not set
@@ -455,7 +459,12 @@ CONFIG_GELIC_NET=y
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_LIBERTAS is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
#
# USB Network Adapters
@@ -464,8 +473,8 @@ CONFIG_GELIC_NET=y
# CONFIG_USB_KAWETH is not set
CONFIG_USB_PEGASUS=m
# CONFIG_USB_RTL8150 is not set
-CONFIG_USB_USBNET_MII=m
CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
# CONFIG_USB_NET_CDCETHER is not set
# CONFIG_USB_NET_DM9601 is not set
# CONFIG_USB_NET_GL620A is not set
@@ -499,9 +508,8 @@ CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-# CONFIG_INPUT_EVDEV is not set
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_EVBUG is not set
#
@@ -561,7 +569,6 @@ CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
CONFIG_GEN_RTC=y
# CONFIG_GEN_RTC_X is not set
@@ -579,6 +586,13 @@ CONFIG_GEN_RTC=y
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
#
# Multifunction device drivers
@@ -595,12 +609,6 @@ CONFIG_GEN_RTC=y
#
# Graphics support
#
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
CONFIG_FB=y
@@ -609,6 +617,7 @@ CONFIG_FB=y
# CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_IMAGEBLIT=y
@@ -628,8 +637,14 @@ CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_IBM_GXT4500 is not set
CONFIG_FB_PS3=y
-CONFIG_FB_PS3_DEFAULT_SIZE_M=18
+CONFIG_FB_PS3_DEFAULT_SIZE_M=9
# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
@@ -713,6 +728,7 @@ CONFIG_SND_PS3_DEFAULT_START_DELAY=2000
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
#
# USB Input Devices
@@ -776,12 +792,14 @@ CONFIG_USB_STORAGE=m
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_LIBUSUAL is not set
@@ -839,19 +857,6 @@ CONFIG_USB_MON=y
# CONFIG_RTC_CLASS is not set
#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
-
-#
# Userspace I/O
#
# CONFIG_UIO is not set
@@ -868,7 +873,6 @@ CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4DEV_FS is not set
CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
@@ -881,6 +885,8 @@ CONFIG_FS_MBCACHE=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
@@ -919,7 +925,6 @@ CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLBFS is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
@@ -938,10 +943,7 @@ CONFIG_RAMFS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
@@ -973,10 +975,6 @@ CONFIG_CIFS=m
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
@@ -1017,10 +1015,6 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
# CONFIG_DLM is not set
# CONFIG_UCC_SLOW is not set
@@ -1038,17 +1032,16 @@ CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
-
-#
-# Instrumentation Support
-#
+CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
# CONFIG_KPROBES is not set
+# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_UNUSED_SYMBOLS is not set
@@ -1060,7 +1053,7 @@ CONFIG_DETECT_SOFTLOCKUP=y
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
CONFIG_DEBUG_SPINLOCK=y
@@ -1072,9 +1065,12 @@ CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
CONFIG_DEBUG_LIST=y
+# CONFIG_DEBUG_SG is not set
CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
CONFIG_DEBUG_STACKOVERFLOW=y
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_PAGEALLOC is not set
@@ -1088,6 +1084,7 @@ CONFIG_IRQSTACKS=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y
@@ -1107,22 +1104,26 @@ CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
+CONFIG_CRYPTO_AES=m
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
+CONFIG_CRYPTO_MICHAEL_MIC=m
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
CONFIG_CRYPTO_HW=y
+# CONFIG_PPC_CLOCK is not set
^ permalink raw reply
* [PATCH] pci: Fix bus resource assignment on 32 bits with 64b resources
From: Benjamin Herrenschmidt @ 2007-12-05 6:40 UTC (permalink / raw)
To: Greg Kroah-Hartman; +Cc: linuxppc-dev, linux-pci, linux-kernel
The current pci_assign_unassigned_resources() code doesn't work properly
on 32 bits platforms with 64 bits resources. The main reason is the use
of unsigned long in various places instead of resource_size_t.
This fixes it, along with some tricks to avoid casting to 64 bits on
platforms that don't need it in every printk around.
This is a pre-requisite for making powerpc use the generic code instead of
its own half-useful implementation.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
This version fixes some stupid warnings when using 32 bits resources
drivers/pci/pci.h | 11 +++++++++++
drivers/pci/setup-bus.c | 32 +++++++++++++++++---------------
drivers/pci/setup-res.c | 5 ++---
include/linux/pci.h | 4 ++--
4 files changed, 32 insertions(+), 20 deletions(-)
Index: linux-work/drivers/pci/pci.h
===================================================================
--- linux-work.orig/drivers/pci/pci.h 2007-12-05 11:55:49.000000000 +1100
+++ linux-work/drivers/pci/pci.h 2007-12-05 13:37:45.000000000 +1100
@@ -91,3 +91,14 @@ pci_match_one_device(const struct pci_de
}
struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
+
+#ifdef CONFIG_RESOURCES_64BIT
+#define RESOURCE_ORDER(order) (1ULL << (order))
+#define RES_PR "%016llx"
+#else
+#define RESOURCE_ORDER(order) (1UL << (order))
+#define RES_PR "%08x"
+#endif
+
+#define RANGE_PR RES_PR "-" RES_PR
+
Index: linux-work/drivers/pci/setup-bus.c
===================================================================
--- linux-work.orig/drivers/pci/setup-bus.c 2007-12-05 11:55:49.000000000 +1100
+++ linux-work/drivers/pci/setup-bus.c 2007-12-05 12:04:35.000000000 +1100
@@ -26,6 +26,7 @@
#include <linux/cache.h>
#include <linux/slab.h>
+#include "pci.h"
#define DEBUG_CONFIG 1
#if DEBUG_CONFIG
@@ -89,8 +90,9 @@ void pci_setup_cardbus(struct pci_bus *b
* The IO resource is allocated a range twice as large as it
* would normally need. This allows us to set both IO regs.
*/
- printk(" IO window: %08lx-%08lx\n",
- region.start, region.end);
+ printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
+ (unsigned long)region.start,
+ (unsigned long)region.end);
pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
region.start);
pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
@@ -99,7 +101,7 @@ void pci_setup_cardbus(struct pci_bus *b
pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
if (bus->resource[1]->flags & IORESOURCE_IO) {
- printk(" IO window: %08lx-%08lx\n",
+ printk(KERN_INFO " IO window: "RANGE_PR"\n",
region.start, region.end);
pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
region.start);
@@ -109,7 +111,7 @@ void pci_setup_cardbus(struct pci_bus *b
pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
if (bus->resource[2]->flags & IORESOURCE_MEM) {
- printk(" PREFETCH window: %08lx-%08lx\n",
+ printk(KERN_INFO " PREFETCH window: "RANGE_PR"\n",
region.start, region.end);
pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
region.start);
@@ -119,7 +121,7 @@ void pci_setup_cardbus(struct pci_bus *b
pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
if (bus->resource[3]->flags & IORESOURCE_MEM) {
- printk(" MEM window: %08lx-%08lx\n",
+ printk(KERN_INFO " MEM window: "RANGE_PR"\n",
region.start, region.end);
pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
region.start);
@@ -159,7 +161,8 @@ pci_setup_bridge(struct pci_bus *bus)
/* Set up upper 16 bits of I/O base/limit. */
io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
DBG(KERN_INFO " IO window: %04lx-%04lx\n",
- region.start, region.end);
+ (unsigned long)region.start,
+ (unsigned long)region.end);
}
else {
/* Clear upper 16 bits of I/O base/limit. */
@@ -180,7 +183,7 @@ pci_setup_bridge(struct pci_bus *bus)
if (bus->resource[1]->flags & IORESOURCE_MEM) {
l = (region.start >> 16) & 0xfff0;
l |= region.end & 0xfff00000;
- DBG(KERN_INFO " MEM window: %08lx-%08lx\n",
+ DBG(KERN_INFO " MEM window: "RANGE_PR"\n",
region.start, region.end);
}
else {
@@ -199,7 +202,7 @@ pci_setup_bridge(struct pci_bus *bus)
if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
l = (region.start >> 16) & 0xfff0;
l |= region.end & 0xfff00000;
- DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n",
+ DBG(KERN_INFO " PREFETCH window: "RANGE_PR"\n",
region.start, region.end);
}
else {
@@ -323,8 +326,8 @@ static void pbus_size_io(struct pci_bus
static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
{
struct pci_dev *dev;
- unsigned long min_align, align, size;
- unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */
+ resource_size_t min_align, align, size;
+ resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
int order, max_order;
struct resource *b_res = find_free_bus_resource(bus, type);
@@ -340,7 +343,7 @@ static int pbus_size_mem(struct pci_bus
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
struct resource *r = &dev->resource[i];
- unsigned long r_size;
+ resource_size_t r_size;
if (r->parent || (r->flags & mask) != type)
continue;
@@ -350,10 +353,9 @@ static int pbus_size_mem(struct pci_bus
order = __ffs(align) - 20;
if (order > 11) {
printk(KERN_WARNING "PCI: region %s/%d "
- "too large: %llx-%llx\n",
+ "too large: " RANGE_PR "\n",
pci_name(dev), i,
- (unsigned long long)r->start,
- (unsigned long long)r->end);
+ r->start, r->end);
r->flags = 0;
continue;
}
@@ -372,7 +374,7 @@ static int pbus_size_mem(struct pci_bus
align = 0;
min_align = 0;
for (order = 0; order <= max_order; order++) {
- unsigned long align1 = 1UL << (order + 20);
+ resource_size_t align1 = RESOURCE_ORDER(order + 20);
if (!align)
min_align = align1;
Index: linux-work/drivers/pci/setup-res.c
===================================================================
--- linux-work.orig/drivers/pci/setup-res.c 2007-12-05 11:55:49.000000000 +1100
+++ linux-work/drivers/pci/setup-res.c 2007-12-05 12:04:35.000000000 +1100
@@ -51,9 +51,8 @@ pci_update_resource(struct pci_dev *dev,
pcibios_resource_to_bus(dev, ®ion, res);
- pr_debug(" got res [%llx:%llx] bus [%lx:%lx] flags %lx for "
- "BAR %d of %s\n", (unsigned long long)res->start,
- (unsigned long long)res->end,
+ pr_debug(" got res ["RANGE_PR"] bus ["RANGE_PR"] flags %lx for "
+ "BAR %d of %s\n", res->start, res->end,
region.start, region.end, res->flags, resno, pci_name(dev));
new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
Index: linux-work/include/linux/pci.h
===================================================================
--- linux-work.orig/include/linux/pci.h 2007-12-05 11:55:49.000000000 +1100
+++ linux-work/include/linux/pci.h 2007-12-05 12:04:35.000000000 +1100
@@ -314,8 +314,8 @@ struct pci_raw_ops {
extern struct pci_raw_ops *raw_pci_ops;
struct pci_bus_region {
- unsigned long start;
- unsigned long end;
+ resource_size_t start;
+ resource_size_t end;
};
struct pci_dynids {
^ permalink raw reply
* Re: problem in creation of .ko file while compiling the kernel
From: Misbah khan @ 2007-12-05 6:12 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20071205060957.GA17391@lixom.net>
I need to know what could be the reason that .ko files are not been generated
while selecting as Module in menuconfig
----misbah
Olof Johansson-2 wrote:
>
> On Tue, Dec 04, 2007 at 08:46:21PM -0800, Misbah khan wrote:
>
>> I need to select USB support in the kernel for PPC8272 board. Source code
>> is
>> already present and montavista provides the support for it .
>
> Sounds like a question you should ask montavista support then?
>
>
> -Olof
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
--
View this message in context: http://www.nabble.com/problem-in-creation-of-.ko-file-while-compiling-the-kernel-tf4947452.html#a14165890
Sent from the linuxppc-embedded mailing list archive at Nabble.com.
^ permalink raw reply
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