* Re: [PATCH -mm 18/43] powerpc compat_binfmt_elf
From: Christoph Hellwig @ 2007-12-21 7:12 UTC (permalink / raw)
To: Roland McGrath
Cc: linux-arch, linux-kernel, linuxppc-dev, Paul Mackerras,
Andrew Morton, Linus Torvalds
In-Reply-To: <20071220115816.504CC26F98E@magilla.localdomain>
On Thu, Dec 20, 2007 at 03:58:16AM -0800, Roland McGrath wrote:
> +obj-$(CONFIG_PPC64) += ../../../fs/compat_binfmt_elf.o
Building files from another directory is nasty. Please add a
CONFIG_BINFMT_COMPAT_ELF so we can simply build it in fs/
^ permalink raw reply
* [PATCH 2/3] [POWERPC] Makalu dts
From: Stefan Roese @ 2007-12-21 7:10 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/powerpc/boot/dts/makalu.dts | 347 ++++++++++++++++++++++++++++++++++++++
1 files changed, 347 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/makalu.dts
diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts
new file mode 100644
index 0000000..bdd70e4
--- /dev/null
+++ b/arch/powerpc/boot/dts/makalu.dts
@@ -0,0 +1,347 @@
+/*
+ * Device Tree Source for AMCC Makalu (405EX)
+ *
+ * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "amcc,makalu";
+ compatible = "amcc,makalu";
+ dcr-parent = <&/cpus/cpu@0>;
+
+ aliases {
+ ethernet0 = &EMAC0;
+ ethernet1 = &EMAC1;
+ serial0 = &UART0;
+ serial1 = &UART1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,405EX";
+ reg = <0>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <20>;
+ d-cache-line-size = <20>;
+ i-cache-size = <4000>; /* 16 kB */
+ d-cache-size = <4000>; /* 16 kB */
+ dcr-controller;
+ dcr-access-method = "native";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller {
+ compatible = "ibm,uic-405ex", "ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0c0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "ibm,uic-405ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0d0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1e 4 1f 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "ibm,uic-405ex","ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0e0 009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <1c 4 1d 4>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ plb {
+ compatible = "ibm,plb-405ex", "ibm,plb4";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: memory-controller {
+ compatible = "ibm,sdram-405ex";
+ dcr-reg = <010 2>;
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
+ dcr-reg = <180 62>;
+ num-tx-chans = <2>;
+ num-rx-chans = <2>;
+ interrupt-parent = <&MAL0>;
+ interrupts = <0 1 2 3 4>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
+ /*RXEOB*/ 1 &UIC0 b 4
+ /*SERR*/ 2 &UIC1 0 4
+ /*TXDE*/ 3 &UIC1 1 4
+ /*RXDE*/ 4 &UIC1 2 4>;
+ interrupt-map-mask = <ffffffff>;
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-405ex", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <80000000 80000000 10000000
+ ef600000 ef600000 a00000
+ f0000000 f0000000 10000000>;
+ dcr-reg = <0a0 5>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-405ex", "ibm,ebc";
+ dcr-reg = <012 2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ /* ranges property is supplied by U-Boot */
+ interrupts = <5 1>;
+ interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ compatible = "amd,s29gl512n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0 000000 4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "kernel";
+ reg = <0 200000>;
+ };
+ partition@200000 {
+ label = "root";
+ reg = <200000 200000>;
+ };
+ partition@400000 {
+ label = "user";
+ reg = <400000 3b60000>;
+ };
+ partition@3f60000 {
+ label = "env";
+ reg = <3f60000 40000>;
+ };
+ partition@3fa0000 {
+ label = "u-boot";
+ reg = <3fa0000 60000>;
+ };
+ };
+ };
+
+ UART0: serial@ef600200 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600200 8>;
+ virtual-reg = <ef600200>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1a 4>;
+ };
+
+ UART1: serial@ef600300 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <ef600300 8>;
+ virtual-reg = <ef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ current-speed = <0>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <1 4>;
+ };
+
+ IIC0: i2c@ef600400 {
+ device_type = "i2c";
+ compatible = "ibm,iic-405ex", "ibm,iic";
+ reg = <ef600400 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <2 4>;
+ };
+
+ IIC1: i2c@ef600500 {
+ device_type = "i2c";
+ compatible = "ibm,iic-405ex", "ibm,iic";
+ reg = <ef600500 14>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <7 4>;
+ };
+
+
+ RGMII0: emac-rgmii@ef600b00 {
+ device_type = "rgmii-interface";
+ compatible = "ibm,rgmii-405ex", "ibm,rgmii";
+ reg = <ef600b00 104>;
+ has-mdio;
+ };
+
+ EMAC0: ethernet@ef600900 {
+ linux,network-index = <0>;
+ device_type = "network";
+ compatible = "ibm,emac-405ex", "ibm,emac4";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC0 18 4
+ /*Wake*/ 1 &UIC1 1d 4>;
+ reg = <ef600900 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <0000003f>; /* Start at 6 */
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ };
+
+ EMAC1: ethernet@ef600a00 {
+ linux,network-index = <1>;
+ device_type = "network";
+ compatible = "ibm,emac-405ex", "ibm,emac4";
+ interrupt-parent = <&EMAC1>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = </*Status*/ 0 &UIC0 19 4
+ /*Wake*/ 1 &UIC1 1f 4>;
+ reg = <ef600a00 70>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <1>;
+ mal-rx-channel = <1>;
+ cell-index = <1>;
+ max-frame-size = <5dc>;
+ rx-fifo-size = <1000>;
+ tx-fifo-size = <800>;
+ phy-mode = "rgmii";
+ phy-map = <00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <1>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ };
+ };
+
+ PCIE0: pciex@0a0000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
+ primary;
+ port = <0>; /* port number */
+ reg = <a0000000 20000000 /* Config space access */
+ ef000000 00001000>; /* Registers */
+ dcr-reg = <040 020>;
+ sdr-base = <400>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 90000000 0 08000000
+ 01000000 0 00000000 e0000000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 80000000>;
+
+ /* This drives busses 0x00 to 0x3f */
+ bus-range = <00 3f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 1 &UIC2 0 4 /* swizzled int A */
+ 0000 0 0 2 &UIC2 1 4 /* swizzled int B */
+ 0000 0 0 3 &UIC2 2 4 /* swizzled int C */
+ 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
+ };
+
+ PCIE1: pciex@0c0000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
+ primary;
+ port = <1>; /* port number */
+ reg = <c0000000 20000000 /* Config space access */
+ ef001000 00001000>; /* Registers */
+ dcr-reg = <060 020>;
+ sdr-base = <440>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <02000000 0 80000000 98000000 0 08000000
+ 01000000 0 00000000 e0010000 0 00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 80000000>;
+
+ /* This drives busses 0x40 to 0x7f */
+ bus-range = <40 7f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0000 0 0 7>;
+ interrupt-map = <
+ 0000 0 0 1 &UIC2 b 4 /* swizzled int A */
+ 0000 0 0 2 &UIC2 c 4 /* swizzled int B */
+ 0000 0 0 3 &UIC2 d 4 /* swizzled int C */
+ 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
+ };
+ };
+};
--
1.5.4.rc1
^ permalink raw reply related
* MPC83xx - 2.6.23, UCC_GETH and NFS Boot
From: Russell McGuire @ 2007-12-21 8:03 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <mailman.715.1198212922.17691.linuxppc-embedded@ozlabs.org>
All,
I am attempting to get a new board booted up using NFS root file system.
HW: Board based lightly on the MPC8360E_MDS
I have the kernel 2.6.23-dirty configured to use the Freescale QE driver.
I am using U-boot 1.3.0 and am able to use the Ethernet there, so I know it
is up.
I am using the following bootargs from U-boot.
bootargs=console=ttyS0,115200 root=/dev/nfs rw
nfsroot=192.168.5.205:/usr/local/eldk/ppc_6xx
ip=192.168.5.50:192.168.5.205:192.168.5.1::MIB305_50::off
I can see during initial kernel load up that it loads:
"ucc_geth: QE UCC Gigabit Ethernet Controller"
However, later IP-Config claims there is no valid Ethernet device
registered.
Is there something I have to do specify what type of PHY device I am using?
Perhaps a National DP8365 is not supported yet? Or perhaps the MDIO driver
in linux is not looking at the correct MDIO address?
In U-boot I am using PHY addr 0x01, could this present a problem?
-Russ
^ permalink raw reply
* Re: [PATCH -mm 18/43] powerpc compat_binfmt_elf
From: Roland McGrath @ 2007-12-21 8:56 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-arch, linux-kernel, linuxppc-dev, Paul Mackerras,
Andrew Morton, Linus Torvalds
In-Reply-To: <20071221071229.GC4345@infradead.org>
> On Thu, Dec 20, 2007 at 03:58:16AM -0800, Roland McGrath wrote:
> > +obj-$(CONFIG_PPC64) += ../../../fs/compat_binfmt_elf.o
>
> Building files from another directory is nasty. Please add a
> CONFIG_BINFMT_COMPAT_ELF so we can simply build it in fs/
If that's better, please post the precise Kconfig magic you have in mind to
have it set when it should be.
Thanks,
Roland
^ permalink raw reply
* [PATCH 2/3] (Resend part #1) Add the RapidIO support to powerpc architecture with memory mapping support.
From: Zhang Wei @ 2007-12-21 9:58 UTC (permalink / raw)
To: mporter, paulus, galak; +Cc: linuxppc-dev, linux-kernel, Zhang Wei
The patch adds the RapidIO support to powerpc with of-device support.
New Serial RapidIO of new Freescale processor, such as MPC8548, MPC8568,
is also added.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
arch/powerpc/Kconfig | 12 +
arch/powerpc/platforms/85xx/Kconfig | 1 +
arch/powerpc/platforms/86xx/Kconfig | 1 +
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_rio.c | 1130 ++++++++++++++++++++++++++---------
5 files changed, 861 insertions(+), 284 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 18f397c..ee27b77 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -523,6 +523,18 @@ source "drivers/pci/Kconfig"
source "drivers/pcmcia/Kconfig"
+config FSL_RAPIDIO
+ bool
+ default n
+
+config RAPIDIO
+ bool "RapidIO support" if FSL_RAPIDIO
+ help
+ If you say Y here, the kernel will include drivers and
+ infrastructure code to support RapidIO interconnect devices.
+
+source "drivers/rapidio/Kconfig"
+
source "drivers/pci/hotplug/Kconfig"
endmenu
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 7748a3a..09c522d 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -56,6 +56,7 @@ config MPC85xx
select PPC_UDBG_16550
select PPC_INDIRECT_PCI if PCI
select MPIC
+ select FSL_RAPIDIO
select FSL_PCI if PCI
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 21d1135..a6a6593 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -24,6 +24,7 @@ config MPC8641
select FSL_PCI if PCI
select PPC_UDBG_16550
select MPIC
+ select FSL_RAPIDIO
default y if MPC8641_HPCN
config MPC8610
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99a77d7..073d197 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o
+obj-$(CONFIG_FSL_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index af2425e..525066c 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1,5 +1,8 @@
/*
- * MPC85xx RapidIO support
+ * Freescale PowerPC RapidIO support
+ *
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Zhang Wei <wei.zhang@freescale.com>, Jun 2007
*
* Copyright 2005 MontaVista Software, Inc.
* Matt Porter <mporter@kernel.crashing.org>
@@ -8,6 +11,13 @@
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
+ *
+ * Changelog:
+ * Jun 2007 Zhang Wei <wei.zhang@freescale.com>
+ * - This file is moved from arch/ppc/ppc85xx_rio.c. And the OF-tree support
+ * is added. New silicons such as MPC8548, MPC8641 are all supported.
+ * Memory driver hardware operations are added.
+ *
*/
#include <linux/init.h>
@@ -17,14 +27,41 @@
#include <linux/interrupt.h>
#include <linux/rio.h>
#include <linux/rio_drv.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
#include <asm/io.h>
+#include <asm/prom.h>
+#include "fsl_soc.h"
+
+/* RapidIO definition irq, which read from OF-tree */
+#define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
+#define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
+#define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
+
+#define ERR(fmt, arg...) \
+ printk(KERN_ERR "RIO %s: " fmt, __FUNCTION__, ## arg)
+#define INFO(fmt...) printk(KERN_INFO "RIO: " fmt)
+#define IS_64BIT_RES ((sizeof(resource_size_t) == 8) ? 1 : 0)
-#define RIO_REGS_BASE (CCSRBAR + 0xc0000)
#define RIO_ATMU_REGS_OFFSET 0x10c00
-#define RIO_MSG_REGS_OFFSET 0x11000
+#define RIO_P_MSG_REGS_OFFSET 0x11000
+#define RIO_S_MSG_REGS_OFFSET 0x13000
+#define RIO_ESCSR 0x158
+#define RIO_CCSR 0x15c
+#define RIO_ISR_AACR 0x10120
+#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
#define RIO_MAINT_WIN_SIZE 0x400000
#define RIO_DBELL_WIN_SIZE 0x1000
+#define RIO_MAX_INB_ATMU 4
+#define RIO_MAX_OUTB_ATMU 8
+#define RIO_INB_ATMU_REGS_OFFSET 0x10de0
+#define RIO_ATMU_EN_MASK 0x80000000
+
+#define RIO_NREAD 0x4
+#define RIO_NWRITE 0x4
+#define RIO_NWRITE_R 0x5
+#define RIO_NREAD_R 0x5
#define RIO_MSG_OMR_MUI 0x00000002
#define RIO_MSG_OSR_TE 0x00000080
@@ -50,24 +87,33 @@
#define DOORBELL_DSR_TE 0x00000080
#define DOORBELL_DSR_QFI 0x00000010
#define DOORBELL_DSR_DIQI 0x00000001
-#define DOORBELL_TID_OFFSET 0x03
-#define DOORBELL_SID_OFFSET 0x05
+#define DOORBELL_TID_OFFSET 0x02
+#define DOORBELL_SID_OFFSET 0x04
#define DOORBELL_INFO_OFFSET 0x06
#define DOORBELL_MESSAGE_SIZE 0x08
-#define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
-#define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
+#define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
+#define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
struct rio_atmu_regs {
u32 rowtar;
- u32 pad1;
+ u32 rowtear;
u32 rowbar;
u32 pad2;
u32 rowar;
u32 pad3[3];
};
+struct rio_inb_atmu_regs {
+ u32 riwtar;
+ u32 pad1;
+ u32 riwbar;
+ u32 pad2;
+ u32 riwar;
+ u32 pad3[3];
+};
+
struct rio_msg_regs {
u32 omr;
u32 osr;
@@ -87,7 +133,15 @@ struct rio_msg_regs {
u32 ifqdpar;
u32 pad6;
u32 ifqepar;
- u32 pad7[250];
+ u32 pad7[226];
+ u32 odmr;
+ u32 odsr;
+ u32 res0[4];
+ u32 oddpr;
+ u32 oddatr;
+ u32 res1[3];
+ u32 odretcr;
+ u32 res2[12];
u32 dmr;
u32 dsr;
u32 pad8;
@@ -112,20 +166,12 @@ struct rio_tx_desc {
u32 res4;
};
-static u32 regs_win;
-static struct rio_atmu_regs *atmu_regs;
-static struct rio_atmu_regs *maint_atmu_regs;
-static struct rio_atmu_regs *dbell_atmu_regs;
-static u32 dbell_win;
-static u32 maint_win;
-static struct rio_msg_regs *msg_regs;
-
-static struct rio_dbell_ring {
+struct rio_dbell_ring {
void *virt;
dma_addr_t phys;
-} dbell_ring;
+};
-static struct rio_msg_tx_ring {
+struct rio_msg_tx_ring {
void *virt;
dma_addr_t phys;
void *virt_buffer[RIO_MAX_TX_RING_SIZE];
@@ -133,77 +179,110 @@ static struct rio_msg_tx_ring {
int tx_slot;
int size;
void *dev_id;
-} msg_tx_ring;
+};
-static struct rio_msg_rx_ring {
+struct rio_msg_rx_ring {
void *virt;
dma_addr_t phys;
void *virt_buffer[RIO_MAX_RX_RING_SIZE];
int rx_slot;
int size;
void *dev_id;
-} msg_rx_ring;
+};
+
+struct rio_priv {
+ volatile void __iomem *regs_win;
+ volatile struct rio_atmu_regs __iomem *atmu_regs;
+ volatile struct rio_atmu_regs __iomem *maint_atmu_regs;
+ volatile struct rio_atmu_regs __iomem *dbell_atmu_regs;
+ volatile void __iomem *dbell_win;
+ volatile void __iomem *maint_win;
+ volatile struct rio_msg_regs __iomem *msg_regs;
+ struct rio_dbell_ring dbell_ring;
+ struct rio_msg_tx_ring msg_tx_ring;
+ struct rio_msg_rx_ring msg_rx_ring;
+ int bellirq;
+ int txirq;
+ int rxirq;
+};
/**
- * mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message
+ * fsl_rio_doorbell_send - Send a RapidIO doorbell message
* @index: ID of RapidIO interface
* @destid: Destination ID of target device
* @data: 16-bit info field of RapidIO doorbell message
*
- * Sends a MPC85xx doorbell message. Returns %0 on success or
+ * Sends a RapidIO doorbell message. Returns %0 on success or
* %-EINVAL on failure.
*/
-static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data)
+static int fsl_rio_doorbell_send(struct rio_mport *mport, int index, u16 destid, u16 data)
{
- pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n",
- index, destid, data);
- out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22);
- out_be16((void *)(dbell_win), data);
+ struct rio_priv *priv = mport->priv;
+ pr_debug("fsl_doorbell_send: index %d destid 0x%04x data 0x%04x\n",
+ index, destid, data);
+
+ switch (mport->phy_type) {
+ case RIO_PHY_SERIAL:
+ /* In the later version silicons, such as MPC8548, MPC8641,
+ * below operations is must be.
+ */
+ out_be32(&priv->msg_regs->odmr, 0x00000000);
+ out_be32(&priv->msg_regs->odretcr, 0x00000004);
+ out_be32(&priv->msg_regs->oddpr, destid << 16);
+ out_be32(&priv->msg_regs->oddatr,data );
+ out_be32(&priv->msg_regs->odmr, 0x00000001);
+ break;
+ case RIO_PHY_PARALLEL:
+ out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
+ out_be16(priv->dbell_win, data);
+ break;
+ }
return 0;
}
/**
- * mpc85xx_local_config_read - Generate a MPC85xx local config space read
+ * fsl_local_config_read - Generate a RapidIO local config space read
* @index: ID of RapdiIO interface
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @data: Value to be read into
*
- * Generates a MPC85xx local configuration space read. Returns %0 on
+ * Generates a RapidIO local configuration space read. Returns %0 on
* success or %-EINVAL on failure.
*/
-static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data)
+static int fsl_local_config_read(struct rio_mport *mport, int index, u32 offset, int len, u32 * data)
{
- pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index,
- offset);
- *data = in_be32((void *)(regs_win + offset));
+ struct rio_priv *priv = mport->priv;
+ pr_debug("fsl_local_config_read: index %d offset 0x%08x\n", index,
+ offset);
+ *data = in_be32(priv->regs_win + offset);
return 0;
}
/**
- * mpc85xx_local_config_write - Generate a MPC85xx local config space write
+ * fsl_local_config_write - Generate a RapidIO local config space write
* @index: ID of RapdiIO interface
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @data: Value to be written
*
- * Generates a MPC85xx local configuration space write. Returns %0 on
+ * Generates a RapidIO local configuration space write. Returns %0 on
* success or %-EINVAL on failure.
*/
-static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data)
+static int fsl_local_config_write(struct rio_mport *mport, int index, u32 offset, int len, u32 data)
{
- pr_debug
- ("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n",
- index, offset, data);
- out_be32((void *)(regs_win + offset), data);
+ struct rio_priv *priv = mport->priv;
+ pr_debug("fsl_local_config_write: index %d offset 0x%08x data 0x%08x\n",
+ index, offset, data);
+ out_be32(priv->regs_win + offset, data);
return 0;
}
/**
- * mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction
+ * fsl_rio_config_read - Generate a read maintenance transaction
* @index: ID of RapdiIO interface
* @destid: Destination ID of transaction
* @hopcount: Number of hops to target device
@@ -211,31 +290,33 @@ static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data)
* @len: Length (in bytes) of the maintenance transaction
* @val: Location to be read into
*
- * Generates a MPC85xx read maintenance transaction. Returns %0 on
+ * Generates a read maintenance transaction. Returns %0 on
* success or %-EINVAL on failure.
*/
-static int
-mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
- u32 * val)
+static int fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
+ u8 hopcount, u32 offset, int len, u32 * val)
{
- u8 *data;
-
- pr_debug
- ("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
- index, destid, hopcount, offset, len);
- out_be32((void *)&maint_atmu_regs->rowtar,
- (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
-
- data = (u8 *) maint_win + offset;
+ volatile void __iomem *data;
+ struct rio_priv *priv = mport->priv;
+
+ pr_debug("fsl_rio_config_read: index %d destid %d hopcount %d "
+ "offset 0x%08x len %d\n",
+ index, destid, hopcount, offset, len);
+ out_be32(&priv->maint_atmu_regs->rowtar,
+ ((destid & 0x3ff) << 22) | (hopcount << 12)
+ | ((offset & ~0x3) >> 9));
+ out_be32(&priv->maint_atmu_regs->rowtear, (destid & 0xfc00) >> 10);
+
+ data = priv->maint_win + offset;
switch (len) {
case 1:
- *val = in_8((u8 *) data);
+ *val = in_8(data);
break;
case 2:
- *val = in_be16((u16 *) data);
+ *val = in_be16(data);
break;
default:
- *val = in_be32((u32 *) data);
+ *val = in_be32(data);
break;
}
@@ -243,7 +324,7 @@ mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
}
/**
- * mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction
+ * fsl_rio_config_write - Generate a write maintenance transaction
* @index: ID of RapdiIO interface
* @destid: Destination ID of transaction
* @hopcount: Number of hops to target device
@@ -251,30 +332,32 @@ mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
* @len: Length (in bytes) of the maintenance transaction
* @val: Value to be written
*
- * Generates an MPC85xx write maintenance transaction. Returns %0 on
+ * Generates an write maintenance transaction. Returns %0 on
* success or %-EINVAL on failure.
*/
-static int
-mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset,
- int len, u32 val)
+static int fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
+ u8 hopcount, u32 offset, int len, u32 val)
{
- u8 *data;
- pr_debug
- ("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
- index, destid, hopcount, offset, len, val);
- out_be32((void *)&maint_atmu_regs->rowtar,
- (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
-
- data = (u8 *) maint_win + offset;
+ volatile void __iomem *data;
+ struct rio_priv *priv = mport->priv;
+ pr_debug("fsl_rio_config_write: index %d destid %d hopcount %d"
+ "offset 0x%08x len %d val 0x%08x\n",
+ index, destid, hopcount, offset, len, val);
+ out_be32(&priv->maint_atmu_regs->rowtar,
+ ((destid & 0x3ff) << 22) | (hopcount << 12)
+ | ((offset & ~0x3) >> 9));
+ out_be32(&priv->maint_atmu_regs->rowtear, (destid & 0xfc00) >> 10);
+
+ data = priv->maint_win + offset;
switch (len) {
case 1:
- out_8((u8 *) data, val);
+ out_8(data, val);
break;
case 2:
- out_be16((u16 *) data, val);
+ out_be16(data, val);
break;
default:
- out_be32((u32 *) data, val);
+ out_be32(data, val);
break;
}
@@ -282,28 +365,204 @@ mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset,
}
/**
- * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
+ * fsl_rio_map_inb_mem -- Mapping inbound memory region.
+ * @lstart: Local memory space start address.
+ * @rstart: RapidIO space start address.
+ * @size: The mapping region size.
+ * @flags: Flags for mapping. 0 for using default flags.
+ *
+ * Return: 0 -- Success.
+ *
+ * This function will create the inbound mapping
+ * from rstart to lstart.
+ */
+static int fsl_rio_map_inb_mem(struct rio_mport *mport, resource_size_t lstart,
+ resource_size_t rstart, resource_size_t size,
+ u32 flags)
+{
+ int i;
+ struct rio_priv *priv = mport->priv;
+ volatile struct rio_inb_atmu_regs __iomem *inbatmu =
+ (struct rio_inb_atmu_regs *)
+ (priv->regs_win + RIO_INB_ATMU_REGS_OFFSET) - 1;
+ int size_ffs;
+ resource_size_t align;
+
+ if (flags == 0)
+ flags = (RIO_NREAD_R << 4) | RIO_NWRITE_R;
+
+ align = (size < 0x1000) ? 0x1000 : 1 << (__ilog2(size - 1) + 1);
+
+ /* Align the size */
+ if ((lstart + size) > (_ALIGN_DOWN(lstart, align) + align)) {
+ size_ffs = __ffs(_ALIGN_DOWN(lstart + size - 1, align));
+ size = 1 << (size_ffs + (((_ALIGN_DOWN(lstart, 1 << size_ffs) +
+ (1 << size_ffs)) < (lstart + size)) ? 1 : 0));
+ } else
+ size = align;
+
+ if ((lstart & (size - 1)) != (rstart & (size - 1))) {
+ ERR("The local address 0x%x can not be aligned to the same size"
+ " 0x%x with the RapidIO space address 0x%x!\n", lstart,
+ size, rstart);
+ return -EINVAL;
+ }
+
+ /* Search for free inbound ATMU */
+ for (i = 1;
+ (i <= RIO_MAX_INB_ATMU) && (inbatmu->riwar & RIO_ATMU_EN_MASK);
+ i++, inbatmu--)
+ ;
+
+ if (i > RIO_MAX_INB_ATMU) {
+ ERR("No free inbound ATMU!\n");
+ return -EBUSY;
+ }
+ out_be32(&inbatmu->riwtar, ((IS_64BIT_RES ? (lstart >> 32)
+ & 0xf : 0) << 20) | ((lstart >> 12) & 0xfffff));
+ out_be32(&inbatmu->riwbar, ((IS_64BIT_RES ? (rstart >> 32)
+ & 0x3 : 0) << 20) | ((rstart >> 12) & 0xfffff));
+ out_be32(&inbatmu->riwar, 0x80000000 | (0xf << 20)
+ | ((flags & 0xff) << 12)
+ | (__ilog2(size) - 1));
+ return 0;
+}
+
+/**
+ * fsl_rio_map_outb_mem -- Mapping outbound memory region.
+ * @lstart: Local memory space start address.
+ * @rstart: RapidIO space start address.
+ * @size: The mapping region size.
+ * @tid: The target RapidIO device id.
+ * @flags: Flags for mapping. 0 for using default flags.
+ *
+ * Return: 0 -- Success.
+ *
+ * This function will create the outbound mapping
+ * from lstart to rstart.
+ */
+static int fsl_rio_map_outb_mem(struct rio_mport *mport, resource_size_t lstart,
+ resource_size_t rstart, resource_size_t size,
+ u16 tid, u32 flags)
+{
+ int i;
+ struct rio_priv *priv = mport->priv;
+ volatile struct rio_atmu_regs __iomem *outbatmu =
+ (struct rio_atmu_regs *)
+ (priv->regs_win + RIO_ATMU_REGS_OFFSET) + 1;
+ int size_ffs;
+ resource_size_t align;
+
+ if (flags == 0)
+ flags = (RIO_NREAD << 4) | RIO_NWRITE_R;
+
+ align = (size < 0x1000) ? 0x1000 : 1 << (__ilog2(size - 1) + 1);
+
+ /* Align the size */
+ if ((lstart + size) > (_ALIGN_DOWN(lstart, align) + align)) {
+ size_ffs = __ffs(_ALIGN_DOWN(lstart + size - 1, align));
+ size = 1 << (size_ffs + (((_ALIGN_DOWN(lstart, 1 << size_ffs) +
+ (1 << size_ffs)) < (lstart + size)) ? 1 : 0));
+ } else
+ size = align;
+
+ if ((lstart & (size - 1)) != (rstart & (size - 1))) {
+ ERR("The local address 0x%x can not be aligned to the same size"
+ " 0x%x with the RapidIO space address 0x%x!\n", lstart,
+ size, rstart);
+ return -EINVAL;
+ }
+
+ /* Search for free outbound ATMU */
+ for (i = 1;
+ (i <= RIO_MAX_OUTB_ATMU) && (outbatmu->rowar & RIO_ATMU_EN_MASK);
+ i++, outbatmu++)
+ ;
+
+ if (i > RIO_MAX_OUTB_ATMU) {
+ ERR("No free outbound ATMU!\n");
+ return -EBUSY;
+ }
+ out_be32(&outbatmu->rowtar, ((tid & 0x3ff) << 22)
+ | ((IS_64BIT_RES ? (rstart >> 32) & 0x3 : 0) << 20)
+ | ((rstart >> 12) & 0xfffff));
+ if (mport->phy_type == RIO_PHY_SERIAL)
+ out_be32(&outbatmu->rowtear, tid >> 10);
+ out_be32(&outbatmu->rowbar, ((IS_64BIT_RES ?
+ (lstart >> 32) & 0xf : 0) << 20)
+ | ((lstart >> 12) & 0xfffff));
+ out_be32(&outbatmu->rowar, 0x80000000
+ | ((flags & 0xff) << 12)
+ | (__ilog2(size) - 1));
+ return 0;
+}
+
+/**
+ * fsl_rio_unmap_inb_mem -- Unmapping inbound memory region.
+ * @lstart: Local memory space start address.
+ */
+static void fsl_rio_unmap_inb_mem(struct rio_mport *mport, resource_size_t lstart)
+{
+ int i;
+ struct rio_priv *priv = mport->priv;
+ volatile struct rio_inb_atmu_regs __iomem *inbatmu = (struct rio_inb_atmu_regs *)
+ (priv->regs_win + RIO_INB_ATMU_REGS_OFFSET) - 1;
+
+ /* Search for inbound ATMU */
+ for (i = 1; i <= RIO_MAX_INB_ATMU ; i++, inbatmu--) {
+ u32 tar = ((IS_64BIT_RES ? (lstart >> 32) & 0xf : 0) << 20)
+ | ((lstart >> 12) & 0xfffff);
+ if (inbatmu->riwtar == tar) {
+ out_be32(&inbatmu->riwar, ~(RIO_ATMU_EN_MASK));
+ return;
+ }
+ }
+}
+
+/**
+ * fsl_rio_unmap_inb_mem -- Unmapping outbound memory region.
+ * @lstart: Local memory space start address.
+ */
+static void fsl_rio_unmap_outb_mem(struct rio_mport *mport, resource_size_t lstart)
+{
+ int i;
+ struct rio_priv *priv = mport->priv;
+ volatile struct rio_atmu_regs __iomem *outbatmu = (struct rio_atmu_regs *)
+ (priv->regs_win + RIO_ATMU_REGS_OFFSET) + 1;
+
+ /* Search for outbound ATMU */
+ for (i = 1; i <= RIO_MAX_OUTB_ATMU ; i++, outbatmu++) {
+ u32 bar = ((IS_64BIT_RES ? (lstart >> 32) & 0xf : 0) << 20)
+ | ((lstart >> 12) & 0xfffff);
+ if (outbatmu->rowbar == bar) {
+ out_be32(&outbatmu->rowar, ~(RIO_ATMU_EN_MASK));
+ return;
+ }
+ }
+}
+
+/**
+ * rio_hw_add_outb_message - Add message to the outbound message queue
* @mport: Master port with outbound message queue
* @rdev: Target of outbound message
* @mbox: Outbound mailbox
* @buffer: Message to add to outbound queue
* @len: Length of message
*
- * Adds the @buffer message to the MPC85xx outbound message queue. Returns
+ * Adds the @buffer message to the outbound message queue. Returns
* %0 on success or %-EINVAL on failure.
*/
-int
-rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
- void *buffer, size_t len)
+int rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev,
+ int mbox, void *buffer, size_t len)
{
- u32 omr;
+ struct rio_priv *priv = mport->priv;
struct rio_tx_desc *desc =
- (struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot;
+ (struct rio_tx_desc *)priv->msg_tx_ring.virt + priv->msg_tx_ring.tx_slot;
int ret = 0;
- pr_debug
- ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
- rdev->destid, mbox, (int)buffer, len);
+ pr_debug("RIO: rio_hw_add_outb_message(): "
+ "destid 0x%04x mbox %d buffer %p len 0x%08x\n",
+ rdev->destid, mbox, buffer, len);
if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
ret = -EINVAL;
@@ -311,31 +570,40 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
}
/* Copy and clear rest of buffer */
- memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len);
+ memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer, len);
if (len < (RIO_MAX_MSG_SIZE - 4))
- memset((void *)((u32) msg_tx_ring.
- virt_buffer[msg_tx_ring.tx_slot] + len), 0,
- RIO_MAX_MSG_SIZE - len);
+ memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
+ + len, 0, RIO_MAX_MSG_SIZE - len);
- /* Set mbox field for message */
- desc->dport = mbox & 0x3;
+ switch(mport->phy_type) {
+ case RIO_PHY_SERIAL:
+ /* Set mbox field for message, and set destid */
+ desc->dport = (rdev->destid << 16) | ( mbox & 0x3);
- /* Enable EOMI interrupt, set priority, and set destid */
- desc->dattr = 0x28000000 | (rdev->destid << 2);
+ /* Enable EOMI interrupt and priority */
+ desc->dattr = 0x28000000;
+
+ /* Set mbox field for message */
+ desc->dport = mbox & 0x3;
+ break;
+ case RIO_PHY_PARALLEL:
+ /* Enable EOMI interrupt, set priority, and set destid */
+ desc->dattr = 0x28000000 | (rdev->destid << 2);
+ break;
+ }
/* Set transfer size aligned to next power of 2 (in double words) */
desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
/* Set snooping and source buffer address */
- desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot];
+ desc->saddr = 0x00000004 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
/* Increment enqueue pointer */
- omr = in_be32((void *)&msg_regs->omr);
- out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI);
+ setbits32(&priv->msg_regs->omr, RIO_MSG_OMR_MUI);
/* Go to next descriptor */
- if (++msg_tx_ring.tx_slot == msg_tx_ring.size)
- msg_tx_ring.tx_slot = 0;
+ if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
+ priv->msg_tx_ring.tx_slot = 0;
out:
return ret;
@@ -344,40 +612,40 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
/**
- * mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler
+ * fsl_rio_tx_handler - outbound message interrupt handler
* @irq: Linux interrupt number
* @dev_instance: Pointer to interrupt-specific data
*
* Handles outbound message interrupts. Executes a register outbound
- * mailbox event handler and acks the interrupt occurrence.
+ * mailbox event handler and acks the interrupt occurence.
*/
-static irqreturn_t
-mpc85xx_rio_tx_handler(int irq, void *dev_instance)
+static irqreturn_t fsl_rio_tx_handler(int irq, void *dev_instance)
{
int osr;
struct rio_mport *port = (struct rio_mport *)dev_instance;
+ struct rio_priv *priv = port->priv;
- osr = in_be32((void *)&msg_regs->osr);
+ osr = in_be32(&priv->msg_regs->osr);
- if (osr & RIO_MSG_OSR_TE) {
+ if (unlikely(osr & RIO_MSG_OSR_TE)) {
pr_info("RIO: outbound message transmission error\n");
- out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE);
+ out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
goto out;
}
- if (osr & RIO_MSG_OSR_QOI) {
+ if (unlikely(osr & RIO_MSG_OSR_QOI)) {
pr_info("RIO: outbound message queue overflow\n");
- out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI);
+ out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
goto out;
}
if (osr & RIO_MSG_OSR_EOMI) {
- u32 dqp = in_be32((void *)&msg_regs->odqdpar);
- int slot = (dqp - msg_tx_ring.phys) >> 5;
- port->outb_msg[0].mcback(port, msg_tx_ring.dev_id, -1, slot);
+ u32 dqp = in_be32(&priv->msg_regs->odqdpar);
+ int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
+ port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1, slot);
/* Ack the end-of-message interrupt */
- out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI);
+ out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
}
out:
@@ -385,7 +653,7 @@ mpc85xx_rio_tx_handler(int irq, void *dev_instance)
}
/**
- * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
+ * rio_open_outb_mbox - Initialize outbound mailbox
* @mport: Master port implementing the outbound message unit
* @dev_id: Device specific pointer to pass on event
* @mbox: Mailbox to open
@@ -398,6 +666,7 @@ mpc85xx_rio_tx_handler(int irq, void *dev_instance)
int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
{
int i, j, rc = 0;
+ struct rio_priv *priv = mport->priv;
if ((entries < RIO_MIN_TX_RING_SIZE) ||
(entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
@@ -406,54 +675,54 @@ int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entr
}
/* Initialize shadow copy ring */
- msg_tx_ring.dev_id = dev_id;
- msg_tx_ring.size = entries;
+ priv->msg_tx_ring.dev_id = dev_id;
+ priv->msg_tx_ring.size = entries;
- for (i = 0; i < msg_tx_ring.size; i++) {
- if (!
- (msg_tx_ring.virt_buffer[i] =
+ for (i = 0; i < priv->msg_tx_ring.size; i++) {
+ priv->msg_tx_ring.virt_buffer[i] =
dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
- &msg_tx_ring.phys_buffer[i],
- GFP_KERNEL))) {
+ &priv->msg_tx_ring.phys_buffer[i],
+ GFP_KERNEL);
+ if (!priv->msg_tx_ring.virt_buffer[i]) {
rc = -ENOMEM;
- for (j = 0; j < msg_tx_ring.size; j++)
- if (msg_tx_ring.virt_buffer[j])
+ for (j = 0; j < priv->msg_tx_ring.size; j++)
+ if (priv->msg_tx_ring.virt_buffer[j])
dma_free_coherent(NULL,
RIO_MSG_BUFFER_SIZE,
- msg_tx_ring.
+ priv->msg_tx_ring.
virt_buffer[j],
- msg_tx_ring.
+ priv->msg_tx_ring.
phys_buffer[j]);
goto out;
}
}
/* Initialize outbound message descriptor ring */
- if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL,
- msg_tx_ring.size *
+ priv->msg_tx_ring.virt = dma_alloc_coherent(NULL,
+ priv->msg_tx_ring.size *
RIO_MSG_DESC_SIZE,
- &msg_tx_ring.phys,
- GFP_KERNEL))) {
+ &priv->msg_tx_ring.phys,
+ GFP_KERNEL);
+ if (!priv->msg_tx_ring.virt) {
rc = -ENOMEM;
goto out_dma;
}
- memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE);
- msg_tx_ring.tx_slot = 0;
+ priv->msg_tx_ring.tx_slot = 0;
/* Point dequeue/enqueue pointers at first entry in ring */
- out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys);
- out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys);
+ out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
+ out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
/* Configure for snooping */
- out_be32((void *)&msg_regs->osar, 0x00000004);
+ out_be32(&priv->msg_regs->osar, 0x00000004);
/* Clear interrupt status */
- out_be32((void *)&msg_regs->osr, 0x000000b3);
+ out_be32(&priv->msg_regs->osr, 0x000000b3);
/* Hook up outbound message handler */
- if ((rc =
- request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0,
- "msg_tx", (void *)mport)) < 0)
+ rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, "msg_tx",
+ mport);
+ if (rc < 0)
goto out_irq;
/*
@@ -463,34 +732,33 @@ int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entr
* Chaining mode
* Disable
*/
- out_be32((void *)&msg_regs->omr, 0x00100220);
+ out_be32(&priv->msg_regs->omr, 0x00100220);
/* Set number of entries */
- out_be32((void *)&msg_regs->omr,
- in_be32((void *)&msg_regs->omr) |
+ setbits32(&priv->msg_regs->omr,
((get_bitmask_order(entries) - 2) << 12));
/* Now enable the unit */
- out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1);
+ setbits32(&priv->msg_regs->omr, 0x1);
out:
return rc;
out_irq:
- dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
- msg_tx_ring.virt, msg_tx_ring.phys);
+ dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
+ priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
out_dma:
- for (i = 0; i < msg_tx_ring.size; i++)
+ for (i = 0; i < priv->msg_tx_ring.size; i++)
dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
- msg_tx_ring.virt_buffer[i],
- msg_tx_ring.phys_buffer[i]);
+ priv->msg_tx_ring.virt_buffer[i],
+ priv->msg_tx_ring.phys_buffer[i]);
return rc;
}
/**
- * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
+ * rio_close_outb_mbox - Shut down outbound mailbox
* @mport: Master port implementing the outbound message unit
* @mbox: Mailbox to close
*
@@ -499,36 +767,37 @@ int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entr
*/
void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
{
+ struct rio_priv *priv = mport->priv;
/* Disable inbound message unit */
- out_be32((void *)&msg_regs->omr, 0);
+ out_be32(&priv->msg_regs->omr, 0);
/* Free ring */
- dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
- msg_tx_ring.virt, msg_tx_ring.phys);
+ dma_free_coherent(NULL, priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
+ priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
/* Free interrupt */
- free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport);
+ free_irq(IRQ_RIO_TX(mport), mport);
}
/**
- * mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler
+ * fsl_rio_rx_handler - inbound message interrupt handler
* @irq: Linux interrupt number
* @dev_instance: Pointer to interrupt-specific data
*
* Handles inbound message interrupts. Executes a registered inbound
- * mailbox event handler and acks the interrupt occurrence.
+ * mailbox event handler and acks the interrupt occurence.
*/
-static irqreturn_t
-mpc85xx_rio_rx_handler(int irq, void *dev_instance)
+static irqreturn_t fsl_rio_rx_handler(int irq, void *dev_instance)
{
int isr;
struct rio_mport *port = (struct rio_mport *)dev_instance;
+ struct rio_priv *priv = port->priv;
- isr = in_be32((void *)&msg_regs->isr);
+ isr = in_be32(&priv->msg_regs->isr);
- if (isr & RIO_MSG_ISR_TE) {
+ if (unlikely(isr & RIO_MSG_ISR_TE)) {
pr_info("RIO: inbound message reception error\n");
- out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE);
+ out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_TE);
goto out;
}
@@ -540,10 +809,10 @@ mpc85xx_rio_rx_handler(int irq, void *dev_instance)
* make the callback with an unknown/invalid mailbox number
* argument.
*/
- port->inb_msg[0].mcback(port, msg_rx_ring.dev_id, -1, -1);
+ port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
/* Ack the queueing interrupt */
- out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI);
+ out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
}
out:
@@ -551,7 +820,7 @@ mpc85xx_rio_rx_handler(int irq, void *dev_instance)
}
/**
- * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
+ * rio_open_inb_mbox - Initialize inbound mailbox
* @mport: Master port implementing the inbound message unit
* @dev_id: Device specific pointer to pass on event
* @mbox: Mailbox to open
@@ -564,6 +833,7 @@ mpc85xx_rio_rx_handler(int irq, void *dev_instance)
int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
{
int i, rc = 0;
+ struct rio_priv *priv = mport->priv;
if ((entries < RIO_MIN_RX_RING_SIZE) ||
(entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
@@ -572,36 +842,37 @@ int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entri
}
/* Initialize client buffer ring */
- msg_rx_ring.dev_id = dev_id;
- msg_rx_ring.size = entries;
- msg_rx_ring.rx_slot = 0;
- for (i = 0; i < msg_rx_ring.size; i++)
- msg_rx_ring.virt_buffer[i] = NULL;
+ priv->msg_rx_ring.dev_id = dev_id;
+ priv->msg_rx_ring.size = entries;
+ priv->msg_rx_ring.rx_slot = 0;
+ for (i = 0; i < priv->msg_rx_ring.size; i++)
+ priv->msg_rx_ring.virt_buffer[i] = NULL;
/* Initialize inbound message ring */
- if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL,
- msg_rx_ring.size *
+ priv->msg_rx_ring.virt = dma_alloc_coherent(NULL,
+ priv->msg_rx_ring.size *
RIO_MAX_MSG_SIZE,
- &msg_rx_ring.phys,
- GFP_KERNEL))) {
+ &priv->msg_rx_ring.phys,
+ GFP_KERNEL);
+ if (!priv->msg_rx_ring.virt) {
rc = -ENOMEM;
goto out;
}
/* Point dequeue/enqueue pointers at first entry in ring */
- out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys);
- out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys);
+ out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
+ out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
/* Clear interrupt status */
- out_be32((void *)&msg_regs->isr, 0x00000091);
+ out_be32(&priv->msg_regs->isr, 0x00000091);
/* Hook up inbound message handler */
- if ((rc =
- request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0,
- "msg_rx", (void *)mport)) < 0) {
+ rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
+ "msg_rx", mport);
+ if (rc < 0) {
dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
- msg_tx_ring.virt_buffer[i],
- msg_tx_ring.phys_buffer[i]);
+ priv->msg_tx_ring.virt_buffer[i],
+ priv->msg_tx_ring.phys_buffer[i]);
goto out;
}
@@ -612,22 +883,21 @@ int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entri
* Unmask all interrupt sources
* Disable
*/
- out_be32((void *)&msg_regs->imr, 0x001b0060);
+ out_be32(&priv->msg_regs->imr, 0x001b0060);
/* Set number of queue entries */
- out_be32((void *)&msg_regs->imr,
- in_be32((void *)&msg_regs->imr) |
- ((get_bitmask_order(entries) - 2) << 12));
+ setbits32(&priv->msg_regs->imr,
+ ((get_bitmask_order(entries) - 2) << 12));
/* Now enable the unit */
- out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1);
+ setbits32(&priv->msg_regs->imr, 0x1);
out:
return rc;
}
/**
- * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
+ * rio_close_inb_mbox - Shut down inbound mailbox
* @mport: Master port implementing the inbound message unit
* @mbox: Mailbox to close
*
@@ -636,44 +906,45 @@ int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entri
*/
void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
{
+ struct rio_priv *priv = mport->priv;
/* Disable inbound message unit */
- out_be32((void *)&msg_regs->imr, 0);
+ out_be32(&priv->msg_regs->imr, 0);
/* Free ring */
- dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE,
- msg_rx_ring.virt, msg_rx_ring.phys);
+ dma_free_coherent(NULL, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
+ priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
/* Free interrupt */
- free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport);
+ free_irq(IRQ_RIO_RX(mport), mport);
}
/**
- * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
+ * rio_hw_add_inb_buffer - Add buffer to the inbound message queue
* @mport: Master port implementing the inbound message unit
* @mbox: Inbound mailbox number
* @buf: Buffer to add to inbound queue
*
- * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
+ * Adds the @buf buffer to the inbound message queue. Returns
* %0 on success or %-EINVAL on failure.
*/
int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
{
int rc = 0;
+ struct rio_priv *priv = mport->priv;
pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
- msg_rx_ring.rx_slot);
+ priv->msg_rx_ring.rx_slot);
- if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) {
- printk(KERN_ERR
- "RIO: error adding inbound buffer %d, buffer exists\n",
- msg_rx_ring.rx_slot);
+ if (unlikely(priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot])) {
+ ERR("error adding inbound buffer %d, buffer exists\n",
+ priv->msg_rx_ring.rx_slot);
rc = -EINVAL;
goto out;
}
- msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf;
- if (++msg_rx_ring.rx_slot == msg_rx_ring.size)
- msg_rx_ring.rx_slot = 0;
+ priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
+ if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
+ priv->msg_rx_ring.rx_slot = 0;
out:
return rc;
@@ -682,7 +953,7 @@ int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
/**
- * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
+ * rio_hw_get_inb_message - Fetch inbound message from the message unit
* @mport: Master port implementing the inbound message unit
* @mbox: Inbound mailbox number
*
@@ -691,36 +962,35 @@ EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
*/
void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
{
- u32 imr;
- u32 phys_buf, virt_buf;
+ u32 phys_buf;
+ void *virt_buf = NULL;
void *buf = NULL;
int buf_idx;
+ struct rio_priv *priv = mport->priv;
- phys_buf = in_be32((void *)&msg_regs->ifqdpar);
+ phys_buf = in_be32(&priv->msg_regs->ifqdpar);
/* If no more messages, then bail out */
- if (phys_buf == in_be32((void *)&msg_regs->ifqepar))
+ if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
goto out2;
- virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys);
- buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
- buf = msg_rx_ring.virt_buffer[buf_idx];
+ virt_buf = priv->msg_rx_ring.virt + (phys_buf - priv->msg_rx_ring.phys);
+ buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
+ buf = priv->msg_rx_ring.virt_buffer[buf_idx];
- if (!buf) {
- printk(KERN_ERR
- "RIO: inbound message copy failed, no buffers\n");
+ if (unlikely(!buf)) {
+ ERR("inbound message copy failed, no buffers\n");
goto out1;
}
/* Copy max message size, caller is expected to allocate that big */
- memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
+ memcpy(buf, virt_buf, RIO_MAX_MSG_SIZE);
/* Clear the available buffer */
- msg_rx_ring.virt_buffer[buf_idx] = NULL;
+ priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
out1:
- imr = in_be32((void *)&msg_regs->imr);
- out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI);
+ setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
out2:
return buf;
@@ -729,45 +999,44 @@ void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
/**
- * mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler
+ * fsl_rio_dbell_handler - doorbell interrupt handler
* @irq: Linux interrupt number
* @dev_instance: Pointer to interrupt-specific data
*
* Handles doorbell interrupts. Parses a list of registered
* doorbell event handlers and executes a matching event handler.
*/
-static irqreturn_t
-mpc85xx_rio_dbell_handler(int irq, void *dev_instance)
+static irqreturn_t fsl_rio_dbell_handler(int irq, void *dev_instance)
{
int dsr;
struct rio_mport *port = (struct rio_mport *)dev_instance;
+ struct rio_priv *priv = port->priv;
- dsr = in_be32((void *)&msg_regs->dsr);
+ dsr = in_be32(&priv->msg_regs->dsr);
if (dsr & DOORBELL_DSR_TE) {
pr_info("RIO: doorbell reception error\n");
- out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE);
+ out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
goto out;
}
if (dsr & DOORBELL_DSR_QFI) {
pr_info("RIO: doorbell queue full\n");
- out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI);
+ out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
goto out;
}
/* XXX Need to check/dispatch until queue empty */
if (dsr & DOORBELL_DSR_DIQI) {
u32 dmsg =
- (u32) dbell_ring.virt +
- (in_be32((void *)&msg_regs->dqdpar) & 0xfff);
- u32 dmr;
+ (u32) priv->dbell_ring.virt +
+ (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
struct rio_dbell *dbell;
int found = 0;
- pr_debug
- ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
- DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
+ pr_debug("RIO: processing doorbell, sid 0x%02x tid 0x%02x "
+ "info 0x%04x\n", DBELL_SID(dmsg),
+ DBELL_TID(dmsg), DBELL_INF(dmsg));
list_for_each_entry(dbell, &port->dbells, node) {
if ((dbell->res->start <= DBELL_INF(dmsg)) &&
@@ -780,13 +1049,13 @@ mpc85xx_rio_dbell_handler(int irq, void *dev_instance)
dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
DBELL_INF(dmsg));
} else {
- pr_debug
- ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
- DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
+ pr_debug("RIO: spurious doorbell, sid 0x%02x "
+ "tid 0x%02x info %4.4x\n",
+ DBELL_SID(dmsg), DBELL_TID(dmsg),
+ DBELL_INF(dmsg));
}
- dmr = in_be32((void *)&msg_regs->dmr);
- out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI);
- out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI);
+ setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
+ out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
}
out:
@@ -794,67 +1063,76 @@ mpc85xx_rio_dbell_handler(int irq, void *dev_instance)
}
/**
- * mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init
+ * fsl_rio_doorbell_init - doorbell interface init
* @mport: Master port implementing the inbound doorbell unit
*
* Initializes doorbell unit hardware and inbound DMA buffer
- * ring. Called from mpc85xx_rio_setup(). Returns %0 on success
+ * ring. Called from fsl_rio_setup(). Returns %0 on success
* or %-ENOMEM on failure.
*/
-static int mpc85xx_rio_doorbell_init(struct rio_mport *mport)
+static int fsl_rio_doorbell_init(struct rio_mport *mport, phys_addr_t dbaddr)
{
int rc = 0;
+ struct rio_priv *priv = mport->priv;
/* Map outbound doorbell window immediately after maintenance window */
- if (!(dbell_win =
- (u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
- RIO_DBELL_WIN_SIZE))) {
- printk(KERN_ERR
- "RIO: unable to map outbound doorbell window\n");
+ priv->dbell_win = ioremap(dbaddr, RIO_DBELL_WIN_SIZE);
+ if (!priv->dbell_win) {
+ ERR("unable to map outbound doorbell window\n");
rc = -ENOMEM;
goto out;
}
/* Initialize inbound doorbells */
- if (!(dbell_ring.virt = dma_alloc_coherent(NULL,
+ priv->dbell_ring.virt = dma_alloc_coherent(NULL,
512 * DOORBELL_MESSAGE_SIZE,
- &dbell_ring.phys,
- GFP_KERNEL))) {
- printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
+ &priv->dbell_ring.phys,
+ GFP_KERNEL);
+ if (!priv->dbell_ring.virt) {
+ ERR("unable allocate inbound doorbell ring\n");
rc = -ENOMEM;
- iounmap((void *)dbell_win);
+ iounmap(priv->dbell_win);
goto out;
}
/* Point dequeue/enqueue pointers at first entry in ring */
- out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys);
- out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys);
+ out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
+ out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
/* Clear interrupt status */
- out_be32((void *)&msg_regs->dsr, 0x00000091);
+ out_be32(&priv->msg_regs->dsr, 0x00000091);
/* Hook up doorbell handler */
- if ((rc =
- request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0,
- "dbell_rx", (void *)mport) < 0)) {
- iounmap((void *)dbell_win);
+ rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
+ "dbell_rx", mport);
+ if (rc < 0) {
+ iounmap(priv->dbell_win);
dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
- dbell_ring.virt, dbell_ring.phys);
- printk(KERN_ERR
- "MPC85xx RIO: unable to request inbound doorbell irq");
+ priv->dbell_ring.virt, priv->dbell_ring.phys);
+ ERR("unable to request inbound doorbell irq");
goto out;
}
/* Configure doorbells for snooping, 512 entries, and enable */
- out_be32((void *)&msg_regs->dmr, 0x00108161);
+ out_be32(&priv->msg_regs->dmr, 0x00108161);
out:
return rc;
}
+u32 rio_get_mport_id(struct rio_mport *mport)
+{
+ u32 mport_id = 0;
+
+ rio_local_read_config_32(mport, 0x60, &mport_id);
+ mport_id = mport->sys_size ? (mport_id & 0xffff) : ((mport_id >> 16) & 0xff);
+ return mport_id;
+
+}
+
static char *cmdline = NULL;
-static int mpc85xx_rio_get_hdid(int index)
+static int fsl_rio_get_hdid(int index)
{
/* XXX Need to parse multiple entries in some format */
if (!cmdline)
@@ -863,7 +1141,7 @@ static int mpc85xx_rio_get_hdid(int index)
return simple_strtol(cmdline, NULL, 0);
}
-static int mpc85xx_rio_get_cmdline(char *s)
+static int fsl_rio_get_cmdline(char *s)
{
if (!s)
return 0;
@@ -872,61 +1150,345 @@ static int mpc85xx_rio_get_cmdline(char *s)
return 1;
}
-__setup("riohdid=", mpc85xx_rio_get_cmdline);
+__setup("riohdid=", fsl_rio_get_cmdline);
+
+static struct rio_mem_ops fsl_mem_ops = {
+ .map_inb = fsl_rio_map_inb_mem,
+ .map_outb = fsl_rio_map_outb_mem,
+ .unmap_inb = fsl_rio_unmap_inb_mem,
+ .unmap_outb = fsl_rio_unmap_outb_mem,
+};
+
+static inline void fsl_rio_info(u32 ccsr)
+{
+ if (ccsr & 1) {
+ /* Serial phy */
+ INFO("Hardware port width: ");
+ switch (ccsr >> 30) {
+ case 0:
+ printk("1\n");
+ break;
+ case 1:
+ printk("4\n");
+ break;
+ default:
+ printk("Unknown\n");
+ break;;
+ }
+
+ INFO("Training connection status: ");
+ switch ((ccsr >> 27) & 7) {
+ case 0:
+ printk("Single-lane 0\n");
+ break;
+ case 1:
+ printk("Single-lane 2\n");
+ break;
+ case 2:
+ printk("Four-lane\n");
+ break;
+ default:
+ printk("Unknown\n");
+ }
+ } else {
+ /* Parallel phy */
+ if (ccsr & 0x80000000)
+ INFO("Output port operating in 8-bit mode\n");
+ if (ccsr & 0x08000000)
+ INFO("Input port operating in 8-bit mode\n");
+ }
+
+}
+
+static inline u8 hw_port_width(u32 ccsr)
+{
+ u8 pw = ccsr >> 30;
+ switch (pw) {
+ case 0:
+ return 1;
+ case 1:
+ return 4;
+ default:
+ return 0;
+ }
+}
+
+static int of_cells_get(struct device_node *np, const char *str)
+{
+ struct device_node *tmp = NULL;
+ const int *var = NULL;
+
+ var = of_get_property(np, str, NULL);
+ tmp = of_get_parent(np);
+
+ while (!var && tmp) {
+ var = (int *)of_get_property(tmp, str, NULL);
+ of_node_put(tmp);
+ tmp = of_get_parent(np);
+ }
+
+ return (var ? *var : 0);
+}
/**
- * mpc85xx_rio_setup - Setup MPC85xx RapidIO interface
- * @law_start: Starting physical address of RapidIO LAW
- * @law_size: Size of RapidIO LAW
+ * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
*
- * Initializes MPC85xx RapidIO hardware interface, configures
+ * Initializes Freescale PowerPC RapidIO hardware interface, configures
* master port with system-specific info, and registers the
* master port with the RapidIO subsystem.
*/
-void mpc85xx_rio_setup(int law_start, int law_size)
+int fsl_rio_setup(struct of_device *dev)
{
- struct rio_ops *ops;
- struct rio_mport *port;
+ struct rio_ops *ops = NULL;
+ struct rio_mport *port = NULL;
+ const u32 *dt_range;
+ int rlen = 0;
+ resource_size_t law_start = 0, law_size = 0;
+ struct resource regs;
+ int rc;
+ enum rio_phy_type phy_type;
+ volatile void __iomem *regs_win = NULL;
+ struct rio_priv *priv = NULL;
+ u32 ccsr;
+ int paw, aw, psw;
+ struct device_node *pa;
+
+ if (!dev->node) {
+ ERR("Dev ofnode is NULL\n");
+ return -EFAULT;
+ }
+
+ dt_range = of_get_property(dev->node, "ranges", &rlen);
+ if (!dt_range) {
+ ERR("Can't get %s property 'ranges'\n", dev->node->full_name);
+ return -EFAULT;
+ }
+
+ aw = of_cells_get(dev->node, "#address-cells");
+ pa = of_get_parent(dev->node);
+ paw = of_cells_get(pa, "#address-cells");
+ psw = of_cells_get(pa, "#size-cells");
+ of_node_put(pa);
- ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
- ops->lcread = mpc85xx_local_config_read;
- ops->lcwrite = mpc85xx_local_config_write;
- ops->cread = mpc85xx_rio_config_read;
- ops->cwrite = mpc85xx_rio_config_write;
- ops->dsend = mpc85xx_rio_doorbell_send;
+ law_start = of_read_number(dt_range + aw, paw);
+ law_size = of_read_number(dt_range + aw + paw, psw);
- port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL);
+ rc = of_address_to_resource(dev->node, 0, ®s);
+ if (rc) {
+ ERR("Can't get %s property 'reg'\n", dev->node->full_name);
+ return -EFAULT;
+ }
+ INFO("Of-device full name %s\n", dev->node->full_name);
+ INFO("LAW start 0x%016llx, size 0x%016llx.\n", (u64)law_start,
+ (u64)law_size);
+ INFO("Regs start 0x%08x size 0x%08x\n", regs.start,
+ regs.end - regs.start + 1);
+
+ regs_win = ioremap(regs.start, regs.end - regs.start + 1);
+ if (!regs_win) {
+ ERR("Can't remap io for 'regs_win'\n");
+ rc = -ENOMEM;
+ goto err;
+ }
+
+ /* Probe the RapidIO phy type */
+ ccsr = in_be32(regs_win + RIO_CCSR);
+ if (ccsr & 1)
+ phy_type = RIO_PHY_SERIAL;
+ else
+ phy_type = RIO_PHY_PARALLEL;
+ INFO("Phy type: ");
+ switch (phy_type) {
+ case RIO_PHY_SERIAL:
+ printk("serial\n");
+ break;
+ case RIO_PHY_PARALLEL:
+ printk("parallel");
+ break;
+ default:
+ printk("Unknown type %d\n", phy_type);
+ rc = -EINVAL;
+ goto err;
+ };
+ fsl_rio_info(ccsr);
+
+
+ /* Checking the port training status */
+ if (in_be32((regs_win + RIO_ESCSR)) & 1) {
+ ERR("Port is not ready. Try to restart connection...\n");
+ switch (phy_type) {
+ case RIO_PHY_SERIAL:
+ /* Disable ports */
+ out_be32(regs_win + RIO_CCSR, 0);
+ /* Set 1x lane */
+ setbits32(regs_win + RIO_CCSR, 0x02000000);
+ /* Enable ports */
+ setbits32(regs_win + RIO_CCSR, 0x00600000);
+ break;
+ case RIO_PHY_PARALLEL:
+ /* Disable ports */
+ out_be32(regs_win + RIO_CCSR, 0x22000000);
+ /* Enable ports */
+ out_be32(regs_win + RIO_CCSR, 0x44000000);
+ break;
+ }
+ if (in_be32((regs_win + RIO_ESCSR)) & 1) {
+ ERR("Port restart failed.\n");
+ rc = -ENOLINK;
+ goto err;
+ }
+ INFO("Port restart success!\n");
+ ccsr = in_be32(regs_win + RIO_CCSR);
+ fsl_rio_info(ccsr);
+ }
+
+ ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
+ ops->lcread = fsl_local_config_read;
+ ops->lcwrite = fsl_local_config_write;
+ ops->cread = fsl_rio_config_read;
+ ops->cwrite = fsl_rio_config_write;
+ ops->dsend = fsl_rio_doorbell_send;
+
+ port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
+ if (!port) {
+ ERR("Can't alloc memory for 'port'\n");
+ rc = -ENOMEM;
+ goto err;
+ }
port->id = 0;
port->index = 0;
+
+ port->sys_size = (in_be32((regs_win + RIO_PEF_CAR))
+ & RIO_PEF_CTLS) >> 4;
+ INFO("RapidIO Common Transport System size: %d\n",
+ port->sys_size ? 65536 : 256);
+
+ port->phy_type = phy_type;
+
+ priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
+ if (!priv) {
+ ERR("Can't alloc memory for 'priv'\n");
+ rc = -ENOMEM;
+ goto err;
+ }
+ port->priv = priv;
+ priv->regs_win = regs_win;
INIT_LIST_HEAD(&port->dbells);
port->iores.start = law_start;
port->iores.end = law_start + law_size;
port->iores.flags = IORESOURCE_MEM;
+ port->iores.name = "rio_io_win";
+
+ priv->bellirq = irq_of_parse_and_map(dev->node, 2);
+ priv->txirq = irq_of_parse_and_map(dev->node, 3);
+ priv->rxirq = irq_of_parse_and_map(dev->node, 4);
+ INFO("bellirq: %d, txirq: %d, rxirq %d\n", priv->bellirq,
+ priv->txirq, priv->rxirq);
rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
+
strcpy(port->name, "RIO0 mport");
port->ops = ops;
- port->host_deviceid = mpc85xx_rio_get_hdid(port->id);
+ port->mops = &fsl_mem_ops;
+ port->host_deviceid = fsl_rio_get_hdid(port->id);
rio_register_mport(port);
- regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000);
- atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET);
- maint_atmu_regs = atmu_regs + 1;
- dbell_atmu_regs = atmu_regs + 2;
- msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET);
+ priv->atmu_regs = (struct rio_atmu_regs *)(regs_win +
+ RIO_ATMU_REGS_OFFSET);
+ priv->maint_atmu_regs = priv->atmu_regs + 1;
+ priv->dbell_atmu_regs = priv->atmu_regs + 2;
+ priv->msg_regs = (struct rio_msg_regs *)(regs_win +
+ ((port->phy_type == RIO_PHY_SERIAL)
+ ? RIO_S_MSG_REGS_OFFSET
+ : RIO_P_MSG_REGS_OFFSET));
+
+ /* Set to receive any dist ID for serial RapidIO controller. */
+ if (port->phy_type == RIO_PHY_SERIAL)
+ out_be32((regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
/* Configure maintenance transaction window */
- out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000);
- out_be32((void *)&maint_atmu_regs->rowar, 0x80077015);
+ if (!rio_request_io_region(port, NULL, law_start, RIO_MAINT_WIN_SIZE,
+ "maint_win", RIO_RESOURCE_MAINT, NULL)) {
+ rc = -EPERM;
+ ERR("request maint win error!\n");
+ goto err;
+ }
+ out_be32(&priv->maint_atmu_regs->rowbar,
+ (law_start >> 12) & 0xffffff);
+ out_be32(&priv->maint_atmu_regs->rowar, 0x80077000
+ | (__ilog2(RIO_MAINT_WIN_SIZE) - 1));
- maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE);
+ priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
/* Configure outbound doorbell window */
- out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400);
- out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b);
- mpc85xx_rio_doorbell_init(port);
+ if (!rio_request_io_region(port, NULL, law_start + RIO_MAINT_WIN_SIZE,
+ RIO_DBELL_WIN_SIZE,
+ "dbell_win", RIO_RESOURCE_DOORBELL, NULL)) {
+ rc = -EPERM;
+ ERR("request doorbell win error!\n");
+ goto err;
+ }
+ out_be32(&priv->dbell_atmu_regs->rowbar, ((law_start +
+ RIO_MAINT_WIN_SIZE) >> 12) & 0xfffff);
+ out_be32(&priv->dbell_atmu_regs->rowar, 0x80042000
+ | (__ilog2(RIO_DBELL_WIN_SIZE) - 1));
+ rc = fsl_rio_doorbell_init(port, law_start + RIO_MAINT_WIN_SIZE);
+ if (rc)
+ goto err;
+
+ return 0;
+
+err:
+ if (regs_win)
+ iounmap(regs_win);
+ if (ops)
+ kfree(ops);
+ if (port)
+ kfree(port);
+ if (priv)
+ kfree(priv);
+ return rc;
+}
+
+/* The probe function for RapidIO peer-to-peer network.
+ */
+static int __devinit fsl_of_rio_rpn_probe(struct of_device *dev,
+ const struct of_device_id *match)
+{
+ int rc;
+ printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
+ dev->node->full_name);
+
+ rc = fsl_rio_setup(dev);
+ if (rc)
+ goto out;
+
+ /* Enumerate all registered ports */
+ rc = rio_init_mports();
+out:
+ return rc;
+};
+
+static struct of_device_id fsl_of_rio_rpn_ids[] = {
+ {
+ .compatible = "fsl,rapidio-delta",
+ },
+ {},
+};
+
+static struct of_platform_driver fsl_of_rio_rpn_driver = {
+ .name = "fsl-of-rio",
+ .match_table = fsl_of_rio_rpn_ids,
+ .probe = fsl_of_rio_rpn_probe,
+};
+
+static __init int fsl_of_rio_rpn_init(void)
+{
+ return of_register_platform_driver(&fsl_of_rio_rpn_driver);
}
+
+subsys_initcall(fsl_of_rio_rpn_init);
--
1.5.2
^ permalink raw reply related
* [PATCH 2/3] (Resend part #2) Add RapidIO memory mapping API and simple Bitmap allocation.
From: Zhang Wei @ 2007-12-21 10:01 UTC (permalink / raw)
To: mporter, akpm, paulus, galak; +Cc: linuxppc-dev, linux-kernel, Zhang Wei
Add RapidIO memory mapping API and simple Bitmap allocation with fixed size.
Some bugs are fixed.
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
---
drivers/rapidio/Kconfig | 18 +-
drivers/rapidio/Makefile | 1 +
drivers/rapidio/rio-access.c | 10 +-
drivers/rapidio/rio-scan.c | 53 +++--
drivers/rapidio/rio-sysfs.c | 3 +-
drivers/rapidio/rio.c | 486 ++++++++++++++++++++++++++++++++++-
drivers/rapidio/rio.h | 9 +-
drivers/rapidio/sallocator/Kconfig | 9 +
drivers/rapidio/sallocator/Makefile | 12 +
drivers/rapidio/sallocator/bitmap.c | 383 +++++++++++++++++++++++++++
10 files changed, 944 insertions(+), 40 deletions(-)
create mode 100644 drivers/rapidio/sallocator/Kconfig
create mode 100644 drivers/rapidio/sallocator/Makefile
create mode 100644 drivers/rapidio/sallocator/bitmap.c
diff --git a/drivers/rapidio/Kconfig b/drivers/rapidio/Kconfig
index 4142115..f669108 100644
--- a/drivers/rapidio/Kconfig
+++ b/drivers/rapidio/Kconfig
@@ -1,14 +1,6 @@
#
# RapidIO configuration
#
-config RAPIDIO_8_BIT_TRANSPORT
- bool "8-bit transport addressing"
- depends on RAPIDIO
- ---help---
- By default, the kernel assumes a 16-bit addressed RapidIO
- network. By selecting this option, the kernel will support
- an 8-bit addressed network.
-
config RAPIDIO_DISC_TIMEOUT
int "Discovery timeout duration (seconds)"
depends on RAPIDIO
@@ -16,3 +8,13 @@ config RAPIDIO_DISC_TIMEOUT
---help---
Amount of time a discovery node waits for a host to complete
enumeration before giving up.
+
+config RAPIDIO_PROC_FS
+ bool "I/O and Memory resource debug"
+ depends on RAPIDIO && PROC_FS
+ default y
+ ---help---
+ Enable this option, it will create a /proc/riores node for
+ monitoring the RapidIO I/O and Memory resource.
+
+source "drivers/rapidio/sallocator/Kconfig"
diff --git a/drivers/rapidio/Makefile b/drivers/rapidio/Makefile
index 7c0e181..e5b2f11 100644
--- a/drivers/rapidio/Makefile
+++ b/drivers/rapidio/Makefile
@@ -4,3 +4,4 @@
obj-y += rio.o rio-access.o rio-driver.o rio-scan.o rio-sysfs.o
obj-$(CONFIG_RAPIDIO) += switches/
+obj-$(CONFIG_RAPIDIO) += sallocator/
diff --git a/drivers/rapidio/rio-access.c b/drivers/rapidio/rio-access.c
index 8b56bbd..a3824ba 100644
--- a/drivers/rapidio/rio-access.c
+++ b/drivers/rapidio/rio-access.c
@@ -48,7 +48,7 @@ int __rio_local_read_config_##size \
u32 data = 0; \
if (RIO_##size##_BAD) return RIO_BAD_SIZE; \
spin_lock_irqsave(&rio_config_lock, flags); \
- res = mport->ops->lcread(mport->id, offset, len, &data); \
+ res = mport->ops->lcread(mport, mport->id, offset, len, &data); \
*value = (type)data; \
spin_unlock_irqrestore(&rio_config_lock, flags); \
return res; \
@@ -71,7 +71,7 @@ int __rio_local_write_config_##size \
unsigned long flags; \
if (RIO_##size##_BAD) return RIO_BAD_SIZE; \
spin_lock_irqsave(&rio_config_lock, flags); \
- res = mport->ops->lcwrite(mport->id, offset, len, value); \
+ res = mport->ops->lcwrite(mport, mport->id, offset, len, value);\
spin_unlock_irqrestore(&rio_config_lock, flags); \
return res; \
}
@@ -108,7 +108,7 @@ int rio_mport_read_config_##size \
u32 data = 0; \
if (RIO_##size##_BAD) return RIO_BAD_SIZE; \
spin_lock_irqsave(&rio_config_lock, flags); \
- res = mport->ops->cread(mport->id, destid, hopcount, offset, len, &data); \
+ res = mport->ops->cread(mport, mport->id, destid, hopcount, offset, len, &data); \
*value = (type)data; \
spin_unlock_irqrestore(&rio_config_lock, flags); \
return res; \
@@ -131,7 +131,7 @@ int rio_mport_write_config_##size \
unsigned long flags; \
if (RIO_##size##_BAD) return RIO_BAD_SIZE; \
spin_lock_irqsave(&rio_config_lock, flags); \
- res = mport->ops->cwrite(mport->id, destid, hopcount, offset, len, value); \
+ res = mport->ops->cwrite(mport, mport->id, destid, hopcount, offset, len, value); \
spin_unlock_irqrestore(&rio_config_lock, flags); \
return res; \
}
@@ -166,7 +166,7 @@ int rio_mport_send_doorbell(struct rio_mport *mport, u16 destid, u16 data)
unsigned long flags;
spin_lock_irqsave(&rio_doorbell_lock, flags);
- res = mport->ops->dsend(mport->id, destid, data);
+ res = mport->ops->dsend(mport, mport->id, destid, data);
spin_unlock_irqrestore(&rio_doorbell_lock, flags);
return res;
diff --git a/drivers/rapidio/rio-scan.c b/drivers/rapidio/rio-scan.c
index 4442072..9d52e9b 100644
--- a/drivers/rapidio/rio-scan.c
+++ b/drivers/rapidio/rio-scan.c
@@ -73,7 +73,7 @@ static u16 rio_get_device_id(struct rio_mport *port, u16 destid, u8 hopcount)
rio_mport_read_config_32(port, destid, hopcount, RIO_DID_CSR, &result);
- return RIO_GET_DID(result);
+ return RIO_GET_DID(port->sys_size, result);
}
/**
@@ -88,7 +88,7 @@ static u16 rio_get_device_id(struct rio_mport *port, u16 destid, u8 hopcount)
static void rio_set_device_id(struct rio_mport *port, u16 destid, u8 hopcount, u16 did)
{
rio_mport_write_config_32(port, destid, hopcount, RIO_DID_CSR,
- RIO_SET_DID(did));
+ RIO_SET_DID(port->sys_size, did));
}
/**
@@ -100,7 +100,8 @@ static void rio_set_device_id(struct rio_mport *port, u16 destid, u8 hopcount, u
*/
static void rio_local_set_device_id(struct rio_mport *port, u16 did)
{
- rio_local_write_config_32(port, RIO_DID_CSR, RIO_SET_DID(did));
+ rio_local_write_config_32(port, RIO_DID_CSR, RIO_SET_DID(port->sys_size,
+ did));
}
/**
@@ -350,8 +351,17 @@ static struct rio_dev *rio_setup_device(struct rio_net *net,
rswitch->switchid = next_switchid;
rswitch->hopcount = hopcount;
rswitch->destid = destid;
+ if (!(rswitch->route_table = kzalloc(sizeof(u16)*
+ RIO_MAX_ROUTE_ENTRIES(port->sys_size),
+ GFP_KERNEL))) {
+ kfree(rdev);
+ rdev = NULL;
+ kfree(rswitch);
+ goto out;
+ }
/* Initialize switch route table */
- for (rdid = 0; rdid < RIO_MAX_ROUTE_ENTRIES; rdid++)
+ for (rdid = 0; rdid < RIO_MAX_ROUTE_ENTRIES(port->sys_size);
+ rdid++)
rswitch->route_table[rdid] = RIO_INVALID_ROUTE;
rdev->rswitch = rswitch;
sprintf(rio_name(rdev), "%02x:s:%04x", rdev->net->id,
@@ -480,7 +490,7 @@ static u16 rio_get_host_deviceid_lock(struct rio_mport *port, u8 hopcount)
{
u32 result;
- rio_mport_read_config_32(port, RIO_ANY_DESTID, hopcount,
+ rio_mport_read_config_32(port, RIO_ANY_DESTID(port->sys_size), hopcount,
RIO_HOST_DID_LOCK_CSR, &result);
return (u16) (result & 0xffff);
@@ -571,14 +581,16 @@ static int rio_enum_peer(struct rio_net *net, struct rio_mport *port,
}
/* Attempt to acquire device lock */
- rio_mport_write_config_32(port, RIO_ANY_DESTID, hopcount,
+ rio_mport_write_config_32(port, RIO_ANY_DESTID(port->sys_size),
+ hopcount,
RIO_HOST_DID_LOCK_CSR, port->host_deviceid);
while ((tmp = rio_get_host_deviceid_lock(port, hopcount))
< port->host_deviceid) {
/* Delay a bit */
mdelay(1);
/* Attempt to acquire device lock again */
- rio_mport_write_config_32(port, RIO_ANY_DESTID, hopcount,
+ rio_mport_write_config_32(port, RIO_ANY_DESTID(port->sys_size),
+ hopcount,
RIO_HOST_DID_LOCK_CSR,
port->host_deviceid);
}
@@ -590,7 +602,8 @@ static int rio_enum_peer(struct rio_net *net, struct rio_mport *port,
}
/* Setup new RIO device */
- if ((rdev = rio_setup_device(net, port, RIO_ANY_DESTID, hopcount, 1))) {
+ if ((rdev = rio_setup_device(net, port, RIO_ANY_DESTID(port->sys_size),
+ hopcount, 1))) {
/* Add device to the global and bus/net specific list. */
list_add_tail(&rdev->net_list, &net->devices);
} else
@@ -598,7 +611,8 @@ static int rio_enum_peer(struct rio_net *net, struct rio_mport *port,
if (rio_is_switch(rdev)) {
next_switchid++;
- sw_inport = rio_get_swpinfo_inport(port, RIO_ANY_DESTID, hopcount);
+ sw_inport = rio_get_swpinfo_inport(port,
+ RIO_ANY_DESTID(port->sys_size), hopcount);
rio_route_add_entry(port, rdev->rswitch, RIO_GLOBAL_TABLE,
port->host_deviceid, sw_inport);
rdev->rswitch->route_table[port->host_deviceid] = sw_inport;
@@ -612,7 +626,8 @@ static int rio_enum_peer(struct rio_net *net, struct rio_mport *port,
}
num_ports =
- rio_get_swpinfo_tports(port, RIO_ANY_DESTID, hopcount);
+ rio_get_swpinfo_tports(port, RIO_ANY_DESTID(port->sys_size),
+ hopcount);
pr_debug(
"RIO: found %s (vid %4.4x did %4.4x) with %d ports\n",
rio_name(rdev), rdev->vid, rdev->did, num_ports);
@@ -624,13 +639,15 @@ static int rio_enum_peer(struct rio_net *net, struct rio_mport *port,
cur_destid = next_destid;
if (rio_sport_is_active
- (port, RIO_ANY_DESTID, hopcount, port_num)) {
+ (port, RIO_ANY_DESTID(port->sys_size), hopcount,
+ port_num)) {
pr_debug(
"RIO: scanning device on port %d\n",
port_num);
rio_route_add_entry(port, rdev->rswitch,
RIO_GLOBAL_TABLE,
- RIO_ANY_DESTID, port_num);
+ RIO_ANY_DESTID(port->sys_size),
+ port_num);
if (rio_enum_peer(net, port, hopcount + 1) < 0)
return -1;
@@ -735,7 +752,8 @@ rio_disc_peer(struct rio_net *net, struct rio_mport *port, u16 destid,
pr_debug(
"RIO: scanning device on port %d\n",
port_num);
- for (ndestid = 0; ndestid < RIO_ANY_DESTID;
+ for (ndestid = 0;
+ ndestid < RIO_ANY_DESTID(port->sys_size);
ndestid++) {
rio_route_get_entry(port, rdev->rswitch,
RIO_GLOBAL_TABLE,
@@ -796,7 +814,7 @@ static int rio_mport_is_active(struct rio_mport *port)
* network list of associated master ports. Returns a
* RIO network pointer on success or %NULL on failure.
*/
-static struct rio_net __devinit *rio_alloc_net(struct rio_mport *port)
+static struct rio_net *rio_alloc_net(struct rio_mport *port)
{
struct rio_net *net;
@@ -917,7 +935,9 @@ static void rio_build_route_tables(void)
list_for_each_entry(rdev, &rio_devices, global_list)
if (rio_is_switch(rdev))
- for (i = 0; i < RIO_MAX_ROUTE_ENTRIES; i++) {
+ for (i = 0;
+ i < RIO_MAX_ROUTE_ENTRIES(rdev->net->hport->sys_size);
+ i++) {
if (rio_route_get_entry
(rdev->net->hport, rdev->rswitch, RIO_GLOBAL_TABLE,
i, &sport) < 0)
@@ -981,7 +1001,8 @@ int rio_disc_mport(struct rio_mport *mport)
del_timer_sync(&rio_enum_timer);
pr_debug("done\n");
- if (rio_disc_peer(net, mport, RIO_ANY_DESTID, 0) < 0) {
+ if (rio_disc_peer(net, mport, RIO_ANY_DESTID(mport->sys_size),
+ 0) < 0) {
printk(KERN_INFO
"RIO: master port %d device has failed discovery\n",
mport->id);
diff --git a/drivers/rapidio/rio-sysfs.c b/drivers/rapidio/rio-sysfs.c
index 659e311..97a147f 100644
--- a/drivers/rapidio/rio-sysfs.c
+++ b/drivers/rapidio/rio-sysfs.c
@@ -43,7 +43,8 @@ static ssize_t routes_show(struct device *dev, struct device_attribute *attr, ch
if (!rdev->rswitch)
goto out;
- for (i = 0; i < RIO_MAX_ROUTE_ENTRIES; i++) {
+ for (i = 0; i < RIO_MAX_ROUTE_ENTRIES(rdev->net->hport->sys_size);
+ i++) {
if (rdev->rswitch->route_table[i] == RIO_INVALID_ROUTE)
continue;
str +=
diff --git a/drivers/rapidio/rio.c b/drivers/rapidio/rio.c
index f644807..c3b3c7e 100644
--- a/drivers/rapidio/rio.c
+++ b/drivers/rapidio/rio.c
@@ -2,9 +2,16 @@
* RapidIO interconnect services
* (RapidIO Interconnect Specification, http://www.rapidio.org)
*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Author: Zhang Wei, wei.zhang@freescale.com, Jun 2007
+ *
* Copyright 2005 MontaVista Software, Inc.
* Matt Porter <mporter@kernel.crashing.org>
*
+ * Changelog:
+ * Jun 2007 Zhang Wei <wei.zhang@freescale.com>
+ * - Add memory mapping support.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
@@ -23,10 +30,22 @@
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/dma-mapping.h>
+#include <linux/hardirq.h>
#include "rio.h"
+#define ERR(fmt, arg...) \
+ printk(KERN_ERR "%s:%s: " fmt, __FILE__, __FUNCTION__, ## arg)
+
static LIST_HEAD(rio_mports);
+static LIST_HEAD(rio_inb_mems);
+static LIST_HEAD(rio_outb_mems);
+
+static DEFINE_SPINLOCK(rio_config_lock);
/**
* rio_local_get_device_id - Get the base/extended device id for a port
@@ -42,7 +61,7 @@ u16 rio_local_get_device_id(struct rio_mport *port)
rio_local_read_config_32(port, RIO_DID_CSR, &result);
- return (RIO_GET_DID(result));
+ return (RIO_GET_DID(port->sys_size, result));
}
/**
@@ -332,6 +351,350 @@ int rio_release_outb_dbell(struct rio_dev *rdev, struct resource *res)
}
/**
+ * rio_request_io_region -- request resource in RapidIO IO region
+ * @mport: Master port
+ * @devid: Device specific pointer to pass
+ * @start: IO resource start address
+ * @size: IO resource size
+ * @name: Resource name
+ * @flag: Flag for resource
+ * @res: Return resource which has been allocated. If res == NULL,
+ * the function will alloc the memory for return resource.
+ *
+ * Return: The resource which has been allocated.
+ */
+struct resource *rio_request_io_region(struct rio_mport *mport, void *devid,
+ resource_size_t start, resource_size_t size,
+ const char *name, unsigned long flags,
+ struct resource *res)
+{
+ if (!res && !(res = kmalloc(sizeof(struct resource), GFP_KERNEL))) {
+ ERR("No free memory for res alloc!\n");
+ goto err;
+ }
+ memset(res, 0, sizeof(struct resource));
+ size = (size < 0x1000) ? 0x1000 : 1 << (__ilog2(size - 1) + 1);
+
+ /* if start == 0 then auto locate the start address */
+ if (!start) {
+ if (allocate_resource(&mport->iores, res, size,
+ mport->iores.start, mport->iores.end,
+ size, NULL, NULL) < 0) {
+ ERR("allocte resource error!\n");
+ goto err;
+ }
+ res->name = name;
+ res->flags = flags;
+ } else {
+ rio_init_io_res(res, start, start + size - 1, name, flags);
+ if (request_resource(&mport->iores, res) < 0) {
+ ERR("Can't get SRIO IO resource!\n");
+ goto err;
+ }
+ }
+ return res;
+
+err:
+ if (res)
+ kfree(res);
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(rio_request_io_region);
+
+/**
+ * rio_map_inb_region -- Mapping inbound memory region.
+ * @mport: Master port.
+ * @mem: Memory struction for mapping.
+ * @rflags: Flags for mapping.
+ *
+ * Return: 0 -- Success.
+ *
+ * This function will create the mapping from the mem->riores to mem->iores.
+ */
+int rio_map_inb_region(struct rio_mport *mport, struct rio_mem *mem, u32 rflags)
+{
+ int rc = 0;
+ unsigned long flags;
+
+ if (!mport->mops)
+ return -1;
+ spin_lock_irqsave(&rio_config_lock, flags);
+ rc = mport->mops->map_inb(mport, mem->iores.start, mem->riores.start, mem->size, rflags);
+ spin_unlock_irqrestore(&rio_config_lock, flags);
+ return rc;
+}
+
+/**
+ * rio_map_outb_region -- Mapping outbound memory region.
+ * @mport: Master port.
+ * @tid: Target RapidIO device id.
+ * @mem: Memory struction for mapping.
+ * @rflags: Flags for mapping.
+ *
+ * Return: 0 -- Success.
+ *
+ * This function will create the mapping from the mem->iores to mem->riores.
+ */
+int rio_map_outb_region(struct rio_mport *mport, u16 tid,
+ struct rio_mem *mem, u32 rflags)
+{
+ int rc = 0;
+ unsigned long flags;
+
+ if (!mport->mops)
+ return -1;
+ spin_lock_irqsave(&rio_config_lock, flags);
+ rc = mport->mops->map_outb(mport, mem->iores.start, mem->riores.start, mem->size, tid, rflags);
+ spin_unlock_irqrestore(&rio_config_lock, flags);
+ return rc;
+}
+
+/**
+ * rio_unmap_inb_region -- Unmap the inbound memory region
+ * @mport: Master port
+ * @mem: Memory struction for unmapping.
+ */
+void rio_unmap_inb_region(struct rio_mport *mport, struct rio_mem *mem)
+{
+ unsigned long flags;
+ if (!mport->mops)
+ return;
+ spin_lock_irqsave(&rio_config_lock, flags);
+ mport->mops->unmap_inb(mport, mem->iores.start);
+ spin_unlock_irqrestore(&rio_config_lock, flags);
+}
+
+/**
+ * rio_unmap_outb_region -- Unmap the outbound memory region
+ * @mport: Master port
+ * @mem: Memory struction for unmapping.
+ */
+void rio_unmap_outb_region(struct rio_mport *mport, struct rio_mem *mem)
+{
+ unsigned long flags;
+ if (!mport->mops)
+ return;
+ spin_lock_irqsave(&rio_config_lock, flags);
+ mport->mops->unmap_outb(mport, mem->iores.start);
+ spin_unlock_irqrestore(&rio_config_lock, flags);
+}
+
+/**
+ * rio_release_inb_region -- Release the inbound region resource.
+ * @mport: Master port
+ * @mem: Inbound region descriptor
+ *
+ * Return 0 is successed.
+ */
+int rio_release_inb_region(struct rio_mport *mport, struct rio_mem *mem)
+{
+ int rc = 0;
+ if (!mem)
+ return rc;
+ rio_unmap_inb_region(mport, mem);
+ if (mem->virt)
+ dma_free_coherent(NULL, mem->size, mem->virt, mem->iores.start);
+
+ if (mem->iores.parent)
+ rc = release_resource(&mem->iores);
+ if (mem->riores.parent && !rc)
+ rc = release_resource(&mem->riores);
+
+ if (mem->node.prev)
+ list_del(&mem->node);
+
+ kfree(mem);
+
+ return rc;
+}
+
+/**
+ * rio_request_inb_region -- Request inbound memory region
+ * @mport: Master port
+ * @dev_id: Device specific pointer to pass
+ * @size: The request memory windows size
+ * @name: The region name
+ * @owner: The region owner driver id
+ *
+ * Retrun: The rio_mem struction for inbound memory descriptor.
+ *
+ * This function is used for request RapidIO space inbound region. If the size
+ * less than 4096 or not aligned to 2^N, it will be adjusted. The function will
+ * alloc a block of local DMA memory of the size for inbound region target and
+ * request a RapidIO region for inbound region source. Then the inbound region
+ * will be claimed in RapidIO space and the local DMA memory will be added to
+ * local inbound memory list. The rio_mem with the inbound relationship will
+ * be returned.
+ */
+struct rio_mem *rio_request_inb_region(struct rio_mport *mport, void *dev_id,
+ resource_size_t size, const char *name, u32 owner)
+{
+ struct rio_mem *rmem = NULL;
+ int ret;
+
+ rmem = kzalloc(sizeof(struct rio_mem), GFP_KERNEL);
+ if (!rmem)
+ goto err;
+
+ /* Align the size to 2^N */
+ size = (size < 0x1000) ? 0x1000 : 1 << (__ilog2(size - 1) + 1);
+
+ /* Alloc the RapidIO space */
+ ret = rio_space_request(mport, size, &rmem->riores);
+ if (ret) {
+ printk(KERN_ERR "RIO space request error! ret = %d\n", ret);
+ goto err;
+ }
+
+ rmem->riores.name = name;
+ rmem->size = rmem->riores.end - rmem->riores.start + 1;
+
+ /* Initialize inbound memory */
+ if (!(rmem->virt = dma_alloc_coherent(NULL, rmem->size,
+ &rmem->iores.start, GFP_KERNEL))) {
+ ERR("Inbound memory alloc error\n");
+ goto err;
+ }
+ rmem->iores.end = rmem->iores.start + rmem->size - 1;
+ rmem->owner = owner;
+
+ /* Map RIO space to local DMA memory */
+ if ((ret = rio_map_inb_region(mport, rmem, 0))) {
+ printk(KERN_ERR "RIO map inbound mem error, ret = %d\n", ret);
+ goto err;
+ }
+
+ /* Claim the region */
+ if ((ret = rio_space_claim(rmem))) {
+ printk(KERN_ERR "RIO inbound mem claim error, ret = %d\n", ret);
+ goto err;
+ }
+ list_add(&rmem->node, &rio_inb_mems);
+
+ return rmem;
+
+err:
+ rio_release_inb_region(mport, rmem);
+ return NULL;
+}
+
+/**
+ * rio_release_outb_region -- Release the outbound region resource.
+ * @mport: Master port
+ * @mem: Outbound region descriptor
+ *
+ * Return 0 is successed.
+ */
+int rio_release_outb_region(struct rio_mport *mport, struct rio_mem *mem)
+{
+ int rc = 0;
+ if (!mem)
+ return rc;
+ rio_unmap_outb_region(mport, mem);
+ rio_space_release(mem);
+ if (mem->virt)
+ iounmap(mem->virt);
+
+ if (mem->iores.parent)
+ rc = release_resource(&mem->iores);
+ if (mem->riores.parent && !rc)
+ rc = release_resource(&mem->riores);
+
+ if (mem->node.prev)
+ list_del(&mem->node);
+
+ kfree(mem);
+
+ return rc;
+}
+
+/** rio_prepare_io_mem -- Prepare IO region for RapidIO outbound mapping
+ * @mport: Master port
+ * @dev: RIO device specific pointer to pass
+ * @size: Request IO size
+ * @name: The request IO resource name
+ *
+ * Return: The rio_mem descriptor with IO region resource.
+ *
+ * This function request IO region firstly and ioremap it for preparing
+ * outbound window mapping. The function do not map the outbound region
+ * because ioremap can not located at the interrupt action function.
+ * The function can be called in the initialization for just prepared.
+ */
+struct rio_mem *rio_prepare_io_mem(struct rio_mport *mport,
+ struct rio_dev *dev, resource_size_t size, const char *name)
+{
+ struct rio_mem *rmem = NULL;
+
+ rmem = kzalloc(sizeof(struct rio_mem), GFP_KERNEL);
+ if (!rmem)
+ goto err;
+
+ /* Align the size to 2^N */
+ size = (size < 0x1000) ? 0x1000 : 1 << (__ilog2(size - 1) + 1);
+
+ /* Request RapidIO IO region */
+ if (!(rio_request_io_region(mport, dev, 0, size,
+ name, RIO_RESOURCE_MEM, &rmem->iores))) {
+ ERR("RIO io region request error!\n");
+ goto err;
+ }
+
+ rmem->virt = ioremap((phys_addr_t)(rmem->iores.start), size);
+ rmem->size = size;
+
+ list_add(&rmem->node, &rio_outb_mems);
+ return rmem;
+err:
+ rio_release_outb_region(mport, rmem);
+ return NULL;
+}
+
+/** rio_request_outb_region -- Request IO region and get outbound region
+ * for RapidIO outbound mapping
+ * @mport: Master port
+ * @dev_id: RIO device specific pointer to pass
+ * @size: Request IO size
+ * @name: The request IO resource name
+ * @owner: The outbound region owned driver
+ *
+ * Return: The rio_mem descriptor with IO region resource.
+ *
+ * This function request IO region firstly and ioremap it for preparing
+ * outbound window mapping. And it will find the RapidIO region owned by
+ * the driver id. Then map it. Be careful about that the ioremap can not
+ * be called in the interrupt event action function.
+ */
+struct rio_mem *rio_request_outb_region(struct rio_mport *mport, void *dev_id,
+ resource_size_t size, const char *name, u32 owner)
+{
+ struct rio_mem *rmem = NULL;
+ struct rio_dev *dev = dev_id;
+
+ if (!dev)
+ goto err;
+
+ rmem = rio_prepare_io_mem(mport, dev, size, name);
+ if (!rmem)
+ goto err;
+
+ if (rio_space_find_mem(mport, dev->destid, owner, &rmem->riores)) {
+ ERR("Can not find RIO region meet the ownerid %x\n", owner);
+ goto err;
+ }
+
+ /* Map the rio space to local */
+ if (rio_map_outb_region(mport, dev->destid, rmem, 0)) {
+ ERR("RIO map outb error!\n");
+ goto err;
+ }
+ return rmem;
+err:
+ rio_release_outb_region(mport, rmem);
+ return NULL;
+}
+
+/**
* rio_mport_get_feature - query for devices' extended features
* @port: Master port to issue transaction
* @local: Indicate a local master port or remote device access
@@ -476,8 +839,8 @@ int rio_init_mports(void)
port->iores.end - port->iores.start,
port->name)) {
printk(KERN_ERR
- "RIO: Error requesting master port region %8.8lx-%8.8lx\n",
- port->iores.start, port->iores.end - 1);
+ "RIO: Error requesting master port region %016llx-%016llx\n",
+ (u64)port->iores.start, (u64)port->iores.end - 1);
rc = -ENOMEM;
goto out;
}
@@ -486,6 +849,7 @@ int rio_init_mports(void)
rio_enum_mport(port);
else
rio_disc_mport(port);
+ rio_space_init(port);
}
out:
@@ -508,3 +872,119 @@ EXPORT_SYMBOL_GPL(rio_request_inb_mbox);
EXPORT_SYMBOL_GPL(rio_release_inb_mbox);
EXPORT_SYMBOL_GPL(rio_request_outb_mbox);
EXPORT_SYMBOL_GPL(rio_release_outb_mbox);
+
+#ifdef CONFIG_RAPIDIO_PROC_FS
+enum { MAX_IORES_LEVEL = 5 };
+
+struct riors {
+ struct rio_mport *mp;
+ int res;
+ struct resource *p;
+} riomres;
+
+static void *r_next(struct seq_file *m, void *v, loff_t *pos)
+{
+ struct resource *p = v;
+ struct riors *rs = m->private;
+
+ (*pos)++;
+ if (p->child)
+ return p->child;
+ while (!p->sibling && p->parent)
+ p = p->parent;
+ if (p->sibling)
+ return p->sibling;
+ else {
+ rs->res++;
+ if(rs->res >= RIO_MAX_MPORT_RESOURCES) {
+ rs->mp = list_entry(rs->mp->node.next, struct rio_mport, node);
+ rs->res = 0;
+ if (&rs->mp->node == &rio_mports)
+ return NULL;
+ }
+ seq_printf(m, "%2d: ", rs->res);
+ rs->p = &rs->mp->riores[rs->res];
+ p = rs->p;
+
+ return p;
+ }
+}
+
+static void *r_start(struct seq_file *m, loff_t *pos)
+{
+ struct riors *rs = m->private;
+ struct resource *p;
+
+ if (*pos) {
+ *pos = 0;
+ return NULL;
+ }
+
+ rs->mp = list_entry(rio_mports.next, struct rio_mport, node);
+ rs->res = -1;
+ rs->p = &rs->mp->iores;
+ p = rs->p;
+
+ seq_printf(m, "IO: ");
+
+ return p;
+}
+
+static void r_stop(struct seq_file *m, void *v)
+{
+}
+
+static int r_show(struct seq_file *m, void *v)
+{
+ struct riors *rs = m->private;
+ struct resource *root = rs->p;
+ struct resource *r = v, *p;
+ int width = root->end < 0x10000 ? 4 : 8;
+ int depth;
+
+ for (depth = 0, p = r; p->parent && depth < MAX_IORES_LEVEL; depth++, p = p->parent)
+ if (p == root)
+ break;
+ seq_printf(m, "%*s%0*llx-%0*llx : %s\n",
+ depth * 2, "",
+ width, (unsigned long long) r->start,
+ width, (unsigned long long) r->end,
+ r->name ? r->name : "<BAD>");
+ return 0;
+}
+
+static const struct seq_operations resource_op = {
+ .start = r_start,
+ .next = r_next,
+ .stop = r_stop,
+ .show = r_show,
+};
+
+static int riores_open(struct inode *inode, struct file *file)
+{
+ int res = seq_open(file, &resource_op);
+ if (!res) {
+ struct seq_file *m = file->private_data;
+ m->private = &riomres;
+ }
+ return res;
+}
+
+static const struct file_operations proc_riores_operations = {
+ .open = riores_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = seq_release,
+};
+
+static int __init rioresources_init(void)
+{
+ struct proc_dir_entry *entry;
+
+ entry = create_proc_entry("riores", 0, NULL);
+ if (entry)
+ entry->proc_fops = &proc_riores_operations;
+ return 0;
+}
+__initcall(rioresources_init);
+#endif
diff --git a/drivers/rapidio/rio.h b/drivers/rapidio/rio.h
index b242cee..7a3b62e 100644
--- a/drivers/rapidio/rio.h
+++ b/drivers/rapidio/rio.h
@@ -51,10 +51,5 @@ extern struct rio_route_ops __end_rio_route_ops[];
DECLARE_RIO_ROUTE_SECTION(.rio_route_ops, \
vid, did, add_hook, get_hook)
-#ifdef CONFIG_RAPIDIO_8_BIT_TRANSPORT
-#define RIO_GET_DID(x) ((x & 0x00ff0000) >> 16)
-#define RIO_SET_DID(x) ((x & 0x000000ff) << 16)
-#else
-#define RIO_GET_DID(x) (x & 0xffff)
-#define RIO_SET_DID(x) (x & 0xffff)
-#endif
+#define RIO_GET_DID(size, x) (size ? (x & 0xffff) : ((x & 0x00ff0000) >> 16))
+#define RIO_SET_DID(size, x) (size ? (x & 0xffff) : ((x & 0x000000ff) << 16))
diff --git a/drivers/rapidio/sallocator/Kconfig b/drivers/rapidio/sallocator/Kconfig
new file mode 100644
index 0000000..a33a1b8
--- /dev/null
+++ b/drivers/rapidio/sallocator/Kconfig
@@ -0,0 +1,9 @@
+choice
+ prompt "Default RapidIO Space Allocator"
+ depends on RAPIDIO
+ default RIO_SA_DEFAULT_BITMAP
+
+ config RIO_SA_DEFAULT_BITMAP
+ bool "Bitmap"
+
+endchoice
diff --git a/drivers/rapidio/sallocator/Makefile b/drivers/rapidio/sallocator/Makefile
new file mode 100644
index 0000000..437201c
--- /dev/null
+++ b/drivers/rapidio/sallocator/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+#
+# Author: Zhang Wei, wei.zhang@freescale.com, Jun 2007
+#
+# This is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+
+obj-$(CONFIG_RIO_SA_DEFAULT_BITMAP) += bitmap.o
diff --git a/drivers/rapidio/sallocator/bitmap.c b/drivers/rapidio/sallocator/bitmap.c
new file mode 100644
index 0000000..d10bbf9
--- /dev/null
+++ b/drivers/rapidio/sallocator/bitmap.c
@@ -0,0 +1,383 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ * Author: Zhang Wei, wei.zhang@freescale.com, Jun 2007
+ *
+ * Description:
+ * RapidIO space allocator bitmap arithmetic.
+ * The Bitmap allocator make the whole RapidIO device have the same fixed
+ * inbound memory window. And on the top of each device inbound window,
+ * there is a sect0 area, which will use for recording the individual
+ * driver owned memory space in device.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/rio.h>
+#include <linux/rio_drv.h>
+#include <linux/rio_ids.h>
+#include <linux/rio_regs.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <linux/fs.h>
+#include <linux/proc_fs.h>
+#include <linux/dma-mapping.h>
+
+#include "../rio.h"
+
+#undef DEBUG
+
+#define RIO_SBLOCK_SIZE 4096
+
+#define ERR(fmt, arg...) \
+ printk(KERN_ERR "ERROR %s - %s: " fmt, __FILE__, __FUNCTION__, ## arg)
+#ifdef DEBUG
+#define DBG(fmt...) printk(fmt)
+#else
+#define DBG(fmt...) do {} while (0)
+#endif
+
+#define IS_64BIT_RES ((sizeof(resource_size_t) == 8) ? 1 : 0)
+#define SA_BITMAP_DRV_ID 0x4249544d
+#define SA_RIO_RESERVE_SPACE 0x4000000
+
+/* Definition for struct rio_res:ctrl */
+#define SA_RIO_RES_CTRL_EN 0x80000000
+struct rio_res {
+ u32 ctrl; /* Control words
+ * Bit 31: Enable bit.
+ */
+ u32 addr; /* The start addr bits [0-31] of RapidIO window */
+ u32 extaddr; /* The start addr bits [32-63] of RapidIO window */
+ u32 size; /* The size bits [0-31] of RapidIO window */
+ u32 extsize; /* The size bits [32-63] of RapidIO window */
+ u32 owner; /* The owner driver id */
+ u32 rev[2]; /* For align 32 bytes */
+};
+
+#define SA_BITMAP_MAX_INB_RES 32
+struct rio_sect0 {
+ u32 id; /* ID for Bitmap space allocater driver */
+ u32 rioid; /* RapidIO device id */
+ u32 width; /* The resource width for RIO space, 32 or 64 */
+ u8 rev1[56]; /* Align to 64 bytes */
+ struct rio_res inb_res[SA_BITMAP_MAX_INB_RES];
+ u8 rev2[4096 - 64 - SA_BITMAP_MAX_INB_RES * 32];
+ /* Fill for 4096 bytes */
+};
+
+/* if select 64bit resource, we can use 34-bit rio address, otherwise 32-bit */
+static int rio_addr_size;
+static struct resource *root;
+static struct rio_mem sect0mem; /* Sect 0 memory data */
+static struct rio_sect0 *sect0 = NULL;
+static struct rio_mem *sblock_buf = NULL;
+
+/**
+ * get_rio_addr_size -- get the RapidIO space address size.
+ *
+ * If it's a 64-bit system, the RapidIO space address size could be 34bit,
+ * otherwise, it should be 32 bit.
+ */
+static inline int get_rio_addr_size(void)
+{
+ return (sizeof(resource_size_t) == 8) ? 34 : 32;
+}
+
+/**
+ * rio_space_request -- request RapidIO space.
+ * @mport: RIO master port.
+ * @size: The request space size, must >= 4096.
+ * @new: The resource which required.
+ *
+ * Return:
+ * 0 -- Success
+ * -EINVAL -- size is wrong (<4096)
+ * -EFAULT -- new is NULL
+ * others -- return from allocate_resource()
+ *
+ * This function request a memory from RapidIO space.
+ */
+int rio_space_request(struct rio_mport *mport, resource_size_t size,
+ struct resource *new)
+{
+ int ret = 0;
+
+ /* Align the size to 2^N */
+ size = (size < 0x1000) ? 0x1000 : 1 << (__ilog2(size - 1) + 1);
+
+ memset(new, 0, sizeof(struct resource));
+
+ ret = allocate_resource(root, new, size, root->start, root->end,
+ size, NULL, 0);
+ if (ret) {
+ ERR("No more resource for size 0x%08x!\n", size);
+ goto out;
+ }
+
+out:
+ return ret;
+}
+
+#ifdef DEBUG
+/**
+ * rio_sa_dump_sect0 -- Dump the sect0 content.
+ * @psect0: The point of sect0
+ */
+static void rio_sa_dump_sect0(struct rio_sect0 *psect0)
+{
+ int i;
+
+ if (!psect0)
+ return;
+
+ printk("Rio Sect0 %p dump:\n", psect0);
+ printk("...id = 0x%08x, width = %d, rioid = %d \n",
+ psect0->id, psect0->width, psect0->rioid);
+ for (i = 0; i < SA_BITMAP_MAX_INB_RES; i++)
+ if (psect0->inb_res[i].ctrl & SA_RIO_RES_CTRL_EN)
+ printk("...inb_res[%d]: ctrl 0x%08x, owner 0x%08x\n"
+ "\t\textaddr 0x%08x, addr 0x%08x\n"
+ "\t\textsize 0x%08x, size 0x%08x\n", i,
+ psect0->inb_res[i].ctrl,
+ psect0->inb_res[i].owner,
+ psect0->inb_res[i].extaddr,
+ psect0->inb_res[i].addr,
+ psect0->inb_res[i].extsize,
+ psect0->inb_res[i].size);
+}
+#endif
+
+/**
+ * rio_space_claim -- Claim the memory in RapidIO space
+ * @mem: The memory should be claimed.
+ *
+ * When you get a memory space and get ready of it, you should claim it in
+ * RapidIO space. Then, the other device could get the memory by calling
+ * rio_space_find_mem().
+ */
+int rio_space_claim(struct rio_mem *mem)
+{
+ int i;
+
+ if (!sect0) {
+ ERR("Sect0 is NULL!\n");
+ return -EINVAL;
+ }
+#ifdef DEBUG
+ rio_sa_dump_sect0(sect0);
+#endif
+
+ for (i = 0; i < SA_BITMAP_MAX_INB_RES; i++)
+ if (!(sect0->inb_res[i].ctrl & SA_RIO_RES_CTRL_EN)) {
+ sect0->inb_res[i].ctrl |= SA_RIO_RES_CTRL_EN;
+ sect0->inb_res[i].addr = (u32)(mem->riores.start);
+ sect0->inb_res[i].size = (u32)(mem->riores.end
+ - mem->riores.start + 1);
+ if (IS_64BIT_RES) {
+ sect0->inb_res[i].extaddr =
+ (u64)mem->riores.start >> 32;
+ sect0->inb_res[i].extsize =
+ (u64)(mem->riores.end
+ - mem->riores.start + 1) >> 32;
+ }
+ sect0->inb_res[i].owner = mem->owner;
+ DBG("The new inbound rio mem added:\n");
+ DBG("...inb_res[%d]: ctrl 0x%08x, owner 0x%08x\n"
+ "\t\textaddr 0x%08x, addr 0x%08x\n"
+ "\t\textsize 0x%08x, size 0x%08x\n", i,
+ sect0->inb_res[i].ctrl,
+ sect0->inb_res[i].owner,
+ sect0->inb_res[i].extaddr,
+ sect0->inb_res[i].addr,
+ sect0->inb_res[i].extsize,
+ sect0->inb_res[i].size);
+ return 0;
+ }
+
+ ERR("No free inbound window!\n");
+ return -EBUSY;
+}
+
+/**
+ * rio_space_release -- remove the memory record from RapidIO space.
+ * It's the pair function of rio_space_claim().
+ *
+ * @inbmem: The memory should be release.
+ */
+void rio_space_release(struct rio_mem *inbmem)
+{
+ int i;
+
+ /* Remove it from sect0 inb_res array */
+ for (i = 0; i < SA_BITMAP_MAX_INB_RES; i++)
+ if ((sect0->inb_res[i].ctrl & SA_RIO_RES_CTRL_EN) &&
+ (((u64)sect0->inb_res[i].extaddr << 32 |
+ sect0->inb_res[i].addr)
+ == (u64)inbmem->riores.start)) {
+ sect0->inb_res[i].ctrl = 0;
+ sect0->inb_res[i].addr = 0;
+ sect0->inb_res[i].extaddr = 0;
+ sect0->inb_res[i].size = 0;
+ sect0->inb_res[i].extsize = 0;
+ }
+}
+
+/**
+ * rio_space_get_dev_mem -- get the whole owned inbound space of
+ * RapidIO device with did.
+ */
+static struct resource *rio_space_get_dev_mem(struct rio_mport *mport,
+ u16 did, struct resource *res)
+{
+ if(!res && !(res = kmalloc(sizeof(struct resource), GFP_KERNEL))) {
+ ERR("resource alloc error!\n");
+ return NULL;
+ }
+ memset(res, 0, sizeof(struct resource));
+
+ res->start = SA_RIO_RESERVE_SPACE + (did
+ << (rio_addr_size - __ilog2(RIO_ANY_DESTID(mport->sys_size)
+ + 1)));
+ res->end = res->start +
+ (1 << (rio_addr_size - __ilog2(RIO_ANY_DESTID(mport->sys_size)
+ + 1))) - 1;
+ res->flags = RIO_RESOURCE_MEM;
+
+ return res;
+}
+
+/**
+ * rio_space_find_mem -- Find the memory space (RIO) of the rio driver owned.
+ * @mport: RIO master port.
+ * @tid: The target RapidIO device id which will be searched.
+ * @owner: The driver id as the search keyword.
+ * @res: The result of finding.
+ *
+ * return:
+ * 0 -- Success
+ * -EFAULT -- Remote sect0 is a bad address
+ * -EPROTONOSUPPORT -- The remote space allocator protocol is not support
+ *
+ * This function will find the memory located in RapidIO space, which is owned
+ * by the driver. If the remote RapidIO device use the diffrent space allocator,
+ * it will return -EPROTONOSUPPORT.
+ */
+int rio_space_find_mem(struct rio_mport *mport, u16 tid,
+ u32 owner, struct resource *res)
+{
+ volatile struct rio_sect0 __iomem *rsect0;
+ int i;
+ int ret = 0;
+ u32 width;
+
+ rio_space_get_dev_mem(mport, tid, &sblock_buf->riores);
+ sblock_buf->size = RIO_SBLOCK_SIZE;
+ rio_map_outb_region(mport, tid, sblock_buf, 0);
+
+ if (!sblock_buf->virt) {
+ ERR("Sect0 block buffer is NULL!\n");
+ ret = -EFAULT;
+ goto out;
+ }
+ rsect0 = sblock_buf->virt;
+
+ if (in_be32(&rsect0->id) != SA_BITMAP_DRV_ID) {
+ DBG("The target RapidIO space allocator is not rio_sa_bitmap! "
+ "id = 0x%x\n", rsect0->id);
+ ret = -EPROTONOSUPPORT;
+ goto out;
+ }
+
+#ifdef DEBUG
+ /* Dump remote sect0 for debug */
+ DBG("Dump the remote RIO dev %d sect0\n", tid);
+ rio_sa_dump_sect0(rsect0);
+#endif
+
+ width = in_be32(&rsect0->width);
+ if (sizeof(resource_size_t) * 8 < width)
+ printk(KERN_WARNING "WARNING: The system width %d is smaller "
+ "than the remote RapidIO space address width %d!",
+ sizeof(resource_size_t) * 8, width);
+
+ /* Find the rio space block */
+ for (i = 0; i < SA_BITMAP_MAX_INB_RES; i++)
+ if ((in_be32(&rsect0->inb_res[i].ctrl) & SA_RIO_RES_CTRL_EN)
+ && (in_be32(&rsect0->inb_res[i].owner) == owner )) {
+ if (!res) {
+ ERR("Resource NULL error!\n");
+ ret = -EFAULT;
+ goto out;
+ }
+ memset(res, 0, sizeof(struct resource));
+ res->start = (IS_64BIT_RES && (width > 32)) ?
+ in_be32(&rsect0->inb_res[i].extaddr) << 32 : 0
+ | rsect0->inb_res[i].addr;
+ res->end = res->start - 1 +
+ ((in_be32(&rsect0->inb_res[i].size)) |
+ ((IS_64BIT_RES && (width > 32)) ?
+ ((u64)(in_be32(&rsect0->inb_res[i].extsize))
+ << 32) : 0));
+ goto out;
+ }
+
+out:
+ rio_unmap_outb_region(mport, sblock_buf);
+ return ret;
+}
+
+/**
+ * rio_space_init -- RapidIO space allocator initialization function.
+ * @mport: The master port.
+ */
+int rio_space_init(struct rio_mport *mport)
+{
+ root = &mport->riores[RIO_INB_MEM_RESOURCE];
+ memset(root, 0, sizeof(struct resource));
+
+ rio_addr_size = get_rio_addr_size();
+
+ rio_space_get_dev_mem(mport, rio_get_mport_id(mport), root);
+ root->name = "rio_space_inb";
+
+ /* Alloc the sect 0 for space managerment */
+ memset(§0mem, 0, sizeof(struct rio_mem));
+ if(!(sect0mem.virt = dma_alloc_coherent(NULL, RIO_SBLOCK_SIZE,
+ §0mem.iores.start, GFP_KERNEL))) {
+ ERR("sect0 memory alloc error!\n");
+ return -ENOMEM;
+ }
+ sect0mem.iores.end = sect0mem.iores.start + RIO_SBLOCK_SIZE - 1;
+ sect0mem.size = RIO_SBLOCK_SIZE;
+
+ if(rio_space_request(mport, RIO_SBLOCK_SIZE, §0mem.riores))
+ return -ENOMEM;
+
+ sect0mem.riores.name = "sect 0";
+ sect0 = sect0mem.virt;
+ sect0->id = SA_BITMAP_DRV_ID;
+ sect0->rioid = rio_get_mport_id(mport);
+ sect0->width = rio_addr_size;
+
+ /* map outbond window to access rio inb */
+ rio_map_inb_region(mport, §0mem, 0);
+
+ /* Init sblock buffer for block seeking */
+ sblock_buf = rio_prepare_io_mem(mport, NULL, RIO_SBLOCK_SIZE,
+ "sblock_buf");
+ if (!sblock_buf)
+ return -ENOMEM;
+
+ return 0;
+}
--
1.5.2
^ permalink raw reply related
* Bug#457294: [powerpc] System time not updated after sleep cycle
From: Michel Dänzer @ 2007-12-21 10:21 UTC (permalink / raw)
To: Debian Bug Tracking System
Package: linux-2.6
Version: 2.6.23-1
Severity: important
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
After wakeup from sleep, the system time is still the same as it was when going
to sleep. I have to restart ntp to get it updated.
This problem didn't occur with previous kernels. It persists in
2.6.23-2~snapshot.9949 but is fixed in
2.6.24~rc5-1~experimental.1~snapshot.9974 . I'm CC'ing the linuxppc-dev list on
this report in the hope that someone there remembers how this was fixed post
2.6.23 upstream and that the fix can hopefully be backported.
- -- System Information:
Debian Release: lenny/sid
APT prefers unstable
APT policy: (500, 'unstable'), (500, 'stable'), (102, 'experimental')
Architecture: powerpc (ppc)
Kernel: Linux 2.6.24-rc5-powerpc
Locale: LANG=de_CH.UTF-8, LC_CTYPE=de_CH.UTF-8 (charmap=UTF-8)
Shell: /bin/sh linked to /bin/bash
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.6 (GNU/Linux)
iD8DBQFHa5O1WoGvjmrbsgARAjGpAJ0TaORdhlrDU1kYPDF7dpAvNK0s0ACfU4mX
erietOhcqZUjsxn+803CxXo=
=I/Op
-----END PGP SIGNATURE-----
^ permalink raw reply
* Re: [PATCH 1/21] [POWERPC] Reworking machine check handling and Fix 440/440A
From: Josh Boyer @ 2007-12-21 12:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20071221043925.42B40DDE30@ozlabs.org>
On Fri, 21 Dec 2007 15:39:21 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> Index: linux-merge/include/asm-ppc/reg_booke.h
> ===================================================================
> --- linux-merge.orig/include/asm-ppc/reg_booke.h 2007-09-28 11:42:10.000000000 +1000
> +++ linux-merge/include/asm-ppc/reg_booke.h 2007-12-20 11:35:40.000000000 +1100
> @@ -207,7 +207,7 @@
> #define CCR1_TCS 0x00000080 /* Timer Clock Select */
>
> /* Bit definitions for the MCSR. */
> -#ifdef CONFIG_440A
> +#ifdef CONFIG_44x
Should be #ifdef CONFIG_4xx as I pointed out last time. I'll fix it
when I commit.
josh
^ permalink raw reply
* Yet more patches added to for-2.6.25/master branches
From: Paul Mackerras @ 2007-12-21 12:12 UTC (permalink / raw)
To: linuxppc-dev
Aegis Lin (1):
[POWERPC] spufs: Use separate timer for /proc/spu_loadavg calculation
Andre Detsch (1):
[POWERPC] spufs: DMA Restart after SIGSEGV
Arnd Bergmann (1):
[POWERPC] spufs: block fault handlers in spu_acquire_runnable
Benjamin Herrenschmidt (2):
[POWERPC] Fix for via-pmu based backlight control
[POWERPC] Fix possible NULL deref in ppc32 PCI
Christoph Hellwig (2):
[POWERPC] spufs: add enchanced simple attr macros
[POWERPC] spufs: make state_mutex interruptible
Emil Medve (1):
[POWERPC] Optimize counting distinct entries in the relocation sections
Jeremy Kerr (5):
[POWERPC] spufs: move fault, lscsa_alloc and switch code to spufs module
[POWERPC] spufs: fix incorrect interrupt status clearing in backing mbox stat poll
[POWERPC] spufs: use #defines for SPU class [012] exception status
[POWERPC] spufs: rework class 0 and 1 interrupt handling
[POWERPC] spufs: Don't leak kernel stack through an empty {i,m}box_info read
Julio M. Merino Vidal (1):
[POWERPC] spufs: fix typos in sched.c comments
Luke Browning (4):
[POWERPC] spufs: add backing ops for privcntl register
[POWERPC] spufs: reorganize spu_run_init
[POWERPC] spufs: spu_find_victim may choose wrong victim
[POWERPC] spufs: decouple spu scheduler from spufs_spu_run (asynchronous scheduling)
Masato Noguchi (2):
[POWERPC] cell: wrap master run control bit
[POWERPC] spufs: don't set reserved bits in spu interrupt status
Scott Wood (1):
[POWERPC] Implement arch disable/enable irq hooks.
Stephen Rothwell (5):
[POWERPC] Add EHEA and EHCA as modules in the ppc64_defconfig
[POWERPC] The builtin matches for ibmebus.c can be __initdata
[POWERPC] Constify the of_device_id passed to of_platform_bus_probe
[POWERPC] Pointers marked as __iomem do not need to be volatile
[POWERPC] Make non-PCI build work again
^ permalink raw reply
* Re: [PATCH 18/21] [POWERPC] bamboo: remove bogus "ranges" property in EBC node
From: Josh Boyer @ 2007-12-21 12:09 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20071221043939.72A8BDDFCF@ozlabs.org>
On Fri, 21 Dec 2007 15:39:35 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> This removes a bogus empty "ranges" property in the EBC device node
> of the Bamboo board device-tree.
>
> The "ranges" property will be created by the boot wrapper, there is
> no need to have an empty property there, and that causes recent
> dtc to complain.
The wrapper doesn't do anything with EBC for bamboo because the EBC
stuff is a nightmare on this board. The patch can stand, but I'll
fixup the comments in the changelog.
josh
^ permalink raw reply
* Re: [PATCH 20/21] [POWERPC] pci32: 4xx embedded platforms want to reassign all PCI resources
From: Josh Boyer @ 2007-12-21 12:11 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20071221043941.37EB9DDFEC@ozlabs.org>
On Fri, 21 Dec 2007 15:39:37 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> Index: linux-merge/arch/powerpc/platforms/44x/sequoia.c
> ===================================================================
> --- linux-merge.orig/arch/powerpc/platforms/44x/sequoia.c 2007-12-14 15:48:53.000000000 +1100
> +++ linux-merge/arch/powerpc/platforms/44x/sequoia.c 2007-12-14 15:49:52.000000000 +1100
> @@ -21,7 +21,8 @@
> #include <asm/udbg.h>
> #include <asm/time.h>
> #include <asm/uic.h>
> -#include "44x.h"
> +#include <asm/pci-bridge.h>
> +
This is still broken because you removed the 44x.h include. I'll fix
it on my commit.
josh
^ permalink raw reply
* Re: Yet more patches added to for-2.6.25/master branches
From: Arnd Bergmann @ 2007-12-21 12:37 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
In-Reply-To: <18283.44454.618519.155696@cargo.ozlabs.ibm.com>
Thanks for adding the patches I submitted for 2.6.25.
What's your position on this one:
http://patchwork.ozlabs.org/linuxppc/patch?id=15600
OProfile: remove dependency on spufs module
Jeremy agreed that we should merge it in 2.6.24, but if you think
it's too late for that, please add it to your 2.6.25 queue.
Arnd <><
^ permalink raw reply
* Time for cell code reshuffle?
From: Arnd Bergmann @ 2007-12-21 14:22 UTC (permalink / raw)
To: cbe-oss-dev; +Cc: linuxppc-dev, Paul Mackerras, Jeremy Kerr
We've been discussing in the past a few times where we should best put
the spufs code, and when to do it. Since Jeremy and I now have all the
current patches in powerpc.git, maybe we should do it now.
To the question, where what it should go, I'd leave the decision to
Jeremy, but my current idea would be:
arch/powerpc/platforms/cell/spufs -> arch/powerpc/spufs
arch/powerpc/platforms/cell/spu_{callbacks,base,syscalls,fault,notify}.[co]
-> arch/powerpc/spufs/{callbacks,base,syscalls,fault,notify}.[co]
If we do it in git now, that should result in a minimal breakage of patches.
A related question is what to do about the location of the other cell
related files. platforms/ps3 is already pretty self-contained once we have
spufs outside of platforms/cell, but there is still some code shared between
platforms/cell and platforms/celleb, and each of these directories also contains
code that is only relevant for a subset of the platforms.
My position on these files is that while I find the current state a little
bit confusing, I don't have an idea how to do it better either, and I think
we should just leave the platform files where they are.
Arnd <><
^ permalink raw reply
* Changes to Freescale I2C driver makes it stop working for us moving from 2.6.22 to 2.6.23.9
From: michael.firth @ 2007-12-21 14:33 UTC (permalink / raw)
To: linuxppc-embedded
We've recently updated the kernel on one of our Freescale MPC834x
systems from 2.6.22 to 2.6.23.9.
Everything seemed to be working fine, until we tried the I2C buses. This
had been working find on 2.6.22, but on 2.6.23.9 it fails on trying to
open the I2C devices.
Looking in to the code, the 'fsl_i2c_probe' function has changed
slightly between the releases. Changing this back to the way it was in
2.6.22 make things work again.
Old code:
i2c->adap =3D mpc_ops;
i2c_set_adapdata(&i2c->adap, i2c);
i2c->adap.dev.parent =3D &pdev->dev;
if ((result =3D i2c_add_adapter(&i2c->adap)) < 0) {
printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
goto fail_add;
}
New code:
i2c->adap =3D mpc_ops;
i2c->adap.nr =3D pdev->id;
i2c_set_adapdata(&i2c->adap, i2c);
i2c->adap.dev.parent =3D &pdev->dev;
if ((result =3D i2c_add_numbered_adapter(&i2c->adap)) < 0) {
printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
goto fail_add;
}
Presumably the new code puts additional requirements on the
'platform_device' registration - can anyone let me know what I'll need
to add to get this working with the new driver code?
Thanks in advance
Michael
^ permalink raw reply
* Re: Yet more patches added to for-2.6.25/master branches
From: Marian Balakowicz @ 2007-12-21 14:13 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <18283.44454.618519.155696@cargo.ozlabs.ibm.com>
Any changes to add new 52xx targets:
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14662
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14663
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14743
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14665
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14666
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14667
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14668
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14669
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14670
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14671
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14672
http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14673
Those did not make it to 2.6.24, Grant Likely suggested to wait until
2.6.25 window opens.
Thanks,
Marian
^ permalink raw reply
* Re: Yet more patches added to for-2.6.25/master branches
From: Kumar Gala @ 2007-12-21 15:29 UTC (permalink / raw)
To: Marian Balakowicz; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <476BCA09.3070104@semihalf.com>
On Dec 21, 2007, at 8:13 AM, Marian Balakowicz wrote:
>
> Any changes to add new 52xx targets:
>
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14662
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14663
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14743
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14665
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14666
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14667
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14668
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14669
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14670
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14671
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14672
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14673
>
> Those did not make it to 2.6.24, Grant Likely suggested to wait until
> 2.6.25 window opens.
A few of these patches may need to get updated do to other changes.
For example the i2c nodes in .dts.
- k
^ permalink raw reply
* Re: [PATCH 1/3] sbc8548: Add basic support for Wind River SBC8548 as powerpc
From: Kumar Gala @ 2007-12-21 15:32 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev
In-Reply-To: <11982194344016-git-send-email-paul.gortmaker@windriver.com>
On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:
> This adds the basic support for the Wind River SBC8548 board,
> implemented
> as powerpc. It closely follows the implementation of the MPC8548CDS.
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig | 10 ++-
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/sbc8548.c | 182 ++++++++++++++++++++++++
> +++++++++
> 3 files changed, 191 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/
> platforms/85xx/Kconfig
> index 33d3bea..8407f43 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -39,6 +39,12 @@ config MPC85xx_DS
> help
> This option enables support for the MPC85xx DS (MPC8544 DS) board
>
> +config SBC8548
> + bool "Wind River SBC8548"
> + select DEFAULT_UIMAGE
> + help
> + This option enables support for the Wind River SBC8548 board
> +
> config SBC8560
> bool "Wind River SBC8560"
> select DEFAULT_UIMAGE
> @@ -52,7 +58,7 @@ config MPC8540
> bool
> select PPC_UDBG_16550
> select PPC_INDIRECT_PCI
> - default y if MPC8540_ADS || MPC85xx_CDS
> + default y if MPC8540_ADS || MPC85xx_CDS || SBC8548
>
> config MPC8560
> bool
> @@ -66,4 +72,4 @@ config MPC85xx
> select FSL_PCI if PCI
> select SERIAL_8250_SHARE_IRQ if SERIAL_8250
> default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
> - || MPC85xx_MDS || MPC85xx_DS || SBC8560
> + || MPC85xx_MDS || MPC85xx_DS || SBC8560 || SBC8548
> diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/
> platforms/85xx/Makefile
> index c3f4d01..3a47b7a 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -6,4 +6,5 @@ obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
> obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
> obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
> obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
> +obj-$(CONFIG_SBC8548) += sbc8548.o
> obj-$(CONFIG_SBC8560) += sbc8560.o
> diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/
> platforms/85xx/sbc8548.c
> new file mode 100644
> index 0000000..f3ab271
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/sbc8548.c
> @@ -0,0 +1,182 @@
> +/*
> + * Wind River SBC8548 setup and early boot code.
> + *
> + * Copyright 2007 Wind River Systems Inc.
> + *
> + * By Paul Gortmaker (see MAINTAINERS for contact information)
> + *
> + * Based largely on the MPC8548CDS support - Copyright 2005
> Freescale Inc.
> + *
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/reboot.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/major.h>
> +#include <linux/console.h>
> +#include <linux/delay.h>
> +#include <linux/seq_file.h>
> +#include <linux/initrd.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/fsl_devices.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/system.h>
> +#include <asm/pgtable.h>
> +#include <asm/page.h>
> +#include <asm/atomic.h>
> +#include <asm/time.h>
> +#include <asm/io.h>
> +#include <asm/machdep.h>
> +#include <asm/ipic.h>
> +#include <asm/pci-bridge.h>
> +#include <asm/irq.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +
> +#ifdef CONFIG_PCI
> +static int sbc8548_exclude_device(struct pci_controller *hose,
> + u_char bus, u_char devfn)
> +{
> + if (bus == 0 && PCI_SLOT(devfn) == 0)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> + else
> + return PCIBIOS_SUCCESSFUL;
> +}
> +#endif
see comment on the 8560 support, but I don't think you need to exclude
the PHBs anymore. I've fixed this so we have a general quick for FSL
PHBs.
>
- k
^ permalink raw reply
* Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River SBC8548 board
From: Kumar Gala @ 2007-12-21 15:33 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev
In-Reply-To: <1198219435310-git-send-email-paul.gortmaker@windriver.com>
On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:
> This adds the device tree source for the Wind River SBC8548 board.
> The
> biggest difference between this and the MPC8548CDS reference platform
> is the absence of the CDS's Arcadia peripherals and physical access
> to PCI#2.
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> arch/powerpc/boot/dts/sbc8548.dts | 242 ++++++++++++++++++++++++++++
> +++++++++
> 1 files changed, 242 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/
> dts/sbc8548.dts
> new file mode 100644
> index 0000000..e63ed20
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/sbc8548.dts
> @@ -0,0 +1,242 @@
> +/*
> + * SBC8548 Device Tree Source
> + *
> + * Copyright 2007 Wind River Systems Inc.
> + *
> + * Paul Gortmaker (see MAINTAINERS for contact information)
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +
> +/ {
> + model = "SBC8548";
> + compatible = "SBC8548";
> + #address-cells = <1>;
> + #size-cells = <1>;
mind looking at converting this to a dts-v1 format?
- k
^ permalink raw reply
* Re: [PATCH 1/4] sbc8560: add basic support for Wind River SBC8560 as powerpc
From: Paul Gortmaker @ 2007-12-21 15:37 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev
In-Reply-To: <20071221101425.3408278c.sfr@canb.auug.org.au>
In message: Re: [PATCH 1/4] sbc8560: add basic support for Wind River SBC8560 as powerpc
on 21/12/2007 Stephen Rothwell wrote:
> Hi Paul,
>
> Just a couple of comments.
[...]
> The braces are unnecessary.
>
[...]
> We often say "if (!np)" and leave out the blank line above.
>
> > + if(of_address_to_resource(np, 0, &r)) {
> ^
> Put a space here.
[...]
> Need an of_node_pit(np) - cpm2_pic_init() does its own of_node_get.
>
> > +static struct cpm_pin sbc8560_pins[] = {
>
> const?
>
Sounds reasonable to me. I've integrated these into sbc8560.c (still
looking at how to handle the duart/dts based on feedback). Since I'd
inerited the things you'd requested fixes on from mpc85xx_ads.c, it
probably makes sense to fix them there too I would imagine. I'll send
that under its own subject in a minute.
Paul.
^ permalink raw reply
* CONFIG_PCI interaction with pata_platform driver on MPC834x board
From: Johns Daniel @ 2007-12-21 15:37 UTC (permalink / raw)
To: linuxppc-embedded
I am observing a strange interaction between configuring PCI support
in my kernel and CompactFlash probing. Without PCI support configured,
the CF card is discovered and configured by the kernel. With PCI
support configured, there is some issue in the probing of the CF card.
There are only two things that I notice between the two kernel setups
that might be significant:
1.) The libata virq changes from 19 to 20.
2.) The isa_io_base changes from 0x0 to 0xfcfff000.
Are either of these two changes significant?
I am using the "arch/powerpc" kernel, version 2.6.20.21. The CF is
wired directly to the local bus in True IDE mode.
I have some debug info included below.
-- Johns
================ without CONFIG_PCI =================
ata_device_add: ENTER
ata_port_add: ENTER
ata_port_start: prd alloc, virt dfe2a000, dma 1fe2a000
ata1: PATA max PIO0 cmd 0xE1062000 ctl 0xE106420C bmdma 0x0 irq 19
__ata_port_freeze: ata1 port frozen
ata_device_add: probe begin
scsi0 : pata_platform
ata_port_schedule_eh: port EH scheduled
ata_scsi_error: ENTER
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata_eh_autopsy: ENTER
ata_eh_recover: ENTER
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x0 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEC
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x50)
ata_hsm_move: ata1: dev 0 command complete, drv_stat 0x50
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata_dump_id: 49==0x0200 53==0x0003 63==0x0000 64==0x0003 75==0x0000
ata_dump_id: 80==0x0400 81==0x0000 82==0x0000 83==0x0000 84==0x0000
ata_dump_id: 88==0x0000 93==0x0000
ata1.00: CFA, max PIO4, 250880 sectors: LBA
ata1.00: ata1: dev 0 multi count 0
ata_eh_revalidate_and_attach: EXIT
ata_eh_resume: ENTER
ata_eh_resume: EXIT
ata_eh_suspend: ENTER
ata_eh_suspend: EXIT
ata_eh_recover: EXIT, rc=0
ata_scsi_error: EXIT
ata_device_add: host probe begin
ata_scsi_dump_cdb: CDB (1:0,0,0) 12 00 00 00 24 00 30 58 df
ata_scsiop_inq_std: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 12 00 00 00 60 00 30 58 df
ata_scsiop_inq_std: ENTER
scsi 0:0:0:0: Direct-Access ATA SanDisk SDCFH-12 HDB PQ: 0 ANSI: 5
ata_scsi_dump_cdb: CDB (1:0,0,0) 00 00 00 00 00 00 30 58 df
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 25 00 00 00 00 00 00 00 00
ata_scsiop_read_cap: ENTER
SCSI device sda: 250880 512-byte hdwr sectors (128 MB)
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 3f 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
sda: Write Protect is off
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 24
ata_scsiop_mode_sense: ENTER
SCSI device sda: write cache: disabled, read cache: enabled, doesn't
support DPO or FUA
ata_scsi_dump_cdb: CDB (1:0,0,0) 00 00 00 00 00 00 00 00 24
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 1e 00 00 00 01 00 00 00 24
ata_scsi_dump_cdb: CDB (1:0,0,0) 00 00 00 00 00 00 00 00 24
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 25 00 00 00 00 00 00 00 00
ata_scsiop_read_cap: ENTER
SCSI device sda: 250880 512-byte hdwr sectors (128 MB)
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 3f 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
sda: Write Protect is off
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 24
ata_scsiop_mode_sense: ENTER
SCSI device sda: write cache: disabled, read cache: enabled, doesn't
support DPO or FUA
sda:<3>ata_scsi_dump_cdb: CDB (1:0,0,0) 28 00 00 00 00 00 00 00 08
ata_scsi_translate: ENTER
scsi_10_lba_len: ten-byte command
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x8 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xE0
ata_exec_command_mmio: ata1: cmd 0x20
ata_scsi_translate: EXIT
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x50)
ata_hsm_move: ata1: dev 0 command complete, drv_stat 0x50
sda1 sda2 sda3
sd 0:0:0:0: Attached scsi removable disk sda
ata_device_add: EXIT, returning 1
================ without CONFIG_PCI =================
================== with CONFIG_PCI =================
ata_device_add: ENTER
ata_port_add: ENTER
ata_port_start: prd alloc, virt dfe46000, dma 1fe46000
ata1: PATA max PIO0 cmd 0xE1062000 ctl 0xE106420C bmdma 0x0 irq 20
__ata_port_freeze: ata1 port frozen
ata_device_add: probe begin
scsi0 : pata_platform
ata_port_schedule_eh: port EH scheduled
ata_scsi_error: ENTER
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata_eh_autopsy: ENTER
ata_eh_recover: ENTER
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x0 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEC
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ATA: abnormal status 0x58 on port 0xE106200E
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x58)
ata_hsm_move: ata1: protocol 2 task_state 3 (dev_stat 0x58)
__ata_port_freeze: ata1 port frozen
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata1.00: failed to IDENTIFY (I/O error, err_mask=0x2)
ata_eh_revalidate_and_attach: EXIT
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x0 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEC
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ATA: abnormal status 0x58 on port 0xE106200E
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x58)
ata_hsm_move: ata1: protocol 2 task_state 3 (dev_stat 0x58)
__ata_port_freeze: ata1 port frozen
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata1.00: failed to IDENTIFY (I/O error, err_mask=0x2)
ata_eh_revalidate_and_attach: EXIT
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x0 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEC
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ATA: abnormal status 0x58 on port 0xE106200E
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x58)
ata_hsm_move: ata1: protocol 2 task_state 3 (dev_stat 0x58)
__ata_port_freeze: ata1 port frozen
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata1.00: failed to IDENTIFY (I/O error, err_mask=0x2)
ata_eh_revalidate_and_attach: EXIT
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata_eh_revalidate_and_attach: EXIT
ata_eh_resume: ENTER
ata_eh_resume: EXIT
ata_eh_suspend: ENTER
ata_eh_suspend: EXIT
ata_eh_recover: EXIT, rc=0
ata_scsi_error: EXIT
ata_device_add: host probe begin
ata_device_add: EXIT, returning 1
================== with CONFIG_PCI =================
^ permalink raw reply
* [PATCH] mpc85xx_ads: add in missing of_node_put()
From: Paul Gortmaker @ 2007-12-21 15:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sfr
cpm2_pic_init() does its own of_node_get() so we should do an of_node_put()
before calling it. This and other coding style cleanups as suggested by
Stephen Rothwell.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index bccdc25..ea4886f 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -52,9 +52,9 @@ static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
int cascade_irq;
- while ((cascade_irq = cpm2_get_irq()) >= 0) {
+ while ((cascade_irq = cpm2_get_irq()) >= 0)
generic_handle_irq(cascade_irq);
- }
+
desc->chip->eoi(irq);
}
@@ -70,13 +70,12 @@ static void __init mpc85xx_ads_pic_init(void)
#endif
np = of_find_node_by_type(np, "open-pic");
-
- if (np == NULL) {
+ if (!np) {
printk(KERN_ERR "Could not find open-pic node\n");
return;
}
- if(of_address_to_resource(np, 0, &r)) {
+ if (of_address_to_resource(np, 0, &r)) {
printk(KERN_ERR "Could not map mpic register space\n");
of_node_put(np);
return;
@@ -98,6 +97,7 @@ static void __init mpc85xx_ads_pic_init(void)
return;
}
irq = irq_of_parse_and_map(np, 0);
+ of_node_put(np);
cpm2_pic_init(np);
set_irq_chained_handler(irq, cpm2_cascade);
@@ -112,7 +112,7 @@ struct cpm_pin {
int port, pin, flags;
};
-static struct cpm_pin mpc8560_ads_pins[] = {
+static const struct cpm_pin mpc8560_ads_pins[] = {
/* SCC1 */
{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* GPIO causing bus error
From: Wyse, Chris @ 2007-12-21 15:54 UTC (permalink / raw)
To: linuxppc-dev, linuxppc-embedded, +techfield, +linux-embedded,
+linux-eng, linux-kernel, Wessel, Jason, support
Cc: Slimm, Rob, Read, Tricia, Ayer, Charles, Touron, Emmanuel
[-- Attachment #1.1: Type: text/plain, Size: 3041 bytes --]
Hi,
I'm having trouble with an unusual problem. I'm working on relatively
new hardware, so it's possible that there could be a hardware issue
involved.
I have an FPGA on my PPC440GX board that gets loaded via JTAG during the
kernel boot process (Linux 2.6.10). It uses the 440GX GPIO lines to
send the necessary JTAG commands to the FPGA to perform the initial
load. This process is USUALLY functional, but on some of the boards
(which we produce), the GPIO write fails with a bus error. On the
boards that fail, it only occurs after a cold boot, and only if the
board has been powered off for a few minutes. A quick hard reboot will
not generate the problem. When I issue the failing write to the GPIO
lines, some of the SDRAM gets corrupted. I don't appear to be taking
any interrupts that might have corrupted the RAM.
I've checked the TLB entries, and it maps correctly to the PPC register
area. Additionally, I can read and write to other registers using the
same TLB mapping WITHOUT any error. I can also READ the GPIO lines
without an error - the error is only on the write. I've checked the
SDR0_PFC0 bits to make sure everything is set properly (it is). The bus
error indicates "PLB Timeout Error Status Master 2, Master 2 slave error
occurred" (Master 2 is the write-only data cache unit (DCU)) and "Write
Error Interrupt Master 2, Write error detected - master 2 interrupt
request is active". I'm not sure why there would be any error in the
DCU, since the region I'm writing to is cache inhibited and guarded.
If I issue a soft reset of the GPIO subsystem, I can read and write to
the GPIO lines again.
The error does not occur on the first write to the GPIO. I go through
the failing routine several times before it fails. However, when it
fails, it consistently fails at the same spot, after the same number of
passes through the code.
I'm using RGMII ethernet on EMAC2 (Group 4), but the GPIO lines that I'm
using are not the Trace/GPIO lines (26-31) so I believe that they should
work fine (and they usually do). Also, the errata mentions that
SDR0_PFC0[G11E] has no effect - but I'm not using GPIO 11 anyway.
Here are some relevant register values after the error:
SDR0_PFC0 : 0x083FFE00
POB0_BESR0: 0x00008400
POB0_BEARH: 0x00000001
POB0_BEARL: 0x40000701
GPIO0_OR : 0x000400C0
GPIO0_TCR : 0x00278AE0
GPIO0_ODR : 0x00000000
GPIO0_IR : 0x00000000
I've attached two log files, that contain most of the 440 registers, one
for before the error and one after. In the log files, the bus error has
been cleared, so use the values shown above.
I'm looking for some suggestions on what to try to debug/resolve this
issue. I'm open to both hardware and software based suggestions. Any
help would be greatly appreciated.
Chris Wyse
Senior Member of Technical Staff
Embedded Technologies
860-978-0849 cell/office
413-778-9101 fax
http://www.windriver.com <http://www.windriver.com/>
[-- Attachment #1.2: Type: text/html, Size: 6449 bytes --]
[-- Attachment #2: pre_error.log --]
[-- Type: application/octet-stream, Size: 27172 bytes --]
>BKM>dr all /ignore
GPR register Group. (GPR)
R00 = 00040040 R01 = CFFB1D80 R02 = CFC89AE0 R03 = C02B575C
R04 = 000000F8 R05 = 00000005 R06 = 000004A3 R07 = 00000000
R08 = C02B4E28 R09 = D1000700 R10 = C02B4E28 R11 = 000400C0
R12 = 00000080 R13 = 00000000 R14 = 0FFF4C00 R15 = 00000000
R16 = 00000001 R17 = 00000001 R18 = FFFFFFFF R19 = 007FFC00
R20 = 0FFEF148 R21 = 00000000 R22 = 00000003 R23 = 00000004
R24 = 00000000 R25 = 007FFB50 R26 = 00000E60 R27 = 007FFD0B
R28 = 007FFC00 R29 = C0400000 R30 = C000149C R31 = CFFB1E90
CR = 24FF2F24 MSR = 00029200 LR = C000EF64 SRR0 = C0003458
SRR1 = 00021200 SPRG0 = 00000000 SPRG1 = 00000000 SPRG2 = 00000000
SPRG3 = CFC89CB8 XER = 20000000 CTR = C000EEBC PC = C000EE10
4XXSPR register Group. (4XXSPR)
CSRR0 = 00000000 CSRR1 = 00000000 SPRG4_R = C02EDFB0 SPRG4_W = 00000000
SPRG5_R = 00000000 SPRG5_W = 00000000 SPRG6_R = 04502940 SPRG6_W = 00000000
SPRG7_R = 24FF2F48 SPRG7_W = 00000000 USPRG0 = 04502940 MCSRR0 = 00000000
MCSRR1 = 00000000 MCSR = 00000000 CCR1 = 00000000
CTRL register Group. (CTRL)
PVR = 51B21894 PID = 00000000 PIR = 00000000 MMUCR = 00000000
RSTCFG = 00000001 CCR0 = 00306000
DEBUG register Group. (DEBUG)
DBCR0 = 81000001 DBCR1 = 00000000 DBCR2 = 00000000 DBSR = 00400000
DAC1 = 00000000 DAC2 = 00000000 DVC1 = 00000000 DVC2 = 00000000
IAC1 = 00000000 IAC2 = 00000000 IAC3 = 00000000 IAC4 = E7F9B8FC
TIMERS register Group. (TIMERS)
TCR = 04000000 TSR = C4000000 TBL = 8FB5D62B TBU = 00000000
DEC = 00022286 DECAR = 00000000
EXCEPTS register Group. (EXCEPTS)
ESR = 00000000 DEAR = D1000704 IVPR = C0000000
CPR_CPM register Group. (CPR_CPM)
CPM0_ER = 00000000 CPM0_FR = 00000000 CPM0_SR = 00000000 CPR0_CLKUPD = 00000000
CPR0_PLLC = 400002B8 CPR0_PLLD = 04020702 CPR0_PRIMAD = 01000000 CPR0_PRIMBD = 01000000
CPR0_OPBD = 02000000 CPR0_PERD = 01000000 CPR0_MALD = 02000000 CPR0_ICFG = 00000007
CPR0_CFGADDR = 000000E0 CPR0_CFGDATA = 01000000
SDR0 register Group. (SDR0)
SDR0_SDSTP0 = 857042E6 SDR0_SDSTP1 = 09960D20 SDR0_PINSTP = E0000000 SDR0_SDCS = A0000003
SDR0_ECID0 = 07E00DD4 SDR0_ECID1 = 0D47FFFF SDR0_ECID2 = 040D0000 SDR0_JTAG = 52054049
SDR0_DDRDL = 00000012 SDR0_EBC = 10000000 SDR0_UART0 = 20800001 SDR0_UART1 = 20000026
SDR0_CP440 = 1EAAEA00 SDR0_XCR = C1A00000 SDR0_XPLLC = 000002B8 SDR0_XPLLD = 010A0000
SDR0_SRST = 00000000 SDR0_SLPIPE = F0000000 SDR0_AMP = 00000000 SDR0_MIRQ0 = 00000000
SDR0_MIRQ1 = 00000000 SDR0_MALTBL = 55550000 SDR0_MALRBL = 55550000 SDR0_MALTBS = F0000000
SDR0_MALRBS = F0000000 SDR0_CUST0 = FFFFFFFF SDR0_SDSTP2 = 00000000 SDR0_CUST1 = FFFFFFFF
SDR0_SDSTP3 = 00000000 SDR0_PFC0 = 083FFE00 SDR0_PFC1 = 01200000 SDR0_PLBTR = 000001B0
SDR0_MFR = 00000000 SDR0_CFGADDR = 00004100 SDR0_CFGDATA = 083FFE00
CACHE register Group. (CACHE)
ICDBDR = 00C00000 ICDBTRH = C0000000 ICDBTRL = 00000001 DCDBTRH = BBFFFF88
DCDBTRL = 0007BFE0 DNV0 = 32370237 DNV1 = 0F20191D DNV2 = 033C2300
DNV3 = 071D3532 DTV0 = 00000000 DTV1 = 00000000 DTV2 = 00000000
DTV3 = 00000000 DVLIM = 0001F800 INV0 = 01010101 INV1 = 00000000
INV2 = 00000001 INV3 = 01010101 ITV0 = 00000000 ITV1 = 00000000
ITV2 = 00000000 ITV3 = 00000000 IVLIM = 0001F800
L2CACHE register Group. (L2CACHE)
L2C0_CFG = E1A70080 L2C0_CMD = 00000000 L2C0_ADDR = 00000000 L2C0_DATA = 00000000
L2C0_SR = 88000000 L2C0_REVID = 00000101 L2C0_SNP0 = 0000F800 L2C0_SNP1 = 8000F800
TLB register Group. (TLB)
TLB0PID = 00000000 TLB0WORD0 = 00000000 TLB0WORD1 = 00000000 TLB0WORD2 = 00000000
TLB1PID = 00000000 TLB1WORD0 = FDFFF210 TLB1WORD1 = 0EC80002 TLB1WORD2 = 00000503
TLB2PID = 00000000 TLB2WORD0 = FDFED210 TLB2WORD1 = 40000001 TLB2WORD2 = 00000503
TLB3PID = 00000000 TLB3WORD0 = D1000210 TLB3WORD1 = 40000001 TLB3WORD2 = 00000503
TLB4PID = 00000000 TLB4WORD0 = 00000000 TLB4WORD1 = 00000000 TLB4WORD2 = 00000000
TLB5PID = 00000000 TLB5WORD0 = 00000000 TLB5WORD1 = 00000000 TLB5WORD2 = 00000000
TLB6PID = 00000000 TLB6WORD0 = 00000000 TLB6WORD1 = 00000000 TLB6WORD2 = 00000000
TLB7PID = 00000000 TLB7WORD0 = 00000000 TLB7WORD1 = 00000000 TLB7WORD2 = 00000000
TLB8PID = 00000000 TLB8WORD0 = 00000000 TLB8WORD1 = 00000000 TLB8WORD2 = 00000000
TLB9PID = 00000000 TLB9WORD0 = 00000000 TLB9WORD1 = 00000000 TLB9WORD2 = 00000000
TLB10PID = 00000000 TLB10WORD0 = 00000000 TLB10WORD1 = 00000000 TLB10WORD2 = 00000000
TLB11PID = 00000000 TLB11WORD0 = 00000000 TLB11WORD1 = 00000000 TLB11WORD2 = 00000000
TLB12PID = 00000000 TLB12WORD0 = 00000000 TLB12WORD1 = 00000000 TLB12WORD2 = 00000000
TLB13PID = 00000000 TLB13WORD0 = 00000000 TLB13WORD1 = 00000000 TLB13WORD2 = 00000000
TLB14PID = 00000000 TLB14WORD0 = 00000000 TLB14WORD1 = 00000000 TLB14WORD2 = 00000000
TLB15PID = 00000000 TLB15WORD0 = 00000000 TLB15WORD1 = 00000000 TLB15WORD2 = 00000000
TLB16PID = 00000000 TLB16WORD0 = 00000000 TLB16WORD1 = 00000000 TLB16WORD2 = 00000000
TLB17PID = 00000000 TLB17WORD0 = 00000000 TLB17WORD1 = 00000000 TLB17WORD2 = 00000000
TLB18PID = 00000000 TLB18WORD0 = 00000000 TLB18WORD1 = 00000000 TLB18WORD2 = 00000000
TLB19PID = 00000000 TLB19WORD0 = 00000000 TLB19WORD1 = 00000000 TLB19WORD2 = 00000000
TLB20PID = 00000000 TLB20WORD0 = 00000000 TLB20WORD1 = 00000000 TLB20WORD2 = 00000000
TLB21PID = 00000000 TLB21WORD0 = 00000000 TLB21WORD1 = 00000000 TLB21WORD2 = 00000000
TLB22PID = 00000000 TLB22WORD0 = 00000000 TLB22WORD1 = 00000000 TLB22WORD2 = 00000000
TLB23PID = 00000000 TLB23WORD0 = 00000000 TLB23WORD1 = 00000000 TLB23WORD2 = 00000000
TLB24PID = 00000000 TLB24WORD0 = 00000000 TLB24WORD1 = 00000000 TLB24WORD2 = 00000000
TLB25PID = 00000000 TLB25WORD0 = 00000000 TLB25WORD1 = 00000000 TLB25WORD2 = 00000000
TLB26PID = 00000000 TLB26WORD0 = 00000000 TLB26WORD1 = 00000000 TLB26WORD2 = 00000000
TLB27PID = 00000000 TLB27WORD0 = 00000000 TLB27WORD1 = 00000000 TLB27WORD2 = 00000000
TLB28PID = 00000000 TLB28WORD0 = 00000000 TLB28WORD1 = 00000000 TLB28WORD2 = 00000000
TLB29PID = 00000000 TLB29WORD0 = 00000000 TLB29WORD1 = 00000000 TLB29WORD2 = 00000000
TLB30PID = 00000000 TLB30WORD0 = 00000000 TLB30WORD1 = 00000000 TLB30WORD2 = 00000000
TLB31PID = 00000000 TLB31WORD0 = 00000000 TLB31WORD1 = 00000000 TLB31WORD2 = 00000000
TLB32PID = 00000000 TLB32WORD0 = 00000000 TLB32WORD1 = 00000000 TLB32WORD2 = 00000000
TLB33PID = 00000000 TLB33WORD0 = 00000000 TLB33WORD1 = 00000000 TLB33WORD2 = 00000000
TLB34PID = 00000000 TLB34WORD0 = 00000000 TLB34WORD1 = 00000000 TLB34WORD2 = 00000000
TLB35PID = 00000000 TLB35WORD0 = 00000000 TLB35WORD1 = 00000000 TLB35WORD2 = 00000000
TLB36PID = 00000000 TLB36WORD0 = 00000000 TLB36WORD1 = 00000000 TLB36WORD2 = 00000000
TLB37PID = 00000000 TLB37WORD0 = 00000000 TLB37WORD1 = 00000000 TLB37WORD2 = 00000000
TLB38PID = 00000000 TLB38WORD0 = 00000000 TLB38WORD1 = 00000000 TLB38WORD2 = 00000000
TLB39PID = 00000000 TLB39WORD0 = 00000000 TLB39WORD1 = 00000000 TLB39WORD2 = 00000000
TLB40PID = 00000000 TLB40WORD0 = 00000000 TLB40WORD1 = 00000000 TLB40WORD2 = 00000000
TLB41PID = 00000000 TLB41WORD0 = 00000000 TLB41WORD1 = 00000000 TLB41WORD2 = 00000000
TLB42PID = 00000000 TLB42WORD0 = 00000000 TLB42WORD1 = 00000000 TLB42WORD2 = 00000000
TLB43PID = 00000000 TLB43WORD0 = 00000000 TLB43WORD1 = 00000000 TLB43WORD2 = 00000000
TLB44PID = 00000000 TLB44WORD0 = 00000000 TLB44WORD1 = 00000000 TLB44WORD2 = 00000000
TLB45PID = 00000000 TLB45WORD0 = 00000000 TLB45WORD1 = 00000000 TLB45WORD2 = 00000000
TLB46PID = 00000000 TLB46WORD0 = 00000000 TLB46WORD1 = 00000000 TLB46WORD2 = 00000000
TLB47PID = 00000000 TLB47WORD0 = 00000000 TLB47WORD1 = 00000000 TLB47WORD2 = 00000000
TLB48PID = 00000000 TLB48WORD0 = 00000000 TLB48WORD1 = 00000000 TLB48WORD2 = 00000000
TLB49PID = 00000000 TLB49WORD0 = 00000000 TLB49WORD1 = 00000000 TLB49WORD2 = 00000000
TLB50PID = 00000000 TLB50WORD0 = 00000000 TLB50WORD1 = 00000000 TLB50WORD2 = 00000000
TLB51PID = 00000000 TLB51WORD0 = 00000000 TLB51WORD1 = 00000000 TLB51WORD2 = 00000000
TLB52PID = 00000000 TLB52WORD0 = 00000000 TLB52WORD1 = 00000000 TLB52WORD2 = 00000000
TLB53PID = 00000000 TLB53WORD0 = 00000000 TLB53WORD1 = 00000000 TLB53WORD2 = 00000000
TLB54PID = 00000000 TLB54WORD0 = 00000000 TLB54WORD1 = 00000000 TLB54WORD2 = 00000000
TLB55PID = 00000000 TLB55WORD0 = 00000000 TLB55WORD1 = 00000000 TLB55WORD2 = 00000000
TLB56PID = 00000000 TLB56WORD0 = 00000000 TLB56WORD1 = 00000000 TLB56WORD2 = 00000000
TLB57PID = 00000000 TLB57WORD0 = 00000000 TLB57WORD1 = 00000000 TLB57WORD2 = 00000000
TLB58PID = 00000000 TLB58WORD0 = 00000000 TLB58WORD1 = 00000000 TLB58WORD2 = 00000000
TLB59PID = 00000000 TLB59WORD0 = 00000000 TLB59WORD1 = 00000000 TLB59WORD2 = 00000000
TLB60PID = 00000000 TLB60WORD0 = 00000000 TLB60WORD1 = 00000000 TLB60WORD2 = 00000000
TLB61PID = 00000000 TLB61WORD0 = 00000000 TLB61WORD1 = 00000000 TLB61WORD2 = 00000000
TLB62PID = 00000000 TLB62WORD0 = 00000000 TLB62WORD1 = 00000000 TLB62WORD2 = 00000000
TLB63PID = 00000000 TLB63WORD0 = C0000290 TLB63WORD1 = 00000000 TLB63WORD2 = 00000107
SRAM0 register Group. (SRAM0)
SRAM0_SB0CR = 80000800 SRAM0_SB1CR = 80010800 SRAM0_SB2CR = 80020800 SRAM0_SB3CR = 80030800
SRAM0_BEAR = 00000000 SRAM0_BESR0 = 00000000 SRAM0_BESR1 = 00000000 SRAM0_PMEG = 01E00000
SRAM0_CID = 322B0000 SRAM0_REVID = 04005800 SRAM0_DPC = 00000000
EBC0 register Group. (EBC0)
EBC0_CFG = 17004000 EBC0_B0CR = FF09A000 EBC0_B1CR = F001A000 EBC0_B2CR = F0118000
EBC0_B3CR = F0218000 EBC0_B4CR = F031A000 EBC0_B5CR = F041E000 EBC0_B6CR = F0518000
EBC0_B7CR = F0F18000 EBC0_B0AP = 9B015400 EBC0_B1AP = 9B055480 EBC0_B2AP = 1B015480
EBC0_B3AP = 12815280 EBC0_B4AP = 12815400 EBC0_B5AP = 1B015400 EBC0_B6AP = 00000000
EBC0_B7AP = 010502C0 EBC0_BEAR = 00000000 EBC0_BESR = 00000000 EBC0_CID = 32401093
EBC0_CFGADDR = 00000017 EBC0_CFGDATA = 010502C0
EBMI register Group. (EBMI)
EBM0_CTL = 88400000 EBM0_LCNT = 00000000 EBM0_BEAR = 00000000 EBM0_BESR = 00000000
EBM0_BEMR = 00000000 EBM0_UAR = 00000000 EBM0_UAM = 00000000 EBM0_SLPMD = 07C00000
EBM0_FAIR = FFF00000 EBM0_MISCSTS = 36000008 EBM0_CID = 32501054 EBM0_CFGADDR = 00000000
EBM0_CFGDATA = 88400000
SDRAM0 register Group. (SDRAM0)
SDRAM0_BESR0 = 00000000 SDRAM0_BESR1 = 00000000 SDRAM0_BEAR = 00000000 SDRAM0_MIRQ = 00000000
SDRAM0_UABBA = 00000000 SDRAM0_SLIO = 00000000 SDRAM0_DEVOPT = 00000000 SDRAM0_WDDCTR = 00000000
SDRAM0_CLKTR = 40000000 SDRAM0_CFG0A = 86000000 SDRAM0_CFG1 = 00000000 SDRAM0_PMIT = 07C00000
SDRAM0_TR0 = 410A4016 SDRAM0_TR1 = 80800828 SDRAM0_RTR = 04B00000 SDRAM0_B0CR = 000C4001
SDRAM0_B1CR = 00000000 SDRAM0_B2CR = 00000000 SDRAM0_B3CR = 00000000 SDRAM0_DLYCAL = 200000B0
SDRAM0_ECCESR = 00000000 SDRAM0_CID = 320B0000 SDRAM0_RID = 00003101 SDRAM0_CFG0B = 86000000
SDRAM0_MCSTS = A0000000 SDRAM0_CFGADDR = 0000004C SDRAM0_CFGDATA = 00000000
OCBUSES register Group. (OCBUSES)
PLB0_REVID = 00000101 PLB0_ACR = 9B000000 PLB0_BESR = 00000000 PLB0_BEARL = F77FFFFF
PLB0_BEARH = FDFFFFFF POB0_BESR0 = 00000000 POB0_BEARL = 00000000 POB0_BEARH = 00000000
POB0_BESR1 = 00000000 POB0_CONFG = 00000000 POB0_LATENCY = 78000000 POB0_REVID = 00000122
OPB0_BCTRL = 00000000 OPB0_BSTAT = 00000000 OPB0_BEARL = FFFFFFFF OPB0_BEARH = 0000000F
OPB0_REVID = 00000130
IVOR register Group. (IVOR)
IVOR0 = 00000240 IVOR1 = 00000340 IVOR2 = 00000460 IVOR3 = 00000560
IVOR4 = 00000620 IVOR5 = 000006E0 IVOR6 = 000007A0 IVOR7 = 00000860
IVOR8 = 00000920 IVOR9 = 000009E0 IVOR10 = 00000AA0 IVOR11 = 00000B60
IVOR12 = 00000C20 IVOR13 = 00000D20 IVOR14 = 00000DC0 IVOR15 = 00000E60
UIC register Group. (UIC)
UIC0_SR = 00000040 UIC0_ER = 00000000 UIC0_CR = 00000000 UIC0_PR = FFFFFE13
UIC0_TR = 01C00040 UIC0_MSR = 00000000 UIC0_VR = 00000000 UIC0_VCR = 00000040
UIC1_SR = 00002700 UIC1_ER = 00000000 UIC1_CR = 00000000 UIC1_PR = FFFFE0FF
UIC1_TR = 00FFC000 UIC1_MSR = 00000000 UIC1_VR = 00000000 UIC1_VCR = 00002700
UIC2_SR = 00000000 UIC2_ER = 00000100 UIC2_CR = 00000000 UIC2_PR = FFFFFFFF
UIC2_TR = 00FF8D0F UIC2_MSR = 00000000 UIC2_VR = 00000000 UIC2_VCR = 00000000
UICB0_SR = 03FFFFFF UICB0_ER = 54000000 UICB0_CR = 00000000 UICB0_PR = FC000000
UICB0_TR = 00000000 UICB0_MSR = 00000000 UICB0_VR = 00000000 UICB0_VCR = 03FFFFFF
DMA0 register Group. (DMA0)
DMA0_CR0 = 00000000 DMA0_CT0 = 00000000 DMA0_SAH0 = 00000000 DMA0_SAL0 = 00000000
DMA0_DAH0 = 00000000 DMA0_DAL0 = 00000000 DMA0_SGH0 = 00000000 DMA0_SGL0 = 00000000
DMA0_CR1 = 00000000 DMA0_CT1 = 00000000 DMA0_SAH1 = 00000000 DMA0_SAL1 = 00000000
DMA0_DAH1 = 00000000 DMA0_DAL1 = 00000000 DMA0_SGH1 = 00000000 DMA0_SGL1 = 00000000
DMA0_CR2 = 00000000 DMA0_CT2 = 00000000 DMA0_SAH2 = 00000000 DMA0_SAL2 = 00000000
DMA0_DAH2 = 00000000 DMA0_DAL2 = 00000000 DMA0_SGH2 = 00000000 DMA0_SGL2 = 00000000
DMA0_CR3 = 00000000 DMA0_CT3 = 00000000 DMA0_SAH3 = 00000000 DMA0_SAL3 = 00000000
DMA0_DAH3 = 00000000 DMA0_DAL3 = 00000000 DMA0_SGH3 = 00000000 DMA0_SGL3 = 00000000
DMA0_SR = 00008000 DMA0_SGC = 00000000 DMA0_SLP = 07C00000 DMA0_POL = 00000000
MAL0 register Group. (MAL0)
MAL0_CFG = 0037C086 MAL0_ESR = 00000000 MAL0_IER = 00000017 MAL0_TXCASR = 00000000
MAL0_TXCARR = 00000000 MAL0_TXEOBISR = 00000000 MAL0_TXDEIR = 00000000 MAL0_RXCASR = 00000000
MAL0_RXCARR = 00000000 MAL0_RXEOBISR = 00000000 MAL0_RXDEIR = 00000000 MAL0_TXCTP0R = 00000000
MAL0_TXCTP1R = 00000000 MAL0_TXCTP2R = 0FFA1340 MAL0_TXCTP3R = 00000000 MAL0_RXCTP0R = 00000000
MAL0_RXCTP1R = 00000000 MAL0_RXCTP2R = 0FFA13A0 MAL0_RXCTP3R = 00000000 MAL0_RCBS0 = 00000000
MAL0_RCBS1 = 00000000 MAL0_RCBS2 = 00000060 MAL0_RCBS3 = 00000000 MAL0_TXBADDR = 00000000
MAL0_RXBADDR = 00000000
PPM0 register Group. (PPM0)
PPM0_ISR = 00000000 PPM0_CR = 00000000 PPM0_CCR = FFFFFFFF PPM0_UAR = 00000000
PPM0_LAR = 00000000 PPM0_UAMR = FFFFFFFF PPM0_LAMR = FFFFFFFF PPM0_RIDR = C27E3411
PPM0_MCSR0 = 00000000 PPM0_MCSR1 = 00000000 PPM0_MCSR2 = 00000000 PPM0_MCSR3 = 00000000
PPM0_SCSR0 = 00000000 PPM0_SCSR1 = 00000000 PPM0_SCSR2 = 00000000 PPM0_SCSR3 = 00000000
PPM0_GCSR0 = 00000000 PPM0_GCSR1 = 00000000 PPM0_GCSR2 = 00000000 PPM0_GCSR3 = 00000000
PPM0_MCR0 = 00000000 PPM0_MCR1 = 00000000 PPM0_MCR2 = 00000000 PPM0_MCR3 = 00000000
PPM0_SCR0 = 00000000 PPM0_SCR1 = 00000000 PPM0_SCR2 = 00000000 PPM0_SCR3 = 00000000
PPM0_GCR0 = 00000000 PPM0_GCR1 = 00000000 PPM0_GCR2 = 00000000 PPM0_GCR3 = 00000000
PPM0_DCSR0 = 00000000 PPM0_DCSR1 = 00000000 PPM0_DCMXR0 = 00000000 PPM0_DCMXR1 = 00000000
PPM0_DCMNR0 = 00FFFFFF PPM0_DCMNR1 = 00FFFFFF PPM0_DCTVR0 = 00000000 PPM0_DCTVR1 = 00000000
PPM0_DCOTR0 = 00000000 PPM0_DCOTR1 = 00000000 PPM0_CFGADDR = 00000000 PPM0_CFGDATA = 00000000
[-- Attachment #3: post_error.log --]
[-- Type: application/octet-stream, Size: 27172 bytes --]
>BKM>dr all /ignore
GPR register Group. (GPR)
R00 = 00040040 R01 = CFFB1D80 R02 = CFC89AE0 R03 = C02B575C
R04 = 000000F8 R05 = 00000005 R06 = 000004A3 R07 = 00000000
R08 = C02B4E28 R09 = D1000700 R10 = C02B4E28 R11 = 000400C0
R12 = 00000080 R13 = 00000000 R14 = 0FFF4C00 R15 = 00000000
R16 = 00000001 R17 = 00000001 R18 = FFFFFFFF R19 = 007FFC00
R20 = 0FFEF148 R21 = 00000000 R22 = 00000003 R23 = 00000004
R24 = 00000000 R25 = 007FFB50 R26 = 00000E60 R27 = 007FFD0B
R28 = 007FFC00 R29 = C0400000 R30 = C000149C R31 = CFFB1E90
CR = 24FF2F24 MSR = 00029200 LR = C000EF64 SRR0 = C000EE10
SRR1 = 00029200 SPRG0 = 00000000 SPRG1 = 00000000 SPRG2 = 00000000
SPRG3 = CFC89CB8 XER = 20000000 CTR = C000EEBC PC = C000EE14
4XXSPR register Group. (4XXSPR)
CSRR0 = 00000000 CSRR1 = 00000000 SPRG4_R = C02EDFB0 SPRG4_W = 00000000
SPRG5_R = 00000000 SPRG5_W = 00000000 SPRG6_R = 04502940 SPRG6_W = 00000000
SPRG7_R = 24FF2F48 SPRG7_W = 00000000 USPRG0 = 04502940 MCSRR0 = 00000000
MCSRR1 = 00000000 MCSR = 00000000 CCR1 = 00000000
CTRL register Group. (CTRL)
PVR = 51B21894 PID = 00000000 PIR = 00000000 MMUCR = 00000000
RSTCFG = 00000001 CCR0 = 00306000
DEBUG register Group. (DEBUG)
DBCR0 = 81000001 DBCR1 = 00000000 DBCR2 = 00000000 DBSR = 00000000
DAC1 = 00000000 DAC2 = 00000000 DVC1 = 00000000 DVC2 = 00000000
IAC1 = 00000000 IAC2 = 00000000 IAC3 = 00000000 IAC4 = E7F9B8FC
TIMERS register Group. (TIMERS)
TCR = 04000000 TSR = C4000000 TBL = 8FB5D62B TBU = 00000000
DEC = 00022286 DECAR = 00000000
EXCEPTS register Group. (EXCEPTS)
ESR = 00000000 DEAR = DEC00000 IVPR = C0000000
CPR_CPM register Group. (CPR_CPM)
CPM0_ER = 00000000 CPM0_FR = 00000000 CPM0_SR = 00000000 CPR0_CLKUPD = 00000000
CPR0_PLLC = 400002B8 CPR0_PLLD = 04020702 CPR0_PRIMAD = 01000000 CPR0_PRIMBD = 01000000
CPR0_OPBD = 02000000 CPR0_PERD = 01000000 CPR0_MALD = 02000000 CPR0_ICFG = 00000007
CPR0_CFGADDR = 000000E0 CPR0_CFGDATA = 01000000
SDR0 register Group. (SDR0)
SDR0_SDSTP0 = 857042E6 SDR0_SDSTP1 = 09960D20 SDR0_PINSTP = E0000000 SDR0_SDCS = A0000003
SDR0_ECID0 = 07E00DD4 SDR0_ECID1 = 0D47FFFF SDR0_ECID2 = 040D0000 SDR0_JTAG = 52054049
SDR0_DDRDL = 00000012 SDR0_EBC = 10000000 SDR0_UART0 = 20800001 SDR0_UART1 = 20000026
SDR0_CP440 = 1EAAEA00 SDR0_XCR = C1A00000 SDR0_XPLLC = 000002B8 SDR0_XPLLD = 010A0000
SDR0_SRST = 00000000 SDR0_SLPIPE = F0000000 SDR0_AMP = 00000000 SDR0_MIRQ0 = 00000000
SDR0_MIRQ1 = 00000000 SDR0_MALTBL = 55550000 SDR0_MALRBL = 55550000 SDR0_MALTBS = F0000000
SDR0_MALRBS = F0000000 SDR0_CUST0 = FFFFFFFF SDR0_SDSTP2 = 00000000 SDR0_CUST1 = FFFFFFFF
SDR0_SDSTP3 = 00000000 SDR0_PFC0 = 083FFE00 SDR0_PFC1 = 01200000 SDR0_PLBTR = 000001B0
SDR0_MFR = 00000000 SDR0_CFGADDR = 00004100 SDR0_CFGDATA = 083FFE00
CACHE register Group. (CACHE)
ICDBDR = 00C00000 ICDBTRH = C0000000 ICDBTRL = 00000001 DCDBTRH = BBFFFF88
DCDBTRL = 0007BFE0 DNV0 = 32370237 DNV1 = 0F20191D DNV2 = 033C2300
DNV3 = 071D3532 DTV0 = 00000000 DTV1 = 00000000 DTV2 = 00000000
DTV3 = 00000000 DVLIM = 0001F800 INV0 = 01010000 INV1 = 00000000
INV2 = 00000000 INV3 = 00000000 ITV0 = 00000000 ITV1 = 00000000
ITV2 = 00000000 ITV3 = 00000000 IVLIM = 0001F800
L2CACHE register Group. (L2CACHE)
L2C0_CFG = E1A70080 L2C0_CMD = 00000000 L2C0_ADDR = 00000000 L2C0_DATA = 00000000
L2C0_SR = 88000000 L2C0_REVID = 00000101 L2C0_SNP0 = 0000F800 L2C0_SNP1 = 8000F800
TLB register Group. (TLB)
TLB0PID = 00000000 TLB0WORD0 = 00000000 TLB0WORD1 = 00000000 TLB0WORD2 = 00000000
TLB1PID = 00000000 TLB1WORD0 = FDFFF210 TLB1WORD1 = 0EC80002 TLB1WORD2 = 00000503
TLB2PID = 00000000 TLB2WORD0 = FDFED210 TLB2WORD1 = 40000001 TLB2WORD2 = 00000503
TLB3PID = 00000000 TLB3WORD0 = D1000210 TLB3WORD1 = 40000001 TLB3WORD2 = 00000503
TLB4PID = 00000000 TLB4WORD0 = 00000000 TLB4WORD1 = 00000000 TLB4WORD2 = 00000000
TLB5PID = 00000000 TLB5WORD0 = 00000000 TLB5WORD1 = 00000000 TLB5WORD2 = 00000000
TLB6PID = 00000000 TLB6WORD0 = 00000000 TLB6WORD1 = 00000000 TLB6WORD2 = 00000000
TLB7PID = 00000000 TLB7WORD0 = 00000000 TLB7WORD1 = 00000000 TLB7WORD2 = 00000000
TLB8PID = 00000000 TLB8WORD0 = 00000000 TLB8WORD1 = 00000000 TLB8WORD2 = 00000000
TLB9PID = 00000000 TLB9WORD0 = 00000000 TLB9WORD1 = 00000000 TLB9WORD2 = 00000000
TLB10PID = 00000000 TLB10WORD0 = 00000000 TLB10WORD1 = 00000000 TLB10WORD2 = 00000000
TLB11PID = 00000000 TLB11WORD0 = 00000000 TLB11WORD1 = 00000000 TLB11WORD2 = 00000000
TLB12PID = 00000000 TLB12WORD0 = 00000000 TLB12WORD1 = 00000000 TLB12WORD2 = 00000000
TLB13PID = 00000000 TLB13WORD0 = 00000000 TLB13WORD1 = 00000000 TLB13WORD2 = 00000000
TLB14PID = 00000000 TLB14WORD0 = 00000000 TLB14WORD1 = 00000000 TLB14WORD2 = 00000000
TLB15PID = 00000000 TLB15WORD0 = 00000000 TLB15WORD1 = 00000000 TLB15WORD2 = 00000000
TLB16PID = 00000000 TLB16WORD0 = 00000000 TLB16WORD1 = 00000000 TLB16WORD2 = 00000000
TLB17PID = 00000000 TLB17WORD0 = 00000000 TLB17WORD1 = 00000000 TLB17WORD2 = 00000000
TLB18PID = 00000000 TLB18WORD0 = 00000000 TLB18WORD1 = 00000000 TLB18WORD2 = 00000000
TLB19PID = 00000000 TLB19WORD0 = 00000000 TLB19WORD1 = 00000000 TLB19WORD2 = 00000000
TLB20PID = 00000000 TLB20WORD0 = 00000000 TLB20WORD1 = 00000000 TLB20WORD2 = 00000000
TLB21PID = 00000000 TLB21WORD0 = 00000000 TLB21WORD1 = 00000000 TLB21WORD2 = 00000000
TLB22PID = 00000000 TLB22WORD0 = 00000000 TLB22WORD1 = 00000000 TLB22WORD2 = 00000000
TLB23PID = 00000000 TLB23WORD0 = 00000000 TLB23WORD1 = 00000000 TLB23WORD2 = 00000000
TLB24PID = 00000000 TLB24WORD0 = 00000000 TLB24WORD1 = 00000000 TLB24WORD2 = 00000000
TLB25PID = 00000000 TLB25WORD0 = 00000000 TLB25WORD1 = 00000000 TLB25WORD2 = 00000000
TLB26PID = 00000000 TLB26WORD0 = 00000000 TLB26WORD1 = 00000000 TLB26WORD2 = 00000000
TLB27PID = 00000000 TLB27WORD0 = 00000000 TLB27WORD1 = 00000000 TLB27WORD2 = 00000000
TLB28PID = 00000000 TLB28WORD0 = 00000000 TLB28WORD1 = 00000000 TLB28WORD2 = 00000000
TLB29PID = 00000000 TLB29WORD0 = 00000000 TLB29WORD1 = 00000000 TLB29WORD2 = 00000000
TLB30PID = 00000000 TLB30WORD0 = 00000000 TLB30WORD1 = 00000000 TLB30WORD2 = 00000000
TLB31PID = 00000000 TLB31WORD0 = 00000000 TLB31WORD1 = 00000000 TLB31WORD2 = 00000000
TLB32PID = 00000000 TLB32WORD0 = 00000000 TLB32WORD1 = 00000000 TLB32WORD2 = 00000000
TLB33PID = 00000000 TLB33WORD0 = 00000000 TLB33WORD1 = 00000000 TLB33WORD2 = 00000000
TLB34PID = 00000000 TLB34WORD0 = 00000000 TLB34WORD1 = 00000000 TLB34WORD2 = 00000000
TLB35PID = 00000000 TLB35WORD0 = 00000000 TLB35WORD1 = 00000000 TLB35WORD2 = 00000000
TLB36PID = 00000000 TLB36WORD0 = 00000000 TLB36WORD1 = 00000000 TLB36WORD2 = 00000000
TLB37PID = 00000000 TLB37WORD0 = 00000000 TLB37WORD1 = 00000000 TLB37WORD2 = 00000000
TLB38PID = 00000000 TLB38WORD0 = 00000000 TLB38WORD1 = 00000000 TLB38WORD2 = 00000000
TLB39PID = 00000000 TLB39WORD0 = 00000000 TLB39WORD1 = 00000000 TLB39WORD2 = 00000000
TLB40PID = 00000000 TLB40WORD0 = 00000000 TLB40WORD1 = 00000000 TLB40WORD2 = 00000000
TLB41PID = 00000000 TLB41WORD0 = 00000000 TLB41WORD1 = 00000000 TLB41WORD2 = 00000000
TLB42PID = 00000000 TLB42WORD0 = 00000000 TLB42WORD1 = 00000000 TLB42WORD2 = 00000000
TLB43PID = 00000000 TLB43WORD0 = 00000000 TLB43WORD1 = 00000000 TLB43WORD2 = 00000000
TLB44PID = 00000000 TLB44WORD0 = 00000000 TLB44WORD1 = 00000000 TLB44WORD2 = 00000000
TLB45PID = 00000000 TLB45WORD0 = 00000000 TLB45WORD1 = 00000000 TLB45WORD2 = 00000000
TLB46PID = 00000000 TLB46WORD0 = 00000000 TLB46WORD1 = 00000000 TLB46WORD2 = 00000000
TLB47PID = 00000000 TLB47WORD0 = 00000000 TLB47WORD1 = 00000000 TLB47WORD2 = 00000000
TLB48PID = 00000000 TLB48WORD0 = 00000000 TLB48WORD1 = 00000000 TLB48WORD2 = 00000000
TLB49PID = 00000000 TLB49WORD0 = 00000000 TLB49WORD1 = 00000000 TLB49WORD2 = 00000000
TLB50PID = 00000000 TLB50WORD0 = 00000000 TLB50WORD1 = 00000000 TLB50WORD2 = 00000000
TLB51PID = 00000000 TLB51WORD0 = 00000000 TLB51WORD1 = 00000000 TLB51WORD2 = 00000000
TLB52PID = 00000000 TLB52WORD0 = 00000000 TLB52WORD1 = 00000000 TLB52WORD2 = 00000000
TLB53PID = 00000000 TLB53WORD0 = 00000000 TLB53WORD1 = 00000000 TLB53WORD2 = 00000000
TLB54PID = 00000000 TLB54WORD0 = 00000000 TLB54WORD1 = 00000000 TLB54WORD2 = 00000000
TLB55PID = 00000000 TLB55WORD0 = 00000000 TLB55WORD1 = 00000000 TLB55WORD2 = 00000000
TLB56PID = 00000000 TLB56WORD0 = 00000000 TLB56WORD1 = 00000000 TLB56WORD2 = 00000000
TLB57PID = 00000000 TLB57WORD0 = 00000000 TLB57WORD1 = 00000000 TLB57WORD2 = 00000000
TLB58PID = 00000000 TLB58WORD0 = 00000000 TLB58WORD1 = 00000000 TLB58WORD2 = 00000000
TLB59PID = 00000000 TLB59WORD0 = 00000000 TLB59WORD1 = 00000000 TLB59WORD2 = 00000000
TLB60PID = 00000000 TLB60WORD0 = 00000000 TLB60WORD1 = 00000000 TLB60WORD2 = 00000000
TLB61PID = 00000000 TLB61WORD0 = 00000000 TLB61WORD1 = 00000000 TLB61WORD2 = 00000000
TLB62PID = 00000000 TLB62WORD0 = 00000000 TLB62WORD1 = 00000000 TLB62WORD2 = 00000000
TLB63PID = 00000000 TLB63WORD0 = C0000290 TLB63WORD1 = 00000000 TLB63WORD2 = 00000107
SRAM0 register Group. (SRAM0)
SRAM0_SB0CR = 80000800 SRAM0_SB1CR = 80010800 SRAM0_SB2CR = 80020800 SRAM0_SB3CR = 80030800
SRAM0_BEAR = 00000000 SRAM0_BESR0 = 00000000 SRAM0_BESR1 = 00000000 SRAM0_PMEG = 01E00000
SRAM0_CID = 322B0000 SRAM0_REVID = 04005800 SRAM0_DPC = 00000000
EBC0 register Group. (EBC0)
EBC0_CFG = 17004000 EBC0_B0CR = FF09A000 EBC0_B1CR = F001A000 EBC0_B2CR = F0118000
EBC0_B3CR = F0218000 EBC0_B4CR = F031A000 EBC0_B5CR = F041E000 EBC0_B6CR = F0518000
EBC0_B7CR = F0F18000 EBC0_B0AP = 9B015400 EBC0_B1AP = 9B055480 EBC0_B2AP = 1B015480
EBC0_B3AP = 12815280 EBC0_B4AP = 12815400 EBC0_B5AP = 1B015400 EBC0_B6AP = 00000000
EBC0_B7AP = 010502C0 EBC0_BEAR = 00000000 EBC0_BESR = 00000000 EBC0_CID = 32401093
EBC0_CFGADDR = 00000017 EBC0_CFGDATA = 010502C0
EBMI register Group. (EBMI)
EBM0_CTL = 88400000 EBM0_LCNT = 00000000 EBM0_BEAR = 00000000 EBM0_BESR = 00000000
EBM0_BEMR = 00000000 EBM0_UAR = 00000000 EBM0_UAM = 00000000 EBM0_SLPMD = 07C00000
EBM0_FAIR = FFF00000 EBM0_MISCSTS = 36000008 EBM0_CID = 32501054 EBM0_CFGADDR = 00000000
EBM0_CFGDATA = 88400000
SDRAM0 register Group. (SDRAM0)
SDRAM0_BESR0 = 00000000 SDRAM0_BESR1 = 00000000 SDRAM0_BEAR = 00000000 SDRAM0_MIRQ = 00000000
SDRAM0_UABBA = 00000000 SDRAM0_SLIO = 00000000 SDRAM0_DEVOPT = 00000000 SDRAM0_WDDCTR = 00000000
SDRAM0_CLKTR = 40000000 SDRAM0_CFG0A = 86000000 SDRAM0_CFG1 = 00000000 SDRAM0_PMIT = 07C00000
SDRAM0_TR0 = 410A4016 SDRAM0_TR1 = 80800828 SDRAM0_RTR = 04B00000 SDRAM0_B0CR = 000C4001
SDRAM0_B1CR = 00000000 SDRAM0_B2CR = 00000000 SDRAM0_B3CR = 00000000 SDRAM0_DLYCAL = 200000B0
SDRAM0_ECCESR = 00000000 SDRAM0_CID = 320B0000 SDRAM0_RID = 00003101 SDRAM0_CFG0B = 86000000
SDRAM0_MCSTS = A0000000 SDRAM0_CFGADDR = 0000004C SDRAM0_CFGDATA = 00000000
OCBUSES register Group. (OCBUSES)
PLB0_REVID = 00000101 PLB0_ACR = 9B000000 PLB0_BESR = 00000000 PLB0_BEARL = F77FFFFF
PLB0_BEARH = FDFFFFFF POB0_BESR0 = 00000000 POB0_BEARL = 00000000 POB0_BEARH = 00000000
POB0_BESR1 = 00000000 POB0_CONFG = 00000000 POB0_LATENCY = 78000000 POB0_REVID = 00000122
OPB0_BCTRL = 00000000 OPB0_BSTAT = 00000000 OPB0_BEARL = FFFFFFFF OPB0_BEARH = 0000000F
OPB0_REVID = 00000130
IVOR register Group. (IVOR)
IVOR0 = 00000240 IVOR1 = 00000340 IVOR2 = 00000460 IVOR3 = 00000560
IVOR4 = 00000620 IVOR5 = 000006E0 IVOR6 = 000007A0 IVOR7 = 00000860
IVOR8 = 00000920 IVOR9 = 000009E0 IVOR10 = 00000AA0 IVOR11 = 00000B60
IVOR12 = 00000C20 IVOR13 = 00000D20 IVOR14 = 00000DC0 IVOR15 = 00000E60
UIC register Group. (UIC)
UIC0_SR = 00000040 UIC0_ER = 00000000 UIC0_CR = 00000000 UIC0_PR = FFFFFE13
UIC0_TR = 01C00040 UIC0_MSR = 00000000 UIC0_VR = 00000000 UIC0_VCR = 00000040
UIC1_SR = 00002700 UIC1_ER = 00000000 UIC1_CR = 00000000 UIC1_PR = FFFFE0FF
UIC1_TR = 00FFC000 UIC1_MSR = 00000000 UIC1_VR = 00000000 UIC1_VCR = 00002700
UIC2_SR = 00000000 UIC2_ER = 00000100 UIC2_CR = 00000000 UIC2_PR = FFFFFFFF
UIC2_TR = 00FF8D0F UIC2_MSR = 00000000 UIC2_VR = 00000000 UIC2_VCR = 00000000
UICB0_SR = 03FFFFFF UICB0_ER = 54000000 UICB0_CR = 00000000 UICB0_PR = FC000000
UICB0_TR = 00000000 UICB0_MSR = 00000000 UICB0_VR = 00000000 UICB0_VCR = 03FFFFFF
DMA0 register Group. (DMA0)
DMA0_CR0 = 00000000 DMA0_CT0 = 00000000 DMA0_SAH0 = 00000000 DMA0_SAL0 = 00000000
DMA0_DAH0 = 00000000 DMA0_DAL0 = 00000000 DMA0_SGH0 = 00000000 DMA0_SGL0 = 00000000
DMA0_CR1 = 00000000 DMA0_CT1 = 00000000 DMA0_SAH1 = 00000000 DMA0_SAL1 = 00000000
DMA0_DAH1 = 00000000 DMA0_DAL1 = 00000000 DMA0_SGH1 = 00000000 DMA0_SGL1 = 00000000
DMA0_CR2 = 00000000 DMA0_CT2 = 00000000 DMA0_SAH2 = 00000000 DMA0_SAL2 = 00000000
DMA0_DAH2 = 00000000 DMA0_DAL2 = 00000000 DMA0_SGH2 = 00000000 DMA0_SGL2 = 00000000
DMA0_CR3 = 00000000 DMA0_CT3 = 00000000 DMA0_SAH3 = 00000000 DMA0_SAL3 = 00000000
DMA0_DAH3 = 00000000 DMA0_DAL3 = 00000000 DMA0_SGH3 = 00000000 DMA0_SGL3 = 00000000
DMA0_SR = 00008000 DMA0_SGC = 00000000 DMA0_SLP = 07C00000 DMA0_POL = 00000000
MAL0 register Group. (MAL0)
MAL0_CFG = 0037C086 MAL0_ESR = 00000000 MAL0_IER = 00000017 MAL0_TXCASR = 00000000
MAL0_TXCARR = 00000000 MAL0_TXEOBISR = 00000000 MAL0_TXDEIR = 00000000 MAL0_RXCASR = 00000000
MAL0_RXCARR = 00000000 MAL0_RXEOBISR = 00000000 MAL0_RXDEIR = 00000000 MAL0_TXCTP0R = 00000000
MAL0_TXCTP1R = 00000000 MAL0_TXCTP2R = 0FFA1340 MAL0_TXCTP3R = 00000000 MAL0_RXCTP0R = 00000000
MAL0_RXCTP1R = 00000000 MAL0_RXCTP2R = 0FFA13A0 MAL0_RXCTP3R = 00000000 MAL0_RCBS0 = 00000000
MAL0_RCBS1 = 00000000 MAL0_RCBS2 = 00000060 MAL0_RCBS3 = 00000000 MAL0_TXBADDR = 00000000
MAL0_RXBADDR = 00000000
PPM0 register Group. (PPM0)
PPM0_ISR = 00000000 PPM0_CR = 00000000 PPM0_CCR = FFFFFFFF PPM0_UAR = 00000000
PPM0_LAR = 00000000 PPM0_UAMR = FFFFFFFF PPM0_LAMR = FFFFFFFF PPM0_RIDR = C27E3411
PPM0_MCSR0 = 00000000 PPM0_MCSR1 = 00000000 PPM0_MCSR2 = 00000000 PPM0_MCSR3 = 00000000
PPM0_SCSR0 = 00000000 PPM0_SCSR1 = 00000000 PPM0_SCSR2 = 00000000 PPM0_SCSR3 = 00000000
PPM0_GCSR0 = 00000000 PPM0_GCSR1 = 00000000 PPM0_GCSR2 = 00000000 PPM0_GCSR3 = 00000000
PPM0_MCR0 = 00000000 PPM0_MCR1 = 00000000 PPM0_MCR2 = 00000000 PPM0_MCR3 = 00000000
PPM0_SCR0 = 00000000 PPM0_SCR1 = 00000000 PPM0_SCR2 = 00000000 PPM0_SCR3 = 00000000
PPM0_GCR0 = 00000000 PPM0_GCR1 = 00000000 PPM0_GCR2 = 00000000 PPM0_GCR3 = 00000000
PPM0_DCSR0 = 00000000 PPM0_DCSR1 = 00000000 PPM0_DCMXR0 = 00000000 PPM0_DCMXR1 = 00000000
PPM0_DCMNR0 = 00FFFFFF PPM0_DCMNR1 = 00FFFFFF PPM0_DCTVR0 = 00000000 PPM0_DCTVR1 = 00000000
PPM0_DCOTR0 = 00000000 PPM0_DCOTR1 = 00000000 PPM0_CFGADDR = 00000000 PPM0_CFGDATA = 00000000
^ permalink raw reply
* [PATCH 0/4] PowerPC: more Sequoia/Rainier updates for 2.6.25
From: Valentine Barshak @ 2007-12-21 16:07 UTC (permalink / raw)
To: linuxppc-dev
This patch series has a couple of PowerPC 440EPx/GRx fixes and
adds PCI to Sequoia/Rainier DTS.
Thanks,
Valentine.
^ permalink raw reply
* [PATCH 1/4] PowerPC: Correct 440GRx machine_check callback
From: Valentine Barshak @ 2007-12-21 16:22 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071221160723.GA1430@ru.mvista.com>
Correct the PowerPC 440GRx machine check callback.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
arch/powerpc/kernel/cputable.c | 2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
diff -pruN linux-2.6.orig/arch/powerpc/kernel/cputable.c linux-2.6/arch/powerpc/kernel/cputable.c
--- linux-2.6.orig/arch/powerpc/kernel/cputable.c 2007-12-21 17:14:17.000000000 +0300
+++ linux-2.6/arch/powerpc/kernel/cputable.c 2007-12-21 18:05:08.000000000 +0300
@@ -1247,7 +1247,7 @@ static struct cpu_spec __initdata cpu_sp
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_440grx,
- .machine_check = machine_check_4xx,
+ .machine_check = machine_check_440A,
.platform = "ppc440",
},
{ /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
^ permalink raw reply
* RE: [techfield] GPIO causing bus error
From: Elayda, Bernardo (Bernie) @ 2007-12-21 16:27 UTC (permalink / raw)
To: +techfield, Wyse, Chris, linuxppc-dev, linuxppc-embedded,
+linux-embedded, +linux-eng, linux-kernel, Wessel, Jason, support
Cc: Slimm, Rob, Read, Tricia, Ayer, Charles, Touron, Emmanuel
In-Reply-To: <AF1602CB2550CE4381C0C75118A7856B020C60D7@ala-mail02.corp.ad.wrs.com>
[-- Attachment #1: Type: text/plain, Size: 5858 bytes --]
Hi Chris,
I'm going to look at this problem from the FPGA hardware level because I
used to work for one of the FPGA companies.
I'm not familiar with your PPC440GX board, so some of my suggestions may
be difficult to implement or totally unreasonable, especially if it
requires soldering to an FPGA in a ball grid array or extermely fine
pitch pins.
(1) You should capture the configuration sequence on FPGA's JTAG pins
using a logic analyzer in functional mode.
In functional mode, you can capture an extermely long sequence of
configuration events. Also, in the past, I've used this mode and found
that when the FPGA doesn't configure, usually there are too few or too
many clocks on the TCK line.
(2) Sometimes, rarely, the FPGA design itself can cause a boot up
problem.
Instead of using the real design, send a 'blank' design with no logic
implemented at all. If this works, then it's the FPGA design itself
that is causing the boot problem.
(3) When the boot process happens, what is the power sequence of the
FPGA?
Most FPGA's out there like a nice smooth power profile that ramps up
quickly. Check and see if the profile is quick and smooth vs. spikey
and erratic. Also, sometimes configuration data gets sent before the
FPGA is ready to receive data. Try delaying the sending of
configuration data by a millisecond or so.
(4) Manually delay the configuration of the FPGA.
In other words, let the system boot, but modify the code to allow the
FPGA to configure only after a button is pushed. In theory, if the FPGA
power has properply initialized the FPGA, you could keep the system this
way forever until a 'button' is pushed to configure the FPGA. if this
works, this tends to imply that there is a timing issue. If it doesn't
work, it's possible that the FPGA's JTAG tap is actually in a state that
won't allow configuration to complete, such as non shift-dr or non
shift-ir state.
(5) If your FPGA is using one of the SVF-based software configuration
methods via JTAG, make sure you are using the latest SVF player and
latest software for generating the FPGA bitstream. The configuration
method may have changed. The FPGA silicon you are using may be newer
than the configuration algorithm that has been implemented.
I hope this helps!
Regards,
Bernie Elayda
the ex-X guy
________________________________
From: owner-techfield@windriver.com
[mailto:owner-techfield@windriver.com] On Behalf Of Wyse, Chris
Sent: Friday, December 21, 2007 7:55 AM
To: linuxppc-dev@ozlabs.org; linuxppc-embedded@ozlabs.org; +techfield;
+linux-embedded; +linux-eng; linux-kernel; Wessel, Jason;
support@amcc.com
Cc: Touron, Emmanuel; Read, Tricia; Ayer, Charles; Slimm, Rob
Subject: [techfield] GPIO causing bus error
Hi,
I'm having trouble with an unusual problem. I'm working on relatively
new hardware, so it's possible that there could be a hardware issue
involved.
I have an FPGA on my PPC440GX board that gets loaded via JTAG during the
kernel boot process (Linux 2.6.10). It uses the 440GX GPIO lines to
send the necessary JTAG commands to the FPGA to perform the initial
load. This process is USUALLY functional, but on some of the boards
(which we produce), the GPIO write fails with a bus error. On the
boards that fail, it only occurs after a cold boot, and only if the
board has been powered off for a few minutes. A quick hard reboot will
not generate the problem. When I issue the failing write to the GPIO
lines, some of the SDRAM gets corrupted. I don't appear to be taking
any interrupts that might have corrupted the RAM.
I've checked the TLB entries, and it maps correctly to the PPC register
area. Additionally, I can read and write to other registers using the
same TLB mapping WITHOUT any error. I can also READ the GPIO lines
without an error - the error is only on the write. I've checked the
SDR0_PFC0 bits to make sure everything is set properly (it is). The bus
error indicates "PLB Timeout Error Status Master 2, Master 2 slave error
occurred" (Master 2 is the write-only data cache unit (DCU)) and "Write
Error Interrupt Master 2, Write error detected - master 2 interrupt
request is active". I'm not sure why there would be any error in the
DCU, since the region I'm writing to is cache inhibited and guarded.
If I issue a soft reset of the GPIO subsystem, I can read and write to
the GPIO lines again.
The error does not occur on the first write to the GPIO. I go through
the failing routine several times before it fails. However, when it
fails, it consistently fails at the same spot, after the same number of
passes through the code.
I'm using RGMII ethernet on EMAC2 (Group 4), but the GPIO lines that I'm
using are not the Trace/GPIO lines (26-31) so I believe that they should
work fine (and they usually do). Also, the errata mentions that
SDR0_PFC0[G11E] has no effect - but I'm not using GPIO 11 anyway.
Here are some relevant register values after the error:
SDR0_PFC0 : 0x083FFE00
POB0_BESR0: 0x00008400
POB0_BEARH: 0x00000001
POB0_BEARL: 0x40000701
GPIO0_OR : 0x000400C0
GPIO0_TCR : 0x00278AE0
GPIO0_ODR : 0x00000000
GPIO0_IR : 0x00000000
I've attached two log files, that contain most of the 440 registers, one
for before the error and one after. In the log files, the bus error has
been cleared, so use the values shown above.
I'm looking for some suggestions on what to try to debug/resolve this
issue. I'm open to both hardware and software based suggestions. Any
help would be greatly appreciated.
Chris Wyse
Senior Member of Technical Staff
Embedded Technologies
860-978-0849 cell/office
413-778-9101 fax
http://www.windriver.com <http://www.windriver.com/>
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