* Re: Yet more patches added to for-2.6.25/master branches
From: Grant Likely @ 2007-12-21 18:13 UTC (permalink / raw)
To: Marian Balakowicz; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <476C00C9.8080107@semihalf.com>
On 12/21/07, Marian Balakowicz <m8@semihalf.com> wrote:
> Grant Likely wrote:
> >
> > On 12/21/07, *Marian Balakowicz* <m8@semihalf.com
> >
> > Any changes to add new 52xx targets:
> >
> > http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
> [...]
> >
> > Those did not make it to 2.6.24, Grant Likely suggested to wait until
> > 2.6.25 window opens.
> >
> >
> > I'll be picking these up next week. I haven't had time to do it earlier.
>
> Great, I'll retest the set with the latest vanilla next week.
Actually, you should retest against Paulus' latest tree instead
because that is what it will be merged against.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: Yet more patches added to for-2.6.25/master branches
From: Marian Balakowicz @ 2007-12-21 18:07 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <fa686aa40712210934s607ab3c3x6374d2850b9e987a@mail.gmail.com>
Grant Likely wrote:
>
> On 12/21/07, *Marian Balakowicz* <m8@semihalf.com
>
> Any changes to add new 52xx targets:
>
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
[...]
>
> Those did not make it to 2.6.24, Grant Likely suggested to wait until
> 2.6.25 window opens.
>
>
> I'll be picking these up next week. I haven't had time to do it earlier.
Great, I'll retest the set with the latest vanilla next week.
Thanks,
Marian
^ permalink raw reply
* [PATCH 4/4] PowerPC: Add PCI entry to 440GRx Rainier DTS.
From: Valentine Barshak @ 2007-12-21 17:22 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <476BF5B7.3030201@ru.mvista.com>
This adds PCI entry to PowerPC 440GRx Rainier DTS.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
arch/powerpc/boot/dts/rainier.dts | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+)
--- linux-2.6.orig/arch/powerpc/boot/dts/rainier.dts 2007-12-19 16:00:01.000000000 +0300
+++ linux-2.6/arch/powerpc/boot/dts/rainier.dts 2007-12-20 21:59:42.000000000 +0300
@@ -317,6 +317,33 @@
has-new-stacr-staopc;
};
};
+
+ PCI0: pci@1ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
+ primary;
+ reg = <1 eec00000 8 /* Config space access */
+ 1 eed00000 4 /* IACK */
+ 1 eed00000 4 /* Special cycle */
+ 1 ef400000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 80000000 1 80000000 0 10000000
+ 01000000 0 00000000 1 e8000000 0 00100000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* All PCI interrupts are routed to IRQ 67 */
+ interrupt-map-mask = <0000 0 0 0>;
+ interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
+ };
};
chosen {
^ permalink raw reply
* Re: [PATCH -mm 18/43] powerpc compat_binfmt_elf
From: Kyle McMartin @ 2007-12-21 17:51 UTC (permalink / raw)
To: Roland McGrath
Cc: linux-arch, linux-kernel, Christoph Hellwig, linuxppc-dev,
Paul Mackerras, Andrew Morton, Linus Torvalds
In-Reply-To: <20071221085609.4D53B26F98A@magilla.localdomain>
On Fri, Dec 21, 2007 at 12:56:09AM -0800, Roland McGrath wrote:
> > On Thu, Dec 20, 2007 at 03:58:16AM -0800, Roland McGrath wrote:
> > > +obj-$(CONFIG_PPC64) += ../../../fs/compat_binfmt_elf.o
> >
> > Building files from another directory is nasty. Please add a
> > CONFIG_BINFMT_COMPAT_ELF so we can simply build it in fs/
>
> If that's better, please post the precise Kconfig magic you have in mind to
> have it set when it should be.
>
Just taking a stab that hch means,
config BINFMT_COMPAT_ELF
def_bool n
depends on 64BIT
and then in arch/powerpc/Kconfig
config COMPAT
bool
default y if PPC64
select BINFMT_COMPAT_ELF
or somesuch.
Regards, Kyle
^ permalink raw reply
* Re: [PATCH 3/4] sbc8560: Add device tree source for Wind River SBC8560 board
From: Scott Wood @ 2007-12-21 17:40 UTC (permalink / raw)
To: Paul Gortmaker, linuxppc-dev
In-Reply-To: <20071220235724.GA2665@localhost.localdomain>
On Fri, Dec 21, 2007 at 10:57:24AM +1100, David Gibson wrote:
> > + mpic: pic@40000 {
> > + clock-frequency = <0>;
>
> The mpic has a clock-frequency??
Yes, there's a timer on the PIC.
> > + interrupt-controller;
> > + #address-cells = <0>;
>
> Should have #size-cells = <0> too.
This is debatable. :-)
-Scott
^ permalink raw reply
* Re: Yet more patches added to for-2.6.25/master branches
From: Grant Likely @ 2007-12-21 17:34 UTC (permalink / raw)
To: Marian Balakowicz; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <476BCA09.3070104@semihalf.com>
[-- Attachment #1: Type: text/plain, Size: 1236 bytes --]
On 12/21/07, Marian Balakowicz <m8@semihalf.com> wrote:
>
>
> Any changes to add new 52xx targets:
>
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14661
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14662
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14663
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14743
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14665
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14666
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14667
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14668
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14669
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14670
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14671
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14672
> http://patchwork.ozlabs.org/linuxppc/patch?person=988&id=14673
>
> Those did not make it to 2.6.24, Grant Likely suggested to wait until
> 2.6.25 window opens.
I'll be picking these up next week. I haven't had time to do it earlier.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
[-- Attachment #2: Type: text/html, Size: 2744 bytes --]
^ permalink raw reply
* Re: [PATCH 0/4] arch/powerpc support for SBC8560 board
From: Scott Wood @ 2007-12-21 17:31 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev, david
In-Reply-To: <20071221033815.GA13921@windriver.com>
On Thu, Dec 20, 2007 at 10:38:15PM -0500, Paul Gortmaker wrote:
> Here is my interpretation of what is happening here -- we come in via
> find_legacy_serial_ports() to pick a console port. It grabs "chosen"
> to get np stdout, and then checks the parent of the 16550 compat ports
> against the following, requiring at least one of them to match:
>
> parent->type == "soc" ? add_legacy_soc_port()
>
> parent->type == "isa" ? add_legacy_isa_port()
>
> parent->type == "tsi-bridge" ? add_legacy_soc_port()
>
> parent->type == "opb" ? add_legacy_soc_port()
We should probably add a parent-is-compatible-with-"simple-bus" check, to
avoid needing to extend this hack even further.
> > Out of interest how exactly are the duart's wired on the 8560. Are they
> > off localbus?
>
> The board has a bunch of stuff hanging off of CS5 -- an RTC, a 7 segment
> display, an EEPROM, some BCSR-like registers, and of course the two
> UARTs which are supposed to be 16C2550. According to TFM, an EPM7128
> PLD is responsible for mashing/sub-decoding this all onto/off of CS5.
> CS3 and CS4 are the LB-SDRAM.
I'd put these devices under a /localbus node.
-Scott
^ permalink raw reply
* Re: Time for cell code reshuffle?
From: Geoff Levand @ 2007-12-21 17:23 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev, Paul Mackerras, cbe-oss-dev, Jeremy Kerr
In-Reply-To: <200712211522.03841.arnd@arndb.de>
Arnd Bergmann wrote:
> We've been discussing in the past a few times where we should best put
> the spufs code, and when to do it. Since Jeremy and I now have all the
> current patches in powerpc.git, maybe we should do it now.
>
> To the question, where what it should go, I'd leave the decision to
> Jeremy, but my current idea would be:
>
> arch/powerpc/platforms/cell/spufs -> arch/powerpc/spufs
> arch/powerpc/platforms/cell/spu_{callbacks,base,syscalls,fault,notify}.[co]
> -> arch/powerpc/spufs/{callbacks,base,syscalls,fault,notify}.[co]
I think we should consider support for SpursEngine. At the moment I have no
idea of what it needs, and if no one else does we need to find out.
> If we do it in git now, that should result in a minimal breakage of patches.
>
> A related question is what to do about the location of the other cell
> related files. platforms/ps3 is already pretty self-contained once we have
> spufs outside of platforms/cell, but there is still some code shared between
> platforms/cell and platforms/celleb, and each of these directories also contains
> code that is only relevant for a subset of the platforms.
It seems platforms/cell should have the shared and/or generic code, and the other
stuff moved into a new platform directory, but is it worth the effort?
-Geoff
^ permalink raw reply
* Re: [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.
From: Valentine Barshak @ 2007-12-21 17:19 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071221162708.GA1724@ru.mvista.com>
> + reg = <1 eec00000 8 /* Config space access */
> + 1 eed80000 4 /* IACK */
> + 1 eed80000 4 /* Special cycle */
Please, discard this one, since it contains the typos pasted from
previous bamboo dts, which have been fixed :).
I'll send the corrected patch right away.
Thanks,
Valentine.
^ permalink raw reply
* Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River SBC8548 board
From: Paul Gortmaker @ 2007-12-21 17:20 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <1ED67FCC-132F-4E9A-BDC9-41BF557FF0D6@kernel.crashing.org>
In message: Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River SBC8548 board
on 21/12/2007 Kumar Gala wrote:
>
> On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:
>
>> This adds the device tree source for the Wind River SBC8548 board.
[...]
> mind looking at converting this to a dts-v1 format?
>
> - k
I figured there might be value in having it as a separate commit, seeing
as there aren't that many other dts-v1 as a reference (yet). Not sure
if I've got all the v1 type changes in that you had in mind, but I fed
it through the latest dtc from git and fed it to the board and it still
seems happy with it.
I'll probably be away from e-mail after this afternoon for the holiday
period -- so thanks (everyone) for the feedback and whatever I don't
get to today, or any additional recommended changes I'll pick up in Jan.
P.
---
>From: Paul Gortmaker <paul.gortmaker@windriver.com>
>Date: Fri, 21 Dec 2007 12:11:17 -0500
>Subject: [PATCH] sbc8548: Convert device tree to be dts-v1 compatible
This converts the sbc8548 dts to be dts-v1 compatible. Tested with the
latest git pull of dtc (Dec 21/07).
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/boot/dts/sbc8548.dts | 122 +++++++++++++++++++------------------
1 files changed, 62 insertions(+), 60 deletions(-)
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index e63ed20..14be38a 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -12,6 +12,8 @@
*/
+/dts-v1/;
+
/ {
model = "SBC8548";
compatible = "SBC8548";
@@ -35,10 +37,10 @@
PowerPC,8548@0 {
device_type = "cpu";
reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ d-cache-line-size = <0x20>; // 32 bytes
+ i-cache-line-size = <0x20>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>;
clock-frequency = <0>;
@@ -47,31 +49,31 @@
memory {
device_type = "memory";
- reg = <00000000 10000000>;
+ reg = <0x00000000 0x10000000>;
};
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <00000000 e0000000 00100000>;
- reg = <e0000000 00001000>; // CCSRBAR
+ ranges = <0x00000000 0xe0000000 0x00100000>;
+ reg = <0xe0000000 0x00001000>; // CCSRBAR
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <0x12 0x2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <80000>; // L2, 512K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <0x20>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <0x10 0x2>;
};
i2c@3000 {
@@ -79,8 +81,8 @@
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@@ -90,8 +92,8 @@
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
- reg = <3100 100>;
- interrupts = <2b 2>;
+ reg = <0x3100 0x100>;
+ interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@@ -100,18 +102,18 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@19 {
interrupt-parent = <&mpic>;
- interrupts = <6 1>;
- reg = <19>;
+ interrupts = <0x6 0x1>;
+ reg = <0x19>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1a {
interrupt-parent = <&mpic>;
- interrupts = <7 1>;
- reg = <1a>;
+ interrupts = <0x7 0x1>;
+ reg = <0x1a>;
device_type = "ethernet-phy";
};
};
@@ -121,9 +123,9 @@
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
@@ -133,9 +135,9 @@
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
@@ -144,9 +146,9 @@
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>; // reg base, size
+ reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
};
@@ -154,15 +156,15 @@
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>; // reg base, size
+ reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities reg
compatible = "fsl,mpc8548-guts";
- reg = <e0000 1000>;
+ reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
@@ -171,7 +173,7 @@
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@@ -180,63 +182,63 @@
pci0: pci@e0008000 {
cell-index = <0>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x01 (PCI-X slot) */
- 00800 0 0 1 &mpic 0 1
- 00800 0 0 2 &mpic 1 1
- 00800 0 0 3 &mpic 2 1
- 00800 0 0 4 &mpic 3 1>;
+ 0x0800 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0800 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
+ interrupts = <0x18 0x2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00800000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+ 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0008000 1000>;
+ reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
pci2: pcie@e000a000 {
cell-index = <2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
- 00000 0 0 1 &mpic 0 1
- 00000 0 0 2 &mpic 1 1
- 00000 0 0 3 &mpic 2 1
- 00000 0 0 4 &mpic 3 1>;
+ 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 08000000>;
- clock-frequency = <1fca055>;
+ interrupts = <0x1a 0x2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;
+ clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e000a000 1000>;
+ reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 a0000000
- 02000000 0 a0000000
- 0 20000000
+ ranges = <0x02000000 0x0 0xa0000000
+ 0x02000000 0x0 0xa0000000
+ 0x0 0x20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 08000000>;
+ 0x01000000 0x0 0x00000000
+ 0x01000000 0x0 0x00000000
+ 0x0 0x08000000>;
};
};
};
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* OProfile callgraph support not working correctly on PPC processors
From: Bob Nelson @ 2007-12-21 17:15 UTC (permalink / raw)
To: linuxppc
I have been investigating why I have not been able to get callgraph code fo=
r=20
OProfile on Cell to work correctly and I am pretty sure that I have run int=
o=20
a problem that is common across all the Power platforms. (At least the oth=
er=20
ones I have looked at.) I have a simple test program that is attached=20
below. =A0It has a main, that calls function1, which calls function2. =A0Ea=
ch of=20
the functions has some type of loop in it so that I can catch it spending=20
some CPU time with OProfile. =A0I have also attached the objdump -d output =
for=20
the program cut down to the three pertinent functions that shows what is=20
happening. =A0In a nutshell when a terminal function (calls no other functi=
on)=20
is called the compiler is making an optimization that seems to break the AB=
I=20
convention as far as I can tell. =A0It does not store the Link Register on =
the=20
stack like any other function. It just leaves the return address in LR,=20
knowing that nothing should change it. =A0(You can see at the top of both m=
ain=20
and function1 the first thing it does is "mflr =A0r0" to copy the link regi=
ster=20
to R0 to be saved. It does not do that in function2.) =A0 When OProfile tak=
es=20
an interrupt and needs to gather the callgraph information it does so by=20
grabbing the process' stack pointer (R1) and follows the chain back up the=
=20
stack to gather all the caller's addresses. =A0This works for most function=
s,=20
except for terminal functions for the reason noted above.
Looking at the assembly listing I drew myself a diagram of the stack while=
=20
function2 is active to convince myself of what was wrong and here is what I=
=20
see it as... =A0When the interrupt is handled OProfile grabs a copy of R1, =
it=20
ignores the first frame on the stack because there should be no address=20
stored. =A0In the second frame it expects to find function2's caller but si=
nce=20
function2 doesn't store it, it grabs some random data and proceeds. The sta=
ck=20
chain is all ok so it doesn't go off into neverland trying to follow a bad=
=20
chain, but it grabs an invalid address for the caller. =A0And that is why=20
OProfile thinks terminal functions have no callers on PPC...
Any suggestions on how this can be fixed? =A0I am guessing that changing th=
e=20
compiler and recompiling every program is probably not the answer. I assum=
e=20
the link register has to be saved in the interrupt routine when it runs, or=
=20
else it couldn't call anything else without crashing the program that was=20
interrupted. Is there a safe place to find it?
Thanks, Bob Nelson
top of stack =A0 ------------------------------
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0|
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| <------------------------------
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0 =A0 =A0 =
=A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0R0 (link register) =A0 =A0 =A0| =A0=
=2D-> main's caller =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0 =A0 =A0 =
=A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0flags (unused) =A0 =A0 =A0 =A0 =A0|=
=A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------|=A0 =A0 =A0 =
=A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0R1 (previous frame) |>---------=
=2D---------------------
R1 main =A0 =A0 -> |----------------------------| 0 (Offset from R1 <----=
=2D-----
=A0 =A0(entry) =A0 =A0=A0| =A0 =A0R31 save =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|=
=A0 at entry to main) =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 |----------------------------| -8 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0|=A0 =A0 =A0 =A0 =A0 =A0 |=20
=A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0|
=A0 =A0 =A0 =A0 =A0 =A0 =A0 |----------------------------| =A0 =A0 =A0 =A0=
=A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0R0 (link register) =A0 =A0 =A0| =A0--=
>function1's caller (main) |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 |----------------------------| =A0 =A0 =
=A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0flags (not stored)=A0 =A0 =A0 |=A0 =
=A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 |----------------------------| =A0 =A0 =A0 =A0=
=A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0R1 (previous frame) |>-----------=
=2D-------------------
R1 function1-->|----------------------------| -144 <-----------------------=
=2D-
=A0 =A0(entry) =A0 =A0 | =A0 =A0R31 save =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =
=A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------|=A0 =A0 =A0 =
=A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0 =A0 =A0 =
=A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0nothing stored =A0 =A0 =A0 =A0 =A0|=
(should be function2's caller |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0function1)=
=A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0flags (not stored) =A0 =A0 =A0| =A0=
=A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0 =A0 =A0 =
=A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0R1 (previous frame) |>---------=
=2D---------------------
R1 function2-->|----------------------------| -288 <-----------------------=
=2D-
=A0 =A0(entry) =A0 =A0 | =A0 =A0R31 save =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =
=A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0 =A0 =A0 =
=A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0| =A0 =A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0 =A0 =A0 =
=A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0nothing stored =A0 =A0 =A0 =A0 =A0|=
=A0would be used if function2 =A0|
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0called any=
thing |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0flags (not stored) =A0 =A0 =A0| =A0=
=A0 =A0 =A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|----------------------------| =A0 =A0 =A0 =
=A0 =A0 =A0 |
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0 =A0R1 (previous frame) |>---------=
=2D---------------------
R1 function2-->|----------------------------| -368=A0 =A0(running)
| =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|
=A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 . =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0|
=A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0|
/* loop.c - nonsense code for testing OProfile */
#include <stdio.h>
int function2( int count )
{
int i, j, k;
for ( i=3D0; i<count; i++ )
{
k =3D k + j * i;
}
return k;
}
int function1( int count )
{
int i, j;
i =3D function2( count );
for ( j=3D0; j<1000; j++ ) i++;
return i;
}
int main( int argc, char *argv[] )
{
int count, i, j, k;
if ( argc > 0 )
count =3D atoi( argv[1] );
else
count =3D 10000;
for ( i=3D0; i<count; i++ )
{
j =3D function1( 10000 );
for( j=3D0; j<10000; j++ ) k =3D k + j;
}
return 0;
}
loop.64: file format elf64-powerpc
=2E.. deleted ...
00000000100005b0 <.function2>:
100005b0: fb e1 ff f8 std r31,-8(r1)
100005b4: f8 21 ff b1 stdu r1,-80(r1)
100005b8: 7c 3f 0b 78 mr r31,r1
100005bc: 7c 60 1b 78 mr r0,r3
100005c0: 90 1f 00 80 stw r0,128(r31)
100005c4: 38 00 00 00 li r0,0
100005c8: 90 1f 00 38 stw r0,56(r31)
100005cc: 48 00 00 2c b 100005f8 <.function2+0x48>
100005d0: 81 3f 00 34 lwz r9,52(r31)
100005d4: 80 1f 00 38 lwz r0,56(r31)
100005d8: 7c 09 01 d6 mullw r0,r9,r0
100005dc: 7c 09 07 b4 extsw r9,r0
100005e0: 80 1f 00 30 lwz r0,48(r31)
100005e4: 7c 00 4a 14 add r0,r0,r9
100005e8: 90 1f 00 30 stw r0,48(r31)
100005ec: 81 3f 00 38 lwz r9,56(r31)
100005f0: 38 09 00 01 addi r0,r9,1
100005f4: 90 1f 00 38 stw r0,56(r31)
100005f8: 80 1f 00 38 lwz r0,56(r31)
100005fc: 81 3f 00 80 lwz r9,128(r31)
10000600: 7f 80 48 00 cmpw cr7,r0,r9
10000604: 41 9c ff cc blt+ cr7,100005d0 <.function2+0x20>
10000608: 80 1f 00 30 lwz r0,48(r31)
1000060c: 7c 00 07 b4 extsw r0,r0
10000610: 7c 03 03 78 mr r3,r0
10000614: e8 21 00 00 ld r1,0(r1)
10000618: eb e1 ff f8 ld r31,-8(r1)
1000061c: 4e 80 00 20 blr
...
10000628: 80 01 00 01 lwz r0,1(r1)
000000001000062c <.function1>:
1000062c: 7c 08 02 a6 mflr r0
10000630: fb e1 ff f8 std r31,-8(r1)
10000634: f8 01 00 10 std r0,16(r1)
10000638: f8 21 ff 71 stdu r1,-144(r1)
1000063c: 7c 3f 0b 78 mr r31,r1
10000640: 7c 60 1b 78 mr r0,r3
10000644: 90 1f 00 c0 stw r0,192(r31)
10000648: 80 1f 00 c0 lwz r0,192(r31)
1000064c: 7c 00 07 b4 extsw r0,r0
10000650: 7c 03 03 78 mr r3,r0
10000654: 4b ff ff 5d bl 100005b0 <.function2>
10000658: 7c 60 1b 78 mr r0,r3
1000065c: 90 1f 00 74 stw r0,116(r31)
10000660: 38 00 00 00 li r0,0
10000664: 90 1f 00 70 stw r0,112(r31)
10000668: 48 00 00 1c b 10000684 <.function1+0x58>
1000066c: 81 3f 00 74 lwz r9,116(r31)
10000670: 38 09 00 01 addi r0,r9,1
10000674: 90 1f 00 74 stw r0,116(r31)
10000678: 81 3f 00 70 lwz r9,112(r31)
1000067c: 38 09 00 01 addi r0,r9,1
10000680: 90 1f 00 70 stw r0,112(r31)
10000684: 80 1f 00 70 lwz r0,112(r31)
10000688: 2f 80 03 e7 cmpwi cr7,r0,999
1000068c: 40 9d ff e0 ble+ cr7,1000066c <.function1+0x40>
10000690: 80 1f 00 74 lwz r0,116(r31)
10000694: 7c 00 07 b4 extsw r0,r0
10000698: 7c 03 03 78 mr r3,r0
1000069c: e8 21 00 00 ld r1,0(r1)
100006a0: e8 01 00 10 ld r0,16(r1)
100006a4: 7c 08 03 a6 mtlr r0
100006a8: eb e1 ff f8 ld r31,-8(r1)
100006ac: 4e 80 00 20 blr
100006b0: 00 00 00 00 .long 0x0
100006b4: 00 00 00 01 .long 0x1
100006b8: 80 01 00 01 lwz r0,1(r1)
00000000100006bc <.main>:
100006bc: 7c 08 02 a6 mflr r0
100006c0: fb e1 ff f8 std r31,-8(r1)
100006c4: f8 01 00 10 std r0,16(r1)
100006c8: f8 21 ff 71 stdu r1,-144(r1)
100006cc: 7c 3f 0b 78 mr r31,r1
100006d0: 7c 60 1b 78 mr r0,r3
100006d4: f8 9f 00 c8 std r4,200(r31)
100006d8: 90 1f 00 c0 stw r0,192(r31)
100006dc: 80 1f 00 c0 lwz r0,192(r31)
100006e0: 2f 80 00 00 cmpwi cr7,r0,0
100006e4: 40 9d 00 28 ble- cr7,1000070c <.main+0x50>
100006e8: e9 3f 00 c8 ld r9,200(r31)
100006ec: 39 29 00 08 addi r9,r9,8
100006f0: e8 09 00 00 ld r0,0(r9)
100006f4: 7c 03 03 78 mr r3,r0
100006f8: 4b ff fc f9 bl 100003f0 <._init+0x38>
100006fc: e8 41 00 28 ld r2,40(r1)
10000700: 7c 60 1b 78 mr r0,r3
10000704: 90 1f 00 7c stw r0,124(r31)
10000708: 48 00 00 0c b 10000714 <.main+0x58>
1000070c: 38 00 27 10 li r0,10000
10000710: 90 1f 00 7c stw r0,124(r31)
10000714: 38 00 00 00 li r0,0
10000718: 90 1f 00 78 stw r0,120(r31)
1000071c: 48 00 00 54 b 10000770 <.main+0xb4>
10000720: 38 60 27 10 li r3,10000
10000724: 4b ff ff 09 bl 1000062c <.function1>
10000728: 7c 60 1b 78 mr r0,r3
1000072c: 90 1f 00 74 stw r0,116(r31)
10000730: 38 00 00 00 li r0,0
10000734: 90 1f 00 74 stw r0,116(r31)
10000738: 48 00 00 20 b 10000758 <.main+0x9c>
1000073c: 81 3f 00 70 lwz r9,112(r31)
10000740: 80 1f 00 74 lwz r0,116(r31)
10000744: 7c 09 02 14 add r0,r9,r0
10000748: 90 1f 00 70 stw r0,112(r31)
1000074c: 81 3f 00 74 lwz r9,116(r31)
10000750: 38 09 00 01 addi r0,r9,1
10000754: 90 1f 00 74 stw r0,116(r31)
10000758: 80 1f 00 74 lwz r0,116(r31)
1000075c: 2f 80 27 0f cmpwi cr7,r0,9999
10000760: 40 9d ff dc ble+ cr7,1000073c <.main+0x80>
10000764: 81 3f 00 78 lwz r9,120(r31)
10000768: 38 09 00 01 addi r0,r9,1
1000076c: 90 1f 00 78 stw r0,120(r31)
10000770: 80 1f 00 78 lwz r0,120(r31)
10000774: 81 3f 00 7c lwz r9,124(r31)
10000778: 7f 80 48 00 cmpw cr7,r0,r9
1000077c: 41 9c ff a4 blt+ cr7,10000720 <.main+0x64>
10000780: 38 00 00 00 li r0,0
10000784: 7c 03 03 78 mr r3,r0
10000788: e8 21 00 00 ld r1,0(r1)
1000078c: e8 01 00 10 ld r0,16(r1)
10000790: 7c 08 03 a6 mtlr r0
10000794: eb e1 ff f8 ld r31,-8(r1)
10000798: 4e 80 00 20 blr
1000079c: 00 00 00 00 .long 0x0
100007a0: 00 00 00 01 .long 0x1
100007a4: 80 01 00 01 lwz r0,1(r1)
100007a8: 60 00 00 00 nop
100007ac: 60 00 00 00 nop
=2E.. deleted ...
^ permalink raw reply
* Re: [RESEND DTC PATCH 2/2] Add support for binary includes.
From: Scott Wood @ 2007-12-21 17:09 UTC (permalink / raw)
To: jdl, linuxppc-dev, u-boot-users
In-Reply-To: <20071221002922.GF2665@localhost.localdomain>
On Fri, Dec 21, 2007 at 11:29:22AM +1100, David Gibson wrote:
> On Thu, Dec 20, 2007 at 01:52:59PM -0600, Scott Wood wrote:
> > A property's data can be populated with a file's contents
> > as follows:
> >
> > node {
> > prop = /bin-include/ "path/to/data";
> > };
>
> I'd be inclined to use /incbin/ rather than /bin-include/. It's only
> slightly less obvious, but it's then the same as the gas pseudo-op as
> well as being a little briefer.
OK.
> > Search paths are not yet implemented; non-absolute lookups are relative to
> > the directory from which dtc was invoked.
>
> Hrm. I think that's a bit too bogus. Although it's rather more work
> to implement, I think we have to make relative paths relative to the
> location of the dts file until search paths are implemented.
OK. I was being lazy. :-P
> > + | propdataprefix DT_BININCLUDE DT_STRING
> > + {
> > + struct stat st;
> > + FILE *f;
> > + int fd;
> > +
> > + f = fopen($3.val, "rb");
> > + if (!f) {
> > + yyerrorf("Cannot open file \"%s\": %s",
> > + $3.val, strerror(errno));
> > + YYERROR;
>
> Hrm. I'm not sure that being unable to open the file should cause a
> *parse* error which is what YYERROR will do. Probably better to print
> an error message, but let the parsing continue, with the property
> value being as though the file were empty.
Yeah, I wanted something that would cause dtc to return an error code,
and it doesn't seem that calling yyerror(f) will do that at present. I
guess I should fix that rather than overload YYERROR.
>
> > + }
> > +
> > + fd = fileno(f);
> > + if (fstat(fd, &st) < 0) {
> > + yyerrorf("Cannot stat file \"%s\": %s",
> > + $3.val, strerror(errno));
> > + YYERROR;
> > + }
>
> I'm also not sure that stat()ing the file is a good way to get the
> size. This requires that the included file be a regular file with a
> sane st_size value, and I can imagine cases where it might be useful
> to incbin from a /dev node or other special file. Obviosuly
> implementing that will require work to data_copy_file().
Hmm... do you have a use case in mind?
> Actually, I think the way to go here would be to have two variants of
> the incbin directive: one which takes just a filename and includes
> the whole file contents, another which takes a filename and a number
> and includes just the first N bytes of the file.
Maybe. /incbinrange/ "path/name" start len?
> > diff --git a/dtc.h b/dtc.h
> > index 9b89689..87b5bb1 100644
> > --- a/dtc.h
> > +++ b/dtc.h
> > @@ -138,6 +138,7 @@ struct data data_grow_for(struct data d, int xlen);
> > struct data data_copy_mem(const char *mem, int len);
> > struct data data_copy_escape_string(const char *s, int len);
> > struct data data_copy_file(FILE *f, size_t len);
> > +struct data data_bin_include(const char *filename);
>
> This looks like a hangover from an earlier version.
Oops, yes.
-Scott
^ permalink raw reply
* Re: [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround
From: Josh Boyer @ 2007-12-21 16:43 UTC (permalink / raw)
To: Valentine Barshak; +Cc: linuxppc-dev
In-Reply-To: <20071221162402.GA1673@ru.mvista.com>
On Fri, 21 Dec 2007 19:24:02 +0300
Valentine Barshak <vbarshak@ru.mvista.com> wrote:
> Commit 3ee133269861dc449ad5be761aa8570b1b05571f introduced
> a CPU "model" property and thus broke PowerPC 440EP(x)/440GR(x)
> identical PVR workaround. The patch updates it to use the new
> model property for CPU identification.
Good catch. I'll have to look more closely to see if anything else
would be broken by changing the cpu node name from "PowerPC,xxxx@0" to
"cpu@0".
josh
^ permalink raw reply
* [PATCH 4/4] PowerPC: Add PCI node to 440GRx Rainier DTS.
From: Valentine Barshak @ 2007-12-21 16:27 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071221160723.GA1430@ru.mvista.com>
This adds PCI entry to PowerPC 440GRx Rainier DTS.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
arch/powerpc/boot/dts/rainier.dts | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+)
--- linux-2.6.orig/arch/powerpc/boot/dts/rainier.dts 2007-12-19 16:00:01.000000000 +0300
+++ linux-2.6/arch/powerpc/boot/dts/rainier.dts 2007-12-20 21:59:42.000000000 +0300
@@ -317,6 +317,33 @@
has-new-stacr-staopc;
};
};
+
+ PCI0: pci@1ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
+ primary;
+ reg = <1 eec00000 8 /* Config space access */
+ 1 eed80000 4 /* IACK */
+ 1 eed80000 4 /* Special cycle */
+ 1 ef400000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 80000000 1 80000000 0 10000000
+ 01000000 0 00000000 1 e8000000 0 00100000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* All PCI interrupts are routed to IRQ 67 */
+ interrupt-map-mask = <0000 0 0 0>;
+ interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
+ };
};
chosen {
^ permalink raw reply
* [PATCH 3/4] PowerPC: Add PCI entry to 440EPx Sequoia DTS.
From: Valentine Barshak @ 2007-12-21 16:26 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071221160723.GA1430@ru.mvista.com>
This adds PCI entry to PowerPC 440EPx Sequoia DTS.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
arch/powerpc/boot/dts/sequoia.dts | 27 +++++++++++++++++++++++++++
1 files changed, 27 insertions(+)
--- linux-2.6.orig/arch/powerpc/boot/dts/sequoia.dts 2007-12-21 17:14:17.000000000 +0300
+++ linux-2.6/arch/powerpc/boot/dts/sequoia.dts 2007-12-21 17:18:32.000000000 +0300
@@ -324,6 +324,33 @@
has-new-stacr-staopc;
};
};
+
+ PCI0: pci@1ec000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
+ primary;
+ reg = <1 eec00000 8 /* Config space access */
+ 1 eed00000 4 /* IACK */
+ 1 eed00000 4 /* Special cycle */
+ 1 ef400000 40>; /* Internal registers */
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed. Chip supports a second
+ * IO range but we don't use it for now
+ */
+ ranges = <02000000 0 80000000 1 80000000 0 10000000
+ 01000000 0 00000000 1 e8000000 0 00100000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+ /* All PCI interrupts are routed to IRQ 67 */
+ interrupt-map-mask = <0000 0 0 0>;
+ interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
+ };
};
chosen {
^ permalink raw reply
* [PATCH 2/4] PowerPC: update 440EP(x)/440GR(x) identical PVR issue workaround
From: Valentine Barshak @ 2007-12-21 16:24 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071221160723.GA1430@ru.mvista.com>
Commit 3ee133269861dc449ad5be761aa8570b1b05571f introduced
a CPU "model" property and thus broke PowerPC 440EP(x)/440GR(x)
identical PVR workaround. The patch updates it to use the new
model property for CPU identification.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
arch/powerpc/kernel/prom.c | 37 +++++++++++++++++++++++++------------
1 files changed, 25 insertions(+), 12 deletions(-)
diff -pruN linux-2.6.orig/arch/powerpc/kernel/prom.c linux-2.6/arch/powerpc/kernel/prom.c
--- linux-2.6.orig/arch/powerpc/kernel/prom.c 2007-12-21 17:14:17.000000000 +0300
+++ linux-2.6/arch/powerpc/kernel/prom.c 2007-12-21 18:42:09.000000000 +0300
@@ -614,6 +614,29 @@ static struct feature_property {
#endif /* CONFIG_PPC64 */
};
+#if defined(CONFIG_44x) && defined(CONFIG_PPC_FPU)
+static inline void identical_pvr_fixup(unsigned long node)
+{
+ unsigned int pvr;
+ char *model = of_get_flat_dt_prop(node, "model", NULL);
+
+ /*
+ * Since 440GR(x)/440EP(x) processors have the same pvr,
+ * we check the node path and set bit 28 in the cur_cpu_spec
+ * pvr for EP(x) processor version. This bit is always 0 in
+ * the "real" pvr. Then we call identify_cpu again with
+ * the new logical pvr to enable FPU support.
+ */
+ if (model && strstr(model, "440EP")) {
+ pvr = cur_cpu_spec->pvr_value | 0x8;
+ identify_cpu(0, pvr);
+ DBG("Using logical pvr %x for %s\n", pvr, model);
+ }
+}
+#else
+#define identical_pvr_fixup(node) do { } while(0)
+#endif
+
static void __init check_cpu_feature_properties(unsigned long node)
{
unsigned long i;
@@ -711,18 +734,8 @@ static int __init early_init_dt_scan_cpu
prop = of_get_flat_dt_prop(node, "cpu-version", NULL);
if (prop && (*prop & 0xff000000) == 0x0f000000)
identify_cpu(0, *prop);
-#if defined(CONFIG_44x) && defined(CONFIG_PPC_FPU)
- /*
- * Since 440GR(x)/440EP(x) processors have the same pvr,
- * we check the node path and set bit 28 in the cur_cpu_spec
- * pvr for EP(x) processor version. This bit is always 0 in
- * the "real" pvr. Then we call identify_cpu again with
- * the new logical pvr to enable FPU support.
- */
- if (strstr(uname, "440EP")) {
- identify_cpu(0, cur_cpu_spec->pvr_value | 0x8);
- }
-#endif
+
+ identical_pvr_fixup(node);
}
check_cpu_feature_properties(node);
^ permalink raw reply
* RE: [techfield] GPIO causing bus error
From: Elayda, Bernardo (Bernie) @ 2007-12-21 16:27 UTC (permalink / raw)
To: +techfield, Wyse, Chris, linuxppc-dev, linuxppc-embedded,
+linux-embedded, +linux-eng, linux-kernel, Wessel, Jason, support
Cc: Slimm, Rob, Read, Tricia, Ayer, Charles, Touron, Emmanuel
In-Reply-To: <AF1602CB2550CE4381C0C75118A7856B020C60D7@ala-mail02.corp.ad.wrs.com>
[-- Attachment #1: Type: text/plain, Size: 5858 bytes --]
Hi Chris,
I'm going to look at this problem from the FPGA hardware level because I
used to work for one of the FPGA companies.
I'm not familiar with your PPC440GX board, so some of my suggestions may
be difficult to implement or totally unreasonable, especially if it
requires soldering to an FPGA in a ball grid array or extermely fine
pitch pins.
(1) You should capture the configuration sequence on FPGA's JTAG pins
using a logic analyzer in functional mode.
In functional mode, you can capture an extermely long sequence of
configuration events. Also, in the past, I've used this mode and found
that when the FPGA doesn't configure, usually there are too few or too
many clocks on the TCK line.
(2) Sometimes, rarely, the FPGA design itself can cause a boot up
problem.
Instead of using the real design, send a 'blank' design with no logic
implemented at all. If this works, then it's the FPGA design itself
that is causing the boot problem.
(3) When the boot process happens, what is the power sequence of the
FPGA?
Most FPGA's out there like a nice smooth power profile that ramps up
quickly. Check and see if the profile is quick and smooth vs. spikey
and erratic. Also, sometimes configuration data gets sent before the
FPGA is ready to receive data. Try delaying the sending of
configuration data by a millisecond or so.
(4) Manually delay the configuration of the FPGA.
In other words, let the system boot, but modify the code to allow the
FPGA to configure only after a button is pushed. In theory, if the FPGA
power has properply initialized the FPGA, you could keep the system this
way forever until a 'button' is pushed to configure the FPGA. if this
works, this tends to imply that there is a timing issue. If it doesn't
work, it's possible that the FPGA's JTAG tap is actually in a state that
won't allow configuration to complete, such as non shift-dr or non
shift-ir state.
(5) If your FPGA is using one of the SVF-based software configuration
methods via JTAG, make sure you are using the latest SVF player and
latest software for generating the FPGA bitstream. The configuration
method may have changed. The FPGA silicon you are using may be newer
than the configuration algorithm that has been implemented.
I hope this helps!
Regards,
Bernie Elayda
the ex-X guy
________________________________
From: owner-techfield@windriver.com
[mailto:owner-techfield@windriver.com] On Behalf Of Wyse, Chris
Sent: Friday, December 21, 2007 7:55 AM
To: linuxppc-dev@ozlabs.org; linuxppc-embedded@ozlabs.org; +techfield;
+linux-embedded; +linux-eng; linux-kernel; Wessel, Jason;
support@amcc.com
Cc: Touron, Emmanuel; Read, Tricia; Ayer, Charles; Slimm, Rob
Subject: [techfield] GPIO causing bus error
Hi,
I'm having trouble with an unusual problem. I'm working on relatively
new hardware, so it's possible that there could be a hardware issue
involved.
I have an FPGA on my PPC440GX board that gets loaded via JTAG during the
kernel boot process (Linux 2.6.10). It uses the 440GX GPIO lines to
send the necessary JTAG commands to the FPGA to perform the initial
load. This process is USUALLY functional, but on some of the boards
(which we produce), the GPIO write fails with a bus error. On the
boards that fail, it only occurs after a cold boot, and only if the
board has been powered off for a few minutes. A quick hard reboot will
not generate the problem. When I issue the failing write to the GPIO
lines, some of the SDRAM gets corrupted. I don't appear to be taking
any interrupts that might have corrupted the RAM.
I've checked the TLB entries, and it maps correctly to the PPC register
area. Additionally, I can read and write to other registers using the
same TLB mapping WITHOUT any error. I can also READ the GPIO lines
without an error - the error is only on the write. I've checked the
SDR0_PFC0 bits to make sure everything is set properly (it is). The bus
error indicates "PLB Timeout Error Status Master 2, Master 2 slave error
occurred" (Master 2 is the write-only data cache unit (DCU)) and "Write
Error Interrupt Master 2, Write error detected - master 2 interrupt
request is active". I'm not sure why there would be any error in the
DCU, since the region I'm writing to is cache inhibited and guarded.
If I issue a soft reset of the GPIO subsystem, I can read and write to
the GPIO lines again.
The error does not occur on the first write to the GPIO. I go through
the failing routine several times before it fails. However, when it
fails, it consistently fails at the same spot, after the same number of
passes through the code.
I'm using RGMII ethernet on EMAC2 (Group 4), but the GPIO lines that I'm
using are not the Trace/GPIO lines (26-31) so I believe that they should
work fine (and they usually do). Also, the errata mentions that
SDR0_PFC0[G11E] has no effect - but I'm not using GPIO 11 anyway.
Here are some relevant register values after the error:
SDR0_PFC0 : 0x083FFE00
POB0_BESR0: 0x00008400
POB0_BEARH: 0x00000001
POB0_BEARL: 0x40000701
GPIO0_OR : 0x000400C0
GPIO0_TCR : 0x00278AE0
GPIO0_ODR : 0x00000000
GPIO0_IR : 0x00000000
I've attached two log files, that contain most of the 440 registers, one
for before the error and one after. In the log files, the bus error has
been cleared, so use the values shown above.
I'm looking for some suggestions on what to try to debug/resolve this
issue. I'm open to both hardware and software based suggestions. Any
help would be greatly appreciated.
Chris Wyse
Senior Member of Technical Staff
Embedded Technologies
860-978-0849 cell/office
413-778-9101 fax
http://www.windriver.com <http://www.windriver.com/>
[-- Attachment #2: Type: text/html, Size: 12913 bytes --]
^ permalink raw reply
* [PATCH 1/4] PowerPC: Correct 440GRx machine_check callback
From: Valentine Barshak @ 2007-12-21 16:22 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20071221160723.GA1430@ru.mvista.com>
Correct the PowerPC 440GRx machine check callback.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
arch/powerpc/kernel/cputable.c | 2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
diff -pruN linux-2.6.orig/arch/powerpc/kernel/cputable.c linux-2.6/arch/powerpc/kernel/cputable.c
--- linux-2.6.orig/arch/powerpc/kernel/cputable.c 2007-12-21 17:14:17.000000000 +0300
+++ linux-2.6/arch/powerpc/kernel/cputable.c 2007-12-21 18:05:08.000000000 +0300
@@ -1247,7 +1247,7 @@ static struct cpu_spec __initdata cpu_sp
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_440grx,
- .machine_check = machine_check_4xx,
+ .machine_check = machine_check_440A,
.platform = "ppc440",
},
{ /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
^ permalink raw reply
* [PATCH 0/4] PowerPC: more Sequoia/Rainier updates for 2.6.25
From: Valentine Barshak @ 2007-12-21 16:07 UTC (permalink / raw)
To: linuxppc-dev
This patch series has a couple of PowerPC 440EPx/GRx fixes and
adds PCI to Sequoia/Rainier DTS.
Thanks,
Valentine.
^ permalink raw reply
* GPIO causing bus error
From: Wyse, Chris @ 2007-12-21 15:54 UTC (permalink / raw)
To: linuxppc-dev, linuxppc-embedded, +techfield, +linux-embedded,
+linux-eng, linux-kernel, Wessel, Jason, support
Cc: Slimm, Rob, Read, Tricia, Ayer, Charles, Touron, Emmanuel
[-- Attachment #1.1: Type: text/plain, Size: 3041 bytes --]
Hi,
I'm having trouble with an unusual problem. I'm working on relatively
new hardware, so it's possible that there could be a hardware issue
involved.
I have an FPGA on my PPC440GX board that gets loaded via JTAG during the
kernel boot process (Linux 2.6.10). It uses the 440GX GPIO lines to
send the necessary JTAG commands to the FPGA to perform the initial
load. This process is USUALLY functional, but on some of the boards
(which we produce), the GPIO write fails with a bus error. On the
boards that fail, it only occurs after a cold boot, and only if the
board has been powered off for a few minutes. A quick hard reboot will
not generate the problem. When I issue the failing write to the GPIO
lines, some of the SDRAM gets corrupted. I don't appear to be taking
any interrupts that might have corrupted the RAM.
I've checked the TLB entries, and it maps correctly to the PPC register
area. Additionally, I can read and write to other registers using the
same TLB mapping WITHOUT any error. I can also READ the GPIO lines
without an error - the error is only on the write. I've checked the
SDR0_PFC0 bits to make sure everything is set properly (it is). The bus
error indicates "PLB Timeout Error Status Master 2, Master 2 slave error
occurred" (Master 2 is the write-only data cache unit (DCU)) and "Write
Error Interrupt Master 2, Write error detected - master 2 interrupt
request is active". I'm not sure why there would be any error in the
DCU, since the region I'm writing to is cache inhibited and guarded.
If I issue a soft reset of the GPIO subsystem, I can read and write to
the GPIO lines again.
The error does not occur on the first write to the GPIO. I go through
the failing routine several times before it fails. However, when it
fails, it consistently fails at the same spot, after the same number of
passes through the code.
I'm using RGMII ethernet on EMAC2 (Group 4), but the GPIO lines that I'm
using are not the Trace/GPIO lines (26-31) so I believe that they should
work fine (and they usually do). Also, the errata mentions that
SDR0_PFC0[G11E] has no effect - but I'm not using GPIO 11 anyway.
Here are some relevant register values after the error:
SDR0_PFC0 : 0x083FFE00
POB0_BESR0: 0x00008400
POB0_BEARH: 0x00000001
POB0_BEARL: 0x40000701
GPIO0_OR : 0x000400C0
GPIO0_TCR : 0x00278AE0
GPIO0_ODR : 0x00000000
GPIO0_IR : 0x00000000
I've attached two log files, that contain most of the 440 registers, one
for before the error and one after. In the log files, the bus error has
been cleared, so use the values shown above.
I'm looking for some suggestions on what to try to debug/resolve this
issue. I'm open to both hardware and software based suggestions. Any
help would be greatly appreciated.
Chris Wyse
Senior Member of Technical Staff
Embedded Technologies
860-978-0849 cell/office
413-778-9101 fax
http://www.windriver.com <http://www.windriver.com/>
[-- Attachment #1.2: Type: text/html, Size: 6449 bytes --]
[-- Attachment #2: pre_error.log --]
[-- Type: application/octet-stream, Size: 27172 bytes --]
>BKM>dr all /ignore
GPR register Group. (GPR)
R00 = 00040040 R01 = CFFB1D80 R02 = CFC89AE0 R03 = C02B575C
R04 = 000000F8 R05 = 00000005 R06 = 000004A3 R07 = 00000000
R08 = C02B4E28 R09 = D1000700 R10 = C02B4E28 R11 = 000400C0
R12 = 00000080 R13 = 00000000 R14 = 0FFF4C00 R15 = 00000000
R16 = 00000001 R17 = 00000001 R18 = FFFFFFFF R19 = 007FFC00
R20 = 0FFEF148 R21 = 00000000 R22 = 00000003 R23 = 00000004
R24 = 00000000 R25 = 007FFB50 R26 = 00000E60 R27 = 007FFD0B
R28 = 007FFC00 R29 = C0400000 R30 = C000149C R31 = CFFB1E90
CR = 24FF2F24 MSR = 00029200 LR = C000EF64 SRR0 = C0003458
SRR1 = 00021200 SPRG0 = 00000000 SPRG1 = 00000000 SPRG2 = 00000000
SPRG3 = CFC89CB8 XER = 20000000 CTR = C000EEBC PC = C000EE10
4XXSPR register Group. (4XXSPR)
CSRR0 = 00000000 CSRR1 = 00000000 SPRG4_R = C02EDFB0 SPRG4_W = 00000000
SPRG5_R = 00000000 SPRG5_W = 00000000 SPRG6_R = 04502940 SPRG6_W = 00000000
SPRG7_R = 24FF2F48 SPRG7_W = 00000000 USPRG0 = 04502940 MCSRR0 = 00000000
MCSRR1 = 00000000 MCSR = 00000000 CCR1 = 00000000
CTRL register Group. (CTRL)
PVR = 51B21894 PID = 00000000 PIR = 00000000 MMUCR = 00000000
RSTCFG = 00000001 CCR0 = 00306000
DEBUG register Group. (DEBUG)
DBCR0 = 81000001 DBCR1 = 00000000 DBCR2 = 00000000 DBSR = 00400000
DAC1 = 00000000 DAC2 = 00000000 DVC1 = 00000000 DVC2 = 00000000
IAC1 = 00000000 IAC2 = 00000000 IAC3 = 00000000 IAC4 = E7F9B8FC
TIMERS register Group. (TIMERS)
TCR = 04000000 TSR = C4000000 TBL = 8FB5D62B TBU = 00000000
DEC = 00022286 DECAR = 00000000
EXCEPTS register Group. (EXCEPTS)
ESR = 00000000 DEAR = D1000704 IVPR = C0000000
CPR_CPM register Group. (CPR_CPM)
CPM0_ER = 00000000 CPM0_FR = 00000000 CPM0_SR = 00000000 CPR0_CLKUPD = 00000000
CPR0_PLLC = 400002B8 CPR0_PLLD = 04020702 CPR0_PRIMAD = 01000000 CPR0_PRIMBD = 01000000
CPR0_OPBD = 02000000 CPR0_PERD = 01000000 CPR0_MALD = 02000000 CPR0_ICFG = 00000007
CPR0_CFGADDR = 000000E0 CPR0_CFGDATA = 01000000
SDR0 register Group. (SDR0)
SDR0_SDSTP0 = 857042E6 SDR0_SDSTP1 = 09960D20 SDR0_PINSTP = E0000000 SDR0_SDCS = A0000003
SDR0_ECID0 = 07E00DD4 SDR0_ECID1 = 0D47FFFF SDR0_ECID2 = 040D0000 SDR0_JTAG = 52054049
SDR0_DDRDL = 00000012 SDR0_EBC = 10000000 SDR0_UART0 = 20800001 SDR0_UART1 = 20000026
SDR0_CP440 = 1EAAEA00 SDR0_XCR = C1A00000 SDR0_XPLLC = 000002B8 SDR0_XPLLD = 010A0000
SDR0_SRST = 00000000 SDR0_SLPIPE = F0000000 SDR0_AMP = 00000000 SDR0_MIRQ0 = 00000000
SDR0_MIRQ1 = 00000000 SDR0_MALTBL = 55550000 SDR0_MALRBL = 55550000 SDR0_MALTBS = F0000000
SDR0_MALRBS = F0000000 SDR0_CUST0 = FFFFFFFF SDR0_SDSTP2 = 00000000 SDR0_CUST1 = FFFFFFFF
SDR0_SDSTP3 = 00000000 SDR0_PFC0 = 083FFE00 SDR0_PFC1 = 01200000 SDR0_PLBTR = 000001B0
SDR0_MFR = 00000000 SDR0_CFGADDR = 00004100 SDR0_CFGDATA = 083FFE00
CACHE register Group. (CACHE)
ICDBDR = 00C00000 ICDBTRH = C0000000 ICDBTRL = 00000001 DCDBTRH = BBFFFF88
DCDBTRL = 0007BFE0 DNV0 = 32370237 DNV1 = 0F20191D DNV2 = 033C2300
DNV3 = 071D3532 DTV0 = 00000000 DTV1 = 00000000 DTV2 = 00000000
DTV3 = 00000000 DVLIM = 0001F800 INV0 = 01010101 INV1 = 00000000
INV2 = 00000001 INV3 = 01010101 ITV0 = 00000000 ITV1 = 00000000
ITV2 = 00000000 ITV3 = 00000000 IVLIM = 0001F800
L2CACHE register Group. (L2CACHE)
L2C0_CFG = E1A70080 L2C0_CMD = 00000000 L2C0_ADDR = 00000000 L2C0_DATA = 00000000
L2C0_SR = 88000000 L2C0_REVID = 00000101 L2C0_SNP0 = 0000F800 L2C0_SNP1 = 8000F800
TLB register Group. (TLB)
TLB0PID = 00000000 TLB0WORD0 = 00000000 TLB0WORD1 = 00000000 TLB0WORD2 = 00000000
TLB1PID = 00000000 TLB1WORD0 = FDFFF210 TLB1WORD1 = 0EC80002 TLB1WORD2 = 00000503
TLB2PID = 00000000 TLB2WORD0 = FDFED210 TLB2WORD1 = 40000001 TLB2WORD2 = 00000503
TLB3PID = 00000000 TLB3WORD0 = D1000210 TLB3WORD1 = 40000001 TLB3WORD2 = 00000503
TLB4PID = 00000000 TLB4WORD0 = 00000000 TLB4WORD1 = 00000000 TLB4WORD2 = 00000000
TLB5PID = 00000000 TLB5WORD0 = 00000000 TLB5WORD1 = 00000000 TLB5WORD2 = 00000000
TLB6PID = 00000000 TLB6WORD0 = 00000000 TLB6WORD1 = 00000000 TLB6WORD2 = 00000000
TLB7PID = 00000000 TLB7WORD0 = 00000000 TLB7WORD1 = 00000000 TLB7WORD2 = 00000000
TLB8PID = 00000000 TLB8WORD0 = 00000000 TLB8WORD1 = 00000000 TLB8WORD2 = 00000000
TLB9PID = 00000000 TLB9WORD0 = 00000000 TLB9WORD1 = 00000000 TLB9WORD2 = 00000000
TLB10PID = 00000000 TLB10WORD0 = 00000000 TLB10WORD1 = 00000000 TLB10WORD2 = 00000000
TLB11PID = 00000000 TLB11WORD0 = 00000000 TLB11WORD1 = 00000000 TLB11WORD2 = 00000000
TLB12PID = 00000000 TLB12WORD0 = 00000000 TLB12WORD1 = 00000000 TLB12WORD2 = 00000000
TLB13PID = 00000000 TLB13WORD0 = 00000000 TLB13WORD1 = 00000000 TLB13WORD2 = 00000000
TLB14PID = 00000000 TLB14WORD0 = 00000000 TLB14WORD1 = 00000000 TLB14WORD2 = 00000000
TLB15PID = 00000000 TLB15WORD0 = 00000000 TLB15WORD1 = 00000000 TLB15WORD2 = 00000000
TLB16PID = 00000000 TLB16WORD0 = 00000000 TLB16WORD1 = 00000000 TLB16WORD2 = 00000000
TLB17PID = 00000000 TLB17WORD0 = 00000000 TLB17WORD1 = 00000000 TLB17WORD2 = 00000000
TLB18PID = 00000000 TLB18WORD0 = 00000000 TLB18WORD1 = 00000000 TLB18WORD2 = 00000000
TLB19PID = 00000000 TLB19WORD0 = 00000000 TLB19WORD1 = 00000000 TLB19WORD2 = 00000000
TLB20PID = 00000000 TLB20WORD0 = 00000000 TLB20WORD1 = 00000000 TLB20WORD2 = 00000000
TLB21PID = 00000000 TLB21WORD0 = 00000000 TLB21WORD1 = 00000000 TLB21WORD2 = 00000000
TLB22PID = 00000000 TLB22WORD0 = 00000000 TLB22WORD1 = 00000000 TLB22WORD2 = 00000000
TLB23PID = 00000000 TLB23WORD0 = 00000000 TLB23WORD1 = 00000000 TLB23WORD2 = 00000000
TLB24PID = 00000000 TLB24WORD0 = 00000000 TLB24WORD1 = 00000000 TLB24WORD2 = 00000000
TLB25PID = 00000000 TLB25WORD0 = 00000000 TLB25WORD1 = 00000000 TLB25WORD2 = 00000000
TLB26PID = 00000000 TLB26WORD0 = 00000000 TLB26WORD1 = 00000000 TLB26WORD2 = 00000000
TLB27PID = 00000000 TLB27WORD0 = 00000000 TLB27WORD1 = 00000000 TLB27WORD2 = 00000000
TLB28PID = 00000000 TLB28WORD0 = 00000000 TLB28WORD1 = 00000000 TLB28WORD2 = 00000000
TLB29PID = 00000000 TLB29WORD0 = 00000000 TLB29WORD1 = 00000000 TLB29WORD2 = 00000000
TLB30PID = 00000000 TLB30WORD0 = 00000000 TLB30WORD1 = 00000000 TLB30WORD2 = 00000000
TLB31PID = 00000000 TLB31WORD0 = 00000000 TLB31WORD1 = 00000000 TLB31WORD2 = 00000000
TLB32PID = 00000000 TLB32WORD0 = 00000000 TLB32WORD1 = 00000000 TLB32WORD2 = 00000000
TLB33PID = 00000000 TLB33WORD0 = 00000000 TLB33WORD1 = 00000000 TLB33WORD2 = 00000000
TLB34PID = 00000000 TLB34WORD0 = 00000000 TLB34WORD1 = 00000000 TLB34WORD2 = 00000000
TLB35PID = 00000000 TLB35WORD0 = 00000000 TLB35WORD1 = 00000000 TLB35WORD2 = 00000000
TLB36PID = 00000000 TLB36WORD0 = 00000000 TLB36WORD1 = 00000000 TLB36WORD2 = 00000000
TLB37PID = 00000000 TLB37WORD0 = 00000000 TLB37WORD1 = 00000000 TLB37WORD2 = 00000000
TLB38PID = 00000000 TLB38WORD0 = 00000000 TLB38WORD1 = 00000000 TLB38WORD2 = 00000000
TLB39PID = 00000000 TLB39WORD0 = 00000000 TLB39WORD1 = 00000000 TLB39WORD2 = 00000000
TLB40PID = 00000000 TLB40WORD0 = 00000000 TLB40WORD1 = 00000000 TLB40WORD2 = 00000000
TLB41PID = 00000000 TLB41WORD0 = 00000000 TLB41WORD1 = 00000000 TLB41WORD2 = 00000000
TLB42PID = 00000000 TLB42WORD0 = 00000000 TLB42WORD1 = 00000000 TLB42WORD2 = 00000000
TLB43PID = 00000000 TLB43WORD0 = 00000000 TLB43WORD1 = 00000000 TLB43WORD2 = 00000000
TLB44PID = 00000000 TLB44WORD0 = 00000000 TLB44WORD1 = 00000000 TLB44WORD2 = 00000000
TLB45PID = 00000000 TLB45WORD0 = 00000000 TLB45WORD1 = 00000000 TLB45WORD2 = 00000000
TLB46PID = 00000000 TLB46WORD0 = 00000000 TLB46WORD1 = 00000000 TLB46WORD2 = 00000000
TLB47PID = 00000000 TLB47WORD0 = 00000000 TLB47WORD1 = 00000000 TLB47WORD2 = 00000000
TLB48PID = 00000000 TLB48WORD0 = 00000000 TLB48WORD1 = 00000000 TLB48WORD2 = 00000000
TLB49PID = 00000000 TLB49WORD0 = 00000000 TLB49WORD1 = 00000000 TLB49WORD2 = 00000000
TLB50PID = 00000000 TLB50WORD0 = 00000000 TLB50WORD1 = 00000000 TLB50WORD2 = 00000000
TLB51PID = 00000000 TLB51WORD0 = 00000000 TLB51WORD1 = 00000000 TLB51WORD2 = 00000000
TLB52PID = 00000000 TLB52WORD0 = 00000000 TLB52WORD1 = 00000000 TLB52WORD2 = 00000000
TLB53PID = 00000000 TLB53WORD0 = 00000000 TLB53WORD1 = 00000000 TLB53WORD2 = 00000000
TLB54PID = 00000000 TLB54WORD0 = 00000000 TLB54WORD1 = 00000000 TLB54WORD2 = 00000000
TLB55PID = 00000000 TLB55WORD0 = 00000000 TLB55WORD1 = 00000000 TLB55WORD2 = 00000000
TLB56PID = 00000000 TLB56WORD0 = 00000000 TLB56WORD1 = 00000000 TLB56WORD2 = 00000000
TLB57PID = 00000000 TLB57WORD0 = 00000000 TLB57WORD1 = 00000000 TLB57WORD2 = 00000000
TLB58PID = 00000000 TLB58WORD0 = 00000000 TLB58WORD1 = 00000000 TLB58WORD2 = 00000000
TLB59PID = 00000000 TLB59WORD0 = 00000000 TLB59WORD1 = 00000000 TLB59WORD2 = 00000000
TLB60PID = 00000000 TLB60WORD0 = 00000000 TLB60WORD1 = 00000000 TLB60WORD2 = 00000000
TLB61PID = 00000000 TLB61WORD0 = 00000000 TLB61WORD1 = 00000000 TLB61WORD2 = 00000000
TLB62PID = 00000000 TLB62WORD0 = 00000000 TLB62WORD1 = 00000000 TLB62WORD2 = 00000000
TLB63PID = 00000000 TLB63WORD0 = C0000290 TLB63WORD1 = 00000000 TLB63WORD2 = 00000107
SRAM0 register Group. (SRAM0)
SRAM0_SB0CR = 80000800 SRAM0_SB1CR = 80010800 SRAM0_SB2CR = 80020800 SRAM0_SB3CR = 80030800
SRAM0_BEAR = 00000000 SRAM0_BESR0 = 00000000 SRAM0_BESR1 = 00000000 SRAM0_PMEG = 01E00000
SRAM0_CID = 322B0000 SRAM0_REVID = 04005800 SRAM0_DPC = 00000000
EBC0 register Group. (EBC0)
EBC0_CFG = 17004000 EBC0_B0CR = FF09A000 EBC0_B1CR = F001A000 EBC0_B2CR = F0118000
EBC0_B3CR = F0218000 EBC0_B4CR = F031A000 EBC0_B5CR = F041E000 EBC0_B6CR = F0518000
EBC0_B7CR = F0F18000 EBC0_B0AP = 9B015400 EBC0_B1AP = 9B055480 EBC0_B2AP = 1B015480
EBC0_B3AP = 12815280 EBC0_B4AP = 12815400 EBC0_B5AP = 1B015400 EBC0_B6AP = 00000000
EBC0_B7AP = 010502C0 EBC0_BEAR = 00000000 EBC0_BESR = 00000000 EBC0_CID = 32401093
EBC0_CFGADDR = 00000017 EBC0_CFGDATA = 010502C0
EBMI register Group. (EBMI)
EBM0_CTL = 88400000 EBM0_LCNT = 00000000 EBM0_BEAR = 00000000 EBM0_BESR = 00000000
EBM0_BEMR = 00000000 EBM0_UAR = 00000000 EBM0_UAM = 00000000 EBM0_SLPMD = 07C00000
EBM0_FAIR = FFF00000 EBM0_MISCSTS = 36000008 EBM0_CID = 32501054 EBM0_CFGADDR = 00000000
EBM0_CFGDATA = 88400000
SDRAM0 register Group. (SDRAM0)
SDRAM0_BESR0 = 00000000 SDRAM0_BESR1 = 00000000 SDRAM0_BEAR = 00000000 SDRAM0_MIRQ = 00000000
SDRAM0_UABBA = 00000000 SDRAM0_SLIO = 00000000 SDRAM0_DEVOPT = 00000000 SDRAM0_WDDCTR = 00000000
SDRAM0_CLKTR = 40000000 SDRAM0_CFG0A = 86000000 SDRAM0_CFG1 = 00000000 SDRAM0_PMIT = 07C00000
SDRAM0_TR0 = 410A4016 SDRAM0_TR1 = 80800828 SDRAM0_RTR = 04B00000 SDRAM0_B0CR = 000C4001
SDRAM0_B1CR = 00000000 SDRAM0_B2CR = 00000000 SDRAM0_B3CR = 00000000 SDRAM0_DLYCAL = 200000B0
SDRAM0_ECCESR = 00000000 SDRAM0_CID = 320B0000 SDRAM0_RID = 00003101 SDRAM0_CFG0B = 86000000
SDRAM0_MCSTS = A0000000 SDRAM0_CFGADDR = 0000004C SDRAM0_CFGDATA = 00000000
OCBUSES register Group. (OCBUSES)
PLB0_REVID = 00000101 PLB0_ACR = 9B000000 PLB0_BESR = 00000000 PLB0_BEARL = F77FFFFF
PLB0_BEARH = FDFFFFFF POB0_BESR0 = 00000000 POB0_BEARL = 00000000 POB0_BEARH = 00000000
POB0_BESR1 = 00000000 POB0_CONFG = 00000000 POB0_LATENCY = 78000000 POB0_REVID = 00000122
OPB0_BCTRL = 00000000 OPB0_BSTAT = 00000000 OPB0_BEARL = FFFFFFFF OPB0_BEARH = 0000000F
OPB0_REVID = 00000130
IVOR register Group. (IVOR)
IVOR0 = 00000240 IVOR1 = 00000340 IVOR2 = 00000460 IVOR3 = 00000560
IVOR4 = 00000620 IVOR5 = 000006E0 IVOR6 = 000007A0 IVOR7 = 00000860
IVOR8 = 00000920 IVOR9 = 000009E0 IVOR10 = 00000AA0 IVOR11 = 00000B60
IVOR12 = 00000C20 IVOR13 = 00000D20 IVOR14 = 00000DC0 IVOR15 = 00000E60
UIC register Group. (UIC)
UIC0_SR = 00000040 UIC0_ER = 00000000 UIC0_CR = 00000000 UIC0_PR = FFFFFE13
UIC0_TR = 01C00040 UIC0_MSR = 00000000 UIC0_VR = 00000000 UIC0_VCR = 00000040
UIC1_SR = 00002700 UIC1_ER = 00000000 UIC1_CR = 00000000 UIC1_PR = FFFFE0FF
UIC1_TR = 00FFC000 UIC1_MSR = 00000000 UIC1_VR = 00000000 UIC1_VCR = 00002700
UIC2_SR = 00000000 UIC2_ER = 00000100 UIC2_CR = 00000000 UIC2_PR = FFFFFFFF
UIC2_TR = 00FF8D0F UIC2_MSR = 00000000 UIC2_VR = 00000000 UIC2_VCR = 00000000
UICB0_SR = 03FFFFFF UICB0_ER = 54000000 UICB0_CR = 00000000 UICB0_PR = FC000000
UICB0_TR = 00000000 UICB0_MSR = 00000000 UICB0_VR = 00000000 UICB0_VCR = 03FFFFFF
DMA0 register Group. (DMA0)
DMA0_CR0 = 00000000 DMA0_CT0 = 00000000 DMA0_SAH0 = 00000000 DMA0_SAL0 = 00000000
DMA0_DAH0 = 00000000 DMA0_DAL0 = 00000000 DMA0_SGH0 = 00000000 DMA0_SGL0 = 00000000
DMA0_CR1 = 00000000 DMA0_CT1 = 00000000 DMA0_SAH1 = 00000000 DMA0_SAL1 = 00000000
DMA0_DAH1 = 00000000 DMA0_DAL1 = 00000000 DMA0_SGH1 = 00000000 DMA0_SGL1 = 00000000
DMA0_CR2 = 00000000 DMA0_CT2 = 00000000 DMA0_SAH2 = 00000000 DMA0_SAL2 = 00000000
DMA0_DAH2 = 00000000 DMA0_DAL2 = 00000000 DMA0_SGH2 = 00000000 DMA0_SGL2 = 00000000
DMA0_CR3 = 00000000 DMA0_CT3 = 00000000 DMA0_SAH3 = 00000000 DMA0_SAL3 = 00000000
DMA0_DAH3 = 00000000 DMA0_DAL3 = 00000000 DMA0_SGH3 = 00000000 DMA0_SGL3 = 00000000
DMA0_SR = 00008000 DMA0_SGC = 00000000 DMA0_SLP = 07C00000 DMA0_POL = 00000000
MAL0 register Group. (MAL0)
MAL0_CFG = 0037C086 MAL0_ESR = 00000000 MAL0_IER = 00000017 MAL0_TXCASR = 00000000
MAL0_TXCARR = 00000000 MAL0_TXEOBISR = 00000000 MAL0_TXDEIR = 00000000 MAL0_RXCASR = 00000000
MAL0_RXCARR = 00000000 MAL0_RXEOBISR = 00000000 MAL0_RXDEIR = 00000000 MAL0_TXCTP0R = 00000000
MAL0_TXCTP1R = 00000000 MAL0_TXCTP2R = 0FFA1340 MAL0_TXCTP3R = 00000000 MAL0_RXCTP0R = 00000000
MAL0_RXCTP1R = 00000000 MAL0_RXCTP2R = 0FFA13A0 MAL0_RXCTP3R = 00000000 MAL0_RCBS0 = 00000000
MAL0_RCBS1 = 00000000 MAL0_RCBS2 = 00000060 MAL0_RCBS3 = 00000000 MAL0_TXBADDR = 00000000
MAL0_RXBADDR = 00000000
PPM0 register Group. (PPM0)
PPM0_ISR = 00000000 PPM0_CR = 00000000 PPM0_CCR = FFFFFFFF PPM0_UAR = 00000000
PPM0_LAR = 00000000 PPM0_UAMR = FFFFFFFF PPM0_LAMR = FFFFFFFF PPM0_RIDR = C27E3411
PPM0_MCSR0 = 00000000 PPM0_MCSR1 = 00000000 PPM0_MCSR2 = 00000000 PPM0_MCSR3 = 00000000
PPM0_SCSR0 = 00000000 PPM0_SCSR1 = 00000000 PPM0_SCSR2 = 00000000 PPM0_SCSR3 = 00000000
PPM0_GCSR0 = 00000000 PPM0_GCSR1 = 00000000 PPM0_GCSR2 = 00000000 PPM0_GCSR3 = 00000000
PPM0_MCR0 = 00000000 PPM0_MCR1 = 00000000 PPM0_MCR2 = 00000000 PPM0_MCR3 = 00000000
PPM0_SCR0 = 00000000 PPM0_SCR1 = 00000000 PPM0_SCR2 = 00000000 PPM0_SCR3 = 00000000
PPM0_GCR0 = 00000000 PPM0_GCR1 = 00000000 PPM0_GCR2 = 00000000 PPM0_GCR3 = 00000000
PPM0_DCSR0 = 00000000 PPM0_DCSR1 = 00000000 PPM0_DCMXR0 = 00000000 PPM0_DCMXR1 = 00000000
PPM0_DCMNR0 = 00FFFFFF PPM0_DCMNR1 = 00FFFFFF PPM0_DCTVR0 = 00000000 PPM0_DCTVR1 = 00000000
PPM0_DCOTR0 = 00000000 PPM0_DCOTR1 = 00000000 PPM0_CFGADDR = 00000000 PPM0_CFGDATA = 00000000
[-- Attachment #3: post_error.log --]
[-- Type: application/octet-stream, Size: 27172 bytes --]
>BKM>dr all /ignore
GPR register Group. (GPR)
R00 = 00040040 R01 = CFFB1D80 R02 = CFC89AE0 R03 = C02B575C
R04 = 000000F8 R05 = 00000005 R06 = 000004A3 R07 = 00000000
R08 = C02B4E28 R09 = D1000700 R10 = C02B4E28 R11 = 000400C0
R12 = 00000080 R13 = 00000000 R14 = 0FFF4C00 R15 = 00000000
R16 = 00000001 R17 = 00000001 R18 = FFFFFFFF R19 = 007FFC00
R20 = 0FFEF148 R21 = 00000000 R22 = 00000003 R23 = 00000004
R24 = 00000000 R25 = 007FFB50 R26 = 00000E60 R27 = 007FFD0B
R28 = 007FFC00 R29 = C0400000 R30 = C000149C R31 = CFFB1E90
CR = 24FF2F24 MSR = 00029200 LR = C000EF64 SRR0 = C000EE10
SRR1 = 00029200 SPRG0 = 00000000 SPRG1 = 00000000 SPRG2 = 00000000
SPRG3 = CFC89CB8 XER = 20000000 CTR = C000EEBC PC = C000EE14
4XXSPR register Group. (4XXSPR)
CSRR0 = 00000000 CSRR1 = 00000000 SPRG4_R = C02EDFB0 SPRG4_W = 00000000
SPRG5_R = 00000000 SPRG5_W = 00000000 SPRG6_R = 04502940 SPRG6_W = 00000000
SPRG7_R = 24FF2F48 SPRG7_W = 00000000 USPRG0 = 04502940 MCSRR0 = 00000000
MCSRR1 = 00000000 MCSR = 00000000 CCR1 = 00000000
CTRL register Group. (CTRL)
PVR = 51B21894 PID = 00000000 PIR = 00000000 MMUCR = 00000000
RSTCFG = 00000001 CCR0 = 00306000
DEBUG register Group. (DEBUG)
DBCR0 = 81000001 DBCR1 = 00000000 DBCR2 = 00000000 DBSR = 00000000
DAC1 = 00000000 DAC2 = 00000000 DVC1 = 00000000 DVC2 = 00000000
IAC1 = 00000000 IAC2 = 00000000 IAC3 = 00000000 IAC4 = E7F9B8FC
TIMERS register Group. (TIMERS)
TCR = 04000000 TSR = C4000000 TBL = 8FB5D62B TBU = 00000000
DEC = 00022286 DECAR = 00000000
EXCEPTS register Group. (EXCEPTS)
ESR = 00000000 DEAR = DEC00000 IVPR = C0000000
CPR_CPM register Group. (CPR_CPM)
CPM0_ER = 00000000 CPM0_FR = 00000000 CPM0_SR = 00000000 CPR0_CLKUPD = 00000000
CPR0_PLLC = 400002B8 CPR0_PLLD = 04020702 CPR0_PRIMAD = 01000000 CPR0_PRIMBD = 01000000
CPR0_OPBD = 02000000 CPR0_PERD = 01000000 CPR0_MALD = 02000000 CPR0_ICFG = 00000007
CPR0_CFGADDR = 000000E0 CPR0_CFGDATA = 01000000
SDR0 register Group. (SDR0)
SDR0_SDSTP0 = 857042E6 SDR0_SDSTP1 = 09960D20 SDR0_PINSTP = E0000000 SDR0_SDCS = A0000003
SDR0_ECID0 = 07E00DD4 SDR0_ECID1 = 0D47FFFF SDR0_ECID2 = 040D0000 SDR0_JTAG = 52054049
SDR0_DDRDL = 00000012 SDR0_EBC = 10000000 SDR0_UART0 = 20800001 SDR0_UART1 = 20000026
SDR0_CP440 = 1EAAEA00 SDR0_XCR = C1A00000 SDR0_XPLLC = 000002B8 SDR0_XPLLD = 010A0000
SDR0_SRST = 00000000 SDR0_SLPIPE = F0000000 SDR0_AMP = 00000000 SDR0_MIRQ0 = 00000000
SDR0_MIRQ1 = 00000000 SDR0_MALTBL = 55550000 SDR0_MALRBL = 55550000 SDR0_MALTBS = F0000000
SDR0_MALRBS = F0000000 SDR0_CUST0 = FFFFFFFF SDR0_SDSTP2 = 00000000 SDR0_CUST1 = FFFFFFFF
SDR0_SDSTP3 = 00000000 SDR0_PFC0 = 083FFE00 SDR0_PFC1 = 01200000 SDR0_PLBTR = 000001B0
SDR0_MFR = 00000000 SDR0_CFGADDR = 00004100 SDR0_CFGDATA = 083FFE00
CACHE register Group. (CACHE)
ICDBDR = 00C00000 ICDBTRH = C0000000 ICDBTRL = 00000001 DCDBTRH = BBFFFF88
DCDBTRL = 0007BFE0 DNV0 = 32370237 DNV1 = 0F20191D DNV2 = 033C2300
DNV3 = 071D3532 DTV0 = 00000000 DTV1 = 00000000 DTV2 = 00000000
DTV3 = 00000000 DVLIM = 0001F800 INV0 = 01010000 INV1 = 00000000
INV2 = 00000000 INV3 = 00000000 ITV0 = 00000000 ITV1 = 00000000
ITV2 = 00000000 ITV3 = 00000000 IVLIM = 0001F800
L2CACHE register Group. (L2CACHE)
L2C0_CFG = E1A70080 L2C0_CMD = 00000000 L2C0_ADDR = 00000000 L2C0_DATA = 00000000
L2C0_SR = 88000000 L2C0_REVID = 00000101 L2C0_SNP0 = 0000F800 L2C0_SNP1 = 8000F800
TLB register Group. (TLB)
TLB0PID = 00000000 TLB0WORD0 = 00000000 TLB0WORD1 = 00000000 TLB0WORD2 = 00000000
TLB1PID = 00000000 TLB1WORD0 = FDFFF210 TLB1WORD1 = 0EC80002 TLB1WORD2 = 00000503
TLB2PID = 00000000 TLB2WORD0 = FDFED210 TLB2WORD1 = 40000001 TLB2WORD2 = 00000503
TLB3PID = 00000000 TLB3WORD0 = D1000210 TLB3WORD1 = 40000001 TLB3WORD2 = 00000503
TLB4PID = 00000000 TLB4WORD0 = 00000000 TLB4WORD1 = 00000000 TLB4WORD2 = 00000000
TLB5PID = 00000000 TLB5WORD0 = 00000000 TLB5WORD1 = 00000000 TLB5WORD2 = 00000000
TLB6PID = 00000000 TLB6WORD0 = 00000000 TLB6WORD1 = 00000000 TLB6WORD2 = 00000000
TLB7PID = 00000000 TLB7WORD0 = 00000000 TLB7WORD1 = 00000000 TLB7WORD2 = 00000000
TLB8PID = 00000000 TLB8WORD0 = 00000000 TLB8WORD1 = 00000000 TLB8WORD2 = 00000000
TLB9PID = 00000000 TLB9WORD0 = 00000000 TLB9WORD1 = 00000000 TLB9WORD2 = 00000000
TLB10PID = 00000000 TLB10WORD0 = 00000000 TLB10WORD1 = 00000000 TLB10WORD2 = 00000000
TLB11PID = 00000000 TLB11WORD0 = 00000000 TLB11WORD1 = 00000000 TLB11WORD2 = 00000000
TLB12PID = 00000000 TLB12WORD0 = 00000000 TLB12WORD1 = 00000000 TLB12WORD2 = 00000000
TLB13PID = 00000000 TLB13WORD0 = 00000000 TLB13WORD1 = 00000000 TLB13WORD2 = 00000000
TLB14PID = 00000000 TLB14WORD0 = 00000000 TLB14WORD1 = 00000000 TLB14WORD2 = 00000000
TLB15PID = 00000000 TLB15WORD0 = 00000000 TLB15WORD1 = 00000000 TLB15WORD2 = 00000000
TLB16PID = 00000000 TLB16WORD0 = 00000000 TLB16WORD1 = 00000000 TLB16WORD2 = 00000000
TLB17PID = 00000000 TLB17WORD0 = 00000000 TLB17WORD1 = 00000000 TLB17WORD2 = 00000000
TLB18PID = 00000000 TLB18WORD0 = 00000000 TLB18WORD1 = 00000000 TLB18WORD2 = 00000000
TLB19PID = 00000000 TLB19WORD0 = 00000000 TLB19WORD1 = 00000000 TLB19WORD2 = 00000000
TLB20PID = 00000000 TLB20WORD0 = 00000000 TLB20WORD1 = 00000000 TLB20WORD2 = 00000000
TLB21PID = 00000000 TLB21WORD0 = 00000000 TLB21WORD1 = 00000000 TLB21WORD2 = 00000000
TLB22PID = 00000000 TLB22WORD0 = 00000000 TLB22WORD1 = 00000000 TLB22WORD2 = 00000000
TLB23PID = 00000000 TLB23WORD0 = 00000000 TLB23WORD1 = 00000000 TLB23WORD2 = 00000000
TLB24PID = 00000000 TLB24WORD0 = 00000000 TLB24WORD1 = 00000000 TLB24WORD2 = 00000000
TLB25PID = 00000000 TLB25WORD0 = 00000000 TLB25WORD1 = 00000000 TLB25WORD2 = 00000000
TLB26PID = 00000000 TLB26WORD0 = 00000000 TLB26WORD1 = 00000000 TLB26WORD2 = 00000000
TLB27PID = 00000000 TLB27WORD0 = 00000000 TLB27WORD1 = 00000000 TLB27WORD2 = 00000000
TLB28PID = 00000000 TLB28WORD0 = 00000000 TLB28WORD1 = 00000000 TLB28WORD2 = 00000000
TLB29PID = 00000000 TLB29WORD0 = 00000000 TLB29WORD1 = 00000000 TLB29WORD2 = 00000000
TLB30PID = 00000000 TLB30WORD0 = 00000000 TLB30WORD1 = 00000000 TLB30WORD2 = 00000000
TLB31PID = 00000000 TLB31WORD0 = 00000000 TLB31WORD1 = 00000000 TLB31WORD2 = 00000000
TLB32PID = 00000000 TLB32WORD0 = 00000000 TLB32WORD1 = 00000000 TLB32WORD2 = 00000000
TLB33PID = 00000000 TLB33WORD0 = 00000000 TLB33WORD1 = 00000000 TLB33WORD2 = 00000000
TLB34PID = 00000000 TLB34WORD0 = 00000000 TLB34WORD1 = 00000000 TLB34WORD2 = 00000000
TLB35PID = 00000000 TLB35WORD0 = 00000000 TLB35WORD1 = 00000000 TLB35WORD2 = 00000000
TLB36PID = 00000000 TLB36WORD0 = 00000000 TLB36WORD1 = 00000000 TLB36WORD2 = 00000000
TLB37PID = 00000000 TLB37WORD0 = 00000000 TLB37WORD1 = 00000000 TLB37WORD2 = 00000000
TLB38PID = 00000000 TLB38WORD0 = 00000000 TLB38WORD1 = 00000000 TLB38WORD2 = 00000000
TLB39PID = 00000000 TLB39WORD0 = 00000000 TLB39WORD1 = 00000000 TLB39WORD2 = 00000000
TLB40PID = 00000000 TLB40WORD0 = 00000000 TLB40WORD1 = 00000000 TLB40WORD2 = 00000000
TLB41PID = 00000000 TLB41WORD0 = 00000000 TLB41WORD1 = 00000000 TLB41WORD2 = 00000000
TLB42PID = 00000000 TLB42WORD0 = 00000000 TLB42WORD1 = 00000000 TLB42WORD2 = 00000000
TLB43PID = 00000000 TLB43WORD0 = 00000000 TLB43WORD1 = 00000000 TLB43WORD2 = 00000000
TLB44PID = 00000000 TLB44WORD0 = 00000000 TLB44WORD1 = 00000000 TLB44WORD2 = 00000000
TLB45PID = 00000000 TLB45WORD0 = 00000000 TLB45WORD1 = 00000000 TLB45WORD2 = 00000000
TLB46PID = 00000000 TLB46WORD0 = 00000000 TLB46WORD1 = 00000000 TLB46WORD2 = 00000000
TLB47PID = 00000000 TLB47WORD0 = 00000000 TLB47WORD1 = 00000000 TLB47WORD2 = 00000000
TLB48PID = 00000000 TLB48WORD0 = 00000000 TLB48WORD1 = 00000000 TLB48WORD2 = 00000000
TLB49PID = 00000000 TLB49WORD0 = 00000000 TLB49WORD1 = 00000000 TLB49WORD2 = 00000000
TLB50PID = 00000000 TLB50WORD0 = 00000000 TLB50WORD1 = 00000000 TLB50WORD2 = 00000000
TLB51PID = 00000000 TLB51WORD0 = 00000000 TLB51WORD1 = 00000000 TLB51WORD2 = 00000000
TLB52PID = 00000000 TLB52WORD0 = 00000000 TLB52WORD1 = 00000000 TLB52WORD2 = 00000000
TLB53PID = 00000000 TLB53WORD0 = 00000000 TLB53WORD1 = 00000000 TLB53WORD2 = 00000000
TLB54PID = 00000000 TLB54WORD0 = 00000000 TLB54WORD1 = 00000000 TLB54WORD2 = 00000000
TLB55PID = 00000000 TLB55WORD0 = 00000000 TLB55WORD1 = 00000000 TLB55WORD2 = 00000000
TLB56PID = 00000000 TLB56WORD0 = 00000000 TLB56WORD1 = 00000000 TLB56WORD2 = 00000000
TLB57PID = 00000000 TLB57WORD0 = 00000000 TLB57WORD1 = 00000000 TLB57WORD2 = 00000000
TLB58PID = 00000000 TLB58WORD0 = 00000000 TLB58WORD1 = 00000000 TLB58WORD2 = 00000000
TLB59PID = 00000000 TLB59WORD0 = 00000000 TLB59WORD1 = 00000000 TLB59WORD2 = 00000000
TLB60PID = 00000000 TLB60WORD0 = 00000000 TLB60WORD1 = 00000000 TLB60WORD2 = 00000000
TLB61PID = 00000000 TLB61WORD0 = 00000000 TLB61WORD1 = 00000000 TLB61WORD2 = 00000000
TLB62PID = 00000000 TLB62WORD0 = 00000000 TLB62WORD1 = 00000000 TLB62WORD2 = 00000000
TLB63PID = 00000000 TLB63WORD0 = C0000290 TLB63WORD1 = 00000000 TLB63WORD2 = 00000107
SRAM0 register Group. (SRAM0)
SRAM0_SB0CR = 80000800 SRAM0_SB1CR = 80010800 SRAM0_SB2CR = 80020800 SRAM0_SB3CR = 80030800
SRAM0_BEAR = 00000000 SRAM0_BESR0 = 00000000 SRAM0_BESR1 = 00000000 SRAM0_PMEG = 01E00000
SRAM0_CID = 322B0000 SRAM0_REVID = 04005800 SRAM0_DPC = 00000000
EBC0 register Group. (EBC0)
EBC0_CFG = 17004000 EBC0_B0CR = FF09A000 EBC0_B1CR = F001A000 EBC0_B2CR = F0118000
EBC0_B3CR = F0218000 EBC0_B4CR = F031A000 EBC0_B5CR = F041E000 EBC0_B6CR = F0518000
EBC0_B7CR = F0F18000 EBC0_B0AP = 9B015400 EBC0_B1AP = 9B055480 EBC0_B2AP = 1B015480
EBC0_B3AP = 12815280 EBC0_B4AP = 12815400 EBC0_B5AP = 1B015400 EBC0_B6AP = 00000000
EBC0_B7AP = 010502C0 EBC0_BEAR = 00000000 EBC0_BESR = 00000000 EBC0_CID = 32401093
EBC0_CFGADDR = 00000017 EBC0_CFGDATA = 010502C0
EBMI register Group. (EBMI)
EBM0_CTL = 88400000 EBM0_LCNT = 00000000 EBM0_BEAR = 00000000 EBM0_BESR = 00000000
EBM0_BEMR = 00000000 EBM0_UAR = 00000000 EBM0_UAM = 00000000 EBM0_SLPMD = 07C00000
EBM0_FAIR = FFF00000 EBM0_MISCSTS = 36000008 EBM0_CID = 32501054 EBM0_CFGADDR = 00000000
EBM0_CFGDATA = 88400000
SDRAM0 register Group. (SDRAM0)
SDRAM0_BESR0 = 00000000 SDRAM0_BESR1 = 00000000 SDRAM0_BEAR = 00000000 SDRAM0_MIRQ = 00000000
SDRAM0_UABBA = 00000000 SDRAM0_SLIO = 00000000 SDRAM0_DEVOPT = 00000000 SDRAM0_WDDCTR = 00000000
SDRAM0_CLKTR = 40000000 SDRAM0_CFG0A = 86000000 SDRAM0_CFG1 = 00000000 SDRAM0_PMIT = 07C00000
SDRAM0_TR0 = 410A4016 SDRAM0_TR1 = 80800828 SDRAM0_RTR = 04B00000 SDRAM0_B0CR = 000C4001
SDRAM0_B1CR = 00000000 SDRAM0_B2CR = 00000000 SDRAM0_B3CR = 00000000 SDRAM0_DLYCAL = 200000B0
SDRAM0_ECCESR = 00000000 SDRAM0_CID = 320B0000 SDRAM0_RID = 00003101 SDRAM0_CFG0B = 86000000
SDRAM0_MCSTS = A0000000 SDRAM0_CFGADDR = 0000004C SDRAM0_CFGDATA = 00000000
OCBUSES register Group. (OCBUSES)
PLB0_REVID = 00000101 PLB0_ACR = 9B000000 PLB0_BESR = 00000000 PLB0_BEARL = F77FFFFF
PLB0_BEARH = FDFFFFFF POB0_BESR0 = 00000000 POB0_BEARL = 00000000 POB0_BEARH = 00000000
POB0_BESR1 = 00000000 POB0_CONFG = 00000000 POB0_LATENCY = 78000000 POB0_REVID = 00000122
OPB0_BCTRL = 00000000 OPB0_BSTAT = 00000000 OPB0_BEARL = FFFFFFFF OPB0_BEARH = 0000000F
OPB0_REVID = 00000130
IVOR register Group. (IVOR)
IVOR0 = 00000240 IVOR1 = 00000340 IVOR2 = 00000460 IVOR3 = 00000560
IVOR4 = 00000620 IVOR5 = 000006E0 IVOR6 = 000007A0 IVOR7 = 00000860
IVOR8 = 00000920 IVOR9 = 000009E0 IVOR10 = 00000AA0 IVOR11 = 00000B60
IVOR12 = 00000C20 IVOR13 = 00000D20 IVOR14 = 00000DC0 IVOR15 = 00000E60
UIC register Group. (UIC)
UIC0_SR = 00000040 UIC0_ER = 00000000 UIC0_CR = 00000000 UIC0_PR = FFFFFE13
UIC0_TR = 01C00040 UIC0_MSR = 00000000 UIC0_VR = 00000000 UIC0_VCR = 00000040
UIC1_SR = 00002700 UIC1_ER = 00000000 UIC1_CR = 00000000 UIC1_PR = FFFFE0FF
UIC1_TR = 00FFC000 UIC1_MSR = 00000000 UIC1_VR = 00000000 UIC1_VCR = 00002700
UIC2_SR = 00000000 UIC2_ER = 00000100 UIC2_CR = 00000000 UIC2_PR = FFFFFFFF
UIC2_TR = 00FF8D0F UIC2_MSR = 00000000 UIC2_VR = 00000000 UIC2_VCR = 00000000
UICB0_SR = 03FFFFFF UICB0_ER = 54000000 UICB0_CR = 00000000 UICB0_PR = FC000000
UICB0_TR = 00000000 UICB0_MSR = 00000000 UICB0_VR = 00000000 UICB0_VCR = 03FFFFFF
DMA0 register Group. (DMA0)
DMA0_CR0 = 00000000 DMA0_CT0 = 00000000 DMA0_SAH0 = 00000000 DMA0_SAL0 = 00000000
DMA0_DAH0 = 00000000 DMA0_DAL0 = 00000000 DMA0_SGH0 = 00000000 DMA0_SGL0 = 00000000
DMA0_CR1 = 00000000 DMA0_CT1 = 00000000 DMA0_SAH1 = 00000000 DMA0_SAL1 = 00000000
DMA0_DAH1 = 00000000 DMA0_DAL1 = 00000000 DMA0_SGH1 = 00000000 DMA0_SGL1 = 00000000
DMA0_CR2 = 00000000 DMA0_CT2 = 00000000 DMA0_SAH2 = 00000000 DMA0_SAL2 = 00000000
DMA0_DAH2 = 00000000 DMA0_DAL2 = 00000000 DMA0_SGH2 = 00000000 DMA0_SGL2 = 00000000
DMA0_CR3 = 00000000 DMA0_CT3 = 00000000 DMA0_SAH3 = 00000000 DMA0_SAL3 = 00000000
DMA0_DAH3 = 00000000 DMA0_DAL3 = 00000000 DMA0_SGH3 = 00000000 DMA0_SGL3 = 00000000
DMA0_SR = 00008000 DMA0_SGC = 00000000 DMA0_SLP = 07C00000 DMA0_POL = 00000000
MAL0 register Group. (MAL0)
MAL0_CFG = 0037C086 MAL0_ESR = 00000000 MAL0_IER = 00000017 MAL0_TXCASR = 00000000
MAL0_TXCARR = 00000000 MAL0_TXEOBISR = 00000000 MAL0_TXDEIR = 00000000 MAL0_RXCASR = 00000000
MAL0_RXCARR = 00000000 MAL0_RXEOBISR = 00000000 MAL0_RXDEIR = 00000000 MAL0_TXCTP0R = 00000000
MAL0_TXCTP1R = 00000000 MAL0_TXCTP2R = 0FFA1340 MAL0_TXCTP3R = 00000000 MAL0_RXCTP0R = 00000000
MAL0_RXCTP1R = 00000000 MAL0_RXCTP2R = 0FFA13A0 MAL0_RXCTP3R = 00000000 MAL0_RCBS0 = 00000000
MAL0_RCBS1 = 00000000 MAL0_RCBS2 = 00000060 MAL0_RCBS3 = 00000000 MAL0_TXBADDR = 00000000
MAL0_RXBADDR = 00000000
PPM0 register Group. (PPM0)
PPM0_ISR = 00000000 PPM0_CR = 00000000 PPM0_CCR = FFFFFFFF PPM0_UAR = 00000000
PPM0_LAR = 00000000 PPM0_UAMR = FFFFFFFF PPM0_LAMR = FFFFFFFF PPM0_RIDR = C27E3411
PPM0_MCSR0 = 00000000 PPM0_MCSR1 = 00000000 PPM0_MCSR2 = 00000000 PPM0_MCSR3 = 00000000
PPM0_SCSR0 = 00000000 PPM0_SCSR1 = 00000000 PPM0_SCSR2 = 00000000 PPM0_SCSR3 = 00000000
PPM0_GCSR0 = 00000000 PPM0_GCSR1 = 00000000 PPM0_GCSR2 = 00000000 PPM0_GCSR3 = 00000000
PPM0_MCR0 = 00000000 PPM0_MCR1 = 00000000 PPM0_MCR2 = 00000000 PPM0_MCR3 = 00000000
PPM0_SCR0 = 00000000 PPM0_SCR1 = 00000000 PPM0_SCR2 = 00000000 PPM0_SCR3 = 00000000
PPM0_GCR0 = 00000000 PPM0_GCR1 = 00000000 PPM0_GCR2 = 00000000 PPM0_GCR3 = 00000000
PPM0_DCSR0 = 00000000 PPM0_DCSR1 = 00000000 PPM0_DCMXR0 = 00000000 PPM0_DCMXR1 = 00000000
PPM0_DCMNR0 = 00FFFFFF PPM0_DCMNR1 = 00FFFFFF PPM0_DCTVR0 = 00000000 PPM0_DCTVR1 = 00000000
PPM0_DCOTR0 = 00000000 PPM0_DCOTR1 = 00000000 PPM0_CFGADDR = 00000000 PPM0_CFGDATA = 00000000
^ permalink raw reply
* [PATCH] mpc85xx_ads: add in missing of_node_put()
From: Paul Gortmaker @ 2007-12-21 15:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sfr
cpm2_pic_init() does its own of_node_get() so we should do an of_node_put()
before calling it. This and other coding style cleanups as suggested by
Stephen Rothwell.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index bccdc25..ea4886f 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -52,9 +52,9 @@ static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
int cascade_irq;
- while ((cascade_irq = cpm2_get_irq()) >= 0) {
+ while ((cascade_irq = cpm2_get_irq()) >= 0)
generic_handle_irq(cascade_irq);
- }
+
desc->chip->eoi(irq);
}
@@ -70,13 +70,12 @@ static void __init mpc85xx_ads_pic_init(void)
#endif
np = of_find_node_by_type(np, "open-pic");
-
- if (np == NULL) {
+ if (!np) {
printk(KERN_ERR "Could not find open-pic node\n");
return;
}
- if(of_address_to_resource(np, 0, &r)) {
+ if (of_address_to_resource(np, 0, &r)) {
printk(KERN_ERR "Could not map mpic register space\n");
of_node_put(np);
return;
@@ -98,6 +97,7 @@ static void __init mpc85xx_ads_pic_init(void)
return;
}
irq = irq_of_parse_and_map(np, 0);
+ of_node_put(np);
cpm2_pic_init(np);
set_irq_chained_handler(irq, cpm2_cascade);
@@ -112,7 +112,7 @@ struct cpm_pin {
int port, pin, flags;
};
-static struct cpm_pin mpc8560_ads_pins[] = {
+static const struct cpm_pin mpc8560_ads_pins[] = {
/* SCC1 */
{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* CONFIG_PCI interaction with pata_platform driver on MPC834x board
From: Johns Daniel @ 2007-12-21 15:37 UTC (permalink / raw)
To: linuxppc-embedded
I am observing a strange interaction between configuring PCI support
in my kernel and CompactFlash probing. Without PCI support configured,
the CF card is discovered and configured by the kernel. With PCI
support configured, there is some issue in the probing of the CF card.
There are only two things that I notice between the two kernel setups
that might be significant:
1.) The libata virq changes from 19 to 20.
2.) The isa_io_base changes from 0x0 to 0xfcfff000.
Are either of these two changes significant?
I am using the "arch/powerpc" kernel, version 2.6.20.21. The CF is
wired directly to the local bus in True IDE mode.
I have some debug info included below.
-- Johns
================ without CONFIG_PCI =================
ata_device_add: ENTER
ata_port_add: ENTER
ata_port_start: prd alloc, virt dfe2a000, dma 1fe2a000
ata1: PATA max PIO0 cmd 0xE1062000 ctl 0xE106420C bmdma 0x0 irq 19
__ata_port_freeze: ata1 port frozen
ata_device_add: probe begin
scsi0 : pata_platform
ata_port_schedule_eh: port EH scheduled
ata_scsi_error: ENTER
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata_eh_autopsy: ENTER
ata_eh_recover: ENTER
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x0 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEC
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x50)
ata_hsm_move: ata1: dev 0 command complete, drv_stat 0x50
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata_dump_id: 49==0x0200 53==0x0003 63==0x0000 64==0x0003 75==0x0000
ata_dump_id: 80==0x0400 81==0x0000 82==0x0000 83==0x0000 84==0x0000
ata_dump_id: 88==0x0000 93==0x0000
ata1.00: CFA, max PIO4, 250880 sectors: LBA
ata1.00: ata1: dev 0 multi count 0
ata_eh_revalidate_and_attach: EXIT
ata_eh_resume: ENTER
ata_eh_resume: EXIT
ata_eh_suspend: ENTER
ata_eh_suspend: EXIT
ata_eh_recover: EXIT, rc=0
ata_scsi_error: EXIT
ata_device_add: host probe begin
ata_scsi_dump_cdb: CDB (1:0,0,0) 12 00 00 00 24 00 30 58 df
ata_scsiop_inq_std: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 12 00 00 00 60 00 30 58 df
ata_scsiop_inq_std: ENTER
scsi 0:0:0:0: Direct-Access ATA SanDisk SDCFH-12 HDB PQ: 0 ANSI: 5
ata_scsi_dump_cdb: CDB (1:0,0,0) 00 00 00 00 00 00 30 58 df
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 25 00 00 00 00 00 00 00 00
ata_scsiop_read_cap: ENTER
SCSI device sda: 250880 512-byte hdwr sectors (128 MB)
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 3f 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
sda: Write Protect is off
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 24
ata_scsiop_mode_sense: ENTER
SCSI device sda: write cache: disabled, read cache: enabled, doesn't
support DPO or FUA
ata_scsi_dump_cdb: CDB (1:0,0,0) 00 00 00 00 00 00 00 00 24
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 1e 00 00 00 01 00 00 00 24
ata_scsi_dump_cdb: CDB (1:0,0,0) 00 00 00 00 00 00 00 00 24
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 25 00 00 00 00 00 00 00 00
ata_scsiop_read_cap: ENTER
SCSI device sda: 250880 512-byte hdwr sectors (128 MB)
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 3f 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
sda: Write Protect is off
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 24
ata_scsiop_mode_sense: ENTER
SCSI device sda: write cache: disabled, read cache: enabled, doesn't
support DPO or FUA
sda:<3>ata_scsi_dump_cdb: CDB (1:0,0,0) 28 00 00 00 00 00 00 00 08
ata_scsi_translate: ENTER
scsi_10_lba_len: ten-byte command
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x8 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xE0
ata_exec_command_mmio: ata1: cmd 0x20
ata_scsi_translate: EXIT
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_host_intr: ata1: protocol 2 task_state 1
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x50)
ata_hsm_move: ata1: dev 0 command complete, drv_stat 0x50
sda1 sda2 sda3
sd 0:0:0:0: Attached scsi removable disk sda
ata_device_add: EXIT, returning 1
================ without CONFIG_PCI =================
================== with CONFIG_PCI =================
ata_device_add: ENTER
ata_port_add: ENTER
ata_port_start: prd alloc, virt dfe46000, dma 1fe46000
ata1: PATA max PIO0 cmd 0xE1062000 ctl 0xE106420C bmdma 0x0 irq 20
__ata_port_freeze: ata1 port frozen
ata_device_add: probe begin
scsi0 : pata_platform
ata_port_schedule_eh: port EH scheduled
ata_scsi_error: ENTER
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata_eh_autopsy: ENTER
ata_eh_recover: ENTER
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x0 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEC
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ATA: abnormal status 0x58 on port 0xE106200E
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x58)
ata_hsm_move: ata1: protocol 2 task_state 3 (dev_stat 0x58)
__ata_port_freeze: ata1 port frozen
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata1.00: failed to IDENTIFY (I/O error, err_mask=0x2)
ata_eh_revalidate_and_attach: EXIT
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x0 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEC
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ATA: abnormal status 0x58 on port 0xE106200E
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x58)
ata_hsm_move: ata1: protocol 2 task_state 3 (dev_stat 0x58)
__ata_port_freeze: ata1 port frozen
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata1.00: failed to IDENTIFY (I/O error, err_mask=0x2)
ata_eh_revalidate_and_attach: EXIT
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata1: ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x0 nsect 0x0 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEC
ata_hsm_move: ata1: protocol 2 task_state 1 (dev_stat 0x58)
ata_pio_sector: data read
ATA: abnormal status 0x58 on port 0xE106200E
ata_hsm_move: ata1: protocol 2 task_state 2 (dev_stat 0x58)
ata_hsm_move: ata1: protocol 2 task_state 3 (dev_stat 0x58)
__ata_port_freeze: ata1 port frozen
ata_port_flush_task: ENTER
ata_port_flush_task: flush #1
ata1.00: failed to IDENTIFY (I/O error, err_mask=0x2)
ata_eh_revalidate_and_attach: EXIT
ata_eh_prep_resume: ENTER
ata_eh_prep_resume: EXIT
__ata_port_freeze: ata1 port frozen
ata_std_softreset: ENTER
ata_std_softreset: about to softreset, devmask=3
ata_bus_softreset: ata1: bus reset via SRST
ata_dev_classify: found ATA device by sig
ata_dev_classify: found ATA device by sig
ata_std_softreset: EXIT, classes[0]=1 [1]=5
ata_std_postreset: ENTER
ata_std_postreset: EXIT
ata_eh_thaw_port: ata1 port thawed
ata_eh_revalidate_and_attach: ENTER
ata_eh_revalidate_and_attach: EXIT
ata_eh_resume: ENTER
ata_eh_resume: EXIT
ata_eh_suspend: ENTER
ata_eh_suspend: EXIT
ata_eh_recover: EXIT, rc=0
ata_scsi_error: EXIT
ata_device_add: host probe begin
ata_device_add: EXIT, returning 1
================== with CONFIG_PCI =================
^ permalink raw reply
* Re: [PATCH 1/4] sbc8560: add basic support for Wind River SBC8560 as powerpc
From: Paul Gortmaker @ 2007-12-21 15:37 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev
In-Reply-To: <20071221101425.3408278c.sfr@canb.auug.org.au>
In message: Re: [PATCH 1/4] sbc8560: add basic support for Wind River SBC8560 as powerpc
on 21/12/2007 Stephen Rothwell wrote:
> Hi Paul,
>
> Just a couple of comments.
[...]
> The braces are unnecessary.
>
[...]
> We often say "if (!np)" and leave out the blank line above.
>
> > + if(of_address_to_resource(np, 0, &r)) {
> ^
> Put a space here.
[...]
> Need an of_node_pit(np) - cpm2_pic_init() does its own of_node_get.
>
> > +static struct cpm_pin sbc8560_pins[] = {
>
> const?
>
Sounds reasonable to me. I've integrated these into sbc8560.c (still
looking at how to handle the duart/dts based on feedback). Since I'd
inerited the things you'd requested fixes on from mpc85xx_ads.c, it
probably makes sense to fix them there too I would imagine. I'll send
that under its own subject in a minute.
Paul.
^ permalink raw reply
* Re: [PATCH 2/3] sbc8548: Add device tree source for Wind River SBC8548 board
From: Kumar Gala @ 2007-12-21 15:33 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev
In-Reply-To: <1198219435310-git-send-email-paul.gortmaker@windriver.com>
On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:
> This adds the device tree source for the Wind River SBC8548 board.
> The
> biggest difference between this and the MPC8548CDS reference platform
> is the absence of the CDS's Arcadia peripherals and physical access
> to PCI#2.
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> arch/powerpc/boot/dts/sbc8548.dts | 242 ++++++++++++++++++++++++++++
> +++++++++
> 1 files changed, 242 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/
> dts/sbc8548.dts
> new file mode 100644
> index 0000000..e63ed20
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/sbc8548.dts
> @@ -0,0 +1,242 @@
> +/*
> + * SBC8548 Device Tree Source
> + *
> + * Copyright 2007 Wind River Systems Inc.
> + *
> + * Paul Gortmaker (see MAINTAINERS for contact information)
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +
> +/ {
> + model = "SBC8548";
> + compatible = "SBC8548";
> + #address-cells = <1>;
> + #size-cells = <1>;
mind looking at converting this to a dts-v1 format?
- k
^ permalink raw reply
* Re: [PATCH 1/3] sbc8548: Add basic support for Wind River SBC8548 as powerpc
From: Kumar Gala @ 2007-12-21 15:32 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev
In-Reply-To: <11982194344016-git-send-email-paul.gortmaker@windriver.com>
On Dec 21, 2007, at 12:43 AM, Paul Gortmaker wrote:
> This adds the basic support for the Wind River SBC8548 board,
> implemented
> as powerpc. It closely follows the implementation of the MPC8548CDS.
>
> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig | 10 ++-
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/sbc8548.c | 182 ++++++++++++++++++++++++
> +++++++++
> 3 files changed, 191 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/
> platforms/85xx/Kconfig
> index 33d3bea..8407f43 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -39,6 +39,12 @@ config MPC85xx_DS
> help
> This option enables support for the MPC85xx DS (MPC8544 DS) board
>
> +config SBC8548
> + bool "Wind River SBC8548"
> + select DEFAULT_UIMAGE
> + help
> + This option enables support for the Wind River SBC8548 board
> +
> config SBC8560
> bool "Wind River SBC8560"
> select DEFAULT_UIMAGE
> @@ -52,7 +58,7 @@ config MPC8540
> bool
> select PPC_UDBG_16550
> select PPC_INDIRECT_PCI
> - default y if MPC8540_ADS || MPC85xx_CDS
> + default y if MPC8540_ADS || MPC85xx_CDS || SBC8548
>
> config MPC8560
> bool
> @@ -66,4 +72,4 @@ config MPC85xx
> select FSL_PCI if PCI
> select SERIAL_8250_SHARE_IRQ if SERIAL_8250
> default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
> - || MPC85xx_MDS || MPC85xx_DS || SBC8560
> + || MPC85xx_MDS || MPC85xx_DS || SBC8560 || SBC8548
> diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/
> platforms/85xx/Makefile
> index c3f4d01..3a47b7a 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -6,4 +6,5 @@ obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
> obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
> obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
> obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
> +obj-$(CONFIG_SBC8548) += sbc8548.o
> obj-$(CONFIG_SBC8560) += sbc8560.o
> diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/
> platforms/85xx/sbc8548.c
> new file mode 100644
> index 0000000..f3ab271
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/sbc8548.c
> @@ -0,0 +1,182 @@
> +/*
> + * Wind River SBC8548 setup and early boot code.
> + *
> + * Copyright 2007 Wind River Systems Inc.
> + *
> + * By Paul Gortmaker (see MAINTAINERS for contact information)
> + *
> + * Based largely on the MPC8548CDS support - Copyright 2005
> Freescale Inc.
> + *
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/reboot.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/major.h>
> +#include <linux/console.h>
> +#include <linux/delay.h>
> +#include <linux/seq_file.h>
> +#include <linux/initrd.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/fsl_devices.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/system.h>
> +#include <asm/pgtable.h>
> +#include <asm/page.h>
> +#include <asm/atomic.h>
> +#include <asm/time.h>
> +#include <asm/io.h>
> +#include <asm/machdep.h>
> +#include <asm/ipic.h>
> +#include <asm/pci-bridge.h>
> +#include <asm/irq.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +
> +#ifdef CONFIG_PCI
> +static int sbc8548_exclude_device(struct pci_controller *hose,
> + u_char bus, u_char devfn)
> +{
> + if (bus == 0 && PCI_SLOT(devfn) == 0)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> + else
> + return PCIBIOS_SUCCESSFUL;
> +}
> +#endif
see comment on the 8560 support, but I don't think you need to exclude
the PHBs anymore. I've fixed this so we have a general quick for FSL
PHBs.
>
- k
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