* Re: [PATCH 3/7] sbc8560: add support for Wind River SBC8560 in arch/powerpc
From: Paul Gortmaker @ 2008-01-09 4:39 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev
In-Reply-To: <20080108113219.860ac365.sfr@canb.auug.org.au>
Stephen Rothwell wrote:
> Hi Paul,
>
> On Mon, 7 Jan 2008 09:25:28 -0500 Paul Gortmaker <paul.gortmaker@windriver.com> wrote:
>
>
[...]
>> +static const struct cpm_pin sbc8560_pins[] = {
>>
>
> Of course, these could be __initdata (but not const as well). Sorry
> about not mentioning this last time and it is a trivial change that
> should not stop this stuff going in.
>
No problem. I think you will find all these issues are applicable to
the mpc8560mds support that I based things off too. I'd rather do
a single patch for both boards to deal with these, rather than respin
the sbc8560 patches again and leave the mpc8560mds behind.
Assuming everyone else is OK with this approach.
Thanks,
Paul.
^ permalink raw reply
* Re: [PATCH 1/8] pseries: phyp dump: Docmentation
From: Michael Ellerman @ 2008-01-09 4:58 UTC (permalink / raw)
To: Nathan Lynch; +Cc: lkessler, linuxppc-dev, mahuja, linasvepstas, strosake
In-Reply-To: <20080109042911.GT14201@localdomain>
[-- Attachment #1: Type: text/plain, Size: 4886 bytes --]
On Tue, 2008-01-08 at 22:29 -0600, Nathan Lynch wrote:
> Manish Ahuja wrote:
> > +
> > + Hypervisor-Assisted Dump
> > + ------------------------
> > + November 2007
>
> Date is unneeded (and, uhm, dated :)
>
>
> > +The goal of hypervisor-assisted dump is to enable the dump of
> > +a crashed system, and to do so from a fully-reset system, and
> > +to minimize the total elapsed time until the system is back
> > +in production use.
>
> Is it actually faster than kdump?
>
>
> > +As compared to kdump or other strategies, hypervisor-assisted
> > +dump offers several strong, practical advantages:
> > +
> > +-- Unlike kdump, the system has been reset, and loaded
> > + with a fresh copy of the kernel. In particular,
> > + PCI and I/O devices have been reinitialized and are
> > + in a clean, consistent state.
> > +-- As the dump is performed, the dumped memory becomes
> > + immediately available to the system for normal use.
> > +-- After the dump is completed, no further reboots are
> > + required; the system will be fully usable, and running
> > + in it's normal, production mode on it normal kernel.
> > +
> > +The above can only be accomplished by coordination with,
> > +and assistance from the hypervisor. The procedure is
> > +as follows:
> > +
> > +-- When a system crashes, the hypervisor will save
> > + the low 256MB of RAM to a previously registered
> > + save region. It will also save system state, system
> > + registers, and hardware PTE's.
> > +
> > +-- After the low 256MB area has been saved, the
> > + hypervisor will reset PCI and other hardware state.
> > + It will *not* clear RAM. It will then launch the
> > + bootloader, as normal.
> > +
> > +-- The freshly booted kernel will notice that there
> > + is a new node (ibm,dump-kernel) in the device tree,
> > + indicating that there is crash data available from
> > + a previous boot. It will boot into only 256MB of RAM,
> > + reserving the rest of system memory.
> > +
> > +-- Userspace tools will parse /sys/kernel/release_region
> > + and read /proc/vmcore to obtain the contents of memory,
> > + which holds the previous crashed kernel. The userspace
> > + tools may copy this info to disk, or network, nas, san,
> > + iscsi, etc. as desired.
> > +
> > + For Example: the values in /sys/kernel/release-region
> > + would look something like this (address-range pairs).
> > + CPU:0x177fee000-0x10000: HPTE:0x177ffe020-0x1000: /
> > + DUMP:0x177fff020-0x10000000, 0x10000000-0x16F1D370A
> > +
> > +-- As the userspace tools complete saving a portion of
> > + dump, they echo an offset and size to
> > + /sys/kernel/release_region to release the reserved
> > + memory back to general use.
> > +
> > + An example of this is:
> > + "echo 0x40000000 0x10000000 > /sys/kernel/release_region"
> > + which will release 256MB at the 1GB boundary.
>
> This violates the "one file, one value" rule of sysfs, but nobody
> really takes that seriously, I guess. In any case, consider
> documenting this in Documentation/ABI.
>
>
> > +
> > +Please note that the hypervisor-assisted dump feature
> > +is only available on Power6-based systems with recent
> > +firmware versions.
>
> This statement will of course become dated/incorrect so I recommend
> removing it.
>
>
> > +
> > +Implementation details:
> > +----------------------
> > +In order for this scheme to work, memory needs to be reserved
> > +quite early in the boot cycle. However, access to the device
> > +tree this early in the boot cycle is difficult, and device-tree
> > +access is needed to determine if there is a crash data waiting.
>
> I don't think this bit about early device tree access is correct. By
> the time your code is reserving memory (from early_init_devtree(), I
> think), RTAS has been instantiated and you are able to test for the
> existence of /rtas/ibm,dump-kernel.
Yep it's early_init_devtree(), and yes it's fairly easy to access the
(flattened) device tree at that point.
> > +To work around this problem, all but 256MB of RAM is reserved
> > +during early boot. A short while later in boot, a check is made
> > +to determine if there is dump data waiting. If there isn't,
> > +then the reserved memory is released to general kernel use.
>
> So I think these gymnastics are unneeded -- unless I'm
> misunderstanding something, you should be able to determine very early
> whether to reserve that memory.
I agree.
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: printk() does not work on UART1
From: mike zheng @ 2008-01-09 5:06 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <5c9cd53b0801081611ve59e9a8q6ae2fd227bfc0ed8@mail.gmail.com>
Hi All,
I have one mpc8568 board using UART1 as the serial port. The OS is
Linux Kernel2.4. If I use the polling mode driver of
gen550_progress(), it works fine. However the printk() does not work
after the console_init(). Anyone know what shall I change in the
kernel to use UART1 as serial console? I assume the default is UART0,
but I don't know where the value is set. I changed the CONFIG_CMDLINE
to ttyS1, it does NOT work.
Thanks for your help,
Mike
^ permalink raw reply
* [PATCH V2] [POWERPC] Add common clock setting routine mpc52xx_psc_set_clkdiv()
From: Grant Likely @ 2008-01-09 5:09 UTC (permalink / raw)
To: linuxppc-dev
From: Grant Likely <grant.likely@secretlab.ca>
PSC drivers should not access the CDM registers directly. Instead provide
a common routine for setting the PSC clock parameters with the required
locking.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
---
arch/powerpc/platforms/52xx/efika.c | 3 +
arch/powerpc/platforms/52xx/lite5200.c | 10 +--
arch/powerpc/platforms/52xx/mpc5200_simple.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 90 +++++++++++++++++++++++---
arch/ppc/syslib/mpc52xx_setup.c | 36 ++++++++++
include/asm-powerpc/mpc52xx.h | 13 ++--
6 files changed, 134 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c
index a0da70c..a2068fa 100644
--- a/arch/powerpc/platforms/52xx/efika.c
+++ b/arch/powerpc/platforms/52xx/efika.c
@@ -180,6 +180,9 @@ static void __init efika_setup_arch(void)
{
rtas_initialize();
+ /* Map important registers from the internal memory map */
+ mpc52xx_map_common_devices();
+
efika_pcisetup();
#ifdef CONFIG_PM
diff --git a/arch/powerpc/platforms/52xx/lite5200.c b/arch/powerpc/platforms/52xx/lite5200.c
index f8ba5f2..42e87b6 100644
--- a/arch/powerpc/platforms/52xx/lite5200.c
+++ b/arch/powerpc/platforms/52xx/lite5200.c
@@ -150,15 +150,15 @@ static void __init lite5200_setup_arch(void)
if (ppc_md.progress)
ppc_md.progress("lite5200_setup_arch()", 0);
- /* Fix things that firmware should have done. */
- lite5200_fix_clock_config();
- lite5200_fix_port_config();
+ /* Map important registers from the internal memory map */
+ mpc52xx_map_common_devices();
/* Some mpc5200 & mpc5200b related configuration */
mpc5200_setup_xlb_arbiter();
- /* Map wdt for mpc52xx_restart() */
- mpc52xx_map_wdt();
+ /* Fix things that firmware should have done. */
+ lite5200_fix_clock_config();
+ lite5200_fix_port_config();
#ifdef CONFIG_PM
mpc52xx_suspend.board_suspend_prepare = lite5200_suspend_prepare;
diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c
index 754aa93..c48b82b 100644
--- a/arch/powerpc/platforms/52xx/mpc5200_simple.c
+++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c
@@ -39,12 +39,12 @@ static void __init mpc5200_simple_setup_arch(void)
if (ppc_md.progress)
ppc_md.progress("mpc5200_simple_setup_arch()", 0);
+ /* Map important registers from the internal memory map */
+ mpc52xx_map_common_devices();
+
/* Some mpc5200 & mpc5200b related configuration */
mpc5200_setup_xlb_arbiter();
- /* Map wdt for mpc52xx_restart() */
- mpc52xx_map_wdt();
-
mpc52xx_setup_pci();
}
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 59346e3..ee104dd 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -13,6 +13,7 @@
#undef DEBUG
#include <linux/kernel.h>
+#include <linux/spinlock.h>
#include <linux/of_platform.h>
#include <asm/io.h>
#include <asm/prom.h>
@@ -24,7 +25,9 @@
* from interrupt context while node mapping (which calls ioremap())
* cannot be used at such point.
*/
-static volatile struct mpc52xx_gpt *mpc52xx_wdt = NULL;
+static spinlock_t mpc52xx_lock = SPIN_LOCK_UNLOCKED;
+static struct mpc52xx_gpt __iomem *mpc52xx_wdt;
+static struct mpc52xx_cdm __iomem *mpc52xx_cdm;
/**
* mpc52xx_find_ipb_freq - Find the IPB bus frequency for a device
@@ -93,16 +96,24 @@ mpc5200_setup_xlb_arbiter(void)
iounmap(xlb);
}
-static struct of_device_id __init mpc52xx_ids[] = {
+/*
+ * Match table used by mpc52xx_declare_of_platform_devices
+ */
+static struct of_device_id mpc52xx_ids[] __initdata = {
{ .compatible = "fsl,mpc5200-immr", },
{ .compatible = "fsl,lpb", },
/* depreciated matches; shouldn't be used in new device trees */
{ .type = "builtin", .compatible = "mpc5200", }, /* efika */
- { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
+ { .type = "soc", .compatible = "mpc5200", }, /* old */
{}
};
+/**
+ * mpc52xx_declare_of_platform_devices: register internal devices and children
+ * of the localplus bus to the of_platform
+ * bus.
+ */
void __init
mpc52xx_declare_of_platform_devices(void)
{
@@ -112,30 +123,87 @@ mpc52xx_declare_of_platform_devices(void)
"Error while probing of_platform bus\n");
}
+/*
+ * match tables used by mpc52xx_map_common_devices()
+ */
+static struct of_device_id mpc52xx_gpt_ids[] __initdata = {
+ { .compatible = "fsl,mpc5200-gpt", },
+ { .compatible = "mpc5200-gpt", }, /* old */
+ {}
+};
+static struct of_device_id mpc52xx_cdm_ids[] __initdata = {
+ { .compatible = "fsl,mpc5200-cdm", },
+ { .compatible = "mpc5200-cdm", }, /* old */
+ {}
+};
+
+/**
+ * mpc52xx_map_common_devices: iomap devices required by common code
+ */
void __init
-mpc52xx_map_wdt(void)
+mpc52xx_map_common_devices(void)
{
struct device_node *np;
- struct of_device_id gpt_ids[] = {
- { .compatible = "fsl,mpc5200-gpt", },
- { .compatible = "mpc5200-gpt", },
- {}
- };
/* mpc52xx_wdt is mapped here and used in mpc52xx_restart,
* possibly from a interrupt context. wdt is only implement
* on a gpt0, so check has-wdt property before mapping.
*/
- for_each_matching_node(np, gpt_ids) {
+ for_each_matching_node(np, mpc52xx_gpt_ids) {
if (of_get_property(np, "fsl,has-wdt", NULL) ||
of_get_property(np, "has-wdt", NULL)) {
mpc52xx_wdt = of_iomap(np, 0);
of_node_put(np);
- return;
+ break;
}
}
+
+ /* Clock Distribution Module, used by PSC clock setting function */
+ np = of_find_matching_node(NULL, mpc52xx_cdm_ids);
+ mpc52xx_cdm = of_iomap(np, 0);
+ of_node_put(np);
+}
+
+/**
+ * mpc52xx_set_psc_clkdiv: Set clock divider in the CDM for PSC ports
+ *
+ * @psc_id: id of psc port; must be 1,2,3 or 6
+ * @clkdiv: clock divider value to put into CDM PSC register.
+ */
+int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
+{
+ unsigned long flags;
+ u16 __iomem *reg;
+ u32 val;
+ u32 mask;
+ u32 mclken_div;
+
+ if (!mpc52xx_cdm)
+ return -ENODEV;
+
+ mclken_div = 0x8000 | (clkdiv & 0x1FF);
+ switch (psc_id) {
+ case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break;
+ case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break;
+ case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break;
+ case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break;
+ default:
+ return -ENODEV;
+ }
+
+ /* Set the rate and enable the clock */
+ spin_lock_irqsave(&mpc52xx_lock, flags);
+ out_be16(reg, mclken_div);
+ val = in_be32(&mpc52xx_cdm->clk_enables);
+ out_be32(&mpc52xx_cdm->clk_enables, val | mask);
+ spin_unlock_irqrestore(&mpc52xx_lock, flags);
+
+ return 0;
}
+/**
+ * mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer
+ */
void
mpc52xx_restart(char *cmd)
{
diff --git a/arch/ppc/syslib/mpc52xx_setup.c b/arch/ppc/syslib/mpc52xx_setup.c
index ecfa2c0..57c9c87 100644
--- a/arch/ppc/syslib/mpc52xx_setup.c
+++ b/arch/ppc/syslib/mpc52xx_setup.c
@@ -16,6 +16,7 @@
*/
+#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/time.h>
#include <asm/mpc52xx.h>
@@ -275,3 +276,38 @@ int mpc52xx_match_psc_function(int psc_idx, const char *func)
return 0;
}
+
+int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
+{
+ static spinlock_t lock = SPIN_LOCK_UNLOCKED;
+ struct mpc52xx_cdm __iomem *cdm;
+ unsigned long flags;
+ u16 mclken_div;
+ u16 __iomem *reg;
+ u32 mask;
+
+ cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
+ if (!cdm) {
+ printk(KERN_ERR __FILE__ ": Error mapping CDM\n");
+ return -ENODEV;
+ }
+
+ mclken_div = 0x8000 | (clkdiv & 0x1FF);
+ switch (psc_id) {
+ case 1: reg = &cdm->mclken_div_psc1; mask = 0x20; break;
+ case 2: reg = &cdm->mclken_div_psc2; mask = 0x40; break;
+ case 3: reg = &cdm->mclken_div_psc3; mask = 0x80; break;
+ case 6: reg = &cdm->mclken_div_psc6; mask = 0x10; break;
+ default:
+ return -ENODEV;
+ }
+
+ /* Set the rate and enable the clock */
+ spin_lock_irqsave(&lock, flags);
+ out_be16(reg, mclken_div);
+ out_be32(&cdm->clk_enables, in_be32(&cdm->clk_enables) | mask);
+ spin_unlock_irqrestore(&lock, flags);
+
+ iounmap(cdm);
+ return 0;
+}
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
index 1c48c6d..c7a0710 100644
--- a/include/asm-powerpc/mpc52xx.h
+++ b/include/asm-powerpc/mpc52xx.h
@@ -248,13 +248,19 @@ struct mpc52xx_cdm {
#ifndef __ASSEMBLY__
+/* mpc52xx_common.c */
extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
-extern void mpc5200_setup_xlb_arbiter(void);
-extern void mpc52xx_declare_of_platform_devices(void);
+extern void __init mpc5200_setup_xlb_arbiter(void);
+extern void __init mpc52xx_declare_of_platform_devices(void);
+extern void __init mpc52xx_map_common_devices(void);
+extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
+extern void mpc52xx_restart(char *cmd);
+/* mpc52xx_pic.c */
extern void mpc52xx_init_irq(void);
extern unsigned int mpc52xx_get_irq(void);
+/* mpc52xx_pci.c */
#ifdef CONFIG_PCI
extern int __init mpc52xx_add_bridge(struct device_node *node);
extern void __init mpc52xx_setup_pci(void);
@@ -262,9 +268,6 @@ extern void __init mpc52xx_setup_pci(void);
static inline void mpc52xx_setup_pci(void) { }
#endif
-extern void __init mpc52xx_map_wdt(void);
-extern void mpc52xx_restart(char *cmd);
-
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_PM
^ permalink raw reply related
* printk() does not work on UART1
From: mike zheng @ 2008-01-09 5:11 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <5c9cd53b0801081611ve59e9a8q6ae2fd227bfc0ed8@mail.gmail.com>
Hi All,
I have one mpc8568 board using UART1 as the serial port. The OS is
Linux Kernel2.4. If I use the polling mode driver of
gen550_progress(), it works fine. However the printk() does not work
after the console_init(). Anyone know what shall I change in the
kernel to use UART1 as serial console? I assume the default is UART0,
but I don't know where the value is set. I changed the CONFIG_CMDLINE
to ttyS1, it does NOT work.
Thanks for your help,
Mike
^ permalink raw reply
* [PATCH 0/5] Powerpc support for SBC8548 board
From: Paul Gortmaker @ 2008-01-09 5:18 UTC (permalink / raw)
To: linuxppc-dev
This is a repost of the SBC8548 patches, as requested, which contains the
dts-v1 patch and the pci exclude removal in addition to the original
three 8548 patches. These are layered on top of the SBC8560 patches
I'd sent yesterday (since they both go after the same Makefile/Kconfig etc).
The patches are as follows:
1) Add basic support for Wind River SBC8548 as powerpc
This adds in the basic platform support file -- closely matching that which
exists for the MPC8548CDS board.
2) Add device tree source for Wind River SBC8548 board
This also closely matches what exists for the MPC8548CDS platform. The big
difference here is that this board doesn't have physical access to PCI#2
and it doesn't have the CDS's bridges, i8259, peripherals, etc, so the dts
is overall quite a bit smaller. I've believe I've got all aliases and the
associated gianfar updates etc. that I'd somehow missed in the sbc8560 dts.
3) Add default .config file for Wind River SBC8548
This config gives basic serial console and ethernet support for doing an
NFS root setup. The SBC8548 has one PCI-X slot, and a short PCI-e slot,
so I've enabled PCI.
4) Convert device tree to be dts-v1 compatible
Tag all the values/resources normally in hex with 0x; convert items like
frequencies usually expressed in decimal to decimal; add the dts-v1 tag.
5) Remove PCI exclude device for sbc8548 and sbc8560
The exclude device doesn't need to filter out the PHB anymore, and since
that was all it was doing, it can go entirely.
Paul.
^ permalink raw reply
* [PATCH 1/5] sbc8548: Add basic support for Wind River SBC8548 as powerpc
From: Paul Gortmaker @ 2008-01-09 5:18 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Gortmaker
In-Reply-To: <1199855910574-git-send-email-paul.gortmaker@windriver.com>
This adds the basic support for the Wind River SBC8548 board, implemented
as powerpc. It closely follows the implementation of the MPC8548CDS.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/platforms/85xx/Kconfig | 10 ++-
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/sbc8548.c | 182 +++++++++++++++++++++++++++++++++
3 files changed, 191 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 33d3bea..8407f43 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -39,6 +39,12 @@ config MPC85xx_DS
help
This option enables support for the MPC85xx DS (MPC8544 DS) board
+config SBC8548
+ bool "Wind River SBC8548"
+ select DEFAULT_UIMAGE
+ help
+ This option enables support for the Wind River SBC8548 board
+
config SBC8560
bool "Wind River SBC8560"
select DEFAULT_UIMAGE
@@ -52,7 +58,7 @@ config MPC8540
bool
select PPC_UDBG_16550
select PPC_INDIRECT_PCI
- default y if MPC8540_ADS || MPC85xx_CDS
+ default y if MPC8540_ADS || MPC85xx_CDS || SBC8548
config MPC8560
bool
@@ -66,4 +72,4 @@ config MPC85xx
select FSL_PCI if PCI
select SERIAL_8250_SHARE_IRQ if SERIAL_8250
default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
- || MPC85xx_MDS || MPC85xx_DS || SBC8560
+ || MPC85xx_MDS || MPC85xx_DS || SBC8560 || SBC8548
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index c3f4d01..3a47b7a 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+obj-$(CONFIG_SBC8548) += sbc8548.o
obj-$(CONFIG_SBC8560) += sbc8560.o
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
new file mode 100644
index 0000000..f3ab271
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -0,0 +1,182 @@
+/*
+ * Wind River SBC8548 setup and early boot code.
+ *
+ * Copyright 2007 Wind River Systems Inc.
+ *
+ * By Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * Based largely on the MPC8548CDS support - Copyright 2005 Freescale Inc.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/initrd.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/fsl_devices.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/pci-bridge.h>
+#include <asm/irq.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#ifdef CONFIG_PCI
+static int sbc8548_exclude_device(struct pci_controller *hose,
+ u_char bus, u_char devfn)
+{
+ if (bus == 0 && PCI_SLOT(devfn) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ else
+ return PCIBIOS_SUCCESSFUL;
+}
+#endif
+
+static void __init sbc8548_pic_init(void)
+{
+ struct mpic *mpic;
+ struct resource r;
+ struct device_node *np = NULL;
+
+ np = of_find_node_by_type(np, "open-pic");
+
+ if (np == NULL) {
+ printk(KERN_ERR "Could not find open-pic node\n");
+ return;
+ }
+
+ if (of_address_to_resource(np, 0, &r)) {
+ printk(KERN_ERR "Failed to map mpic register space\n");
+ of_node_put(np);
+ return;
+ }
+
+ mpic = mpic_alloc(np, r.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 0, 256, " OpenPIC ");
+ BUG_ON(mpic == NULL);
+
+ /* Return the mpic node */
+ of_node_put(np);
+
+ mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init sbc8548_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("sbc8548_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for_each_node_by_type(np, "pci") {
+ if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+ of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == 0x8000)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+ }
+ }
+
+ ppc_md.pci_exclude_device = sbc8548_exclude_device;
+#endif
+}
+
+static void sbc8548_show_cpuinfo(struct seq_file *m)
+{
+ uint pvid, svid, phid1;
+ uint memsize = total_memory;
+
+ pvid = mfspr(SPRN_PVR);
+ svid = mfspr(SPRN_SVR);
+
+ seq_printf(m, "Vendor\t\t: Wind River\n");
+ seq_printf(m, "Machine\t\t: SBC8548\n");
+ seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+ /* Display cpu Pll setting */
+ phid1 = mfspr(SPRN_HID1);
+ seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+
+ /* Display the amount of memory */
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+ { .name = "soc", },
+ { .type = "soc", },
+ {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+ if (!machine_is(sbc8548))
+ return 0;
+
+ of_platform_bus_probe(NULL, of_bus_ids, NULL);
+ return 0;
+}
+device_initcall(declare_of_platform_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init sbc8548_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "SBC8548");
+}
+
+define_machine(sbc8548) {
+ .name = "SBC8548",
+ .probe = sbc8548_probe,
+ .setup_arch = sbc8548_setup_arch,
+ .init_IRQ = sbc8548_pic_init,
+ .show_cpuinfo = sbc8548_show_cpuinfo,
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* [PATCH 2/5] sbc8548: Add device tree source for Wind River SBC8548 board
From: Paul Gortmaker @ 2008-01-09 5:18 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Gortmaker
In-Reply-To: <93a0b006474cd6884392682c82b232fc2aea7794.1199854466.git.paul.gortmaker@windriver.com>
This adds the device tree source for the Wind River SBC8548 board. The
biggest difference between this and the MPC8548CDS reference platform
is the absence of the CDS's Arcadia peripherals and physical access to PCI#2.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/boot/dts/sbc8548.dts | 242 +++++++++++++++++++++++++++++++++++++
1 files changed, 242 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
new file mode 100644
index 0000000..e63ed20
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -0,0 +1,242 @@
+/*
+ * SBC8548 Device Tree Source
+ *
+ * Copyright 2007 Wind River Systems Inc.
+ *
+ * Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+
+/ {
+ model = "SBC8548";
+ compatible = "SBC8548";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ /* pci1 doesn't have a corresponding physical connector */
+ pci2 = &pci2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8548@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>; // 32 bytes
+ i-cache-line-size = <20>; // 32 bytes
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>; // From uboot
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 10000000>;
+ };
+
+ soc8548@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <00000000 e0000000 00100000>;
+ reg = <e0000000 00001000>; // CCSRBAR
+ bus-frequency = <0>;
+
+ memory-controller@2000 {
+ compatible = "fsl,8548-memory-controller";
+ reg = <2000 1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <12 2>;
+ };
+
+ l2-cache-controller@20000 {
+ compatible = "fsl,8548-l2-cache-controller";
+ reg = <20000 1000>;
+ cache-line-size = <20>; // 32 bytes
+ cache-size = <80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <10 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <2b 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <2b 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <24520 20>;
+
+ phy0: ethernet-phy@19 {
+ interrupt-parent = <&mpic>;
+ interrupts = <6 1>;
+ reg = <19>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy@1a {
+ interrupt-parent = <&mpic>;
+ interrupts = <7 1>;
+ reg = <1a>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet0: ethernet@24000 {
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <1d 2 1e 2 22 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy0>;
+ };
+
+ enet1: ethernet@25000 {
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <23 2 24 2 28 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
+ interrupts = <2a 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
+ interrupts = <2a 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities reg
+ compatible = "fsl,mpc8548-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
+
+ pci0: pci@e0008000 {
+ cell-index = <0>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x01 (PCI-X slot) */
+ 00800 0 0 1 &mpic 0 1
+ 00800 0 0 2 &mpic 1 1
+ 00800 0 0 3 &mpic 2 1
+ 00800 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00800000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e0008000 1000>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
+
+ pci2: pcie@e000a000 {
+ cell-index = <2>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x0 (PEX) */
+ 00000 0 0 1 &mpic 0 1
+ 00000 0 0 2 &mpic 1 1
+ 00000 0 0 3 &mpic 2 1
+ 00000 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <1a 2>;
+ bus-range = <0 ff>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 08000000>;
+ clock-frequency = <1fca055>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <e000a000 1000>;
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <02000000 0 a0000000
+ 02000000 0 a0000000
+ 0 20000000
+
+ 01000000 0 00000000
+ 01000000 0 00000000
+ 0 08000000>;
+ };
+ };
+};
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* [PATCH 3/5] sbc8548: Add default .config file for Wind River SBC8548
From: Paul Gortmaker @ 2008-01-09 5:18 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Gortmaker
In-Reply-To: <93a0b006474cd6884392682c82b232fc2aea7794.1199854466.git.paul.gortmaker@windriver.com>
This is a suitable .config file for building the WRS SBC8548 kernel
to be used for NFS root via one of the TSEC interfaces and with
serial console via the soc/16550 compatible UART.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/configs/sbc8548_defconfig | 740 ++++++++++++++++++++++++++++++++
1 files changed, 740 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/sbc8548_defconfig b/arch/powerpc/configs/sbc8548_defconfig
new file mode 100644
index 0000000..cb0448a
--- /dev/null
+++ b/arch/powerpc/configs/sbc8548_defconfig
@@ -0,0 +1,740 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc4
+# Thu Dec 20 18:10:58 2007
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+CONFIG_PPC_85xx=y
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_85xx=y
+CONFIG_E500=y
+CONFIG_BOOKE=y
+CONFIG_FSL_BOOKE=y
+# CONFIG_PHYS_64BIT is not set
+CONFIG_SPE=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Platform support
+#
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_MPC8540_ADS is not set
+# CONFIG_MPC8560_ADS is not set
+# CONFIG_MPC85xx_CDS is not set
+# CONFIG_MPC85xx_MDS is not set
+# CONFIG_MPC85xx_DS is not set
+CONFIG_SBC8548=y
+# CONFIG_SBC8560 is not set
+CONFIG_MPC8540=y
+CONFIG_MPC85xx=y
+CONFIG_MPIC=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+CONFIG_BINFMT_MISC=y
+CONFIG_MATH_EMULATION=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_HIBERNATION_UP_POSSIBLE=y
+# CONFIG_SECCOMP is not set
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_DEVICE_TREE=""
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_FSL_PCI=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_PCIEPORTBUS is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+# CONFIG_PCI_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_IP1000 is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_GIANFAR=y
+CONFIG_GFAR_NAPI=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+# CONFIG_UCC_SLOW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* [PATCH 4/5] sbc8548: Convert device tree to be dts-v1 compatible
From: Paul Gortmaker @ 2008-01-09 5:18 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Gortmaker
In-Reply-To: <93a0b006474cd6884392682c82b232fc2aea7794.1199854466.git.paul.gortmaker@windriver.com>
This converts the dts to be dts-v1 compatible. Tested with the latest
git pull of dtc (Dec 21/07).
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/boot/dts/sbc8548.dts | 122 +++++++++++++++++++------------------
1 files changed, 62 insertions(+), 60 deletions(-)
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index e63ed20..14be38a 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -12,6 +12,8 @@
*/
+/dts-v1/;
+
/ {
model = "SBC8548";
compatible = "SBC8548";
@@ -35,10 +37,10 @@
PowerPC,8548@0 {
device_type = "cpu";
reg = <0>;
- d-cache-line-size = <20>; // 32 bytes
- i-cache-line-size = <20>; // 32 bytes
- d-cache-size = <8000>; // L1, 32K
- i-cache-size = <8000>; // L1, 32K
+ d-cache-line-size = <0x20>; // 32 bytes
+ i-cache-line-size = <0x20>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
timebase-frequency = <0>; // From uboot
bus-frequency = <0>;
clock-frequency = <0>;
@@ -47,31 +49,31 @@
memory {
device_type = "memory";
- reg = <00000000 10000000>;
+ reg = <0x00000000 0x10000000>;
};
soc8548@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
- ranges = <00000000 e0000000 00100000>;
- reg = <e0000000 00001000>; // CCSRBAR
+ ranges = <0x00000000 0xe0000000 0x00100000>;
+ reg = <0xe0000000 0x00001000>; // CCSRBAR
bus-frequency = <0>;
memory-controller@2000 {
compatible = "fsl,8548-memory-controller";
- reg = <2000 1000>;
+ reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
- interrupts = <12 2>;
+ interrupts = <0x12 0x2>;
};
l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
- reg = <20000 1000>;
- cache-line-size = <20>; // 32 bytes
- cache-size = <80000>; // L2, 512K
+ reg = <0x20000 0x1000>;
+ cache-line-size = <0x20>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
interrupt-parent = <&mpic>;
- interrupts = <10 2>;
+ interrupts = <0x10 0x2>;
};
i2c@3000 {
@@ -79,8 +81,8 @@
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- reg = <3000 100>;
- interrupts = <2b 2>;
+ reg = <0x3000 0x100>;
+ interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@@ -90,8 +92,8 @@
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
- reg = <3100 100>;
- interrupts = <2b 2>;
+ reg = <0x3100 0x100>;
+ interrupts = <0x2b 0x2>;
interrupt-parent = <&mpic>;
dfsrr;
};
@@ -100,18 +102,18 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
- reg = <24520 20>;
+ reg = <0x24520 0x20>;
phy0: ethernet-phy@19 {
interrupt-parent = <&mpic>;
- interrupts = <6 1>;
- reg = <19>;
+ interrupts = <0x6 0x1>;
+ reg = <0x19>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@1a {
interrupt-parent = <&mpic>;
- interrupts = <7 1>;
- reg = <1a>;
+ interrupts = <0x7 0x1>;
+ reg = <0x1a>;
device_type = "ethernet-phy";
};
};
@@ -121,9 +123,9 @@
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <24000 1000>;
+ reg = <0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <1d 2 1e 2 22 2>;
+ interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
};
@@ -133,9 +135,9 @@
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
- reg = <25000 1000>;
+ reg = <0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <23 2 24 2 28 2>;
+ interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
};
@@ -144,9 +146,9 @@
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
- reg = <4500 100>; // reg base, size
+ reg = <0x4500 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
};
@@ -154,15 +156,15 @@
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
- reg = <4600 100>; // reg base, size
+ reg = <0x4600 0x100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot?
- interrupts = <2a 2>;
+ interrupts = <0x2a 0x2>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 { //global utilities reg
compatible = "fsl,mpc8548-guts";
- reg = <e0000 1000>;
+ reg = <0xe0000 0x1000>;
fsl,has-rstcr;
};
@@ -171,7 +173,7 @@
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
- reg = <40000 40000>;
+ reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
big-endian;
@@ -180,63 +182,63 @@
pci0: pci@e0008000 {
cell-index = <0>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x01 (PCI-X slot) */
- 00800 0 0 1 &mpic 0 1
- 00800 0 0 2 &mpic 1 1
- 00800 0 0 3 &mpic 2 1
- 00800 0 0 4 &mpic 3 1>;
+ 0x0800 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0800 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <18 2>;
+ interrupts = <0x18 0x2>;
bus-range = <0 0>;
- ranges = <02000000 0 80000000 80000000 0 10000000
- 01000000 0 00000000 e2000000 0 00800000>;
- clock-frequency = <3f940aa>;
+ ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+ 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
+ clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e0008000 1000>;
+ reg = <0xe0008000 0x1000>;
compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci";
};
pci2: pcie@e000a000 {
cell-index = <2>;
- interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
- 00000 0 0 1 &mpic 0 1
- 00000 0 0 2 &mpic 1 1
- 00000 0 0 3 &mpic 2 1
- 00000 0 0 4 &mpic 3 1>;
+ 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
interrupt-parent = <&mpic>;
- interrupts = <1a 2>;
- bus-range = <0 ff>;
- ranges = <02000000 0 a0000000 a0000000 0 20000000
- 01000000 0 00000000 e3000000 0 08000000>;
- clock-frequency = <1fca055>;
+ interrupts = <0x1a 0x2>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x08000000>;
+ clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
- reg = <e000a000 1000>;
+ reg = <0xe000a000 0x1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
pcie@0 {
- reg = <0 0 0 0 0>;
+ reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- ranges = <02000000 0 a0000000
- 02000000 0 a0000000
- 0 20000000
+ ranges = <0x02000000 0x0 0xa0000000
+ 0x02000000 0x0 0xa0000000
+ 0x0 0x20000000
- 01000000 0 00000000
- 01000000 0 00000000
- 0 08000000>;
+ 0x01000000 0x0 0x00000000
+ 0x01000000 0x0 0x00000000
+ 0x0 0x08000000>;
};
};
};
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* [PATCH 5/5] sbc85xx: remove PCI exclude device for sbc8548/sbc8560
From: Paul Gortmaker @ 2008-01-09 5:18 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Gortmaker
In-Reply-To: <93a0b006474cd6884392682c82b232fc2aea7794.1199854466.git.paul.gortmaker@windriver.com>
The PCI exclude device for the sbc85xx boards was only filtering out
the PHB and nothing else. This functionality is no longer required
at a board specific level -- it is handled as a more global quirk now.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/platforms/85xx/sbc8548.c | 13 -------------
arch/powerpc/platforms/85xx/sbc8560.c | 13 -------------
2 files changed, 0 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/sbc8548.c b/arch/powerpc/platforms/85xx/sbc8548.c
index f3ab271..de27b57 100644
--- a/arch/powerpc/platforms/85xx/sbc8548.c
+++ b/arch/powerpc/platforms/85xx/sbc8548.c
@@ -49,17 +49,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-#ifdef CONFIG_PCI
-static int sbc8548_exclude_device(struct pci_controller *hose,
- u_char bus, u_char devfn)
-{
- if (bus == 0 && PCI_SLOT(devfn) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
- else
- return PCIBIOS_SUCCESSFUL;
-}
-#endif
-
static void __init sbc8548_pic_init(void)
{
struct mpic *mpic;
@@ -114,8 +103,6 @@ static void __init sbc8548_setup_arch(void)
fsl_add_bridge(np, 0);
}
}
-
- ppc_md.pci_exclude_device = sbc8548_exclude_device;
#endif
}
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index 6aef38b..2030e87 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -37,17 +37,6 @@
#include <sysdev/cpm2_pic.h>
#endif
-#ifdef CONFIG_PCI
-static int sbc8560_exclude_device(struct pci_controller *hose,
- u_char bus, u_char devfn)
-{
- if (bus == 0 && PCI_SLOT(devfn) == 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
- else
- return PCIBIOS_SUCCESSFUL;
-}
-#endif /* CONFIG_PCI */
-
#ifdef CONFIG_CPM2
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
@@ -199,8 +188,6 @@ static void __init sbc8560_setup_arch(void)
#ifdef CONFIG_PCI
for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
fsl_add_bridge(np, 1);
-
- ppc_md.pci_exclude_device = sbc8560_exclude_device;
#endif
}
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* Re: [PATCH 2/3 v2] Add initial iomega StorCenter board port.
From: Stephen Rothwell @ 2008-01-09 5:29 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1JCMbN-0002mN-MD@jdl.com>
[-- Attachment #1: Type: text/plain, Size: 1112 bytes --]
Hi Jon,
On Tue, 08 Jan 2008 16:07:17 -0600 Jon Loeliger <jdl@jdl.com> wrote:
>
> +static void __init storcenter_init_IRQ(void)
> +{
> + struct mpic *mpic;
> + struct device_node *dnp;
> + const void *prop;
> + int size;
> + phys_addr_t paddr;
> +
> + dnp = of_find_node_by_type(NULL, "open-pic");
> + if (dnp == NULL)
> + return;
> +
> + prop = of_get_property(dnp, "reg", &size);
> + paddr = (phys_addr_t)of_translate_address(dnp, prop);
> + mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET,
> + 4, 32, " EPIC ");
> + BUG_ON(mpic == NULL);
> + mpic_assign_isu(mpic, 0, paddr + 0x10200);
> + mpic_assign_isu(mpic, 1, paddr + 0x10220);
> + mpic_assign_isu(mpic, 2, paddr + 0x10240);
> + mpic_assign_isu(mpic, 3, paddr + 0x10260);
> + mpic_assign_isu(mpic, 4, paddr + 0x10280);
> + mpic_assign_isu(mpic, 5, paddr + 0x11120);
> + mpic_assign_isu(mpic, 6, paddr + 0x11140);
> +
> + mpic_init(mpic);
> +}
The above needs a of_node_put(dnp) somewhere.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [PATCH 0/3] Powerpc support for SBC834x board
From: Paul Gortmaker @ 2008-01-09 5:49 UTC (permalink / raw)
To: linuxppc-dev
The following three patches add support for the Wind River SBC834x board
into arch/powerpc. The support is primarily based on the existing Fsl
MPC834x_MDS board support.
1) Add support for Wind River SBC834x boards
b/arch/powerpc/platforms/83xx/Kconfig | 9 ++
b/arch/powerpc/platforms/83xx/Makefile | 1
b/arch/powerpc/platforms/83xx/sbc834x.c | 117 +++++++++++++++++++++++++++++++-
3 files changed, 125 insertions(+), 2 deletions(-)
2) Add device tree source (v1) for Wind River SBC834x board
b/arch/powerpc/boot/dts/sbc8349.dts | 248 +++++++++++++++++++++++++++++++++++-
1 file changed, 247 insertions(+), 1 deletion(-)
3) Add default config file for Wind River SBC8349 board
b/arch/powerpc/configs/sbc834x_defconfig | 801 ++++++++++++++++++++++++++++++-
1 file changed, 800 insertions(+), 1 deletion(-)
I've tested this with u-boot 1.3.1 + the three recent minor sbc834x u-boot
patches I'd put out plus the latest dtc from git, and it all seems happy.
Paul.
^ permalink raw reply
* [PATCH 1/3] sbc834x: Add support for Wind River SBC834x boards
From: Paul Gortmaker @ 2008-01-09 5:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Gortmaker
In-Reply-To: <11998577723665-git-send-email-paul.gortmaker@windriver.com>
This adds the basic support for the Wind River SBC834x boards. The
SBC8349 is more common, although it should work on the SBC8347 board
as well. Support is heavily based on the existing MPC834x_MDS code.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/platforms/83xx/Kconfig | 9 ++-
arch/powerpc/platforms/83xx/Makefile | 1 +
arch/powerpc/platforms/83xx/sbc834x.c | 116 +++++++++++++++++++++++++++++++++
3 files changed, 125 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 2430ac8..782bff0 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -55,6 +55,13 @@ config MPC837x_MDS
select DEFAULT_UIMAGE
help
This option enables support for the MPC837x MDS Processor Board.
+
+config SBC834x
+ bool "Wind River SBC834x"
+ select DEFAULT_UIMAGE
+ help
+ This option enables support for the Wind River SBC834x board.
+
endchoice
config PPC_MPC831x
@@ -73,7 +80,7 @@ config MPC834x
bool
select PPC_UDBG_16550
select PPC_INDIRECT_PCI
- default y if MPC834x_MDS || MPC834x_ITX
+ default y if MPC834x_MDS || MPC834x_ITX || SBC834x
config PPC_MPC836x
bool
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index df46629..3a35242 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
obj-$(CONFIG_MPC832x_MDS) += mpc832x_mds.o
obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o
+obj-$(CONFIG_SBC834x) += sbc834x.o
diff --git a/arch/powerpc/platforms/83xx/sbc834x.c b/arch/powerpc/platforms/83xx/sbc834x.c
new file mode 100644
index 0000000..b448123
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/sbc834x.c
@@ -0,0 +1,116 @@
+/*
+ * arch/powerpc/platforms/83xx/sbc834x.c
+ *
+ * Wind River SBC834x board specific routines
+ *
+ * By Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * Based largely on the mpc834x_mds.c support by Kumar Gala.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+
+#include "mpc83xx.h"
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init sbc834x_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("sbc834x_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
+ mpc83xx_add_bridge(np);
+#endif
+
+}
+
+static void __init sbc834x_init_IRQ(void)
+{
+ struct device_node *np;
+
+ np = of_find_node_by_type(NULL, "ipic");
+ if (!np)
+ return;
+
+ ipic_init(np, 0);
+
+ /* Initialize the default interrupt mapping priorities,
+ * in case the boot rom changed something on us.
+ */
+ ipic_set_default_priority();
+}
+
+static struct of_device_id sbc834x_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ {},
+};
+
+static int __init sbc834x_declare_of_platform_devices(void)
+{
+ if (!machine_is(sbc834x))
+ return 0;
+
+ of_platform_bus_probe(NULL, sbc834x_ids, NULL);
+ return 0;
+}
+device_initcall(sbc834x_declare_of_platform_devices);
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init sbc834x_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "SBC834x");
+}
+
+define_machine(sbc834x) {
+ .name = "SBC834x",
+ .probe = sbc834x_probe,
+ .setup_arch = sbc834x_setup_arch,
+ .init_IRQ = sbc834x_init_IRQ,
+ .get_irq = ipic_get_irq,
+ .restart = mpc83xx_restart,
+ .time_init = mpc83xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* [PATCH 2/3] sbc834x: Add device tree source for Wind River SBC834x board.
From: Paul Gortmaker @ 2008-01-09 5:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Gortmaker
In-Reply-To: <ac667c5b2e8acb0f92d31b8e3b590432bb939df9.1199850992.git.paul.gortmaker@windriver.com>
This adds the device tree source for the Wind River SBC834x board.
It is based on the MPC834x_MDS DTS, with the biggest difference being
the lack of BCSR and the PCI2 that the MDS gets via the PIB. That,
and this file is also dts-v1 format.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/boot/dts/sbc8349.dts | 247 +++++++++++++++++++++++++++++++++++++
1 files changed, 247 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
new file mode 100644
index 0000000..dd5a0f2
--- /dev/null
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -0,0 +1,247 @@
+/*
+ * SBC8349E Device Tree Source
+ *
+ * Copyright 2007 Wind River Inc.
+ *
+ * Paul Gortmaker (see MAINTAINERS for contact information)
+ *
+ * -based largely on the Freescale MPC834x_MDS dts.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "SBC8349E";
+ compatible = "SBC834xE";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8349@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <0x20>; // 32 bytes
+ i-cache-line-size = <0x20>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>; // from bootloader
+ bus-frequency = <0>; // from bootloader
+ clock-frequency = <0>; // from bootloader
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; // 256MB at 0
+ };
+
+ soc@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0x0 0xe0000000 0x00100000>;
+ reg = <0xe0000000 0x00000200>;
+ bus-frequency = <0>;
+
+ wdt@200 {
+ device_type = "watchdog";
+ compatible = "mpc83xx_wdt";
+ reg = <0x200 0x100>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <0xe 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <0xf 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ spi@7000 {
+ device_type = "spi";
+ compatible = "fsl_spi";
+ reg = <0x7000 0x1000>;
+ interrupts = <0x10 0x8>;
+ interrupt-parent = <&ipic>;
+ mode = "cpu";
+ };
+
+ /* phy type (ULPI or SERIAL) are only types supported for MPH */
+ /* port = 0 or 1 */
+ usb@22000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-mph";
+ reg = <0x22000 0x1000>;
+ #address-cells = <0x1>;
+ #size-cells = <0>;
+ interrupt-parent = <&ipic>;
+ interrupts = <0x27 0x8>;
+ phy_type = "ulpi";
+ port1;
+ };
+ /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
+ usb@23000 {
+ device_type = "usb";
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&ipic>;
+ interrupts = <0x26 0x8>;
+ dr_mode = "otg";
+ phy_type = "ulpi";
+ };
+
+ mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+
+ phy0: ethernet-phy@19 {
+ interrupt-parent = <&ipic>;
+ interrupts = <0x14 0x8>;
+ reg = <0x19>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy@1a {
+ interrupt-parent = <&ipic>;
+ interrupts = <0x15 0x8>;
+ reg = <0x1a>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet0: ethernet@24000 {
+ cell-index = <0>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
+ interrupt-parent = <&ipic>;
+ phy-handle = <&phy0>;
+ linux,network-index = <0>;
+ };
+
+ enet1: ethernet@25000 {
+ cell-index = <1>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
+ interrupt-parent = <&ipic>;
+ phy-handle = <&phy1>;
+ linux,network-index = <1>;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <0x9 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <0xa 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ /* May need to remove if on a part without crypto engine */
+ crypto@30000 {
+ device_type = "crypto";
+ model = "SEC2";
+ compatible = "talitos";
+ reg = <0x30000 0x10000>;
+ interrupts = <0xb 0x8>;
+ interrupt-parent = <&ipic>;
+ num-channels = <4>;
+ channel-fifo-len = <0x18>;
+ exec-units-mask = <0x0000007e>;
+ /* desc mask is for rev2.0,
+ * we need runtime fixup for >2.0 */
+ descriptor-types-mask = <0x01010ebf>;
+ };
+
+ /* IPIC
+ * interrupts cell = <intr #, sense>
+ * sense values match linux IORESOURCE_IRQ_* defines:
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ ipic: pic@700 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x700 0x100>;
+ device_type = "ipic";
+ };
+ };
+
+ pci0: pci@e0008500 {
+ cell-index = <1>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 */
+ 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8
+ 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8
+ 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8
+ 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8>;
+
+ interrupt-parent = <&ipic>;
+ interrupts = <0x42 0x8>;
+ bus-range = <0 0>;
+ ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+ 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+ 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
+ clock-frequency = <66666666>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xe0008500 0x100>;
+ compatible = "fsl,mpc8349-pci";
+ device_type = "pci";
+ };
+};
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* [PATCH 3/3] sbc834x: Add default config file for Wind River SBC8349 board
From: Paul Gortmaker @ 2008-01-09 5:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Gortmaker
In-Reply-To: <ac667c5b2e8acb0f92d31b8e3b590432bb939df9.1199850992.git.paul.gortmaker@windriver.com>
Default config file for SBC8349 board, suitable for use as with NFS as
a root file system and gianfar as NFS root device.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
arch/powerpc/configs/sbc834x_defconfig | 800 ++++++++++++++++++++++++++++++++
1 files changed, 800 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/sbc834x_defconfig b/arch/powerpc/configs/sbc834x_defconfig
new file mode 100644
index 0000000..ab48ccc
--- /dev/null
+++ b/arch/powerpc/configs/sbc834x_defconfig
@@ -0,0 +1,800 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc6
+# Tue Jan 8 19:48:27 2008
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_83xx=y
+CONFIG_PPC_FPU=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+# CONFIG_EPOLL is not set
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+
+#
+# Platform support
+#
+# CONFIG_PPC_MULTIPLATFORM is not set
+# CONFIG_PPC_82xx is not set
+CONFIG_PPC_83xx=y
+# CONFIG_PPC_86xx is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_MPC8313_RDB is not set
+# CONFIG_MPC832x_MDS is not set
+# CONFIG_MPC832x_RDB is not set
+# CONFIG_MPC834x_MDS is not set
+# CONFIG_MPC834x_ITX is not set
+# CONFIG_MPC836x_MDS is not set
+# CONFIG_MPC837x_MDS is not set
+CONFIG_SBC834x=y
+CONFIG_MPC834x=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_CPM2 is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_TICK_ONESHOT is not set
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_HIBERNATION_UP_POSSIBLE=y
+CONFIG_SECCOMP=y
+CONFIG_WANT_DEVICE_TREE=y
+CONFIG_DEVICE_TREE=""
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+CONFIG_OF_DEVICE=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_GIANFAR=y
+# CONFIG_GFAR_NAPI is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_OF_PLATFORM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_83xx_WDT=y
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+# CONFIG_UCC_SLOW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+# CONFIG_INSTRUMENTATION is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_PPC_CLOCK is not set
--
1.5.0.rc1.gf4b6c
^ permalink raw reply related
* Re: [PATCH 7/7] Add MPC512x PSC serial driver
From: Stephen Rothwell @ 2008-01-09 6:06 UTC (permalink / raw)
To: John Rigby; +Cc: linuxppc-dev
In-Reply-To: <20080109141649.04a1783c.sfr@canb.auug.org.au>
[-- Attachment #1: Type: text/plain, Size: 517 bytes --]
On Wed, 9 Jan 2008 14:16:49 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> On Tue, 8 Jan 2008 09:01:33 -0700 John Rigby <jrigby@freescale.com> wrote:
> >
> > +++ b/drivers/serial/mpc512x_uart.c
> >
> > +#include <asm/of_platform.h>
>
> Purely to avoid suggestions of favouritism, I will not the above. :-)
^^^
"note", of course :-(
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* Please pull linux-2.6-virtex.git
From: Grant Likely @ 2008-01-09 6:07 UTC (permalink / raw)
To: linuxppc-dev, Josh Boyer
Josh, here are some Xilinx Virtex changes for 2.6.25:
git://git.secretlab.ca/git/linux-2.6-virtex.git virtex-for-2.6.25
Cheers,
g.
---
The following changes since commit 4f43143f9fbbb679c38d2ff99e44d3aaa00d0fe1:
Paul Mackerras (1):
Merge branch 'for-2.6.25' of git://git.kernel.org/.../olof/pasemi
are available in the git repository at:
git://git.secretlab.ca/git/linux-2.6-virtex.git virtex-for-2.6.25
Grant Likely (1):
[POWERPC] Xilinx Uartlite: Make console output actually work.
Stephen Neuendorffer (6):
[POWERPC] Xilinx: update compatible list for interrupt controller
[POWERPC] Xilinx: Update compatible to use values generated by
BSP generator.
[POWERPC] Xilinx: Add correct compatible list for device tree
bus bindings.
[POWERPC] Xilinx: Update booting-without-of.
[POWERPC] Xilinx: updated device tree compatibility to match
uboot bsp generator.
[POWERPC] Xilinx uartlite: Section type fixups
Documentation/powerpc/booting-without-of.txt | 56 +++++----
arch/powerpc/boot/serial.c | 3 +-
arch/powerpc/platforms/40x/virtex.c | 14 ++-
arch/powerpc/sysdev/xilinx_intc.c | 8 +-
drivers/block/xsysace.c | 4 +-
drivers/serial/uartlite.c | 164 ++++++++++++++++---------
drivers/video/xilinxfb.c | 2 +-
7 files changed, 163 insertions(+), 88 deletions(-)
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH 3/7] sbc8560: add support for Wind River SBC8560 in arch/powerpc
From: Stephen Rothwell @ 2008-01-09 6:23 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev
In-Reply-To: <47845009.8070106@windriver.com>
[-- Attachment #1: Type: text/plain, Size: 546 bytes --]
On Tue, 08 Jan 2008 23:39:37 -0500 Paul Gortmaker <paul.gortmaker@windriver.com> wrote:
>
> No problem. I think you will find all these issues are applicable to
> the mpc8560mds support that I based things off too. I'd rather do
> a single patch for both boards to deal with these, rather than respin
> the sbc8560 patches again and leave the mpc8560mds behind.
> Assuming everyone else is OK with this approach.
Fine by me.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* Re: [PATCH V2] [POWERPC] Add common clock setting routine mpc52xx_psc_set_clkdiv()
From: Stephen Rothwell @ 2008-01-09 6:37 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev
In-Reply-To: <20080109050950.14630.17832.stgit@trillian.secretlab.ca>
[-- Attachment #1: Type: text/plain, Size: 1780 bytes --]
Hi Grant,
Just a couple of trivial things.
On Tue, 08 Jan 2008 22:09:50 -0700 Grant Likely <grant.likely@secretlab.ca> wrote:
>
> +int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
> + switch (psc_id) {
> + case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break;
> + case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break;
> + case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break;
> + case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break;
> + default:
> + return -ENODEV;
> + }
We line up case labels with the switch statement itself.
> +int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
> + switch (psc_id) {
> + case 1: reg = &cdm->mclken_div_psc1; mask = 0x20; break;
> + case 2: reg = &cdm->mclken_div_psc2; mask = 0x40; break;
> + case 3: reg = &cdm->mclken_div_psc3; mask = 0x80; break;
> + case 6: reg = &cdm->mclken_div_psc6; mask = 0x10; break;
> + default:
> + return -ENODEV;
> + }
Here as well.
> +++ b/include/asm-powerpc/mpc52xx.h
> -extern void mpc5200_setup_xlb_arbiter(void);
> -extern void mpc52xx_declare_of_platform_devices(void);
> +extern void __init mpc5200_setup_xlb_arbiter(void);
> +extern void __init mpc52xx_declare_of_platform_devices(void);
> +extern void __init mpc52xx_map_common_devices(void);
We don't mark things __init in header files. It is unnecessary and can
get out of sync - which causes unexpected results.
> +/* mpc52xx_pci.c */
> #ifdef CONFIG_PCI
> extern int __init mpc52xx_add_bridge(struct device_node *node);
> extern void __init mpc52xx_setup_pci(void);
I see where yours above came from ...
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* [patch 2/4 v2] PS3: Add logical performance monitor repository routines
From: Geoff Levand @ 2008-01-09 6:35 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Takashi Yamamoto
In-Reply-To: <477EF59C.2070809@am.sony.com>
From: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Add repository routines for the PS3 Logical Performance Monitor (lpm).
Signed-off-by: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
v2: correct Yamamoto-san's mail addr.
arch/powerpc/platforms/ps3/platform.h | 7 ++++
arch/powerpc/platforms/ps3/repository.c | 48 ++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+), 1 deletion(-)
--- a/arch/powerpc/platforms/ps3/platform.h
+++ b/arch/powerpc/platforms/ps3/platform.h
@@ -189,7 +189,7 @@ int ps3_repository_read_stor_dev_region(
/* repository pu and memory info */
int ps3_repository_read_num_pu(unsigned int *num_pu);
-int ps3_repository_read_ppe_id(unsigned int *pu_index, unsigned int *ppe_id);
+int ps3_repository_read_pu_id(unsigned int pu_index, u64 *pu_id);
int ps3_repository_read_rm_base(unsigned int ppe_id, u64 *rm_base);
int ps3_repository_read_rm_size(unsigned int ppe_id, u64 *rm_size);
int ps3_repository_read_region_total(u64 *region_total);
@@ -203,6 +203,11 @@ int ps3_repository_read_be_node_id(unsig
int ps3_repository_read_tb_freq(u64 node_id, u64 *tb_freq);
int ps3_repository_read_be_tb_freq(unsigned int be_index, u64 *tb_freq);
+/* repository performance monitor info */
+
+int ps3_repository_read_lpm_privileges(unsigned int be_index, u64 *lpar,
+ u64 *rights);
+
/* repository 'Other OS' area */
int ps3_repository_read_boot_dat_addr(u64 *lpar_addr);
--- a/arch/powerpc/platforms/ps3/repository.c
+++ b/arch/powerpc/platforms/ps3/repository.c
@@ -902,6 +902,54 @@ int ps3_repository_read_be_tb_freq(unsig
: ps3_repository_read_tb_freq(node_id, tb_freq);
}
+int ps3_repository_read_lpm_privileges(unsigned int be_index, u64 *lpar,
+ u64 *rights)
+{
+ int result;
+ u64 node_id;
+
+ *lpar = 0;
+ *rights = 0;
+ result = ps3_repository_read_be_node_id(be_index, &node_id);
+ return result ? result
+ : read_node(PS3_LPAR_ID_PME,
+ make_first_field("be", 0),
+ node_id,
+ make_field("lpm", 0),
+ make_field("priv", 0),
+ lpar, rights);
+}
+
+int ps3_repository_read_num_pu(unsigned int *num_pu)
+{
+ int result;
+ u64 v1;
+
+ v1 = 0;
+ result = read_node(PS3_LPAR_ID_CURRENT,
+ make_first_field("bi", 0),
+ make_field("pun", 0),
+ 0, 0,
+ &v1, NULL);
+ *num_pu = v1;
+ return result;
+}
+
+int ps3_repository_read_pu_id(unsigned int pu_index, u64 *pu_id)
+{
+ int result;
+ u64 v1;
+
+ v1 = 0;
+ result = read_node(PS3_LPAR_ID_CURRENT,
+ make_first_field("bi", 0),
+ make_field("pu", pu_index),
+ 0, 0,
+ &v1, NULL);
+ *pu_id = v1;
+ return result;
+}
+
#if defined(DEBUG)
int ps3_repository_dump_resource_info(const struct ps3_repository_device *repo)
^ permalink raw reply
* [patch 1/4] POWERPC: Add Cell SPRN bookmark register
From: Geoff Levand @ 2008-01-09 6:35 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <477EF59C.2070809@am.sony.com>
Add a definition for the Cell SPRN bookmark register
to asm-powerpc/regs.h
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
Needed for PS3's lpm driver.
include/asm-powerpc/reg.h | 1 +
1 file changed, 1 insertion(+)
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -553,6 +553,7 @@
#define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */
#define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */
#define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */
+#define SPRN_BKMK 1020 /* Cell Bookmark Register */
#define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */
^ permalink raw reply
* [patch 4/4 v2] PS3: Add logical performance monitor driver support
From: Geoff Levand @ 2008-01-09 6:35 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, Takashi Yamamoto
In-Reply-To: <477EF59C.2070809@am.sony.com>
From: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Add PS3 logical performance monitor (lpm) device driver.
The PS3's LV1 hypervisor provides a Logical Performance Monitor that
abstarcts the Cell processor's performance monitor features for use
by guest operating systems.
Signed-off-by: Takashi Yamamoto <TakashiA.Yamamoto@jp.sony.com>
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
v2: o Correct Yamamoto-san's mail addr.
o Text cleanups.
o Added more comments explaining lpm operation.
o Split SRPN_BKMK into separate patch.
o Use get_hard_smp_processor_id() in ps3_get_hw_thread_id().
o Split ps3_copy_trace_buffer() into ps3_lpm_copy_tb() and ps3_lpm_copy_tb_to_user().
o Replace mutex with atomic_t in ps3_lpm_open()/ps3_lpm_close().
o General cleanup of ps3_lpm_open()/ps3_lpm_close().
arch/powerpc/platforms/ps3/Kconfig | 13
drivers/ps3/Makefile | 1
drivers/ps3/ps3-lpm.c | 1242 +++++++++++++++++++++++++++++++++++++
include/asm-powerpc/ps3.h | 62 +
4 files changed, 1318 insertions(+)
create mode 100644 arch/powerpc/platforms/ps3/ps3-lpm.c
--- a/arch/powerpc/platforms/ps3/Kconfig
+++ b/arch/powerpc/platforms/ps3/Kconfig
@@ -138,4 +138,17 @@ config PS3_FLASH
be disabled on the kernel command line using "ps3flash=off", to
not allocate this fixed buffer.
+config PS3_LPM
+ tristate "PS3 Logical Performance Monitor support"
+ depends on PPC_PS3
+ help
+ Include support for the PS3 Logical Performance Monitor.
+
+ This support is required to use the logical performance monitor
+ of the PS3's LV1 hypervisor.
+
+ If you intend to use the advanced performance monitoring and
+ profiling support of the Cell processor with programs like
+ oprofile and perfmon2, then say Y or M, otherwise say N.
+
endmenu
--- a/drivers/ps3/Makefile
+++ b/drivers/ps3/Makefile
@@ -4,3 +4,4 @@ ps3av_mod-objs += ps3av.o ps3av_cmd.o
obj-$(CONFIG_PPC_PS3) += sys-manager-core.o
obj-$(CONFIG_PS3_SYS_MANAGER) += ps3-sys-manager.o
obj-$(CONFIG_PS3_STORAGE) += ps3stor_lib.o
+obj-$(CONFIG_PS3_LPM) += ps3-lpm.o
--- /dev/null
+++ b/drivers/ps3/ps3-lpm.c
@@ -0,0 +1,1242 @@
+/*
+ * PS3 Logical Performance Monitor.
+ *
+ * Copyright (C) 2007 Sony Computer Entertainment Inc.
+ * Copyright 2007 Sony Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/uaccess.h>
+#include <asm/ps3.h>
+#include <asm/lv1call.h>
+#include <asm/cell-pmu.h>
+
+
+/* BOOKMARK tag macros */
+#define PS3_PM_BOOKMARK_START 0x8000000000000000ULL
+#define PS3_PM_BOOKMARK_STOP 0x4000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_KERNEL 0x1000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_USER 0x3000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_MASK_HI 0xF000000000000000ULL
+#define PS3_PM_BOOKMARK_TAG_MASK_LO 0x0F00000000000000ULL
+
+/* CBE PM CONTROL register macros */
+#define PS3_PM_CONTROL_PPU_TH0_BOOKMARK 0x00001000
+#define PS3_PM_CONTROL_PPU_TH1_BOOKMARK 0x00000800
+#define PS3_PM_CONTROL_PPU_COUNT_MODE_MASK 0x000C0000
+#define PS3_PM_CONTROL_PPU_COUNT_MODE_PROBLEM 0x00080000
+#define PS3_WRITE_PM_MASK 0xFFFFFFFFFFFFFFFFULL
+
+/* CBE PM START STOP register macros */
+#define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START 0x02000000
+#define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START 0x01000000
+#define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP 0x00020000
+#define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP 0x00010000
+#define PS3_PM_START_STOP_START_MASK 0xFF000000
+#define PS3_PM_START_STOP_STOP_MASK 0x00FF0000
+
+/* CBE PM COUNTER register macres */
+#define PS3_PM_COUNTER_MASK_HI 0xFFFFFFFF00000000ULL
+#define PS3_PM_COUNTER_MASK_LO 0x00000000FFFFFFFFULL
+
+/* BASE SIGNAL GROUP NUMBER macros */
+#define PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER 0
+#define PM_ISLAND2_SIGNAL_GROUP_NUMBER1 6
+#define PM_ISLAND2_SIGNAL_GROUP_NUMBER2 7
+#define PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER 7
+#define PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER 15
+#define PM_SPU_TRIGGER_SIGNAL_GROUP_NUMBER 17
+#define PM_SPU_EVENT_SIGNAL_GROUP_NUMBER 18
+#define PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER 18
+#define PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER 24
+#define PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER 49
+#define PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER 52
+#define PM_SIG_GROUP_SPU 41
+#define PM_SIG_GROUP_SPU_TRIGGER 42
+#define PM_SIG_GROUP_SPU_EVENT 43
+#define PM_SIG_GROUP_MFC_MAX 60
+
+/**
+ * struct ps3_lpm_shadow_regs - Performance monitor shadow registers.
+ *
+ * @pm_control: Shadow of the processor's pm_control register.
+ * @pm_start_stop: Shadow of the processor's pm_start_stop register.
+ * @pm_interval: Shadow of the processor's pm_interval register.
+ * @group_control: Shadow of the processor's group_control register.
+ * @debug_bus_control: Shadow of the processor's debug_bus_control register.
+ *
+ * The logical performance monitor provides a write-only interface to
+ * these processor registers. These shadow variables cache the processor
+ * register values for reading.
+ *
+ * The initial value of the shadow registers at lpm creation is
+ * PS3_LPM_SHADOW_REG_INIT.
+ */
+
+struct ps3_lpm_shadow_regs {
+ u64 pm_control;
+ u64 pm_start_stop;
+ u64 pm_interval;
+ u64 group_control;
+ u64 debug_bus_control;
+};
+
+#define PS3_LPM_SHADOW_REG_INIT 0xFFFFFFFF00000000ULL
+
+/**
+ * struct ps3_lpm_priv - Private lpm device data.
+ *
+ * @open: An atomic variable indicating the lpm driver has been opened.
+ * @rights: The lpm rigths granted by the system policy module. A logical
+ * OR of enum ps3_lpm_rights.
+ * @pu_id: The lv1 id of the BE prosessor for this lpm instance.
+ * @lpm_id: The lv1 id of this lpm instance.
+ * @outlet_id: The outlet created by lv1 for this lpm instance.
+ * @tb_count: The number of bytes of data held in the lv1 trace buffer.
+ * @tb_cache: Kernel buffer to receive the data from the lv1 trace buffer.
+ * Must be 128 byte aligned.
+ * @tb_cache_size: Size of the kernel @tb_cache buffer. Must be 128 byte
+ * aligned.
+ * @tb_cache_internal: An unaligned buffer allocated by this driver to be
+ * used for the trace buffer cache when ps3_lpm_open() is called with a
+ * NULL tb_cache argument. Otherwise unused.
+ * @shadow: Processor register shadow of type struct ps3_lpm_shadow_regs.
+ * @sbd: The struct ps3_system_bus_device attached to this driver.
+ *
+ * The trace buffer is a buffer allocated and used internally to the lv1
+ * hypervisor to collect trace data. The trace buffer cache is a guest
+ * buffer that accepts the trace data from the trace buffer.
+ */
+
+struct ps3_lpm_priv {
+ atomic_t open;
+ u64 rights;
+ u64 pu_id;
+ u64 lpm_id;
+ u64 outlet_id;
+ u64 tb_count;
+ void *tb_cache;
+ u64 tb_cache_size;
+ void *tb_cache_internal;
+ struct ps3_lpm_shadow_regs shadow;
+ struct ps3_system_bus_device *sbd;
+};
+
+enum {
+ PS3_LPM_DEFAULT_TB_CACHE_SIZE = 0x4000,
+};
+
+/**
+ * lpm_priv - Static instance of the lpm data.
+ *
+ * Since the exported routines don't support the notion of a device
+ * instance we need to hold the instance in this static variable
+ * and then only allow at most one instance at a time to be created.
+ */
+
+static struct ps3_lpm_priv *lpm_priv;
+
+static struct device *sbd_core(void)
+{
+ BUG_ON(!lpm_priv || !lpm_priv->sbd);
+ return &lpm_priv->sbd->core;
+}
+
+/**
+ * use_start_stop_bookmark - Enable the PPU bookmark trace.
+ *
+ * And it enables PPU bookmark triggers ONLY if the other triggers are not set.
+ * The start/stop bookmarks are inserted at ps3_enable_pm() and ps3_disable_pm()
+ * to start/stop LPM.
+ *
+ * Used to get good quality of the performance counter.
+ */
+
+enum {use_start_stop_bookmark = 1,};
+
+void ps3_set_bookmark(u64 bookmark)
+{
+ /*
+ * As per the PPE book IV, to avoid bookmark lost there must
+ * not be a traced branch within 10 cycles of setting the
+ * SPRN_BKMK register. The actual text is unclear if 'within'
+ * includes cycles before the call.
+ */
+
+ asm volatile("or 29, 29, 29;"); /* db10cyc */
+ mtspr(SPRN_BKMK, bookmark);
+ asm volatile("or 29, 29, 29;"); /* db10cyc */
+}
+EXPORT_SYMBOL_GPL(ps3_set_bookmark);
+
+void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id)
+{
+ u64 bookmark;
+
+ bookmark = (get_tb() & 0x00000000FFFFFFFFULL) |
+ PS3_PM_BOOKMARK_TAG_KERNEL;
+ bookmark = ((tag << 56) & PS3_PM_BOOKMARK_TAG_MASK_LO) |
+ (incident << 48) | (th_id << 32) | bookmark;
+ ps3_set_bookmark(bookmark);
+}
+EXPORT_SYMBOL_GPL(ps3_set_pm_bookmark);
+
+/**
+ * ps3_read_phys_ctr - Read physical counter registers.
+ *
+ * Each physical counter can act as one 32 bit counter or as two 16 bit
+ * counters.
+ */
+
+u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr)
+{
+ int result;
+ u64 counter0415;
+ u64 counter2637;
+
+ if (phys_ctr >= NR_PHYS_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
+ __LINE__, phys_ctr);
+ return 0;
+ }
+
+ result = lv1_set_lpm_counter(lpm_priv->lpm_id, 0, 0, 0, 0, &counter0415,
+ &counter2637);
+ if (result) {
+ dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter failed: "
+ "phys_ctr %u, %s\n", __func__, __LINE__, phys_ctr,
+ ps3_result(result));
+ return 0;
+ }
+
+ switch (phys_ctr) {
+ case 0:
+ return counter0415 >> 32;
+ case 1:
+ return counter0415 & PS3_PM_COUNTER_MASK_LO;
+ case 2:
+ return counter2637 >> 32;
+ case 3:
+ return counter2637 & PS3_PM_COUNTER_MASK_LO;
+ default:
+ BUG();
+ }
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_read_phys_ctr);
+
+/**
+ * ps3_write_phys_ctr - Write physical counter registers.
+ *
+ * Each physical counter can act as one 32 bit counter or as two 16 bit
+ * counters.
+ */
+
+void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
+{
+ u64 counter0415;
+ u64 counter0415_mask;
+ u64 counter2637;
+ u64 counter2637_mask;
+ int result;
+
+ if (phys_ctr >= NR_PHYS_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
+ __LINE__, phys_ctr);
+ return;
+ }
+
+ switch (phys_ctr) {
+ case 0:
+ counter0415 = (u64)val << 32;
+ counter0415_mask = PS3_PM_COUNTER_MASK_HI;
+ counter2637 = 0x0;
+ counter2637_mask = 0x0;
+ break;
+ case 1:
+ counter0415 = (u64)val;
+ counter0415_mask = PS3_PM_COUNTER_MASK_LO;
+ counter2637 = 0x0;
+ counter2637_mask = 0x0;
+ break;
+ case 2:
+ counter0415 = 0x0;
+ counter0415_mask = 0x0;
+ counter2637 = (u64)val << 32;
+ counter2637_mask = PS3_PM_COUNTER_MASK_HI;
+ break;
+ case 3:
+ counter0415 = 0x0;
+ counter0415_mask = 0x0;
+ counter2637 = (u64)val;
+ counter2637_mask = PS3_PM_COUNTER_MASK_LO;
+ break;
+ default:
+ BUG();
+ }
+
+ result = lv1_set_lpm_counter(lpm_priv->lpm_id,
+ counter0415, counter0415_mask,
+ counter2637, counter2637_mask,
+ &counter0415, &counter2637);
+ if (result)
+ dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter failed: "
+ "phys_ctr %u, val %u, %s\n", __func__, __LINE__,
+ phys_ctr, val, ps3_result(result));
+}
+EXPORT_SYMBOL_GPL(ps3_write_phys_ctr);
+
+/**
+ * ps3_read_ctr - Read counter.
+ *
+ * Read 16 or 32 bits depending on the current size of the counter.
+ * Counters 4, 5, 6 & 7 are always 16 bit.
+ */
+
+u32 ps3_read_ctr(u32 cpu, u32 ctr)
+{
+ u32 val;
+ u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
+
+ val = ps3_read_phys_ctr(cpu, phys_ctr);
+
+ if (ps3_get_ctr_size(cpu, phys_ctr) == 16)
+ val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
+
+ return val;
+}
+EXPORT_SYMBOL_GPL(ps3_read_ctr);
+
+/**
+ * ps3_write_ctr - Write counter.
+ *
+ * Write 16 or 32 bits depending on the current size of the counter.
+ * Counters 4, 5, 6 & 7 are always 16 bit.
+ */
+
+void ps3_write_ctr(u32 cpu, u32 ctr, u32 val)
+{
+ u32 phys_ctr;
+ u32 phys_val;
+
+ phys_ctr = ctr & (NR_PHYS_CTRS - 1);
+
+ if (ps3_get_ctr_size(cpu, phys_ctr) == 16) {
+ phys_val = ps3_read_phys_ctr(cpu, phys_ctr);
+
+ if (ctr < NR_PHYS_CTRS)
+ val = (val << 16) | (phys_val & 0xffff);
+ else
+ val = (val & 0xffff) | (phys_val & 0xffff0000);
+ }
+
+ ps3_write_phys_ctr(cpu, phys_ctr, val);
+}
+EXPORT_SYMBOL_GPL(ps3_write_ctr);
+
+/**
+ * ps3_read_pm07_control - Read counter control registers.
+ *
+ * Each logical counter has a corresponding control register.
+ */
+
+u32 ps3_read_pm07_control(u32 cpu, u32 ctr)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_read_pm07_control);
+
+/**
+ * ps3_write_pm07_control - Write counter control registers.
+ *
+ * Each logical counter has a corresponding control register.
+ */
+
+void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val)
+{
+ int result;
+ static const u64 mask = 0xFFFFFFFFFFFFFFFFULL;
+ u64 old_value;
+
+ if (ctr >= NR_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: ctr too big: %u\n", __func__,
+ __LINE__, ctr);
+ return;
+ }
+
+ result = lv1_set_lpm_counter_control(lpm_priv->lpm_id, ctr, val, mask,
+ &old_value);
+ if (result)
+ dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter_control "
+ "failed: ctr %u, %s\n", __func__, __LINE__, ctr,
+ ps3_result(result));
+}
+EXPORT_SYMBOL_GPL(ps3_write_pm07_control);
+
+/**
+ * ps3_read_pm - Read Other LPM control registers.
+ */
+
+u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg)
+{
+ int result = 0;
+ u64 val = 0;
+
+ switch (reg) {
+ case pm_control:
+ return lpm_priv->shadow.pm_control;
+ case trace_address:
+ return CBE_PM_TRACE_BUF_EMPTY;
+ case pm_start_stop:
+ return lpm_priv->shadow.pm_start_stop;
+ case pm_interval:
+ return lpm_priv->shadow.pm_interval;
+ case group_control:
+ return lpm_priv->shadow.group_control;
+ case debug_bus_control:
+ return lpm_priv->shadow.debug_bus_control;
+ case pm_status:
+ result = lv1_get_lpm_interrupt_status(lpm_priv->lpm_id,
+ &val);
+ if (result) {
+ val = 0;
+ dev_dbg(sbd_core(), "%s:%u: lv1 get_lpm_status failed: "
+ "reg %u, %s\n", __func__, __LINE__, reg,
+ ps3_result(result));
+ }
+ return (u32)val;
+ case ext_tr_timer:
+ return 0;
+ default:
+ dev_dbg(sbd_core(), "%s:%u: unknown reg: %d\n", __func__,
+ __LINE__, reg);
+ BUG();
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_read_pm);
+
+/**
+ * ps3_write_pm - Write Other LPM control registers.
+ */
+
+void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
+{
+ int result = 0;
+ u64 dummy;
+
+ switch (reg) {
+ case group_control:
+ if (val != lpm_priv->shadow.group_control)
+ result = lv1_set_lpm_group_control(lpm_priv->lpm_id,
+ val,
+ PS3_WRITE_PM_MASK,
+ &dummy);
+ lpm_priv->shadow.group_control = val;
+ break;
+ case debug_bus_control:
+ if (val != lpm_priv->shadow.debug_bus_control)
+ result = lv1_set_lpm_debug_bus_control(lpm_priv->lpm_id,
+ val,
+ PS3_WRITE_PM_MASK,
+ &dummy);
+ lpm_priv->shadow.debug_bus_control = val;
+ break;
+ case pm_control:
+ if (use_start_stop_bookmark)
+ val |= (PS3_PM_CONTROL_PPU_TH0_BOOKMARK |
+ PS3_PM_CONTROL_PPU_TH1_BOOKMARK);
+ if (val != lpm_priv->shadow.pm_control)
+ result = lv1_set_lpm_general_control(lpm_priv->lpm_id,
+ val,
+ PS3_WRITE_PM_MASK,
+ 0, 0, &dummy,
+ &dummy);
+ lpm_priv->shadow.pm_control = val;
+ break;
+ case pm_interval:
+ if (val != lpm_priv->shadow.pm_interval)
+ result = lv1_set_lpm_interval(lpm_priv->lpm_id, val,
+ PS3_WRITE_PM_MASK, &dummy);
+ lpm_priv->shadow.pm_interval = val;
+ break;
+ case pm_start_stop:
+ if (val != lpm_priv->shadow.pm_start_stop)
+ result = lv1_set_lpm_trigger_control(lpm_priv->lpm_id,
+ val,
+ PS3_WRITE_PM_MASK,
+ &dummy);
+ lpm_priv->shadow.pm_start_stop = val;
+ break;
+ case trace_address:
+ case ext_tr_timer:
+ case pm_status:
+ break;
+ default:
+ dev_dbg(sbd_core(), "%s:%u: unknown reg: %d\n", __func__,
+ __LINE__, reg);
+ BUG();
+ break;
+ }
+
+ if (result)
+ dev_err(sbd_core(), "%s:%u: lv1 set_control failed: "
+ "reg %u, %s\n", __func__, __LINE__, reg,
+ ps3_result(result));
+}
+EXPORT_SYMBOL_GPL(ps3_write_pm);
+
+/**
+ * ps3_get_ctr_size - Get the size of a physical counter.
+ *
+ * Returns either 16 or 32.
+ */
+
+u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr)
+{
+ u32 pm_ctrl;
+
+ if (phys_ctr >= NR_PHYS_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
+ __LINE__, phys_ctr);
+ return 0;
+ }
+
+ pm_ctrl = ps3_read_pm(cpu, pm_control);
+ return (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
+}
+EXPORT_SYMBOL_GPL(ps3_get_ctr_size);
+
+/**
+ * ps3_set_ctr_size - Set the size of a physical counter to 16 or 32 bits.
+ */
+
+void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
+{
+ u32 pm_ctrl;
+
+ if (phys_ctr >= NR_PHYS_CTRS) {
+ dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
+ __LINE__, phys_ctr);
+ return;
+ }
+
+ pm_ctrl = ps3_read_pm(cpu, pm_control);
+
+ switch (ctr_size) {
+ case 16:
+ pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
+ ps3_write_pm(cpu, pm_control, pm_ctrl);
+ break;
+
+ case 32:
+ pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
+ ps3_write_pm(cpu, pm_control, pm_ctrl);
+ break;
+ default:
+ BUG();
+ }
+}
+EXPORT_SYMBOL_GPL(ps3_set_ctr_size);
+
+static u64 pm_translate_signal_group_number_on_island2(u64 subgroup)
+{
+
+ if (subgroup == 2)
+ subgroup = 3;
+
+ if (subgroup <= 6)
+ return PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+ else if (subgroup == 7)
+ return PM_ISLAND2_SIGNAL_GROUP_NUMBER1;
+ else
+ return PM_ISLAND2_SIGNAL_GROUP_NUMBER2;
+}
+
+static u64 pm_translate_signal_group_number_on_island3(u64 subgroup)
+{
+
+ switch (subgroup) {
+ case 2:
+ case 3:
+ case 4:
+ subgroup += 2;
+ break;
+ case 5:
+ subgroup = 8;
+ break;
+ default:
+ break;
+ }
+ return PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_translate_signal_group_number_on_island4(u64 subgroup)
+{
+ return PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_translate_signal_group_number_on_island5(u64 subgroup)
+{
+
+ switch (subgroup) {
+ case 3:
+ subgroup = 4;
+ break;
+ case 4:
+ subgroup = 6;
+ break;
+ default:
+ break;
+ }
+ return PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_translate_signal_group_number_on_island6(u64 subgroup,
+ u64 subsubgroup)
+{
+ switch (subgroup) {
+ case 3:
+ case 4:
+ case 5:
+ subgroup += 1;
+ break;
+ default:
+ break;
+ }
+
+ switch (subsubgroup) {
+ case 4:
+ case 5:
+ case 6:
+ subsubgroup += 2;
+ break;
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ subsubgroup += 4;
+ break;
+ case 11:
+ case 12:
+ case 13:
+ subsubgroup += 5;
+ break;
+ default:
+ break;
+ }
+
+ if (subgroup <= 5)
+ return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup);
+ else
+ return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup
+ + subsubgroup - 1);
+}
+
+static u64 pm_translate_signal_group_number_on_island7(u64 subgroup)
+{
+ return PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_translate_signal_group_number_on_island8(u64 subgroup)
+{
+ return PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER + subgroup;
+}
+
+static u64 pm_signal_group_to_ps3_lv1_signal_group(u64 group)
+{
+ u64 island;
+ u64 subgroup;
+ u64 subsubgroup;
+
+ subgroup = 0;
+ subsubgroup = 0;
+ island = 0;
+ if (group < 1000) {
+ if (group < 100) {
+ if (20 <= group && group < 30) {
+ island = 2;
+ subgroup = group - 20;
+ } else if (30 <= group && group < 40) {
+ island = 3;
+ subgroup = group - 30;
+ } else if (40 <= group && group < 50) {
+ island = 4;
+ subgroup = group - 40;
+ } else if (50 <= group && group < 60) {
+ island = 5;
+ subgroup = group - 50;
+ } else if (60 <= group && group < 70) {
+ island = 6;
+ subgroup = group - 60;
+ } else if (70 <= group && group < 80) {
+ island = 7;
+ subgroup = group - 70;
+ } else if (80 <= group && group < 90) {
+ island = 8;
+ subgroup = group - 80;
+ }
+ } else if (200 <= group && group < 300) {
+ island = 2;
+ subgroup = group - 200;
+ } else if (600 <= group && group < 700) {
+ island = 6;
+ subgroup = 5;
+ subsubgroup = group - 650;
+ }
+ } else if (6000 <= group && group < 7000) {
+ island = 6;
+ subgroup = 5;
+ subsubgroup = group - 6500;
+ }
+
+ switch (island) {
+ case 2:
+ return pm_translate_signal_group_number_on_island2(subgroup);
+ case 3:
+ return pm_translate_signal_group_number_on_island3(subgroup);
+ case 4:
+ return pm_translate_signal_group_number_on_island4(subgroup);
+ case 5:
+ return pm_translate_signal_group_number_on_island5(subgroup);
+ case 6:
+ return pm_translate_signal_group_number_on_island6(subgroup,
+ subsubgroup);
+ case 7:
+ return pm_translate_signal_group_number_on_island7(subgroup);
+ case 8:
+ return pm_translate_signal_group_number_on_island8(subgroup);
+ default:
+ dev_dbg(sbd_core(), "%s:%u: island not found: %lu\n", __func__,
+ __LINE__, group);
+ BUG();
+ break;
+ }
+ return 0;
+}
+
+static u64 pm_bus_word_to_ps3_lv1_bus_word(u8 word)
+{
+
+ switch (word) {
+ case 1:
+ return 0xF000;
+ case 2:
+ return 0x0F00;
+ case 4:
+ return 0x00F0;
+ case 8:
+ default:
+ return 0x000F;
+ }
+}
+
+static int __ps3_set_signal(u64 lv1_signal_group, u64 bus_select,
+ u64 signal_select, u64 attr1, u64 attr2, u64 attr3)
+{
+ int ret;
+
+ ret = lv1_set_lpm_signal(lpm_priv->lpm_id, lv1_signal_group, bus_select,
+ signal_select, attr1, attr2, attr3);
+ if (ret)
+ dev_err(sbd_core(),
+ "%s:%u: error:%d 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx 0x%lx\n",
+ __func__, __LINE__, ret, lv1_signal_group, bus_select,
+ signal_select, attr1, attr2, attr3);
+
+ return ret;
+}
+
+int ps3_set_signal(u64 signal_group, u8 signal_bit, u16 sub_unit,
+ u8 bus_word)
+{
+ int ret;
+ u64 lv1_signal_group;
+ u64 bus_select;
+ u64 signal_select;
+ u64 attr1, attr2, attr3;
+
+ if (signal_group == 0)
+ return __ps3_set_signal(0, 0, 0, 0, 0, 0);
+
+ lv1_signal_group =
+ pm_signal_group_to_ps3_lv1_signal_group(signal_group);
+ bus_select = pm_bus_word_to_ps3_lv1_bus_word(bus_word);
+
+ switch (signal_group) {
+ case PM_SIG_GROUP_SPU_TRIGGER:
+ signal_select = 1;
+ signal_select = signal_select << (63 - signal_bit);
+ break;
+ case PM_SIG_GROUP_SPU_EVENT:
+ signal_select = 1;
+ signal_select = (signal_select << (63 - signal_bit)) | 0x3;
+ break;
+ default:
+ signal_select = 0;
+ break;
+ }
+
+ /*
+ * 0: physical object.
+ * 1: logical object.
+ * This parameter is only used for the PPE and SPE signals.
+ */
+ attr1 = 1;
+
+ /*
+ * This parameter is used to specify the target physical/logical
+ * PPE/SPE object.
+ */
+ if (PM_SIG_GROUP_SPU <= signal_group &&
+ signal_group < PM_SIG_GROUP_MFC_MAX)
+ attr2 = sub_unit;
+ else
+ attr2 = lpm_priv->pu_id;
+
+ /*
+ * This parameter is only used for setting the SPE signal.
+ */
+ attr3 = 0;
+
+ ret = __ps3_set_signal(lv1_signal_group, bus_select, signal_select,
+ attr1, attr2, attr3);
+ if (ret)
+ dev_err(sbd_core(), "%s:%u: __ps3_set_signal failed: %d\n",
+ __func__, __LINE__, ret);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(ps3_set_signal);
+
+u32 ps3_get_hw_thread_id(int cpu)
+{
+ return get_hard_smp_processor_id(cpu);
+}
+EXPORT_SYMBOL_GPL(ps3_get_hw_thread_id);
+
+/**
+ * ps3_enable_pm - Enable the entire performance monitoring unit.
+ *
+ * When we enable the LPM, all pending writes to counters get committed.
+ */
+
+void ps3_enable_pm(u32 cpu)
+{
+ int result;
+ u64 tmp;
+ int insert_bookmark = 0;
+
+ lpm_priv->tb_count = 0;
+
+ if (use_start_stop_bookmark) {
+ if (!(lpm_priv->shadow.pm_start_stop &
+ (PS3_PM_START_STOP_START_MASK
+ | PS3_PM_START_STOP_STOP_MASK))) {
+ result = lv1_set_lpm_trigger_control(lpm_priv->lpm_id,
+ (PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START |
+ PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START |
+ PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP |
+ PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP),
+ 0xFFFFFFFFFFFFFFFFULL, &tmp);
+
+ if (result)
+ dev_err(sbd_core(), "%s:%u: "
+ "lv1_set_lpm_trigger_control failed: "
+ "%s\n", __func__, __LINE__,
+ ps3_result(result));
+
+ insert_bookmark = !result;
+ }
+ }
+
+ result = lv1_start_lpm(lpm_priv->lpm_id);
+
+ if (result)
+ dev_err(sbd_core(), "%s:%u: lv1_start_lpm failed: %s\n",
+ __func__, __LINE__, ps3_result(result));
+
+ if (use_start_stop_bookmark && !result && insert_bookmark)
+ ps3_set_bookmark(get_tb() | PS3_PM_BOOKMARK_START);
+}
+EXPORT_SYMBOL_GPL(ps3_enable_pm);
+
+/**
+ * ps3_disable_pm - Disable the entire performance monitoring unit.
+ */
+
+void ps3_disable_pm(u32 cpu)
+{
+ int result;
+ u64 tmp;
+
+ ps3_set_bookmark(get_tb() | PS3_PM_BOOKMARK_STOP);
+
+ result = lv1_stop_lpm(lpm_priv->lpm_id, &tmp);
+
+ if (result) {
+ dev_err(sbd_core(), "%s:%u: lv1_stop_lpm failed: %s\n",
+ __func__, __LINE__, ps3_result(result));
+ return;
+ }
+
+ lpm_priv->tb_count = tmp;
+
+ dev_err(sbd_core(), "%s:%u: tb_count %lu (%lxh)\n", __func__, __LINE__,
+ lpm_priv->tb_count, lpm_priv->tb_count);
+}
+EXPORT_SYMBOL_GPL(ps3_disable_pm);
+
+/**
+ * ps3_lpm_copy_tb - Copy data from the trace buffer to a kernel buffer.
+ * @offset: Offset in bytes from the start of the trace buffer.
+ * @buf: Copy destination.
+ * @count: Maximum count of bytes to copy.
+ * @bytes_copied: Pointer to a variable that will recieve the number of
+ * bytes copied to @buf.
+ *
+ * On error @buf will contain any successfully copied trace buffer data
+ * and bytes_copied will be set to the number of bytes successfully copied.
+ */
+
+int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
+ unsigned long *bytes_copied)
+{
+ int result;
+
+ *bytes_copied = 0;
+
+ if (!lpm_priv->tb_cache)
+ return -EPERM;
+
+ if (offset >= lpm_priv->tb_count)
+ return 0;
+
+ count = min(count, lpm_priv->tb_count - offset);
+
+ while (*bytes_copied < count) {
+ const unsigned long request = count - *bytes_copied;
+ u64 tmp;
+
+ result = lv1_copy_lpm_trace_buffer(lpm_priv->lpm_id, offset,
+ request, &tmp);
+ if (result) {
+ dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%lx\n",
+ __func__, __LINE__, request, offset);
+
+ dev_err(sbd_core(), "%s:%u: lv1_copy_lpm_trace_buffer "
+ "failed: %s\n", __func__, __LINE__,
+ ps3_result(result));
+ return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL;
+ }
+
+ memcpy(buf, lpm_priv->tb_cache, tmp);
+ buf += tmp;
+ *bytes_copied += tmp;
+ offset += tmp;
+ }
+ dev_dbg(sbd_core(), "%s:%u: copied %lxh bytes\n", __func__, __LINE__,
+ *bytes_copied);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_lpm_copy_tb);
+
+/**
+ * ps3_lpm_copy_tb_to_user - Copy data from the trace buffer to a user buffer.
+ * @offset: Offset in bytes from the start of the trace buffer.
+ * @buf: A __user copy destination.
+ * @count: Maximum count of bytes to copy.
+ * @bytes_copied: Pointer to a variable that will recieve the number of
+ * bytes copied to @buf.
+ *
+ * On error @buf will contain any successfully copied trace buffer data
+ * and bytes_copied will be set to the number of bytes successfully copied.
+ */
+
+int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
+ unsigned long count, unsigned long *bytes_copied)
+{
+ int result;
+
+ *bytes_copied = 0;
+
+ if (!lpm_priv->tb_cache)
+ return -EPERM;
+
+ if (offset >= lpm_priv->tb_count)
+ return 0;
+
+ count = min(count, lpm_priv->tb_count - offset);
+
+ while (*bytes_copied < count) {
+ const unsigned long request = count - *bytes_copied;
+ u64 tmp;
+
+ result = lv1_copy_lpm_trace_buffer(lpm_priv->lpm_id, offset,
+ request, &tmp);
+ if (result) {
+ dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%lx\n",
+ __func__, __LINE__, request, offset);
+ dev_err(sbd_core(), "%s:%u: lv1_copy_lpm_trace_buffer "
+ "failed: %s\n", __func__, __LINE__,
+ ps3_result(result));
+ return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL;
+ }
+
+ result = copy_to_user(buf, lpm_priv->tb_cache, tmp);
+
+ if (result) {
+ dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%p\n",
+ __func__, __LINE__, tmp, buf);
+ dev_err(sbd_core(), "%s:%u: copy_to_user failed: %d\n",
+ __func__, __LINE__, result);
+ return -EFAULT;
+ }
+
+ buf += tmp;
+ *bytes_copied += tmp;
+ offset += tmp;
+ }
+ dev_dbg(sbd_core(), "%s:%u: copied %lxh bytes\n", __func__, __LINE__,
+ *bytes_copied);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_lpm_copy_tb_to_user);
+
+/**
+ * ps3_get_and_clear_pm_interrupts -
+ *
+ * Clearing interrupts for the entire performance monitoring unit.
+ * Reading pm_status clears the interrupt bits.
+ */
+
+u32 ps3_get_and_clear_pm_interrupts(u32 cpu)
+{
+ return ps3_read_pm(cpu, pm_status);
+}
+EXPORT_SYMBOL_GPL(ps3_get_and_clear_pm_interrupts);
+
+/**
+ * ps3_enable_pm_interrupts -
+ *
+ * Enabling interrupts for the entire performance monitoring unit.
+ * Enables the interrupt bits in the pm_status register.
+ */
+
+void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
+{
+ if (mask)
+ ps3_write_pm(cpu, pm_status, mask);
+}
+EXPORT_SYMBOL_GPL(ps3_enable_pm_interrupts);
+
+/**
+ * ps3_enable_pm_interrupts -
+ *
+ * Disabling interrupts for the entire performance monitoring unit.
+ */
+
+void ps3_disable_pm_interrupts(u32 cpu)
+{
+ ps3_get_and_clear_pm_interrupts(cpu);
+ ps3_write_pm(cpu, pm_status, 0);
+}
+EXPORT_SYMBOL_GPL(ps3_disable_pm_interrupts);
+
+/**
+ * ps3_lpm_open - Open the logical performance monitor device.
+ * @tb_type: Specifies the type of trace buffer lv1 sould use for this lpm
+ * instance, specified by one of enum ps3_lpm_tb_type.
+ * @tb_cache: Optional user supplied buffer to use as the trace buffer cache.
+ * If NULL, the driver will allocate and manage an internal buffer.
+ * Unused when when @tb_type is PS3_LPM_TB_TYPE_NONE.
+ * @tb_cache_size: The size in bytes of the user supplied @tb_cache buffer.
+ * Unused when @tb_cache is NULL or @tb_type is PS3_LPM_TB_TYPE_NONE.
+ */
+
+int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
+ u64 tb_cache_size)
+{
+ int result;
+ u64 tb_size;
+
+ BUG_ON(!lpm_priv);
+ BUG_ON(tb_type != PS3_LPM_TB_TYPE_NONE
+ && tb_type != PS3_LPM_TB_TYPE_INTERNAL);
+
+ if (tb_type == PS3_LPM_TB_TYPE_NONE && tb_cache)
+ dev_dbg(sbd_core(), "%s:%u: bad in vals\n", __func__, __LINE__);
+
+ if (!atomic_add_unless(&lpm_priv->open, 1, 1)) {
+ dev_dbg(sbd_core(), "%s:%u: busy\n", __func__, __LINE__);
+ return -EBUSY;
+ }
+
+ if (tb_type == PS3_LPM_TB_TYPE_NONE) {
+ lpm_priv->tb_cache_internal = NULL;
+ lpm_priv->tb_cache_size = 0;
+ lpm_priv->tb_cache = NULL;
+ } else if (tb_cache) {
+ if (tb_cache != (void *)_ALIGN_UP((unsigned long)tb_cache, 128)
+ || tb_cache_size != _ALIGN_UP(tb_cache_size, 128)) {
+ dev_err(sbd_core(), "%s:%u: unaligned tb_cache\n",
+ __func__, __LINE__);
+ result = -EINVAL;
+ goto fail_align;
+ }
+ lpm_priv->tb_cache_internal = NULL;
+ lpm_priv->tb_cache_size = tb_cache_size;
+ lpm_priv->tb_cache = tb_cache;
+ } else {
+ /* tb_cache needs 128 byte alignment. */
+ lpm_priv->tb_cache_size = PS3_LPM_DEFAULT_TB_CACHE_SIZE;
+ lpm_priv->tb_cache_internal = kzalloc(tb_cache_size + 127,
+ GFP_KERNEL);
+ if (!lpm_priv->tb_cache_internal) {
+ dev_err(sbd_core(), "%s:%u: alloc internal tb_cache "
+ "failed\n", __func__, __LINE__);
+ result = -ENOMEM;
+ goto fail_malloc;
+ }
+ lpm_priv->tb_cache = (void *)_ALIGN_UP(
+ (unsigned long)lpm_priv->tb_cache_internal, 128);
+ }
+
+ result = lv1_construct_lpm(0, tb_type, 0, 0,
+ ps3_mm_phys_to_lpar(__pa(lpm_priv->tb_cache)),
+ lpm_priv->tb_cache_size, &lpm_priv->lpm_id,
+ &lpm_priv->outlet_id, &tb_size);
+
+ if (result) {
+ dev_err(sbd_core(), "%s:%u: lv1_construct_lpm failed: %s\n",
+ __func__, __LINE__, ps3_result(result));
+ result = -EINVAL;
+ goto fail_construct;
+ }
+
+ lpm_priv->shadow.pm_control = PS3_LPM_SHADOW_REG_INIT;
+ lpm_priv->shadow.pm_start_stop = PS3_LPM_SHADOW_REG_INIT;
+ lpm_priv->shadow.pm_interval = PS3_LPM_SHADOW_REG_INIT;
+ lpm_priv->shadow.group_control = PS3_LPM_SHADOW_REG_INIT;
+ lpm_priv->shadow.debug_bus_control = PS3_LPM_SHADOW_REG_INIT;
+
+ dev_dbg(sbd_core(), "%s:%u: lpm_id 0x%lx, outlet_id 0x%lx, "
+ "tb_size 0x%lx\n", __func__, __LINE__, lpm_priv->lpm_id,
+ lpm_priv->outlet_id, tb_size);
+
+ return 0;
+
+fail_construct:
+ kfree(lpm_priv->tb_cache_internal);
+ lpm_priv->tb_cache_internal = NULL;
+fail_malloc:
+fail_align:
+ atomic_dec(&lpm_priv->open);
+ return result;
+}
+EXPORT_SYMBOL_GPL(ps3_lpm_open);
+
+/**
+ * ps3_lpm_close - Close the lpm device.
+ *
+ */
+
+int ps3_lpm_close(void)
+{
+ dev_dbg(sbd_core(), "%s:%u\n", __func__, __LINE__);
+
+ lv1_destruct_lpm(lpm_priv->lpm_id);
+ lpm_priv->lpm_id = 0;
+
+ kfree(lpm_priv->tb_cache_internal);
+ lpm_priv->tb_cache_internal = NULL;
+
+ atomic_dec(&lpm_priv->open);
+ return 0;
+}
+EXPORT_SYMBOL_GPL(ps3_lpm_close);
+
+static int __devinit ps3_lpm_probe(struct ps3_system_bus_device *dev)
+{
+ dev_dbg(&dev->core, " -> %s:%u\n", __func__, __LINE__);
+
+ if (lpm_priv) {
+ dev_info(&dev->core, "%s:%u: called twice\n",
+ __func__, __LINE__);
+ return -EBUSY;
+ }
+
+ lpm_priv = kzalloc(sizeof(*lpm_priv), GFP_KERNEL);
+
+ if (!lpm_priv)
+ return -ENOMEM;
+
+ lpm_priv->sbd = dev;
+ lpm_priv->pu_id = dev->lpm.pu_id;
+ lpm_priv->rights = dev->lpm.rights;
+
+ dev_info(&dev->core, " <- %s:%u:\n", __func__, __LINE__);
+
+ return 0;
+}
+
+static int ps3_lpm_remove(struct ps3_system_bus_device *dev)
+{
+ dev_dbg(&dev->core, " -> %s:%u:\n", __func__, __LINE__);
+
+ ps3_lpm_close();
+
+ kfree(lpm_priv);
+ lpm_priv = NULL;
+
+ dev_info(&dev->core, " <- %s:%u:\n", __func__, __LINE__);
+ return 0;
+}
+
+static struct ps3_system_bus_driver ps3_lpm_driver = {
+ .match_id = PS3_MATCH_ID_LPM,
+ .core.name = "ps3-lpm",
+ .core.owner = THIS_MODULE,
+ .probe = ps3_lpm_probe,
+ .remove = ps3_lpm_remove,
+ .shutdown = ps3_lpm_remove,
+};
+
+static int __init ps3_lpm_init(void)
+{
+ pr_debug("%s:%d:\n", __func__, __LINE__);
+ return ps3_system_bus_driver_register(&ps3_lpm_driver);
+}
+
+static void __exit ps3_lpm_exit(void)
+{
+ pr_debug("%s:%d:\n", __func__, __LINE__);
+ ps3_system_bus_driver_unregister(&ps3_lpm_driver);
+}
+
+module_init(ps3_lpm_init);
+module_exit(ps3_lpm_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PS3 Logical Performance Monitor Driver");
+MODULE_AUTHOR("Sony Corporation");
+MODULE_ALIAS(PS3_MODULE_ALIAS_LPM);
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/device.h>
+#include "cell-pmu.h"
union ps3_firmware_version {
u64 raw;
@@ -445,5 +446,66 @@ struct ps3_prealloc {
extern struct ps3_prealloc ps3fb_videomemory;
extern struct ps3_prealloc ps3flash_bounce_buffer;
+/* logical performance monitor */
+
+/**
+ * enum ps3_lpm_rights - Rigths granted by the system policy module.
+ *
+ * @PS3_LPM_RIGHTS_USE_LPM: The right to use the lpm.
+ * @PS3_LPM_RIGHTS_USE_TB: The right to use the internal trace buffer.
+ */
+
+enum ps3_lpm_rights {
+ PS3_LPM_RIGHTS_USE_LPM = 0x001,
+ PS3_LPM_RIGHTS_USE_TB = 0x100,
+};
+
+/**
+ * enum ps3_lpm_tb_type - Type of trace buffer lv1 should use.
+ *
+ * @PS3_LPM_TB_TYPE_NONE: Do not use a trace buffer.
+ * @PS3_LPM_RIGHTS_USE_TB: Use the lv1 internal trace buffer. Must have
+ * rights @PS3_LPM_RIGHTS_USE_TB.
+ */
+
+enum ps3_lpm_tb_type {
+ PS3_LPM_TB_TYPE_NONE = 0,
+ PS3_LPM_TB_TYPE_INTERNAL = 1,
+};
+
+int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
+ u64 tb_cache_size);
+int ps3_lpm_close(void);
+int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
+ unsigned long *bytes_copied);
+int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
+ unsigned long count, unsigned long *bytes_copied);
+void ps3_set_bookmark(u64 bookmark);
+void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id);
+int ps3_set_signal(u64 rtas_signal_group, u8 signal_bit, u16 sub_unit,
+ u8 bus_word);
+
+u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr);
+void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
+u32 ps3_read_ctr(u32 cpu, u32 ctr);
+void ps3_write_ctr(u32 cpu, u32 ctr, u32 val);
+
+u32 ps3_read_pm07_control(u32 cpu, u32 ctr);
+void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val);
+u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg);
+void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
+
+u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr);
+void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
+
+void ps3_enable_pm(u32 cpu);
+void ps3_disable_pm(u32 cpu);
+void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
+void ps3_disable_pm_interrupts(u32 cpu);
+
+u32 ps3_get_and_clear_pm_interrupts(u32 cpu);
+void ps3_sync_irq(int node);
+u32 ps3_get_hw_thread_id(int cpu);
+u64 ps3_get_spe_id(void *arg);
#endif
^ permalink raw reply
* [patch 3/4 v2] PS3: Add logical performance monitor device support
From: Geoff Levand @ 2008-01-09 6:35 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
In-Reply-To: <477EF59C.2070809@am.sony.com>
Add PS3 logical performance monitor device support to the
PS3 system-bus and platform device registration routines.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
v2: o Add enum ps3_lpm_tb_type.
o Remove redundant enclosing structure and return proper
error codes from ps3_register_lpm_devices().
arch/powerpc/platforms/ps3/device-init.c | 91 +++++++++++++++++++++++++++++++
arch/powerpc/platforms/ps3/system-bus.c | 5 +
include/asm-powerpc/ps3.h | 7 ++
3 files changed, 103 insertions(+)
create mode 100644 arch/powerpc/platforms/ps3/lpm.c
--- a/arch/powerpc/platforms/ps3/device-init.c
+++ b/arch/powerpc/platforms/ps3/device-init.c
@@ -30,6 +30,95 @@
#include "platform.h"
+static int __init ps3_register_lpm_devices(void)
+{
+ int result;
+ unsigned int pu_count;
+ u64 tmp1;
+ u64 tmp2;
+ struct ps3_system_bus_device *dev;
+
+ pr_debug(" -> %s:%d\n", __func__, __LINE__);
+
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ dev->match_id = PS3_MATCH_ID_LPM;
+ dev->dev_type = PS3_DEVICE_TYPE_LPM;
+
+ result = ps3_repository_read_num_pu(&pu_count);
+
+ if (result) {
+ pr_debug("%s:%d: ps3_repository_read_num_pu failed \n",
+ __func__, __LINE__);
+ goto fail_read_repo;
+ }
+
+ /* The current lpm driver only supports a single BE processor. */
+
+ if (pu_count > 1) {
+ pr_info("%s:%d: found %u BE processors, only one supported\n",
+ __func__, __LINE__, pu_count);
+ }
+
+ result = ps3_repository_read_pu_id(0, &dev->lpm.pu_id);
+
+ if (result) {
+ pr_debug("%s:%d: ps3_repository_read_pu_id failed \n",
+ __func__, __LINE__);
+ goto fail_read_repo;
+ }
+
+ result = ps3_repository_read_lpm_privileges(0, &tmp1,
+ &dev->lpm.rights);
+
+ if (result) {
+ pr_debug("%s:%d: ps3_repository_read_lpm_privleges failed \n",
+ __func__, __LINE__);
+ goto fail_read_repo;
+ }
+
+ lv1_get_logical_partition_id(&tmp2);
+
+ if (tmp1 != tmp2) {
+ pr_debug("%s:%d: wrong lpar\n",
+ __func__, __LINE__);
+ result = -ENODEV;
+ goto fail_rights;
+ }
+
+ if (!(dev->lpm.rights & PS3_LPM_RIGHTS_USE_LPM)) {
+ pr_debug("%s:%d: don't have rights to use lpm\n",
+ __func__, __LINE__);
+ result = -EPERM;
+ goto fail_rights;
+ }
+
+ pr_debug("%s:%d: pu_id %lu, rights %lu(%lxh)\n",
+ __func__, __LINE__, dev->lpm.pu_id, dev->lpm.rights,
+ dev->lpm.rights);
+
+ result = ps3_system_bus_device_register(dev);
+
+ if (result) {
+ pr_debug("%s:%d ps3_system_bus_device_register failed\n",
+ __func__, __LINE__);
+ goto fail_register;
+ }
+
+ pr_debug(" <- %s:%d\n", __func__, __LINE__);
+ return 0;
+
+
+fail_register:
+fail_rights:
+fail_read_repo:
+ kfree(dev);
+ pr_debug(" <- %s:%d: failed\n", __func__, __LINE__);
+ return result;
+}
+
/**
* ps3_setup_gelic_device - Setup and register a gelic device instance.
*
@@ -787,6 +876,8 @@ static int __init ps3_register_devices(v
ps3_register_sound_devices();
+ ps3_register_lpm_devices();
+
pr_debug(" <- %s:%d\n", __func__, __LINE__);
return 0;
}
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -715,6 +715,7 @@ int ps3_system_bus_device_register(struc
static unsigned int dev_ioc0_count;
static unsigned int dev_sb_count;
static unsigned int dev_vuart_count;
+ static unsigned int dev_lpm_count;
if (!dev->core.parent)
dev->core.parent = &ps3_system_bus;
@@ -737,6 +738,10 @@ int ps3_system_bus_device_register(struc
snprintf(dev->core.bus_id, sizeof(dev->core.bus_id),
"vuart_%02x", ++dev_vuart_count);
break;
+ case PS3_DEVICE_TYPE_LPM:
+ snprintf(dev->core.bus_id, sizeof(dev->core.bus_id),
+ "lpm_%02x", ++dev_lpm_count);
+ break;
default:
BUG();
};
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -317,6 +317,7 @@ enum ps3_match_id {
PS3_MATCH_ID_STOR_FLASH = 8,
PS3_MATCH_ID_SOUND = 9,
PS3_MATCH_ID_GRAPHICS = 10,
+ PS3_MATCH_ID_LPM = 11,
};
#define PS3_MODULE_ALIAS_EHCI "ps3:1"
@@ -329,11 +330,13 @@ enum ps3_match_id {
#define PS3_MODULE_ALIAS_STOR_FLASH "ps3:8"
#define PS3_MODULE_ALIAS_SOUND "ps3:9"
#define PS3_MODULE_ALIAS_GRAPHICS "ps3:10"
+#define PS3_MODULE_ALIAS_LPM "ps3:11"
enum ps3_system_bus_device_type {
PS3_DEVICE_TYPE_IOC0 = 1,
PS3_DEVICE_TYPE_SB,
PS3_DEVICE_TYPE_VUART,
+ PS3_DEVICE_TYPE_LPM,
};
/**
@@ -350,6 +353,10 @@ struct ps3_system_bus_device {
struct ps3_dma_region *d_region; /* SB, IOC0 */
struct ps3_mmio_region *m_region; /* SB, IOC0*/
unsigned int port_number; /* VUART */
+ struct { /* LPM */
+ u64 pu_id;
+ u64 rights;
+ } lpm;
/* struct iommu_table *iommu_table; -- waiting for BenH's cleanups */
struct device core;
^ permalink raw reply
* Re: [PATCH 1/3] sbc834x: Add support for Wind River SBC834x boards
From: Stephen Rothwell @ 2008-01-09 7:01 UTC (permalink / raw)
To: Paul Gortmaker; +Cc: linuxppc-dev
In-Reply-To: <1199857773848-git-send-email-paul.gortmaker@windriver.com>
[-- Attachment #1: Type: text/plain, Size: 975 bytes --]
Hi Paul,
On Wed, 9 Jan 2008 00:49:30 -0500 Paul Gortmaker <paul.gortmaker@windriver.com> wrote:
>
> +static void __init sbc834x_init_IRQ(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_node_by_type(NULL, "ipic");
> + if (!np)
> + return;
> +
> + ipic_init(np, 0);
> +
> + /* Initialize the default interrupt mapping priorities,
> + * in case the boot rom changed something on us.
> + */
> + ipic_set_default_priority();
> +}
This needs an of_node_put(np) somewhere.
> +static struct of_device_id sbc834x_ids[] = {
__initdata
> +static int __init sbc834x_declare_of_platform_devices(void)
> +{
> + if (!machine_is(sbc834x))
> + return 0;
> +
> + of_platform_bus_probe(NULL, sbc834x_ids, NULL);
> + return 0;
> +}
> +device_initcall(sbc834x_declare_of_platform_devices);
machine_device_initcall(sbc834x, ...
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
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