* [PATCH 3/4] Emerson KSI8560 device tree
From: Alexandr Smirnov @ 2008-03-06 15:14 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20080304162322.GA19634@ru.mvista.com>
Add device tree file for Emerson KSI8560 board.
Signed-off-by: Alexandr Smirnov <asmirnov@ru.mvista.com>
b/arch/powerpc/boot/dts/ksi8560.dts | 264 ++++++++++++++++++++++++++++++++++++
1 file changed, 264 insertions(+)
diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts
new file mode 100644
index 0000000..78d26f4
--- /dev/null
+++ b/arch/powerpc/boot/dts/ksi8560.dts
@@ -0,0 +1,264 @@
+/*
+ * Device Tree Source for Emerson KSI8560
+ *
+ * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
+ *
+ * Based on mpc8560ads.dts
+ *
+ * 2008 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ */
+
+/dts-v1/;
+
+/ {
+ model = "KSI8560";
+ compatible = "emerson,KSI8560";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8560@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>; /* L1, 32K */
+ i-cache-size = <0x8000>; /* L1, 32K */
+ timebase-frequency = <0>; /* From U-boot */
+ bus-frequency = <0>; /* From U-boot */
+ clock-frequency = <0>; /* From U-boot */
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; /* Fixed by bootwrapper */
+ };
+
+ soc@fdf00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0x00000000 0xfdf00000 0x00100000>;
+ bus-frequency = <0>; /* Fixed by bootwrapper */
+
+ memory-controller@2000 {
+ compatible = "fsl,8540-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&MPIC>;
+ interrupts = <0x12 0x2>;
+ };
+
+ l2-cache-controller@20000 {
+ compatible = "fsl,8540-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <0x20>; /* 32 bytes */
+ cache-size = <0x40000>; /* L2, 256K */
+ interrupt-parent = <&MPIC>;
+ interrupts = <0x10 0x2>;
+ };
+
+ i2c@3000 {
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <0x2b 0x2>;
+ interrupt-parent = <&MPIC>;
+ dfsrr;
+ };
+
+ mdio@24520 { /* For TSECs */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+
+ PHY1: ethernet-phy@1 {
+ interrupt-parent = <&MPIC>;
+ reg = <0x1>;
+ device_type = "ethernet-phy";
+ };
+
+ PHY2: ethernet-phy@2 {
+ interrupt-parent = <&MPIC>;
+ reg = <0x2>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet0: ethernet@24000 {
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ /* Mac address filled in by bootwrapper */
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
+ interrupt-parent = <&MPIC>;
+ phy-handle = <&PHY1>;
+ };
+
+ enet1: ethernet@25000 {
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ /* Mac address filled in by bootwrapper */
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
+ interrupt-parent = <&MPIC>;
+ phy-handle = <&PHY2>;
+ };
+
+ MPIC: pic@40000 {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x40000 0x40000>;
+ device_type = "open-pic";
+ };
+
+ cpm@919c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
+ reg = <0x919c0 0x30>;
+ ranges;
+
+ muram@80000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x80000 0x10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0x0 0x4000 0x9000 0x2000>;
+ };
+ };
+
+ brg@919f0 {
+ compatible = "fsl,mpc8560-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <0x919f0 0x10 0x915f0 0x10>;
+ clock-frequency = <165000000>; /* 166MHz */
+ };
+
+ CPMPIC: pic@90c00 {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <0x2e 0x2>;
+ interrupt-parent = <&MPIC>;
+ reg = <0x90c00 0x80>;
+ compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
+ };
+
+ serial@91a00 {
+ device_type = "serial";
+ compatible = "fsl,mpc8560-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <0x91a00 0x20 0x88000 0x100>;
+ fsl,cpm-brg = <1>;
+ fsl,cpm-command = <0x800000>;
+ current-speed = <0x1c200>;
+ interrupts = <0x28 0x8>;
+ interrupt-parent = <&CPMPIC>;
+ };
+
+ serial@91a20 {
+ device_type = "serial";
+ compatible = "fsl,mpc8560-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <0x91a20 0x20 0x88100 0x100>;
+ fsl,cpm-brg = <2>;
+ fsl,cpm-command = <0x4a00000>;
+ current-speed = <0x1c200>;
+ interrupts = <0x29 0x8>;
+ interrupt-parent = <&CPMPIC>;
+ };
+
+ mdio@90d00 { /* For FCCs */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,cpm2-mdio-bitbang";
+ reg = <0x90d00 0x14>;
+ fsl,mdio-pin = <24>;
+ fsl,mdc-pin = <25>;
+
+ PHY0: ethernet-phy@0 {
+ interrupt-parent = <&MPIC>;
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ enet2: ethernet@91300 {
+ device_type = "network";
+ compatible = "fsl,mpc8560-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <0x91300 0x20 0x88400 0x100 0x91390 0x1>;
+ /* Mac address filled in by bootwrapper */
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ fsl,cpm-command = <0x12000300>;
+ interrupts = <0x20 0x8>;
+ interrupt-parent = <&CPMPIC>;
+ phy-handle = <&PHY0>;
+ };
+ };
+ };
+
+ localbus@fdf05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8560-localbus";
+ reg = <0xfdf05000 0x68>;
+
+ ranges = <0x0 0x0 0xe0000000 0x00800000
+ 0x4 0x0 0xe8080000 0x00080000>;
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec-flash";
+ reg = <0x0 0x0 0x800000>;
+ bank-width = <0x2>;
+
+ partition@0 {
+ label = "Primary Kernel";
+ reg = <0x0 0x180000>;
+ };
+ partition@180000 {
+ label = "Primary Filesystem";
+ reg = <0x180000 0x580000>;
+ };
+ partition@700000 {
+ label = "Monitor";
+ reg = <0x300000 0x100000>;
+ read-only;
+ };
+ };
+
+ cpld@4,0 {
+ compatible = "emerson,KSI8560-cpld";
+ reg = <0x4 0x0 0x80000>;
+ };
+ };
+
+
+ chosen {
+ linux,stdout-path = "/soc/cpm/serial@91a00";
+ };
+};
^ permalink raw reply related
* [PATCH] PowerPC 4xx: Use dcri_clrset() for PCIe indirect dcr read/modify/write access
From: Valentine Barshak @ 2008-03-06 14:34 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <47CFFAD0.9060609@ru.mvista.com>
Use dcri_clrset() for PCIe SDR0 read/modify/write access.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
arch/powerpc/sysdev/ppc4xx_pci.c | 13 +++++--------
1 files changed, 5 insertions(+), 8 deletions(-)
diff -pruN linux-2.6.orig/arch/powerpc/sysdev/ppc4xx_pci.c linux-2.6/arch/powerpc/sysdev/ppc4xx_pci.c
--- linux-2.6.orig/arch/powerpc/sysdev/ppc4xx_pci.c 2008-03-06 14:39:46.000000000 +0300
+++ linux-2.6/arch/powerpc/sysdev/ppc4xx_pci.c 2008-03-06 17:20:16.000000000 +0300
@@ -645,7 +645,7 @@ static int __init ppc440spe_pciex_core_i
int time_out = 20;
/* Set PLL clock receiver to LVPECL */
- mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28);
+ dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
/* Shouldn't we do all the calibration stuff etc... here ? */
if (ppc440spe_pciex_check_reset(np))
@@ -659,8 +659,7 @@ static int __init ppc440spe_pciex_core_i
}
/* De-assert reset of PCIe PLL, wait for lock */
- mtdcri(SDR0, PESDR0_PLLLCT1,
- mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
+ dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
udelay(3);
while (time_out) {
@@ -712,9 +711,8 @@ static int ppc440spe_pciex_init_port_hw(
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
0x35000000);
}
- val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET);
- mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
- (val & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
+ (1 << 24) | (1 << 16), 1 << 12);
return 0;
}
@@ -1042,8 +1040,7 @@ static int __init ppc4xx_pciex_port_init
port->link = 0;
}
- mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
- mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
+ dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
msleep(100);
return 0;
^ permalink raw reply
* Realtime ethernet
From: Mehlan, Markus (Ritter Elektronik) @ 2008-03-06 14:48 UTC (permalink / raw)
To: Linuxppc-dev
In-Reply-To: <74F2472D-65F2-422B-821B-554EC81A3494@kernel.crashing.org>
Hello,
who knows a solution for realtime ethernet with
an actual kernel (> 2.6.23)?
Best regards,
Markus=20
^ permalink raw reply
* Re: [PATCH] PowerPC 4xx: Use dcri_clrset() for PCIe indirect dcr read/modify/write access
From: Valentine Barshak @ 2008-03-06 14:08 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20080306133751.GA31690@ru.mvista.com>
Oops, sorry, please discard this one.
There's a typo in it. The fixed patch is coming right away.
Thanks.
Valentine.
Valentine Barshak wrote:
> Use dcri_clrset() for PCIe SDR0 read/modify/write access.
>
> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
> ---
> arch/powerpc/sysdev/ppc4xx_pci.c | 11 ++++-------
> 1 files changed, 4 insertions(+), 7 deletions(-)
>
> diff -pruN linux-2.6.orig/arch/powerpc/sysdev/ppc4xx_pci.c linux-2.6/arch/powerpc/sysdev/ppc4xx_pci.c
> --- linux-2.6.orig/arch/powerpc/sysdev/ppc4xx_pci.c 2008-03-06 14:39:46.000000000 +0300
> +++ linux-2.6/arch/powerpc/sysdev/ppc4xx_pci.c 2008-03-06 14:52:02.000000000 +0300
> @@ -645,7 +645,7 @@ static int __init ppc440spe_pciex_core_i
> int time_out = 20;
>
> /* Set PLL clock receiver to LVPECL */
> - mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28);
> + dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
>
> /* Shouldn't we do all the calibration stuff etc... here ? */
> if (ppc440spe_pciex_check_reset(np))
> @@ -659,8 +659,7 @@ static int __init ppc440spe_pciex_core_i
> }
>
> /* De-assert reset of PCIe PLL, wait for lock */
> - mtdcri(SDR0, PESDR0_PLLLCT1,
> - mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
> + dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
> udelay(3);
>
> while (time_out) {
> @@ -712,9 +711,8 @@ static int ppc440spe_pciex_init_port_hw(
> mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
> 0x35000000);
> }
> - val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET);
> mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
> - (val & ~(1 << 24 | 1 << 16)) | 1 << 12);
> + (1 << 24) | (1 << 16), 1 << 12);
>
> return 0;
> }
> @@ -1042,8 +1040,7 @@ static int __init ppc4xx_pciex_port_init
> port->link = 0;
> }
>
> - mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
> - mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
> + dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
> msleep(100);
>
> return 0;
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* RE: TQM5200 2.6-denx SM501 voyager enabling problem.
From: Pedro Luis D. L. @ 2008-03-06 14:09 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <BLU106-W293FED7524135F0A85B76BCA1B0@phx.gbl>
I wrote: (:-p)
>=20
>=20
> Martin Krause wrote:
>=20
>=20
>> Hi Pedro,
>>=20
>> Pedro Luis D. L. hotmail.com> writes:
>>> Hello,
>>> I'm working right now with a TQM5200 microcontroller on a STX5200 board=
.
>>> I'm having problems to enable SM501 video output using 2.6-denx kernel.=
The=20
>>=20
>> Have you tried to contact TQ-Components (the manufacturer of the TQM5200=
=20
>> board)? Under the email address support@tqc.de you should get help for
>> hardware and software questions to all of their products.
>>=20
>> Regards,
>> Martin
>=20
> Hi Martin,
>=20
> Well, that sounds like a very reasonable suggestion. I think I should giv=
e it a try. Maybe my bad experience with other providers pushed me to ask i=
n this list before. But you're right!
>=20
> Regards,
> Pedro.
> =20
>=20
I tried to contact TQ but they seem not to be able to solve my problem. The=
y suggested that the problem could be in the different endianness used by M=
PC5200 and SMI501. That problem seems to be corrected in the driver. Anyway=
, this endianness problem may come to light if I had any video output. It i=
s possible to change the endianness of SM501 chip from the u-boot writing a=
register. I did it and it made no difference at all. The real problem is s=
till that none device is initialized or detected even when the Framebuffer =
driver for SM501 and MFD Driver for SM501 are compiled with the kernel. I c=
hecked that platform driver for both are registered (using some printk outp=
ut) but their probe functions are never invoked.
I thought that my problem could be that I don't have initialized the device=
within the platform file tqm5200.c. I added the following code (marked wit=
h +) to this file under arch/powerpc/platforms/52xx/tqm5200.c
+static struct resource sm501_resources[] =3D {
+ [0] =3D {
+ .start =3D 0xE3E00000,
+ .end =3D 0xE3DFFFFF,
+ .flags =3D IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device sm501_device =3D {
+ .name =3D "sm501",
+ .id =3D 0,
+ .num_resources =3D ARRAY_SIZE(sm501_resources),
+ .resource =3D sm501_resources,
+};
static void __init tqm5200_setup_arch(void)
{
if (ppc_md.progress)
ppc_md.progress("tqm5200_setup_arch()", 0);
/* Some mpc5200 & mpc5200b related configuration */
mpc5200_setup_xlb_arbiter();
/* Map wdt for mpc52xx_restart() */
mpc52xx_map_wdt();
#ifdef CONFIG_PCI
np =3D of_find_node_by_type(NULL, "pci");
if (np) {
mpc52xx_add_bridge(np);
of_node_put(np);
}
#endif
+
+ platform_device_register(&sm501_device);
+
}
I got this idea from the configuration files from other platforms, but I st=
ill need to find out how exactly "resources" must be defined. Anybody knows=
wheather am I pointing in the right direction and this makes any sense?
As far as I understand now (and I may be terribly wrong), once that SM501 M=
FD and Framebuffer drivers are registered, I need to tell the kernel where=
to find the device in the local bus. Is it right?
Thanks in advance,
Pedro.
_________________________________________________________________
Tecnolog=EDa, moda, motor, viajes,=85suscr=EDbete a nuestros boletines para=
estar siempre a la =FAltima
Guapos y guapas, clips musicales y estrenos de cine. =
^ permalink raw reply
* Re: [PATCH] The MPC83xx family doesn't support performance monitor instructions
From: Kumar Gala @ 2008-03-06 14:07 UTC (permalink / raw)
To: Gerald Van Baren; +Cc: linuxppc-dev
In-Reply-To: <20080306003316.GA14068@cideas.com>
On Mar 5, 2008, at 6:33 PM, Gerald Van Baren wrote:
> "Errata to MPC8349EA PowerQUICC[tm] II Pro Integrated Host Processor
> Family
> Reference Manual, Rev. 1" (Freescale)
>
> Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
> ---
>
> Hi Kumar,
>
> Please apply this fix to 2.6.25rc4 if possible. Without this
> patch, the PPC_83xx family configuration is broken (will not compile).
What's the compile issue? Some of the 83xx family have perf mon so we
need to fix the compile issue.
- k
^ permalink raw reply
* [PATCH] PowerPC 4xx: Use dcri_clrset() for PCIe indirect dcr read/modify/write access
From: Valentine Barshak @ 2008-03-06 13:37 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1204804237.21545.257.camel@pasglop>
Use dcri_clrset() for PCIe SDR0 read/modify/write access.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
arch/powerpc/sysdev/ppc4xx_pci.c | 11 ++++-------
1 files changed, 4 insertions(+), 7 deletions(-)
diff -pruN linux-2.6.orig/arch/powerpc/sysdev/ppc4xx_pci.c linux-2.6/arch/powerpc/sysdev/ppc4xx_pci.c
--- linux-2.6.orig/arch/powerpc/sysdev/ppc4xx_pci.c 2008-03-06 14:39:46.000000000 +0300
+++ linux-2.6/arch/powerpc/sysdev/ppc4xx_pci.c 2008-03-06 14:52:02.000000000 +0300
@@ -645,7 +645,7 @@ static int __init ppc440spe_pciex_core_i
int time_out = 20;
/* Set PLL clock receiver to LVPECL */
- mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28);
+ dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
/* Shouldn't we do all the calibration stuff etc... here ? */
if (ppc440spe_pciex_check_reset(np))
@@ -659,8 +659,7 @@ static int __init ppc440spe_pciex_core_i
}
/* De-assert reset of PCIe PLL, wait for lock */
- mtdcri(SDR0, PESDR0_PLLLCT1,
- mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
+ dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
udelay(3);
while (time_out) {
@@ -712,9 +711,8 @@ static int ppc440spe_pciex_init_port_hw(
mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
0x35000000);
}
- val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET);
mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
- (val & ~(1 << 24 | 1 << 16)) | 1 << 12);
+ (1 << 24) | (1 << 16), 1 << 12);
return 0;
}
@@ -1042,8 +1040,7 @@ static int __init ppc4xx_pciex_port_init
port->link = 0;
}
- mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
- mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
+ dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
msleep(100);
return 0;
^ permalink raw reply
* [PATCH 2/2] ibm_newemac: PowerPC 440EP/440GR EMAC PHY clock workaround
From: Valentine Barshak @ 2008-03-06 13:43 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1204804237.21545.257.camel@pasglop>
This patch adds ibm_newemac PHY clock workaround for 440EP/440GR EMAC
attached to a PHY which doesn't generate RX clock if there is no link.
The code is based on the previous ibm_emac driver stuff. The 440EP/440GR
allows controlling each EMAC clock separately as opposed to global clock
selection for 440GX.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
drivers/net/ibm_newemac/core.c | 34 ++++++++++++++++++++++++++++++++--
drivers/net/ibm_newemac/core.h | 6 +++++-
2 files changed, 37 insertions(+), 3 deletions(-)
diff -pruN linux-2.6.orig/drivers/net/ibm_newemac/core.c linux-2.6/drivers/net/ibm_newemac/core.c
--- linux-2.6.orig/drivers/net/ibm_newemac/core.c 2008-02-26 16:32:33.000000000 +0300
+++ linux-2.6/drivers/net/ibm_newemac/core.c 2008-02-26 16:37:52.000000000 +0300
@@ -129,10 +129,29 @@ static struct device_node *emac_boot_lis
static inline void emac_report_timeout_error(struct emac_instance *dev,
const char *error)
{
- if (net_ratelimit())
+ if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
+ EMAC_FTR_440EP_PHY_CLK_FIX))
+ DBG(dev, "%s" NL, error);
+ else if (net_ratelimit())
printk(KERN_ERR "%s: %s\n", dev->ndev->name, error);
}
+/* EMAC PHY clock workaround:
+ * 440EP/440GR has more sane SDR0_MFR register implementation than 440GX,
+ * which allows controlling each EMAC clock
+ */
+static inline void emac_rx_clk_tx(struct emac_instance *dev)
+{
+ if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
+ dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS >> dev->cell_index);
+}
+
+static inline void emac_rx_clk_default(struct emac_instance *dev)
+{
+ if (emac_has_feature(dev, EMAC_FTR_440EP_PHY_CLK_FIX))
+ dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS >> dev->cell_index, 0);
+}
+
/* PHY polling intervals */
#define PHY_POLL_LINK_ON HZ
#define PHY_POLL_LINK_OFF (HZ / 5)
@@ -1089,9 +1112,11 @@ static int emac_open(struct net_device *
int link_poll_interval;
if (dev->phy.def->ops->poll_link(&dev->phy)) {
dev->phy.def->ops->read_link(&dev->phy);
+ emac_rx_clk_default(dev);
netif_carrier_on(dev->ndev);
link_poll_interval = PHY_POLL_LINK_ON;
} else {
+ emac_rx_clk_tx(dev);
netif_carrier_off(dev->ndev);
link_poll_interval = PHY_POLL_LINK_OFF;
}
@@ -1169,6 +1194,7 @@ static void emac_link_timer(struct work_
if (dev->phy.def->ops->poll_link(&dev->phy)) {
if (!netif_carrier_ok(dev->ndev)) {
+ emac_rx_clk_default(dev);
/* Get new link parameters */
dev->phy.def->ops->read_link(&dev->phy);
@@ -1181,6 +1207,7 @@ static void emac_link_timer(struct work_
link_poll_interval = PHY_POLL_LINK_ON;
} else {
if (netif_carrier_ok(dev->ndev)) {
+ emac_rx_clk_tx(dev);
netif_carrier_off(dev->ndev);
netif_tx_disable(dev->ndev);
emac_reinitialize(dev);
@@ -2325,9 +2352,12 @@ static int __devinit emac_init_phy(struc
dev->phy.mdio_read = emac_mdio_read;
dev->phy.mdio_write = emac_mdio_write;
- /* Enable internal clock source */
+ /* EMAC PHY clock workaround */
if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
+ /* Enable internal clock source */
dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
+ else
+ emac_rx_clk_tx(dev);
/* Configure EMAC with defaults so we can at least use MDIO
* This is needed mostly for 440GX
@@ -2495,6 +2525,10 @@ static int __devinit emac_init_config(st
dev->features |= EMAC_FTR_EMAC4;
if (of_device_is_compatible(np, "ibm,emac-440gx"))
dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
+ } else {
+ if (of_device_is_compatible(np, "ibm,emac-440ep") ||
+ of_device_is_compatible(np, "ibm,emac-440gr"))
+ dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
}
/* Fixup some feature bits based on the device tree */
diff -pruN linux-2.6.orig/drivers/net/ibm_newemac/core.h linux-2.6/drivers/net/ibm_newemac/core.h
--- linux-2.6.orig/drivers/net/ibm_newemac/core.h 2008-02-26 16:32:33.000000000 +0300
+++ linux-2.6/drivers/net/ibm_newemac/core.h 2008-02-26 16:37:52.000000000 +0300
@@ -305,6 +305,10 @@ struct emac_instance {
* Set if we need phy clock workaround for 440gx
*/
#define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080
+/*
+ * Set if we need phy clock workaround for 440ep or 440gr
+ */
+#define EMAC_FTR_440EP_PHY_CLK_FIX 0x00000100
/* Right now, we don't quite handle the always/possible masks on the
@@ -328,7 +332,7 @@ enum {
#ifdef CONFIG_IBM_NEW_EMAC_RGMII
EMAC_FTR_HAS_RGMII |
#endif
- 0,
+ EMAC_FTR_440EP_PHY_CLK_FIX,
};
static inline int emac_has_feature(struct emac_instance *dev,
^ permalink raw reply
* [PATCH 1/2] ibm_newemac: PowerPC 440GX EMAC PHY clock workaround
From: Valentine Barshak @ 2008-03-06 13:41 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1204804237.21545.257.camel@pasglop>
The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout error)
if there's no link. Because of that it fails to find PHY chip. The older ibm_emac
driver had a workaround for that: the EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros,
which toggle the Ethernet Clock Select bit in the SDR0_MFR register. This patch
does the same for "ibm,emac-440gx" compatible chips. The workaround forces
clock on -all- EMACs, so we select clock under global emac_phy_map_lock.
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
---
drivers/net/ibm_newemac/core.c | 16 +++++++++++++++-
drivers/net/ibm_newemac/core.h | 8 ++++++--
2 files changed, 21 insertions(+), 3 deletions(-)
diff -pruN linux-2.6.orig/drivers/net/ibm_newemac/core.c linux-2.6/drivers/net/ibm_newemac/core.c
--- linux-2.6.orig/drivers/net/ibm_newemac/core.c 2008-02-22 19:56:26.000000000 +0300
+++ linux-2.6/drivers/net/ibm_newemac/core.c 2008-02-22 20:38:47.000000000 +0300
@@ -43,6 +43,8 @@
#include <asm/io.h>
#include <asm/dma.h>
#include <asm/uaccess.h>
+#include <asm/dcr.h>
+#include <asm/dcr-regs.h>
#include "core.h"
@@ -2323,6 +2325,10 @@ static int __devinit emac_init_phy(struc
dev->phy.mdio_read = emac_mdio_read;
dev->phy.mdio_write = emac_mdio_write;
+ /* Enable internal clock source */
+ if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
+ dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
+
/* Configure EMAC with defaults so we can at least use MDIO
* This is needed mostly for 440GX
*/
@@ -2355,6 +2361,11 @@ static int __devinit emac_init_phy(struc
if (!emac_mii_phy_probe(&dev->phy, i))
break;
}
+
+ /* Enable external clock source */
+ if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
+ dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
+
mutex_unlock(&emac_phy_map_lock);
if (i == 0x20) {
printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
@@ -2480,8 +2491,11 @@ static int __devinit emac_init_config(st
}
/* Check EMAC version */
- if (of_device_is_compatible(np, "ibm,emac4"))
+ if (of_device_is_compatible(np, "ibm,emac4")) {
dev->features |= EMAC_FTR_EMAC4;
+ if (of_device_is_compatible(np, "ibm,emac-440gx"))
+ dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
+ }
/* Fixup some feature bits based on the device tree */
if (of_get_property(np, "has-inverted-stacr-oc", NULL))
diff -pruN linux-2.6.orig/drivers/net/ibm_newemac/core.h linux-2.6/drivers/net/ibm_newemac/core.h
--- linux-2.6.orig/drivers/net/ibm_newemac/core.h 2008-02-21 16:45:36.000000000 +0300
+++ linux-2.6/drivers/net/ibm_newemac/core.h 2008-02-22 19:57:44.000000000 +0300
@@ -301,6 +301,10 @@ struct emac_instance {
* Set if we have new type STACR with STAOPC
*/
#define EMAC_FTR_HAS_NEW_STACR 0x00000040
+/*
+ * Set if we need phy clock workaround for 440gx
+ */
+#define EMAC_FTR_440GX_PHY_CLK_FIX 0x00000080
/* Right now, we don't quite handle the always/possible masks on the
@@ -312,8 +316,8 @@ enum {
EMAC_FTRS_POSSIBLE =
#ifdef CONFIG_IBM_NEW_EMAC_EMAC4
- EMAC_FTR_EMAC4 | EMAC_FTR_HAS_NEW_STACR |
- EMAC_FTR_STACR_OC_INVERT |
+ EMAC_FTR_EMAC4 | EMAC_FTR_HAS_NEW_STACR |
+ EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
#endif
#ifdef CONFIG_IBM_NEW_EMAC_TAH
EMAC_FTR_HAS_TAH |
^ permalink raw reply
* RE: I2S driver
From: Pedro Luis D. L. @ 2008-03-06 13:41 UTC (permalink / raw)
Cc: linuxppc-embedded
In-Reply-To: <352127.99121.qm@web23109.mail.ird.yahoo.com>
Angelo wrote:
> how can i take these headers file?
>=20
>> Pedro wrote:
>> #include=20
>> #include=20
>> #include=20
>=20
> I try to download some kernel version (2.6.23 and 2.6.24) but there aren'=
t any library of bestcomm.
>=20
> Many thanks.
>=20
You can get the patches from:
http://patchwork.ozlabs.org/linuxppc/list?q=3Dbestcomm&order=3Ddate
Regards,
Pedro L.
>=20
> ________________________________
> Inviato da Yahoo! Mail.
> La web mail pi=F9 usata al mondo.
_________________________________________________________________
MSN Video.=20
http://video.msn.com/?mkt=3Des-es=
^ permalink raw reply
* Re: [PATCH] PPC: in celleb_show_cpuinfo() convert strncpy(x, y, sizeof(x)) to strlcpy
From: Roel Kluin @ 2008-03-06 13:20 UTC (permalink / raw)
To: paulus, arnd; +Cc: linuxppc-dev, lkml
In-Reply-To: <47CFEE9D.1020300@tiscali.nl>
Roel Kluin wrote:
> This patch was not yet tested. Please confirm it's right.
was too quick with the send button. the batch below is probably better
---
strncpy does not append '\0' if the length of the source string equals
the size parameter, strlcpy does.
Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
---
diff --git a/arch/powerpc/platforms/celleb/setup.c b/arch/powerpc/platforms/celleb/setup.c
index f27ae1e..cbe09d9 100644
--- a/arch/powerpc/platforms/celleb/setup.c
+++ b/arch/powerpc/platforms/celleb/setup.c
@@ -81,8 +81,7 @@ static void celleb_show_cpuinfo(struct seq_file *m)
static int __init celleb_machine_type_hack(char *ptr)
{
- strncpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
- celleb_machine_type[sizeof(celleb_machine_type)-1] = 0;
+ strlcpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
return 0;
}
^ permalink raw reply related
* [PATCH] PPC: in celleb_show_cpuinfo() convert strncpy(x, y, sizeof(x)) to strlcpy
From: Roel Kluin @ 2008-03-06 13:16 UTC (permalink / raw)
To: paulus, arnd; +Cc: linuxppc-dev, lkml
This patch was not yet tested. Please confirm it's right.
---
strncpy does not append '\0' if the length of the source string equals
the size parameter, strlcpy does.
Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
---
diff --git a/arch/powerpc/platforms/celleb/setup.c b/arch/powerpc/platforms/celleb/setup.c
index f27ae1e..d70fc53 100644
--- a/arch/powerpc/platforms/celleb/setup.c
+++ b/arch/powerpc/platforms/celleb/setup.c
@@ -81,7 +81,7 @@ static void celleb_show_cpuinfo(struct seq_file *m)
static int __init celleb_machine_type_hack(char *ptr)
{
- strncpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
+ strlcpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
celleb_machine_type[sizeof(celleb_machine_type)-1] = 0;
return 0;
}
^ permalink raw reply related
* Re: [PATCH] PowerPC 4xx: Add dcri_clrset() for locked read/modify/write functionality
From: Benjamin Herrenschmidt @ 2008-03-06 11:50 UTC (permalink / raw)
To: Valentine Barshak; +Cc: linuxppc-dev
In-Reply-To: <47CFD607.2000309@ru.mvista.com>
On Thu, 2008-03-06 at 14:31 +0300, Valentine Barshak wrote:
> Josh Boyer wrote:
> > On Thu, 06 Mar 2008 11:06:18 +1100
> > Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> >
> >> On Wed, 2008-03-05 at 21:38 +0300, Valentine Barshak wrote:
> >>> This adds dcri_clrset() macro which does read/modify/write
> >>> on indirect dcr registers while holding indirect dcr lock.
> >>>
> >>> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
> >> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >
> > Indeed, looks good. Valentine, are you going to rework your EMAC patch
> > to use this?
> >
> > josh
>
> Yes, I was going to update the pcie stuff and rework the emac patches.
The PCIe stuff is less of an issue as it happens early during boot,
there should be no race there, but it's still a good idea in the long
run. The EMAC bits look more like that kind of stuff we should have
ready asap for linux-next.
Cheers,
Ben.
^ permalink raw reply
* [POWERPC] 8xx: fix swap
From: Vitaly Bordug @ 2008-03-06 10:53 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, LKML
This makes swap routines operate correctly on the ppc_8xx based machines.
Code has been revalidated on mpc885ads (8M sdram) with recent kernel. Based
on patch from Yuri Tikhonov <yur@emcraft.com> to do the same on arch/ppc
instance.
Recent kernel's size makes swap feature very important on low-memory platforms,
those are actually non-operable without it.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
---
arch/powerpc/kernel/head_8xx.S | 30 +++++++++++++++++++++++++++++-
include/asm-powerpc/pgtable-ppc32.h | 8 --------
2 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index f745839..3c9452d 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -332,8 +332,18 @@ InstructionTLBMiss:
mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
lwz r10, 0(r11) /* Get the pte */
+#ifdef CONFIG_SWAP
+ /* do not set the _PAGE_ACCESSED bit of a non-present page */
+ andi. r11, r10, _PAGE_PRESENT
+ beq 4f
+ ori r10, r10, _PAGE_ACCESSED
+ mfspr r11, SPRN_MD_TWC /* get the pte address again */
+ stw r10, 0(r11)
+4:
+#else
ori r10, r10, _PAGE_ACCESSED
stw r10, 0(r11)
+#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 21, 22 and 28 must be clear.
@@ -398,8 +408,17 @@ DataStoreTLBMiss:
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11
- mfspr r11, SPRN_MD_TWC /* get the pte address again */
+#ifdef CONFIG_SWAP
+ /* do not set the _PAGE_ACCESSED bit of a non-present page */
+ andi. r11, r10, _PAGE_PRESENT
+ beq 4f
ori r10, r10, _PAGE_ACCESSED
+4:
+ /* and update pte in table */
+#else
+ ori r10, r10, _PAGE_ACCESSED
+#endif
+ mfspr r11, SPRN_MD_TWC /* get the pte address again */
stw r10, 0(r11)
/* The Linux PTE won't go exactly into the MMU TLB.
@@ -507,7 +526,16 @@ DataTLBError:
/* Update 'changed', among others.
*/
+#ifdef CONFIG_SWAP
+ ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
+ /* do not set the _PAGE_ACCESSED bit of a non-present page */
+ andi. r11, r10, _PAGE_PRESENT
+ beq 4f
+ ori r10, r10, _PAGE_ACCESSED
+4:
+#else
ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
+#endif
mfspr r11, SPRN_MD_TWC /* Get pte address again */
stw r10, 0(r11) /* and update pte in table */
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index d1332bb..2c79f55 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -339,14 +339,6 @@ extern int icache_44x_need_flush;
#define _PMD_PAGE_MASK 0x000c
#define _PMD_PAGE_8M 0x000c
-/*
- * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
- * for an address even if _PAGE_PRESENT is not set, as a performance
- * optimization. This is a bug if you ever want to use swap unless
- * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
- * definitions for __swp_entry etc. below, which would be gross.
- * -- paulus
- */
#define _PTE_NONE_MASK _PAGE_ACCESSED
#else /* CONFIG_6xx */
--
Sincerely,
Vitaly
^ permalink raw reply related
* [PATCH 1/2] fix wrong USB phy type in mpc837xmds dts
From: Li Yang @ 2008-03-06 10:42 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev, Li Yang, paulus
Due to chip constraint MPC837x USB DR module can only use
ULPI and serial PHY interfaces. The patch fixes the wrong
type in dts.
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/mpc8377_mds.dts | 4 ++--
arch/powerpc/boot/dts/mpc8378_mds.dts | 4 ++--
arch/powerpc/boot/dts/mpc8379_mds.dts | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index a3637ff..677a061 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -91,7 +91,6 @@
mode = "cpu";
};
- /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
@@ -99,7 +98,8 @@
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
- phy_type = "utmi_wide";
+ dr_mode = "host";
+ phy_type = "ulpi";
};
mdio@24520 {
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 533e9b0..3f9e9fe 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -91,7 +91,6 @@
mode = "cpu";
};
- /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
@@ -99,7 +98,8 @@
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
- phy_type = "utmi_wide";
+ dr_mode = "host";
+ phy_type = "ulpi";
};
mdio@24520 {
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index c270685..36c1c13 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -91,7 +91,6 @@
mode = "cpu";
};
- /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
@@ -99,7 +98,8 @@
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
- phy_type = "utmi_wide";
+ dr_mode = "host";
+ phy_type = "ulpi";
};
mdio@24520 {
--
1.5.4.rc4
^ permalink raw reply related
* Re: [PATCH] PowerPC 4xx: Add dcri_clrset() for locked read/modify/write functionality
From: Valentine Barshak @ 2008-03-06 11:31 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20080305191216.5089f696@zod.rchland.ibm.com>
Josh Boyer wrote:
> On Thu, 06 Mar 2008 11:06:18 +1100
> Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
>> On Wed, 2008-03-05 at 21:38 +0300, Valentine Barshak wrote:
>>> This adds dcri_clrset() macro which does read/modify/write
>>> on indirect dcr registers while holding indirect dcr lock.
>>>
>>> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
>> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Indeed, looks good. Valentine, are you going to rework your EMAC patch
> to use this?
>
> josh
Yes, I was going to update the pcie stuff and rework the emac patches.
Thanks,
Valentine.
^ permalink raw reply
* [PATCH 2/2] Add local bus device nodes to MPC837xMDS device trees.
From: Li Yang @ 2008-03-06 10:42 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev, Li Yang, paulus
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/mpc8377_mds.dts | 66 +++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8378_mds.dts | 66 +++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8379_mds.dts | 66 +++++++++++++++++++++++++++++
arch/powerpc/platforms/83xx/mpc837x_mds.c | 8 +--
4 files changed, 201 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 677a061..3aac8b7 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -47,6 +47,72 @@
reg = <0x00000000 0x20000000>; // 512MB at 0
};
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+
+ // booting from NOR flash
+ ranges = <0 0x0 0xfe000000 0x02000000
+ 1 0x0 0xf8000000 0x00008000
+ 3 0x0 0xe0600000 0x00008000>;
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0 0x0 0x2000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ fs@100000 {
+ reg = <0x100000 0x800000>;
+ };
+
+ kernel@1d00000 {
+ reg = <0x1d00000 0x200000>;
+ };
+
+ dtb@1f00000 {
+ reg = <0x1f00000 0x100000>;
+ };
+ };
+
+ bcsr@1,0 {
+ reg = <1 0x0 0x8000>;
+ compatible = "fsl,mpc837xmds-bcsr";
+ };
+
+ nand@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8377-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <3 0x0 0x8000>;
+
+ u-boot@0 {
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ kernel@100000 {
+ reg = <0x100000 0x300000>;
+ };
+
+ fs@400000 {
+ reg = <0x400000 0x1c00000>;
+ };
+ };
+ };
+
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 3f9e9fe..2496e19 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -47,6 +47,72 @@
reg = <0x00000000 0x20000000>; // 512MB at 0
};
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+
+ // booting from NOR flash
+ ranges = <0 0x0 0xfe000000 0x02000000
+ 1 0x0 0xf8000000 0x00008000
+ 3 0x0 0xe0600000 0x00008000>;
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0 0x0 0x2000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ fs@100000 {
+ reg = <0x100000 0x800000>;
+ };
+
+ kernel@1d00000 {
+ reg = <0x1d00000 0x200000>;
+ };
+
+ dtb@1f00000 {
+ reg = <0x1f00000 0x100000>;
+ };
+ };
+
+ bcsr@1,0 {
+ reg = <1 0x0 0x8000>;
+ compatible = "fsl,mpc837xmds-bcsr";
+ };
+
+ nand@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8378-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <3 0x0 0x8000>;
+
+ u-boot@0 {
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ kernel@100000 {
+ reg = <0x100000 0x300000>;
+ };
+
+ fs@400000 {
+ reg = <0x400000 0x1c00000>;
+ };
+ };
+ };
+
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index 36c1c13..5ae4644 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -47,6 +47,72 @@
reg = <0x00000000 0x20000000>; // 512MB at 0
};
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <77 0x8>;
+ interrupt-parent = <&ipic>;
+
+ // booting from NOR flash
+ ranges = <0 0x0 0xfe000000 0x02000000
+ 1 0x0 0xf8000000 0x00008000
+ 3 0x0 0xe0600000 0x00008000>;
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0 0x0 0x2000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ u-boot@0 {
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ fs@100000 {
+ reg = <0x100000 0x800000>;
+ };
+
+ kernel@1d00000 {
+ reg = <0x1d00000 0x200000>;
+ };
+
+ dtb@1f00000 {
+ reg = <0x1f00000 0x100000>;
+ };
+ };
+
+ bcsr@1,0 {
+ reg = <1 0x0 0x8000>;
+ compatible = "fsl,mpc837xmds-bcsr";
+ };
+
+ nand@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8379-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <3 0x0 0x8000>;
+
+ u-boot@0 {
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ kernel@100000 {
+ reg = <0x100000 0x300000>;
+ };
+
+ fs@400000 {
+ reg = <0x400000 0x1c00000>;
+ };
+ };
+ };
+
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index 8a9c269..1f4b7e8 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -39,12 +39,9 @@ static int mpc837xmds_usb_cfg(void)
if (ret)
return ret;
/* Map BCSR area */
- np = of_find_node_by_name(NULL, "bcsr");
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc837xmds-bcsr");
if (np) {
- struct resource res;
-
- of_address_to_resource(np, 0, &res);
- bcsr_regs = ioremap(res.start, res.end - res.start + 1);
+ bcsr_regs = of_iomap(np, 0);
of_node_put(np);
}
if (!bcsr_regs)
@@ -96,6 +93,7 @@ static void __init mpc837x_mds_setup_arch(void)
static struct of_device_id mpc837x_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
+ { .compatible = "simple-bus", },
{},
};
--
1.5.4.rc4
^ permalink raw reply related
* RE: I2S driver
From: Angelo @ 2008-03-06 10:27 UTC (permalink / raw)
To: Pedro Luis D. L.; +Cc: linuxppc-embedded
In-Reply-To: <BLU106-W10231BF41CAF09DAD5DBC0CA110@phx.gbl>
[-- Attachment #1: Type: text/plain, Size: 393 bytes --]
how can i take these headers file?
> Pedro wrote:
> #include <sysdev/bestcomm/bestcomm.h>
> #include <sysdev/bestcomm/gen_bd.h>
> #include <sysdev/bestcomm/bestcomm_priv.h>
I try to download some kernel version (2.6.23 and 2.6.24) but there aren't any library of bestcomm.
Many thanks.
---------------------------------
Inviato da Yahoo! Mail.
La web mail più usata al mondo.
[-- Attachment #2: Type: text/html, Size: 751 bytes --]
^ permalink raw reply
* How to boot kernel in JTAG mode
From: learn linux @ 2008-03-06 10:20 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: Heydeck
[-- Attachment #1: Type: text/plain, Size: 241 bytes --]
Hi,
I am new to this linux and jtag. I want to set up the my board in jtag
mode so that I could boot the kernel in jtag mode and try to debug the
kernel.
I need a general information how to set it up.
Thanks in advance,
Sudeep.
[-- Attachment #2: Type: text/html, Size: 321 bytes --]
^ permalink raw reply
* RAW Sockets - HDLC or Ethernet
From: Russell McGuire @ 2008-03-06 9:24 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1562 bytes --]
Anyone,
Yet another mysterious question, at least to me.
I have written to simple utilities to send and receive a file / data through
a newly created driver, HDLC using an MPC8360E.
Though I doubt this question is limited to that specific HW.
The main question is that everything I send though device HDLC0 I can
immediately read from HDLC0 even though logically there is no connection
there. It as if the kernel is immediately allowing me to read from the same
device, what a separate application just wrote.???
HOW CAN THIS BE?
Details:
I have two applications: send and receive. (pseudo code as follows)
Send opens a socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL)).
And binds it (AF_PACKET, ETH_P_HLDC, if_index(hdlc0))
Receive opens a socket to the same device
socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL))
bind(AF_PACKET, ETH_P_ALL, if_index(hdlc0)
Note they are opening the same device.
Now if I send anything through the send application, I immediately receive
it via the receive application??
Note, entirely separate processes!
Note, there is NO hardware loopback, this should be a dead end, and I should
get nothing back at least as far as HW is concerned.
What am I missing, that causes all my TX data to show up immediately in the
RX app? Note I have verified my HDLC drier is not actually receiving
anything, so is there something in the kernel that is bridging the TX / RX
paths, or am I just missing the function of this? If so how can I use RAW
mode, while not mixing this, or at least keeping them separate in the
applications?
-Russ
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^ permalink raw reply
* dtc: Abolish asize field of struct data
From: David Gibson @ 2008-03-06 4:48 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
The asize field in struct data is a hangover from the early days when
a struct data was sometimes allowed to refer to a static chunk of
memory rather than a malloc()ed block.
That's long gone, since the lifetime issues were far more trouble than
it was worth, so get rid of the asize field.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Index: dtc/dtc.h
===================================================================
--- dtc.orig/dtc.h 2008-03-06 15:43:56.000000000 +1100
+++ dtc/dtc.h 2008-03-06 15:44:06.000000000 +1100
@@ -118,7 +118,6 @@
struct data {
int len;
char *val;
- int asize;
struct marker *markers;
};
Index: dtc/data.c
===================================================================
--- dtc.orig/data.c 2008-03-06 15:44:27.000000000 +1100
+++ dtc/data.c 2008-03-06 15:45:01.000000000 +1100
@@ -32,8 +32,6 @@
m = nm;
}
- assert(!d.val || d.asize);
-
if (d.val)
free(d.val);
}
@@ -43,9 +41,6 @@
struct data nd;
int newsize;
- /* we must start with an allocated datum */
- assert(!d.val || d.asize);
-
if (xlen == 0)
return d;
@@ -56,11 +51,8 @@
while ((d.len + xlen) > newsize)
newsize *= 2;
- nd.asize = newsize;
nd.val = xrealloc(d.val, newsize);
- assert(nd.asize >= (d.len + xlen));
-
return nd;
}
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* RE: [PATCH] math-emu: delete PowerPC old math-emu headers
From: Liu Yu @ 2008-03-06 3:05 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1204713892.21545.199.camel@pasglop>
>=20
> On Wed, 2008-03-05 at 17:02 +0800, Liu Yu wrote:
> > Use common headers as a replacement.
> > The Common headers are located in "include/math-emu/", they=20
> are used=20
> > by multiple platforms such as s390, sparc, alpha.
> >=20
> > As the common headers have more developers, they are more=20
> popular and=20
> > more stable.
> >=20
> > In fact, PowerPC old math-emu headers cannot handle float point=20
> > exceptions exactly while the common headers can.
>=20
> That sounds like an excellent idea. However, were you able to=20
> run some kind of test suite to verify that the emulation=20
> works properly ?
>=20
Not yet, for I don't have the right environment. :-(
We have a patch to handle MPC85xx SPE.
The patch is not yet a part of kernel and used to adopt PowerPC math-emu
headers=20
like current math-emu for PowerPC FP does.=20
When we ran TestFloat which is a famous FP test suite to test the SPE
patch,
it reported numerous errors and most of them concerned wrong FP
exception flags.
After we change the SPE patch to the common math-emu headers, the result
of TestFloat are splendid.
So I think the same change should be done on current PowerPC FP
math-emu.
^ permalink raw reply
* dtc: Remove ugly include stack abuse
From: David Gibson @ 2008-03-06 1:45 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
Currently, dt_from_source() uses push_input_file() to set up the
initial input file for the lexer. That sounds sensible - put the
outermost input file at the bottom of the stack - until you realise
that what it *actually* does is pushes the current, uninitialized,
lexer input state onto the stack, then sets up the new lexer input.
That necessitates an extra check in pop_input_file(), rather than
signalling termination in the natural way when the include stack is
empty, it has to check when it pops the bogus uninitialized state off
the stack. Ick.
With that fixed, push_input_file(), pop_input_file() and
incl_file_stack itself become local to the lexer, so make them static.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
dtc-lexer.l | 12 ++++++------
srcpos.h | 3 ---
treesource.c | 3 ++-
3 files changed, 8 insertions(+), 10 deletions(-)
Index: dtc/treesource.c
===================================================================
--- dtc.orig/treesource.c 2008-03-05 16:14:54.000000000 +1100
+++ dtc/treesource.c 2008-03-06 12:24:49.000000000 +1100
@@ -32,7 +32,8 @@
the_boot_info = NULL;
treesource_error = 0;
- push_input_file(fname);
+ srcpos_file = dtc_open_file(fname, NULL);
+ yyin = srcpos_file->file;
if (yyparse() != 0)
return NULL;
Index: dtc/dtc-lexer.l
===================================================================
--- dtc.orig/dtc-lexer.l 2008-03-06 12:25:24.000000000 +1100
+++ dtc/dtc-lexer.l 2008-03-06 12:43:52.000000000 +1100
@@ -52,6 +52,9 @@
DPRINT("<V1>\n"); \
BEGIN(V1); \
}
+
+static void push_input_file(const char *filename);
+static int pop_input_file(void);
%}
%%
@@ -229,7 +232,7 @@
struct incl_file *prev;
};
-struct incl_file *incl_file_stack;
+static struct incl_file *incl_file_stack;
/*
@@ -240,7 +243,7 @@
static int incl_depth = 0;
-void push_input_file(const char *filename)
+static void push_input_file(const char *filename)
{
struct incl_file *incl_file;
struct dtc_file *newfile;
@@ -282,7 +285,7 @@
}
-int pop_input_file(void)
+static int pop_input_file(void)
{
struct incl_file *incl_file;
@@ -312,8 +315,5 @@
*/
free(incl_file);
- if (YY_CURRENT_BUFFER == 0)
- return 0;
-
return 1;
}
Index: dtc/srcpos.h
===================================================================
--- dtc.orig/srcpos.h 2008-03-06 12:43:23.000000000 +1100
+++ dtc/srcpos.h 2008-03-06 12:43:25.000000000 +1100
@@ -75,9 +75,6 @@
extern struct dtc_file *srcpos_file;
-extern void push_input_file(const char *filename);
-extern int pop_input_file(void);
-
struct search_path {
const char *dir; /* NULL for current directory */
struct search_path *prev, *next;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* dtc: Make dtc_open_file() die() if unable to open requested file
From: David Gibson @ 2008-03-06 1:16 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
All current callers of dtc_open_file() immediately die() if it returns
an error. In a non-interative tool like dtc, it's hard to see what
you could sensibly do to recover from a failure to open an input file
in any case.
Therefore, make dtc_open_file() itself die() if there's an error
opening the requested file. This removes the need for error checking
at the callsites, and ensures a consistent error message in all cases.
While we're at it, change the rror message from fstree.c when we fail
to open the input directory to match dtc_open_file()'s error message.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
dtc-lexer.l | 3 ---
dtc.c | 4 ----
fstree.c | 4 ++--
srcpos.c | 11 ++++-------
4 files changed, 6 insertions(+), 16 deletions(-)
Index: dtc/dtc-lexer.l
===================================================================
--- dtc.orig/dtc-lexer.l 2008-03-06 12:07:32.000000000 +1100
+++ dtc/dtc-lexer.l 2008-03-06 12:08:22.000000000 +1100
@@ -259,9 +259,6 @@
}
newfile = dtc_open_file(filename, searchptr);
- if (!newfile)
- die("Couldn't open \"%s\": %s", filename, strerror(errno));
-
incl_file = xmalloc(sizeof(struct incl_file));
Index: dtc/fstree.c
===================================================================
--- dtc.orig/fstree.c 2008-03-06 12:07:32.000000000 +1100
+++ dtc/fstree.c 2008-03-06 12:08:22.000000000 +1100
@@ -31,8 +31,8 @@
struct node *tree;
d = opendir(dirname);
- if (! d)
- die("opendir(): %s\n", strerror(errno));
+ if (!d)
+ die("Couldn't opendir() \"%s\": %s\n", dirname, strerror(errno));
tree = build_node(NULL, NULL);
Index: dtc/srcpos.c
===================================================================
--- dtc.orig/srcpos.c 2008-03-06 12:07:32.000000000 +1100
+++ dtc/srcpos.c 2008-03-06 12:08:22.000000000 +1100
@@ -82,9 +82,8 @@
if (fname[0] == '/') {
file->file = fopen(fname, "r");
-
if (!file->file)
- goto out;
+ goto fail;
file->name = strdup(fname);
return file;
@@ -98,15 +97,13 @@
return file;
if (errno != ENOENT)
- goto out;
+ goto fail;
search = search->next;
}
-out:
- free(file->dir);
- free(file);
- return NULL;
+fail:
+ die("Couldn't open \"%s\": %s\n", fname, strerror(errno));
}
void dtc_close_file(struct dtc_file *file)
Index: dtc/dtc.c
===================================================================
--- dtc.orig/dtc.c 2008-03-06 12:08:34.000000000 +1100
+++ dtc/dtc.c 2008-03-06 12:08:38.000000000 +1100
@@ -193,10 +193,6 @@
bi = dt_from_fs(arg);
} else if(streq(inform, "dtb")) {
inf = dtc_open_file(arg, NULL);
- if (!inf)
- die("Couldn't open \"%s\": %s\n", arg,
- strerror(errno));
-
bi = dt_from_blob(inf->file);
} else {
die("Unknown input format \"%s\"\n", inform);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH] PowerPC 4xx: Add dcri_clrset() for locked read/modify/write functionality
From: Josh Boyer @ 2008-03-06 1:12 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1204761978.21545.240.camel@pasglop>
On Thu, 06 Mar 2008 11:06:18 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> On Wed, 2008-03-05 at 21:38 +0300, Valentine Barshak wrote:
> > This adds dcri_clrset() macro which does read/modify/write
> > on indirect dcr registers while holding indirect dcr lock.
> >
> > Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
>
> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Indeed, looks good. Valentine, are you going to rework your EMAC patch
to use this?
josh
^ permalink raw reply
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