* Re: [PATCH 1/9] [POWERPC] mv64x60: change FDT compatible prefix to mrvl
From: Dale Farnsworth @ 2008-03-29 0:00 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, paulus
In-Reply-To: <fa686aa40803281647y4ccc4605n1507f9c1868d4c0f@mail.gmail.com>
On Fri, Mar 28, 2008 at 05:47:25PM -0600, Grant Likely wrote:
> On Fri, Mar 28, 2008 at 5:42 PM, Dale Farnsworth <dale@farnsworth.org> wrote:
> > From: Dale Farnsworth <dale@farnsworth.org>
> >
> > Follow the convention that compatible names are prefixed by the
> > vendor's stock ticker symbol. For Marvell Technology Group Ltd.,
> > that's MRVL.
> >
> > Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
> > Acked-by: Mark A. Greer <mgreer@mvista.com>
>
> Are there any boards "in the wild" using the old string? If so are
> does changing this string risk complicating upgrades to a new kernel
> version?
I don't think this complicates things much, since all these boards boot
a dtbImage, with an embedded dtb file built from the kernel source.
So the dts and code don't have much opportunity to get out of sync.
-Dale
^ permalink raw reply
* Re: [PATCH 1/9] [POWERPC] mv64x60: change FDT compatible prefix to mrvl
From: Grant Likely @ 2008-03-29 0:12 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, paulus
In-Reply-To: <20080329000047.GA31116@farnsworth.org>
On Fri, Mar 28, 2008 at 6:00 PM, Dale Farnsworth <dale@farnsworth.org> wrote:
> On Fri, Mar 28, 2008 at 05:47:25PM -0600, Grant Likely wrote:
> > On Fri, Mar 28, 2008 at 5:42 PM, Dale Farnsworth <dale@farnsworth.org> wrote:
> > > From: Dale Farnsworth <dale@farnsworth.org>
> > >
> > > Follow the convention that compatible names are prefixed by the
> > > vendor's stock ticker symbol. For Marvell Technology Group Ltd.,
> > > that's MRVL.
> > >
> > > Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
> > > Acked-by: Mark A. Greer <mgreer@mvista.com>
> >
> > Are there any boards "in the wild" using the old string? If so are
> > does changing this string risk complicating upgrades to a new kernel
> > version?
>
> I don't think this complicates things much, since all these boards boot
> a dtbImage, with an embedded dtb file built from the kernel source.
> So the dts and code don't have much opportunity to get out of sync.
Cool; then looks good to me! :-)
Acked-by: Grant Likely <grant.likely@secretlab.ca>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH] Make pasemi_mac.c depend on PPC_PASEMI to prevent link errors
From: Jeff Garzik @ 2008-03-29 1:53 UTC (permalink / raw)
To: Michael Ellerman; +Cc: Olof Johannsson, linuxppc-dev
In-Reply-To: <c9b4b088d00e37e33907b15ac59450c04ef36112.1206666963.git.michael@ellerman.id.au>
Michael Ellerman wrote:
> drivers/net/pasemi_mac.c is enabled by CONFIG_PASEMI_MAC, which depends on
> PPC64 && PCI. However pasemi_mac.c uses several routines that are only
> built when PPC_PASEMI is selected. This can lead to an unbuildable config:
>
> ERROR: ".pasemi_dma_start_chan" [drivers/net/pasemi_mac.ko] undefined!
>
> So make CONFIG_PASEMI_MAC depend on PPC_PASEMI instead of PPC64.
>
> Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
> ---
> drivers/net/Kconfig | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
>
>
> Jeff, pending Olof's ack, this would be nice for 25, but is obviously
> not super important.
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index fe7b5ec..3a0b20a 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -2635,7 +2635,7 @@ config NIU
>
> config PASEMI_MAC
> tristate "PA Semi 1/10Gbit MAC"
> - depends on PPC64 && PCI
> + depends on PPC_PASEMI && PCI
> select PHYLIB
applied
^ permalink raw reply
* Re: [PATCH] ibm_newemac: emac_tx_csum typo fix
From: Jeff Garzik @ 2008-03-29 1:54 UTC (permalink / raw)
To: Valentine Barshak; +Cc: linuxppc-dev, netdev
In-Reply-To: <20080327144357.GA9111@ru.mvista.com>
Valentine Barshak wrote:
> Move the "&& skb->ip_summed == CHECKSUM_PARTIAL" part out of
> emac_has_feature parameters.
>
> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
> ---
> drivers/net/ibm_newemac/core.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff -pruN linux-2.6.orig/drivers/net/ibm_newemac/core.c linux-2.6/drivers/net/ibm_newemac/core.c
> --- linux-2.6.orig/drivers/net/ibm_newemac/core.c 2008-02-21 16:45:36.000000000 +0300
> +++ linux-2.6/drivers/net/ibm_newemac/core.c 2008-02-22 19:55:29.000000000 +0300
> @@ -1235,8 +1235,8 @@ static int emac_close(struct net_device
> static inline u16 emac_tx_csum(struct emac_instance *dev,
> struct sk_buff *skb)
> {
> - if (emac_has_feature(dev, EMAC_FTR_HAS_TAH &&
> - skb->ip_summed == CHECKSUM_PARTIAL)) {
> + if (emac_has_feature(dev, EMAC_FTR_HAS_TAH) &&
> + (skb->ip_summed == CHECKSUM_PARTIAL)) {
> ++dev->stats.tx_packets_csum;
> return EMAC_TX_CTRL_TAH_CSUM;
applied
^ permalink raw reply
* Re: [PATCH 2/2 v2] pasemi_mac: Netpoll support
From: Jeff Garzik @ 2008-03-29 2:11 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev, pasemi-linux, ncase, netdev
In-Reply-To: <20080327224007.GB17980@lixom.net>
Olof Johansson wrote:
> Add netpoll support to allow use of netconsole.
>
> Signed-off-by: Nate Case <ncase@xes-inc.com>
> Signed-off-by: Olof Johansson <olof@lixom.net>
>
> ---
> Changed the interrupt handler arguments as found by Valentine. Will push
> through powerpc.git with Jeff's ACKs (that were already given).
>
>
> -Olof
ACK
^ permalink raw reply
* Re: [PATCH 1/2] ibm_newemac: PowerPC 440GX EMAC PHY clock workaround
From: Jeff Garzik @ 2008-03-29 2:18 UTC (permalink / raw)
To: Valentine Barshak; +Cc: linuxppc-dev, netdev
In-Reply-To: <20080327144044.GA8831@ru.mvista.com>
Valentine Barshak wrote:
> The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout error)
> if there's no link. Because of that it fails to find PHY chip. The older ibm_emac
> driver had a workaround for that: the EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros,
> which toggle the Ethernet Clock Select bit in the SDR0_MFR register. This patch
> does the same for "ibm,emac-440gx" compatible chips. The workaround forces
> clock on -all- EMACs, so we select clock under global emac_phy_map_lock.
>
> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
> ---
> drivers/net/ibm_newemac/core.c | 16 +++++++++++++++-
> drivers/net/ibm_newemac/core.h | 8 ++++++--
> 2 files changed, 21 insertions(+), 3 deletions(-)
is this for 2.6.25-rc?
^ permalink raw reply
* [PATCH] vma_map: use proper pointer types
From: Al Viro @ 2008-03-29 3:08 UTC (permalink / raw)
To: torvalds; +Cc: linuxppc-dev, linux-kernel
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
---
arch/powerpc/oprofile/cell/vma_map.c | 37 ++++++++++++++-------------------
1 files changed, 16 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/oprofile/cell/vma_map.c b/arch/powerpc/oprofile/cell/vma_map.c
index 76ec1d1..9a93217 100644
--- a/arch/powerpc/oprofile/cell/vma_map.c
+++ b/arch/powerpc/oprofile/cell/vma_map.c
@@ -92,7 +92,7 @@ vma_map_add(struct vma_to_fileoffset_map *map, unsigned int vma,
* A pointer to the first vma_map in the generated list
* of vma_maps is returned. */
struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
- unsigned long spu_elf_start)
+ unsigned long __spu_elf_start)
{
static const unsigned char expected[EI_PAD] = {
[EI_MAG0] = ELFMAG0,
@@ -107,9 +107,11 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
int grd_val;
struct vma_to_fileoffset_map *map = NULL;
+ void __user *spu_elf_start = (void __user *)__spu_elf_start;
struct spu_overlay_info ovly;
unsigned int overlay_tbl_offset = -1;
- unsigned long phdr_start, shdr_start;
+ Elf32_Phdr __user *phdr_start;
+ Elf32_Shdr __user *shdr_start;
Elf32_Ehdr ehdr;
Elf32_Phdr phdr;
Elf32_Shdr shdr, shdr_str;
@@ -121,12 +123,12 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
unsigned int ovly_buf_table_sym = 0;
unsigned int ovly_table_end_sym = 0;
unsigned int ovly_buf_table_end_sym = 0;
- unsigned long ovly_table;
+ struct spu_overlay_info __user *ovly_table;
unsigned int n_ovlys;
/* Get and validate ELF header. */
- if (copy_from_user(&ehdr, (void *) spu_elf_start, sizeof (ehdr)))
+ if (copy_from_user(&ehdr, spu_elf_start, sizeof (ehdr)))
goto fail;
if (memcmp(ehdr.e_ident, expected, EI_PAD) != 0) {
@@ -152,9 +154,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
/* Traverse program headers. */
for (i = 0; i < ehdr.e_phnum; i++) {
- if (copy_from_user(&phdr,
- (void *) (phdr_start + i * sizeof(phdr)),
- sizeof(phdr)))
+ if (copy_from_user(&phdr, phdr_start + i, sizeof(phdr)))
goto fail;
if (phdr.p_type != PT_LOAD)
@@ -171,9 +171,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
pr_debug("SPU_PROF: Created non-overlay maps\n");
/* Traverse section table and search for overlay-related symbols. */
for (i = 0; i < ehdr.e_shnum; i++) {
- if (copy_from_user(&shdr,
- (void *) (shdr_start + i * sizeof(shdr)),
- sizeof(shdr)))
+ if (copy_from_user(&shdr, shdr_start + i, sizeof(shdr)))
goto fail;
if (shdr.sh_type != SHT_SYMTAB)
@@ -182,8 +180,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
continue;
if (copy_from_user(&shdr_str,
- (void *) (shdr_start + shdr.sh_link *
- sizeof(shdr)),
+ shdr_start + shdr.sh_link,
sizeof(shdr)))
goto fail;
@@ -191,15 +188,15 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
goto fail;;
for (j = 0; j < shdr.sh_size / sizeof (sym); j++) {
- if (copy_from_user(&sym, (void *) (spu_elf_start +
- shdr.sh_offset + j *
- sizeof (sym)),
+ if (copy_from_user(&sym, spu_elf_start +
+ shdr.sh_offset +
+ j * sizeof (sym),
sizeof (sym)))
goto fail;
- if (copy_from_user(name, (void *)
- (spu_elf_start + shdr_str.sh_offset +
- sym.st_name),
+ if (copy_from_user(name,
+ spu_elf_start + shdr_str.sh_offset +
+ sym.st_name,
20))
goto fail;
@@ -245,9 +242,7 @@ struct vma_to_fileoffset_map *create_vma_map(const struct spu *aSpu,
/* Traverse overlay table. */
for (i = 0; i < n_ovlys; i++) {
- if (copy_from_user(&ovly, (void *)
- (ovly_table + i * sizeof (ovly)),
- sizeof (ovly)))
+ if (copy_from_user(&ovly, ovly_table + i, sizeof (ovly)))
goto fail;
/* The ovly.vma/size/offset arguments are analogous to the same
--
1.5.3.GIT
^ permalink raw reply related
* [PATCH] powerpc/pseries/xcis: ansify
From: Al Viro @ 2008-03-29 3:10 UTC (permalink / raw)
To: torvalds; +Cc: linuxppc-dev, linux-kernel
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
---
arch/powerpc/platforms/pseries/xics.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index ca52b58..a977f20 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -763,7 +763,7 @@ void xics_request_IPIs(void)
}
#endif /* CONFIG_SMP */
-void xics_teardown_cpu()
+void xics_teardown_cpu(void)
{
int cpu = smp_processor_id();
--
1.5.3.GIT
^ permalink raw reply related
* Re: [PATCH 1/2] ibm_newemac: PowerPC 440GX EMAC PHY clock workaround
From: Josh Boyer @ 2008-03-29 3:30 UTC (permalink / raw)
To: Jeff Garzik; +Cc: linuxppc-dev, netdev
In-Reply-To: <47EDA6F1.9080206@garzik.org>
On Fri, 28 Mar 2008 22:18:25 -0400
Jeff Garzik <jeff@garzik.org> wrote:
> Valentine Barshak wrote:
> > The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout error)
> > if there's no link. Because of that it fails to find PHY chip. The older ibm_emac
> > driver had a workaround for that: the EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros,
> > which toggle the Ethernet Clock Select bit in the SDR0_MFR register. This patch
> > does the same for "ibm,emac-440gx" compatible chips. The workaround forces
> > clock on -all- EMACs, so we select clock under global emac_phy_map_lock.
> >
> > Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
> > ---
> > drivers/net/ibm_newemac/core.c | 16 +++++++++++++++-
> > drivers/net/ibm_newemac/core.h | 8 ++++++--
> > 2 files changed, 21 insertions(+), 3 deletions(-)
>
> is this for 2.6.25-rc?
No. This, and patch 2/2, are for 2.6.26 and depend on a patch in my
tree. These are the two Ben asked about going through the powerpc tree
but naturally we wanted an Ack from you first.
thx,
josh
^ permalink raw reply
* Re: [PATCH 1/2] ibm_newemac: PowerPC 440GX EMAC PHY clock workaround
From: Benjamin Herrenschmidt @ 2008-03-29 3:28 UTC (permalink / raw)
To: Jeff Garzik; +Cc: linuxppc-dev, netdev
In-Reply-To: <47EDA6F1.9080206@garzik.org>
On Fri, 2008-03-28 at 22:18 -0400, Jeff Garzik wrote:
> Valentine Barshak wrote:
> > The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout error)
> > if there's no link. Because of that it fails to find PHY chip. The older ibm_emac
> > driver had a workaround for that: the EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros,
> > which toggle the Ethernet Clock Select bit in the SDR0_MFR register. This patch
> > does the same for "ibm,emac-440gx" compatible chips. The workaround forces
> > clock on -all- EMACs, so we select clock under global emac_phy_map_lock.
> >
> > Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
> > ---
> > drivers/net/ibm_newemac/core.c | 16 +++++++++++++++-
> > drivers/net/ibm_newemac/core.h | 8 ++++++--
> > 2 files changed, 21 insertions(+), 3 deletions(-)
>
> is this for 2.6.25-rc?
Nah, too late imho.
Ben.
^ permalink raw reply
* Xilinx LLTEMAC driver issues
From: Magnus Hjorth @ 2008-03-29 12:54 UTC (permalink / raw)
To: 'git'; +Cc: linuxppc-embedded
Hi,
I'm having some networking troubles with the Xilinx LLTEMAC driver from =
the
Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
xps_ll_temac v1.00.b=20
The weird thing is, that it sort of half works. It successfully makes a =
DHCP
request and gets its IP address. I tried setting up a tftpd server, and =
I can
see UDP requests coming in but the response doesn't seem to come out. I =
also
tried running a TCP server on the board, and it can see and accept =
incoming
connections but after that no data seems to get through. I can ping out =
and
get around 40% packet loss.
Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
interrupts. No eth0 interrupts but that seems to be OK judging by the =
driver
source comments. Ifconfig shows no collistions, no dropped packets, no =
errors,
so the system seems to think that everything is OK.=20
Clues anyone? I'm starting to run out of ideas...
Best regards,
Magnus
--
Magnus Hjorth, M.Sc.
Omnisys Instruments AB
Gruvgatan 8
SE-421 30 V=E4stra Fr=F6lunda, SWEDEN
Phone: +46 31 734 34 09
Fax: +46 31 734 34 29
http://www.omnisys.se
^ permalink raw reply
* [PATCH v2] [POWERPC] 85xx: Add support for relocatble kernel (and booting at non-zero)
From: Kumar Gala @ 2008-03-29 13:34 UTC (permalink / raw)
To: linuxppc-dev
Added support to allow an 85xx kernel to be run from a non-zero physical
address (useful for cooperative asymmetric multiprocessing situations) and
kdump. The support can either be at compile time or runtime
(CONFIG_RELOCATABLE).
Currently we are limited to running at a physical address that is module
256M. This is due to how we map TLBs to cover lowmem and should be fixed
up to allow 64M or maybe even 16M alignment in the future.
All the magic for this support is accomplished by proper initializating
of the kernel memory subsystem properly and ARCH_PFN_OFFSET.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
The alignment compile check broke building on ppc32 (pmac, etc) since
CONFIG_PHYSICAL_ALIGN isn't defined there.
arch/powerpc/Kconfig | 69 ++++++++++++++++++++++++++++++++-
arch/powerpc/boot/Makefile | 4 +-
arch/powerpc/kernel/head_fsl_booke.S | 11 +++++
arch/powerpc/kernel/prom.c | 4 ++
arch/powerpc/kernel/setup_64.c | 2 +-
arch/powerpc/mm/init_32.c | 4 +-
arch/powerpc/mm/init_64.c | 3 +-
arch/powerpc/mm/mem.c | 5 +-
include/asm-powerpc/kdump.h | 5 --
include/asm-powerpc/page.h | 43 +++++++++++++++++---
include/asm-powerpc/page_32.h | 6 +++
include/asm-powerpc/pgtable-ppc32.h | 5 +--
12 files changed, 135 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 4d9ced2..42c22f7 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -619,21 +619,76 @@ config LOWMEM_SIZE
hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL
default "0x30000000"
+config RELOCATABLE
+ bool "Build a relocatable kernel (EXPERIMENTAL)"
+ depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE
+ help
+ This builds a kernel image that is capable of running at the
+ location the kernel is loaded at (some alignment restrictions may
+ exist).
+
+ One use is for the kexec on panic case where the recovery kernel
+ must live at a different physical address than the primary
+ kernel.
+
+ Note: If CONFIG_RELOCATABLE=y, then the kernel runs from the address
+ it has been loaded at and the compile time physical addresses
+ CONFIG_PHYSICAL_START is ignored. However CONFIG_PHYSICAL_START
+ setting can still be useful to bootwrappers that need to know the
+ load location of the kernel (eg. u-boot/mkimage).
+
+config PAGE_OFFSET_BOOL
+ bool "Set custom page offset address"
+ depends on ADVANCED_OPTIONS
+ help
+ This option allows you to set the kernel virtual address at which
+ the kernel will map low memory. This can be useful in optimizing
+ the virtual memory layout of the system.
+
+ Say N here unless you know what you are doing.
+
+config PAGE_OFFSET
+ hex "Virtual address of memory base" if PAGE_OFFSET_BOOL
+ default "0xc0000000"
+
config KERNEL_START_BOOL
bool "Set custom kernel base address"
depends on ADVANCED_OPTIONS
help
This option allows you to set the kernel virtual address at which
- the kernel will map low memory (the kernel image will be linked at
- this address). This can be useful in optimizing the virtual memory
- layout of the system.
+ the kernel will be loaded. Normally this should match PAGE_OFFSET
+ however there are times (like kdump) that one might not want them
+ to be the same.
Say N here unless you know what you are doing.
config KERNEL_START
hex "Virtual address of kernel base" if KERNEL_START_BOOL
+ default PAGE_OFFSET if PAGE_OFFSET_BOOL
+ default "0xc2000000" if CRASH_DUMP
default "0xc0000000"
+config PHYSICAL_START_BOOL
+ bool "Set physical address where the kernel is loaded"
+ depends on ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE
+ help
+ This gives the physical address where the kernel is loaded.
+
+ Say N here unless you know what you are doing.
+
+config PHYSICAL_START
+ hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL
+ default "0x02000000" if PPC_STD_MMU && CRASH_DUMP
+ default "0x00000000"
+
+config PHYSICAL_ALIGN
+ hex
+ default "0x10000000" if FSL_BOOKE
+ help
+ This value puts the alignment restrictions on physical address
+ where kernel is loaded and run from. Kernel is compiled for an
+ address which meets above alignment restriction.
+
config TASK_SIZE_BOOL
bool "Set custom user task size"
depends on ADVANCED_OPTIONS
@@ -680,9 +735,17 @@ config PIN_TLB
endmenu
if PPC64
+config PAGE_OFFSET
+ hex
+ default "0xc000000000000000"
config KERNEL_START
hex
+ default "0xc000000002000000" if CRASH_DUMP
default "0xc000000000000000"
+config PHYSICAL_START
+ hex
+ default "0x02000000" if CRASH_DUMP
+ default "0x00000000"
endif
source "net/Kconfig"
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 3c80858..c7c2a9d 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -35,8 +35,8 @@ endif
BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) -I$(srctree)/$(src)/libfdt
-ifdef CONFIG_MEMORY_START
-MEMBASE=$(CONFIG_MEMORY_START)
+ifdef CONFIG_PHYSICAL_START
+MEMBASE=$(CONFIG_PHYSICAL_START)
else
MEMBASE=0x00000000
endif
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 9f40b3e..4d0336b 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -368,6 +368,17 @@ skpinv: addi r6,r6,1 /* Increment */
bl early_init
+#ifdef CONFIG_RELOCATABLE
+ lis r3,kernstart_addr@ha
+ la r3,kernstart_addr@l(r3)
+#ifdef CONFIG_PHYS_64BIT
+ stw r23,0(r3)
+ stw r25,4(r3)
+#else
+ stw r25,0(r3)
+#endif
+#endif
+
mfspr r3,SPRN_TLB1CFG
andi. r3,r3,0xfff
lis r4,num_tlbcam_entries@ha
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 60ef7d1..988cbde 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -53,6 +53,7 @@
#include <asm/pci-bridge.h>
#include <asm/phyp_dump.h>
#include <asm/kexec.h>
+#include <mm/mmu_decl.h>
#ifdef DEBUG
#define DBG(fmt...) printk(KERN_ERR fmt)
@@ -978,7 +979,10 @@ static int __init early_init_dt_scan_memory(unsigned long node,
}
#endif
lmb_add(base, size);
+
+ memstart_addr = min((u64)memstart_addr, base);
}
+
return 0;
}
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 0205d40..9087e7a 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -431,7 +431,7 @@ void __init setup_system(void)
printk("htab_address = 0x%p\n", htab_address);
printk("htab_hash_mask = 0x%lx\n", htab_hash_mask);
#if PHYSICAL_START > 0
- printk("physical_start = 0x%x\n", PHYSICAL_START);
+ printk("physical_start = 0x%lx\n", PHYSICAL_START);
#endif
printk("-----------------------------------------------------\n");
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 555bb7e..68ba60c 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -59,8 +59,10 @@ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
unsigned long total_memory;
unsigned long total_lowmem;
-phys_addr_t memstart_addr;
+phys_addr_t memstart_addr = (phys_addr_t)~0ull;
EXPORT_SYMBOL(memstart_addr);
+phys_addr_t kernstart_addr;
+EXPORT_SYMBOL(kernstart_addr);
phys_addr_t lowmem_end_addr;
int boot_mapsize;
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index f18b203..7fbbafd 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -75,7 +75,8 @@
/* max amount of RAM to use */
unsigned long __max_memory;
-phys_addr_t memstart_addr;
+phys_addr_t memstart_addr = ~0;
+phys_addr_t kernstart_addr;
void free_initmem(void)
{
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 9c10b14..3ec7814 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -217,7 +217,7 @@ void __init do_init_bootmem(void)
unsigned long total_pages;
int boot_mapsize;
- max_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
+ max_low_pfn = max_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
total_pages = (lmb_end_of_DRAM() - memstart_addr) >> PAGE_SHIFT;
#ifdef CONFIG_HIGHMEM
total_pages = total_lowmem >> PAGE_SHIFT;
@@ -233,7 +233,8 @@ void __init do_init_bootmem(void)
start = lmb_alloc(bootmap_pages << PAGE_SHIFT, PAGE_SIZE);
- boot_mapsize = init_bootmem(start >> PAGE_SHIFT, total_pages);
+ min_low_pfn = MEMORY_START >> PAGE_SHIFT;
+ boot_mapsize = init_bootmem_node(NODE_DATA(0), start >> PAGE_SHIFT, min_low_pfn, max_low_pfn);
/* Add active regions with valid PFNs */
for (i = 0; i < lmb.memory.cnt; i++) {
diff --git a/include/asm-powerpc/kdump.h b/include/asm-powerpc/kdump.h
index 10e8eb1..f6c93c7 100644
--- a/include/asm-powerpc/kdump.h
+++ b/include/asm-powerpc/kdump.h
@@ -11,16 +11,11 @@
#ifdef CONFIG_CRASH_DUMP
-#define PHYSICAL_START KDUMP_KERNELBASE
#define KDUMP_TRAMPOLINE_START 0x0100
#define KDUMP_TRAMPOLINE_END 0x3000
#define KDUMP_MIN_TCE_ENTRIES 2048
-#else /* !CONFIG_CRASH_DUMP */
-
-#define PHYSICAL_START 0x0
-
#endif /* CONFIG_CRASH_DUMP */
#ifndef __ASSEMBLY__
diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h
index df47bbb..adf0591 100644
--- a/include/asm-powerpc/page.h
+++ b/include/asm-powerpc/page.h
@@ -12,6 +12,7 @@
#include <asm/asm-compat.h>
#include <asm/kdump.h>
+#include <asm/types.h>
/*
* On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software
@@ -42,8 +43,23 @@
*
* The kdump dump kernel is one example where KERNELBASE != PAGE_OFFSET.
*
- * To get a physical address from a virtual one you subtract PAGE_OFFSET,
- * _not_ KERNELBASE.
+ * PAGE_OFFSET is the virtual address of the start of lowmem.
+ *
+ * PHYSICAL_START is the physical address of the start of the kernel.
+ *
+ * MEMORY_START is the physical address of the start of lowmem.
+ *
+ * KERNELBASE, PAGE_OFFSET, and PHYSICAL_START are all configurable on
+ * ppc32 and based on how they are set we determine MEMORY_START.
+ *
+ * For the linear mapping the following equation should be true:
+ * KERNELBASE - PAGE_OFFSET = PHYSICAL_START - MEMORY_START
+ *
+ * Also, KERNELBASE >= PAGE_OFFSET and PHYSICAL_START >= MEMORY_START
+ *
+ * There are two was to determine a physical address from a virtual one:
+ * va = pa + PAGE_OFFSET - MEMORY_START
+ * va = pa + KERNELBASE - PHYSICAL_START
*
* If you want to know something's offset from the start of the kernel you
* should subtract KERNELBASE.
@@ -51,19 +67,32 @@
* If you want to test if something's a kernel address, use is_kernel_addr().
*/
-#define PAGE_OFFSET ASM_CONST(CONFIG_KERNEL_START)
-#define KERNELBASE (PAGE_OFFSET + PHYSICAL_START)
+#define KERNELBASE ASM_CONST(CONFIG_KERNEL_START)
+#define PAGE_OFFSET ASM_CONST(CONFIG_PAGE_OFFSET)
+
+#if defined(CONFIG_RELOCATABLE) && defined(CONFIG_FLATMEM)
+#ifndef __ASSEMBLY__
+extern phys_addr_t memstart_addr;
+extern phys_addr_t kernstart_addr;
+#endif
+#define PHYSICAL_START kernstart_addr
+#define MEMORY_START memstart_addr
+#else
+#define PHYSICAL_START ASM_CONST(CONFIG_PHYSICAL_START)
+#define MEMORY_START (PHYSICAL_START + PAGE_OFFSET - KERNELBASE)
+#endif
#ifdef CONFIG_FLATMEM
-#define pfn_valid(pfn) ((pfn) < max_mapnr)
+#define ARCH_PFN_OFFSET (MEMORY_START >> PAGE_SHIFT)
+#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < (ARCH_PFN_OFFSET + max_mapnr))
#endif
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET))
-#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET)
+#define __va(x) ((void *)((unsigned long)(x) - PHYSICAL_START + KERNELBASE))
+#define __pa(x) ((unsigned long)(x) + PHYSICAL_START - KERNELBASE)
/*
* Unfortunately the PLT is in the BSS in the PPC32 ELF ABI,
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
index 51f8134..ebfae53 100644
--- a/include/asm-powerpc/page_32.h
+++ b/include/asm-powerpc/page_32.h
@@ -1,6 +1,12 @@
#ifndef _ASM_POWERPC_PAGE_32_H
#define _ASM_POWERPC_PAGE_32_H
+#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
+#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
+#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
+#endif
+#endif
+
#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
#ifdef CONFIG_NOT_COHERENT_CACHE
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 2c79f55..dbd1875 100644
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -98,9 +98,6 @@ extern int icache_44x_need_flush;
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
#define FIRST_USER_ADDRESS 0
-#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
-#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
-
#define pte_ERROR(e) \
printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
(unsigned long long)pte_val(e))
@@ -692,7 +689,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
#define pmd_page_vaddr(pmd) \
((unsigned long) (pmd_val(pmd) & PAGE_MASK))
#define pmd_page(pmd) \
- (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
+ (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT) - ARCH_PFN_OFFSET)
#endif
/* to find an entry in a kernel page-table-directory */
--
1.5.4.1
^ permalink raw reply related
* RE: Xilinx LLTEMAC driver issues
From: John Linn @ 2008-03-29 13:58 UTC (permalink / raw)
To: Magnus Hjorth, git; +Cc: linuxppc-embedded
In-Reply-To: <20080329125416.B09261AD8051@mail119-sin.bigfish.com>
Hi Magnus,
Sorry to hear you're having problems with it.
I am doing testing on an ML405 which is the same board but with a bigger =
FPGA, but with ppc arch and I don't see this issue. I have done limited =
testing with powerpc arch and the LL TEMAC, but I didn't see this issue =
there either. Powerpc arch is definitely less mature in my experience =
than the ppc arch. I'll do a quick test with my powerpc arch and make =
sure again I'm not seeing it.
My kernel is from the Xilinx Git tree, but there have been a number of =
changes we have pushed out so I don't know how long ago you pulled from =
the Git tree.
My EDK project is 10.1 so it's a little newer. I am using LL TEMAC 1.01a =
so it's a little newer. I reviewed the change log for the LL TEMAC and =
don't see any big problems that were fixed in the newer versions, more =
new features. I'll check with some others here to see if I missed =
something there.
I am using DMA also, but no DRE or checksum offload. You didn't say =
anything about those. I'm going to insert my mhs file that describes my =
system to let you compare your system configuration. It's not clear to =
me yet if you have a h/w or s/w problem. =20
I'll also insert some of my device tree with the LL TEMAC so you can =
compare (ignore 16550 stuff as we are still working on that).
Since you can't ping reliably I would probably focus on that since it's =
simpler than the other issues you're seeing.
Thanks,
John
# =
#########################################################################=
#####
# Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build =
EDK_K_SP1.1
# Thu Feb 14 14:11:12 2008
# Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
# Family: virtex4
# Device: xc4vfx20
# Package: ff672
# Speed Grade: -10
# Processor: ppc405_0
# Processor clock frequency: 300.00 MHz
# Bus clock frequency: 100.00 MHz
# On Chip Memory : 8 KB
# Total Off Chip Memory : 128 MB
# - DDR_SDRAM =3D 128 MB
# =
#########################################################################=
#####
PARAMETER VERSION =3D 2.1.0
PORT fpga_0_RS232_Uart_sin_pin =3D fpga_0_RS232_Uart_sin, DIR =3D I
PORT fpga_0_RS232_Uart_sout_pin =3D fpga_0_RS232_Uart_sout, DIR =3D O
PORT fpga_0_LEDs_4Bit_GPIO_IO_pin =3D fpga_0_LEDs_4Bit_GPIO_IO, DIR =3D =
IO, VEC =3D [0:3]
PORT fpga_0_IIC_EEPROM_Scl_pin =3D fpga_0_IIC_EEPROM_Scl, DIR =3D IO
PORT fpga_0_IIC_EEPROM_Sda_pin =3D fpga_0_IIC_EEPROM_Sda, DIR =3D IO
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR =3D I
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR =3D O, VEC =3D [6:1]
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR =3D IO, VEC =3D [15:0]
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR =3D O
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR =3D O
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR =3D O
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =3D =
fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR =3D I
PORT fpga_0_DDR_SDRAM_DDR_Clk_pin =3D fpga_0_DDR_SDRAM_DDR_Clk, DIR =3D =
O
PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin =3D fpga_0_DDR_SDRAM_DDR_Clk_n, DIR =
=3D O
PORT fpga_0_DDR_SDRAM_DDR_Addr_pin =3D fpga_0_DDR_SDRAM_DDR_Addr, DIR =
=3D O, VEC =3D [12:0]
PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =3D =
fpga_0_DDR_SDRAM_DDR_BankAddr, DIR =3D O, VEC =3D [1:0]
PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CAS_n, DIR =
=3D O
PORT fpga_0_DDR_SDRAM_DDR_CE_pin =3D fpga_0_DDR_SDRAM_DDR_CE, DIR =3D O
PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CS_n, DIR =
=3D O
PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin =3D fpga_0_DDR_SDRAM_DDR_RAS_n, DIR =
=3D O
PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin =3D fpga_0_DDR_SDRAM_DDR_WE_n, DIR =
=3D O
PORT fpga_0_DDR_SDRAM_DDR_DM_pin =3D fpga_0_DDR_SDRAM_DDR_DM, DIR =3D =
O, VEC =3D [3:0]
PORT fpga_0_DDR_SDRAM_DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS, DIR =3D IO, =
VEC =3D [3:0]
PORT fpga_0_DDR_SDRAM_DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ, DIR =3D IO, =
VEC =3D [31:0]
PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR =3D O, VEC =3D [7:0]
PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR =3D O
PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR =3D O
PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR =3D O
PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR =3D I, VEC =3D [7:0]
PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR =3D I
PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR =3D I
PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin =3D =
fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR =3D I
PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR =3D I
PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MDIO_0, DIR =3D IO
PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MDC_0, DIR =3D O
PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin =3D =
fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR =3D O
PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =3D =
100000000
PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SIGIS =
=3D RST
BEGIN ppc405_virtex4
PARAMETER INSTANCE =3D ppc405_0
PARAMETER HW_VER =3D 2.01.a
PARAMETER C_FASTEST_PLB_CLOCK =3D DPLB1
PARAMETER C_IDCR_BASEADDR =3D 0b0100000000
PARAMETER C_IDCR_HIGHADDR =3D 0b0111111111
BUS_INTERFACE JTAGPPC =3D jtagppc_0_0
BUS_INTERFACE IPLB0 =3D plb
BUS_INTERFACE DPLB0 =3D plb
BUS_INTERFACE IPLB1 =3D ppc405_0_iplb1
BUS_INTERFACE DPLB1 =3D ppc405_0_dplb1
BUS_INTERFACE RESETPPC =3D ppc_reset_bus
PORT CPMC405CLOCK =3D proc_clk_s
PORT EICC405EXTINPUTIRQ =3D EICC405EXTINPUTIRQ
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE =3D jtagppc_0
PARAMETER HW_VER =3D 2.01.a
BUS_INTERFACE JTAGPPC0 =3D jtagppc_0_0
END
BEGIN plb_v46
PARAMETER INSTANCE =3D plb
PARAMETER C_DCR_INTFCE =3D 0
PARAMETER C_NUM_CLK_PLB2OPB_REARB =3D 100
PARAMETER HW_VER =3D 1.02.a
PORT PLB_Clk =3D sys_clk_s
PORT SYS_Rst =3D sys_bus_reset
END
BEGIN xps_bram_if_cntlr
PARAMETER INSTANCE =3D xps_bram_if_cntlr_1
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_SPLB_NATIVE_DWIDTH =3D 64
PARAMETER C_BASEADDR =3D 0xffffe000
PARAMETER C_HIGHADDR =3D 0xffffffff
BUS_INTERFACE SPLB =3D plb
BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
END
BEGIN bram_block
PARAMETER INSTANCE =3D plb_bram_if_cntlr_1_bram
PARAMETER HW_VER =3D 1.00.a
BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
END
BEGIN xps_uart16550
PARAMETER INSTANCE =3D RS232_Uart
PARAMETER HW_VER =3D 2.00.a
PARAMETER C_IS_A_16550 =3D 1
PARAMETER C_BASEADDR =3D 0x83e00000
PARAMETER C_HIGHADDR =3D 0x83e0ffff
BUS_INTERFACE SPLB =3D plb
PORT sin =3D fpga_0_RS232_Uart_sin
PORT sout =3D fpga_0_RS232_Uart_sout
PORT IP2INTC_Irpt =3D RS232_Uart_IP2INTC_Irpt
END
BEGIN xps_gpio
PARAMETER INSTANCE =3D LEDs_4Bit
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_INTERRUPT_PRESENT =3D 1
PARAMETER C_GPIO_WIDTH =3D 4
PARAMETER C_IS_DUAL =3D 0
PARAMETER C_IS_BIDIR =3D 1
PARAMETER C_ALL_INPUTS =3D 0
PARAMETER C_BASEADDR =3D 0x81400000
PARAMETER C_HIGHADDR =3D 0x8140ffff
BUS_INTERFACE SPLB =3D plb
PORT GPIO_IO =3D fpga_0_LEDs_4Bit_GPIO_IO
PORT IP2INTC_Irpt =3D LEDs_4Bit_IP2INTC_Irpt
END
BEGIN xps_iic
PARAMETER INSTANCE =3D IIC_EEPROM
PARAMETER HW_VER =3D 2.00.a
PARAMETER C_CLK_FREQ =3D 100000000
PARAMETER C_IIC_FREQ =3D 100000
PARAMETER C_TEN_BIT_ADR =3D 0
PARAMETER C_BASEADDR =3D 0x81600000
PARAMETER C_HIGHADDR =3D 0x8160ffff
BUS_INTERFACE SPLB =3D plb
PORT Scl =3D fpga_0_IIC_EEPROM_Scl
PORT Sda =3D fpga_0_IIC_EEPROM_Sda
PORT IIC2INTC_Irpt =3D IIC_EEPROM_IIC2INTC_Irpt
END
BEGIN xps_sysace
PARAMETER INSTANCE =3D SysACE_CompactFlash
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_MEM_WIDTH =3D 16
PARAMETER C_BASEADDR =3D 0x83600000
PARAMETER C_HIGHADDR =3D 0x8360ffff
BUS_INTERFACE SPLB =3D plb
PORT SysACE_CLK =3D fpga_0_SysACE_CompactFlash_SysACE_CLK
PORT SysACE_MPA =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
PORT SysACE_MPD =3D fpga_0_SysACE_CompactFlash_SysACE_MPD
PORT SysACE_CEN =3D fpga_0_SysACE_CompactFlash_SysACE_CEN
PORT SysACE_OEN =3D fpga_0_SysACE_CompactFlash_SysACE_OEN
PORT SysACE_WEN =3D fpga_0_SysACE_CompactFlash_SysACE_WEN
PORT SysACE_MPIRQ =3D fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
PORT SysACE_IRQ =3D SysACE_CompactFlash_SysACE_IRQ
END
BEGIN mpmc
PARAMETER INSTANCE =3D DDR_SDRAM
PARAMETER HW_VER =3D 4.00.a
PARAMETER C_NUM_PORTS =3D 3
PARAMETER C_MEM_PARTNO =3D HYB25D512160BE-5
PARAMETER C_MEM_DATA_WIDTH =3D 32
PARAMETER C_MEM_DQS_WIDTH =3D 4
PARAMETER C_MEM_DM_WIDTH =3D 4
PARAMETER C_MEM_TYPE =3D DDR
PARAMETER C_NUM_IDELAYCTRL =3D 2
PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
PARAMETER C_PIM0_BASETYPE =3D 2
PARAMETER C_PIM1_BASETYPE =3D 2
PARAMETER C_PIM2_BASETYPE =3D 3
PARAMETER C_MPMC_CLK0_PERIOD_PS =3D 10000
PARAMETER C_SDMA2_PI2LL_CLK_RATIO =3D 1
PARAMETER C_MPMC_BASEADDR =3D 0x00000000
PARAMETER C_MPMC_HIGHADDR =3D 0x07ffffff
PARAMETER C_SDMA_CTRL_BASEADDR =3D 0x84600000
PARAMETER C_SDMA_CTRL_HIGHADDR =3D 0x8460ffff
BUS_INTERFACE SPLB0 =3D ppc405_0_iplb1
BUS_INTERFACE SPLB1 =3D ppc405_0_dplb1
BUS_INTERFACE SDMA_LL2 =3D TriMode_MAC_GMII_LLINK0
BUS_INTERFACE SDMA_CTRL2 =3D plb
PORT DDR_Addr =3D fpga_0_DDR_SDRAM_DDR_Addr
PORT DDR_BankAddr =3D fpga_0_DDR_SDRAM_DDR_BankAddr
PORT DDR_CAS_n =3D fpga_0_DDR_SDRAM_DDR_CAS_n
PORT DDR_CE =3D fpga_0_DDR_SDRAM_DDR_CE
PORT DDR_CS_n =3D fpga_0_DDR_SDRAM_DDR_CS_n
PORT DDR_RAS_n =3D fpga_0_DDR_SDRAM_DDR_RAS_n
PORT DDR_WE_n =3D fpga_0_DDR_SDRAM_DDR_WE_n
PORT DDR_DM =3D fpga_0_DDR_SDRAM_DDR_DM
PORT DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS
PORT DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ
PORT DDR_Clk =3D fpga_0_DDR_SDRAM_DDR_Clk
PORT DDR_Clk_n =3D fpga_0_DDR_SDRAM_DDR_Clk_n
PORT MPMC_Clk0 =3D sys_clk_s
PORT MPMC_Clk90 =3D DDR_SDRAM_mpmc_clk_90_s
PORT SDMA2_Clk =3D sys_clk_s
PORT MPMC_Clk_200MHz =3D clk_200mhz_s
PORT MPMC_Rst =3D sys_periph_reset
PORT SDMA2_Rx_IntOut =3D DDR_SDRAM_SDMA2_Rx_IntOut
PORT SDMA2_Tx_IntOut =3D DDR_SDRAM_SDMA2_Tx_IntOut
END
BEGIN xps_ll_temac
PARAMETER INSTANCE =3D TriMode_MAC_GMII
PARAMETER HW_VER =3D 1.01.a
PARAMETER C_SPLB_CLK_PERIOD_PS =3D 10000
PARAMETER C_PHY_TYPE =3D 1
PARAMETER C_NUM_IDELAYCTRL =3D 4
PARAMETER C_IDELAYCTRL_LOC =3D =
IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
PARAMETER C_TEMAC_TYPE =3D 1
PARAMETER C_BUS2CORE_CLK_RATIO =3D 1
PARAMETER C_BASEADDR =3D 0x81c00000
PARAMETER C_HIGHADDR =3D 0x81c0ffff
BUS_INTERFACE SPLB =3D plb
BUS_INTERFACE LLINK0 =3D TriMode_MAC_GMII_LLINK0
PORT GMII_TXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TXD_0
PORT GMII_TX_EN_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
PORT GMII_TX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
PORT GMII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
PORT GMII_RXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RXD_0
PORT GMII_RX_DV_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
PORT GMII_RX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
PORT GMII_RX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
PORT MII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
PORT MDIO_0 =3D fpga_0_TriMode_MAC_GMII_MDIO_0
PORT MDC_0 =3D fpga_0_TriMode_MAC_GMII_MDC_0
PORT TemacPhy_RST_n =3D fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
PORT GTX_CLK_0 =3D temac_clk_s
PORT REFCLK =3D clk_200mhz_s
PORT LlinkTemac0_CLK =3D sys_clk_s
PORT TemacIntc0_Irpt =3D TriMode_MAC_GMII_TemacIntc0_Irpt
END
BEGIN util_bus_split
PARAMETER INSTANCE =3D SysACE_CompactFlash_util_bus_split_0
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_SIZE_IN =3D 7
PARAMETER C_LEFT_POS =3D 0
PARAMETER C_SPLIT =3D 6
PORT Sig =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
PORT Out1 =3D fpga_0_SysACE_CompactFlash_SysACE_MPA
END
BEGIN plb_v46
PARAMETER INSTANCE =3D ppc405_0_iplb1
PARAMETER HW_VER =3D 1.02.a
PORT PLB_Clk =3D sys_clk_s
PORT SYS_Rst =3D sys_bus_reset
END
BEGIN plb_v46
PARAMETER INSTANCE =3D ppc405_0_dplb1
PARAMETER HW_VER =3D 1.02.a
PORT PLB_Clk =3D sys_clk_s
PORT SYS_Rst =3D sys_bus_reset
END
BEGIN clock_generator
PARAMETER INSTANCE =3D clock_generator_0
PARAMETER HW_VER =3D 2.00.a
PARAMETER C_EXT_RESET_HIGH =3D 1
PARAMETER C_CLKIN_FREQ =3D 100000000
PARAMETER C_CLKOUT0_FREQ =3D 100000000
PARAMETER C_CLKOUT0_BUF =3D TRUE
PARAMETER C_CLKOUT0_PHASE =3D 0
PARAMETER C_CLKOUT0_GROUP =3D DCM0
PARAMETER C_CLKOUT1_FREQ =3D 100000000
PARAMETER C_CLKOUT1_BUF =3D TRUE
PARAMETER C_CLKOUT1_PHASE =3D 90
PARAMETER C_CLKOUT1_GROUP =3D DCM0
PARAMETER C_CLKOUT2_FREQ =3D 300000000
PARAMETER C_CLKOUT2_BUF =3D TRUE
PARAMETER C_CLKOUT2_PHASE =3D 0
PARAMETER C_CLKOUT2_GROUP =3D DCM0
PARAMETER C_CLKOUT3_FREQ =3D 200000000
PARAMETER C_CLKOUT3_BUF =3D TRUE
PARAMETER C_CLKOUT3_PHASE =3D 0
PARAMETER C_CLKOUT3_GROUP =3D NONE
PARAMETER C_CLKOUT4_FREQ =3D 125000000
PARAMETER C_CLKOUT4_BUF =3D TRUE
PARAMETER C_CLKOUT4_PHASE =3D 0
PARAMETER C_CLKOUT4_GROUP =3D NONE
PORT CLKOUT0 =3D sys_clk_s
PORT CLKOUT1 =3D DDR_SDRAM_mpmc_clk_90_s
PORT CLKOUT2 =3D proc_clk_s
PORT CLKOUT3 =3D clk_200mhz_s
PORT CLKOUT4 =3D temac_clk_s
PORT CLKIN =3D dcm_clk_s
PORT LOCKED =3D Dcm_all_locked
PORT RST =3D net_gnd
END
BEGIN proc_sys_reset
PARAMETER INSTANCE =3D proc_sys_reset_0
PARAMETER HW_VER =3D 2.00.a
PARAMETER C_EXT_RESET_HIGH =3D 0
BUS_INTERFACE RESETPPC0 =3D ppc_reset_bus
PORT Slowest_sync_clk =3D sys_clk_s
PORT Dcm_locked =3D Dcm_all_locked
PORT Ext_Reset_In =3D sys_rst_s
PORT Bus_Struct_Reset =3D sys_bus_reset
PORT Peripheral_Reset =3D sys_periph_reset
END
BEGIN xps_intc
PARAMETER INSTANCE =3D xps_intc_0
PARAMETER HW_VER =3D 1.00.a
PARAMETER C_BASEADDR =3D 0x81800000
PARAMETER C_HIGHADDR =3D 0x8180ffff
BUS_INTERFACE SPLB =3D plb
PORT Irq =3D EICC405EXTINPUTIRQ
PORT Intr =3D RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & =
IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & =
TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut & =
DDR_SDRAM_SDMA2_Tx_IntOut
END
#address-cells =3D <1>;
#size-cells =3D <1>;
compatible =3D "xlnx,virtex";
model =3D "testing";
DDR_SDRAM: memory@0 {
device_type =3D "memory";
reg =3D < 0 8000000 >;
} ;
chosen {
bootargs =3D "console=3DttyS0,9600 ip=3Don =
nfsroot=3D172.16.40.76:/v2pclients/jhl26,tcp";=20
linux,stdout-path =3D "/plb@0/serial@83e00000";
} ;
cpus {
#address-cells =3D <1>;
#cpus =3D <1>;
#size-cells =3D <0>;
ppc405_0: cpu@0 {
clock-frequency =3D <11e1a300>;
compatible =3D "PowerPC,405", "ibm,ppc405";
d-cache-line-size =3D <20>;
d-cache-size =3D <4000>;
device_type =3D "cpu";
i-cache-line-size =3D <20>;
i-cache-size =3D <4000>;
model =3D "PowerPC,405";
reg =3D <0>;
timebase-frequency =3D <11e1a300>;
xlnx,apu-control =3D <de00>;
xlnx,apu-udi-1 =3D <a18983>;
xlnx,apu-udi-2 =3D <a38983>;
xlnx,apu-udi-3 =3D <a589c3>;
xlnx,apu-udi-4 =3D <a789c3>;
xlnx,apu-udi-5 =3D <a98c03>;
xlnx,apu-udi-6 =3D <ab8c03>;
xlnx,apu-udi-7 =3D <ad8c43>;
xlnx,apu-udi-8 =3D <af8c43>;
xlnx,deterministic-mult =3D <0>;
xlnx,disable-operand-forwarding =3D <1>;
xlnx,fastest-plb-clock =3D "DPLB0";
xlnx,generate-plb-timespecs =3D <1>;
xlnx,mmu-enable =3D <1>;
xlnx,pvr-high =3D <0>;
xlnx,pvr-low =3D <0>;
} ;
} ;
plb: plb@0 {
#address-cells =3D <1>;
#size-cells =3D <1>;
compatible =3D "xlnx,plb-v46-1.02.a";
ranges ;
IIC_EEPROM: i2c@81600000 {
compatible =3D "xlnx,xps-iic-2.00.a";
interrupt-parent =3D <&xps_intc_0>;
interrupts =3D < 4 2 >;
reg =3D < 81600000 10000 >;
xlnx,clk-freq =3D <5f5e100>;
xlnx,family =3D "virtex4";
xlnx,gpo-width =3D <1>;
xlnx,iic-freq =3D <186a0>;
xlnx,scl-inertial-delay =3D <0>;
xlnx,sda-inertial-delay =3D <0>;
xlnx,ten-bit-adr =3D <0>;
} ;
LEDs_4Bit: gpio@81400000 {
compatible =3D "xlnx,xps-gpio-1.00.a";
interrupt-parent =3D <&xps_intc_0>;
interrupts =3D < 5 2 >;
reg =3D < 81400000 10000 >;
xlnx,all-inputs =3D <0>;
xlnx,all-inputs-2 =3D <0>;
xlnx,dout-default =3D <0>;
xlnx,dout-default-2 =3D <0>;
xlnx,family =3D "virtex4";
xlnx,gpio-width =3D <4>;
xlnx,interrupt-present =3D <1>;
xlnx,is-bidir =3D <1>;
xlnx,is-bidir-2 =3D <1>;
xlnx,is-dual =3D <0>;
xlnx,tri-default =3D <ffffffff>;
xlnx,tri-default-2 =3D <ffffffff>;
} ;
RS232_Uart: serial@83e00000 {
compatible =3D "xlnx,xps-uart16550-2.00.a";
// compatible =3D "ns16550";=20
device_type =3D "serial";
interrupt-parent =3D <&xps_intc_0>;=20
interrupts =3D < 6 2 >;=20
reg =3D < 83e00000 10000 >;
current-speed =3D <d#9600>;
clock-frequency =3D <d#100000000>; /* added by jhl */
reg-shift =3D <2>;
xlnx,family =3D "virtex4";
xlnx,has-external-rclk =3D <0>;
xlnx,has-external-xin =3D <0>;
xlnx,is-a-16550 =3D <1>;
} ;
SysACE_CompactFlash: sysace@83600000 {
compatible =3D "xlnx,xps-sysace-1.00.a";
interrupt-parent =3D <&xps_intc_0>;
interrupts =3D < 3 2 >;
reg =3D < 83600000 10000 >;
xlnx,family =3D "virtex4";
xlnx,mem-width =3D <10>;
} ;
TriMode_MAC_GMII: xps-ll-temac@81c00000 {
#address-cells =3D <1>;
#size-cells =3D <1>;
compatible =3D "xlnx,compound";
ethernet@81c00000 {
compatible =3D "xlnx,xps-ll-temac-1.01.a";
device_type =3D "network";
interrupt-parent =3D <&xps_intc_0>;
interrupts =3D < 2 2 >;
llink-connected =3D <&PIM2>;
local-mac-address =3D [ 02 00 00 00 00 01 ];
reg =3D < 81c00000 40 >;
xlnx,bus2core-clk-ratio =3D <1>;
xlnx,phy-type =3D <1>;
xlnx,phyaddr =3D <1>;
xlnx,rxcsum =3D <0>;
xlnx,rxfifo =3D <1000>;
xlnx,temac-type =3D <1>;
xlnx,txcsum =3D <0>;
xlnx,txfifo =3D <1000>;
} ;
} ;
mpmc@0 {
#address-cells =3D <1>;
#size-cells =3D <1>;
compatible =3D "xlnx,mpmc-4.00.a";
PIM2: sdma@84600100 {
compatible =3D "xlnx,ll-dma-1.00.a";
interrupt-parent =3D <&xps_intc_0>;
interrupts =3D < 1 2 0 2 >;
reg =3D < 84600100 80 >;
} ;
} ;
xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
compatible =3D "xlnx,xps-bram-if-cntlr-1.00.a";
reg =3D < ffffe000 2000 >;
xlnx,family =3D "virtex4";
} ;
xps_intc_0: interrupt-controller@81800000 {
#interrupt-cells =3D <2>;
compatible =3D "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg =3D < 81800000 10000 >;
xlnx,num-intr-inputs =3D <7>;
} ;
} ;
ppc405_0_dplb1: plb@1 {
#address-cells =3D <1>;
#size-cells =3D <1>;
compatible =3D "xlnx,plb-v46-1.02.a";
ranges ;
} ;
} ;
-----Original Message-----
From: Magnus Hjorth [mailto:mh@omnisys.se]=20
Sent: Saturday, March 29, 2008 6:54 AM
To: git
Cc: linuxppc-embedded@ozlabs.org
Subject: Xilinx LLTEMAC driver issues
Hi,
I'm having some networking troubles with the Xilinx LLTEMAC driver from =
the
Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
xps_ll_temac v1.00.b=20
The weird thing is, that it sort of half works. It successfully makes a =
DHCP
request and gets its IP address. I tried setting up a tftpd server, and =
I can
see UDP requests coming in but the response doesn't seem to come out. I =
also
tried running a TCP server on the board, and it can see and accept =
incoming
connections but after that no data seems to get through. I can ping out =
and
get around 40% packet loss.
Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
interrupts. No eth0 interrupts but that seems to be OK judging by the =
driver
source comments. Ifconfig shows no collistions, no dropped packets, no =
errors,
so the system seems to think that everything is OK.=20
Clues anyone? I'm starting to run out of ideas...
Best regards,
Magnus
--
Magnus Hjorth, M.Sc.
Omnisys Instruments AB
Gruvgatan 8
SE-421 30 V=E4stra Fr=F6lunda, SWEDEN
Phone: +46 31 734 34 09
Fax: +46 31 734 34 29
http://www.omnisys.se
^ permalink raw reply
* RE: Xilinx LLTEMAC driver issues
From: Magnus Hjorth @ 2008-03-29 14:50 UTC (permalink / raw)
To: John Linn; +Cc: git, linuxppc-embedded
In-Reply-To: <20080329135813.B3832DE8062@mail60-sin.bigfish.com>
Hi John,
Thanks for the very fast reply! Right now I'm not at work so I don't
have the board or EDK here to test anything.
I'm using checksum offload, but I don't know if DRE is enabled or not. I
can't recall seeing any setting to enable/disable DRE..
A few things that crossed my mind:
Last year I did a design with EDK 8.2, back then there was an issue with
the ML403 boards having an old revision of the FPGA which wasn't
compatible with some versions of the IP core. There are no such version
issues with the xps_ll_temac?
I don't think that I had phy-addr set in the DTS file. Will test that on
Monday.
Best regards,
Magnus
On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
> Hi Magnus,
>
> Sorry to hear you're having problems with it.
>
> I am doing testing on an ML405 which is the same board but with a bigger FPGA, but with ppc arch and I don't see this issue. I have done limited testing with powerpc arch and the LL TEMAC, but I didn't see this issue there either. Powerpc arch is definitely less mature in my experience than the ppc arch. I'll do a quick test with my powerpc arch and make sure again I'm not seeing it.
>
> My kernel is from the Xilinx Git tree, but there have been a number of changes we have pushed out so I don't know how long ago you pulled from the Git tree.
>
> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC 1.01a so it's a little newer. I reviewed the change log for the LL TEMAC and don't see any big problems that were fixed in the newer versions, more new features. I'll check with some others here to see if I missed something there.
>
> I am using DMA also, but no DRE or checksum offload. You didn't say anything about those. I'm going to insert my mhs file that describes my system to let you compare your system configuration. It's not clear to me yet if you have a h/w or s/w problem.
>
> I'll also insert some of my device tree with the LL TEMAC so you can compare (ignore 16550 stuff as we are still working on that).
>
> Since you can't ping reliably I would probably focus on that since it's simpler than the other issues you're seeing.
>
> Thanks,
> John
>
>
>
> # ##############################################################################
> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build EDK_K_SP1.1
> # Thu Feb 14 14:11:12 2008
> # Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
> # Family: virtex4
> # Device: xc4vfx20
> # Package: ff672
> # Speed Grade: -10
> # Processor: ppc405_0
> # Processor clock frequency: 300.00 MHz
> # Bus clock frequency: 100.00 MHz
> # On Chip Memory : 8 KB
> # Total Off Chip Memory : 128 MB
> # - DDR_SDRAM = 128 MB
> # ##############################################################################
> PARAMETER VERSION = 2.1.0
>
>
> PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
> PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
> PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
> PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
> PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
> PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
> PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
> PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
> PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
> PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
> PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
> PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
> PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
> PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
> PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
> PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [3:0]
> PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [3:0]
> PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [31:0]
> PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]
> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O
> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O
> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O
> PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]
> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I
> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I
> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I
> PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I
> PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0, DIR = IO
> PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0, DIR = O
> PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O
> PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
> PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
>
>
> BEGIN ppc405_virtex4
> PARAMETER INSTANCE = ppc405_0
> PARAMETER HW_VER = 2.01.a
> PARAMETER C_FASTEST_PLB_CLOCK = DPLB1
> PARAMETER C_IDCR_BASEADDR = 0b0100000000
> PARAMETER C_IDCR_HIGHADDR = 0b0111111111
> BUS_INTERFACE JTAGPPC = jtagppc_0_0
> BUS_INTERFACE IPLB0 = plb
> BUS_INTERFACE DPLB0 = plb
> BUS_INTERFACE IPLB1 = ppc405_0_iplb1
> BUS_INTERFACE DPLB1 = ppc405_0_dplb1
> BUS_INTERFACE RESETPPC = ppc_reset_bus
> PORT CPMC405CLOCK = proc_clk_s
> PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
> END
>
> BEGIN jtagppc_cntlr
> PARAMETER INSTANCE = jtagppc_0
> PARAMETER HW_VER = 2.01.a
> BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
> END
>
> BEGIN plb_v46
> PARAMETER INSTANCE = plb
> PARAMETER C_DCR_INTFCE = 0
> PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
> PARAMETER HW_VER = 1.02.a
> PORT PLB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
>
> BEGIN xps_bram_if_cntlr
> PARAMETER INSTANCE = xps_bram_if_cntlr_1
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_SPLB_NATIVE_DWIDTH = 64
> PARAMETER C_BASEADDR = 0xffffe000
> PARAMETER C_HIGHADDR = 0xffffffff
> BUS_INTERFACE SPLB = plb
> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> END
>
> BEGIN bram_block
> PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
> PARAMETER HW_VER = 1.00.a
> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
> END
>
> BEGIN xps_uart16550
> PARAMETER INSTANCE = RS232_Uart
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_IS_A_16550 = 1
> PARAMETER C_BASEADDR = 0x83e00000
> PARAMETER C_HIGHADDR = 0x83e0ffff
> BUS_INTERFACE SPLB = plb
> PORT sin = fpga_0_RS232_Uart_sin
> PORT sout = fpga_0_RS232_Uart_sout
> PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
> END
>
> BEGIN xps_gpio
> PARAMETER INSTANCE = LEDs_4Bit
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_INTERRUPT_PRESENT = 1
> PARAMETER C_GPIO_WIDTH = 4
> PARAMETER C_IS_DUAL = 0
> PARAMETER C_IS_BIDIR = 1
> PARAMETER C_ALL_INPUTS = 0
> PARAMETER C_BASEADDR = 0x81400000
> PARAMETER C_HIGHADDR = 0x8140ffff
> BUS_INTERFACE SPLB = plb
> PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
> PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
> END
>
> BEGIN xps_iic
> PARAMETER INSTANCE = IIC_EEPROM
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_CLK_FREQ = 100000000
> PARAMETER C_IIC_FREQ = 100000
> PARAMETER C_TEN_BIT_ADR = 0
> PARAMETER C_BASEADDR = 0x81600000
> PARAMETER C_HIGHADDR = 0x8160ffff
> BUS_INTERFACE SPLB = plb
> PORT Scl = fpga_0_IIC_EEPROM_Scl
> PORT Sda = fpga_0_IIC_EEPROM_Sda
> PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
> END
>
> BEGIN xps_sysace
> PARAMETER INSTANCE = SysACE_CompactFlash
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_MEM_WIDTH = 16
> PARAMETER C_BASEADDR = 0x83600000
> PARAMETER C_HIGHADDR = 0x8360ffff
> BUS_INTERFACE SPLB = plb
> PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
> PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
> PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
> PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
> PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
> PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
> PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
> END
>
> BEGIN mpmc
> PARAMETER INSTANCE = DDR_SDRAM
> PARAMETER HW_VER = 4.00.a
> PARAMETER C_NUM_PORTS = 3
> PARAMETER C_MEM_PARTNO = HYB25D512160BE-5
> PARAMETER C_MEM_DATA_WIDTH = 32
> PARAMETER C_MEM_DQS_WIDTH = 4
> PARAMETER C_MEM_DM_WIDTH = 4
> PARAMETER C_MEM_TYPE = DDR
> PARAMETER C_NUM_IDELAYCTRL = 2
> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
> PARAMETER C_PIM0_BASETYPE = 2
> PARAMETER C_PIM1_BASETYPE = 2
> PARAMETER C_PIM2_BASETYPE = 3
> PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
> PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
> PARAMETER C_MPMC_BASEADDR = 0x00000000
> PARAMETER C_MPMC_HIGHADDR = 0x07ffffff
> PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
> PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
> BUS_INTERFACE SPLB0 = ppc405_0_iplb1
> BUS_INTERFACE SPLB1 = ppc405_0_dplb1
> BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0
> BUS_INTERFACE SDMA_CTRL2 = plb
> PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
> PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
> PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
> PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
> PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
> PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
> PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
> PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
> PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
> PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
> PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
> PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
> PORT MPMC_Clk0 = sys_clk_s
> PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
> PORT SDMA2_Clk = sys_clk_s
> PORT MPMC_Clk_200MHz = clk_200mhz_s
> PORT MPMC_Rst = sys_periph_reset
> PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut
> PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut
> END
>
> BEGIN xps_ll_temac
> PARAMETER INSTANCE = TriMode_MAC_GMII
> PARAMETER HW_VER = 1.01.a
> PARAMETER C_SPLB_CLK_PERIOD_PS = 10000
> PARAMETER C_PHY_TYPE = 1
> PARAMETER C_NUM_IDELAYCTRL = 4
> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
> PARAMETER C_TEMAC_TYPE = 1
> PARAMETER C_BUS2CORE_CLK_RATIO = 1
> PARAMETER C_BASEADDR = 0x81c00000
> PARAMETER C_HIGHADDR = 0x81c0ffff
> BUS_INTERFACE SPLB = plb
> BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0
> PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0
> PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
> PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
> PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
> PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0
> PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
> PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
> PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
> PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
> PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0
> PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0
> PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
> PORT GTX_CLK_0 = temac_clk_s
> PORT REFCLK = clk_200mhz_s
> PORT LlinkTemac0_CLK = sys_clk_s
> PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt
> END
>
> BEGIN util_bus_split
> PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_SIZE_IN = 7
> PARAMETER C_LEFT_POS = 0
> PARAMETER C_SPLIT = 6
> PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA
> END
>
> BEGIN plb_v46
> PARAMETER INSTANCE = ppc405_0_iplb1
> PARAMETER HW_VER = 1.02.a
> PORT PLB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
>
> BEGIN plb_v46
> PARAMETER INSTANCE = ppc405_0_dplb1
> PARAMETER HW_VER = 1.02.a
> PORT PLB_Clk = sys_clk_s
> PORT SYS_Rst = sys_bus_reset
> END
>
> BEGIN clock_generator
> PARAMETER INSTANCE = clock_generator_0
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_EXT_RESET_HIGH = 1
> PARAMETER C_CLKIN_FREQ = 100000000
> PARAMETER C_CLKOUT0_FREQ = 100000000
> PARAMETER C_CLKOUT0_BUF = TRUE
> PARAMETER C_CLKOUT0_PHASE = 0
> PARAMETER C_CLKOUT0_GROUP = DCM0
> PARAMETER C_CLKOUT1_FREQ = 100000000
> PARAMETER C_CLKOUT1_BUF = TRUE
> PARAMETER C_CLKOUT1_PHASE = 90
> PARAMETER C_CLKOUT1_GROUP = DCM0
> PARAMETER C_CLKOUT2_FREQ = 300000000
> PARAMETER C_CLKOUT2_BUF = TRUE
> PARAMETER C_CLKOUT2_PHASE = 0
> PARAMETER C_CLKOUT2_GROUP = DCM0
> PARAMETER C_CLKOUT3_FREQ = 200000000
> PARAMETER C_CLKOUT3_BUF = TRUE
> PARAMETER C_CLKOUT3_PHASE = 0
> PARAMETER C_CLKOUT3_GROUP = NONE
> PARAMETER C_CLKOUT4_FREQ = 125000000
> PARAMETER C_CLKOUT4_BUF = TRUE
> PARAMETER C_CLKOUT4_PHASE = 0
> PARAMETER C_CLKOUT4_GROUP = NONE
> PORT CLKOUT0 = sys_clk_s
> PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s
> PORT CLKOUT2 = proc_clk_s
> PORT CLKOUT3 = clk_200mhz_s
> PORT CLKOUT4 = temac_clk_s
> PORT CLKIN = dcm_clk_s
> PORT LOCKED = Dcm_all_locked
> PORT RST = net_gnd
> END
>
> BEGIN proc_sys_reset
> PARAMETER INSTANCE = proc_sys_reset_0
> PARAMETER HW_VER = 2.00.a
> PARAMETER C_EXT_RESET_HIGH = 0
> BUS_INTERFACE RESETPPC0 = ppc_reset_bus
> PORT Slowest_sync_clk = sys_clk_s
> PORT Dcm_locked = Dcm_all_locked
> PORT Ext_Reset_In = sys_rst_s
> PORT Bus_Struct_Reset = sys_bus_reset
> PORT Peripheral_Reset = sys_periph_reset
> END
>
> BEGIN xps_intc
> PARAMETER INSTANCE = xps_intc_0
> PARAMETER HW_VER = 1.00.a
> PARAMETER C_BASEADDR = 0x81800000
> PARAMETER C_HIGHADDR = 0x8180ffff
> BUS_INTERFACE SPLB = plb
> PORT Irq = EICC405EXTINPUTIRQ
> PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut & DDR_SDRAM_SDMA2_Tx_IntOut
> END
>
>
>
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "xlnx,virtex";
> model = "testing";
> DDR_SDRAM: memory@0 {
> device_type = "memory";
> reg = < 0 8000000 >;
> } ;
> chosen {
> bootargs = "console=ttyS0,9600 ip=on nfsroot=172.16.40.76:/v2pclients/jhl26,tcp";
> linux,stdout-path = "/plb@0/serial@83e00000";
> } ;
> cpus {
> #address-cells = <1>;
> #cpus = <1>;
> #size-cells = <0>;
> ppc405_0: cpu@0 {
> clock-frequency = <11e1a300>;
> compatible = "PowerPC,405", "ibm,ppc405";
> d-cache-line-size = <20>;
> d-cache-size = <4000>;
> device_type = "cpu";
> i-cache-line-size = <20>;
> i-cache-size = <4000>;
> model = "PowerPC,405";
> reg = <0>;
> timebase-frequency = <11e1a300>;
> xlnx,apu-control = <de00>;
> xlnx,apu-udi-1 = <a18983>;
> xlnx,apu-udi-2 = <a38983>;
> xlnx,apu-udi-3 = <a589c3>;
> xlnx,apu-udi-4 = <a789c3>;
> xlnx,apu-udi-5 = <a98c03>;
> xlnx,apu-udi-6 = <ab8c03>;
> xlnx,apu-udi-7 = <ad8c43>;
> xlnx,apu-udi-8 = <af8c43>;
> xlnx,deterministic-mult = <0>;
> xlnx,disable-operand-forwarding = <1>;
> xlnx,fastest-plb-clock = "DPLB0";
> xlnx,generate-plb-timespecs = <1>;
> xlnx,mmu-enable = <1>;
> xlnx,pvr-high = <0>;
> xlnx,pvr-low = <0>;
> } ;
> } ;
> plb: plb@0 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "xlnx,plb-v46-1.02.a";
> ranges ;
> IIC_EEPROM: i2c@81600000 {
> compatible = "xlnx,xps-iic-2.00.a";
> interrupt-parent = <&xps_intc_0>;
> interrupts = < 4 2 >;
> reg = < 81600000 10000 >;
> xlnx,clk-freq = <5f5e100>;
> xlnx,family = "virtex4";
> xlnx,gpo-width = <1>;
> xlnx,iic-freq = <186a0>;
> xlnx,scl-inertial-delay = <0>;
> xlnx,sda-inertial-delay = <0>;
> xlnx,ten-bit-adr = <0>;
> } ;
> LEDs_4Bit: gpio@81400000 {
> compatible = "xlnx,xps-gpio-1.00.a";
> interrupt-parent = <&xps_intc_0>;
> interrupts = < 5 2 >;
> reg = < 81400000 10000 >;
> xlnx,all-inputs = <0>;
> xlnx,all-inputs-2 = <0>;
> xlnx,dout-default = <0>;
> xlnx,dout-default-2 = <0>;
> xlnx,family = "virtex4";
> xlnx,gpio-width = <4>;
> xlnx,interrupt-present = <1>;
> xlnx,is-bidir = <1>;
> xlnx,is-bidir-2 = <1>;
> xlnx,is-dual = <0>;
> xlnx,tri-default = <ffffffff>;
> xlnx,tri-default-2 = <ffffffff>;
> } ;
> RS232_Uart: serial@83e00000 {
> compatible = "xlnx,xps-uart16550-2.00.a";
> // compatible = "ns16550";
> device_type = "serial";
> interrupt-parent = <&xps_intc_0>;
> interrupts = < 6 2 >;
> reg = < 83e00000 10000 >;
> current-speed = <d#9600>;
> clock-frequency = <d#100000000>; /* added by jhl */
> reg-shift = <2>;
> xlnx,family = "virtex4";
> xlnx,has-external-rclk = <0>;
> xlnx,has-external-xin = <0>;
> xlnx,is-a-16550 = <1>;
> } ;
> SysACE_CompactFlash: sysace@83600000 {
> compatible = "xlnx,xps-sysace-1.00.a";
> interrupt-parent = <&xps_intc_0>;
> interrupts = < 3 2 >;
> reg = < 83600000 10000 >;
> xlnx,family = "virtex4";
> xlnx,mem-width = <10>;
> } ;
> TriMode_MAC_GMII: xps-ll-temac@81c00000 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "xlnx,compound";
> ethernet@81c00000 {
> compatible = "xlnx,xps-ll-temac-1.01.a";
> device_type = "network";
> interrupt-parent = <&xps_intc_0>;
> interrupts = < 2 2 >;
> llink-connected = <&PIM2>;
> local-mac-address = [ 02 00 00 00 00 01 ];
> reg = < 81c00000 40 >;
> xlnx,bus2core-clk-ratio = <1>;
> xlnx,phy-type = <1>;
> xlnx,phyaddr = <1>;
> xlnx,rxcsum = <0>;
> xlnx,rxfifo = <1000>;
> xlnx,temac-type = <1>;
> xlnx,txcsum = <0>;
> xlnx,txfifo = <1000>;
> } ;
> } ;
> mpmc@0 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "xlnx,mpmc-4.00.a";
> PIM2: sdma@84600100 {
> compatible = "xlnx,ll-dma-1.00.a";
> interrupt-parent = <&xps_intc_0>;
> interrupts = < 1 2 0 2 >;
> reg = < 84600100 80 >;
> } ;
> } ;
> xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
> compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
> reg = < ffffe000 2000 >;
> xlnx,family = "virtex4";
> } ;
> xps_intc_0: interrupt-controller@81800000 {
> #interrupt-cells = <2>;
> compatible = "xlnx,xps-intc-1.00.a";
> interrupt-controller ;
> reg = < 81800000 10000 >;
> xlnx,num-intr-inputs = <7>;
> } ;
> } ;
> ppc405_0_dplb1: plb@1 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "xlnx,plb-v46-1.02.a";
> ranges ;
> } ;
> } ;
>
>
>
> -----Original Message-----
> From: Magnus Hjorth [mailto:mh@omnisys.se]
> Sent: Saturday, March 29, 2008 6:54 AM
> To: git
> Cc: linuxppc-embedded@ozlabs.org
> Subject: Xilinx LLTEMAC driver issues
>
> Hi,
>
> I'm having some networking troubles with the Xilinx LLTEMAC driver from the
> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
> xps_ll_temac v1.00.b
>
> The weird thing is, that it sort of half works. It successfully makes a DHCP
> request and gets its IP address. I tried setting up a tftpd server, and I can
> see UDP requests coming in but the response doesn't seem to come out. I also
> tried running a TCP server on the board, and it can see and accept incoming
> connections but after that no data seems to get through. I can ping out and
> get around 40% packet loss.
>
> Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
> interrupts. No eth0 interrupts but that seems to be OK judging by the driver
> source comments. Ifconfig shows no collistions, no dropped packets, no errors,
> so the system seems to think that everything is OK.
>
> Clues anyone? I'm starting to run out of ideas...
>
> Best regards,
> Magnus
>
>
> --
>
> Magnus Hjorth, M.Sc.
> Omnisys Instruments AB
> Gruvgatan 8
> SE-421 30 Västra Frölunda, SWEDEN
> Phone: +46 31 734 34 09
> Fax: +46 31 734 34 29
> http://www.omnisys.se
^ permalink raw reply
* Re: [PATCH 15/18] ide: remove broken/dangerous HDIO_[UNREGISTER, SCAN]_HWIF ioctls
From: Bartlomiej Zolnierkiewicz @ 2008-03-29 16:03 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: linux-ide, linux-kernel, linuxppc-dev
In-Reply-To: <47EBDBAA.2020308@ru.mvista.com>
On Thursday 27 March 2008, Sergei Shtylyov wrote:
[...]
> > Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
>
> Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Thanks for reviewing it.
> > Index: b/drivers/ide/ide-pnp.c
> > ===================================================================
> > --- a/drivers/ide/ide-pnp.c
> > +++ b/drivers/ide/ide-pnp.c
> [...]
> > @@ -655,52 +530,6 @@ void ide_init_port_hw(ide_hwif_t *hwif,
> > }
> > EXPORT_SYMBOL_GPL(ide_init_port_hw);
> >
> > -/**
> > - * ide_register_hw - register IDE interface
> > - * @hw: hardware registers
> > - * @quirkproc: quirkproc function
> > - * @hwifp: pointer to returned hwif
> > - *
> > - * Register an IDE interface, specifying exactly the registers etc.
> > - *
> > - * Returns -1 on error.
> > - */
> > -
> > -static int ide_register_hw(hw_regs_t *hw, void (*quirkproc)(ide_drive_t *),
> > - ide_hwif_t **hwifp)
> > -{
> > - int index, retry = 1;
> > - ide_hwif_t *hwif;
> > - u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
> > -
> > - do {
> > - hwif = ide_find_port(hw->io_ports[IDE_DATA_OFFSET]);
> > - index = hwif->index;
> > - if (hwif)
> > - goto found;
>
> Hm, I remember there was a patch that fixed the above bug where hwif is
> dereferenced before being checked for NULL, I wonder how come it was lost?
It has been already merged into Linus' tree
(commit 0c6025d44448bd688dfd351a09bc620aafa4d1ff).
Thanks,
Bart
^ permalink raw reply
* Re: [PATCH 15/18] ide: remove broken/dangerous HDIO_[UNREGISTER, SCAN]_HWIF ioctls
From: Bartlomiej Zolnierkiewicz @ 2008-03-29 16:10 UTC (permalink / raw)
To: Mark Lord; +Cc: linux-ide, linux-kernel, linuxppc-dev
In-Reply-To: <47ED439C.9030400@rtr.ca>
On Friday 28 March 2008, Mark Lord wrote:
> Sergei Shtylyov wrote:
> > Bartlomiej Zolnierkiewicz wrote:
> >
> >> hdparm explicitely marks HDIO_[UNREGISTER,SCAN]_HWIF ioctls as DANGEROUS
> >> and given the number of bugs we can assume that there are no real users:
> ..
>
> There is the odd user of these, actually.
>
> But the most recent to email me (a few weeks ago),
> reported that the SCAN function was no longer working on his kernel.
>
> I'll remove the -R and -U flags completely from hdparm-8.7.
This will be quite helpful, thanks!
Bart
^ permalink raw reply
* Re: [PATCH 4/9] [POWERPC] mv64x60: Fix FDT compatible names: mv64x60 => mv64360
From: Olof Johansson @ 2008-03-29 21:57 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, paulus
In-Reply-To: <20080328234704.GD30214@farnsworth.org>
On Fri, Mar 28, 2008 at 04:47:04PM -0700, Dale Farnsworth wrote:
> From: Mark A. Greer <mgreer@mvista.com>
>
> Compatible names should refer to a specific version of the hardware,
> without wildcards. Change each instance of mv64x60 to mv64360, which
> is the oldest version we currently support.
Actually, it's normal to have more than one compatible field, from
specific to generic. So it should make sense to have both (with the
64360 entry first).
-Olof
^ permalink raw reply
* Re: [PATCH 6/9] [POWERPC] prpmc2800: clean up dts properties
From: Olof Johansson @ 2008-03-29 21:59 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, paulus
In-Reply-To: <20080328234900.GF30214@farnsworth.org>
On Fri, Mar 28, 2008 at 04:49:00PM -0700, Dale Farnsworth wrote:
> From: Mark A. Greer <mgreer@mvista.com>
>
> Remove several unused (or software config only) properties.
> Rename marvel node to "soc". Technically, it's not an SOC,
> but its organization is the same as an SOC. Also, rename the
> "block-index" property to "cell-index" to conform to current
> practice.
I see this rename as purely misleading. It isn't an soc, so it shouldn't
be named as such. Call it system-controller or something. Pretty much
any other name is better. :-)
-Olof
^ permalink raw reply
* Re: [PATCH v2] [POWERPC] 85xx: Add support for relocatble kernel (and booting at non-zero)
From: Stephen Rothwell @ 2008-03-29 23:51 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, linux-next
In-Reply-To: <Pine.LNX.4.64.0803290834300.4672@blarg.am.freescale.net>
[-- Attachment #1: Type: text/plain, Size: 610 bytes --]
Hi Kumar,
On Sat, 29 Mar 2008 08:34:49 -0500 (CDT) Kumar Gala <galak@kernel.crashing.org> wrote:
>
> The alignment compile check broke building on ppc32 (pmac, etc) since
> CONFIG_PHYSICAL_ALIGN isn't defined there.
OK, so that explains why linux-next failed to build for 32 bit powerpc
yesterday. In the future, please do not put things that are this
experimental into your powerpc-next branch as it impacts the testing of
everything else that is destined for the next merge window ...
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH][NEWEMAC] Fix section mismatch warnings
From: Benjamin Herrenschmidt @ 2008-03-30 1:36 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, netdev
In-Reply-To: <20080302163732.7c3af536@vader.jdub.homelinux.org>
On Sun, 2008-03-02 at 16:37 -0600, Josh Boyer wrote:
> This patch fixes several section mismatch warnings in the
> ibm_newemac driver similar to:
>
> WARNING: vmlinux.o(.devinit.text+0x3a04): Section mismatch in reference from the function emac_probe() to the function .devexit.text:tah_detach()
> The function __devinit emac_probe() references
> a function __devexit tah_detach().
>
> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Ack.
> ---
> drivers/net/ibm_newemac/core.c | 2 +-
> drivers/net/ibm_newemac/mal.c | 4 ++--
> drivers/net/ibm_newemac/rgmii.c | 2 +-
> drivers/net/ibm_newemac/tah.c | 2 +-
> drivers/net/ibm_newemac/zmii.c | 2 +-
> 5 files changed, 6 insertions(+), 6 deletions(-)
>
> --- linux-2.6.orig/drivers/net/ibm_newemac/core.c
> +++ linux-2.6/drivers/net/ibm_newemac/core.c
> @@ -2230,7 +2230,7 @@ static int __devinit emac_of_bus_notify(
> return 0;
> }
>
> -static struct notifier_block emac_of_bus_notifier = {
> +static struct notifier_block emac_of_bus_notifier __devinitdata = {
> .notifier_call = emac_of_bus_notify
> };
>
> --- linux-2.6.orig/drivers/net/ibm_newemac/mal.c
> +++ linux-2.6/drivers/net/ibm_newemac/mal.c
> @@ -61,8 +61,8 @@ int __devinit mal_register_commac(struct
> return 0;
> }
>
> -void __devexit mal_unregister_commac(struct mal_instance *mal,
> - struct mal_commac *commac)
> +void mal_unregister_commac(struct mal_instance *mal,
> + struct mal_commac *commac)
> {
> unsigned long flags;
>
> --- linux-2.6.orig/drivers/net/ibm_newemac/rgmii.c
> +++ linux-2.6/drivers/net/ibm_newemac/rgmii.c
> @@ -179,7 +179,7 @@ void rgmii_put_mdio(struct of_device *of
> mutex_unlock(&dev->lock);
> }
>
> -void __devexit rgmii_detach(struct of_device *ofdev, int input)
> +void rgmii_detach(struct of_device *ofdev, int input)
> {
> struct rgmii_instance *dev = dev_get_drvdata(&ofdev->dev);
> struct rgmii_regs __iomem *p = dev->base;
> --- linux-2.6.orig/drivers/net/ibm_newemac/tah.c
> +++ linux-2.6/drivers/net/ibm_newemac/tah.c
> @@ -35,7 +35,7 @@ int __devinit tah_attach(struct of_devic
> return 0;
> }
>
> -void __devexit tah_detach(struct of_device *ofdev, int channel)
> +void tah_detach(struct of_device *ofdev, int channel)
> {
> struct tah_instance *dev = dev_get_drvdata(&ofdev->dev);
>
> --- linux-2.6.orig/drivers/net/ibm_newemac/zmii.c
> +++ linux-2.6/drivers/net/ibm_newemac/zmii.c
> @@ -189,7 +189,7 @@ void zmii_set_speed(struct of_device *of
> mutex_unlock(&dev->lock);
> }
>
> -void __devexit zmii_detach(struct of_device *ofdev, int input)
> +void zmii_detach(struct of_device *ofdev, int input)
> {
> struct zmii_instance *dev = dev_get_drvdata(&ofdev->dev);
>
^ permalink raw reply
* 8543 console baud rate change problem
From: Dan Wilson @ 2008-03-30 2:13 UTC (permalink / raw)
To: linuxppc-embedded
We are using ELDK 4.1, linux kernel 2.6.22 on an 8543 board with a Layer
2 switch on it (i.e., the actual packet switching is done in an external
chip, not by the 8543 itself). One of our customers has encountered a
strange issue with system console baud rate changes. The system console
is connected to a UART port on the 8543.
Here is the sequence of events:
+ powercycle unit at 115200
+ have ping session going
+ establish telnet session
+ have L2 traffic traversing the switch
+ switch baud rate to any other baud rate beside 38400
+ hit a few returns
+ switch baud rate back to 115200 and no problem
+ switch baud rate to 38400
+ type a few char
+ switch baud rate back to 115200
+ console is not responsive
+ existing ping session is still going
+ L2 traffic is still OK
+ telnet session disconnected and can not reconnect;
telnet session is being served by linux ip stack
+ Had to power cycle to get everything back
Thanks!
Dan
^ permalink raw reply
* 8543 console baud rate change problem
From: Dan Wilson @ 2008-03-30 2:30 UTC (permalink / raw)
To: linuxppc-embedded
We are using ELDK 4.1, linux kernel 2.6.22 on an 8543 board with a Layer
2 switch on it (i.e., the actual packet switching is done in an external
chip, not by the 8543 itself). One of our customers has encountered a
strange issue with system console baud rate changes. The system console
is connected to a UART port on the 8543.
Here is the sequence of events:
+ powercycle unit at 115200
+ have ping session going
+ establish telnet session
+ have L2 traffic traversing the switch
+ switch baud rate to any other baud rate beside 38400
+ hit a few returns
+ switch baud rate back to 115200 and no problem
+ switch baud rate to 38400
+ type a few char
+ switch baud rate back to 115200
+ console is not responsive
+ existing ping session is still going
+ L2 traffic is still OK
+ telnet session disconnected and can not reconnect;
telnet session is being served by linux ip stack
+ Had to power cycle to get everything back
Thanks!
Dan
^ permalink raw reply
* segment fault problem
From: 刘小双 @ 2008-03-30 9:34 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1.1: Type: text/plain, Size: 516 bytes --]
hi, all
My platform is mpc8540 with graphics chip Fujitsu MB86296, my kernel version
is 2.6.12.6. I compiled DirectFB with gfxdriver mb86296, I wrote this
gfxdriver myself. Then I run a program named "simple" in
DFBTutorials-0.5.0which I downloaded from
directfb.org website. I want to see if the gfxdriver worked well. When I run
./simple there is a segment fault problem, and I don't how to fix it.
The attachment mb86296 is the gfxdriver.
The attachment simple.c is part of DFBTutorials-0.5.0.
Thanks
liuxs
[-- Attachment #1.2: Type: text/html, Size: 897 bytes --]
[-- Attachment #2: simple.c --]
[-- Type: text/plain, Size: 5305 bytes --]
/*
DirectFB Tutorials
(c) Copyright 2000-2002 convergence integrated media GmbH.
(c) Copyright 2002 convergence GmbH.
All rights reserved.
Written by Denis Oliver Kropp <dok@directfb.org>,
Andreas Hundt <andi@fischlustig.de> and
Sven Neumann <neo@directfb.org>.
This file is subject to the terms and conditions of the MIT License:
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge,
publish, distribute, sublicense, and/or sell copies of the Software,
and to permit persons to whom the Software is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/**
* simple.c
*
* Simple fullscreen application that draws a horizontal line
*/
#include <stdio.h>
#include <unistd.h>
#include <directfb.h>
/*
* This is the super interface, it's the entry point to all functionality.
*/
static IDirectFB *dfb = NULL;
/*
* The primary surface, i.e. the "screen".
* In cooperative level DFSCL_FULLSCREEN it's the surface of the primary layer.
*/
static IDirectFBSurface *primary = NULL;
/*
* Store the width and height of the primary surface here to support all resolutions.
*/
static int screen_width = 0;
static int screen_height = 0;
/*
* An error checking macro for a call to DirectFB.
* It is suitable for very simple apllications or tutorials.
* In more sophisticated applications this general error checking should not be used.
*/
#define DFBCHECK(x...) \
{ \
DFBResult err = x; \
\
if (err != DFB_OK) \
{ \
fprintf( stderr, "%s <%d>:\n\t", __FILE__, __LINE__ ); \
DirectFBErrorFatal( #x, err ); \
} \
}
int main (int argc, char **argv)
{
/*
* A surface description is needed to create a surface.
*/
DFBSurfaceDescription dsc;
/*
* Initialize DirectFB passing argc and argv
* to support the standard DirectFB command line options.
*
* DirectFB command line options will be stripped out automatically.
*/
DFBCHECK (DirectFBInit (&argc, &argv));
printf("simple.c DirectFBInit() is called\n");
/*
* Create the super interface.
*/
DFBCHECK (DirectFBCreate (&dfb));
printf("simple.c DirectFBCreate() is called\n");
/*
* We want to go fullscreen,
* the primary surface will be exclusive access to the surface of the primary layer.
*
* If you disable this call a window will be created implicitly,
* no further changes needed, flipping the surface updates the window.
*/
DFBCHECK (dfb->SetCooperativeLevel (dfb, DFSCL_FULLSCREEN));
/*
* 1. Specify which fields of the struct are set.
* 2. Fill out fields,
* in this example we want to have a flippable primary surface.
*/
dsc.flags = DSDESC_CAPS;
dsc.caps = DSCAPS_PRIMARY | DSCAPS_FLIPPING;
/*
* Create the primary surface by passing our surface description.
*/
DFBCHECK (dfb->CreateSurface( dfb, &dsc, &primary ));
printf("simple.c CreateSurface() is called \n");
/*
* We have exclusive access to the primary layer's surface now,
* get the width and height of the surface, i.e. the screen resolution.
*/
DFBCHECK (primary->GetSize (primary, &screen_width, &screen_height));
/*
* Clear the screen by filling a rectangle with the size of the surface.
* Default color is black, default drawing flags are DSDRAW_NOFX.
*/
DFBCHECK (primary->FillRectangle (primary, 0, 0, screen_width, screen_height));
/*
* Draw a horizontal line in the middle of the screen.
* Current color is black, so we have to set another one before.
*/
DFBCHECK (primary->SetColor (primary, 0x80, 0x80, 0xff, 0xff));
DFBCHECK (primary->DrawLine (primary,
0, screen_height / 2,
screen_width - 1, screen_height / 2));
/*
* Now flip the whole surface to make things visible.
*/
DFBCHECK (primary->Flip (primary, NULL, 0));
/*
* Wait a bit to see the result before exiting the example application.
*/
sleep (5);
/*
* Cleanup in a stack like style.
*/
primary->Release( primary );
dfb->Release( dfb );
return 23;
}
[-- Attachment #3: mb86296.rar --]
[-- Type: application/octet-stream, Size: 61566 bytes --]
^ permalink raw reply
* Re: [PATCH 6/9] [POWERPC] prpmc2800: clean up dts properties
From: David Gibson @ 2008-03-30 10:11 UTC (permalink / raw)
To: Olof Johansson; +Cc: paulus, linuxppc-dev
In-Reply-To: <20080329215942.GB27226@lixom.net>
On Sat, Mar 29, 2008 at 04:59:42PM -0500, Olof Johansson wrote:
> On Fri, Mar 28, 2008 at 04:49:00PM -0700, Dale Farnsworth wrote:
> > From: Mark A. Greer <mgreer@mvista.com>
> >
> > Remove several unused (or software config only) properties.
> > Rename marvel node to "soc". Technically, it's not an SOC,
> > but its organization is the same as an SOC. Also, rename the
> > "block-index" property to "cell-index" to conform to current
> > practice.
>
> I see this rename as purely misleading. It isn't an soc, so it shouldn't
> be named as such. Call it system-controller or something. Pretty much
> any other name is better. :-)
I agree. system-controller, host-bridge, north-bridge, maybe, but not
soc. With current conventions, the node name is primarily for the
benefit of human readers, so if it misleads it has failed entirely in
its purpose.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* mmu_hash_lock deadlock causes kernel stuck at 2.6.21 SMP powerpc 32bit
From: Gaash Hazan @ 2008-03-30 11:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: gaash-ppclnx, gilad
Hello PPC SMP MM experts,
mmu_hash_lock (arch/powerpc/mm/hash_low_32.S) is a
(non-standard) spin lock that protects the CPU MMU
hashing table. It exists and used only with SMP
configurations.
In some scenarios, the spin lock is taken when
interrupts are *enabled* causing kernel deadlock at
the next take attempt in the same CPU.
The deadlock happened on 2.6.21 kernel, Powerpc 32 bit
with SMP enabled. At this moment system had one active
CPU. The sequence I saw was:
do_exit (program termination)
exit_mm
mmput
exit_mmap
free_pgtables
free_pgd_range
unmap_vmas
pte_free
hash_page_sync (takes mmu_hash_lock. Note: interrupts
are enabled)
timer_interrupt (timer interrupts occurs during
hash_page_sync, lock is taken)
irq_exit
do_softirq
__do_softirq
net_rx_action (packet received from network)
( ... omitted ... )
xdr_skb_read_bits
skb_copy_bits
memcpy - memcpy causes DSI exception(0x300). This is
OK.
DSI exception handler calls hash_page
hash_page waits for mmu_mash_lock. It waits forever
since the lock is already taken.
Deadlock! with interrupts disabled. kernel is dead.
I think the rout cause of the problem is
hash_page_sync() taking the mmu_hash_lock spin lock
without disabling interrupts. This leads to the
deadlock.
To verify the theory, hash_page_sync() was wrapped
with interrupts disabled code and problem never
occurred again. Of course this is temporary workaround
as there are several places needed to be fixed.
What do you think?
Thanks,
Gaash
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox