* Re: [PATCH] [POWERPC] i2c: fix build breakage introduced by OF helpers
From: Paul Mackerras @ 2008-04-19 5:22 UTC (permalink / raw)
To: David Miller; +Cc: sfr, linux-kernel, linuxppc-dev, i2c, scottwood, khali
In-Reply-To: <20080418.210933.01471700.davem@davemloft.net>
David Miller writes:
> From: Paul Mackerras <paulus@samba.org>
> Date: Sat, 19 Apr 2008 14:04:32 +1000
>
> > Jochen Friedrich writes:
> >
> > > Fix build breakage introduced in commit
> > > "[POWERPC] i2c: OF helpers for the i2c API".
> > > If i2c-core is compiled as module, the helper needs to be
> > > compiled as module, as well. Rename i2c.c to of_i2c.c to
> > > avoid name space conflict.
> >
> > Actually, since only powerpc has irq_of_parse_and_map, I'm now
> > inclined to think that drivers/of/i2c.c should live under arch/powerpc
> > for now, or at the least its option should depend on PPC_OF.
>
> I specifically asked for this to not be PPC only so that I
> can make use of this infrastructure on sparc64 for I2C devices.
OK.
> It's OK if this breaks the sparc64 allmodconfig build, I'll take
> care of this once it's merged in.
It breaks the sparc32 allmodconfig build, which seems to be a
concern. How do you suggest we fix that?
> Please merge the PPC tree to Linus soon, so that I can merge
> in my sparc64 NUMA bits which depend upon the LMB changesets
> in the PPC tree.
Sure, it's just this sparc32 breakage which is holding me up.
Paul.
^ permalink raw reply
* RE: XPS_LL_TEMAC works correctly?
From: Mohammad Sadegh Sadri @ 2008-04-19 5:06 UTC (permalink / raw)
To: Rick Moleres, Rami WEHBI, linuxppc-embedded
In-Reply-To: <20080414154236.64322C88074@mail166-sin.bigfish.com>
I solved the problem,=20
As i said,=20
problem was : kernel could easily mount the root file system on NFS and beg=
in init , but after that every thing stopped and there was no more progress=
.=20
My problem was with the kernel command line parameters :=20
console=3DttyUL0 console=3Dtty0 root=3D/dev/nfs.......
the second console parameter was the source of the problem, when init is ex=
ecuted, the second parameter caused no more messages to be written on the s=
creen.
I tested using both LL_TEMAC 1.00a and 1.00b , both work well.=20
thanks.
________________________________
> Subject: RE: XPS_LL_TEMAC works correctly?
> Date: Mon, 14 Apr 2008 09:42:33 -0600
> From: Rick.Moleres@xilinx.com
> To: mamsadegh@hotmail.com; rwehbi@wirecom-tech.com; linuxppc-embedded@ozl=
abs.org
>=20
>=20
> There are a couple of bugs in the v1.00b version of xps_ll_temac (one in =
checksum offload, one in multicast address reception). You should try drop=
ping back to v1.00a of the core and give that a try, or if you have EDK 10.=
1 you can move to v1.01a of the core.
>=20
>=20
>=20
> -Rick
>=20
>=20
>=20
> ________________________________
>=20
> From: linuxppc-embedded-bounces+moleres=3Dxilinx.com@ozlabs.org [mailto:l=
inuxppc-embedded-bounces+moleres=3Dxilinx.com@ozlabs.org] On Behalf Of Moha=
mmad Sadegh Sadri
> Sent: Monday, April 14, 2008 3:10 AM
> To: Rami WEHBI; linuxppc-embedded@ozlabs.org
> Subject: RE: XPS_LL_TEMAC works correctly?
>=20
>=20
>=20
> Rami,
>=20
> Thanks for reply,
>=20
> But if u study the kernel log I posted carefully, you can simply see that=
Kernel has mounted the root file system,
> Look at this line in my prev post : VFS: Mounted root (nfs filesystem). t=
hen init has began and after that nothing more happens.
>=20
> the NFS is working correctly and the folder can be mounted easily from ot=
her computers. I personally think that the problem can be with NFS or the r=
oot file system of ELDK.
>=20
> I have done the same things with older versions of EDK using PLB_TEMAC an=
d every thing has worked correctly.
>=20
>=20
> ________________________________
>=20
> Subject: RE: XPS_LL_TEMAC works correctly?
> Date: Mon, 14 Apr 2008 10:31:31 +0200
> From: rwehbi@wirecom-tech.com
> To: mamsadegh@hotmail.com
>=20
> Hi,
>=20
>=20
>=20
> I would suggest that you verify that your system file is already mounted =
on the host PC (where your server NFS is installed), and that the /etc/expo=
rts file (configuration file of the nfs server) permit to your board to mou=
nt the system file.
>=20
>=20
>=20
> example of an /etc/exports file:
>=20
>=20
>=20
> /opt/ml403/rootfs
>=20
> 192.168.206.223/24(rw,no_root_squash,sync,subtree_check)
>=20
>=20
>=20
> where the ip addresse is that of nfs client, and the path indicates where=
I mounted the system file.
>=20
>=20
>=20
> Good luck,
>=20
>=20
>=20
> Rami
>=20
>=20
>=20
> ________________________________
>=20
> De : linuxppc-embedded-bounces+rami.wehbi=3Dwirecom-tech.com@ozlabs.org [=
mailto:linuxppc-embedded-bounces+rami.wehbi=3Dwirecom-tech.com@ozlabs.org] =
De la part de Mohammad Sadegh Sadri
> Envoy=E9 : lundi 14 avril 2008 10:16
> =C0 : linuxppc-embedded@ozlabs.org
> Objet : XPS_LL_TEMAC works correctly?
>=20
> Hi all,
>=20
> Using:
> EDK 9.2.02,
> Xilinx Linux 2.6.24-rc8-xlnx
> XPS_LL_TEMAC version 1.00.b
>=20
> I bring up the Linux kernel on ML403 -Rev04 board,
> LL_TEMAC buffer size 128kbits, and set to use SG DMA
>=20
> I encounter the following messages when the kernel wants to mount the roo=
t file system, as one can see the kernel has mounter the nfs root file syst=
em and init is initiated, but after that a Link carrier lost happens and it=
stops working.
>=20
> is this behavior natural? ( the PC has attansic gigabit ethernet port wit=
h kernel 2.6.24.4 running, nfs works very well in other tests)
>=20
> thanks
>=20
> .............
> eth0: XLlTemac: speed set to 1000Mb/s
> eth0: XLlTemac: Send Threshold =3D 24, Receive Threshold =3D 4
> eth0: XLlTemac: Send Wait bound =3D 254, Receive Wait bound =3D 254
> IP-Config: Complete:
> device=3Deth0, addr=3D10.10.10.11, mask=3D255.255.255.0, gw=3D10.10=
.10.10,
> host=3D10.10.10.11, domain=3D, nis-domain=3D(none),
> bootserver=3D10.10.10.10, rootserver=3D10.10.10.10, rootpath=3D
> Looking up port of RPC 100003/2 on 10.10.10.10
> Looking up port of RPC 100005/1 on 10.10.10.10
> VFS: Mounted root (nfs filesystem).
> Freeing unused kernel memory: 88k init
> eth0: XLlTemac: PHY Link carrier lost.
> eth0: XLlTemac: speed set to 1000Mb/s
> eth0: XLlTemac: PHY Link carrier restored.
> ( KERNEL STOPS WORKING HERE!!!!!!!!)
>=20
>=20
>=20
> ________________________________
>=20
> Sign in today. When you sign in to Windows Live Messenger you could win $=
1000 a day until May 12th. Learn more at SignInAndWIN.ca
>=20
>=20
>=20
> ________________________________
>=20
> Sign in now! Windows Live Messenger is giving you a chance to win $1000 a=
day until May 12th Check out SignInAndWIN.ca today!
_________________________________________________________________
Find hidden words, unscramble celebrity names, or try the ultimate crosswor=
d puzzle with Live Search Games. Play now!
http://g.msn.ca/ca55/212=
^ permalink raw reply
* Re: [PATCH] [POWERPC] i2c: fix build breakage introduced by OF helpers
From: David Miller @ 2008-04-19 4:09 UTC (permalink / raw)
To: paulus; +Cc: sfr, linux-kernel, linuxppc-dev, i2c, scottwood, khali
In-Reply-To: <18441.28496.84724.411784@cargo.ozlabs.ibm.com>
From: Paul Mackerras <paulus@samba.org>
Date: Sat, 19 Apr 2008 14:04:32 +1000
> Jochen Friedrich writes:
>
> > Fix build breakage introduced in commit
> > "[POWERPC] i2c: OF helpers for the i2c API".
> > If i2c-core is compiled as module, the helper needs to be
> > compiled as module, as well. Rename i2c.c to of_i2c.c to
> > avoid name space conflict.
>
> Actually, since only powerpc has irq_of_parse_and_map, I'm now
> inclined to think that drivers/of/i2c.c should live under arch/powerpc
> for now, or at the least its option should depend on PPC_OF.
I specifically asked for this to not be PPC only so that I
can make use of this infrastructure on sparc64 for I2C devices.
It's OK if this breaks the sparc64 allmodconfig build, I'll take
care of this once it's merged in.
Please merge the PPC tree to Linus soon, so that I can merge
in my sparc64 NUMA bits which depend upon the LMB changesets
in the PPC tree.
Thanks.
^ permalink raw reply
* Re: [PATCH] [POWERPC] i2c: fix build breakage introduced by OF helpers
From: Paul Mackerras @ 2008-04-19 4:04 UTC (permalink / raw)
To: Jochen Friedrich
Cc: Stephen Rothwell, linuxppc-dev list, Kernel, Linux, Scott Wood,
Linux I2C, Jean Delvare, David Miller
In-Reply-To: <4808AEC7.8040000@scram.de>
Jochen Friedrich writes:
> Fix build breakage introduced in commit
> "[POWERPC] i2c: OF helpers for the i2c API".
> If i2c-core is compiled as module, the helper needs to be
> compiled as module, as well. Rename i2c.c to of_i2c.c to
> avoid name space conflict.
Actually, since only powerpc has irq_of_parse_and_map, I'm now
inclined to think that drivers/of/i2c.c should live under arch/powerpc
for now, or at the least its option should depend on PPC_OF.
Paul.
^ permalink raw reply
* Re: [PATCH 1/2] [v3][POWERPC] refactor dcr code
From: Benjamin Herrenschmidt @ 2008-04-19 3:04 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev
In-Reply-To: <fa686aa40804181930s724b2e11we01943236ec0b8a7@mail.gmail.com>
> By current conventions; these should probably be static functions (but
> don't make them inline). The compiler will do the right thing with
> them. Functions are easier to validate by the compiler and sparse
> than #defines.
Not necessarily... yes we tend to prefer functions, but in that case
which is 100% a renaming trick, macros are fine and somewhat simpler.
There is no type difference and the macro will not prevent type checking
here.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 2/2] [POWERPC] Xilinx: Virtex: Enable dcr for MMIO and NATIVE
From: Grant Likely @ 2008-04-19 2:31 UTC (permalink / raw)
To: Stephen Neuendorffer; +Cc: linuxppc-dev
In-Reply-To: <20080418215513.C8D1A44007F@mail114-dub.bigfish.com>
On Fri, Apr 18, 2008 at 3:55 PM, Stephen Neuendorffer
<stephen.neuendorffer@xilinx.com> wrote:
> FPGA designs may have need of both MMIO-based and NATIVE-based dcr
> interfaces.
>
> Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
> ---
> arch/powerpc/platforms/40x/Kconfig | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
> index a9260e2..b8e06df 100644
> --- a/arch/powerpc/platforms/40x/Kconfig
> +++ b/arch/powerpc/platforms/40x/Kconfig
> @@ -123,6 +123,8 @@ config 405GPR
>
> config XILINX_VIRTEX
> bool
> + select PPC_DCR_MMIO
> + select PPC_DCR_NATIVE
Yeah; we'll probably want to be more sophisticated about this in the
future; but for now...
Acked-by: Grant Likely <grant.likely@secretlab.ca>
(Paulus; but this does depend on patch 1 of this series)
>
> config XILINX_VIRTEX_II_PRO
> bool
> --
> 1.5.3.4-dirty
>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH 1/2] [v3][POWERPC] refactor dcr code
From: Grant Likely @ 2008-04-19 2:30 UTC (permalink / raw)
To: Stephen Neuendorffer; +Cc: linuxppc-dev
In-Reply-To: <20080418215513.ACA0C17F007A@mail131-dub.bigfish.com>
On Fri, Apr 18, 2008 at 3:55 PM, Stephen Neuendorffer
<stephen.neuendorffer@xilinx.com> wrote:
> Previously, dcr support was configured at compile time to either using
> MMIO or native dcr instructions. Although this works for most
> platforms, it fails on FPGA platforms:
>
> 1) Systems may include more than one dcr bus.
> 2) Systems may be native dcr capable and still use memory mapped dcr interface.
>
> This patch provides runtime support based on the device trees for the
> case where CONFIG_PPC_DCR_MMIO and CONFIG_PPC_DCR_NATIVE are both
> selected. Previously, this was a poorly defined configuration, which
> happened to provide NATIVE support. The runtime selection is made
> based on the dcr controller having a 'dcr-access-method' attribute
>
> in the device tree. If only one of the above options is selected,
> then the code uses #defines to select only the used code in order to
> avoid introducing overhead in existing usage.
I'm not really qualified to ack this patch, but it looks right to me;
except for one comment below (sorry I didn't get to looking at this
earlier).
> diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
> index 9338d50..6b86322 100644
> --- a/include/asm-powerpc/dcr.h
> +++ b/include/asm-powerpc/dcr.h
> @@ -20,14 +20,47 @@
> #ifndef _ASM_POWERPC_DCR_H
> #define _ASM_POWERPC_DCR_H
> #ifdef __KERNEL__
> +#ifndef __ASSEMBLY__
> #ifdef CONFIG_PPC_DCR
>
> #ifdef CONFIG_PPC_DCR_NATIVE
> #include <asm/dcr-native.h>
> -#else
> +#endif
> +
> +#ifdef CONFIG_PPC_DCR_MMIO
> #include <asm/dcr-mmio.h>
> #endif
>
> +#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
> +
> +#include <asm/dcr-generic.h>
> +
> +#define DCR_MAP_OK(host) dcr_map_ok_generic(host)
> +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
> +#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
> +#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
> +#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
> +
> +#else
> +
> +#ifdef CONFIG_PPC_DCR_NATIVE
> +typedef dcr_host_native_t dcr_host_t;
> +#define DCR_MAP_OK(host) dcr_map_ok_native(host)
> +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
> +#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
> +#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
> +#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
> +#else
> +typedef dcr_host_mmio_t dcr_host_t;
> +#define DCR_MAP_OK(host) dcr_map_ok_mmio(host)
> +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
> +#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
> +#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
> +#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
> +#endif
> +
> +#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
> +
By current conventions; these should probably be static functions (but
don't make them inline). The compiler will do the right thing with
them. Functions are easier to validate by the compiler and sparse
than #defines.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: pci issue - wrong detection of pci ressources
From: Benjamin Herrenschmidt @ 2008-04-19 0:51 UTC (permalink / raw)
To: Christian Ehrhardt; +Cc: linuxppc-dev, Detlev Zundel, Hollis Blanchard
In-Reply-To: <1208566122.6958.425.camel@pasglop>
On Sat, 2008-04-19 at 10:48 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2008-04-18 at 14:07 +0200, Christian Ehrhardt wrote:
> > => Region 2 is not detected with our kernel, this later break things
> > like radeonfb initialization.
>
> I'll need some information here:
>
> - Your device-tree (is that the base sequoia one ?)
> - Enable DEBUG in arch/powerpc/kernel/pci-common.c and pci_32.c
> - Send me the resulting dmesg log
> - Also include the output of /proc/iomem
Actually, there's a bug in radeonfb:
In radeonfb.h, try changing
unsigned long mmio_base_phys;
unsigned long fb_base_phys;
To
resource_size_t mmio_base_phys;
resource_size_t fb_base_phys;
And tell us if it makes a difference too.
Cheers,
Ben.
^ permalink raw reply
* Re: [EFIKA] Really, don't pretend to be CHRP
From: Benjamin Herrenschmidt @ 2008-04-19 0:53 UTC (permalink / raw)
To: David Woodhouse; +Cc: paulus, linuxppc-dev
In-Reply-To: <1208450247.9212.275.camel@pmac.infradead.org>
> OTOH, it probably wouldn't be _so_ hard to port Mitch's OpenFirmware to
> mpc5200...
Yup, especially since it's pretty much just a 603 core which I would
expect is already supported by firmworks stuff...
Ben.
^ permalink raw reply
* Re: pci issue - wrong detection of pci ressources
From: Benjamin Herrenschmidt @ 2008-04-19 0:48 UTC (permalink / raw)
To: Christian Ehrhardt; +Cc: linuxppc-dev, Detlev Zundel, Hollis Blanchard
In-Reply-To: <48088F02.2060806@linux.vnet.ibm.com>
On Fri, 2008-04-18 at 14:07 +0200, Christian Ehrhardt wrote:
> => Region 2 is not detected with our kernel, this later break things
> like radeonfb initialization.
I'll need some information here:
- Your device-tree (is that the base sequoia one ?)
- Enable DEBUG in arch/powerpc/kernel/pci-common.c and pci_32.c
- Send me the resulting dmesg log
- Also include the output of /proc/iomem
Thanks !
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] sysdev,mv64x60: initialization of mv64x60 ethernet, serial and I2C
From: Remi Machet @ 2008-04-19 0:31 UTC (permalink / raw)
To: Dale Farnsworth; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <20080418205815.GA21162@farnsworth.org>
Hi Dale,
Thanks for the comments, I will re-submit the patch on Monday without
the of_node_put and split in 2.
Remi
On Fri, 2008-04-18 at 13:58 -0700, Dale Farnsworth wrote:
> On Thu, Apr 17, 2008 at 04:35:55PM -0700, Remi Machet wrote:
> > This patch affects only the mv64x60 driver. It fixes 2 problem:
>
> Hi Remi,
>
> Thanks for finding and addressing these issues.
> BTW, since you're fixing 2 problems, you might split this into 2 patches.
>
> > -If one of the devices of the mv64x60 init fails, the remaining
> > devices are not initialized => I changed the code to display an
> > error and continue the initialization.
>
> I agree that this is a good idea. A small comment on details below.
>
> > -I2C parameters freq_m and freq_n are assigned default in the code
> > but if those properties are not found in the open firmware description
> > the init returns an error=> the code now uses the default
> > values if the properties are not found.
>
> Yes. Sigh, I can't believe I missed this.
>
> > diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
> > index 047b310..ef0fc99 100644
> > --- a/arch/powerpc/sysdev/mv64x60_dev.c
> > +++ b/arch/powerpc/sysdev/mv64x60_dev.c
> > @@ -433,9 +431,15 @@ static int __init mv64x60_device_setup(void)
> > int err;
> >
> > id = 0;
> > - for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc")
> > - if ((err = mv64x60_mpsc_device_setup(np, id++)))
> > - goto error;
> > + for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc") {
> > + err = mv64x60_mpsc_device_setup(np, id++);
> > + if (err) {
> > + printk(KERN_ERR "Failed to initialize MV64x60 " \
> > + "serial device %s: error %d.\n",
> > + np->full_name, err);
> > + of_node_put(np);
>
> This of_node_put call (and the others you added) are not needed.
>
> Thanks,
> -Dale
^ permalink raw reply
* [PATCH 04/15] [PPC] minor irq handler cleanups
From: Jeff Garzik @ 2008-04-18 23:22 UTC (permalink / raw)
To: vitb, linuxppc-dev; +Cc: Andrew Morton, LKML
In-Reply-To: <d7afbccda111e535bb14ad8082b208c7a2cd9833.1208559659.git.jgarzik@redhat.com>
- whitespace cleanups
- remove pointless prototype (uses always follow func implementation)
- 'irq' argument is often used purely as a local variable. rename
argument to 'dummy' and define 'irq' as local to make this plain.
- remove pointless casts from void*
This change's main purpose is to prepare for the patchset in
jgarzik/misc-2.6.git#irq-remove, that explores removal of the
never-used 'irq' argument in each interrupt handler.
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
---
arch/ppc/8xx_io/fec.c | 3 +--
arch/ppc/platforms/sbc82xx.c | 4 +++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/8xx_io/fec.c b/arch/ppc/8xx_io/fec.c
index 11b0aa6..d7b7ba9 100644
--- a/arch/ppc/8xx_io/fec.c
+++ b/arch/ppc/8xx_io/fec.c
@@ -199,7 +199,6 @@ static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
#ifdef CONFIG_USE_MDIO
static void fec_enet_mii(struct net_device *dev);
#endif /* CONFIG_USE_MDIO */
-static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
#ifdef CONFIG_FEC_PACKETHOOK
static void fec_enet_tx(struct net_device *dev, __u32 regval);
static void fec_enet_rx(struct net_device *dev, __u32 regval);
@@ -472,7 +471,7 @@ fec_timeout(struct net_device *dev)
* This is called from the MPC core interrupt.
*/
static irqreturn_t
-fec_enet_interrupt(int irq, void * dev_id)
+fec_enet_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
volatile fec_t *fecp;
diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c
index cc0935c..0df6aac 100644
--- a/arch/ppc/platforms/sbc82xx.c
+++ b/arch/ppc/platforms/sbc82xx.c
@@ -121,8 +121,10 @@ struct hw_interrupt_type sbc82xx_i8259_ic = {
.end = sbc82xx_i8259_end_irq,
};
-static irqreturn_t sbc82xx_i8259_demux(int irq, void *dev_id)
+static irqreturn_t sbc82xx_i8259_demux(int dummy, void *dev_id)
{
+ int irq;
+
spin_lock(&sbc82xx_i8259_lock);
sbc82xx_i8259_map[0] = 0x0c; /* OCW3: Read IR register on RD# pulse */
--
1.5.4.1
^ permalink raw reply related
* Re: [PATCH v2.6.26] powerpc: Add 8568 PHY workaround to board code
From: Anton Vorontsov @ 2008-04-18 22:59 UTC (permalink / raw)
To: Andy Fleming; +Cc: linuxppc-dev, jgarzik
In-Reply-To: <1208558149-6029-1-git-send-email-afleming@freescale.com>
On Fri, Apr 18, 2008 at 05:35:49PM -0500, Andy Fleming wrote:
> The 8568 MDS needs some configuration changes to the PHY in order to work
> properly. These are done in the firmware, normally, but Linux shouldn't
> need to rely on the firmware running such things (someone could disable
> the PHY support in the firmware to save space, for instance).
>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
>
> Jeff, copying you so you can see what code uses the board fixup patch. Also,
> Kumar, note that this patch is utterly useless without the patch sent to netdev:
> Add support for board-level PHY fixups.
>
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 114 +++++++++++++++++++++++++++++
> 1 files changed, 114 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> index 25f8bc7..b1bf06d 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
[...]
Hi Andy,
Just two fluffy comments...
> +static int __init board_fixups(void)
> +{
> + char phy_id[BUS_ID_SIZE];
> + struct device_node *mdio;
> + struct resource res;
> +
> + /* Register a workaround to fixup the clock source */
> + mdio = of_find_node_by_name(NULL, "mdio");
MPC8568E-MDS can use either one of two mdio buses, so I'd suggest to
do fixups for both via of_find_compatible_node(), or
for_each_compatible_node().
> + of_address_to_resource(mdio, 0, &res);
> + snprintf(phy_id, BUS_ID_SIZE, "%x:%02x", res.start, 1);
> +
> + phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
> + phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
> +
> + /* Register a workaround for errata */
> + snprintf(phy_id, BUS_ID_SIZE, "%x:%02x", res.start, 7);
> + phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
of_node_put(mdio); is missing here, I think.
> + return 0;
> +}
> +arch_initcall(board_fixups);
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* Re: RFC: MPC5200 PSC AC97 driver
From: Grant Likely @ 2008-04-18 22:53 UTC (permalink / raw)
To: Matt Sealey; +Cc: linuxppc-dev
In-Reply-To: <4808E469.9020408@genesi-usa.com>
On Fri, Apr 18, 2008 at 12:11 PM, Matt Sealey <matt@genesi-usa.com> wrote:
>
> Juergen Beisert wrote:
>
> >
> > On Friday 18 April 2008 17:43, Peter Czanik wrote:
> >
> > I'm not sure if "cell-index" is a correct property. I copied it from the
> uart driver, because this driver needs something to distinguish between PSC1
> and PSC2. Maybe there is a better and correct oftree solution? Any oftree
> expert here?
> >
>
> cell-index is correct by legacy, but I think it has been said by that you
> could
> just as well pick which PSC you are running on by it's address.
>
> I would prefer the address approach, but everyone's going to keep
> cell-index
> around anyway so why not leave it there and why not keep using it?
I was the one who started using cell-index in the first place; but
I've had a change of opinion and I think doing it by address would be
better. That being said, it doesn't hurt to have the cell-index
property in there. If/when we rework the drivers to use address, then
it will just be a harmless and superfluous property.
BTW, is anyone trying to shepherd this driver into the ALSA tree? Its
out of my area of expertise and responsibility, so I haven't been
pursuing it.
Cheers,
g.
>
>
> --
> Matt Sealey <matt@genesi-usa.com>
> Genesi, Manager, Developer Relations
>
> _______________________________________________
>
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* [PATCH] [POWERPC] mpc5200: Switch mpc5200 dts files to dts-v1 format
From: Grant Likely @ 2008-04-18 16:10 UTC (permalink / raw)
To: linuxppc-dev, m8
Update dts files to current format
From: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
---
arch/powerpc/boot/dts/cm5200.dts | 98 +++++++++++------------
arch/powerpc/boot/dts/lite5200.dts | 132 ++++++++++++++++----------------
arch/powerpc/boot/dts/lite5200b.dts | 146 +++++++++++++++++------------------
arch/powerpc/boot/dts/motionpro.dts | 118 ++++++++++++++--------------
arch/powerpc/boot/dts/tqm5200.dts | 80 ++++++++++---------
5 files changed, 286 insertions(+), 288 deletions(-)
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index c6ca631..2f74cc4 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -10,11 +10,7 @@
* option) any later version.
*/
-/*
- * WARNING: Do not depend on this tree layout remaining static just yet.
- * The MPC5200 device tree conventions are still in flux
- * Keep an eye on the linuxppc-dev mailing list for more details
- */
+/dts-v1/;
/ {
model = "schindler,cm5200";
@@ -29,10 +25,10 @@
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
- d-cache-line-size = <20>;
- i-cache-line-size = <20>;
- d-cache-size = <4000>; // L1, 16K
- i-cache-size = <4000>; // L1, 16K
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
@@ -41,34 +37,34 @@
memory {
device_type = "memory";
- reg = <00000000 04000000>; // 64MB
+ reg = <0x00000000 0x04000000>; // 64MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
- ranges = <0 f0000000 0000c000>;
- reg = <f0000000 00000100>;
+ ranges = <0 0xf0000000 0x0000c000>;
+ reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <200 38>;
+ reg = <0x200 0x38>;
};
- mpc5200_pic: pic@500 {
+ mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <500 80>;
+ reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <600 10>;
+ reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt;
@@ -76,108 +72,108 @@
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <610 10>;
- interrupts = <1 a 0>;
+ reg = <0x610 0x10>;
+ interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <620 10>;
- interrupts = <1 b 0>;
+ reg = <0x620 0x10>;
+ interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <630 10>;
- interrupts = <1 c 0>;
+ reg = <0x630 0x10>;
+ interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <640 10>;
- interrupts = <1 d 0>;
+ reg = <0x640 0x10>;
+ interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <650 10>;
- interrupts = <1 e 0>;
+ reg = <0x650 0x10>;
+ interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <660 10>;
- interrupts = <1 f 0>;
+ reg = <0x660 0x10>;
+ interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <670 10>;
- interrupts = <1 10 0>;
+ reg = <0x670 0x10>;
+ interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
- reg = <800 100>;
+ reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <b00 40>;
+ reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <c00 40>;
+ reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <f00 20>;
- interrupts = <2 d 0 2 e 0>;
+ reg = <0xf00 0x20>;
+ interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <1000 ff>;
+ reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <1200 80>;
+ reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 a 0 3 b 0
- 3 c 0 3 d 0 3 e 0 3 f 0>;
+ 3 8 0 3 9 0 3 10 0 3 11 0
+ 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <1f00 100>;
+ reg = <0x1f00 0x100>;
};
serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
- reg = <2000 100>;
+ reg = <0x2000 0x100>;
interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -186,7 +182,7 @@
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart";
port-number = <1>; // Logical port assignment
- reg = <2200 100>;
+ reg = <0x2200 0x100>;
interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -195,7 +191,7 @@
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart";
port-number = <2>; // Logical port assignment
- reg = <2400 100>;
+ reg = <0x2400 0x100>;
interrupts = <2 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -204,7 +200,7 @@
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <5>; // Logical port assignment
- reg = <2c00 100>;
+ reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -212,7 +208,7 @@
ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <3000 400>;
+ reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -223,7 +219,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <3000 400>; // fec range, since we need to setup fec interrupts
+ reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
@@ -237,15 +233,15 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <3d40 40>;
- interrupts = <2 10 0>;
+ reg = <0x3d40 0x40>;
+ interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
- reg = <8000 4000>;
+ reg = <0x8000 0x4000>;
};
};
@@ -254,12 +250,12 @@
compatible = "fsl,lpb";
#address-cells = <2>;
#size-cells = <1>;
- ranges = <0 0 fc000000 2000000>;
+ ranges = <0 0 0xfc000000 0x2000000>;
// 16-bit flash device at LocalPlus Bus CS0
flash@0,0 {
compatible = "cfi-flash";
- reg = <0 0 2000000>;
+ reg = <0 0 0x2000000>;
bank-width = <2>;
device-width = <2>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 09b4e16..2cf9a87 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -10,6 +10,8 @@
* option) any later version.
*/
+/dts-v1/;
+
/ {
model = "fsl,lite5200";
compatible = "fsl,lite5200";
@@ -23,10 +25,10 @@
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
- d-cache-line-size = <20>;
- i-cache-line-size = <20>;
- d-cache-size = <4000>; // L1, 16K
- i-cache-size = <4000>; // L1, 16K
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
@@ -35,21 +37,21 @@
memory {
device_type = "memory";
- reg = <00000000 04000000>; // 64MB
+ reg = <0x00000000 0x04000000>; // 64MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200-immr";
- ranges = <0 f0000000 0000c000>;
- reg = <f0000000 00000100>;
+ ranges = <0 0xf0000000 0x0000c000>;
+ reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200-cdm";
- reg = <200 38>;
+ reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
@@ -58,13 +60,13 @@
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200-pic";
- reg = <500 80>;
+ reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <0>;
- reg = <600 10>;
+ reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt;
@@ -73,63 +75,63 @@
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <1>;
- reg = <610 10>;
- interrupts = <1 a 0>;
+ reg = <0x610 0x10>;
+ interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <2>;
- reg = <620 10>;
- interrupts = <1 b 0>;
+ reg = <0x620 0x10>;
+ interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <3>;
- reg = <630 10>;
- interrupts = <1 c 0>;
+ reg = <0x630 0x10>;
+ interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <4>;
- reg = <640 10>;
- interrupts = <1 d 0>;
+ reg = <0x640 0x10>;
+ interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <5>;
- reg = <650 10>;
- interrupts = <1 e 0>;
+ reg = <0x650 0x10>;
+ interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <6>;
- reg = <660 10>;
- interrupts = <1 f 0>;
+ reg = <0x660 0x10>;
+ interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
cell-index = <7>;
- reg = <670 10>;
- interrupts = <1 10 0>;
+ reg = <0x670 0x10>;
+ interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200-rtc";
device_type = "rtc";
- reg = <800 100>;
+ reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -137,43 +139,43 @@
can@900 {
compatible = "fsl,mpc5200-mscan";
cell-index = <0>;
- interrupts = <2 11 0>;
+ interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
- reg = <900 80>;
+ reg = <0x900 0x80>;
};
can@980 {
compatible = "fsl,mpc5200-mscan";
cell-index = <1>;
- interrupts = <2 12 0>;
+ interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
- reg = <980 80>;
+ reg = <0x980 0x80>;
};
gpio@b00 {
compatible = "fsl,mpc5200-gpio";
- reg = <b00 40>;
+ reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@c00 {
compatible = "fsl,mpc5200-gpio-wkup";
- reg = <c00 40>;
+ reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
compatible = "fsl,mpc5200-spi";
- reg = <f00 20>;
- interrupts = <2 d 0 2 e 0>;
+ reg = <0xf00 0x20>;
+ interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
compatible = "fsl,mpc5200-ohci","ohci-be";
- reg = <1000 ff>;
+ reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -181,17 +183,17 @@
dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200-bestcomm";
- reg = <1200 80>;
+ reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 a 0 3 b 0
- 3 c 0 3 d 0 3 e 0 3 f 0>;
+ 3 8 0 3 9 0 3 10 0 3 11 0
+ 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
compatible = "fsl,mpc5200-xlb";
- reg = <1f00 100>;
+ reg = <0x1f00 0x100>;
};
serial@2000 { // PSC1
@@ -199,7 +201,7 @@
compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>;
- reg = <2000 100>;
+ reg = <0x2000 0x100>;
interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -208,7 +210,7 @@
//ac97@2200 { // PSC2
// compatible = "fsl,mpc5200-psc-ac97";
// cell-index = <1>;
- // reg = <2200 100>;
+ // reg = <0x2200 0x100>;
// interrupts = <2 2 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -217,7 +219,7 @@
//i2s@2400 { // PSC3
// compatible = "fsl,mpc5200-psc-i2s";
// cell-index = <2>;
- // reg = <2400 100>;
+ // reg = <0x2400 0x100>;
// interrupts = <2 3 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -227,8 +229,8 @@
// device_type = "serial";
// compatible = "fsl,mpc5200-psc-uart";
// cell-index = <3>;
- // reg = <2600 100>;
- // interrupts = <2 b 0>;
+ // reg = <0x2600 0x100>;
+ // interrupts = <2 11 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -237,8 +239,8 @@
// device_type = "serial";
// compatible = "fsl,mpc5200-psc-uart";
// cell-index = <4>;
- // reg = <2800 100>;
- // interrupts = <2 c 0>;
+ // reg = <0x2800 0x100>;
+ // interrupts = <2 12 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -246,7 +248,7 @@
//spi@2c00 { // PSC6
// compatible = "fsl,mpc5200-psc-spi";
// cell-index = <5>;
- // reg = <2c00 100>;
+ // reg = <0x2c00 0x100>;
// interrupts = <2 4 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -254,7 +256,7 @@
ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200-fec";
- reg = <3000 800>;
+ reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -265,11 +267,11 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200-mdio";
- reg = <3000 400>; // fec range, since we need to setup fec interrupts
+ reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
- phy0:ethernet-phy@1 {
+ phy0: ethernet-phy@1 {
device_type = "ethernet-phy";
reg = <1>;
};
@@ -278,7 +280,7 @@
ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200-ata";
- reg = <3a00 100>;
+ reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -288,8 +290,8 @@
#size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
- reg = <3d00 40>;
- interrupts = <2 f 0>;
+ reg = <0x3d00 0x40>;
+ interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
@@ -299,14 +301,14 @@
#size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
- reg = <3d40 40>;
- interrupts = <2 10 0>;
+ reg = <0x3d40 0x40>;
+ interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200-sram","sram";
- reg = <8000 4000>;
+ reg = <0x8000 0x4000>;
};
};
@@ -316,18 +318,18 @@
#address-cells = <3>;
device_type = "pci";
compatible = "fsl,mpc5200-pci";
- reg = <f0000d00 100>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
- c000 0 0 2 &mpc5200_pic 0 0 3
- c000 0 0 3 &mpc5200_pic 0 0 3
- c000 0 0 4 &mpc5200_pic 0 0 3>;
+ reg = <0xf0000d00 0x100>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
+ 0xc000 0 0 2 &mpc5200_pic 0 0 3
+ 0xc000 0 0 3 &mpc5200_pic 0 0 3
+ 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 a 0>;
+ interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 b0000000 0 01000000>;
+ ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
+ 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+ 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
};
};
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 2e9bc39..7bd5b9c 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -10,11 +10,7 @@
* option) any later version.
*/
-/*
- * WARNING: Do not depend on this tree layout remaining static just yet.
- * The MPC5200 device tree conventions are still in flux
- * Keep an eye on the linuxppc-dev mailing list for more details
- */
+/dts-v1/;
/ {
model = "fsl,lite5200b";
@@ -29,10 +25,10 @@
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
- d-cache-line-size = <20>;
- i-cache-line-size = <20>;
- d-cache-size = <4000>; // L1, 16K
- i-cache-size = <4000>; // L1, 16K
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
@@ -41,21 +37,21 @@
memory {
device_type = "memory";
- reg = <00000000 10000000>; // 256MB
+ reg = <0x00000000 0x10000000>; // 256MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
- ranges = <0 f0000000 0000c000>;
- reg = <f0000000 00000100>;
+ ranges = <0 0xf0000000 0x0000c000>;
+ reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <200 38>;
+ reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
@@ -64,13 +60,13 @@
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <500 80>;
+ reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <0>;
- reg = <600 10>;
+ reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt;
@@ -79,63 +75,63 @@
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <1>;
- reg = <610 10>;
- interrupts = <1 a 0>;
+ reg = <0x610 0x10>;
+ interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <2>;
- reg = <620 10>;
- interrupts = <1 b 0>;
+ reg = <0x620 0x10>;
+ interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <3>;
- reg = <630 10>;
- interrupts = <1 c 0>;
+ reg = <0x630 0x10>;
+ interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <4>;
- reg = <640 10>;
- interrupts = <1 d 0>;
+ reg = <0x640 0x10>;
+ interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <5>;
- reg = <650 10>;
- interrupts = <1 e 0>;
+ reg = <0x650 0x10>;
+ interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <6>;
- reg = <660 10>;
- interrupts = <1 f 0>;
+ reg = <0x660 0x10>;
+ interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <7>;
- reg = <670 10>;
- interrupts = <1 10 0>;
+ reg = <0x670 0x10>;
+ interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
device_type = "rtc";
- reg = <800 100>;
+ reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -143,43 +139,43 @@
can@900 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <0>;
- interrupts = <2 11 0>;
+ interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
- reg = <900 80>;
+ reg = <0x900 0x80>;
};
can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <1>;
- interrupts = <2 12 0>;
+ interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
- reg = <980 80>;
+ reg = <0x980 0x80>;
};
gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <b00 40>;
+ reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <c00 40>;
+ reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <f00 20>;
- interrupts = <2 d 0 2 e 0>;
+ reg = <0xf00 0x20>;
+ interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <1000 ff>;
+ reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -187,17 +183,17 @@
dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <1200 80>;
+ reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 a 0 3 b 0
- 3 c 0 3 d 0 3 e 0 3 f 0>;
+ 3 8 0 3 9 0 3 10 0 3 11 0
+ 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <1f00 100>;
+ reg = <0x1f00 0x100>;
};
serial@2000 { // PSC1
@@ -205,7 +201,7 @@
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>;
- reg = <2000 100>;
+ reg = <0x2000 0x100>;
interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -214,7 +210,7 @@
//ac97@2200 { // PSC2
// compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
// cell-index = <1>;
- // reg = <2200 100>;
+ // reg = <0x2200 0x100>;
// interrupts = <2 2 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -223,7 +219,7 @@
//i2s@2400 { // PSC3
// compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
// cell-index = <2>;
- // reg = <2400 100>;
+ // reg = <0x2400 0x100>;
// interrupts = <2 3 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -233,8 +229,8 @@
// device_type = "serial";
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
// cell-index = <3>;
- // reg = <2600 100>;
- // interrupts = <2 b 0>;
+ // reg = <0x2600 0x100>;
+ // interrupts = <2 11 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -243,8 +239,8 @@
// device_type = "serial";
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
// cell-index = <4>;
- // reg = <2800 100>;
- // interrupts = <2 c 0>;
+ // reg = <0x2800 0x100>;
+ // interrupts = <2 12 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -252,7 +248,7 @@
//spi@2c00 { // PSC6
// compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
// cell-index = <5>;
- // reg = <2c00 100>;
+ // reg = <0x2c00 0x100>;
// interrupts = <2 4 0>;
// interrupt-parent = <&mpc5200_pic>;
//};
@@ -260,7 +256,7 @@
ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <3000 400>;
+ reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -271,11 +267,11 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
- reg = <3000 400>; // fec range, since we need to setup fec interrupts
+ reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
- phy0:ethernet-phy@0 {
+ phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>;
};
@@ -284,7 +280,7 @@
ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <3a00 100>;
+ reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -294,8 +290,8 @@
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
- reg = <3d00 40>;
- interrupts = <2 f 0>;
+ reg = <0x3d00 0x40>;
+ interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
@@ -305,14 +301,14 @@
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
- reg = <3d40 40>;
- interrupts = <2 10 0>;
+ reg = <0x3d40 0x40>;
+ interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
- reg = <8000 4000>;
+ reg = <0x8000 0x4000>;
};
};
@@ -322,23 +318,23 @@
#address-cells = <3>;
device_type = "pci";
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
- reg = <f0000d00 100>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
- c000 0 0 2 &mpc5200_pic 1 1 3
- c000 0 0 3 &mpc5200_pic 1 2 3
- c000 0 0 4 &mpc5200_pic 1 3 3
-
- c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
- c800 0 0 2 &mpc5200_pic 1 2 3
- c800 0 0 3 &mpc5200_pic 1 3 3
- c800 0 0 4 &mpc5200_pic 0 0 3>;
+ reg = <0xf0000d00 0x100>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
+ 0xc000 0 0 2 &mpc5200_pic 1 1 3
+ 0xc000 0 0 3 &mpc5200_pic 1 2 3
+ 0xc000 0 0 4 &mpc5200_pic 1 3 3
+
+ 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
+ 0xc800 0 0 2 &mpc5200_pic 1 2 3
+ 0xc800 0 0 3 &mpc5200_pic 1 3 3
+ 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 a 0>;
+ interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 b0000000 0 01000000>;
+ ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
+ 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
+ 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
};
};
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 2b0dde0..9e3c921 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -10,6 +10,8 @@
* option) any later version.
*/
+/dts-v1/;
+
/ {
model = "promess,motionpro";
compatible = "promess,motionpro";
@@ -23,10 +25,10 @@
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
- d-cache-line-size = <20>;
- i-cache-line-size = <20>;
- d-cache-size = <4000>; // L1, 16K
- i-cache-size = <4000>; // L1, 16K
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
@@ -35,21 +37,21 @@
memory {
device_type = "memory";
- reg = <00000000 04000000>; // 64MB
+ reg = <0x00000000 0x04000000>; // 64MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200b-immr";
- ranges = <0 f0000000 0000c000>;
- reg = <f0000000 00000100>;
+ ranges = <0 0xf0000000 0x0000c000>;
+ reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <200 38>;
+ reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
@@ -57,12 +59,12 @@
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <500 80>;
+ reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <600 10>;
+ reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt;
@@ -70,118 +72,118 @@
timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <610 10>;
- interrupts = <1 a 0>;
+ reg = <0x610 0x10>;
+ interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <620 10>;
- interrupts = <1 b 0>;
+ reg = <0x620 0x10>;
+ interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <630 10>;
- interrupts = <1 c 0>;
+ reg = <0x630 0x10>;
+ interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <640 10>;
- interrupts = <1 d 0>;
+ reg = <0x640 0x10>;
+ interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <650 10>;
- interrupts = <1 e 0>;
+ reg = <0x650 0x10>;
+ interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
motionpro-led@660 { // Motion-PRO status LED
compatible = "promess,motionpro-led";
label = "motionpro-statusled";
- reg = <660 10>;
- interrupts = <1 f 0>;
+ reg = <0x660 0x10>;
+ interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
- blink-delay = <64>; // 100 msec
+ blink-delay = <100>; // 100 msec
};
motionpro-led@670 { // Motion-PRO ready LED
compatible = "promess,motionpro-led";
label = "motionpro-readyled";
- reg = <670 10>;
- interrupts = <1 10 0>;
+ reg = <0x670 0x10>;
+ interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
- reg = <800 100>;
+ reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
- mscan@980 {
+ can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 12 0>;
+ interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
- reg = <980 80>;
+ reg = <0x980 0x80>;
};
gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <b00 40>;
+ reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <c00 40>;
+ reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <f00 20>;
- interrupts = <2 d 0 2 e 0>;
+ reg = <0xf00 0x20>;
+ interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <1000 ff>;
+ reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <1200 80>;
+ reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 a 0 3 b 0
- 3 c 0 3 d 0 3 e 0 3 f 0>;
+ 3 8 0 3 9 0 3 10 0 3 11 0
+ 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <1f00 100>;
+ reg = <0x1f00 0x100>;
};
serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
- reg = <2000 100>;
+ reg = <0x2000 0x100>;
interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -190,7 +192,7 @@
spi@2200 { // PSC2
compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
cell-index = <1>;
- reg = <2200 100>;
+ reg = <0x2200 0x100>;
interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -200,15 +202,15 @@
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <4>; // Logical port assignment
- reg = <2800 100>;
- interrupts = <2 c 0>;
+ reg = <0x2800 0x100>;
+ interrupts = <2 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <3000 400>;
+ reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -219,7 +221,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <3000 400>; // fec range, since we need to setup fec interrupts
+ reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
@@ -231,7 +233,7 @@
ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <3a00 100>;
+ reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -240,21 +242,21 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <3d40 40>;
- interrupts = <2 10 0>;
+ reg = <0x3d40 0x40>;
+ interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
rtc@68 {
device_type = "rtc";
compatible = "dallas,ds1339";
- reg = <68>;
+ reg = <0x68>;
};
};
sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
- reg = <8000 4000>;
+ reg = <0x8000 0x4000>;
};
};
@@ -262,15 +264,15 @@
compatible = "fsl,lpb";
#address-cells = <2>;
#size-cells = <1>;
- ranges = <0 0 ff000000 01000000
- 1 0 50000000 00010000
- 2 0 50010000 00010000
- 3 0 50020000 00010000>;
+ ranges = <0 0 0xff000000 0x01000000
+ 1 0 0x50000000 0x00010000
+ 2 0 0x50010000 0x00010000
+ 3 0 0x50020000 0x00010000>;
// 8-bit DualPort SRAM on LocalPlus Bus CS1
kollmorgen@1,0 {
compatible = "promess,motionpro-kollmorgen";
- reg = <1 0 10000>;
+ reg = <1 0 0x10000>;
interrupts = <1 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -278,13 +280,13 @@
// 8-bit board CPLD on LocalPlus Bus CS2
cpld@2,0 {
compatible = "promess,motionpro-cpld";
- reg = <2 0 10000>;
+ reg = <2 0 0x10000>;
};
// 8-bit custom Anybus Module on LocalPlus Bus CS3
anybus@3,0 {
compatible = "promess,motionpro-anybus";
- reg = <3 0 10000>;
+ reg = <3 0 0x10000>;
};
pro_module_general@3,0 {
compatible = "promess,pro_module_general";
@@ -292,13 +294,13 @@
};
pro_module_dio@3,800 {
compatible = "promess,pro_module_dio";
- reg = <3 800 2>;
+ reg = <3 0x800 2>;
};
// 16-bit flash device at LocalPlus Bus CS0
flash@0,0 {
compatible = "cfi-flash";
- reg = <0 0 01000000>;
+ reg = <0 0 0x01000000>;
bank-width = <2>;
device-width = <2>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index 65bcea6..773a68e 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -10,6 +10,8 @@
* option) any later version.
*/
+/dts-v1/;
+
/ {
model = "tqc,tqm5200";
compatible = "tqc,tqm5200";
@@ -23,10 +25,10 @@
PowerPC,5200@0 {
device_type = "cpu";
reg = <0>;
- d-cache-line-size = <20>;
- i-cache-line-size = <20>;
- d-cache-size = <4000>; // L1, 16K
- i-cache-size = <4000>; // L1, 16K
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
@@ -35,21 +37,21 @@
memory {
device_type = "memory";
- reg = <00000000 04000000>; // 64MB
+ reg = <0x00000000 0x04000000>; // 64MB
};
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc5200-immr";
- ranges = <0 f0000000 0000c000>;
- reg = <f0000000 00000100>;
+ ranges = <0 0xf0000000 0x0000c000>;
+ reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
compatible = "fsl,mpc5200-cdm";
- reg = <200 38>;
+ reg = <0x200 0x38>;
};
mpc5200_pic: interrupt-controller@500 {
@@ -57,12 +59,12 @@
interrupt-controller;
#interrupt-cells = <3>;
compatible = "fsl,mpc5200-pic";
- reg = <500 80>;
+ reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt";
- reg = <600 10>;
+ reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt;
@@ -70,38 +72,38 @@
gpio@b00 {
compatible = "fsl,mpc5200-gpio";
- reg = <b00 40>;
+ reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
compatible = "fsl,mpc5200-ohci","ohci-be";
- reg = <1000 ff>;
+ reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
dma-controller@1200 {
compatible = "fsl,mpc5200-bestcomm";
- reg = <1200 80>;
+ reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 a 0 3 b 0
- 3 c 0 3 d 0 3 e 0 3 f 0>;
+ 3 8 0 3 9 0 3 10 0 3 11 0
+ 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
compatible = "fsl,mpc5200-xlb";
- reg = <1f00 100>;
+ reg = <0x1f00 0x100>;
};
serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
- reg = <2000 100>;
+ reg = <0x2000 0x100>;
interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -110,7 +112,7 @@
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart";
port-number = <1>; // Logical port assignment
- reg = <2200 100>;
+ reg = <0x2200 0x100>;
interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -119,7 +121,7 @@
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart";
port-number = <2>; // Logical port assignment
- reg = <2400 100>;
+ reg = <0x2400 0x100>;
interrupts = <2 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -127,7 +129,7 @@
ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200-fec";
- reg = <3000 400>;
+ reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -137,8 +139,8 @@
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <3000 400>; // fec range, since we need to setup fec interrupts
+ compatible = "fsl,mpc5200-mdio";
+ reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
@@ -150,7 +152,7 @@
ata@3a00 {
compatible = "fsl,mpc5200-ata";
- reg = <3a00 100>;
+ reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
@@ -159,21 +161,21 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c";
- reg = <3d40 40>;
- interrupts = <2 10 0>;
+ reg = <0x3d40 0x40>;
+ interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
rtc@68 {
device_type = "rtc";
compatible = "dallas,ds1307";
- reg = <68>;
+ reg = <0x68>;
};
};
sram@8000 {
compatible = "fsl,mpc5200-sram";
- reg = <8000 4000>;
+ reg = <0x8000 0x4000>;
};
};
@@ -182,11 +184,11 @@
compatible = "fsl,lpb";
#address-cells = <2>;
#size-cells = <1>;
- ranges = <0 0 fc000000 02000000>;
+ ranges = <0 0 0xfc000000 0x02000000>;
flash@0,0 {
compatible = "cfi-flash";
- reg = <0 0 02000000>;
+ reg = <0 0 0x02000000>;
bank-width = <4>;
device-width = <2>;
#size-cells = <1>;
@@ -200,18 +202,18 @@
#address-cells = <3>;
device_type = "pci";
compatible = "fsl,mpc5200-pci";
- reg = <f0000d00 100>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
- c000 0 0 2 &mpc5200_pic 0 0 3
- c000 0 0 3 &mpc5200_pic 0 0 3
- c000 0 0 4 &mpc5200_pic 0 0 3>;
+ reg = <0xf0000d00 0x100>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
+ 0xc000 0 0 2 &mpc5200_pic 0 0 3
+ 0xc000 0 0 3 &mpc5200_pic 0 0 3
+ 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 a 0>;
+ interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 10000000
- 02000000 0 90000000 90000000 0 10000000
- 01000000 0 00000000 a0000000 0 01000000>;
+ ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
+ 0x02000000 0 0x90000000 0x90000000 0 0x10000000
+ 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
};
};
^ permalink raw reply related
* [RFC/POWERPC] mpc5200: remove "mpc5200b-*" from compatible lists in dts files
From: Grant Likely @ 2008-04-18 16:13 UTC (permalink / raw)
To: linuxppc-dev, m8
From: Grant Likely <grant.likely@secretlab.ca>
The mpc5200b is a bug fix of the mpc5200 with a few incompatible changes.
By rights, the current dts trees are the most "correct", but in practical
purposes there is no value in the 5200b devices having 2 compatible
entries for each internal peripheral node. Freescale has done a good job
of documenting exactly where the incompatibilities lie, so it restrict
the extra compatible properties to devices with *documented* changes.
Removing the extra 'b' fields makes the device trees smaller
---
arch/powerpc/boot/dts/cm5200.dts | 48 +++++++++++++------------
arch/powerpc/boot/dts/lite5200b.dts | 66 ++++++++++++++++++-----------------
arch/powerpc/boot/dts/motionpro.dts | 50 +++++++++++++--------------
arch/powerpc/kernel/prom_init.c | 2 +
drivers/net/fec_mpc52xx_phy.c | 2 +
5 files changed, 84 insertions(+), 84 deletions(-)
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 2f74cc4..5f929c3 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -43,14 +43,14 @@
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
+ compatible = "fsl,mpc5200-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+ compatible = "fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
@@ -58,12 +58,12 @@
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+ compatible = "fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -71,91 +71,91 @@
};
timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@660 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x660 0x10>;
interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@670 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x670 0x10>;
interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
+ compatible = "fsl,mpc5200-rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+ compatible = "fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
+ compatible = "fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
+ compatible = "fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
+ compatible = "fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
+ compatible = "fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
@@ -165,13 +165,13 @@
};
xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+ compatible = "fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
serial@2000 { // PSC1
device_type = "serial";
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
@@ -198,7 +198,7 @@
serial@2c00 { // PSC6
device_type = "serial";
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ compatible = "fsl,mpc5200-psc-uart";
port-number = <5>; // Logical port assignment
reg = <0x2c00 0x100>;
interrupts = <2 4 0>;
@@ -207,7 +207,7 @@
ethernet@3000 {
device_type = "network";
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+ compatible = "fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
@@ -218,7 +218,7 @@
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+ compatible = "fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
@@ -232,7 +232,7 @@
i2c@3d40 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+ compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -240,7 +240,7 @@
};
sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+ compatible = "fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 7bd5b9c..0f3e68d 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -43,14 +43,14 @@
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
+ compatible = "fsl,mpc5200-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+ compatible = "fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
@@ -59,12 +59,12 @@
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+ compatible = "fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <0>;
reg = <0x600 0x10>;
interrupts = <1 9 0>;
@@ -73,7 +73,7 @@
};
timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <1>;
reg = <0x610 0x10>;
interrupts = <1 10 0>;
@@ -81,7 +81,7 @@
};
timer@620 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <2>;
reg = <0x620 0x10>;
interrupts = <1 11 0>;
@@ -89,7 +89,7 @@
};
timer@630 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <3>;
reg = <0x630 0x10>;
interrupts = <1 12 0>;
@@ -97,7 +97,7 @@
};
timer@640 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <4>;
reg = <0x640 0x10>;
interrupts = <1 13 0>;
@@ -105,7 +105,7 @@
};
timer@650 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <5>;
reg = <0x650 0x10>;
interrupts = <1 14 0>;
@@ -113,7 +113,7 @@
};
timer@660 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <6>;
reg = <0x660 0x10>;
interrupts = <1 15 0>;
@@ -121,7 +121,7 @@
};
timer@670 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <7>;
reg = <0x670 0x10>;
interrupts = <1 16 0>;
@@ -129,7 +129,7 @@
};
rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
+ compatible = "fsl,mpc5200-rtc";
device_type = "rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
@@ -137,7 +137,7 @@
};
can@900 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
+ compatible = "fsl,mpc5200-mscan";
cell-index = <0>;
interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -145,7 +145,7 @@
};
can@980 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
+ compatible = "fsl,mpc5200-mscan";
cell-index = <1>;
interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -153,28 +153,28 @@
};
gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+ compatible = "fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
+ compatible = "fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
+ compatible = "fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
+ compatible = "fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -182,7 +182,7 @@
dma-controller@1200 {
device_type = "dma-controller";
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
+ compatible = "fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
@@ -192,13 +192,13 @@
};
xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+ compatible = "fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
serial@2000 { // PSC1
device_type = "serial";
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>;
reg = <0x2000 0x100>;
@@ -208,7 +208,7 @@
// PSC2 in ac97 mode example
//ac97@2200 { // PSC2
- // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
+ // compatible = "fsl,mpc5200b-psc-ac97";
// cell-index = <1>;
// reg = <0x2200 0x100>;
// interrupts = <2 2 0>;
@@ -217,7 +217,7 @@
// PSC3 in CODEC mode example
//i2s@2400 { // PSC3
- // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
+ // compatible = "fsl,mpc5200-psc-i2s";
// cell-index = <2>;
// reg = <0x2400 0x100>;
// interrupts = <2 3 0>;
@@ -227,7 +227,7 @@
// PSC4 in uart mode example
//serial@2600 { // PSC4
// device_type = "serial";
- // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ // compatible = "fsl,mpc5200-psc-uart";
// cell-index = <3>;
// reg = <0x2600 0x100>;
// interrupts = <2 11 0>;
@@ -237,7 +237,7 @@
// PSC5 in uart mode example
//serial@2800 { // PSC5
// device_type = "serial";
- // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ // compatible = "fsl,mpc5200-psc-uart";
// cell-index = <4>;
// reg = <0x2800 0x100>;
// interrupts = <2 12 0>;
@@ -246,7 +246,7 @@
// PSC6 in spi mode example
//spi@2c00 { // PSC6
- // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
+ // compatible = "fsl,mpc5200-psc-spi";
// cell-index = <5>;
// reg = <0x2c00 0x100>;
// interrupts = <2 4 0>;
@@ -255,7 +255,7 @@
ethernet@3000 {
device_type = "network";
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+ compatible = "fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
@@ -266,7 +266,7 @@
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
+ compatible = "fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
@@ -279,7 +279,7 @@
ata@3a00 {
device_type = "ata";
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+ compatible = "fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -288,7 +288,7 @@
i2c@3d00 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+ compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
@@ -299,7 +299,7 @@
i2c@3d40 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+ compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
@@ -307,7 +307,7 @@
fsl5200-clocking;
};
sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
+ compatible = "fsl,mpc5200-sram","sram";
reg = <0x8000 0x4000>;
};
};
@@ -317,7 +317,7 @@
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
- compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
+ compatible = "fsl,mpc5200-pci";
reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 9e3c921..9422d59 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -43,14 +43,14 @@
soc5200@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
+ compatible = "fsl,mpc5200-immr";
ranges = <0 0xf0000000 0x0000c000>;
reg = <0xf0000000 0x00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+ compatible = "fsl,mpc5200-cdm";
reg = <0x200 0x38>;
};
@@ -58,12 +58,12 @@
// 5200 interrupts are encoded into two levels;
interrupt-controller;
#interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+ compatible = "fsl,mpc5200-pic";
reg = <0x500 0x80>;
};
timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x600 0x10>;
interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -71,35 +71,35 @@
};
timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x610 0x10>;
interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@620 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x620 0x10>;
interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@630 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x630 0x10>;
interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@640 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x640 0x10>;
interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
};
timer@650 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ compatible = "fsl,mpc5200-gpt";
reg = <0x650 0x10>;
interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -123,49 +123,49 @@
};
rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
+ compatible = "fsl,mpc5200-rtc";
reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
can@980 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
+ compatible = "fsl,mpc5200-mscan";
interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>;
};
gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+ compatible = "fsl,mpc5200-gpio";
reg = <0xb00 0x40>;
interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
};
gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
+ compatible = "fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
+ compatible = "fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
+ compatible = "fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>;
interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
};
dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
+ compatible = "fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0
@@ -175,13 +175,13 @@
};
xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+ compatible = "fsl,mpc5200-xlb";
reg = <0x1f00 0x100>;
};
serial@2000 { // PSC1
device_type = "serial";
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>;
interrupts = <2 1 0>;
@@ -190,7 +190,7 @@
// PSC2 in spi master mode
spi@2200 { // PSC2
- compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
+ compatible = "fsl,mpc5200-psc-spi";
cell-index = <1>;
reg = <0x2200 0x100>;
interrupts = <2 2 0>;
@@ -200,7 +200,7 @@
// PSC5 in uart mode
serial@2800 { // PSC5
device_type = "serial";
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ compatible = "fsl,mpc5200-psc-uart";
port-number = <4>; // Logical port assignment
reg = <0x2800 0x100>;
interrupts = <2 12 0>;
@@ -209,7 +209,7 @@
ethernet@3000 {
device_type = "network";
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+ compatible = "fsl,mpc5200-fec";
reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>;
@@ -220,7 +220,7 @@
mdio@3000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+ compatible = "fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
@@ -232,7 +232,7 @@
};
ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+ compatible = "fsl,mpc5200-ata";
reg = <0x3a00 0x100>;
interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -241,7 +241,7 @@
i2c@3d40 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+ compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
@@ -255,7 +255,7 @@
};
sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+ compatible = "fsl,mpc5200-sram";
reg = <0x8000 0x4000>;
};
};
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 6d6df1e..af837b2 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2179,7 +2179,7 @@ static void __init fixup_device_tree_efika_add_phy(void)
" 1 encode-int s\" #address-cells\" property"
" 0 encode-int s\" #size-cells\" property"
" s\" mdio\" device-name"
- " s\" fsl,mpc5200b-mdio\" encode-string"
+ " s\" fsl,mpc5200-mdio\" encode-string"
" s\" compatible\" property"
" 0xf0003000 0x400 reg"
" 0x2 encode-int"
diff --git a/drivers/net/fec_mpc52xx_phy.c b/drivers/net/fec_mpc52xx_phy.c
index 1d0cd1d..cdca6fe 100644
--- a/drivers/net/fec_mpc52xx_phy.c
+++ b/drivers/net/fec_mpc52xx_phy.c
@@ -185,7 +185,7 @@ static struct of_device_id mpc52xx_fec_mdio_match[] = {
};
struct of_platform_driver mpc52xx_fec_mdio_driver = {
- .name = "mpc5200b-fec-phy",
+ .name = "mpc5200-fec-phy",
.probe = mpc52xx_fec_mdio_probe,
.remove = mpc52xx_fec_mdio_remove,
.match_table = mpc52xx_fec_mdio_match,
^ permalink raw reply related
* Re: [PATCH v2.6.26] powerpc: Add 8568 PHY workaround to board code
From: Kumar Gala @ 2008-04-18 22:37 UTC (permalink / raw)
To: Andy Fleming; +Cc: linuxppc-dev, jgarzik
In-Reply-To: <1208558149-6029-1-git-send-email-afleming@freescale.com>
On Apr 18, 2008, at 5:35 PM, Andy Fleming wrote:
> The 8568 MDS needs some configuration changes to the PHY in order to
> work
> properly. These are done in the firmware, normally, but Linux
> shouldn't
> need to rely on the firmware running such things (someone could
> disable
> the PHY support in the firmware to save space, for instance).
>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
>
> Jeff, copying you so you can see what code uses the board fixup
> patch. Also,
> Kumar, note that this patch is utterly useless without the patch
> sent to netdev:
> Add support for board-level PHY fixups.
ok, I'll queue it up for a post initial pull of netdev, etc.
I'm assuming the board-level PHY fixup support has been ack'd by Jeff
and will go into 2.6.26.
- k
^ permalink raw reply
* [PATCH v2.6.26] gianfar: Add support for multiple gfar mdio interfaces
From: Andy Fleming @ 2008-04-18 22:37 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
The old code assumed there was only one, but the 8572 actually has 3.
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/sysdev/fsl_soc.c | 86 ++++++++++++++++++----------------------
1 files changed, 39 insertions(+), 47 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 3581416..4ed94ee 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -180,66 +180,58 @@ static int __init of_add_fixed_phys(void)
arch_initcall(of_add_fixed_phys);
#endif /* CONFIG_FIXED_PHY */
-static int __init gfar_mdio_of_init(void)
+static int gfar_mdio_of_init_one(struct device_node *np)
{
- struct device_node *np = NULL;
+ int k;
+ struct device_node *child = NULL;
+ struct gianfar_mdio_data mdio_data;
struct platform_device *mdio_dev;
struct resource res;
int ret;
- np = of_find_compatible_node(np, NULL, "fsl,gianfar-mdio");
+ memset(&res, 0, sizeof(res));
+ memset(&mdio_data, 0, sizeof(mdio_data));
- /* try the deprecated version */
- if (!np)
- np = of_find_compatible_node(np, "mdio", "gianfar");
-
- if (np) {
- int k;
- struct device_node *child = NULL;
- struct gianfar_mdio_data mdio_data;
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret)
+ return ret;
- memset(&res, 0, sizeof(res));
- memset(&mdio_data, 0, sizeof(mdio_data));
+ mdio_dev = platform_device_register_simple("fsl-gianfar_mdio",
+ res.start&0xfffff, &res, 1);
+ if (IS_ERR(mdio_dev))
+ return PTR_ERR(mdio_dev);
- ret = of_address_to_resource(np, 0, &res);
- if (ret)
- goto err;
+ for (k = 0; k < 32; k++)
+ mdio_data.irq[k] = PHY_POLL;
- mdio_dev =
- platform_device_register_simple("fsl-gianfar_mdio",
- res.start, &res, 1);
- if (IS_ERR(mdio_dev)) {
- ret = PTR_ERR(mdio_dev);
- goto err;
+ while ((child = of_get_next_child(np, child)) != NULL) {
+ int irq = irq_of_parse_and_map(child, 0);
+ if (irq != NO_IRQ) {
+ const u32 *id = of_get_property(child, "reg", NULL);
+ mdio_data.irq[*id] = irq;
}
+ }
- for (k = 0; k < 32; k++)
- mdio_data.irq[k] = PHY_POLL;
+ ret = platform_device_add_data(mdio_dev, &mdio_data,
+ sizeof(struct gianfar_mdio_data));
+ if (ret)
+ platform_device_unregister(mdio_dev);
- while ((child = of_get_next_child(np, child)) != NULL) {
- int irq = irq_of_parse_and_map(child, 0);
- if (irq != NO_IRQ) {
- const u32 *id = of_get_property(child,
- "reg", NULL);
- mdio_data.irq[*id] = irq;
- }
- }
+ return ret;
+}
- ret =
- platform_device_add_data(mdio_dev, &mdio_data,
- sizeof(struct gianfar_mdio_data));
- if (ret)
- goto unreg;
- }
+static int __init gfar_mdio_of_init(void)
+{
+ struct device_node *np = NULL;
- of_node_put(np);
- return 0;
+ for_each_compatible_node(np, NULL, "fsl,gianfar-mdio")
+ gfar_mdio_of_init_one(np);
-unreg:
- platform_device_unregister(mdio_dev);
-err:
- of_node_put(np);
- return ret;
+ /* try the deprecated version */
+ for_each_compatible_node(np, "mdio", "gianfar");
+ gfar_mdio_of_init_one(np);
+
+ return 0;
}
arch_initcall(gfar_mdio_of_init);
--
1.5.4.GIT
^ permalink raw reply related
* [PATCH v2.6.26] powerpc: Add 8568 PHY workaround to board code
From: Andy Fleming @ 2008-04-18 22:35 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev, jgarzik
The 8568 MDS needs some configuration changes to the PHY in order to work
properly. These are done in the firmware, normally, but Linux shouldn't
need to rely on the firmware running such things (someone could disable
the PHY support in the firmware to save space, for instance).
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
Jeff, copying you so you can see what code uses the board fixup patch. Also,
Kumar, note that this patch is utterly useless without the patch sent to netdev:
Add support for board-level PHY fixups.
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 114 +++++++++++++++++++++++++++++
1 files changed, 114 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 25f8bc7..b1bf06d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -32,6 +32,7 @@
#include <linux/fsl_devices.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
+#include <linux/phy.h>
#include <asm/system.h>
#include <asm/atomic.h>
@@ -56,6 +57,95 @@
#define DBG(fmt...)
#endif
+#define MV88E1111_SCR 0x10
+#define MV88E1111_SCR_125CLK 0x0010
+static int mpc8568_fixup_125_clock(struct phy_device *phydev)
+{
+ int scr;
+ int err;
+
+ /* Workaround for the 125 CLK Toggle */
+ scr = phy_read(phydev, MV88E1111_SCR);
+
+ if (scr < 0)
+ return scr;
+
+ err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
+
+ if (err)
+ return err;
+
+ err = phy_write(phydev, MII_BMCR, BMCR_RESET);
+
+ if (err)
+ return err;
+
+ scr = phy_read(phydev, MV88E1111_SCR);
+
+ if (scr < 0)
+ return err;
+
+ err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
+
+ return err;
+}
+
+static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
+{
+ int temp;
+ int err;
+
+ /* Errata */
+ err = phy_write(phydev,29, 0x0006);
+
+ if (err)
+ return err;
+
+ temp = phy_read(phydev, 30);
+
+ if (temp < 0)
+ return temp;
+
+ temp = (temp & (~0x8000)) | 0x4000;
+ err = phy_write(phydev,30, temp);
+
+ if (err)
+ return err;
+
+ err = phy_write(phydev,29, 0x000a);
+
+ if (err)
+ return err;
+
+ temp = phy_read(phydev, 30);
+
+ if (temp < 0)
+ return temp;
+
+ temp = phy_read(phydev, 30);
+
+ if (temp < 0)
+ return temp;
+
+ temp &= ~0x0020;
+
+ err = phy_write(phydev,30,temp);
+
+ if (err)
+ return err;
+
+ /* Disable automatic MDI/MDIX selection */
+ temp = phy_read(phydev, 16);
+
+ if (temp < 0)
+ return temp;
+
+ temp &= ~0x0060;
+ err = phy_write(phydev,16,temp);
+
+ return err;
+}
+
/* ************************************************************************
*
* Setup the architecture
@@ -138,6 +228,30 @@ static void __init mpc85xx_mds_setup_arch(void)
#endif /* CONFIG_QUICC_ENGINE */
}
+
+static int __init board_fixups(void)
+{
+ char phy_id[BUS_ID_SIZE];
+ struct device_node *mdio;
+ struct resource res;
+
+ /* Register a workaround to fixup the clock source */
+ mdio = of_find_node_by_name(NULL, "mdio");
+
+ of_address_to_resource(mdio, 0, &res);
+ snprintf(phy_id, BUS_ID_SIZE, "%x:%02x", res.start, 1);
+
+ phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
+ phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
+
+ /* Register a workaround for errata */
+ snprintf(phy_id, BUS_ID_SIZE, "%x:%02x", res.start, 7);
+ phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
+
+ return 0;
+}
+arch_initcall(board_fixups);
+
static struct of_device_id mpc85xx_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
--
1.5.4.GIT
^ permalink raw reply related
* [PATCH 1/2] [v3][POWERPC] refactor dcr code
From: Stephen Neuendorffer @ 2008-04-18 21:55 UTC (permalink / raw)
To: benh, linuxppc-dev
In-Reply-To: <1206914576.10388.132.camel@pasglop>
Previously, dcr support was configured at compile time to either using
MMIO or native dcr instructions. Although this works for most
platforms, it fails on FPGA platforms:
1) Systems may include more than one dcr bus.
2) Systems may be native dcr capable and still use memory mapped dcr interface.
This patch provides runtime support based on the device trees for the
case where CONFIG_PPC_DCR_MMIO and CONFIG_PPC_DCR_NATIVE are both
selected. Previously, this was a poorly defined configuration, which
happened to provide NATIVE support. The runtime selection is made
based on the dcr controller having a 'dcr-access-method' attribute
in the device tree. If only one of the above options is selected,
then the code uses #defines to select only the used code in order to
avoid introducing overhead in existing usage.
Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
---
arch/powerpc/sysdev/dcr.c | 91 ++++++++++++++++++++++++++++++++-----
include/asm-powerpc/dcr-generic.h | 49 ++++++++++++++++++++
include/asm-powerpc/dcr-mmio.h | 20 +++++---
include/asm-powerpc/dcr-native.h | 16 ++++---
include/asm-powerpc/dcr.h | 36 ++++++++++++++-
5 files changed, 186 insertions(+), 26 deletions(-)
create mode 100644 include/asm-powerpc/dcr-generic.h
diff --git a/arch/powerpc/sysdev/dcr.c b/arch/powerpc/sysdev/dcr.c
index 437e48d..d3de0ff 100644
--- a/arch/powerpc/sysdev/dcr.c
+++ b/arch/powerpc/sysdev/dcr.c
@@ -23,6 +23,68 @@
#include <asm/prom.h>
#include <asm/dcr.h>
+#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
+
+bool dcr_map_ok_generic(dcr_host_t host)
+{
+ if (host.type == INVALID)
+ return 0;
+ else if (host.type == NATIVE)
+ return dcr_map_ok_native(host.host.native);
+ else
+ return dcr_map_ok_mmio(host.host.mmio);
+}
+EXPORT_SYMBOL_GPL(dcr_map_ok_generic);
+
+dcr_host_t dcr_map_generic(struct device_node *dev,
+ unsigned int dcr_n,
+ unsigned int dcr_c)
+{
+ dcr_host_t host;
+ const char *prop = of_get_property(dev, "dcr-access-method", NULL);
+
+ if (!strcmp(prop, "native")) {
+ host.type = NATIVE;
+ host.host.native = dcr_map_native(dev, dcr_n, dcr_c);
+ } else if (!strcmp(prop, "mmio")) {
+ host.type = MMIO;
+ host.host.mmio = dcr_map_mmio(dev, dcr_n, dcr_c);
+ } else
+ host.type = INVALID;
+
+ return host;
+}
+EXPORT_SYMBOL_GPL(dcr_map_generic);
+
+void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c)
+{
+ if (host.type == NATIVE)
+ dcr_unmap_native(host.host.native, dcr_c);
+ else
+ dcr_unmap_mmio(host.host.mmio, dcr_c);
+}
+EXPORT_SYMBOL_GPL(dcr_unmap_generic);
+
+u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n)
+{
+ if (host.type == NATIVE)
+ return dcr_read_native(host.host.native, dcr_n);
+ else
+ return dcr_read_mmio(host.host.mmio, dcr_n);
+}
+EXPORT_SYMBOL_GPL(dcr_read_generic);
+
+void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value)
+{
+ if (host.type == NATIVE)
+ dcr_write_native(host.host.native, dcr_n, value);
+ else
+ dcr_write_mmio(host.host.mmio, dcr_n, value);
+}
+EXPORT_SYMBOL_GPL(dcr_write_generic);
+
+#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
+
unsigned int dcr_resource_start(struct device_node *np, unsigned int index)
{
unsigned int ds;
@@ -47,7 +109,7 @@ unsigned int dcr_resource_len(struct device_node *np, unsigned int index)
}
EXPORT_SYMBOL_GPL(dcr_resource_len);
-#ifndef CONFIG_PPC_DCR_NATIVE
+#ifdef CONFIG_PPC_DCR_MMIO
static struct device_node * find_dcr_parent(struct device_node * node)
{
@@ -101,18 +163,19 @@ u64 of_translate_dcr_address(struct device_node *dev,
return ret;
}
-dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
- unsigned int dcr_c)
+dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
+ unsigned int dcr_n,
+ unsigned int dcr_c)
{
- dcr_host_t ret = { .token = NULL, .stride = 0, .base = dcr_n };
+ dcr_host_mmio_t ret = { .token = NULL, .stride = 0, .base = dcr_n };
u64 addr;
pr_debug("dcr_map(%s, 0x%x, 0x%x)\n",
dev->full_name, dcr_n, dcr_c);
addr = of_translate_dcr_address(dev, dcr_n, &ret.stride);
- pr_debug("translates to addr: 0x%lx, stride: 0x%x\n",
- addr, ret.stride);
+ pr_debug("translates to addr: 0x%llx, stride: 0x%x\n",
+ (unsigned long long) addr, ret.stride);
if (addr == OF_BAD_ADDR)
return ret;
pr_debug("mapping 0x%x bytes\n", dcr_c * ret.stride);
@@ -124,11 +187,11 @@ dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
ret.token -= dcr_n * ret.stride;
return ret;
}
-EXPORT_SYMBOL_GPL(dcr_map);
+EXPORT_SYMBOL_GPL(dcr_map_mmio);
-void dcr_unmap(dcr_host_t host, unsigned int dcr_c)
+void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c)
{
- dcr_host_t h = host;
+ dcr_host_mmio_t h = host;
if (h.token == NULL)
return;
@@ -136,7 +199,11 @@ void dcr_unmap(dcr_host_t host, unsigned int dcr_c)
iounmap(h.token);
h.token = NULL;
}
-EXPORT_SYMBOL_GPL(dcr_unmap);
-#else /* defined(CONFIG_PPC_DCR_NATIVE) */
+EXPORT_SYMBOL_GPL(dcr_unmap_mmio);
+
+#endif /* defined(CONFIG_PPC_DCR_MMIO) */
+
+#ifdef CONFIG_PPC_DCR_NATIVE
DEFINE_SPINLOCK(dcr_ind_lock);
-#endif /* !defined(CONFIG_PPC_DCR_NATIVE) */
+#endif /* defined(CONFIG_PPC_DCR_NATIVE) */
+
diff --git a/include/asm-powerpc/dcr-generic.h b/include/asm-powerpc/dcr-generic.h
new file mode 100644
index 0000000..0ee74fb
--- /dev/null
+++ b/include/asm-powerpc/dcr-generic.h
@@ -0,0 +1,49 @@
+/*
+ * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
+ * <benh@kernel.crashing.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ * the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_POWERPC_DCR_GENERIC_H
+#define _ASM_POWERPC_DCR_GENERIC_H
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+enum host_type_t {MMIO, NATIVE, INVALID};
+
+typedef struct {
+ enum host_type_t type;
+ union {
+ dcr_host_mmio_t mmio;
+ dcr_host_native_t native;
+ } host;
+} dcr_host_t;
+
+extern bool dcr_map_ok_generic(dcr_host_t host);
+
+extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned int dcr_n,
+ unsigned int dcr_c);
+extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
+
+extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
+
+extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* _ASM_POWERPC_DCR_GENERIC_H */
+
+
diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h
index 08532ff..acd491d 100644
--- a/include/asm-powerpc/dcr-mmio.h
+++ b/include/asm-powerpc/dcr-mmio.h
@@ -27,20 +27,26 @@ typedef struct {
void __iomem *token;
unsigned int stride;
unsigned int base;
-} dcr_host_t;
+} dcr_host_mmio_t;
-#define DCR_MAP_OK(host) ((host).token != NULL)
+static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
+{
+ return host.token != NULL;
+}
-extern dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
- unsigned int dcr_c);
-extern void dcr_unmap(dcr_host_t host, unsigned int dcr_c);
+extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
+ unsigned int dcr_n,
+ unsigned int dcr_c);
+extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c);
-static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n)
+static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int dcr_n)
{
return in_be32(host.token + ((host.base + dcr_n) * host.stride));
}
-static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value)
+static inline void dcr_write_mmio(dcr_host_mmio_t host,
+ unsigned int dcr_n,
+ u32 value)
{
out_be32(host.token + ((host.base + dcr_n) * host.stride), value);
}
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h
index f8398ce..72d2b72 100644
--- a/include/asm-powerpc/dcr-native.h
+++ b/include/asm-powerpc/dcr-native.h
@@ -26,14 +26,18 @@
typedef struct {
unsigned int base;
-} dcr_host_t;
+} dcr_host_native_t;
-#define DCR_MAP_OK(host) (1)
+static inline bool dcr_map_ok_native(dcr_host_native_t host)
+{
+ return 1;
+}
-#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) })
-#define dcr_unmap(host, dcr_c) do {} while (0)
-#define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base)
-#define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
+#define dcr_map_native(dev, dcr_n, dcr_c) \
+ ((dcr_host_native_t){ .base = (dcr_n) })
+#define dcr_unmap_native(host, dcr_c) do {} while (0)
+#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
+#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
/* Device Control Registers */
void __mtdcr(int reg, unsigned int val);
diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
index 9338d50..6b86322 100644
--- a/include/asm-powerpc/dcr.h
+++ b/include/asm-powerpc/dcr.h
@@ -20,14 +20,47 @@
#ifndef _ASM_POWERPC_DCR_H
#define _ASM_POWERPC_DCR_H
#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
#ifdef CONFIG_PPC_DCR
#ifdef CONFIG_PPC_DCR_NATIVE
#include <asm/dcr-native.h>
-#else
+#endif
+
+#ifdef CONFIG_PPC_DCR_MMIO
#include <asm/dcr-mmio.h>
#endif
+#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
+
+#include <asm/dcr-generic.h>
+
+#define DCR_MAP_OK(host) dcr_map_ok_generic(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value)
+
+#else
+
+#ifdef CONFIG_PPC_DCR_NATIVE
+typedef dcr_host_native_t dcr_host_t;
+#define DCR_MAP_OK(host) dcr_map_ok_native(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value)
+#else
+typedef dcr_host_mmio_t dcr_host_t;
+#define DCR_MAP_OK(host) dcr_map_ok_mmio(host)
+#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
+#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
+#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
+#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value)
+#endif
+
+#endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
+
/*
* On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
* base from the device-tree
@@ -41,5 +74,6 @@ extern unsigned int dcr_resource_len(struct device_node *np,
#endif /* CONFIG_PPC_MERGE */
#endif /* CONFIG_PPC_DCR */
+#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_DCR_H */
--
1.5.3.4-dirty
^ permalink raw reply related
* [PATCH 2/2] [POWERPC] Xilinx: Virtex: Enable dcr for MMIO and NATIVE
From: Stephen Neuendorffer @ 2008-04-18 21:55 UTC (permalink / raw)
To: benh, linuxppc-dev
In-Reply-To: <1208555704-8978-1-git-send-email-stephen.neuendorffer@xilinx.com>
FPGA designs may have need of both MMIO-based and NATIVE-based dcr
interfaces.
Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com>
---
arch/powerpc/platforms/40x/Kconfig | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index a9260e2..b8e06df 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -123,6 +123,8 @@ config 405GPR
config XILINX_VIRTEX
bool
+ select PPC_DCR_MMIO
+ select PPC_DCR_NATIVE
config XILINX_VIRTEX_II_PRO
bool
--
1.5.3.4-dirty
^ permalink raw reply related
* RE: [PATCH 1/5] [v2][POWERPC] refactor dcr code
From: Stephen Neuendorffer @ 2008-04-18 21:49 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1206914576.10388.132.camel@pasglop>
Ben,
I'd like to get the first two patches tested and queued up for mainline
(although it's probably too late for this merge window, I suppose). I'm
going to punt on the ppc patches and put off fixing the tft driver until
ARCH=3Dppc goes away.
I've fixed a typo in patch description: The dcr-access-method attribute
is on the dcr-controller, not the dcr slave.
Steve
> -----Original Message-----
> From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> Sent: Sunday, March 30, 2008 3:03 PM
> To: Stephen Neuendorffer
> Cc: linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH 1/5] [v2][POWERPC] refactor dcr code
>=20
>=20
> On Fri, 2008-03-28 at 09:23 -0700, Stephen Neuendorffer wrote:
> > Previously, dcr support was configured at compile time to either
using
> > MMIO or native dcr instructions. Although this works for most
> > platforms, it fails on FPGA platforms:
> >
> > 1) Systems may include more than one dcr bus.
> > 2) Systems may be native dcr capable and still use memory mapped dcr
interface.
> >
> > This patch provides runtime support based on the device trees for
the
> > case where CONFIG_PPC_DCR_MMIO and CONFIG_PPC_DCR_NATIVE are both
> > selected. Previously, this was a poorly defined configuration,
which
> > happened to provide NATIVE support. The runtime selection is made
> > based on the dcr slave device having a 'dcr-access-method' attribute
> > in the device tree. If only one of the above options is selected,
> > then the code uses #defines to select only the used code in order to
> > avoid interoducing overhead in existing usage.
> >
> > Signed-off-by: Stephen Neuendorffer
<stephen.neuendorffer@xilinx.com>
>=20
> Looks good. Haven't had a chance to test it yet, but tentatively
>=20
> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>=20
> Initially, I thought about using function pointers but the if/else
will
> probably end up being more efficient. The only thing maybe to ponder
> is whether we could avoid the dcr-generic.h file completely, and have
> the generic wrappers be inline, though considering how slow DCRs are,
> it may not be that useful in practice and less clean...
>=20
> Cheers,
> Ben.
>=20
>=20
> > ---
> > arch/powerpc/sysdev/dcr.c | 91
++++++++++++++++++++++++++++++++-----
> > include/asm-powerpc/dcr-generic.h | 49 ++++++++++++++++++++
> > include/asm-powerpc/dcr-mmio.h | 20 +++++---
> > include/asm-powerpc/dcr-native.h | 16 ++++---
> > include/asm-powerpc/dcr.h | 36 ++++++++++++++-
> > 5 files changed, 186 insertions(+), 26 deletions(-)
> > create mode 100644 include/asm-powerpc/dcr-generic.h
> >
> > diff --git a/arch/powerpc/sysdev/dcr.c b/arch/powerpc/sysdev/dcr.c
> > index 437e48d..d3de0ff 100644
> > --- a/arch/powerpc/sysdev/dcr.c
> > +++ b/arch/powerpc/sysdev/dcr.c
> > @@ -23,6 +23,68 @@
> > #include <asm/prom.h>
> > #include <asm/dcr.h>
> >
> > +#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
> > +
> > +bool dcr_map_ok_generic(dcr_host_t host)
> > +{
> > + if (host.type =3D=3D INVALID)
> > + return 0;
> > + else if (host.type =3D=3D NATIVE)
> > + return dcr_map_ok_native(host.host.native);
> > + else
> > + return dcr_map_ok_mmio(host.host.mmio);
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_map_ok_generic);
> > +
> > +dcr_host_t dcr_map_generic(struct device_node *dev,
> > + unsigned int dcr_n,
> > + unsigned int dcr_c)
> > +{
> > + dcr_host_t host;
> > + const char *prop =3D of_get_property(dev, "dcr-access-method",
NULL);
> > +
> > + if (!strcmp(prop, "native")) {
> > + host.type =3D NATIVE;
> > + host.host.native =3D dcr_map_native(dev, dcr_n, dcr_c);
> > + } else if (!strcmp(prop, "mmio")) {
> > + host.type =3D MMIO;
> > + host.host.mmio =3D dcr_map_mmio(dev, dcr_n, dcr_c);
> > + } else
> > + host.type =3D INVALID;
> > +
> > + return host;
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_map_generic);
> > +
> > +void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c)
> > +{
> > + if (host.type =3D=3D NATIVE)
> > + dcr_unmap_native(host.host.native, dcr_c);
> > + else
> > + dcr_unmap_mmio(host.host.mmio, dcr_c);
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_unmap_generic);
> > +
> > +u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n)
> > +{
> > + if (host.type =3D=3D NATIVE)
> > + return dcr_read_native(host.host.native, dcr_n);
> > + else
> > + return dcr_read_mmio(host.host.mmio, dcr_n);
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_read_generic);
> > +
> > +void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32
value)
> > +{
> > + if (host.type =3D=3D NATIVE)
> > + dcr_write_native(host.host.native, dcr_n, value);
> > + else
> > + dcr_write_mmio(host.host.mmio, dcr_n, value);
> > +}
> > +EXPORT_SYMBOL_GPL(dcr_write_generic);
> > +
> > +#endif /* defined(CONFIG_PPC_DCR_NATIVE) &&
defined(CONFIG_PPC_DCR_MMIO) */
> > +
> > unsigned int dcr_resource_start(struct device_node *np, unsigned
int index)
> > {
> > unsigned int ds;
> > @@ -47,7 +109,7 @@ unsigned int dcr_resource_len(struct device_node
*np, unsigned int index)
> > }
> > EXPORT_SYMBOL_GPL(dcr_resource_len);
> >
> > -#ifndef CONFIG_PPC_DCR_NATIVE
> > +#ifdef CONFIG_PPC_DCR_MMIO
> >
> > static struct device_node * find_dcr_parent(struct device_node *
node)
> > {
> > @@ -101,18 +163,19 @@ u64 of_translate_dcr_address(struct
device_node *dev,
> > return ret;
> > }
> >
> > -dcr_host_t dcr_map(struct device_node *dev, unsigned int dcr_n,
> > - unsigned int dcr_c)
> > +dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
> > + unsigned int dcr_n,
> > + unsigned int dcr_c)
> > {
> > - dcr_host_t ret =3D { .token =3D NULL, .stride =3D 0, .base =3D =
dcr_n };
> > + dcr_host_mmio_t ret =3D { .token =3D NULL, .stride =3D 0, .base =
=3D
dcr_n };
> > u64 addr;
> >
> > pr_debug("dcr_map(%s, 0x%x, 0x%x)\n",
> > dev->full_name, dcr_n, dcr_c);
> >
> > addr =3D of_translate_dcr_address(dev, dcr_n, &ret.stride);
> > - pr_debug("translates to addr: 0x%lx, stride: 0x%x\n",
> > - addr, ret.stride);
> > + pr_debug("translates to addr: 0x%llx, stride: 0x%x\n",
> > + (unsigned long long) addr, ret.stride);
> > if (addr =3D=3D OF_BAD_ADDR)
> > return ret;
> > pr_debug("mapping 0x%x bytes\n", dcr_c * ret.stride);
> > @@ -124,11 +187,11 @@ dcr_host_t dcr_map(struct device_node *dev,
unsigned int dcr_n,
> > ret.token -=3D dcr_n * ret.stride;
> > return ret;
> > }
> > -EXPORT_SYMBOL_GPL(dcr_map);
> > +EXPORT_SYMBOL_GPL(dcr_map_mmio);
> >
> > -void dcr_unmap(dcr_host_t host, unsigned int dcr_c)
> > +void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c)
> > {
> > - dcr_host_t h =3D host;
> > + dcr_host_mmio_t h =3D host;
> >
> > if (h.token =3D=3D NULL)
> > return;
> > @@ -136,7 +199,11 @@ void dcr_unmap(dcr_host_t host, unsigned int
dcr_c)
> > iounmap(h.token);
> > h.token =3D NULL;
> > }
> > -EXPORT_SYMBOL_GPL(dcr_unmap);
> > -#else /* defined(CONFIG_PPC_DCR_NATIVE) */
> > +EXPORT_SYMBOL_GPL(dcr_unmap_mmio);
> > +
> > +#endif /* defined(CONFIG_PPC_DCR_MMIO) */
> > +
> > +#ifdef CONFIG_PPC_DCR_NATIVE
> > DEFINE_SPINLOCK(dcr_ind_lock);
> > -#endif /* !defined(CONFIG_PPC_DCR_NATIVE) */
> > +#endif /* defined(CONFIG_PPC_DCR_NATIVE) */
> > +
> > diff --git a/include/asm-powerpc/dcr-generic.h
b/include/asm-powerpc/dcr-generic.h
> > new file mode 100644
> > index 0000000..0ee74fb
> > --- /dev/null
> > +++ b/include/asm-powerpc/dcr-generic.h
> > @@ -0,0 +1,49 @@
> > +/*
> > + * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
> > + * <benh@kernel.crashing.org>
> > + *
> > + * This program is free software; you can redistribute it and/or
modify
> > + * it under the terms of the GNU General Public License as
published by
> > + * the Free Software Foundation; either version 2 of the License,
or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be
useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty
of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
> > + * the GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public
License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA
> > + */
> > +
> > +#ifndef _ASM_POWERPC_DCR_GENERIC_H
> > +#define _ASM_POWERPC_DCR_GENERIC_H
> > +#ifdef __KERNEL__
> > +#ifndef __ASSEMBLY__
> > +
> > +enum host_type_t {MMIO, NATIVE, INVALID};
> > +
> > +typedef struct {
> > + enum host_type_t type;
> > + union {
> > + dcr_host_mmio_t mmio;
> > + dcr_host_native_t native;
> > + } host;
> > +} dcr_host_t;
> > +
> > +extern bool dcr_map_ok_generic(dcr_host_t host);
> > +
> > +extern dcr_host_t dcr_map_generic(struct device_node *dev, unsigned
int dcr_n,
> > + unsigned int dcr_c);
> > +extern void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c);
> > +
> > +extern u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n);
> > +
> > +extern void dcr_write_generic(dcr_host_t host, unsigned int dcr_n,
u32 value);
> > +
> > +#endif /* __ASSEMBLY__ */
> > +#endif /* __KERNEL__ */
> > +#endif /* _ASM_POWERPC_DCR_GENERIC_H */
> > +
> > +
> > diff --git a/include/asm-powerpc/dcr-mmio.h
b/include/asm-powerpc/dcr-mmio.h
> > index 08532ff..acd491d 100644
> > --- a/include/asm-powerpc/dcr-mmio.h
> > +++ b/include/asm-powerpc/dcr-mmio.h
> > @@ -27,20 +27,26 @@ typedef struct {
> > void __iomem *token;
> > unsigned int stride;
> > unsigned int base;
> > -} dcr_host_t;
> > +} dcr_host_mmio_t;
> >
> > -#define DCR_MAP_OK(host) ((host).token !=3D NULL)
> > +static inline bool dcr_map_ok_mmio(dcr_host_mmio_t host)
> > +{
> > + return host.token !=3D NULL;
> > +}
> >
> > -extern dcr_host_t dcr_map(struct device_node *dev, unsigned int
dcr_n,
> > - unsigned int dcr_c);
> > -extern void dcr_unmap(dcr_host_t host, unsigned int dcr_c);
> > +extern dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
> > + unsigned int dcr_n,
> > + unsigned int dcr_c);
> > +extern void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int
dcr_c);
> >
> > -static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n)
> > +static inline u32 dcr_read_mmio(dcr_host_mmio_t host, unsigned int
dcr_n)
> > {
> > return in_be32(host.token + ((host.base + dcr_n) *
host.stride));
> > }
> >
> > -static inline void dcr_write(dcr_host_t host, unsigned int dcr_n,
u32 value)
> > +static inline void dcr_write_mmio(dcr_host_mmio_t host,
> > + unsigned int dcr_n,
> > + u32 value)
> > {
> > out_be32(host.token + ((host.base + dcr_n) * host.stride),
value);
> > }
> > diff --git a/include/asm-powerpc/dcr-native.h
b/include/asm-powerpc/dcr-native.h
> > index be6c879..67832e5 100644
> > --- a/include/asm-powerpc/dcr-native.h
> > +++ b/include/asm-powerpc/dcr-native.h
> > @@ -26,14 +26,18 @@
> >
> > typedef struct {
> > unsigned int base;
> > -} dcr_host_t;
> > +} dcr_host_native_t;
> >
> > -#define DCR_MAP_OK(host) (1)
> > +static inline bool dcr_map_ok_native(dcr_host_native_t host)
> > +{
> > + return 1;
> > +}
> >
> > -#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base =3D (dcr_n)
})
> > -#define dcr_unmap(host, dcr_c) do {} while (0)
> > -#define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base)
> > -#define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base,
value)
> > +#define dcr_map_native(dev, dcr_n, dcr_c) \
> > + ((dcr_host_native_t){ .base =3D (dcr_n) })
> > +#define dcr_unmap_native(host, dcr_c) do {} while (0)
> > +#define dcr_read_native(host, dcr_n) mfdcr(dcr_n +
host.base)
> > +#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n +
host.base, value)
> >
> > /* Device Control Registers */
> > void __mtdcr(int reg, unsigned int val);
> > diff --git a/include/asm-powerpc/dcr.h b/include/asm-powerpc/dcr.h
> > index 9338d50..6b86322 100644
> > --- a/include/asm-powerpc/dcr.h
> > +++ b/include/asm-powerpc/dcr.h
> > @@ -20,14 +20,47 @@
> > #ifndef _ASM_POWERPC_DCR_H
> > #define _ASM_POWERPC_DCR_H
> > #ifdef __KERNEL__
> > +#ifndef __ASSEMBLY__
> > #ifdef CONFIG_PPC_DCR
> >
> > #ifdef CONFIG_PPC_DCR_NATIVE
> > #include <asm/dcr-native.h>
> > -#else
> > +#endif
> > +
> > +#ifdef CONFIG_PPC_DCR_MMIO
> > #include <asm/dcr-mmio.h>
> > #endif
> >
> > +#if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
> > +
> > +#include <asm/dcr-generic.h>
> > +
> > +#define DCR_MAP_OK(host) dcr_map_ok_generic(host)
> > +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_generic(dev, dcr_n,
dcr_c)
> > +#define dcr_unmap(host, dcr_c) dcr_unmap_generic(host, dcr_c)
> > +#define dcr_read(host, dcr_n) dcr_read_generic(host, dcr_n)
> > +#define dcr_write(host, dcr_n, value) dcr_write_generic(host,
dcr_n, value)
> > +
> > +#else
> > +
> > +#ifdef CONFIG_PPC_DCR_NATIVE
> > +typedef dcr_host_native_t dcr_host_t;
> > +#define DCR_MAP_OK(host) dcr_map_ok_native(host)
> > +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_native(dev, dcr_n,
dcr_c)
> > +#define dcr_unmap(host, dcr_c) dcr_unmap_native(host, dcr_c)
> > +#define dcr_read(host, dcr_n) dcr_read_native(host, dcr_n)
> > +#define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n,
value)
> > +#else
> > +typedef dcr_host_mmio_t dcr_host_t;
> > +#define DCR_MAP_OK(host) dcr_map_ok_mmio(host)
> > +#define dcr_map(dev, dcr_n, dcr_c) dcr_map_mmio(dev, dcr_n, dcr_c)
> > +#define dcr_unmap(host, dcr_c) dcr_unmap_mmio(host, dcr_c)
> > +#define dcr_read(host, dcr_n) dcr_read_mmio(host, dcr_n)
> > +#define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n,
value)
> > +#endif
> > +
> > +#endif /* defined(CONFIG_PPC_DCR_NATIVE) &&
defined(CONFIG_PPC_DCR_MMIO) */
> > +
> > /*
> > * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR
> > * base from the device-tree
> > @@ -41,5 +74,6 @@ extern unsigned int dcr_resource_len(struct
device_node *np,
> > #endif /* CONFIG_PPC_MERGE */
> >
> > #endif /* CONFIG_PPC_DCR */
> > +#endif /* __ASSEMBLY__ */
> > #endif /* __KERNEL__ */
> > #endif /* _ASM_POWERPC_DCR_H */
>=20
^ permalink raw reply
* Re: [PATCH] sysdev,mv64x60: initialization of mv64x60 ethernet, serial and I2C
From: Dale Farnsworth @ 2008-04-18 20:58 UTC (permalink / raw)
To: Remi Machet; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <1208475355.5789.30.camel@pcds-ts102.slac.stanford.edu>
On Thu, Apr 17, 2008 at 04:35:55PM -0700, Remi Machet wrote:
> This patch affects only the mv64x60 driver. It fixes 2 problem:
Hi Remi,
Thanks for finding and addressing these issues.
BTW, since you're fixing 2 problems, you might split this into 2 patches.
> -If one of the devices of the mv64x60 init fails, the remaining
> devices are not initialized => I changed the code to display an
> error and continue the initialization.
I agree that this is a good idea. A small comment on details below.
> -I2C parameters freq_m and freq_n are assigned default in the code
> but if those properties are not found in the open firmware description
> the init returns an error=> the code now uses the default
> values if the properties are not found.
Yes. Sigh, I can't believe I missed this.
> diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
> index 047b310..ef0fc99 100644
> --- a/arch/powerpc/sysdev/mv64x60_dev.c
> +++ b/arch/powerpc/sysdev/mv64x60_dev.c
> @@ -433,9 +431,15 @@ static int __init mv64x60_device_setup(void)
> int err;
>
> id = 0;
> - for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc")
> - if ((err = mv64x60_mpsc_device_setup(np, id++)))
> - goto error;
> + for_each_compatible_node(np, "serial", "marvell,mv64360-mpsc") {
> + err = mv64x60_mpsc_device_setup(np, id++);
> + if (err) {
> + printk(KERN_ERR "Failed to initialize MV64x60 " \
> + "serial device %s: error %d.\n",
> + np->full_name, err);
> + of_node_put(np);
This of_node_put call (and the others you added) are not needed.
Thanks,
-Dale
^ permalink raw reply
* [PATCH 2/2] aic79xx: fix MMIO for PPC 44x platforms
From: Sergei Shtylyov @ 2008-04-18 19:39 UTC (permalink / raw)
To: James.Bottomley, hare; +Cc: linuxppc-dev, linux-scsi
The driver stores the PCI resource address into 'u_long' variable before
calling ioremap_nocache() on it. This warrants kernel oops when the registers
are accessed on PPC 44x platforms which (being 32-bit) have PCI memory space
mapped beyond 4 GB.
The arch/ppc/ kernel has a fixup in ioremap() that helps create an illusion
that the PCI memory resources are mapped below 4 GB, but arch/powerpc/ code
got rid of this trick, having instead CONFIG_RESOURCES_64BIT enabled.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
---
Changed ahd_linux_pci_reserve_io_region() prototype "for consistency", although
'u_long' was good for the I/O space addresses.
This is the same issue as the one that has been recently addressed by commits
3c34ac36ac1084e571ef9b6fb1d6a5b10ccc1fd0 (e1000: Fix for 32 bits platforms with
64 bits resources) and c976816b6e901341ec3c4653147316c15549a1c4 (siimage: fix
kernel oops on PPC 44x). The patch has only been compile tested though...
drivers/scsi/aic7xxx/aic79xx_osm.h | 2 +-
drivers/scsi/aic7xxx/aic79xx_osm_pci.c | 29 +++++++++++++++--------------
2 files changed, 16 insertions(+), 15 deletions(-)
Index: linux-2.6/drivers/scsi/aic7xxx/aic79xx_osm.h
===================================================================
--- linux-2.6.orig/drivers/scsi/aic7xxx/aic79xx_osm.h
+++ linux-2.6/drivers/scsi/aic7xxx/aic79xx_osm.h
@@ -376,7 +376,7 @@ struct ahd_platform_data {
#define AHD_LINUX_NOIRQ ((uint32_t)~0)
uint32_t irq; /* IRQ for this adapter */
uint32_t bios_address;
- uint32_t mem_busaddr; /* Mem Base Addr */
+ resource_size_t mem_busaddr; /* Mem Base Addr */
};
/************************** OS Utility Wrappers *******************************/
Index: linux-2.6/drivers/scsi/aic7xxx/aic79xx_osm_pci.c
===================================================================
--- linux-2.6.orig/drivers/scsi/aic7xxx/aic79xx_osm_pci.c
+++ linux-2.6/drivers/scsi/aic7xxx/aic79xx_osm_pci.c
@@ -249,8 +249,8 @@ ahd_linux_pci_exit(void)
}
static int
-ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, u_long *base,
- u_long *base2)
+ahd_linux_pci_reserve_io_regions(struct ahd_softc *ahd, resource_size_t *base,
+ resource_size_t *base2)
{
*base = pci_resource_start(ahd->dev_softc, 0);
/*
@@ -272,11 +272,11 @@ ahd_linux_pci_reserve_io_regions(struct
static int
ahd_linux_pci_reserve_mem_region(struct ahd_softc *ahd,
- u_long *bus_addr,
+ resource_size_t *bus_addr,
uint8_t __iomem **maddr)
{
- u_long start;
- u_long base_page;
+ resource_size_t start;
+ resource_size_t base_page;
u_long base_offset;
int error = 0;
@@ -310,7 +310,7 @@ int
ahd_pci_map_registers(struct ahd_softc *ahd)
{
uint32_t command;
- u_long base;
+ resource_size_t base;
uint8_t __iomem *maddr;
int error;
@@ -346,31 +346,32 @@ ahd_pci_map_registers(struct ahd_softc *
} else
command |= PCIM_CMD_MEMEN;
} else if (bootverbose) {
- printf("aic79xx: PCI%d:%d:%d MEM region 0x%lx "
+ printf("aic79xx: PCI%d:%d:%d MEM region 0x%llx "
"unavailable. Cannot memory map device.\n",
ahd_get_pci_bus(ahd->dev_softc),
ahd_get_pci_slot(ahd->dev_softc),
ahd_get_pci_function(ahd->dev_softc),
- base);
+ (unsigned long long)base);
}
if (maddr == NULL) {
- u_long base2;
+ resource_size_t base2;
error = ahd_linux_pci_reserve_io_regions(ahd, &base, &base2);
if (error == 0) {
ahd->tags[0] = BUS_SPACE_PIO;
ahd->tags[1] = BUS_SPACE_PIO;
- ahd->bshs[0].ioport = base;
- ahd->bshs[1].ioport = base2;
+ ahd->bshs[0].ioport = (u_long)base;
+ ahd->bshs[1].ioport = (u_long)base2;
command |= PCIM_CMD_PORTEN;
} else {
- printf("aic79xx: PCI%d:%d:%d IO regions 0x%lx and 0x%lx"
- "unavailable. Cannot map device.\n",
+ printf("aic79xx: PCI%d:%d:%d IO regions 0x%llx and "
+ "0x%llx unavailable. Cannot map device.\n",
ahd_get_pci_bus(ahd->dev_softc),
ahd_get_pci_slot(ahd->dev_softc),
ahd_get_pci_function(ahd->dev_softc),
- base, base2);
+ (unsigned long long)base,
+ (unsigned long long)base2);
}
}
ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, 4);
^ permalink raw reply
* [PATCH 1/2] aic7xxx: fix MMIO for PPC 44x platforms
From: Sergei Shtylyov @ 2008-04-18 19:30 UTC (permalink / raw)
To: James.Bottomley, hare; +Cc: linuxppc-dev, linux-scsi
The driver stores the PCI resource address into 'u_long' variable before
calling ioremap_nocache() on it. This warrants kernel oops when the registers
are accessed on PPC 44x platforms which (being 32-bit) have PCI memory space
mapped beyond 4 GB.
The arch/ppc/ kernel has a fixup in ioremap() that helps create an illusion
that the PCI memory resources are mapped below 4 GB, but arch/powerpc/ code
got rid of this trick, having instead CONFIG_RESOURCES_64BIT enabled.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
---
Reworked to address James' comments.
This is the same issue as the one that has been recently addressed by commits
3c34ac36ac1084e571ef9b6fb1d6a5b10ccc1fd0 (e1000: Fix for 32 bits platforms with
64 bits resources) and c976816b6e901341ec3c4653147316c15549a1c4 (siimage: fix
kernel oops on PPC 44x). The patch has only been compile tested though...
drivers/scsi/aic7xxx/aic7xxx_osm.h | 2 +-
drivers/scsi/aic7xxx/aic7xxx_osm_pci.c | 18 +++++++++---------
2 files changed, 10 insertions(+), 10 deletions(-)
Index: linux-2.6/drivers/scsi/aic7xxx/aic7xxx_osm.h
===================================================================
--- linux-2.6.orig/drivers/scsi/aic7xxx/aic7xxx_osm.h
+++ linux-2.6/drivers/scsi/aic7xxx/aic7xxx_osm.h
@@ -365,7 +365,7 @@ struct ahc_platform_data {
#define AHC_LINUX_NOIRQ ((uint32_t)~0)
uint32_t irq; /* IRQ for this adapter */
uint32_t bios_address;
- uint32_t mem_busaddr; /* Mem Base Addr */
+ resource_size_t mem_busaddr; /* Mem Base Addr */
};
/************************** OS Utility Wrappers *******************************/
Index: linux-2.6/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c
===================================================================
--- linux-2.6.orig/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c
+++ linux-2.6/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c
@@ -293,7 +293,7 @@ ahc_linux_pci_exit(void)
}
static int
-ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, u_long *base)
+ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, resource_size_t *base)
{
if (aic7xxx_allow_memio == 0)
return (ENOMEM);
@@ -308,10 +308,10 @@ ahc_linux_pci_reserve_io_region(struct a
static int
ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
- u_long *bus_addr,
+ resource_size_t *bus_addr,
uint8_t __iomem **maddr)
{
- u_long start;
+ resource_size_t start;
int error;
error = 0;
@@ -336,7 +336,7 @@ int
ahc_pci_map_registers(struct ahc_softc *ahc)
{
uint32_t command;
- u_long base;
+ resource_size_t base;
uint8_t __iomem *maddr;
int error;
@@ -374,12 +374,12 @@ ahc_pci_map_registers(struct ahc_softc *
} else
command |= PCIM_CMD_MEMEN;
} else {
- printf("aic7xxx: PCI%d:%d:%d MEM region 0x%lx "
+ printf("aic7xxx: PCI%d:%d:%d MEM region 0x%llx "
"unavailable. Cannot memory map device.\n",
ahc_get_pci_bus(ahc->dev_softc),
ahc_get_pci_slot(ahc->dev_softc),
ahc_get_pci_function(ahc->dev_softc),
- base);
+ (unsigned long long)base);
}
/*
@@ -390,15 +390,15 @@ ahc_pci_map_registers(struct ahc_softc *
error = ahc_linux_pci_reserve_io_region(ahc, &base);
if (error == 0) {
ahc->tag = BUS_SPACE_PIO;
- ahc->bsh.ioport = base;
+ ahc->bsh.ioport = (u_long)base;
command |= PCIM_CMD_PORTEN;
} else {
- printf("aic7xxx: PCI%d:%d:%d IO region 0x%lx[0..255] "
+ printf("aic7xxx: PCI%d:%d:%d IO region 0x%llx[0..255] "
"unavailable. Cannot map device.\n",
ahc_get_pci_bus(ahc->dev_softc),
ahc_get_pci_slot(ahc->dev_softc),
ahc_get_pci_function(ahc->dev_softc),
- base);
+ (unsigned long long)base);
}
}
ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox