* [PATCH v2] ibm_newemac: Fixes entry of short packets
From: Stefan Roese @ 2008-07-01 8:58 UTC (permalink / raw)
To: linuxppc-dev, netdev; +Cc: Sathya Narayanan
From: Sathya Narayanan <sathyan@teamf1.com>
Short packets has to be discarded by the driver. So this patch addresses the
issue of discarding the short packets of size lesser then ethernet header
size.
Signed-off-by: Sathya Narayanan <sathyan@teamf1.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/net/ibm_newemac/core.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c
index ca63fa0..babc79a 100644
--- a/drivers/net/ibm_newemac/core.c
+++ b/drivers/net/ibm_newemac/core.c
@@ -1636,6 +1636,12 @@ static int emac_poll_rx(void *param, int budget)
goto next;
}
+ if (len < ETH_HLEN) {
+ ++dev->estats.rx_dropped_stack;
+ emac_recycle_rx_skb(dev, slot, len);
+ goto next;
+ }
+
if (len && len < EMAC_RX_COPY_THRESH) {
struct sk_buff *copy_skb =
alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
--
1.5.6.1
^ permalink raw reply related
* [PATCH v3] ibm_newemac: Fixes kernel crashes when speed of cable connected changes
From: Stefan Roese @ 2008-07-01 8:58 UTC (permalink / raw)
To: linuxppc-dev, netdev; +Cc: Sathya Narayanan
From: Sathya Narayanan <sathyan@teamf1.com>
The descriptor pointers were not initialized to NIL values, so it was
poiniting to some random addresses which was completely invalid. This
fix takes care of initializing the descriptor to NIL values and clearing
the valid descriptors on clean ring operation.
Signed-off-by: Sathya Narayanan <sathyan@teamf1.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
drivers/net/ibm_newemac/core.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c
index 5d2108c..ca63fa0 100644
--- a/drivers/net/ibm_newemac/core.c
+++ b/drivers/net/ibm_newemac/core.c
@@ -2719,6 +2719,8 @@ static int __devinit emac_probe(struct of_device *ofdev,
/* Clean rings */
memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor));
memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor));
+ memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *));
+ memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *));
/* Attach to ZMII, if needed */
if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) &&
--
1.5.6.1
^ permalink raw reply related
* Re: [patch 1/6] mm: Allow architectures to define additional protection bits
From: Andrew Morton @ 2008-07-01 8:53 UTC (permalink / raw)
To: shaggy; +Cc: Hugh Dickins, linux-mm, Paul Mackerras, Linuxppc-dev
In-Reply-To: <20080618223328.856102092@linux.vnet.ibm.com>
On Wed, 18 Jun 2008 17:32:55 -0500 shaggy@linux.vnet.ibm.com wrote:
> This patch allows architectures to define functions to deal with
> additional protections bits for mmap() and mprotect().
>
> arch_calc_vm_prot_bits() maps additonal protection bits to vm_flags
> arch_vm_get_page_prot() maps additional vm_flags to the vma's vm_page_prot
> arch_validate_prot() checks for valid values of the protection bits
It'd be simpler if Paul were to merge this. It doesn't conflict with
any pending work.
Acked-by: Andrew Morton <akpm@linux-foundation.org>
> Note: vm_get_page_prot() is now pretty ugly.
It is. But afacit it generates the same code for non-powerpc.
> Suggestions?
nfi. Let us rub the Hugh-summoning lamp.
> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
> ---
>
> include/linux/mman.h | 28 +++++++++++++++++++++++++++-
> mm/mmap.c | 5 +++--
> mm/mprotect.c | 2 +-
> 3 files changed, 31 insertions(+), 4 deletions(-)
>
> Index: linux-2.6.26-rc5/include/linux/mman.h
> ===================================================================
> --- linux-2.6.26-rc5.orig/include/linux/mman.h
> +++ linux-2.6.26-rc5/include/linux/mman.h
> @@ -34,6 +34,31 @@ static inline void vm_unacct_memory(long
> }
>
> /*
> + * Allow architectures to handle additional protection bits
> + */
> +
> +#ifndef arch_calc_vm_prot_bits
> +#define arch_calc_vm_prot_bits(prot) 0
> +#endif
> +
> +#ifndef arch_vm_get_page_prot
> +#define arch_vm_get_page_prot(vm_flags) __pgprot(0)
> +#endif
> +
> +#ifndef arch_validate_prot
> +/*
> + * This is called from mprotect(). PROT_GROWSDOWN and PROT_GROWSUP have
> + * already been masked out.
> + *
> + * Returns true if the prot flags are valid
> + */
> +static inline int arch_validate_prot(unsigned long prot)
> +{
> + return (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM)) == 0;
> +}
Officially we should now have
#define arch_validate_prot arch_validate_prot
here.
> +#endif
> +
> +/*
> * Optimisation macro. It is equivalent to:
> * (x & bit1) ? bit2 : 0
> * but this version is faster.
> @@ -51,7 +76,8 @@ calc_vm_prot_bits(unsigned long prot)
> {
> return _calc_vm_trans(prot, PROT_READ, VM_READ ) |
> _calc_vm_trans(prot, PROT_WRITE, VM_WRITE) |
> - _calc_vm_trans(prot, PROT_EXEC, VM_EXEC );
> + _calc_vm_trans(prot, PROT_EXEC, VM_EXEC) |
> + arch_calc_vm_prot_bits(prot);
> }
>
> /*
> Index: linux-2.6.26-rc5/mm/mmap.c
> ===================================================================
> --- linux-2.6.26-rc5.orig/mm/mmap.c
> +++ linux-2.6.26-rc5/mm/mmap.c
> @@ -72,8 +72,9 @@ pgprot_t protection_map[16] = {
>
> pgprot_t vm_get_page_prot(unsigned long vm_flags)
> {
> - return protection_map[vm_flags &
> - (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)];
> + return __pgprot(pgprot_val(protection_map[vm_flags &
> + (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]) |
> + pgprot_val(arch_vm_get_page_prot(vm_flags)));
> }
> EXPORT_SYMBOL(vm_get_page_prot);
>
> Index: linux-2.6.26-rc5/mm/mprotect.c
> ===================================================================
> --- linux-2.6.26-rc5.orig/mm/mprotect.c
> +++ linux-2.6.26-rc5/mm/mprotect.c
> @@ -239,7 +239,7 @@ sys_mprotect(unsigned long start, size_t
> end = start + len;
> if (end <= start)
> return -ENOMEM;
> - if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM))
> + if (!arch_validate_prot(prot))
> return -EINVAL;
>
> reqprot = prot;
>
> --
^ permalink raw reply
* Re: Commits added to powerpc.git master and powerpc-next branches
From: Laurent Pinchart @ 2008-07-01 8:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
In-Reply-To: <18537.30774.608486.268257@cargo.ozlabs.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1180 bytes --]
Hi Paul,
On Tuesday 01 July 2008, Paul Mackerras wrote:
> The following commits have been added to the master and powerpc-next
> branches of the powerpc.git repository. This includes patches pulled
> from Kumar's and Josh's trees.
Any change of getting the following patches into 2.6.27 ? They have either been acked and not picked, or just ignored so far :-/
[PATCHv2] fs_enet: restore promiscuous and multicast settings in restart()
http://patchwork.ozlabs.org/linuxppc/patch?person=968&id=19228
[PATCH 2/2] fs_enet: MDIO on GPIO support
http://patchwork.ozlabs.org/linuxppc/patch?person=968&id=18693
[PATCHv3 1/2] [POWERPC] CPM2: Implement GPIO LIB API on CPM2 Freescale SoC.
http://patchwork.ozlabs.org/linuxppc/patch?person=968&id=19045
[PATCH] powerpc: Modem control lines support for the cpm_uart driver
http://patchwork.ozlabs.org/linuxppc/patch?person=968&id=17928
[PATCH] cpm_uart: Support uart_wait_until_sent()
http://patchwork.ozlabs.org/linuxppc/patch?person=968&id=19233
Best regards,
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussee de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: This is a digitally signed message part. --]
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^ permalink raw reply
* Re: [BUILD-FAILURE] linux-next: Tree for June 30 - powerpc - build failure at arch_add_memory()
From: Kamalesh Babulal @ 2008-07-01 8:04 UTC (permalink / raw)
To: Tony Breeds
Cc: Stephen Rothwell, linux-kbuild, LKML, linuxppc-dev, linux-next,
Sam Ravnborg
In-Reply-To: <20080701013438.GT20457@bakeyournoodle.com>
Tony Breeds wrote:
> On Mon, Jun 30, 2008 at 11:55:02PM +0530, Kamalesh Babulal wrote:
>> Hi Stephen,
>>
>> next-20080630 kernel build fails on powerpc, with randconfig
>>
>> CC arch/powerpc/mm/mem.o
>> arch/powerpc/mm/mem.c: In function ‘arch_add_memory’:
>> arch/powerpc/mm/mem.c:130: error: implicit declaration of function ‘create_section_mapping’
>> make[1]: *** [arch/powerpc/mm/mem.o] Error 1
>> make: *** [arch/powerpc/mm] Error 2
>
> This problem exists in in 2.6.26-rc8, so it's not specifially linux-next
> realted. The patch at:
> http://patchwork.ozlabs.org/linuxppc/patch?id=19347
> should fix it but is un-ACK'd ;P
Hi Tony,
Thanks, the patch fixes the build failure on the machine.
>
> Yours Tony
>
> linux.conf.au http://www.marchsouth.org/
> Jan 19 - 24 2009 The Australian Linux Technical Conference!
>
--
Thanks & Regards,
Kamalesh Babulal,
Linux Technology Center,
IBM, ISTL.
^ permalink raw reply
* Re: MPC83xx ipic problem
From: André Schwarz @ 2008-07-01 7:45 UTC (permalink / raw)
To: Scott Wood; +Cc: linux-ppc list
In-Reply-To: <48692E18.9050500@freescale.com>
Scott,
thanks for your reply.
Honestly I don't think the board wiring is incorrect.
FPGA goes to IRQ0 and miniPCI is wired to IRQ1.
Maybe there's a crosstalk problem since the pull-up resistors are=20
packaged inside an array ... I'll check this.
regards,
Andr=C3=A9
Scott Wood schrieb:
> Andr=C3=A9 Schwarz wrote:
>> There are two external PCI devices connected (FPGA + miniPCI socket).
>> The FPGA is working fine and uses IRQ0 for its PCI_INTA line.
>>
>> As soon there's a miniPCI module present and the driver loaded=20
>> (actually an ath5k WiFi module) the system complains after a while :
>>
>> irq 48: nobody cared
>> handlers: .... location of the FPGA irq handler
>> Disabling IRQ #48
>>
>> -> This is weird since the FPGA isn't working at all and IRQ0 is *not*=
=20
>> asserted !
>=20
> Are you *sure* that IRQ0 isn't asserted? The IPIC seems to think it is=
.
>=20
>> Of course the miniPCI irq is routed to a different pin on the CPU (IRQ=
1).
>=20
> Perhaps the board wiring is incorrect?
>=20
>> interrupt-map =3D <0x5800 0 0 1 &ipic 0x30 0x8 -> FPGA @ IRQ0
>> 0x6000 0 0 1 &ipic 0x11 0x8 -> miniPCI INTA @ IR=
Q1
>> 0x6000 0 0 2 &ipic 0x11 0x8>; -> miniPCI INTB @ IR=
Q1
>>
>> Is it legal to use a single irq pin twice ?
>=20
> Yes.
>=20
> -Scott
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
MATRIX VISION GmbH, Talstra=DFe 16, DE-71570 Oppenweiler - Registergeric=
ht: Amtsgericht Stuttgart, HRB 271090
Gesch=E4ftsf=FChrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner
^ permalink raw reply
* linux-next: manual merge of the net tree
From: Stephen Rothwell @ 2008-07-01 7:19 UTC (permalink / raw)
To: David Miller
Cc: linuxppc-dev, linux-next, Paul Mackerras, Jason Jin, Jeff Garzik
[-- Attachment #1: Type: text/plain, Size: 638 bytes --]
Hi Dave,
Today's linux-next merge of the net tree got a conflict in between
commits aee1dc73b519227084d77b0b2fc972b68b4153d8 ("[POWERPC] Update
booting-without-of for Freescale PCIe MSI") and
83ff9dcf375c418ca3b98eb950711525ca1269e2 ("powerpc/sysdev: implement FSL
GTM support") from the powerpc tree and commit
a5edeccb1a8432ae5d9fb9bccea5a4b64c565017 ("net: OpenFirmware GPIO based
MDIO bitbang driver") from the net tree.
They are just overlapping additions. I renumbered(?) the "MDIO on GPIOs"
section to 'v'.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* Re: [PATCH] powerpc: fixup lwsync at runtime
From: Benjamin Herrenschmidt @ 2008-07-01 7:15 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <1214893402.20711.104.camel@pasglop>
On Tue, 2008-07-01 at 16:23 +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2008-07-01 at 00:32 -0500, Kumar Gala wrote:
> > To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync
> > at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up
> > the code. We default to 'sync' since that is always safe and if the cpu
> > is capable we will replace 'sync' with 'lwsync'.
> >
> > We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is
> > needed. This flag could be moved elsewhere since we dont really use it
> > for the normal CPU_FTR purpose.
> >
> > Finally we only store the relative offset in the fixup section to keep it
> > as small as possible rather than using a full fixup_entry.
> >
> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>
> I'd rather have some more generic "alternatives" stuff but in the
> meantime, Ack.
Hrm... minus mpe's comments...
Cheers,
Ben.
^ permalink raw reply
* linux-next: manual merge of the net tree
From: Stephen Rothwell @ 2008-07-01 7:11 UTC (permalink / raw)
To: David Miller; +Cc: linuxppc-dev, linux-next, Paul Mackerras
[-- Attachment #1: Type: text/plain, Size: 596 bytes --]
Hi Dave,
Today's linux-next merge of the net tree got a trivial conflict in
drivers/net/fs_enet/fs_enet-main.c between commit
55b6c8e99d582cc66947b465d0ff3147a0219808 ("drivers/net: Use linux/of_
{device,platform}.h instead of asm") from the powerpc tree and commit
d8b35fac8c7e1b44d873c1afcc5f88bc5ef4b361 ("fs_enet: MDIO on GPIO
support") from the net tree.
I fixed it up and can carry the fixup.
(The powerpc commit just changed asm/of_platform.h to linux/of_platform.h)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* [PATCH] powerpc: fix compile warning in init_thread
From: Michael Neuling @ 2008-07-01 7:00 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <18537.30774.608486.268257@cargo.ozlabs.ibm.com>
arch/powerpc/kernel/init_task.c:33: warning: missing braces around initializer
arch/powerpc/kernel/init_task.c:33: warning: (near initialization for 'init_task.thread.fpr[0]')
Noticed by SFR.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
include/asm-powerpc/processor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: linux-2.6-ozlabs/include/asm-powerpc/processor.h
===================================================================
--- linux-2.6-ozlabs.orig/include/asm-powerpc/processor.h
+++ linux-2.6-ozlabs/include/asm-powerpc/processor.h
@@ -222,7 +222,7 @@ struct thread_struct {
.ksp_limit = INIT_SP_LIMIT, \
.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
.fs = KERNEL_DS, \
- .fpr = {0}, \
+ .fpr = {{0}}, \
.fpscr = { .val = 0, }, \
.fpexc_mode = 0, \
}
^ permalink raw reply
* linux-next: manual merge of the powerpc tree
From: Stephen Rothwell @ 2008-07-01 6:48 UTC (permalink / raw)
To: Paul Mackerras, linuxppc-dev; +Cc: linux-next, Bartlomiej Zolnierkiewicz
[-- Attachment #1: Type: text/plain, Size: 628 bytes --]
Hi Paul,
Today's linux-next merge of the powerpc tree got a conflict in
drivers/macintosh/mediabay.c between commit
3fdba626506365e3aaf49140632120cd9156c2e8 ("ide-pmac: media-bay support
fixes (take 3)") from the ide tree and commit
9a24729d8aeef967eac7af71c6a69edc83d06558 ("macintosh/media bay: Convert
semaphore to mutex") from the powerpc tree.
I used the version from the ide tree but with the down/up ->
mutex_lock/mutex_unlock changes applied. It may be worth a check to make
sure I got it right.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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^ permalink raw reply
* Re: [PATCH v2] Parameterize EMAC Multicast Match Handling
From: Stefan Roese @ 2008-07-01 6:37 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev, Grant Erickson
In-Reply-To: <1214892899.20711.95.camel@pasglop>
On Tuesday 01 July 2008, Benjamin Herrenschmidt wrote:
> > Stefan and/or Ben:
> >
> > Any thoughts on this?
>
> I was hesitating a bit... do we really need to be -that- flexible ?
>
> That is, either that or use some new compatible entry to detect the new
> reg layout and whack that as a feature bit instead ? The advantage
> of the later is that we have the possibility of doing conditional
> compile for kernels that support only a given processor or set of
> processors (not that we have implemented much of it, but it just
> becomes Kconfig mumbo jumbo and a little bit of defines in the .h
> by turning the feature test into a compile-time 0 or 1.
>
> But this isn't a hot path and not a lot of code so maybe not worth
> bothering... however, it does add 3 properties to the DT and I know
> embedded people (especially Xilinx) are a bit concerned about the size
> of the DT when they try to fit it in block RAM...
Yes, this was my feeling too. Not the size of the dtb but more the increased
complexity of the EMAC device node. I would prefer Ben's idea with this new
compatible entry too.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
=====================================================================
^ permalink raw reply
* Re: [PATCH] powerpc: fixup lwsync at runtime
From: Michael Ellerman @ 2008-07-01 6:29 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <Pine.LNX.4.64.0807010031241.23830@blarg.am.freescale.net>
[-- Attachment #1: Type: text/plain, Size: 4013 bytes --]
On Tue, 2008-07-01 at 00:32 -0500, Kumar Gala wrote:
> To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync
> at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up
> the code. We default to 'sync' since that is always safe and if the cpu
> is capable we will replace 'sync' with 'lwsync'.
>
> We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is
> needed. This flag could be moved elsewhere since we dont really use it
> for the normal CPU_FTR purpose.
>
> Finally we only store the relative offset in the fixup section to keep it
> as small as possible rather than using a full fixup_entry.
How many entries are we talking? I guess it's not much bother to have a
separate section.
> diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
> index 9e83add..0109e7f 100644
> --- a/arch/powerpc/kernel/setup_32.c
> +++ b/arch/powerpc/kernel/setup_32.c
> @@ -101,6 +101,10 @@ unsigned long __init early_init(unsigned long dt_ptr)
> PTRRELOC(&__start___ftr_fixup),
> PTRRELOC(&__stop___ftr_fixup));
>
> + do_lwsync_fixups(spec->cpu_features,
> + PTRRELOC(&__start___lwsync_fixup),
> + PTRRELOC(&__stop___lwsync_fixup));
> +
This could be changed to use cur_cpu_spec->cpu_features, and then all
the call sites would be passing that, which would mean
do_lwsync_fixups() could just check cur_cpu_spec->cpu_features directly.
> diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c
> index 48e1ed8..ac5f5a1 100644
> --- a/arch/powerpc/lib/feature-fixups.c
> +++ b/arch/powerpc/lib/feature-fixups.c
> @@ -110,6 +110,22 @@ void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
> }
> }
>
> +void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
> +{
> + unsigned int *start, *end, *dest;
> +
> + if (!(value & CPU_FTR_LWSYNC))
> + return ;
> +
> + start = fixup_start;
> + end = fixup_end;
> +
> + for (; start < end; start++) {
> + dest = (void *)start + *start;
> + patch_instruction(dest, PPC_LWSYNC_INSTR);
> + }
> +}
> +
> #ifdef CONFIG_FTR_FIXUP_SELFTEST
...
No tests? :)
> diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
> index 42a1ef5..4737c61 100644
> --- a/include/asm-powerpc/synch.h
> +++ b/include/asm-powerpc/synch.h
> @@ -3,20 +3,37 @@
> #ifdef __KERNEL__
>
> #include <linux/stringify.h>
> +#include <asm/feature-fixups.h>
>
> -#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
> -#define __SUBARCH_HAS_LWSYNC
> -#endif
> +#ifndef __ASSEMBLY__
> +extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
> +extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
> + void *fixup_end);
> +#endif /* __ASSEMBLY__ */
> +
> +#define START_LWSYNC_SECTION(label) label##1:
> +#define MAKE_LWSYNC_SECTION_ENTRY(label, sect) \
> +label##4: \
> + .pushsection sect,"a"; \
> + .align 2; \
> +label##5: \
> + .long label##1b-label##5b; \
> + .popsection;
I'd rather this was in feature-fixups.h, seeing as I just moved all the
feature-fixup related macros in there :)
It might make more sense to use label##2 and label##3.
>
> -#ifdef __SUBARCH_HAS_LWSYNC
> +#if defined(__powerpc64__)
> # define LWSYNC lwsync
> +#elif defined(CONFIG_E500)
> +# define LWSYNC \
> + START_LWSYNC_SECTION(97); \
> + sync; \
> + MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
> #else
> # define LWSYNC sync
> #endif
Using 97 means you can't nest an LWSYNC inside a feature or firmware
feature section, if you use say 96 then nesting should work.
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* RE: [PATCH 12/60] microblaze_v4: Generic dts file for platforms
From: Benjamin Herrenschmidt @ 2008-07-01 6:21 UTC (permalink / raw)
To: Stephen Neuendorffer
Cc: linux-arch, alan, Michal Simek, vapier.adi, arnd, matthew,
microblaze-uclinux, linux-kernel, linuxppc-dev, will.newton, hpa,
John Linn, monstr, drepper, John Williams
In-Reply-To: <20080630033943.332471860046@mail171-va3.bigfish.com>
> As for the copyright, I haven't been able to find much information on
> whether or not generated files are even copyrightable. One might
> argue that they
> don't have sufficient 'creative value' to be copyrightable. Or
> arguably, they are as copyrightable by the generator author as by the
> author or the .mhs file.
> I admit in this case, I've followed the safe route by claiming a
> copyright, which at least at Xilinx has significant precedent.
Also, thinking about your idea of sticking bits in BRAM etc...
what would be nice would be the ability to "merge" trees. We've been
talking about that multiple times, it would be useful at several levels:
- We could provide pre-made DTs for known CPUs (ie, 440GP, 440GX,
405EX, ...)
- Boards can then include that, and then "override" some properties
(clocks, PHY wiring, ...)
- That could be done at the binary level too so that the BRAM contains
on "overlay" on top of the base ref. platform device-tree that comes
with the kernel for example.
This is slightly different between doing that in the .dts source via
some kind of #include vs. doing that by merging blobs but we could make
it be essentially be the same internally: The #include generates a blob
that is then "merged in".
Just random thoughts...
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: fixup lwsync at runtime
From: Benjamin Herrenschmidt @ 2008-07-01 6:23 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <Pine.LNX.4.64.0807010031241.23830@blarg.am.freescale.net>
On Tue, 2008-07-01 at 00:32 -0500, Kumar Gala wrote:
> To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync
> at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up
> the code. We default to 'sync' since that is always safe and if the cpu
> is capable we will replace 'sync' with 'lwsync'.
>
> We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is
> needed. This flag could be moved elsewhere since we dont really use it
> for the normal CPU_FTR purpose.
>
> Finally we only store the relative offset in the fixup section to keep it
> as small as possible rather than using a full fixup_entry.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
I'd rather have some more generic "alternatives" stuff but in the
meantime, Ack.
> ---
>
> Rebased against latest powerpc-next tree.
>
> - k
>
> arch/powerpc/kernel/module.c | 6 ++++++
> arch/powerpc/kernel/setup_32.c | 4 ++++
> arch/powerpc/kernel/setup_64.c | 2 ++
> arch/powerpc/kernel/vdso.c | 10 ++++++++++
> arch/powerpc/kernel/vdso32/vdso32.lds.S | 3 +++
> arch/powerpc/kernel/vdso64/vdso64.lds.S | 3 +++
> arch/powerpc/kernel/vmlinux.lds.S | 6 ++++++
> arch/powerpc/lib/feature-fixups.c | 16 ++++++++++++++++
> include/asm-powerpc/code-patching.h | 3 ++-
> include/asm-powerpc/cputable.h | 21 +++++++++++----------
> include/asm-powerpc/synch.h | 27 ++++++++++++++++++++++-----
> 11 files changed, 85 insertions(+), 16 deletions(-)
>
> diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
> index 40dd52d..af07003 100644
> --- a/arch/powerpc/kernel/module.c
> +++ b/arch/powerpc/kernel/module.c
> @@ -86,6 +86,12 @@ int module_finalize(const Elf_Ehdr *hdr,
> (void *)sect->sh_addr + sect->sh_size);
> #endif
>
> + sect = find_section(hdr, sechdrs, "__lwsync_fixup");
> + if (sect != NULL)
> + do_lwsync_fixups(cur_cpu_spec->cpu_features,
> + (void *)sect->sh_addr,
> + (void *)sect->sh_addr + sect->sh_size);
> +
> return 0;
> }
>
> diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
> index 9e83add..0109e7f 100644
> --- a/arch/powerpc/kernel/setup_32.c
> +++ b/arch/powerpc/kernel/setup_32.c
> @@ -101,6 +101,10 @@ unsigned long __init early_init(unsigned long dt_ptr)
> PTRRELOC(&__start___ftr_fixup),
> PTRRELOC(&__stop___ftr_fixup));
>
> + do_lwsync_fixups(spec->cpu_features,
> + PTRRELOC(&__start___lwsync_fixup),
> + PTRRELOC(&__stop___lwsync_fixup));
> +
> return KERNELBASE + offset;
> }
>
> diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
> index 098fd96..04d8de9 100644
> --- a/arch/powerpc/kernel/setup_64.c
> +++ b/arch/powerpc/kernel/setup_64.c
> @@ -363,6 +363,8 @@ void __init setup_system(void)
> &__start___ftr_fixup, &__stop___ftr_fixup);
> do_feature_fixups(powerpc_firmware_features,
> &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
> + do_lwsync_fixups(cur_cpu_spec->cpu_features,
> + &__start___lwsync_fixup, &__stop___lwsync_fixup);
>
> /*
> * Unflatten the device-tree passed by prom_init or kexec
> diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
> index ce245a8..f177c60 100644
> --- a/arch/powerpc/kernel/vdso.c
> +++ b/arch/powerpc/kernel/vdso.c
> @@ -571,6 +571,11 @@ static __init int vdso_fixup_features(struct lib32_elfinfo *v32,
> if (start64)
> do_feature_fixups(powerpc_firmware_features,
> start64, start64 + size64);
> +
> + start64 = find_section64(v64->hdr, "__lwsync_fixup", &size64);
> + if (start64)
> + do_lwsync_fixups(cur_cpu_spec->cpu_features,
> + start64, start64 + size64);
> #endif /* CONFIG_PPC64 */
>
> start32 = find_section32(v32->hdr, "__ftr_fixup", &size32);
> @@ -585,6 +590,11 @@ static __init int vdso_fixup_features(struct lib32_elfinfo *v32,
> start32, start32 + size32);
> #endif /* CONFIG_PPC64 */
>
> + start32 = find_section32(v32->hdr, "__lwsync_fixup", &size32);
> + if (start32)
> + do_lwsync_fixups(cur_cpu_spec->cpu_features,
> + start32, start32 + size32);
> +
> return 0;
> }
>
> diff --git a/arch/powerpc/kernel/vdso32/vdso32.lds.S b/arch/powerpc/kernel/vdso32/vdso32.lds.S
> index 2717935..be3b6a4 100644
> --- a/arch/powerpc/kernel/vdso32/vdso32.lds.S
> +++ b/arch/powerpc/kernel/vdso32/vdso32.lds.S
> @@ -33,6 +33,9 @@ SECTIONS
> . = ALIGN(8);
> __ftr_fixup : { *(__ftr_fixup) }
>
> + . = ALIGN(8);
> + __lwsync_fixup : { *(__lwsync_fixup) }
> +
> #ifdef CONFIG_PPC64
> . = ALIGN(8);
> __fw_ftr_fixup : { *(__fw_ftr_fixup) }
> diff --git a/arch/powerpc/kernel/vdso64/vdso64.lds.S b/arch/powerpc/kernel/vdso64/vdso64.lds.S
> index e608d1b..d0b2526 100644
> --- a/arch/powerpc/kernel/vdso64/vdso64.lds.S
> +++ b/arch/powerpc/kernel/vdso64/vdso64.lds.S
> @@ -35,6 +35,9 @@ SECTIONS
> __ftr_fixup : { *(__ftr_fixup) }
>
> . = ALIGN(8);
> + __lwsync_fixup : { *(__lwsync_fixup) }
> +
> + . = ALIGN(8);
> __fw_ftr_fixup : { *(__fw_ftr_fixup) }
>
> /*
> diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
> index 3c07811..6856f6c 100644
> --- a/arch/powerpc/kernel/vmlinux.lds.S
> +++ b/arch/powerpc/kernel/vmlinux.lds.S
> @@ -127,6 +127,12 @@ SECTIONS
> *(__ftr_fixup)
> __stop___ftr_fixup = .;
> }
> + . = ALIGN(8);
> + __lwsync_fixup : AT(ADDR(__lwsync_fixup) - LOAD_OFFSET) {
> + __start___lwsync_fixup = .;
> + *(__lwsync_fixup)
> + __stop___lwsync_fixup = .;
> + }
> #ifdef CONFIG_PPC64
> . = ALIGN(8);
> __fw_ftr_fixup : AT(ADDR(__fw_ftr_fixup) - LOAD_OFFSET) {
> diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c
> index 48e1ed8..ac5f5a1 100644
> --- a/arch/powerpc/lib/feature-fixups.c
> +++ b/arch/powerpc/lib/feature-fixups.c
> @@ -110,6 +110,22 @@ void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
> }
> }
>
> +void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
> +{
> + unsigned int *start, *end, *dest;
> +
> + if (!(value & CPU_FTR_LWSYNC))
> + return ;
> +
> + start = fixup_start;
> + end = fixup_end;
> +
> + for (; start < end; start++) {
> + dest = (void *)start + *start;
> + patch_instruction(dest, PPC_LWSYNC_INSTR);
> + }
> +}
> +
> #ifdef CONFIG_FTR_FIXUP_SELFTEST
>
> #define check(x) \
> diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h
> index ef3a5d1..107d9b9 100644
> --- a/include/asm-powerpc/code-patching.h
> +++ b/include/asm-powerpc/code-patching.h
> @@ -12,7 +12,8 @@
>
> #include <asm/types.h>
>
> -#define PPC_NOP_INSTR 0x60000000
> +#define PPC_NOP_INSTR 0x60000000
> +#define PPC_LWSYNC_INSTR 0x7c2004ac
>
> /* Flags for create_branch:
> * "b" == create_branch(addr, target, 0);
> diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
> index 4e4491c..3171ac9 100644
> --- a/include/asm-powerpc/cputable.h
> +++ b/include/asm-powerpc/cputable.h
> @@ -156,6 +156,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
> #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
> #define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
> #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
> +#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
>
> /*
> * Add the 64-bit processor unique features in the top half of the word;
> @@ -369,43 +370,43 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
> CPU_FTR_NODSISRALIGN)
> #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
> CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
> - CPU_FTR_L2CSR)
> + CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
> #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
>
> /* 64-bit CPUs */
> -#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
> -#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
> CPU_FTR_MMCRA | CPU_FTR_CTRL)
> -#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
> CPU_FTR_MMCRA)
> -#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
> CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
> -#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
> CPU_FTR_MMCRA | CPU_FTR_SMT | \
> CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
> CPU_FTR_PURR)
> -#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
> CPU_FTR_MMCRA | CPU_FTR_SMT | \
> CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
> CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
> CPU_FTR_DSCR)
> -#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
> CPU_FTR_MMCRA | CPU_FTR_SMT | \
> CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
> CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
> CPU_FTR_DSCR)
> -#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
> CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
> CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
> -#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
> +#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
> CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
> CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
> CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
> diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
> index 42a1ef5..4737c61 100644
> --- a/include/asm-powerpc/synch.h
> +++ b/include/asm-powerpc/synch.h
> @@ -3,20 +3,37 @@
> #ifdef __KERNEL__
>
> #include <linux/stringify.h>
> +#include <asm/feature-fixups.h>
>
> -#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
> -#define __SUBARCH_HAS_LWSYNC
> -#endif
> +#ifndef __ASSEMBLY__
> +extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
> +extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
> + void *fixup_end);
> +#endif /* __ASSEMBLY__ */
> +
> +#define START_LWSYNC_SECTION(label) label##1:
> +#define MAKE_LWSYNC_SECTION_ENTRY(label, sect) \
> +label##4: \
> + .pushsection sect,"a"; \
> + .align 2; \
> +label##5: \
> + .long label##1b-label##5b; \
> + .popsection;
>
> -#ifdef __SUBARCH_HAS_LWSYNC
> +#if defined(__powerpc64__)
> # define LWSYNC lwsync
> +#elif defined(CONFIG_E500)
> +# define LWSYNC \
> + START_LWSYNC_SECTION(97); \
> + sync; \
> + MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
> #else
> # define LWSYNC sync
> #endif
>
> #ifdef CONFIG_SMP
> #define ISYNC_ON_SMP "\n\tisync\n"
> -#define LWSYNC_ON_SMP __stringify(LWSYNC) "\n"
> +#define LWSYNC_ON_SMP stringify_in_c(LWSYNC) "\n"
> #else
> #define ISYNC_ON_SMP
> #define LWSYNC_ON_SMP
^ permalink raw reply
* Re: [PATCH][RESEND] powerpc: Add 82xx/83xx/86xx to 6xx Multiplatform
From: Arnd Bergmann @ 2008-07-01 6:17 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
In-Reply-To: <Pine.LNX.4.64.0807010030240.23830@blarg.am.freescale.net>
On Tuesday 01 July 2008, Kumar Gala wrote:
> There isn't any reason at this point that we can't build 82xx, 83xx & 86xx
> support in with the other 6xx based boards. =A0Twiddle the Kconfigs to al=
low
> this.
>=20
> This allows us to remove the machine type selection for related to 6xx.
>=20
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Thanks for doing this now. I had sent a similar patch last year when there
were still bugs in the source preventing it from working, but now it all
looks good.
^ permalink raw reply
* RE: [PATCH] [POWERPC] Xilinx: add compatibility for 'simple-bus'.
From: Benjamin Herrenschmidt @ 2008-07-01 6:16 UTC (permalink / raw)
To: Stephen Neuendorffer; +Cc: linuxppc-dev, git, dwg
In-Reply-To: <20080606161932.0650C1500054@mail96-sin.bigfish.com>
On Fri, 2008-06-06 at 09:16 -0700, Stephen Neuendorffer wrote:
> legacy_serial identifies a valid ns16550 on a simple-bus, but the
> legacy_serial driver doesn't understand the shift and offset flags
> necessary to get it to work, which results in no console.
>
> I think the easiest solution is to change the Kconfig so that
> PPC_UDBG_16550 is only selected based on !XILINX_VIRTEX. I've done this
> in my tree, but I've been swamped with other things at the moment, so I
> haven't verified it.
>
> Or is legacy_serial just legacy at this point and can go away entirely?
> I got the impression from some of the earlier discussion that it wasn't
> preferred, at least....
No, legacy serial is useful. Just grow it an understanding of the shift
& offset bits :-)
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v2] Parameterize EMAC Multicast Match Handling
From: Benjamin Herrenschmidt @ 2008-07-01 6:14 UTC (permalink / raw)
To: Grant Erickson; +Cc: linuxppc-dev, Stefan Roese
In-Reply-To: <C48F0E18.101F1%gerickson@nuovations.com>
> Stefan and/or Ben:
>
> Any thoughts on this?
I was hesitating a bit... do we really need to be -that- flexible ?
That is, either that or use some new compatible entry to detect the new
reg layout and whack that as a feature bit instead ? The advantage
of the later is that we have the possibility of doing conditional
compile for kernels that support only a given processor or set of
processors (not that we have implemented much of it, but it just
becomes Kconfig mumbo jumbo and a little bit of defines in the .h
by turning the feature test into a compile-time 0 or 1.
But this isn't a hot path and not a lot of code so maybe not worth
bothering... however, it does add 3 properties to the DT and I know
embedded people (especially Xilinx) are a bit concerned about the size
of the DT when they try to fit it in block RAM...
Cheers,
Ben.
^ permalink raw reply
* [PATCH] powerpc: fixup lwsync at runtime
From: Kumar Gala @ 2008-07-01 5:32 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
To allow for a single kernel image on e500 v1/v2/mc we need to fixup lwsync
at runtime. On e500v1/v2 lwsync causes an illop so we need to patch up
the code. We default to 'sync' since that is always safe and if the cpu
is capable we will replace 'sync' with 'lwsync'.
We introduce CPU_FTR_LWSYNC as a way to determine at runtime if this is
needed. This flag could be moved elsewhere since we dont really use it
for the normal CPU_FTR purpose.
Finally we only store the relative offset in the fixup section to keep it
as small as possible rather than using a full fixup_entry.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
Rebased against latest powerpc-next tree.
- k
arch/powerpc/kernel/module.c | 6 ++++++
arch/powerpc/kernel/setup_32.c | 4 ++++
arch/powerpc/kernel/setup_64.c | 2 ++
arch/powerpc/kernel/vdso.c | 10 ++++++++++
arch/powerpc/kernel/vdso32/vdso32.lds.S | 3 +++
arch/powerpc/kernel/vdso64/vdso64.lds.S | 3 +++
arch/powerpc/kernel/vmlinux.lds.S | 6 ++++++
arch/powerpc/lib/feature-fixups.c | 16 ++++++++++++++++
include/asm-powerpc/code-patching.h | 3 ++-
include/asm-powerpc/cputable.h | 21 +++++++++++----------
include/asm-powerpc/synch.h | 27 ++++++++++++++++++++++-----
11 files changed, 85 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 40dd52d..af07003 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -86,6 +86,12 @@ int module_finalize(const Elf_Ehdr *hdr,
(void *)sect->sh_addr + sect->sh_size);
#endif
+ sect = find_section(hdr, sechdrs, "__lwsync_fixup");
+ if (sect != NULL)
+ do_lwsync_fixups(cur_cpu_spec->cpu_features,
+ (void *)sect->sh_addr,
+ (void *)sect->sh_addr + sect->sh_size);
+
return 0;
}
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 9e83add..0109e7f 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -101,6 +101,10 @@ unsigned long __init early_init(unsigned long dt_ptr)
PTRRELOC(&__start___ftr_fixup),
PTRRELOC(&__stop___ftr_fixup));
+ do_lwsync_fixups(spec->cpu_features,
+ PTRRELOC(&__start___lwsync_fixup),
+ PTRRELOC(&__stop___lwsync_fixup));
+
return KERNELBASE + offset;
}
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 098fd96..04d8de9 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -363,6 +363,8 @@ void __init setup_system(void)
&__start___ftr_fixup, &__stop___ftr_fixup);
do_feature_fixups(powerpc_firmware_features,
&__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
+ do_lwsync_fixups(cur_cpu_spec->cpu_features,
+ &__start___lwsync_fixup, &__stop___lwsync_fixup);
/*
* Unflatten the device-tree passed by prom_init or kexec
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index ce245a8..f177c60 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -571,6 +571,11 @@ static __init int vdso_fixup_features(struct lib32_elfinfo *v32,
if (start64)
do_feature_fixups(powerpc_firmware_features,
start64, start64 + size64);
+
+ start64 = find_section64(v64->hdr, "__lwsync_fixup", &size64);
+ if (start64)
+ do_lwsync_fixups(cur_cpu_spec->cpu_features,
+ start64, start64 + size64);
#endif /* CONFIG_PPC64 */
start32 = find_section32(v32->hdr, "__ftr_fixup", &size32);
@@ -585,6 +590,11 @@ static __init int vdso_fixup_features(struct lib32_elfinfo *v32,
start32, start32 + size32);
#endif /* CONFIG_PPC64 */
+ start32 = find_section32(v32->hdr, "__lwsync_fixup", &size32);
+ if (start32)
+ do_lwsync_fixups(cur_cpu_spec->cpu_features,
+ start32, start32 + size32);
+
return 0;
}
diff --git a/arch/powerpc/kernel/vdso32/vdso32.lds.S b/arch/powerpc/kernel/vdso32/vdso32.lds.S
index 2717935..be3b6a4 100644
--- a/arch/powerpc/kernel/vdso32/vdso32.lds.S
+++ b/arch/powerpc/kernel/vdso32/vdso32.lds.S
@@ -33,6 +33,9 @@ SECTIONS
. = ALIGN(8);
__ftr_fixup : { *(__ftr_fixup) }
+ . = ALIGN(8);
+ __lwsync_fixup : { *(__lwsync_fixup) }
+
#ifdef CONFIG_PPC64
. = ALIGN(8);
__fw_ftr_fixup : { *(__fw_ftr_fixup) }
diff --git a/arch/powerpc/kernel/vdso64/vdso64.lds.S b/arch/powerpc/kernel/vdso64/vdso64.lds.S
index e608d1b..d0b2526 100644
--- a/arch/powerpc/kernel/vdso64/vdso64.lds.S
+++ b/arch/powerpc/kernel/vdso64/vdso64.lds.S
@@ -35,6 +35,9 @@ SECTIONS
__ftr_fixup : { *(__ftr_fixup) }
. = ALIGN(8);
+ __lwsync_fixup : { *(__lwsync_fixup) }
+
+ . = ALIGN(8);
__fw_ftr_fixup : { *(__fw_ftr_fixup) }
/*
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 3c07811..6856f6c 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -127,6 +127,12 @@ SECTIONS
*(__ftr_fixup)
__stop___ftr_fixup = .;
}
+ . = ALIGN(8);
+ __lwsync_fixup : AT(ADDR(__lwsync_fixup) - LOAD_OFFSET) {
+ __start___lwsync_fixup = .;
+ *(__lwsync_fixup)
+ __stop___lwsync_fixup = .;
+ }
#ifdef CONFIG_PPC64
. = ALIGN(8);
__fw_ftr_fixup : AT(ADDR(__fw_ftr_fixup) - LOAD_OFFSET) {
diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c
index 48e1ed8..ac5f5a1 100644
--- a/arch/powerpc/lib/feature-fixups.c
+++ b/arch/powerpc/lib/feature-fixups.c
@@ -110,6 +110,22 @@ void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
}
}
+void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
+{
+ unsigned int *start, *end, *dest;
+
+ if (!(value & CPU_FTR_LWSYNC))
+ return ;
+
+ start = fixup_start;
+ end = fixup_end;
+
+ for (; start < end; start++) {
+ dest = (void *)start + *start;
+ patch_instruction(dest, PPC_LWSYNC_INSTR);
+ }
+}
+
#ifdef CONFIG_FTR_FIXUP_SELFTEST
#define check(x) \
diff --git a/include/asm-powerpc/code-patching.h b/include/asm-powerpc/code-patching.h
index ef3a5d1..107d9b9 100644
--- a/include/asm-powerpc/code-patching.h
+++ b/include/asm-powerpc/code-patching.h
@@ -12,7 +12,8 @@
#include <asm/types.h>
-#define PPC_NOP_INSTR 0x60000000
+#define PPC_NOP_INSTR 0x60000000
+#define PPC_LWSYNC_INSTR 0x7c2004ac
/* Flags for create_branch:
* "b" == create_branch(addr, target, 0);
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 4e4491c..3171ac9 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -156,6 +156,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
+#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
/*
* Add the 64-bit processor unique features in the top half of the word;
@@ -369,43 +370,43 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
- CPU_FTR_L2CSR)
+ CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
/* 64-bit CPUs */
-#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
CPU_FTR_MMCRA | CPU_FTR_CTRL)
-#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA)
-#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
-#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR)
-#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
CPU_FTR_DSCR)
-#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | \
+#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
CPU_FTR_DSCR)
-#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
+#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
-#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
+#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
index 42a1ef5..4737c61 100644
--- a/include/asm-powerpc/synch.h
+++ b/include/asm-powerpc/synch.h
@@ -3,20 +3,37 @@
#ifdef __KERNEL__
#include <linux/stringify.h>
+#include <asm/feature-fixups.h>
-#if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC)
-#define __SUBARCH_HAS_LWSYNC
-#endif
+#ifndef __ASSEMBLY__
+extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
+extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
+ void *fixup_end);
+#endif /* __ASSEMBLY__ */
+
+#define START_LWSYNC_SECTION(label) label##1:
+#define MAKE_LWSYNC_SECTION_ENTRY(label, sect) \
+label##4: \
+ .pushsection sect,"a"; \
+ .align 2; \
+label##5: \
+ .long label##1b-label##5b; \
+ .popsection;
-#ifdef __SUBARCH_HAS_LWSYNC
+#if defined(__powerpc64__)
# define LWSYNC lwsync
+#elif defined(CONFIG_E500)
+# define LWSYNC \
+ START_LWSYNC_SECTION(97); \
+ sync; \
+ MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
#else
# define LWSYNC sync
#endif
#ifdef CONFIG_SMP
#define ISYNC_ON_SMP "\n\tisync\n"
-#define LWSYNC_ON_SMP __stringify(LWSYNC) "\n"
+#define LWSYNC_ON_SMP stringify_in_c(LWSYNC) "\n"
#else
#define ISYNC_ON_SMP
#define LWSYNC_ON_SMP
--
1.5.5.1
^ permalink raw reply related
* [PATCH][RESEND] powerpc: Add 82xx/83xx/86xx to 6xx Multiplatform
From: Kumar Gala @ 2008-07-01 5:31 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
There isn't any reason at this point that we can't build 82xx, 83xx & 86xx
support in with the other 6xx based boards. Twiddle the Kconfigs to allow
this.
This allows us to remove the machine type selection for related to 6xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
Rebased against latest powerpc-next tree.
- k
arch/powerpc/platforms/82xx/Kconfig | 11 ++++++-----
arch/powerpc/platforms/83xx/Kconfig | 10 ++++++----
arch/powerpc/platforms/86xx/Kconfig | 16 +++++++++++-----
arch/powerpc/platforms/Kconfig | 33 +++------------------------------
4 files changed, 26 insertions(+), 44 deletions(-)
diff --git a/arch/powerpc/platforms/82xx/Kconfig b/arch/powerpc/platforms/82xx/Kconfig
index 917ac88..1c8034b 100644
--- a/arch/powerpc/platforms/82xx/Kconfig
+++ b/arch/powerpc/platforms/82xx/Kconfig
@@ -1,7 +1,8 @@
-choice
- prompt "82xx Board Type"
- depends on PPC_82xx
- default MPC8272_ADS
+menuconfig PPC_82xx
+ bool "82xx-based boards (PQ II)"
+ depends on 6xx && PPC_MULTIPLATFORM
+
+if PPC_82xx
config MPC8272_ADS
bool "Freescale MPC8272 ADS"
@@ -36,7 +37,7 @@ config EP8248E
This board is also resold by Freescale as the QUICCStart
MPC8248 Evaluation System and/or the CWH-PPC-8248N-VE.
-endchoice
+endif
config PQ2ADS
bool
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index fe75b2a..27d9bf8 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -1,10 +1,12 @@
-menuconfig MPC83xx
- bool "83xx Board Type"
- depends on PPC_83xx
+menuconfig PPC_83xx
+ bool "83xx-based boards"
+ depends on 6xx && PPC_MULTIPLATFORM
select PPC_UDBG_16550
select PPC_INDIRECT_PCI
+ select FSL_SOC
+ select IPIC
-if MPC83xx
+if PPC_83xx
config MPC831x_RDB
bool "Freescale MPC831x RDB"
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 053f49a..80a81e0 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -1,7 +1,13 @@
-choice
- prompt "86xx Board Type"
- depends on PPC_86xx
- default MPC8641_HPCN
+config PPC_86xx
+menuconfig PPC_86xx
+ bool "86xx-based boards"
+ depends on 6xx && PPC_MULTIPLATFORM
+ select FSL_SOC
+ select ALTIVEC
+ help
+ The Freescale E600 SoCs have 74xx cores.
+
+if PPC_86xx
config MPC8641_HPCN
bool "Freescale MPC8641 HPCN"
@@ -24,7 +30,7 @@ config MPC8610_HPCD
help
This option enables support for the MPC8610 HPCD board.
-endchoice
+endif
config MPC8641
bool
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 87454c5..690c1f4 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -1,36 +1,9 @@
menu "Platform support"
-choice
- prompt "Machine type"
- depends on PPC64 || 6xx
- default PPC_MULTIPLATFORM
-
config PPC_MULTIPLATFORM
- bool "Generic desktop/server/laptop"
- help
- Select this option if configuring for an IBM pSeries or
- RS/6000 machine, an Apple machine, or a PReP, CHRP,
- Maple or Cell-based machine.
-
-config PPC_82xx
- bool "Freescale 82xx"
- depends on 6xx
-
-config PPC_83xx
- bool "Freescale 83xx"
- depends on 6xx
- select FSL_SOC
- select MPC83xx
- select IPIC
-
-config PPC_86xx
- bool "Freescale 86xx"
- depends on 6xx
- select FSL_SOC
- select ALTIVEC
- help
- The Freescale E600 SoCs have 74xx cores.
-endchoice
+ bool
+ depends on PPC64 || 6xx
+ default y
config CLASSIC32
def_bool y
--
1.5.5.1
^ permalink raw reply related
* Re: [PATCH] Fix cpm uart corruption with PREEMPT_RT
From: Kumar Gala @ 2008-07-01 5:28 UTC (permalink / raw)
To: Rune Torgersen; +Cc: linuxppc-dev
In-Reply-To: <20080520193917.C7ED15AF22@innovsys.com>
On May 20, 2008, at 2:39 PM, Rune Torgersen wrote:
> Fix CPM serial port corruption when running with CONFIG_PREEMPT_RT.
> Userland usage of console, and kernel printf's were stepping on each
> others toes.
> Also only take lock if not in an oops.
>
> Signed-off-by: Rune Torgersen <runet@innovsys.com>
applied.
- k
^ permalink raw reply
* Re: [PATCH] Fix pq2fads irq handling with PREEMPT_RT
From: Kumar Gala @ 2008-07-01 5:28 UTC (permalink / raw)
To: Rune Torgersen; +Cc: linuxppc-dev
In-Reply-To: <20080520192857.3C3E95AF22@innovsys.com>
On May 20, 2008, at 2:28 PM, Rune Torgersen wrote:
> Fix interrupt threading issue on pq2fads when running with
> CONFIG_PREEMPT_RT
>
> Signed-off-by: Rune Torgersen <runet@innovsys.com>
applied.
- k
^ permalink raw reply
* Re: [PATCH v2] Parameterize EMAC Multicast Match Handling
From: Grant Erickson @ 2008-07-01 5:26 UTC (permalink / raw)
To: Stefan Roese, Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1214352498-12527-1-git-send-email-gerickson@nuovations.com>
On 6/24/08 5:08 PM, Grant Erickson wrote:
> Various instances of the EMAC core have varying: 1) number of address
> match slots, 2) width of the registers for handling address match slots,
> 3) number of registers for handling address match slots and 4) base
> offset for those registers.
>
> As the driver stands today, it assumes that all EMACs have 4 IAHT and
> GAHT 32-bit registers, starting at offset 0x30 from the register base,
> with only 16-bits of each used for a total of 64 match slots.
>
> The 405EX(r) and 460 now use the EMAC4SYNC core rather than the EMAC4
> core. This core has 8 IAHT and GAHT registers, starting at offset 0x80
> from the register base, with ALL 32-bits of each used for a total of
> 256 match slots.
>
> This adds macros and inlines for handling these differences based on
> three parameters parsed from the device tree:
>
> xaht-slots-shift
> xaht-width-shift
> xaht-base-offset
>
> and reworks the code, where appropriate to use those macros and inlines.
> EMAC/EMAC4 values are defaulted for these keys if missing, resulting in
> a driver that works as today's does for all cores.
>
> In addition the register size passed to ioremap is now taken from the
> device tree:
>
> c0 for EMAC4SYNC cores
> 74 for EMAC4 cores
> 70 for EMAC cores
>
> rathaer than sizeof (emac_regs).
>
> Finally, the device trees have been updated with the appropriate xaht-*
> keys and values.
>
> This has been tested on an AMCC Haleakala board such that: 1) inbound
> ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11
> and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from
> 'haleakala.local' to those same systems in the '.local' domain via MDNS
> now work.
>
> Signed-off-by: Grant Erickson <gerickson@nuovations.com>
> ---
> arch/powerpc/boot/dts/bamboo.dts | 6 +++
> arch/powerpc/boot/dts/canyonlands.dts | 10 ++++-
> arch/powerpc/boot/dts/ebony.dts | 6 +++
> arch/powerpc/boot/dts/ep405.dts | 3 ++
> arch/powerpc/boot/dts/glacier.dts | 20 +++++++++--
> arch/powerpc/boot/dts/haleakala.dts | 5 ++-
> arch/powerpc/boot/dts/katmai.dts | 5 ++-
> arch/powerpc/boot/dts/kilauea.dts | 10 ++++-
> arch/powerpc/boot/dts/makalu.dts | 10 ++++-
> arch/powerpc/boot/dts/rainier.dts | 10 ++++-
> arch/powerpc/boot/dts/sequoia.dts | 10 ++++-
> arch/powerpc/boot/dts/taishan.dts | 20 +++++++++--
> arch/powerpc/boot/dts/walnut.dts | 3 ++
> arch/powerpc/boot/dts/warp.dts | 3 ++
> drivers/net/ibm_newemac/core.c | 55 +++++++++++++++++++----------
> drivers/net/ibm_newemac/core.h | 61
> +++++++++++++++++++++++++++++++++
> drivers/net/ibm_newemac/debug.c | 32 +++++++++++------
> drivers/net/ibm_newemac/emac.h | 15 +-------
> 18 files changed, 219 insertions(+), 65 deletions(-)
Stefan and/or Ben:
Any thoughts on this?
Regards,
Grant
^ permalink raw reply
* Re: [PATCH 1/2] powerpc: Fix compile error for CONFIG_VSX
From: Michael Neuling @ 2008-07-01 4:51 UTC (permalink / raw)
To: Paul Mackerras, linuxppc-dev
In-Reply-To: <20080701040139.A6196702C9@localhost.localdomain>
In message <20080701040139.A6196702C9@localhost.localdomain> you wrote:
> Fix compile error when CONFIG_VSX is enabled.
>
> arch/powerpc/kernel/signal_64.c: In function 'restore_sigcontext':
> arch/powerpc/kernel/signal_64.c:241: error: 'i' undeclared (first use in this
function)
FYI.. this was caused by a merge conflict with sfr's patch
fcbc5a976b1cafe2e866871c86d239d57503bfd5
Mikey
>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
> ---
>
> arch/powerpc/kernel/signal_64.c | 1 +
> 1 file changed, 1 insertion(+)
>
> Index: linux-2.6-ozlabs/arch/powerpc/kernel/signal_64.c
> ===================================================================
> --- linux-2.6-ozlabs.orig/arch/powerpc/kernel/signal_64.c
> +++ linux-2.6-ozlabs/arch/powerpc/kernel/signal_64.c
> @@ -167,6 +167,7 @@ static long restore_sigcontext(struct pt
> #endif
> #ifdef CONFIG_VSX
> double buf[FP_REGS_SIZE];
> + int i;
> #endif
> unsigned long err = 0;
> unsigned long save_r13 = 0;
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
^ permalink raw reply
* [PATCH] powerpc: rework 4xx PTE access and TLB miss
From: Benjamin Herrenschmidt @ 2008-07-01 4:35 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
This is some preliminary work to improve TLB management on SW loaded
TLB powerpc platforms. This introduce support for non-atomic PTE
operations in pgtable-ppc32.h and removes write back to the PTE from
the TLB miss handlers. In addition, the DSI interrupt code no longer
tries to fixup write permission, this is left to generic code, and
_PAGE_HWWRITE is gone.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
This is a first step, plan is to do the same for FSL BookE, 405 and
possibly 8xx too. From there, I want to rework a bit the execute
permission handling to avoid multiple faults, add support for
_PAGE_EXEC (no executable mappings), for prefaulting (especially
for kmap) and proper SMP support for future SMP capable BookE
platforms.
This version fixes a couple of typos, add a few comments and
change use of flush_instruction_cache() to flush_icache_range()
which will be more appropriate if there is ever an SMP variant.
arch/powerpc/kernel/head_44x.S | 279 ++++++++++++------------------------
arch/powerpc/kernel/head_booke.h | 8 +
arch/powerpc/mm/44x_mmu.c | 29 +++
include/asm-powerpc/pgtable-ppc32.h | 61 +++++--
4 files changed, 177 insertions(+), 200 deletions(-)
--- linux-work.orig/arch/powerpc/kernel/head_44x.S 2008-06-26 15:05:48.000000000 +1000
+++ linux-work/arch/powerpc/kernel/head_44x.S 2008-07-01 14:19:18.000000000 +1000
@@ -293,112 +293,7 @@ interrupt_base:
MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception)
/* Data Storage Interrupt */
- START_EXCEPTION(DataStorage)
- mtspr SPRN_SPRG0, r10 /* Save some working registers */
- mtspr SPRN_SPRG1, r11
- mtspr SPRN_SPRG4W, r12
- mtspr SPRN_SPRG5W, r13
- mfcr r11
- mtspr SPRN_SPRG7W, r11
-
- /*
- * Check if it was a store fault, if not then bail
- * because a user tried to access a kernel or
- * read-protected page. Otherwise, get the
- * offending address and handle it.
- */
- mfspr r10, SPRN_ESR
- andis. r10, r10, ESR_ST@h
- beq 2f
-
- mfspr r10, SPRN_DEAR /* Get faulting address */
-
- /* If we are faulting a kernel address, we have to use the
- * kernel page tables.
- */
- lis r11, PAGE_OFFSET@h
- cmplw r10, r11
- blt+ 3f
- lis r11, swapper_pg_dir@h
- ori r11, r11, swapper_pg_dir@l
-
- mfspr r12,SPRN_MMUCR
- rlwinm r12,r12,0,0,23 /* Clear TID */
-
- b 4f
-
- /* Get the PGD for the current thread */
-3:
- mfspr r11,SPRN_SPRG3
- lwz r11,PGDIR(r11)
-
- /* Load PID into MMUCR TID */
- mfspr r12,SPRN_MMUCR /* Get MMUCR */
- mfspr r13,SPRN_PID /* Get PID */
- rlwimi r12,r13,0,24,31 /* Set TID */
-
-4:
- mtspr SPRN_MMUCR,r12
-
- rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
- lwzx r11, r12, r11 /* Get pgd/pmd entry */
- rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
- beq 2f /* Bail if no table */
-
- rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
- lwz r11, 4(r12) /* Get pte entry */
-
- andi. r13, r11, _PAGE_RW /* Is it writeable? */
- beq 2f /* Bail if not */
-
- /* Update 'changed'.
- */
- ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
- stw r11, 4(r12) /* Update Linux page table */
-
- li r13, PPC44x_TLB_SR@l /* Set SR */
- rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */
- rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */
- rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */
- rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
- rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */
- and r12, r12, r11 /* HWEXEC/RW & USER */
- rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */
- rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */
-
- rlwimi r11,r13,0,26,31 /* Insert static perms */
-
- rlwinm r11,r11,0,20,15 /* Clear U0-U3 */
-
- /* find the TLB index that caused the fault. It has to be here. */
- tlbsx r10, 0, r10
-
- tlbwe r11, r10, PPC44x_TLB_ATTRIB /* Write ATTRIB */
-
- /* Done...restore registers and get out of here.
- */
- mfspr r11, SPRN_SPRG7R
- mtcr r11
- mfspr r13, SPRN_SPRG5R
- mfspr r12, SPRN_SPRG4R
-
- mfspr r11, SPRN_SPRG1
- mfspr r10, SPRN_SPRG0
- rfi /* Force context change */
-
-2:
- /*
- * The bailout. Restore registers to pre-exception conditions
- * and call the heavyweights to help us out.
- */
- mfspr r11, SPRN_SPRG7R
- mtcr r11
- mfspr r13, SPRN_SPRG5R
- mfspr r12, SPRN_SPRG4R
-
- mfspr r11, SPRN_SPRG1
- mfspr r10, SPRN_SPRG0
- b data_access
+ DATA_STORAGE_EXCEPTION
/* Instruction Storage Interrupt */
INSTRUCTION_STORAGE_EXCEPTION
@@ -418,7 +313,6 @@ interrupt_base:
#else
EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
#endif
-
/* System Call Interrupt */
START_EXCEPTION(SystemCall)
NORMAL_EXCEPTION_PROLOG
@@ -479,18 +373,57 @@ interrupt_base:
4:
mtspr SPRN_MMUCR,r12
+ /* Mask of required permission bits. Note that while we
+ * do copy ESR:ST to _PAGE_RW position as trying to write
+ * to an RO page is pretty common, we don't do it with
+ * _PAGE_DIRTY. We could do it, but it's a fairly rare
+ * event so I'd rather take the overhead when it happens
+ * rather than adding an instruction here. We should measure
+ * whether the whole thing is worth it in the first place
+ * as we could avoid loading SPRN_ESR completely in the first
+ * place...
+ *
+ * TODO: Is it worth doing that mfspr & rlwimi in the first
+ * place or can we save a couple of instructions here ?
+ */
+ mfspr r12,SPRN_ESR
+ li r13,_PAGE_PRESENT|_PAGE_ACCESSED
+ rlwimi r13,r12,10,30,30
+
+ /* Load the PTE */
rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
lwzx r11, r12, r11 /* Get pgd/pmd entry */
rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
beq 2f /* Bail if no table */
rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
- lwz r11, 4(r12) /* Get pte entry */
- andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
- beq 2f /* Bail if not present */
+ lwz r11, 0(r12) /* Get high word of pte entry */
+ lwz r12, 4(r12) /* Get low word of pte entry */
+
+ lis r10,tlb_44x_index@ha
+
+ andc. r13,r13,r12 /* Check permission */
+
+ /* Load the next available TLB index */
+ lwz r13,tlb_44x_index@l(r10)
- ori r11, r11, _PAGE_ACCESSED
- stw r11, 4(r12)
+ bne 2f /* Bail if permission mismach */
+
+ /* Increment, rollover, and store TLB index */
+ addi r13,r13,1
+
+ /* Compare with watermark (instruction gets patched) */
+ .globl tlb_44x_patch_hwater_D
+tlb_44x_patch_hwater_D:
+ cmpwi 0,r13,1 /* reserve entries */
+ ble 5f
+ li r13,0
+5:
+ /* Store the next available TLB index */
+ stw r13,tlb_44x_index@l(r10)
+
+ /* Re-load the faulting address */
+ mfspr r10,SPRN_DEAR
/* Jump to common tlb load */
b finish_tlb_load
@@ -505,7 +438,7 @@ interrupt_base:
mfspr r12, SPRN_SPRG4R
mfspr r11, SPRN_SPRG1
mfspr r10, SPRN_SPRG0
- b data_access
+ b DataStorage
/* Instruction TLB Error Interrupt */
/*
@@ -549,18 +482,42 @@ interrupt_base:
4:
mtspr SPRN_MMUCR,r12
+ /* Make up the required permissions */
+ li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
+
rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
lwzx r11, r12, r11 /* Get pgd/pmd entry */
rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
beq 2f /* Bail if no table */
rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
- lwz r11, 4(r12) /* Get pte entry */
- andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
- beq 2f /* Bail if not present */
+ lwz r11, 0(r12) /* Get high word of pte entry */
+ lwz r12, 4(r12) /* Get low word of pte entry */
- ori r11, r11, _PAGE_ACCESSED
- stw r11, 4(r12)
+ lis r10,tlb_44x_index@ha
+
+ andc. r13,r13,r12 /* Check permission */
+
+ /* Load the next available TLB index */
+ lwz r13,tlb_44x_index@l(r10)
+
+ bne 2f /* Bail if permission mismach */
+
+ /* Increment, rollover, and store TLB index */
+ addi r13,r13,1
+
+ /* Compare with watermark (instruction gets patched) */
+ .globl tlb_44x_patch_hwater_I
+tlb_44x_patch_hwater_I:
+ cmpwi 0,r13,1 /* reserve entries */
+ ble 5f
+ li r13,0
+5:
+ /* Store the next available TLB index */
+ stw r13,tlb_44x_index@l(r10)
+
+ /* Re-load the faulting address */
+ mfspr r10,SPRN_SRR0
/* Jump to common TLB load point */
b finish_tlb_load
@@ -582,86 +539,40 @@ interrupt_base:
/*
* Local functions
- */
- /*
- * Data TLB exceptions will bail out to this point
- * if they can't resolve the lightweight TLB fault.
- */
-data_access:
- NORMAL_EXCEPTION_PROLOG
- mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
- stw r5,_ESR(r11)
- mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
- EXC_XFER_EE_LITE(0x0300, handle_page_fault)
+ */
/*
* Both the instruction and data TLB miss get to this
* point to load the TLB.
* r10 - EA of fault
- * r11 - available to use
- * r12 - Pointer to the 64-bit PTE
- * r13 - available to use
+ * r11 - PTE high word value
+ * r12 - PTE low word value
+ * r13 - TLB index
* MMUCR - loaded with proper value when we get here
* Upon exit, we reload everything and RFI.
*/
finish_tlb_load:
- /*
- * We set execute, because we don't have the granularity to
- * properly set this at the page level (Linux problem).
- * If shared is set, we cause a zero PID->TID load.
- * Many of these bits are software only. Bits we don't set
- * here we (properly should) assume have the appropriate value.
- */
-
- /* Load the next available TLB index */
- lis r13, tlb_44x_index@ha
- lwz r13, tlb_44x_index@l(r13)
- /* Load the TLB high watermark */
- lis r11, tlb_44x_hwater@ha
- lwz r11, tlb_44x_hwater@l(r11)
-
- /* Increment, rollover, and store TLB index */
- addi r13, r13, 1
- cmpw 0, r13, r11 /* reserve entries */
- ble 7f
- li r13, 0
-7:
- /* Store the next available TLB index */
- lis r11, tlb_44x_index@ha
- stw r13, tlb_44x_index@l(r11)
-
- lwz r11, 0(r12) /* Get MS word of PTE */
- lwz r12, 4(r12) /* Get LS word of PTE */
- rlwimi r11, r12, 0, 0 , 19 /* Insert RPN */
- tlbwe r11, r13, PPC44x_TLB_XLAT /* Write XLAT */
+ /* Combine RPN & ERPN an write WS 0 */
+ rlwimi r11,r12,0,0,19
+ tlbwe r11,r13,PPC44x_TLB_XLAT
/*
- * Create PAGEID. This is the faulting address,
+ * Create WS1. This is the faulting address (EPN),
* page size, and valid flag.
*/
- li r11, PPC44x_TLB_VALID | PPC44x_TLB_4K
- rlwimi r10, r11, 0, 20, 31 /* Insert valid and page size */
- tlbwe r10, r13, PPC44x_TLB_PAGEID /* Write PAGEID */
-
- li r10, PPC44x_TLB_SR@l /* Set SR */
- rlwimi r10, r12, 0, 30, 30 /* Set SW = _PAGE_RW */
- rlwimi r10, r12, 29, 29, 29 /* SX = _PAGE_HWEXEC */
- rlwimi r10, r12, 29, 28, 28 /* UR = _PAGE_USER */
- rlwimi r11, r12, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
- and r11, r12, r11 /* HWEXEC & USER */
- rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */
-
- rlwimi r12, r10, 0, 26, 31 /* Insert static perms */
-
- /*
- * Clear U0-U3 and WL1 IL1I IL1D IL2I IL2D bits which are added
- * on newer 440 cores like the 440x6 used on AMCC 460EX/460GT (see
- * include/asm-powerpc/pgtable-ppc32.h for details).
- */
- rlwinm r12, r12, 0, 20, 10
-
- tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */
+ li r11,PPC44x_TLB_VALID | PPC44x_TLB_4K
+ rlwimi r10,r11,0,20,31 /* Insert valid and page size*/
+ tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */
+
+ /* And WS 2 */
+ li r10,0xf85 /* Mask to apply from PTE */
+ rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
+ and r11,r12,r10 /* Mask PTE bits to keep */
+ andi. r10,r12,_PAGE_USER /* User page ? */
+ beq 1f /* nope, leave U bits empty */
+ rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */
+1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */
/* Done...restore registers and get out of here.
*/
Index: linux-work/arch/powerpc/mm/44x_mmu.c
===================================================================
--- linux-work.orig/arch/powerpc/mm/44x_mmu.c 2008-05-07 09:53:16.000000000 +1000
+++ linux-work/arch/powerpc/mm/44x_mmu.c 2008-07-01 14:32:32.000000000 +1000
@@ -27,6 +27,7 @@
#include <asm/mmu.h>
#include <asm/system.h>
#include <asm/page.h>
+#include <asm/cacheflush.h>
#include "mmu_decl.h"
@@ -37,11 +38,35 @@ unsigned int tlb_44x_index; /* = 0 */
unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
int icache_44x_need_flush;
+static void __init ppc44x_update_tlb_hwater(void)
+{
+ extern unsigned int tlb_44x_patch_hwater_D[];
+ extern unsigned int tlb_44x_patch_hwater_I[];
+
+ /* The TLB miss handlers hard codes the watermark in a cmpli
+ * instruction to improve performances rather than loading it
+ * from the global variable. Thus, we patch the instructions
+ * in the 2 TLB miss handlers when updating the value
+ */
+ tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |
+ tlb_44x_hwater;
+ flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],
+ (unsigned long)&tlb_44x_patch_hwater_D[1]);
+ tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |
+ tlb_44x_hwater;
+ flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],
+ (unsigned long)&tlb_44x_patch_hwater_I[1]);
+}
+
/*
* "Pins" a 256MB TLB entry in AS0 for kernel lowmem
*/
static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
{
+ unsigned int entry = tlb_44x_hwater--;
+
+ ppc44x_update_tlb_hwater();
+
__asm__ __volatile__(
"tlbwe %2,%3,%4\n"
"tlbwe %1,%3,%5\n"
@@ -50,7 +75,7 @@ static void __init ppc44x_pin_tlb(unsign
: "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
"r" (phys),
"r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
- "r" (tlb_44x_hwater--), /* slot for this TLB entry */
+ "r" (entry),
"i" (PPC44x_TLB_PAGEID),
"i" (PPC44x_TLB_XLAT),
"i" (PPC44x_TLB_ATTRIB));
@@ -58,6 +83,8 @@ static void __init ppc44x_pin_tlb(unsign
void __init MMU_init_hw(void)
{
+ ppc44x_update_tlb_hwater();
+
flush_instruction_cache();
}
Index: linux-work/include/asm-powerpc/pgtable-ppc32.h
===================================================================
--- linux-work.orig/include/asm-powerpc/pgtable-ppc32.h 2008-05-28 09:31:19.000000000 +1000
+++ linux-work/include/asm-powerpc/pgtable-ppc32.h 2008-07-01 14:19:18.000000000 +1000
@@ -182,6 +182,9 @@ extern int icache_44x_need_flush;
#define _PMD_SIZE_16M 0x0e0
#define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4))
+/* Until my rework is finished, 40x still needs atomic PTE updates */
+#define PTE_ATOMIC_UPDATES 1
+
#elif defined(CONFIG_44x)
/*
* Definitions for PPC440
@@ -253,17 +256,17 @@ extern int icache_44x_need_flush;
*/
#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
-#define _PAGE_RW 0x00000002 /* S: Write permission */
+#define _PAGE_RW 0x00000002 /* S: Write permission */
#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
+#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
-#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */
-#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */
-#define _PAGE_USER 0x00000040 /* S: User page */
-#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
-#define _PAGE_GUARDED 0x00000100 /* H: G bit */
-#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */
-#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
-#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
+#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
+#define _PAGE_USER 0x00000040 /* S: User page */
+#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
+#define _PAGE_GUARDED 0x00000100 /* H: G bit */
+#define _PAGE_COHERENT 0x00000200 /* H: M bit */
+#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
+#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
/* TODO: Add large page lowmem mapping support */
#define _PMD_PRESENT 0
@@ -273,6 +276,7 @@ extern int icache_44x_need_flush;
/* ERPN in a PTE never gets cleared, ignore it */
#define _PTE_NONE_MASK 0xffffffff00000000ULL
+
#elif defined(CONFIG_FSL_BOOKE)
/*
MMU Assist Register 3:
@@ -315,6 +319,9 @@ extern int icache_44x_need_flush;
#define _PMD_PRESENT_MASK (PAGE_MASK)
#define _PMD_BAD (~PAGE_MASK)
+/* Until my rework is finished, FSL BookE still needs atomic PTE updates */
+#define PTE_ATOMIC_UPDATES 1
+
#elif defined(CONFIG_8xx)
/* Definitions for 8xx embedded chips. */
#define _PAGE_PRESENT 0x0001 /* Page is valid */
@@ -345,6 +352,9 @@ extern int icache_44x_need_flush;
#define _PTE_NONE_MASK _PAGE_ACCESSED
+/* Until my rework is finished, 8xx still needs atomic PTE updates */
+#define PTE_ATOMIC_UPDATES 1
+
#else /* CONFIG_6xx */
/* Definitions for 60x, 740/750, etc. */
#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
@@ -365,6 +375,10 @@ extern int icache_44x_need_flush;
#define _PMD_PRESENT 0
#define _PMD_PRESENT_MASK (PAGE_MASK)
#define _PMD_BAD (~PAGE_MASK)
+
+/* Hash table based platforms need atomic updates of the linux PTE */
+#define PTE_ATOMIC_UPDATES 1
+
#endif
/*
@@ -557,9 +571,11 @@ extern void add_hash_page(unsigned conte
* low PTE word since we expect ALL flag bits to be there
*/
#ifndef CONFIG_PTE_64BIT
-static inline unsigned long pte_update(pte_t *p, unsigned long clr,
+static inline unsigned long pte_update(pte_t *p,
+ unsigned long clr,
unsigned long set)
{
+#ifdef PTE_ATOMIC_UPDATES
unsigned long old, tmp;
__asm__ __volatile__("\
@@ -572,16 +588,26 @@ static inline unsigned long pte_update(p
: "=&r" (old), "=&r" (tmp), "=m" (*p)
: "r" (p), "r" (clr), "r" (set), "m" (*p)
: "cc" );
+#else /* PTE_ATOMIC_UPDATES */
+ unsigned long old = pte_val(*p);
+ *p = __pte((old & ~clr) | set);
+#endif /* !PTE_ATOMIC_UPDATES */
+
#ifdef CONFIG_44x
if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
icache_44x_need_flush = 1;
#endif
return old;
}
-#else
-static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
- unsigned long set)
+#else /* CONFIG_PTE_64BIT */
+/* TODO: Change that to only modify the low word and move set_pte_at()
+ * out of line
+ */
+static inline unsigned long long pte_update(pte_t *p,
+ unsigned long clr,
+ unsigned long set)
{
+#ifdef PTE_ATOMIC_UPDATES
unsigned long long old;
unsigned long tmp;
@@ -596,13 +622,18 @@ static inline unsigned long long pte_upd
: "=&r" (old), "=&r" (tmp), "=m" (*p)
: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
: "cc" );
+#else /* PTE_ATOMIC_UPDATES */
+ unsigned long long old = pte_val(*p);
+ *p = __pte((old & ~clr) | set);
+#endif /* !PTE_ATOMIC_UPDATES */
+
#ifdef CONFIG_44x
if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
icache_44x_need_flush = 1;
#endif
return old;
}
-#endif
+#endif /* CONFIG_PTE_64BIT */
/*
* set_pte stores a linux PTE into the linux page table.
@@ -665,7 +696,7 @@ static inline void __ptep_set_access_fla
({ \
int __changed = !pte_same(*(__ptep), __entry); \
if (__changed) { \
- __ptep_set_access_flags(__ptep, __entry, __dirty); \
+ __ptep_set_access_flags(__ptep, __entry, __dirty); \
flush_tlb_page_nohash(__vma, __address); \
} \
__changed; \
Index: linux-work/arch/powerpc/kernel/head_booke.h
===================================================================
--- linux-work.orig/arch/powerpc/kernel/head_booke.h 2008-06-26 15:05:48.000000000 +1000
+++ linux-work/arch/powerpc/kernel/head_booke.h 2008-07-01 14:19:18.000000000 +1000
@@ -327,6 +327,14 @@ label:
addi r3,r1,STACK_FRAME_OVERHEAD; \
EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
+#define DATA_STORAGE_EXCEPTION \
+ START_EXCEPTION(DataStorage) \
+ NORMAL_EXCEPTION_PROLOG; \
+ mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
+ stw r5,_ESR(r11); \
+ mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
+ EXC_XFER_EE_LITE(0x0300, handle_page_fault)
+
#define INSTRUCTION_STORAGE_EXCEPTION \
START_EXCEPTION(InstructionStorage) \
NORMAL_EXCEPTION_PROLOG; \
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