* Re: Freescale SEC driver with cryptoloop on MPC8567e
From: Kim Phillips @ 2008-07-08 20:28 UTC (permalink / raw)
To: mike zheng; +Cc: linuxppc-dev, linux-crypto
In-Reply-To: <5c9cd53b0807081103y583d0013ic0d22fb46490be2b@mail.gmail.com>
On Tue, 8 Jul 2008 14:03:28 -0400
"mike zheng" <mail4mz@gmail.com> wrote:
> Hello,
>
> Any one know how can I integrate the Freescale's SEC driver with
> cryptoloop in Kernel2.4 on MPC8567e? Or which version of kernel shall
> I take if it is already there?
Take Herbert's cryptodev-2.6 tree and add support in the talitos driver
for the ablkcipher algorithm you're using.
Kim
^ permalink raw reply
* Re: [PATCH 15/16 v3] [v2] ibmvscsi: driver enablement for CMO
From: Robert Jennings @ 2008-07-08 20:35 UTC (permalink / raw)
To: paulus, benh, linuxppc-dev, linux-scsi, Brian King,
Nathan Fontenot, David Darrington
In-Reply-To: <20080704125631.GR1310@linux.vnet.ibm.com>
=46rom: Robert Jennings <rcj@linux.vnet.ibm.com>
I removed references to 'entitlement' after having changed the function
'get_io_entitlement' to 'get_desired_dma' to correctly indicate what the
function was doing. Also, this function does not need to page align the
return value, the VIO bus is responsible for this.
(We would like to take this patch through linuxppc-dev with the full
change set for this feature. We are copying linux-scsi for review and ack)
Enable the driver to function in a Cooperative Memory Overcommitment (CMO)
environment.
The following changes are made to enable the driver for CMO:
* DMA mapping errors will not result in error messages if entitlement has
been exceeded and resources were not available.
* The driver has a get_desired_dma function defined to function
in a CMO environment. It will indicate how much IO memory it would like
to function.
Signed-off-by: Robert Jennings <rcj@linux.vnet.ibm.com>
---
drivers/scsi/ibmvscsi/ibmvscsi.c | 45 +++++++++++++++++++++++++++++++++-=
-----
drivers/scsi/ibmvscsi/ibmvscsi.h | 2 ++
2 files changed, 40 insertions(+), 7 deletions(-)
Index: b/drivers/scsi/ibmvscsi/ibmvscsi.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- a/drivers/scsi/ibmvscsi/ibmvscsi.c
+++ b/drivers/scsi/ibmvscsi/ibmvscsi.c
@@ -72,6 +72,7 @@
#include <linux/delay.h>
#include <asm/firmware.h>
#include <asm/vio.h>
+#include <asm/firmware.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_host.h>
@@ -426,8 +427,10 @@ static int map_sg_data(struct scsi_cmnd=20
SG_ALL * sizeof(struct srp_direct_buf),
&evt_struct->ext_list_token, 0);
if (!evt_struct->ext_list) {
- sdev_printk(KERN_ERR, cmd->device,
- "Can't allocate memory for indirect table\n");
+ if (!firmware_has_feature(FW_FEATURE_CMO))
+ sdev_printk(KERN_ERR, cmd->device,
+ "Can't allocate memory "
+ "for indirect table\n");
return 0;
}
}
@@ -743,7 +746,9 @@ static int ibmvscsi_queuecommand(struct=20
srp_cmd->lun =3D ((u64) lun) << 48;
=20
if (!map_data_for_srp_cmd(cmnd, evt_struct, srp_cmd, hostdata->dev)) {
- sdev_printk(KERN_ERR, cmnd->device, "couldn't convert cmd to srp_cmd\n");
+ if (!firmware_has_feature(FW_FEATURE_CMO))
+ sdev_printk(KERN_ERR, cmnd->device,
+ "couldn't convert cmd to srp_cmd\n");
free_event_struct(&hostdata->pool, evt_struct);
return SCSI_MLQUEUE_HOST_BUSY;
}
@@ -855,7 +860,10 @@ static void send_mad_adapter_info(struct
DMA_BIDIRECTIONAL);
=20
if (dma_mapping_error(req->buffer)) {
- dev_err(hostdata->dev, "Unable to map request_buffer for adapter_info!\n=
");
+ if (!firmware_has_feature(FW_FEATURE_CMO))
+ dev_err(hostdata->dev,
+ "Unable to map request_buffer for "
+ "adapter_info!\n");
free_event_struct(&hostdata->pool, evt_struct);
return;
}
@@ -1400,7 +1408,9 @@ static int ibmvscsi_do_host_config(struc
DMA_BIDIRECTIONAL);
=20
if (dma_mapping_error(host_config->buffer)) {
- dev_err(hostdata->dev, "dma_mapping error getting host config\n");
+ if (!firmware_has_feature(FW_FEATURE_CMO))
+ dev_err(hostdata->dev,
+ "dma_mapping error getting host config\n");
free_event_struct(&hostdata->pool, evt_struct);
return -1;
}
@@ -1604,7 +1614,7 @@ static struct scsi_host_template driver_
.eh_host_reset_handler =3D ibmvscsi_eh_host_reset_handler,
.slave_configure =3D ibmvscsi_slave_configure,
.change_queue_depth =3D ibmvscsi_change_queue_depth,
- .cmd_per_lun =3D 16,
+ .cmd_per_lun =3D IBMVSCSI_CMDS_PER_LUN_DEFAULT,
.can_queue =3D IBMVSCSI_MAX_REQUESTS_DEFAULT,
.this_id =3D -1,
.sg_tablesize =3D SG_ALL,
@@ -1613,6 +1623,26 @@ static struct scsi_host_template driver_
};
=20
/**
+ * ibmvscsi_get_desired_dma - Calculate IO memory desired by the driver
+ *
+ * @vdev: struct vio_dev for the device whose desired IO mem is to be retu=
rned
+ *
+ * Return value:
+ * Number of bytes of IO data the driver will need to perform well.
+ */
+static unsigned long ibmvscsi_get_desired_dma(struct vio_dev *vdev)
+{
+ /* iu_storage data allocated in initialize_event_pool */
+ unsigned long desired_io =3D max_requests * sizeof(union viosrp_iu);
+
+ /* add io space for sg data */
+ desired_io +=3D (IBMVSCSI_MAX_SECTORS_DEFAULT *
+ IBMVSCSI_CMDS_PER_LUN_DEFAULT);
+
+ return desired_io;
+}
+
+/**
* Called by bus code for each adapter
*/
static int ibmvscsi_probe(struct vio_dev *vdev, const struct vio_device_id=
*id)
@@ -1641,7 +1671,7 @@ static int ibmvscsi_probe(struct vio_dev
hostdata->host =3D host;
hostdata->dev =3D dev;
atomic_set(&hostdata->request_limit, -1);
- hostdata->host->max_sectors =3D 32 * 8; /* default max I/O 32 pages */
+ hostdata->host->max_sectors =3D IBMVSCSI_MAX_SECTORS_DEFAULT;
=20
rc =3D ibmvscsi_ops->init_crq_queue(&hostdata->queue, hostdata, max_reque=
sts);
if (rc !=3D 0 && rc !=3D H_RESOURCE) {
@@ -1735,6 +1765,7 @@ static struct vio_driver ibmvscsi_driver
.id_table =3D ibmvscsi_device_table,
.probe =3D ibmvscsi_probe,
.remove =3D ibmvscsi_remove,
+ .get_desired_dma =3D ibmvscsi_get_desired_dma,
.driver =3D {
.name =3D "ibmvscsi",
.owner =3D THIS_MODULE,
Index: b/drivers/scsi/ibmvscsi/ibmvscsi.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- a/drivers/scsi/ibmvscsi/ibmvscsi.h
+++ b/drivers/scsi/ibmvscsi/ibmvscsi.h
@@ -45,6 +45,8 @@ struct Scsi_Host;
#define MAX_INDIRECT_BUFS 10
=20
#define IBMVSCSI_MAX_REQUESTS_DEFAULT 100
+#define IBMVSCSI_CMDS_PER_LUN_DEFAULT 16
+#define IBMVSCSI_MAX_SECTORS_DEFAULT 256 /* 32 * 8 =3D default max I/O 32 =
pages */
#define IBMVSCSI_MAX_CMDS_PER_LUN 64
=20
/* ------------------------------------------------------------
^ permalink raw reply
* Re: [PATCH 14/16 v3] [v2] ibmveth: enable driver for CMO
From: Robert Jennings @ 2008-07-08 20:38 UTC (permalink / raw)
To: paulus, benh, linuxppc-dev, netdev, Brian King, Nathan Fontenot,
David Darrington
In-Reply-To: <20080704125615.GQ1310@linux.vnet.ibm.com>
I removed references to 'entitlement' after having changed the function
'get_io_entitlement' to 'get_desired_dma' to correctly indicate what the
function was doing. Also, this function does not need to page align the
return value, the VIO bus is responsible for this.
(We would like to take this patch through linuxppc-dev with the full
change set for this feature. We are copying netdev for review and ack)
Enable ibmveth for Cooperative Memory Overcommitment (CMO). For this driver
it means calculating a desired amount of IO memory based on the current MTU
and updating this value with the bus when MTU changes occur. Because DMA
mappings can fail, we have added a bounce buffer for temporary cases where
the driver can not map IO memory for the buffer pool.
The following changes are made to enable the driver for CMO:
* DMA mapping errors will not result in error messages if entitlement has
been exceeded and resources were not available.
* DMA mapping errors are handled gracefully, ibmveth_replenish_buffer_pool()
is corrected to check the return from dma_map_single and fail gracefully.
* The driver will have a get_desired_dma function defined to function
in a CMO environment.
* When the MTU is changed, the driver will update the device IO entitlement
Signed-off-by: Robert Jennings <rcj@linux.vnet.ibm.com>
Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
Signed-off-by: Santiago Leon <santil@us.ibm.com>
---
drivers/net/ibmveth.c | 169 ++++++++++++++++++++++++++++++++++++++++----------
drivers/net/ibmveth.h | 5 +
2 files changed, 140 insertions(+), 34 deletions(-)
Index: b/drivers/net/ibmveth.c
===================================================================
--- a/drivers/net/ibmveth.c
+++ b/drivers/net/ibmveth.c
@@ -33,6 +33,7 @@
*/
#include <linux/module.h>
+#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/ioport.h>
@@ -52,7 +53,9 @@
#include <asm/hvcall.h>
#include <asm/atomic.h>
#include <asm/vio.h>
+#include <asm/iommu.h>
#include <asm/uaccess.h>
+#include <asm/firmware.h>
#include <linux/seq_file.h>
#include "ibmveth.h"
@@ -94,8 +97,10 @@ static void ibmveth_proc_register_adapte
static void ibmveth_proc_unregister_adapter(struct ibmveth_adapter *adapter);
static irqreturn_t ibmveth_interrupt(int irq, void *dev_instance);
static void ibmveth_rxq_harvest_buffer(struct ibmveth_adapter *adapter);
+static unsigned long ibmveth_get_desired_dma(struct vio_dev *vdev);
static struct kobj_type ktype_veth_pool;
+
#ifdef CONFIG_PROC_FS
#define IBMVETH_PROC_DIR "ibmveth"
static struct proc_dir_entry *ibmveth_proc_dir;
@@ -226,16 +231,16 @@ static void ibmveth_replenish_buffer_poo
u32 i;
u32 count = pool->size - atomic_read(&pool->available);
u32 buffers_added = 0;
+ struct sk_buff *skb;
+ unsigned int free_index, index;
+ u64 correlator;
+ unsigned long lpar_rc;
+ dma_addr_t dma_addr;
mb();
for(i = 0; i < count; ++i) {
- struct sk_buff *skb;
- unsigned int free_index, index;
- u64 correlator;
union ibmveth_buf_desc desc;
- unsigned long lpar_rc;
- dma_addr_t dma_addr;
skb = alloc_skb(pool->buff_size, GFP_ATOMIC);
@@ -255,6 +260,9 @@ static void ibmveth_replenish_buffer_poo
dma_addr = dma_map_single(&adapter->vdev->dev, skb->data,
pool->buff_size, DMA_FROM_DEVICE);
+ if (dma_mapping_error(dma_addr))
+ goto failure;
+
pool->free_map[free_index] = IBM_VETH_INVALID_MAP;
pool->dma_addr[index] = dma_addr;
pool->skbuff[index] = skb;
@@ -267,20 +275,9 @@ static void ibmveth_replenish_buffer_poo
lpar_rc = h_add_logical_lan_buffer(adapter->vdev->unit_address, desc.desc);
- if(lpar_rc != H_SUCCESS) {
- pool->free_map[free_index] = index;
- pool->skbuff[index] = NULL;
- if (pool->consumer_index == 0)
- pool->consumer_index = pool->size - 1;
- else
- pool->consumer_index--;
- dma_unmap_single(&adapter->vdev->dev,
- pool->dma_addr[index], pool->buff_size,
- DMA_FROM_DEVICE);
- dev_kfree_skb_any(skb);
- adapter->replenish_add_buff_failure++;
- break;
- } else {
+ if (lpar_rc != H_SUCCESS)
+ goto failure;
+ else {
buffers_added++;
adapter->replenish_add_buff_success++;
}
@@ -288,6 +285,24 @@ static void ibmveth_replenish_buffer_poo
mb();
atomic_add(buffers_added, &(pool->available));
+ return;
+
+failure:
+ pool->free_map[free_index] = index;
+ pool->skbuff[index] = NULL;
+ if (pool->consumer_index == 0)
+ pool->consumer_index = pool->size - 1;
+ else
+ pool->consumer_index--;
+ if (!dma_mapping_error(dma_addr))
+ dma_unmap_single(&adapter->vdev->dev,
+ pool->dma_addr[index], pool->buff_size,
+ DMA_FROM_DEVICE);
+ dev_kfree_skb_any(skb);
+ adapter->replenish_add_buff_failure++;
+
+ mb();
+ atomic_add(buffers_added, &(pool->available));
}
/* replenish routine */
@@ -297,7 +312,7 @@ static void ibmveth_replenish_task(struc
adapter->replenish_task_cycles++;
- for(i = 0; i < IbmVethNumBufferPools; i++)
+ for (i = (IbmVethNumBufferPools - 1); i >= 0; i--)
if(adapter->rx_buff_pool[i].active)
ibmveth_replenish_buffer_pool(adapter,
&adapter->rx_buff_pool[i]);
@@ -472,6 +487,18 @@ static void ibmveth_cleanup(struct ibmve
if (adapter->rx_buff_pool[i].active)
ibmveth_free_buffer_pool(adapter,
&adapter->rx_buff_pool[i]);
+
+ if (adapter->bounce_buffer != NULL) {
+ if (!dma_mapping_error(adapter->bounce_buffer_dma)) {
+ dma_unmap_single(&adapter->vdev->dev,
+ adapter->bounce_buffer_dma,
+ adapter->netdev->mtu + IBMVETH_BUFF_OH,
+ DMA_BIDIRECTIONAL);
+ adapter->bounce_buffer_dma = DMA_ERROR_CODE;
+ }
+ kfree(adapter->bounce_buffer);
+ adapter->bounce_buffer = NULL;
+ }
}
static int ibmveth_register_logical_lan(struct ibmveth_adapter *adapter,
@@ -607,6 +634,24 @@ static int ibmveth_open(struct net_devic
return rc;
}
+ adapter->bounce_buffer =
+ kmalloc(netdev->mtu + IBMVETH_BUFF_OH, GFP_KERNEL);
+ if (!adapter->bounce_buffer) {
+ ibmveth_error_printk("unable to allocate bounce buffer\n");
+ ibmveth_cleanup(adapter);
+ napi_disable(&adapter->napi);
+ return -ENOMEM;
+ }
+ adapter->bounce_buffer_dma =
+ dma_map_single(&adapter->vdev->dev, adapter->bounce_buffer,
+ netdev->mtu + IBMVETH_BUFF_OH, DMA_BIDIRECTIONAL);
+ if (dma_mapping_error(adapter->bounce_buffer_dma)) {
+ ibmveth_error_printk("unable to map bounce buffer\n");
+ ibmveth_cleanup(adapter);
+ napi_disable(&adapter->napi);
+ return -ENOMEM;
+ }
+
ibmveth_debug_printk("initial replenish cycle\n");
ibmveth_interrupt(netdev->irq, netdev);
@@ -853,10 +898,12 @@ static int ibmveth_start_xmit(struct sk_
unsigned int tx_packets = 0;
unsigned int tx_send_failed = 0;
unsigned int tx_map_failed = 0;
+ int used_bounce = 0;
+ unsigned long data_dma_addr;
desc.fields.flags_len = IBMVETH_BUF_VALID | skb->len;
- desc.fields.address = dma_map_single(&adapter->vdev->dev, skb->data,
- skb->len, DMA_TO_DEVICE);
+ data_dma_addr = dma_map_single(&adapter->vdev->dev, skb->data,
+ skb->len, DMA_TO_DEVICE);
if (skb->ip_summed == CHECKSUM_PARTIAL &&
ip_hdr(skb)->protocol != IPPROTO_TCP && skb_checksum_help(skb)) {
@@ -875,12 +922,16 @@ static int ibmveth_start_xmit(struct sk_
buf[1] = 0;
}
- if (dma_mapping_error(desc.fields.address)) {
- ibmveth_error_printk("tx: unable to map xmit buffer\n");
+ if (dma_mapping_error(data_dma_addr)) {
+ if (!firmware_has_feature(FW_FEATURE_CMO))
+ ibmveth_error_printk("tx: unable to map xmit buffer\n");
+ skb_copy_from_linear_data(skb, adapter->bounce_buffer,
+ skb->len);
+ desc.fields.address = adapter->bounce_buffer_dma;
tx_map_failed++;
- tx_dropped++;
- goto out;
- }
+ used_bounce = 1;
+ } else
+ desc.fields.address = data_dma_addr;
/* send the frame. Arbitrarily set retrycount to 1024 */
correlator = 0;
@@ -904,8 +955,9 @@ static int ibmveth_start_xmit(struct sk_
netdev->trans_start = jiffies;
}
- dma_unmap_single(&adapter->vdev->dev, desc.fields.address,
- skb->len, DMA_TO_DEVICE);
+ if (!used_bounce)
+ dma_unmap_single(&adapter->vdev->dev, data_dma_addr,
+ skb->len, DMA_TO_DEVICE);
out: spin_lock_irqsave(&adapter->stats_lock, flags);
netdev->stats.tx_dropped += tx_dropped;
@@ -1053,8 +1105,9 @@ static void ibmveth_set_multicast_list(s
static int ibmveth_change_mtu(struct net_device *dev, int new_mtu)
{
struct ibmveth_adapter *adapter = dev->priv;
+ struct vio_dev *viodev = adapter->vdev;
int new_mtu_oh = new_mtu + IBMVETH_BUFF_OH;
- int i, rc;
+ int i;
if (new_mtu < IBMVETH_MAX_MTU)
return -EINVAL;
@@ -1085,10 +1138,15 @@ static int ibmveth_change_mtu(struct net
ibmveth_close(adapter->netdev);
adapter->pool_config = 0;
dev->mtu = new_mtu;
- if ((rc = ibmveth_open(adapter->netdev)))
- return rc;
- } else
- dev->mtu = new_mtu;
+ vio_cmo_set_dev_desired(viodev,
+ ibmveth_get_desired_dma
+ (viodev));
+ return ibmveth_open(adapter->netdev);
+ }
+ dev->mtu = new_mtu;
+ vio_cmo_set_dev_desired(viodev,
+ ibmveth_get_desired_dma
+ (viodev));
return 0;
}
}
@@ -1103,6 +1161,46 @@ static void ibmveth_poll_controller(stru
}
#endif
+/**
+ * ibmveth_get_desired_dma - Calculate IO memory desired by the driver
+ *
+ * @vdev: struct vio_dev for the device whose desired IO mem is to be returned
+ *
+ * Return value:
+ * Number of bytes of IO data the driver will need to perform well.
+ */
+static unsigned long ibmveth_get_desired_dma(struct vio_dev *vdev)
+{
+ struct net_device *netdev = dev_get_drvdata(&vdev->dev);
+ struct ibmveth_adapter *adapter;
+ unsigned long ret;
+ int i;
+ int rxqentries = 1;
+
+ /* netdev inits at probe time along with the structures we need below*/
+ if (netdev == NULL)
+ return IOMMU_PAGE_ALIGN(IBMVETH_IO_ENTITLEMENT_DEFAULT);
+
+ adapter = netdev_priv(netdev);
+
+ ret = IBMVETH_BUFF_LIST_SIZE + IBMVETH_FILT_LIST_SIZE;
+ ret += IOMMU_PAGE_ALIGN(netdev->mtu);
+
+ for (i = 0; i < IbmVethNumBufferPools; i++) {
+ /* add the size of the active receive buffers */
+ if (adapter->rx_buff_pool[i].active)
+ ret +=
+ adapter->rx_buff_pool[i].size *
+ IOMMU_PAGE_ALIGN(adapter->rx_buff_pool[i].
+ buff_size);
+ rxqentries += adapter->rx_buff_pool[i].size;
+ }
+ /* add the size of the receive queue entries */
+ ret += IOMMU_PAGE_ALIGN(rxqentries * sizeof(struct ibmveth_rx_q_entry));
+
+ return ret;
+}
+
static int __devinit ibmveth_probe(struct vio_dev *dev, const struct vio_device_id *id)
{
int rc, i;
@@ -1247,6 +1345,8 @@ static int __devexit ibmveth_remove(stru
ibmveth_proc_unregister_adapter(adapter);
free_netdev(netdev);
+ dev_set_drvdata(&dev->dev, NULL);
+
return 0;
}
@@ -1491,6 +1591,7 @@ static struct vio_driver ibmveth_driver
.id_table = ibmveth_device_table,
.probe = ibmveth_probe,
.remove = ibmveth_remove,
+ .get_desired_dma = ibmveth_get_desired_dma,
.driver = {
.name = ibmveth_driver_name,
.owner = THIS_MODULE,
Index: b/drivers/net/ibmveth.h
===================================================================
--- a/drivers/net/ibmveth.h
+++ b/drivers/net/ibmveth.h
@@ -93,9 +93,12 @@ static inline long h_illan_attributes(un
plpar_hcall_norets(H_CHANGE_LOGICAL_LAN_MAC, ua, mac)
#define IbmVethNumBufferPools 5
+#define IBMVETH_IO_ENTITLEMENT_DEFAULT 4243456 /* MTU of 1500 needs 4.2Mb */
#define IBMVETH_BUFF_OH 22 /* Overhead: 14 ethernet header + 8 opaque handle */
#define IBMVETH_MAX_MTU 68
#define IBMVETH_MAX_POOL_COUNT 4096
+#define IBMVETH_BUFF_LIST_SIZE 4096
+#define IBMVETH_FILT_LIST_SIZE 4096
#define IBMVETH_MAX_BUF_SIZE (1024 * 128)
static int pool_size[] = { 512, 1024 * 2, 1024 * 16, 1024 * 32, 1024 * 64 };
@@ -143,6 +146,8 @@ struct ibmveth_adapter {
struct ibmveth_rx_q rx_queue;
int pool_config;
int rx_csum;
+ void *bounce_buffer;
+ dma_addr_t bounce_buffer_dma;
/* adapter specific stats */
u64 replenish_task_cycles;
^ permalink raw reply
* Re: [PATCH 10/16 v3] [v2] powerpc: iommu enablement for CMO
From: Robert Jennings @ 2008-07-08 20:48 UTC (permalink / raw)
To: paulus, benh, linuxppc-dev, Brian King, Nathan Fontenot,
David Darrington
In-Reply-To: <20080704125459.GM1310@linux.vnet.ibm.com>
=46rom: Robert Jennings <rcj@linux.vnet.ibm.com>
Minor change to add a call to align the return from the device's
get_desired_dma() function with IOMMU_PAGE_ALIGN(). Also removed a
comment referring to a non-existent structure member.
This is a large patch but the normal code path is not affected. For
non-pSeries platforms the code is ifdef'ed out and for non-CMO enabled
pSeries systems this does not affect the normal code path. Devices that
do not perform DMA operations do not need modification with this patch.
The function get_desired_dma was renamed from get_io_entitlement for
clarity.
Overview
Cooperative Memory Overcommitment (CMO) allows for a set of OS partitions
to be run with less RAM than the aggregate needs of the group of
partitions. The firmware will balance memory between the partitions
and page in/out memory as needed. Based on the number and type of IO
adapters preset each partition is allocated an amount of memory for
DMA operations and this allocation will be guaranteed to the partition;
this is referred to as the partition's 'entitlement'.
Partitions running in a CMO environment can only have virtual IO devices
present. The VIO bus layer will manage the IO entitlement for the system.
Accounting, at a system and per-device level, is tracked in the VIO bus
code and exposed via sysfs. A set of dma_ops functions are added to
the bus to allow for this accounting.
Bus initialization
At initialization, the bus will calculate the minimum needs of the system
based on providing each device present with a standard minimum entitlement
along with a spare allocation for the bus to handle hot-plug events.
If the minimum needs can not be met the system boot will be halted.
Device changes
The significant changes for devices while running under CMO are that the
devices must specify how much dedicated IO entitlement they desire and
must also handle DMA mapping errors that can occur due to constrained
IO memory. The virtual IO drivers are modified to silence errors when
DMA mappings fail for CMO and handle these failures gracefully.
Each devices will be guaranteed a minimum entitlement that can always
be mapped. Devices will specify how much entitlement they desire and
the VIO bus will attempt to provide for this. Devices can change their
desired entitlement level at any point in time to address particular needs
(via vio_cmo_set_dev_desired()), not just at device probe time.
VIO bus changes
The system will have a particular entitlement level available from which
it can provide memory to the devices. The bus defines two pools of memory
within this entitlement, the reserved and excess pools. Each device is
provided with it's own entitlement no less than a system defined minimum
entitlement and no greater than what the device has specified as it's
desired entitlement. The entitlement provided to devices comes from the
reserve pool. The reserve pool can also contain a spare allocation as
large as the system defined minimum entitlement which is used for device
hot-plug events. Any entitlement not needed to fulfill the needs of a
reserve pool is placed in the excess pool. Each device is guaranteed
that it can map up to it's entitled level; additional mapping are possible
as long as there is unmapped memory in the excess pool.
Bus probe
As the system starts, each device is given an entitlement equal only
to the system defined minimum entitlement. The reserve pool is equal
to the sum of these entitlements, plus a spare allocation. The VIO bus
also tracks the aggregate desired entitlement of all the devices. If the
system desired entitlement is greater than the size of the reserve pool,
when devices unmap IO memory it will be reserved and a balance operation
will be scheduled for some time in the future.
Entitlement balancing
The balance function tries to fairly distribute entitlement between the
devices in the system with the goal of providing each device with it's
desired amount of entitlement. Devices using more than what would be
ideal will have their entitled set-point adjusted; this will effectively
set a goal for lower IO memory usage as future mappings can fail and
deallocations will trigger a balance operation to distribute the newly
unmapped memory. A fair distribution of entitlement can take several
balance operations to achieve. Entitlement changes and device DLPAR
events will alter the state of CMO and will trigger balance operations.
Hotplug events
The VIO bus allows for changes in system entitlement at run-time via
'vio_cmo_entitlement_update()'. When devices are added the hot-plug
device event will be preceded by a system entitlement increase and this
is reversed when devices are removed.
The following changes are made that the VIO bus layer for CMO:
* add IO memory accounting per device structure.
* add IO memory entitlement query function to driver structure.
* during vio bus probe, if CMO is enabled, check that driver has
memory entitlement query function defined. Fail if function not defined.
* fail to register driver if io entitlement function not defined.
* create set of dma_ops at vio level for CMO that will track allocations
and return DMA failures once entitlement is reached. Entitlement will
limited by overall system entitlement. Devices will have a reserved
quantity of memory that is guaranteed, the rest can be used as available.
* expose entitlement, current allocation, desired allocation, and the
allocation error counter for devices to the user through sysfs
* provide mechanism for changing a device's desired entitlement at run time
for devices as an exported function and sysfs tunable
* track any DMA failures for entitled IO memory for each vio device.
* check entitlement against available system entitlement on device add
* track entitlement metrics (high water mark, current usage)
* provide function to reset high water mark
* provide minimum and desired entitlement numbers at a bus level
* provide drivers with a minimum guaranteed entitlement
* balance available entitlement between devices to satisfy their needs
* handle system entitlement changes and device hot-plug
Signed-off-by: Robert Jennings <rcj@linux.vnet.ibm.com>
---
arch/powerpc/kernel/vio.c | 1024 +++++++++++++++++++++++++++++++++++++++++=
+++++
include/asm-powerpc/vio.h | 27 +
2 files changed, 1043 insertions(+), 8 deletions(-)
Index: b/arch/powerpc/kernel/vio.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -1,11 +1,12 @@
/*
* IBM PowerPC Virtual I/O Infrastructure Support.
*
- * Copyright (c) 2003-2005 IBM Corp.
+ * Copyright (c) 2003,2008 IBM Corp.
* Dave Engebretsen engebret@us.ibm.com
* Santiago Leon santil@us.ibm.com
* Hollis Blanchard <hollisb@us.ibm.com>
* Stephen Rothwell
+ * Robert Jennings <rcjenn@us.ibm.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -46,6 +47,987 @@ static struct vio_dev vio_bus_device =3D=20
.dev.bus =3D &vio_bus_type,
};
=20
+#ifdef CONFIG_PPC_PSERIES
+/**
+ * vio_cmo_pool - A pool of IO memory for CMO use
+ *
+ * @size: The size of the pool in bytes
+ * @free: The amount of free memory in the pool
+ */
+struct vio_cmo_pool {
+ size_t size;
+ size_t free;
+};
+
+/* How many ms to delay queued balance work */
+#define VIO_CMO_BALANCE_DELAY 100
+
+/* Portion out IO memory to CMO devices by this chunk size */
+#define VIO_CMO_BALANCE_CHUNK 131072
+
+/**
+ * vio_cmo_dev_entry - A device that is CMO-enabled and requires entitleme=
nt
+ *
+ * @vio_dev: struct vio_dev pointer
+ * @list: pointer to other devices on bus that are being tracked
+ */
+struct vio_cmo_dev_entry {
+ struct vio_dev *viodev;
+ struct list_head list;
+};
+
+/**
+ * vio_cmo - VIO bus accounting structure for CMO entitlement
+ *
+ * @lock: spinlock for entire structure
+ * @balance_q: work queue for balancing system entitlement
+ * @device_list: list of CMO-enabled devices requiring entitlement
+ * @entitled: total system entitlement in bytes
+ * @reserve: pool of memory from which devices reserve entitlement, incl. =
spare
+ * @excess: pool of excess entitlement not needed for device reserves or s=
pare
+ * @spare: IO memory for device hotplug functionality
+ * @min: minimum necessary for system operation
+ * @desired: desired memory for system operation
+ * @curr: bytes currently allocated
+ * @high: high water mark for IO data usage
+ */
+struct vio_cmo {
+ spinlock_t lock;
+ struct delayed_work balance_q;
+ struct list_head device_list;
+ size_t entitled;
+ struct vio_cmo_pool reserve;
+ struct vio_cmo_pool excess;
+ size_t spare;
+ size_t min;
+ size_t desired;
+ size_t curr;
+ size_t high;
+} vio_cmo;
+
+/**
+ * vio_cmo_OF_devices - Count the number of OF devices that have DMA windo=
ws
+ */
+static int vio_cmo_num_OF_devs(void)
+{
+ struct device_node *node_vroot;
+ int count =3D 0;
+
+ /*
+ * Count the number of vdevice entries with an
+ * ibm,my-dma-window OF property
+ */
+ node_vroot =3D of_find_node_by_name(NULL, "vdevice");
+ if (node_vroot) {
+ struct device_node *of_node;
+ struct property *prop;
+
+ for_each_child_of_node(node_vroot, of_node) {
+ prop =3D of_find_property(of_node, "ibm,my-dma-window",
+ NULL);
+ if (prop)
+ count++;
+ }
+ }
+ of_node_put(node_vroot);
+ return count;
+}
+
+/**
+ * vio_cmo_alloc - allocate IO memory for CMO-enable devices
+ *
+ * @viodev: VIO device requesting IO memory
+ * @size: size of allocation requested
+ *
+ * Allocations come from memory reserved for the devices and any excess
+ * IO memory available to all devices. The spare pool used to service
+ * hotplug must be equal to %VIO_CMO_MIN_ENT for the excess pool to be
+ * made available.
+ *
+ * Return codes:
+ * 0 for successful allocation and -ENOMEM for a failure
+ */
+static inline int vio_cmo_alloc(struct vio_dev *viodev, size_t size)
+{
+ unsigned long flags;
+ size_t reserve_free =3D 0;
+ size_t excess_free =3D 0;
+ int ret =3D -ENOMEM;
+
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+
+ /* Determine the amount of free entitlement available in reserve */
+ if (viodev->cmo.entitled > viodev->cmo.allocated)
+ reserve_free =3D viodev->cmo.entitled - viodev->cmo.allocated;
+
+ /* If spare is not fulfilled, the excess pool can not be used. */
+ if (vio_cmo.spare >=3D VIO_CMO_MIN_ENT)
+ excess_free =3D vio_cmo.excess.free;
+
+ /* The request can be satisfied */
+ if ((reserve_free + excess_free) >=3D size) {
+ vio_cmo.curr +=3D size;
+ if (vio_cmo.curr > vio_cmo.high)
+ vio_cmo.high =3D vio_cmo.curr;
+ viodev->cmo.allocated +=3D size;
+ size -=3D min(reserve_free, size);
+ vio_cmo.excess.free -=3D size;
+ ret =3D 0;
+ }
+
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+ return ret;
+}
+
+/**
+ * vio_cmo_dealloc - deallocate IO memory from CMO-enable devices
+ * @viodev: VIO device freeing IO memory
+ * @size: size of deallocation
+ *
+ * IO memory is freed by the device back to the correct memory pools.
+ * The spare pool is replenished first from either memory pool, then
+ * the reserve pool is used to reduce device entitlement, the excess
+ * pool is used to increase the reserve pool toward the desired entitlement
+ * target, and then the remaining memory is returned to the pools.
+ *
+ */
+static inline void vio_cmo_dealloc(struct vio_dev *viodev, size_t size)
+{
+ unsigned long flags;
+ size_t spare_needed =3D 0;
+ size_t excess_freed =3D 0;
+ size_t reserve_freed =3D size;
+ size_t tmp;
+ int balance =3D 0;
+
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+ vio_cmo.curr -=3D size;
+
+ /* Amount of memory freed from the excess pool */
+ if (viodev->cmo.allocated > viodev->cmo.entitled) {
+ excess_freed =3D min(reserve_freed, (viodev->cmo.allocated -
+ viodev->cmo.entitled));
+ reserve_freed -=3D excess_freed;
+ }
+
+ /* Remove allocation from device */
+ viodev->cmo.allocated -=3D (reserve_freed + excess_freed);
+
+ /* Spare is a subset of the reserve pool, replenish it first. */
+ spare_needed =3D VIO_CMO_MIN_ENT - vio_cmo.spare;
+
+ /*
+ * Replenish the spare in the reserve pool from the excess pool.
+ * This moves entitlement into the reserve pool.
+ */
+ if (spare_needed && excess_freed) {
+ tmp =3D min(excess_freed, spare_needed);
+ vio_cmo.excess.size -=3D tmp;
+ vio_cmo.reserve.size +=3D tmp;
+ vio_cmo.spare +=3D tmp;
+ excess_freed -=3D tmp;
+ spare_needed -=3D tmp;
+ balance =3D 1;
+ }
+
+ /*
+ * Replenish the spare in the reserve pool from the reserve pool.
+ * This removes entitlement from the device down to VIO_CMO_MIN_ENT,
+ * if needed, and gives it to the spare pool. The amount of used
+ * memory in this pool does not change.
+ */
+ if (spare_needed && reserve_freed) {
+ tmp =3D min(spare_needed, min(reserve_freed,
+ (viodev->cmo.entitled -
+ VIO_CMO_MIN_ENT)));
+
+ vio_cmo.spare +=3D tmp;
+ viodev->cmo.entitled -=3D tmp;
+ reserve_freed -=3D tmp;
+ spare_needed -=3D tmp;
+ balance =3D 1;
+ }
+
+ /*
+ * Increase the reserve pool until the desired allocation is met.
+ * Move an allocation freed from the excess pool into the reserve
+ * pool and schedule a balance operation.
+ */
+ if (excess_freed && (vio_cmo.desired > vio_cmo.reserve.size)) {
+ tmp =3D min(excess_freed, (vio_cmo.desired - vio_cmo.reserve.size));
+
+ vio_cmo.excess.size -=3D tmp;
+ vio_cmo.reserve.size +=3D tmp;
+ excess_freed -=3D tmp;
+ balance =3D 1;
+ }
+
+ /* Return memory from the excess pool to that pool */
+ if (excess_freed)
+ vio_cmo.excess.free +=3D excess_freed;
+
+ if (balance)
+ schedule_delayed_work(&vio_cmo.balance_q, VIO_CMO_BALANCE_DELAY);
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+}
+
+/**
+ * vio_cmo_entitlement_update - Manage system entitlement changes
+ *
+ * @new_entitlement: new system entitlement to attempt to accommodate
+ *
+ * Increases in entitlement will be used to fulfill the spare entitlement
+ * and the rest is given to the excess pool. Decreases, if they are
+ * possible, come from the excess pool and from unused device entitlement
+ *
+ * Returns: 0 on success, -ENOMEM when change can not be made
+ */
+int vio_cmo_entitlement_update(size_t new_entitlement)
+{
+ struct vio_dev *viodev;
+ struct vio_cmo_dev_entry *dev_ent;
+ unsigned long flags;
+ size_t avail, delta, tmp;
+
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+
+ /* Entitlement increases */
+ if (new_entitlement > vio_cmo.entitled) {
+ delta =3D new_entitlement - vio_cmo.entitled;
+
+ /* Fulfill spare allocation */
+ if (vio_cmo.spare < VIO_CMO_MIN_ENT) {
+ tmp =3D min(delta, (VIO_CMO_MIN_ENT - vio_cmo.spare));
+ vio_cmo.spare +=3D tmp;
+ vio_cmo.reserve.size +=3D tmp;
+ delta -=3D tmp;
+ }
+
+ /* Remaining new allocation goes to the excess pool */
+ vio_cmo.entitled +=3D delta;
+ vio_cmo.excess.size +=3D delta;
+ vio_cmo.excess.free +=3D delta;
+
+ goto out;
+ }
+
+ /* Entitlement decreases */
+ delta =3D vio_cmo.entitled - new_entitlement;
+ avail =3D vio_cmo.excess.free;
+
+ /*
+ * Need to check how much unused entitlement each device can
+ * sacrifice to fulfill entitlement change.
+ */
+ list_for_each_entry(dev_ent, &vio_cmo.device_list, list) {
+ if (avail >=3D delta)
+ break;
+
+ viodev =3D dev_ent->viodev;
+ if ((viodev->cmo.entitled > viodev->cmo.allocated) &&
+ (viodev->cmo.entitled > VIO_CMO_MIN_ENT))
+ avail +=3D viodev->cmo.entitled -
+ max_t(size_t, viodev->cmo.allocated,
+ VIO_CMO_MIN_ENT);
+ }
+
+ if (delta <=3D avail) {
+ vio_cmo.entitled -=3D delta;
+
+ /* Take entitlement from the excess pool first */
+ tmp =3D min(vio_cmo.excess.free, delta);
+ vio_cmo.excess.size -=3D tmp;
+ vio_cmo.excess.free -=3D tmp;
+ delta -=3D tmp;
+
+ /*
+ * Remove all but VIO_CMO_MIN_ENT bytes from devices
+ * until entitlement change is served
+ */
+ list_for_each_entry(dev_ent, &vio_cmo.device_list, list) {
+ if (!delta)
+ break;
+
+ viodev =3D dev_ent->viodev;
+ tmp =3D 0;
+ if ((viodev->cmo.entitled > viodev->cmo.allocated) &&
+ (viodev->cmo.entitled > VIO_CMO_MIN_ENT))
+ tmp =3D viodev->cmo.entitled -
+ max_t(size_t, viodev->cmo.allocated,
+ VIO_CMO_MIN_ENT);
+ viodev->cmo.entitled -=3D min(tmp, delta);
+ delta -=3D min(tmp, delta);
+ }
+ } else {
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+ return -ENOMEM;
+ }
+
+out:
+ schedule_delayed_work(&vio_cmo.balance_q, 0);
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+ return 0;
+}
+
+/**
+ * vio_cmo_balance - Balance entitlement among devices
+ *
+ * @work: work queue structure for this operation
+ *
+ * Any system entitlement above the minimum needed for devices, or
+ * already allocated to devices, can be distributed to the devices.
+ * The list of devices is iterated through to recalculate the desired
+ * entitlement level and to determine how much entitlement above the
+ * minimum entitlement is allocated to devices.
+ *
+ * Small chunks of the available entitlement are given to devices until
+ * their requirements are fulfilled or there is no entitlement left to giv=
e.
+ * Upon completion sizes of the reserve and excess pools are calculated.
+ *
+ * The system minimum entitlement level is also recalculated here.
+ * Entitlement will be reserved for devices even after vio_bus_remove to
+ * accommodate reloading the driver. The OF tree is walked to count the
+ * number of devices present and this will remove entitlement for devices
+ * that have actually left the system after having vio_bus_remove called.
+ */
+static void vio_cmo_balance(struct work_struct *work)
+{
+ struct vio_cmo *cmo;
+ struct vio_dev *viodev;
+ struct vio_cmo_dev_entry *dev_ent;
+ unsigned long flags;
+ size_t avail =3D 0, level, chunk, need;
+ int devcount =3D 0, fulfilled;
+
+ cmo =3D container_of(work, struct vio_cmo, balance_q.work);
+
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+
+ /* Calculate minimum entitlement and fulfill spare */
+ cmo->min =3D vio_cmo_num_OF_devs() * VIO_CMO_MIN_ENT;
+ BUG_ON(cmo->min > cmo->entitled);
+ cmo->spare =3D min_t(size_t, VIO_CMO_MIN_ENT, (cmo->entitled - cmo->min));
+ cmo->min +=3D cmo->spare;
+ cmo->desired =3D cmo->min;
+
+ /*
+ * Determine how much entitlement is available and reset device
+ * entitlements
+ */
+ avail =3D cmo->entitled - cmo->spare;
+ list_for_each_entry(dev_ent, &vio_cmo.device_list, list) {
+ viodev =3D dev_ent->viodev;
+ devcount++;
+ viodev->cmo.entitled =3D VIO_CMO_MIN_ENT;
+ cmo->desired +=3D (viodev->cmo.desired - VIO_CMO_MIN_ENT);
+ avail -=3D max_t(size_t, viodev->cmo.allocated, VIO_CMO_MIN_ENT);
+ }
+
+ /*
+ * Having provided each device with the minimum entitlement, loop
+ * over the devices portioning out the remaining entitlement
+ * until there is nothing left.
+ */
+ level =3D VIO_CMO_MIN_ENT;
+ while (avail) {
+ fulfilled =3D 0;
+ list_for_each_entry(dev_ent, &vio_cmo.device_list, list) {
+ viodev =3D dev_ent->viodev;
+
+ if (viodev->cmo.desired <=3D level) {
+ fulfilled++;
+ continue;
+ }
+
+ /*
+ * Give the device up to VIO_CMO_BALANCE_CHUNK
+ * bytes of entitlement, but do not exceed the
+ * desired level of entitlement for the device.
+ */
+ chunk =3D min_t(size_t, avail, VIO_CMO_BALANCE_CHUNK);
+ chunk =3D min(chunk, (viodev->cmo.desired -
+ viodev->cmo.entitled));
+ viodev->cmo.entitled +=3D chunk;
+
+ /*
+ * If the memory for this entitlement increase was
+ * already allocated to the device it does not come
+ * from the available pool being portioned out.
+ */
+ need =3D max(viodev->cmo.allocated, viodev->cmo.entitled)-
+ max(viodev->cmo.allocated, level);
+ avail -=3D need;
+
+ }
+ if (fulfilled =3D=3D devcount)
+ break;
+ level +=3D VIO_CMO_BALANCE_CHUNK;
+ }
+
+ /* Calculate new reserve and excess pool sizes */
+ cmo->reserve.size =3D cmo->min;
+ cmo->excess.free =3D 0;
+ cmo->excess.size =3D 0;
+ need =3D 0;
+ list_for_each_entry(dev_ent, &vio_cmo.device_list, list) {
+ viodev =3D dev_ent->viodev;
+ /* Calculated reserve size above the minimum entitlement */
+ if (viodev->cmo.entitled)
+ cmo->reserve.size +=3D (viodev->cmo.entitled -
+ VIO_CMO_MIN_ENT);
+ /* Calculated used excess entitlement */
+ if (viodev->cmo.allocated > viodev->cmo.entitled)
+ need +=3D viodev->cmo.allocated - viodev->cmo.entitled;
+ }
+ cmo->excess.size =3D cmo->entitled - cmo->reserve.size;
+ cmo->excess.free =3D cmo->excess.size - need;
+
+ cancel_delayed_work(container_of(work, struct delayed_work, work));
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+}
+
+static void *vio_dma_iommu_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t fl=
ag)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+ void *ret;
+
+ if (vio_cmo_alloc(viodev, roundup(size, PAGE_SIZE))) {
+ atomic_inc(&viodev->cmo.allocs_failed);
+ return NULL;
+ }
+
+ ret =3D dma_iommu_ops.alloc_coherent(dev, size, dma_handle, flag);
+ if (unlikely(ret =3D=3D NULL)) {
+ vio_cmo_dealloc(viodev, roundup(size, PAGE_SIZE));
+ atomic_inc(&viodev->cmo.allocs_failed);
+ }
+
+ return ret;
+}
+
+static void vio_dma_iommu_free_coherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+
+ dma_iommu_ops.free_coherent(dev, size, vaddr, dma_handle);
+
+ vio_cmo_dealloc(viodev, roundup(size, PAGE_SIZE));
+}
+
+static dma_addr_t vio_dma_iommu_map_single(struct device *dev, void *vaddr,
+ size_t size,
+ enum dma_data_direction directi=
on)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+ dma_addr_t ret =3D DMA_ERROR_CODE;
+
+ if (vio_cmo_alloc(viodev, roundup(size, PAGE_SIZE))) {
+ atomic_inc(&viodev->cmo.allocs_failed);
+ return ret;
+ }
+
+ ret =3D dma_iommu_ops.map_single(dev, vaddr, size, direction);
+ if (unlikely(dma_mapping_error(ret))) {
+ vio_cmo_dealloc(viodev, roundup(size, PAGE_SIZE));
+ atomic_inc(&viodev->cmo.allocs_failed);
+ }
+
+ return ret;
+}
+
+static void vio_dma_iommu_unmap_single(struct device *dev,
+ dma_addr_t dma_handle, size_t size,
+ enum dma_data_direction direction)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+
+ dma_iommu_ops.unmap_single(dev, dma_handle, size, direction);
+
+ vio_cmo_dealloc(viodev, roundup(size, PAGE_SIZE));
+}
+
+static int vio_dma_iommu_map_sg(struct device *dev, struct scatterlist *sg=
list,
+ int nelems, enum dma_data_direction direct=
ion)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+ struct scatterlist *sgl;
+ int ret, count =3D 0;
+ size_t alloc_size =3D 0;
+
+ for (sgl =3D sglist; count < nelems; count++, sgl++)
+ alloc_size +=3D roundup(sgl->length, PAGE_SIZE);
+
+ if (vio_cmo_alloc(viodev, alloc_size)) {
+ atomic_inc(&viodev->cmo.allocs_failed);
+ return 0;
+ }
+
+ ret =3D dma_iommu_ops.map_sg(dev, sglist, nelems, direction);
+
+ if (unlikely(!ret)) {
+ vio_cmo_dealloc(viodev, alloc_size);
+ atomic_inc(&viodev->cmo.allocs_failed);
+ }
+
+ return ret;
+}
+
+static void vio_dma_iommu_unmap_sg(struct device *dev,
+ struct scatterlist *sglist, int nelems,
+ enum dma_data_direction direction)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+ struct scatterlist *sgl;
+ size_t alloc_size =3D 0;
+ int count =3D 0;
+
+ for (sgl =3D sglist; count < nelems; count++, sgl++)
+ alloc_size +=3D roundup(sgl->length, PAGE_SIZE);
+
+ dma_iommu_ops.unmap_sg(dev, sglist, nelems, direction);
+
+ vio_cmo_dealloc(viodev, alloc_size);
+}
+
+struct dma_mapping_ops vio_dma_mapping_ops =3D {
+ .alloc_coherent =3D vio_dma_iommu_alloc_coherent,
+ .free_coherent =3D vio_dma_iommu_free_coherent,
+ .map_single =3D vio_dma_iommu_map_single,
+ .unmap_single =3D vio_dma_iommu_unmap_single,
+ .map_sg =3D vio_dma_iommu_map_sg,
+ .unmap_sg =3D vio_dma_iommu_unmap_sg,
+};
+
+/**
+ * vio_cmo_set_dev_desired - Set desired entitlement for a device
+ *
+ * @viodev: struct vio_dev for device to alter
+ * @new_desired: new desired entitlement level in bytes
+ *
+ * For use by devices to request a change to their entitlement at runtime =
or
+ * through sysfs. The desired entitlement level is changed and a balancing
+ * of system resources is scheduled to run in the future.
+ */
+void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired)
+{
+ unsigned long flags;
+ struct vio_cmo_dev_entry *dev_ent;
+ int found =3D 0;
+
+ if (!firmware_has_feature(FW_FEATURE_CMO))
+ return;
+
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+ if (desired < VIO_CMO_MIN_ENT)
+ desired =3D VIO_CMO_MIN_ENT;
+
+ /*
+ * Changes will not be made for devices not in the device list.
+ * If it is not in the device list, then no driver is loaded
+ * for the device and it can not receive entitlement.
+ */
+ list_for_each_entry(dev_ent, &vio_cmo.device_list, list)
+ if (viodev =3D=3D dev_ent->viodev) {
+ found =3D 1;
+ break;
+ }
+ if (!found)
+ return;
+
+ /* Increase/decrease in desired device entitlement */
+ if (desired >=3D viodev->cmo.desired) {
+ /* Just bump the bus and device values prior to a balance*/
+ vio_cmo.desired +=3D desired - viodev->cmo.desired;
+ viodev->cmo.desired =3D desired;
+ } else {
+ /* Decrease bus and device values for desired entitlement */
+ vio_cmo.desired -=3D viodev->cmo.desired - desired;
+ viodev->cmo.desired =3D desired;
+ /*
+ * If less entitlement is desired than current entitlement, move
+ * any reserve memory in the change region to the excess pool.
+ */
+ if (viodev->cmo.entitled > desired) {
+ vio_cmo.reserve.size -=3D viodev->cmo.entitled - desired;
+ vio_cmo.excess.size +=3D viodev->cmo.entitled - desired;
+ /*
+ * If entitlement moving from the reserve pool to the
+ * excess pool is currently unused, add to the excess
+ * free counter.
+ */
+ if (viodev->cmo.allocated < viodev->cmo.entitled)
+ vio_cmo.excess.free +=3D viodev->cmo.entitled -
+ max(viodev->cmo.allocated, desired);
+ viodev->cmo.entitled =3D desired;
+ }
+ }
+ schedule_delayed_work(&vio_cmo.balance_q, 0);
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+}
+
+/**
+ * vio_cmo_bus_probe - Handle CMO specific bus probe activities
+ *
+ * @viodev - Pointer to struct vio_dev for device
+ *
+ * Determine the devices IO memory entitlement needs, attempting
+ * to satisfy the system minimum entitlement at first and scheduling
+ * a balance operation to take care of the rest at a later time.
+ *
+ * Returns: 0 on success, -EINVAL when device doesn't support CMO, and
+ * -ENOMEM when entitlement is not available for device or
+ * device entry.
+ *
+ */
+static int vio_cmo_bus_probe(struct vio_dev *viodev)
+{
+ struct vio_cmo_dev_entry *dev_ent;
+ struct device *dev =3D &viodev->dev;
+ struct vio_driver *viodrv =3D to_vio_driver(dev->driver);
+ unsigned long flags;
+ size_t size;
+
+ /*
+ * Check to see that device has a DMA window and configure
+ * entitlement for the device.
+ */
+ if (of_get_property(viodev->dev.archdata.of_node,
+ "ibm,my-dma-window", NULL)) {
+ /* Check that the driver is CMO enabled and get desired DMA */
+ if (!viodrv->get_desired_dma) {
+ dev_err(dev, "%s: device driver does not support CMO\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ viodev->cmo.desired =3D IOMMU_PAGE_ALIGN(viodrv->get_desired_dma(viodev)=
);
+ if (viodev->cmo.desired < VIO_CMO_MIN_ENT)
+ viodev->cmo.desired =3D VIO_CMO_MIN_ENT;
+ size =3D VIO_CMO_MIN_ENT;
+
+ dev_ent =3D kmalloc(sizeof(struct vio_cmo_dev_entry),
+ GFP_KERNEL);
+ if (!dev_ent)
+ return -ENOMEM;
+
+ dev_ent->viodev =3D viodev;
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+ list_add(&dev_ent->list, &vio_cmo.device_list);
+ } else {
+ viodev->cmo.desired =3D 0;
+ size =3D 0;
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+ }
+
+ /*
+ * If the needs for vio_cmo.min have not changed since they
+ * were last set, the number of devices in the OF tree has
+ * been constant and the IO memory for this is already in
+ * the reserve pool.
+ */
+ if (vio_cmo.min =3D=3D ((vio_cmo_num_OF_devs() + 1) *
+ VIO_CMO_MIN_ENT)) {
+ /* Updated desired entitlement if device requires it */
+ if (size)
+ vio_cmo.desired +=3D (viodev->cmo.desired -
+ VIO_CMO_MIN_ENT);
+ } else {
+ size_t tmp;
+
+ tmp =3D vio_cmo.spare + vio_cmo.excess.free;
+ if (tmp < size) {
+ dev_err(dev, "%s: insufficient free "
+ "entitlement to add device. "
+ "Need %lu, have %lu\n", __func__,
+ size, (vio_cmo.spare + tmp));
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+ return -ENOMEM;
+ }
+
+ /* Use excess pool first to fulfill request */
+ tmp =3D min(size, vio_cmo.excess.free);
+ vio_cmo.excess.free -=3D tmp;
+ vio_cmo.excess.size -=3D tmp;
+ vio_cmo.reserve.size +=3D tmp;
+
+ /* Use spare if excess pool was insufficient */
+ vio_cmo.spare -=3D size - tmp;
+
+ /* Update bus accounting */
+ vio_cmo.min +=3D size;
+ vio_cmo.desired +=3D viodev->cmo.desired;
+ }
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+ return 0;
+}
+
+/**
+ * vio_cmo_bus_remove - Handle CMO specific bus removal activities
+ *
+ * @viodev - Pointer to struct vio_dev for device
+ *
+ * Remove the device from the cmo device list. The minimum entitlement
+ * will be reserved for the device as long as it is in the system. The
+ * rest of the entitlement the device had been allocated will be returned
+ * to the system.
+ */
+static void vio_cmo_bus_remove(struct vio_dev *viodev)
+{
+ struct vio_cmo_dev_entry *dev_ent;
+ unsigned long flags;
+ size_t tmp;
+
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+ if (viodev->cmo.allocated) {
+ dev_err(&viodev->dev, "%s: device had %lu bytes of IO "
+ "allocated after remove operation.\n",
+ __func__, viodev->cmo.allocated);
+ BUG();
+ }
+
+ /*
+ * Remove the device from the device list being maintained for
+ * CMO enabled devices.
+ */
+ list_for_each_entry(dev_ent, &vio_cmo.device_list, list)
+ if (viodev =3D=3D dev_ent->viodev) {
+ list_del(&dev_ent->list);
+ kfree(dev_ent);
+ break;
+ }
+
+ /*
+ * Devices may not require any entitlement and they do not need
+ * to be processed. Otherwise, return the device's entitlement
+ * back to the pools.
+ */
+ if (viodev->cmo.entitled) {
+ /*
+ * This device has not yet left the OF tree, it's
+ * minimum entitlement remains in vio_cmo.min and
+ * vio_cmo.desired
+ */
+ vio_cmo.desired -=3D (viodev->cmo.desired - VIO_CMO_MIN_ENT);
+
+ /*
+ * Save min allocation for device in reserve as long
+ * as it exists in OF tree as determined by later
+ * balance operation
+ */
+ viodev->cmo.entitled -=3D VIO_CMO_MIN_ENT;
+
+ /* Replenish spare from freed reserve pool */
+ if (viodev->cmo.entitled && (vio_cmo.spare < VIO_CMO_MIN_ENT)) {
+ tmp =3D min(viodev->cmo.entitled, (VIO_CMO_MIN_ENT -
+ vio_cmo.spare));
+ vio_cmo.spare +=3D tmp;
+ viodev->cmo.entitled -=3D tmp;
+ }
+
+ /* Remaining reserve goes to excess pool */
+ vio_cmo.excess.size +=3D viodev->cmo.entitled;
+ vio_cmo.excess.free +=3D viodev->cmo.entitled;
+ vio_cmo.reserve.size -=3D viodev->cmo.entitled;
+
+ /*
+ * Until the device is removed it will keep a
+ * minimum entitlement; this will guarantee that
+ * a module unload/load will result in a success.
+ */
+ viodev->cmo.entitled =3D VIO_CMO_MIN_ENT;
+ viodev->cmo.desired =3D VIO_CMO_MIN_ENT;
+ atomic_set(&viodev->cmo.allocs_failed, 0);
+ }
+
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+}
+
+static void vio_cmo_set_dma_ops(struct vio_dev *viodev)
+{
+ vio_dma_mapping_ops.dma_supported =3D dma_iommu_ops.dma_supported;
+ viodev->dev.archdata.dma_ops =3D &vio_dma_mapping_ops;
+}
+
+/**
+ * vio_cmo_bus_init - CMO entitlement initialization at bus init time
+ *
+ * Set up the reserve and excess entitlement pools based on available
+ * system entitlement and the number of devices in the OF tree that
+ * require entitlement in the reserve pool.
+ */
+static void vio_cmo_bus_init(void)
+{
+ struct hvcall_mpp_data mpp_data;
+ int err;
+
+ memset(&vio_cmo, 0, sizeof(struct vio_cmo));
+ spin_lock_init(&vio_cmo.lock);
+ INIT_LIST_HEAD(&vio_cmo.device_list);
+ INIT_DELAYED_WORK(&vio_cmo.balance_q, vio_cmo_balance);
+
+ /* Get current system entitlement */
+ err =3D h_get_mpp(&mpp_data);
+
+ /*
+ * On failure, continue with entitlement set to 0, will panic()
+ * later when spare is reserved.
+ */
+ if (err !=3D H_SUCCESS) {
+ printk(KERN_ERR "%s: unable to determine system IO "\
+ "entitlement. (%d)\n", __func__, err);
+ vio_cmo.entitled =3D 0;
+ } else {
+ vio_cmo.entitled =3D mpp_data.entitled_mem;
+ }
+
+ /* Set reservation and check against entitlement */
+ vio_cmo.spare =3D VIO_CMO_MIN_ENT;
+ vio_cmo.reserve.size =3D vio_cmo.spare;
+ vio_cmo.reserve.size +=3D (vio_cmo_num_OF_devs() *
+ VIO_CMO_MIN_ENT);
+ if (vio_cmo.reserve.size > vio_cmo.entitled) {
+ printk(KERN_ERR "%s: insufficient system entitlement\n",
+ __func__);
+ panic("%s: Insufficient system entitlement", __func__);
+ }
+
+ /* Set the remaining accounting variables */
+ vio_cmo.excess.size =3D vio_cmo.entitled - vio_cmo.reserve.size;
+ vio_cmo.excess.free =3D vio_cmo.excess.size;
+ vio_cmo.min =3D vio_cmo.reserve.size;
+ vio_cmo.desired =3D vio_cmo.reserve.size;
+}
+
+/* sysfs device functions and data structures for CMO */
+
+#define viodev_cmo_rd_attr(name) \
+static ssize_t viodev_cmo_##name##_show(struct device *dev, \
+ struct device_attribute *attr, \
+ char *buf) \
+{ \
+ return sprintf(buf, "%lu\n", to_vio_dev(dev)->cmo.name); \
+}
+
+static ssize_t viodev_cmo_allocs_failed_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+ return sprintf(buf, "%d\n", atomic_read(&viodev->cmo.allocs_failed));
+}
+
+static ssize_t viodev_cmo_allocs_failed_reset(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+ atomic_set(&viodev->cmo.allocs_failed, 0);
+ return count;
+}
+
+static ssize_t viodev_cmo_desired_set(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ struct vio_dev *viodev =3D to_vio_dev(dev);
+ size_t new_desired;
+ int ret;
+
+ ret =3D strict_strtoul(buf, 10, &new_desired);
+ if (ret)
+ return ret;
+
+ vio_cmo_set_dev_desired(viodev, new_desired);
+ return count;
+}
+
+viodev_cmo_rd_attr(desired);
+viodev_cmo_rd_attr(entitled);
+viodev_cmo_rd_attr(allocated);
+
+static ssize_t name_show(struct device *, struct device_attribute *, char =
*);
+static ssize_t devspec_show(struct device *, struct device_attribute *, ch=
ar *);
+static struct device_attribute vio_cmo_dev_attrs[] =3D {
+ __ATTR_RO(name),
+ __ATTR_RO(devspec),
+ __ATTR(cmo_desired, S_IWUSR|S_IRUSR|S_IWGRP|S_IRGRP|S_IROTH,
+ viodev_cmo_desired_show, viodev_cmo_desired_set),
+ __ATTR(cmo_entitled, S_IRUGO, viodev_cmo_entitled_show, NULL),
+ __ATTR(cmo_allocated, S_IRUGO, viodev_cmo_allocated_show, NULL),
+ __ATTR(cmo_allocs_failed, S_IWUSR|S_IRUSR|S_IWGRP|S_IRGRP|S_IROTH,
+ viodev_cmo_allocs_failed_show, viodev_cmo_allocs_failed_reset),
+ __ATTR_NULL
+};
+
+/* sysfs bus functions and data structures for CMO */
+
+#define viobus_cmo_rd_attr(name) \
+static ssize_t \
+viobus_cmo_##name##_show(struct bus_type *bt, char *buf) \
+{ \
+ return sprintf(buf, "%lu\n", vio_cmo.name); \
+}
+
+#define viobus_cmo_pool_rd_attr(name, var) \
+static ssize_t \
+viobus_cmo_##name##_pool_show_##var(struct bus_type *bt, char *buf) \
+{ \
+ return sprintf(buf, "%lu\n", vio_cmo.name.var); \
+}
+
+static ssize_t viobus_cmo_high_reset(struct bus_type *bt, const char *buf,
+ size_t count)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&vio_cmo.lock, flags);
+ vio_cmo.high =3D vio_cmo.curr;
+ spin_unlock_irqrestore(&vio_cmo.lock, flags);
+
+ return count;
+}
+
+viobus_cmo_rd_attr(entitled);
+viobus_cmo_pool_rd_attr(reserve, size);
+viobus_cmo_pool_rd_attr(excess, size);
+viobus_cmo_pool_rd_attr(excess, free);
+viobus_cmo_rd_attr(spare);
+viobus_cmo_rd_attr(min);
+viobus_cmo_rd_attr(desired);
+viobus_cmo_rd_attr(curr);
+viobus_cmo_rd_attr(high);
+
+static struct bus_attribute vio_cmo_bus_attrs[] =3D {
+ __ATTR(cmo_entitled, S_IRUGO, viobus_cmo_entitled_show, NULL),
+ __ATTR(cmo_reserve_size, S_IRUGO, viobus_cmo_reserve_pool_show_size, NULL=
),
+ __ATTR(cmo_excess_size, S_IRUGO, viobus_cmo_excess_pool_show_size, NULL),
+ __ATTR(cmo_excess_free, S_IRUGO, viobus_cmo_excess_pool_show_free, NULL),
+ __ATTR(cmo_spare, S_IRUGO, viobus_cmo_spare_show, NULL),
+ __ATTR(cmo_min, S_IRUGO, viobus_cmo_min_show, NULL),
+ __ATTR(cmo_desired, S_IRUGO, viobus_cmo_desired_show, NULL),
+ __ATTR(cmo_curr, S_IRUGO, viobus_cmo_curr_show, NULL),
+ __ATTR(cmo_high, S_IWUSR|S_IRUSR|S_IWGRP|S_IRGRP|S_IROTH,
+ viobus_cmo_high_show, viobus_cmo_high_reset),
+ __ATTR_NULL
+};
+
+static void vio_cmo_sysfs_init(void)
+{
+ vio_bus_type.dev_attrs =3D vio_cmo_dev_attrs;
+ vio_bus_type.bus_attrs =3D vio_cmo_bus_attrs;
+}
+#else /* CONFIG_PPC_PSERIES */
+/* Dummy functions for iSeries platform */
+int vio_cmo_entitlement_update(size_t new_entitlement) { return 0; }
+void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired) {}
+static int vio_cmo_bus_probe(struct vio_dev *viodev) { return 0; }
+static void vio_cmo_bus_remove(struct vio_dev *viodev) {}
+static void vio_cmo_set_dma_ops(struct vio_dev *viodev) {}
+static void vio_cmo_bus_init() {}
+static void vio_cmo_sysfs_init() { }
+#endif /* CONFIG_PPC_PSERIES */
+EXPORT_SYMBOL(vio_cmo_entitlement_update);
+EXPORT_SYMBOL(vio_cmo_set_dev_desired);
+
static struct iommu_table *vio_build_iommu_table(struct vio_dev *dev)
{
const unsigned char *dma_window;
@@ -114,8 +1096,17 @@ static int vio_bus_probe(struct device *
return error;
=20
id =3D vio_match_device(viodrv->id_table, viodev);
- if (id)
+ if (id) {
+ memset(&viodev->cmo, 0, sizeof(viodev->cmo));
+ if (firmware_has_feature(FW_FEATURE_CMO)) {
+ error =3D vio_cmo_bus_probe(viodev);
+ if (error)
+ return error;
+ }
error =3D viodrv->probe(viodev, id);
+ if (error)
+ vio_cmo_bus_remove(viodev);
+ }
=20
return error;
}
@@ -125,12 +1116,23 @@ static int vio_bus_remove(struct device=20
{
struct vio_dev *viodev =3D to_vio_dev(dev);
struct vio_driver *viodrv =3D to_vio_driver(dev->driver);
+ struct device *devptr;
+ int ret =3D 1;
+
+ /*
+ * Hold a reference to the device after the remove function is called
+ * to allow for CMO accounting cleanup for the device.
+ */
+ devptr =3D get_device(dev);
=20
if (viodrv->remove)
- return viodrv->remove(viodev);
+ ret =3D viodrv->remove(viodev);
=20
- /* driver can't remove */
- return 1;
+ if (!ret && firmware_has_feature(FW_FEATURE_CMO))
+ vio_cmo_bus_remove(viodev);
+
+ put_device(devptr);
+ return ret;
}
=20
/**
@@ -215,7 +1217,11 @@ struct vio_dev *vio_register_device_node
viodev->unit_address =3D *unit_address;
}
viodev->dev.archdata.of_node =3D of_node_get(of_node);
- viodev->dev.archdata.dma_ops =3D &dma_iommu_ops;
+
+ if (firmware_has_feature(FW_FEATURE_CMO))
+ vio_cmo_set_dma_ops(viodev);
+ else
+ viodev->dev.archdata.dma_ops =3D &dma_iommu_ops;
viodev->dev.archdata.dma_data =3D vio_build_iommu_table(viodev);
viodev->dev.archdata.numa_node =3D of_node_to_nid(of_node);
=20
@@ -245,6 +1251,9 @@ static int __init vio_bus_init(void)
int err;
struct device_node *node_vroot;
=20
+ if (firmware_has_feature(FW_FEATURE_CMO))
+ vio_cmo_sysfs_init();
+
err =3D bus_register(&vio_bus_type);
if (err) {
printk(KERN_ERR "failed to register VIO bus\n");
@@ -262,6 +1271,9 @@ static int __init vio_bus_init(void)
return err;
}
=20
+ if (firmware_has_feature(FW_FEATURE_CMO))
+ vio_cmo_bus_init();
+
node_vroot =3D of_find_node_by_name(NULL, "vdevice");
if (node_vroot) {
struct device_node *of_node;
Index: b/include/asm-powerpc/vio.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--- a/include/asm-powerpc/vio.h
+++ b/include/asm-powerpc/vio.h
@@ -39,16 +39,32 @@
#define VIO_IRQ_DISABLE 0UL
#define VIO_IRQ_ENABLE 1UL
=20
+/*
+ * VIO CMO minimum entitlement for all devices and spare entitlement
+ */
+#define VIO_CMO_MIN_ENT 1562624
+
struct iommu_table;
=20
-/*
- * The vio_dev structure is used to describe virtual I/O devices.
+/**
+ * vio_dev - This structure is used to describe virtual I/O devices.
+ *
+ * @desired: set from return of driver's get_desired_dma() function
+ * @entitled: bytes of IO data that has been reserved for this device.
+ * @allocated: bytes of IO data currently in use by the device.
+ * @allocs_failed: number of DMA failures due to insufficient entitlement.
*/
struct vio_dev {
const char *name;
const char *type;
uint32_t unit_address;
unsigned int irq;
+ struct {
+ size_t desired;
+ size_t entitled;
+ size_t allocated;
+ atomic_t allocs_failed;
+ } cmo;
struct device dev;
};
=20
@@ -56,12 +72,19 @@ struct vio_driver {
const struct vio_device_id *id_table;
int (*probe)(struct vio_dev *dev, const struct vio_device_id *id);
int (*remove)(struct vio_dev *dev);
+ /* A driver must have a get_desired_dma() function to
+ * be loaded in a CMO environment if it uses DMA.
+ */
+ unsigned long (*get_desired_dma)(struct vio_dev *dev);
struct device_driver driver;
};
=20
extern int vio_register_driver(struct vio_driver *drv);
extern void vio_unregister_driver(struct vio_driver *drv);
=20
+extern int vio_cmo_entitlement_update(size_t);
+extern void vio_cmo_set_dev_desired(struct vio_dev *viodev, size_t desired=
);
+
extern void __devinit vio_unregister_device(struct vio_dev *dev);
=20
struct device_node;
^ permalink raw reply
* Re: While(1) in kernel space
From: Paolo Doz @ 2008-07-08 20:53 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <fa686aa40807080747u3e1f4f57of1a2cddc67b446b9@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 888 bytes --]
Thanks for the infos, I'll try kernel thread or timer/softirq in the next
days.
I'll let you know which of them fit my problems.
I actually have about +/- 1msec of freedom (but still require more
investigation).
Paolo
On Tue, Jul 8, 2008 at 4:47 PM, Grant Likely <grant.likely@secretlab.ca>
wrote:
> On Tue, Jul 8, 2008 at 8:45 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Tuesday 08 July 2008, Grant Likely wrote:
> >
> >>
> >> You can use a kernel thread.
> >>
> >> I'm not sure how accurate this is, but here is some information about
> them:
> >>
> >>
> http://www.linuxquestions.org/linux/articles/Technical/Linux_Kernel_Thread
> >
> > Not accurate at all. New code should use kthread_create, as documented in
> >
> > http://lwn.net/Articles/65178/
>
> Teach me to blindly use google. Thanks Arnd.
>
> g.
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>
[-- Attachment #2: Type: text/html, Size: 1539 bytes --]
^ permalink raw reply
* Re: linux-next: kbuild tree build failure
From: Sam Ravnborg @ 2008-07-08 21:19 UTC (permalink / raw)
To: Roman Zippel; +Cc: Stephen Rothwell, linux-next, Paul Mackerras, linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0807071424240.6791@localhost.localdomain>
Hi Roman.
I thought a bit more about this.
> I should have gone through all archs to test this, sorry about that.
> Luckily it's only powerpc that uses 64bit values. I would prefer to
> standardize on 32bit values, as it doesn't really make sense to expect
> from the user to input full 64bit values and it's easy to generate the
> full value in a header.
We use Kconfig for a mixture of user editable values and fixed
configuration values.
And I agree that asking the user to input a 64 bit number is not usefull.
But keeping support for 64 bit values is what I would consider
expected functionality.
So removing support for 64 bit is not good IMO.
> This would also ease on any portability issues
> (kconfig is compiled with the host compiler not the target compiler).
We use strtol() in a few places in symbol.c already where we do an
implicit conversion to int. Why did this not cause us problems before?
Is it because these code paths are only triggered when we deal with ranges?
If so we could 'fix' strdup_type() to not use strto{,u}l() so it
is 64 bit clean and we are back to old behaviour.
Sam
^ permalink raw reply
* Re: [PATCH v2] Add PPC_FEATURE_PSERIES_PMU_COMPAT
From: Kumar Gala @ 2008-07-08 22:05 UTC (permalink / raw)
To: Nathan Lynch; +Cc: Olof Johansson, linuxppc-dev, Paul Mackerras
In-Reply-To: <20080708200137.GN9594@localdomain>
On Jul 8, 2008, at 3:01 PM, Nathan Lynch wrote:
> Background from Maynard Johnson:
> As of POWER6, a set of 32 common events is defined that must be
> supported on all future POWER processors. The main impetus for this
> compat set is the need to support partition migration, especially from
> processor P(n) to processor P(n+1), where performance software that's
> running in the new partition may not be knowledgeable about processor
> P(n+1). If a performance tool determines it does not support the
> physical processor, but is told (via the
> PPC_FEATURE_PSERIES_PMU_COMPAT
> bit) that the processor supports the notion of the PMU compat set,
> then the performance tool can surface just those events to the user
> of the tool.
>
> PPC_FEATURE_PSERIES_PMU_COMPAT indicates that the PMU supports at
> least this basic subset of events which is compatible across POWER
> processor lines.
>
> Signed-off-by: Nathan Lynch <ntl@pobox.com>
> ---
So is PMU here performance monitor unit? I think that was part of my
confusion earlier. I was thinking Power Mgmt Unit (like on Apple HW).
I hate make the name longer, but PPC_FEATURE_PSERIES_PERFMON_COMPAT
would probably be clearer.
- k
^ permalink raw reply
* [PATCH] powerpc/fsl: Refactor device bindings
From: Kumar Gala @ 2008-07-08 22:08 UTC (permalink / raw)
To: linuxppc-dev
Moved Freescale SoC related bindings out of booting-without-of.txt and into
their own files.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
We need to resolve some conflicts in cpm.txt and qe.txt but that will be a
followup patch.
- k
Documentation/powerpc/booting-without-of.txt | 1218 +-------------------
Documentation/powerpc/dts-bindings/fsl/board.txt | 29 +
.../powerpc/dts-bindings/fsl/cpm_qe/cpm.txt | 67 ++
.../powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt | 21 +
.../powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt | 41 +
.../powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt | 18 +
.../powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt | 15 +
.../powerpc/dts-bindings/fsl/cpm_qe/network.txt | 45 +
.../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 58 +
.../dts-bindings/fsl/cpm_qe/qe/firmware.txt | 24 +
.../powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt | 51 +
.../powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt | 60 +
.../powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt | 70 ++
.../powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt | 22 +
.../powerpc/dts-bindings/fsl/cpm_qe/serial.txt | 21 +
Documentation/powerpc/dts-bindings/fsl/diu.txt | 18 +
Documentation/powerpc/dts-bindings/fsl/dma.txt | 127 ++
Documentation/powerpc/dts-bindings/fsl/gtm.txt | 31 +
Documentation/powerpc/dts-bindings/fsl/guts.txt | 25 +
Documentation/powerpc/dts-bindings/fsl/i2c.txt | 32 +
Documentation/powerpc/dts-bindings/fsl/lbc.txt | 35 +
Documentation/powerpc/dts-bindings/fsl/msi-pic.txt | 36 +
Documentation/powerpc/dts-bindings/fsl/sata.txt | 29 +
Documentation/powerpc/dts-bindings/fsl/spi.txt | 24 +
Documentation/powerpc/dts-bindings/fsl/ssi.txt | 38 +
Documentation/powerpc/dts-bindings/fsl/tsec.txt | 69 ++
Documentation/powerpc/dts-bindings/fsl/usb.txt | 59 +
27 files changed, 1077 insertions(+), 1206 deletions(-)
create mode 100644 Documentation/powerpc/dts-bindings/fsl/board.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/diu.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/dma.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/gtm.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/guts.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/i2c.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/lbc.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/sata.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/spi.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/ssi.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/tsec.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/usb.txt
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index f6394b5..de2e5c0 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -41,27 +41,12 @@ Table of Contents
VI - System-on-a-chip devices and nodes
1) Defining child nodes of an SOC
2) Representing devices without a current OF specification
- a) MDIO IO device
- b) Gianfar-compatible ethernet nodes
- c) PHY nodes
- d) Interrupt controllers
- e) I2C
- f) Freescale SOC USB controllers
- g) Freescale SOC SEC Security Engines
- h) Board Control and Status (BCSR)
- i) Freescale QUICC Engine module (QE)
- j) CFI or JEDEC memory-mapped NOR flash
- k) Global Utilities Block
- l) Freescale Communications Processor Module
- m) Chipselect/Local Bus
- n) 4xx/Axon EMAC ethernet nodes
- o) Xilinx IP cores
- p) Freescale Synchronous Serial Interface
- q) USB EHCI controllers
- r) Freescale Display Interface Unit
- s) Freescale on board FPGA
- t) Freescael MSI interrupt controller
- u) Freescale General-purpose Timers Module
+ a) PHY nodes
+ b) Interrupt controllers
+ c) CFI or JEDEC memory-mapped NOR flash
+ d) 4xx/Axon EMAC ethernet nodes
+ e) Xilinx IP cores
+ f) USB EHCI controllers
VII - Marvell Discovery mv64[345]6x System Controller chips
1) The /system-controller node
@@ -1250,80 +1235,7 @@ descriptions for the SOC devices for which new nodes have been
defined; this list will expand as more and more SOC-containing
platforms are moved over to use the flattened-device-tree model.
- a) MDIO IO device
-
- The MDIO is a bus to which the PHY devices are connected. For each
- device that exists on this bus, a child node should be created. See
- the definition of the PHY node below for an example of how to define
- a PHY.
-
- Required properties:
- - reg : Offset and length of the register set for the device
- - compatible : Should define the compatible device type for the
- mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
-
- Example:
-
- mdio@24520 {
- reg = <24520 20>;
- compatible = "fsl,gianfar-mdio";
-
- ethernet-phy@0 {
- ......
- };
- };
-
-
- b) Gianfar-compatible ethernet nodes
-
- Required properties:
-
- - device_type : Should be "network"
- - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
- - compatible : Should be "gianfar"
- - reg : Offset and length of the register set for the device
- - mac-address : List of bytes representing the ethernet address of
- this controller
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
- - phy-handle : The phandle for the PHY connected to this ethernet
- controller.
- - fixed-link : <a b c d e> where a is emulated phy id - choose any,
- but unique to the all specified fixed-links, b is duplex - 0 half,
- 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
- pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
-
- Recommended properties:
-
- - phy-connection-type : a string naming the controller/PHY interface type,
- i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
- "tbi", or "rtbi". This property is only really needed if the connection
- is of type "rgmii-id", as all other connection types are detected by
- hardware.
-
-
- Example:
-
- ethernet@24000 {
- #size-cells = <0>;
- device_type = "network";
- model = "TSEC";
- compatible = "gianfar";
- reg = <24000 1000>;
- mac-address = [ 00 E0 0C 00 73 00 ];
- interrupts = <d 3 e 3 12 3>;
- interrupt-parent = <40000>;
- phy-handle = <2452000>
- };
-
-
-
- c) PHY nodes
+ a) PHY nodes
Required properties:
@@ -1351,7 +1263,7 @@ platforms are moved over to use the flattened-device-tree model.
};
- d) Interrupt controllers
+ b) Interrupt controllers
Some SOC devices contain interrupt controllers that are different
from the standard Open PIC specification. The SOC device nodes for
@@ -1371,508 +1283,7 @@ platforms are moved over to use the flattened-device-tree model.
device_type = "open-pic";
};
-
- e) I2C
-
- Required properties :
-
- - device_type : Should be "i2c"
- - reg : Offset and length of the register set for the device
-
- Recommended properties :
-
- - compatible : Should be "fsl-i2c" for parts compatible with
- Freescale I2C specifications.
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
- - dfsrr : boolean; if defined, indicates that this I2C device has
- a digital filter sampling rate register
- - fsl5200-clocking : boolean; if defined, indicated that this device
- uses the FSL 5200 clocking mechanism.
-
- Example :
-
- i2c@3000 {
- interrupt-parent = <40000>;
- interrupts = <1b 3>;
- reg = <3000 18>;
- device_type = "i2c";
- compatible = "fsl-i2c";
- dfsrr;
- };
-
-
- f) Freescale SOC USB controllers
-
- The device node for a USB controller that is part of a Freescale
- SOC is as described in the document "Open Firmware Recommended
- Practice : Universal Serial Bus" with the following modifications
- and additions :
-
- Required properties :
- - compatible : Should be "fsl-usb2-mph" for multi port host USB
- controllers, or "fsl-usb2-dr" for dual role USB controllers
- - phy_type : For multi port host USB controllers, should be one of
- "ulpi", or "serial". For dual role USB controllers, should be
- one of "ulpi", "utmi", "utmi_wide", or "serial".
- - reg : Offset and length of the register set for the device
- - port0 : boolean; if defined, indicates port0 is connected for
- fsl-usb2-mph compatible controllers. Either this property or
- "port1" (or both) must be defined for "fsl-usb2-mph" compatible
- controllers.
- - port1 : boolean; if defined, indicates port1 is connected for
- fsl-usb2-mph compatible controllers. Either this property or
- "port0" (or both) must be defined for "fsl-usb2-mph" compatible
- controllers.
- - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
- controllers. Can be "host", "peripheral", or "otg". Default to
- "host" if not defined for backward compatibility.
-
- Recommended properties :
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
-
- Example multi port host USB controller device node :
- usb@22000 {
- compatible = "fsl-usb2-mph";
- reg = <22000 1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <700>;
- interrupts = <27 1>;
- phy_type = "ulpi";
- port0;
- port1;
- };
-
- Example dual role USB controller device node :
- usb@23000 {
- compatible = "fsl-usb2-dr";
- reg = <23000 1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <700>;
- interrupts = <26 1>;
- dr_mode = "otg";
- phy = "ulpi";
- };
-
-
- g) Freescale SOC SEC Security Engines
-
- Required properties:
-
- - device_type : Should be "crypto"
- - model : Model of the device. Should be "SEC1" or "SEC2"
- - compatible : Should be "talitos"
- - reg : Offset and length of the register set for the device
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
- - num-channels : An integer representing the number of channels
- available.
- - channel-fifo-len : An integer representing the number of
- descriptor pointers each channel fetch fifo can hold.
- - exec-units-mask : The bitmask representing what execution units
- (EUs) are available. It's a single 32-bit cell. EU information
- should be encoded following the SEC's Descriptor Header Dword
- EU_SEL0 field documentation, i.e. as follows:
-
- bit 0 = reserved - should be 0
- bit 1 = set if SEC has the ARC4 EU (AFEU)
- bit 2 = set if SEC has the DES/3DES EU (DEU)
- bit 3 = set if SEC has the message digest EU (MDEU)
- bit 4 = set if SEC has the random number generator EU (RNG)
- bit 5 = set if SEC has the public key EU (PKEU)
- bit 6 = set if SEC has the AES EU (AESU)
- bit 7 = set if SEC has the Kasumi EU (KEU)
-
- bits 8 through 31 are reserved for future SEC EUs.
-
- - descriptor-types-mask : The bitmask representing what descriptors
- are available. It's a single 32-bit cell. Descriptor type
- information should be encoded following the SEC's Descriptor
- Header Dword DESC_TYPE field documentation, i.e. as follows:
-
- bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
- bit 1 = set if SEC supports the ipsec_esp descriptor type
- bit 2 = set if SEC supports the common_nonsnoop desc. type
- bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
- bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
- bit 5 = set if SEC supports the srtp descriptor type
- bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
- bit 7 = set if SEC supports the pkeu_assemble descriptor type
- bit 8 = set if SEC supports the aesu_key_expand_output desc.type
- bit 9 = set if SEC supports the pkeu_ptmul descriptor type
- bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
- bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
-
- ..and so on and so forth.
-
- Example:
-
- /* MPC8548E */
- crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
- reg = <30000 10000>;
- interrupts = <1d 3>;
- interrupt-parent = <40000>;
- num-channels = <4>;
- channel-fifo-len = <18>;
- exec-units-mask = <000000fe>;
- descriptor-types-mask = <012b0ebf>;
- };
-
- h) Board Control and Status (BCSR)
-
- Required properties:
-
- - device_type : Should be "board-control"
- - reg : Offset and length of the register set for the device
-
- Example:
-
- bcsr@f8000000 {
- device_type = "board-control";
- reg = <f8000000 8000>;
- };
-
- i) Freescale QUICC Engine module (QE)
- This represents qe module that is installed on PowerQUICC II Pro.
-
- NOTE: This is an interim binding; it should be updated to fit
- in with the CPM binding later in this document.
-
- Basically, it is a bus of devices, that could act more or less
- as a complete entity (UCC, USB etc ). All of them should be siblings on
- the "root" qe node, using the common properties from there.
- The description below applies to the qe of MPC8360 and
- more nodes and properties would be extended in the future.
-
- i) Root QE device
-
- Required properties:
- - compatible : should be "fsl,qe";
- - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
- - reg : offset and length of the device registers.
- - bus-frequency : the clock frequency for QUICC Engine.
-
- Recommended properties
- - brg-frequency : the internal clock source frequency for baud-rate
- generators in Hz.
-
- Example:
- qe@e0100000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- compatible = "fsl,qe";
- ranges = <0 e0100000 00100000>;
- reg = <e0100000 480>;
- brg-frequency = <0>;
- bus-frequency = <179A7B00>;
- }
-
-
- ii) SPI (Serial Peripheral Interface)
-
- Required properties:
- - cell-index : SPI controller index.
- - compatible : should be "fsl,spi".
- - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
- - reg : Offset and length of the register set for the device
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
-
- Example:
- spi@4c0 {
- cell-index = <0>;
- compatible = "fsl,spi";
- reg = <4c0 40>;
- interrupts = <82 0>;
- interrupt-parent = <700>;
- mode = "cpu";
- };
-
-
- iii) USB (Universal Serial Bus Controller)
-
- Required properties:
- - compatible : could be "qe_udc" or "fhci-hcd".
- - mode : the could be "host" or "slave".
- - reg : Offset and length of the register set for the device
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
-
- Example(slave):
- usb@6c0 {
- compatible = "qe_udc";
- reg = <6c0 40>;
- interrupts = <8b 0>;
- interrupt-parent = <700>;
- mode = "slave";
- };
-
-
- iv) UCC (Unified Communications Controllers)
-
- Required properties:
- - device_type : should be "network", "hldc", "uart", "transparent"
- "bisync", "atm", or "serial".
- - compatible : could be "ucc_geth" or "fsl_atm" and so on.
- - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
- - reg : Offset and length of the register set for the device
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and level
- information for the interrupt. This should be encoded based on
- the information in section 2) depending on the type of interrupt
- controller you have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
- - pio-handle : The phandle for the Parallel I/O port configuration.
- - port-number : for UART drivers, the port number to use, between 0 and 3.
- This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
- The port number is added to the minor number of the device. Unlike the
- CPM UART driver, the port-number is required for the QE UART driver.
- - soft-uart : for UART drivers, if specified this means the QE UART device
- driver should use "Soft-UART" mode, which is needed on some SOCs that have
- broken UART hardware. Soft-UART is provided via a microcode upload.
- - rx-clock-name: the UCC receive clock source
- "none": clock source is disabled
- "brg1" through "brg16": clock source is BRG1-BRG16, respectively
- "clk1" through "clk24": clock source is CLK1-CLK24, respectively
- - tx-clock-name: the UCC transmit clock source
- "none": clock source is disabled
- "brg1" through "brg16": clock source is BRG1-BRG16, respectively
- "clk1" through "clk24": clock source is CLK1-CLK24, respectively
- The following two properties are deprecated. rx-clock has been replaced
- with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
- Drivers that currently use the deprecated properties should continue to
- do so, in order to support older device trees, but they should be updated
- to check for the new properties first.
- - rx-clock : represents the UCC receive clock source.
- 0x00 : clock source is disabled;
- 0x1~0x10 : clock source is BRG1~BRG16 respectively;
- 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
- - tx-clock: represents the UCC transmit clock source;
- 0x00 : clock source is disabled;
- 0x1~0x10 : clock source is BRG1~BRG16 respectively;
- 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
-
- Required properties for network device_type:
- - mac-address : list of bytes representing the ethernet address.
- - phy-handle : The phandle for the PHY connected to this controller.
-
- Recommended properties:
- - phy-connection-type : a string naming the controller/PHY interface type,
- i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
- Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
- "tbi", or "rtbi".
-
- Example:
- ucc@2000 {
- device_type = "network";
- compatible = "ucc_geth";
- cell-index = <1>;
- reg = <2000 200>;
- interrupts = <a0 0>;
- interrupt-parent = <700>;
- mac-address = [ 00 04 9f 00 23 23 ];
- rx-clock = "none";
- tx-clock = "clk9";
- phy-handle = <212000>;
- phy-connection-type = "gmii";
- pio-handle = <140001>;
- };
-
-
- v) Parallel I/O Ports
-
- This node configures Parallel I/O ports for CPUs with QE support.
- The node should reside in the "soc" node of the tree. For each
- device that using parallel I/O ports, a child node should be created.
- See the definition of the Pin configuration nodes below for more
- information.
-
- Required properties:
- - device_type : should be "par_io".
- - reg : offset to the register set and its length.
- - num-ports : number of Parallel I/O ports
-
- Example:
- par_io@1400 {
- reg = <1400 100>;
- #address-cells = <1>;
- #size-cells = <0>;
- device_type = "par_io";
- num-ports = <7>;
- ucc_pin@01 {
- ......
- };
-
- Note that "par_io" nodes are obsolete, and should not be used for
- the new device trees. Instead, each Par I/O bank should be represented
- via its own gpio-controller node:
-
- Required properties:
- - #gpio-cells : should be "2".
- - compatible : should be "fsl,<chip>-qe-pario-bank",
- "fsl,mpc8323-qe-pario-bank".
- - reg : offset to the register set and its length.
- - gpio-controller : node to identify gpio controllers.
-
- Example:
- qe_pio_a: gpio-controller@1400 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8360-qe-pario-bank",
- "fsl,mpc8323-qe-pario-bank";
- reg = <0x1400 0x18>;
- gpio-controller;
- };
-
- qe_pio_e: gpio-controller@1460 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8360-qe-pario-bank",
- "fsl,mpc8323-qe-pario-bank";
- reg = <0x1460 0x18>;
- gpio-controller;
- };
-
- vi) Pin configuration nodes
-
- Required properties:
- - linux,phandle : phandle of this node; likely referenced by a QE
- device.
- - pio-map : array of pin configurations. Each pin is defined by 6
- integers. The six numbers are respectively: port, pin, dir,
- open_drain, assignment, has_irq.
- - port : port number of the pin; 0-6 represent port A-G in UM.
- - pin : pin number in the port.
- - dir : direction of the pin, should encode as follows:
-
- 0 = The pin is disabled
- 1 = The pin is an output
- 2 = The pin is an input
- 3 = The pin is I/O
-
- - open_drain : indicates the pin is normal or wired-OR:
-
- 0 = The pin is actively driven as an output
- 1 = The pin is an open-drain driver. As an output, the pin is
- driven active-low, otherwise it is three-stated.
-
- - assignment : function number of the pin according to the Pin Assignment
- tables in User Manual. Each pin can have up to 4 possible functions in
- QE and two options for CPM.
- - has_irq : indicates if the pin is used as source of external
- interrupts.
-
- Example:
- ucc_pin@01 {
- linux,phandle = <140001>;
- pio-map = <
- /* port pin dir open_drain assignment has_irq */
- 0 3 1 0 1 0 /* TxD0 */
- 0 4 1 0 1 0 /* TxD1 */
- 0 5 1 0 1 0 /* TxD2 */
- 0 6 1 0 1 0 /* TxD3 */
- 1 6 1 0 3 0 /* TxD4 */
- 1 7 1 0 1 0 /* TxD5 */
- 1 9 1 0 2 0 /* TxD6 */
- 1 a 1 0 2 0 /* TxD7 */
- 0 9 2 0 1 0 /* RxD0 */
- 0 a 2 0 1 0 /* RxD1 */
- 0 b 2 0 1 0 /* RxD2 */
- 0 c 2 0 1 0 /* RxD3 */
- 0 d 2 0 1 0 /* RxD4 */
- 1 1 2 0 2 0 /* RxD5 */
- 1 0 2 0 2 0 /* RxD6 */
- 1 4 2 0 2 0 /* RxD7 */
- 0 7 1 0 1 0 /* TX_EN */
- 0 8 1 0 1 0 /* TX_ER */
- 0 f 2 0 1 0 /* RX_DV */
- 0 10 2 0 1 0 /* RX_ER */
- 0 0 2 0 1 0 /* RX_CLK */
- 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
- 2 8 2 0 1 0>; /* GTX125 - CLK9 */
- };
-
- vii) Multi-User RAM (MURAM)
-
- Required properties:
- - compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
- - mode : the could be "host" or "slave".
- - ranges : Should be defined as specified in 1) to describe the
- translation of MURAM addresses.
- - data-only : sub-node which defines the address area under MURAM
- bus that can be allocated as data/parameter
-
- Example:
-
- muram@10000 {
- compatible = "fsl,qe-muram", "fsl,cpm-muram";
- ranges = <0 00010000 0000c000>;
-
- data-only@0{
- compatible = "fsl,qe-muram-data",
- "fsl,cpm-muram-data";
- reg = <0 c000>;
- };
- };
-
- viii) Uploaded QE firmware
-
- If a new firwmare has been uploaded to the QE (usually by the
- boot loader), then a 'firmware' child node should be added to the QE
- node. This node provides information on the uploaded firmware that
- device drivers may need.
-
- Required properties:
- - id: The string name of the firmware. This is taken from the 'id'
- member of the qe_firmware structure of the uploaded firmware.
- Device drivers can search this string to determine if the
- firmware they want is already present.
- - extended-modes: The Extended Modes bitfield, taken from the
- firmware binary. It is a 64-bit number represented
- as an array of two 32-bit numbers.
- - virtual-traps: The virtual traps, taken from the firmware binary.
- It is an array of 8 32-bit numbers.
-
- Example:
-
- firmware {
- id = "Soft-UART";
- extended-modes = <0 0>;
- virtual-traps = <0 0 0 0 0 0 0 0>;
- }
-
- j) CFI or JEDEC memory-mapped NOR flash
+ c) CFI or JEDEC memory-mapped NOR flash
Flash chips (Memory Technology Devices) are often used for solid state
file systems on embedded devices.
@@ -1936,310 +1347,7 @@ platforms are moved over to use the flattened-device-tree model.
};
};
- k) Global Utilities Block
-
- The global utilities block controls power management, I/O device
- enabling, power-on-reset configuration monitoring, general-purpose
- I/O signal configuration, alternate function selection for multiplexed
- signals, and clock control.
-
- Required properties:
-
- - compatible : Should define the compatible device type for
- global-utilities.
- - reg : Offset and length of the register set for the device.
-
- Recommended properties:
-
- - fsl,has-rstcr : Indicates that the global utilities register set
- contains a functioning "reset control register" (i.e. the board
- is wired to reset upon setting the HRESET_REQ bit in this register).
-
- Example:
-
- global-utilities@e0000 { /* global utilities block */
- compatible = "fsl,mpc8548-guts";
- reg = <e0000 1000>;
- fsl,has-rstcr;
- };
-
- l) Freescale Communications Processor Module
-
- NOTE: This is an interim binding, and will likely change slightly,
- as more devices are supported. The QE bindings especially are
- incomplete.
-
- i) Root CPM node
-
- Properties:
- - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
- - reg : A 48-byte region beginning with CPCR.
-
- Example:
- cpm@119c0 {
- #address-cells = <1>;
- #size-cells = <1>;
- #interrupt-cells = <2>;
- compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
- reg = <119c0 30>;
- }
-
- ii) Properties common to mulitple CPM/QE devices
-
- - fsl,cpm-command : This value is ORed with the opcode and command flag
- to specify the device on which a CPM command operates.
-
- - fsl,cpm-brg : Indicates which baud rate generator the device
- is associated with. If absent, an unused BRG
- should be dynamically allocated. If zero, the
- device uses an external clock rather than a BRG.
-
- - reg : Unless otherwise specified, the first resource represents the
- scc/fcc/ucc registers, and the second represents the device's
- parameter RAM region (if it has one).
-
- iii) Serial
-
- Currently defined compatibles:
- - fsl,cpm1-smc-uart
- - fsl,cpm2-smc-uart
- - fsl,cpm1-scc-uart
- - fsl,cpm2-scc-uart
- - fsl,qe-uart
-
- Example:
-
- serial@11a00 {
- device_type = "serial";
- compatible = "fsl,mpc8272-scc-uart",
- "fsl,cpm2-scc-uart";
- reg = <11a00 20 8000 100>;
- interrupts = <28 8>;
- interrupt-parent = <&PIC>;
- fsl,cpm-brg = <1>;
- fsl,cpm-command = <00800000>;
- };
-
- iii) Network
-
- Currently defined compatibles:
- - fsl,cpm1-scc-enet
- - fsl,cpm2-scc-enet
- - fsl,cpm1-fec-enet
- - fsl,cpm2-fcc-enet (third resource is GFEMR)
- - fsl,qe-enet
-
- Example:
-
- ethernet@11300 {
- device_type = "network";
- compatible = "fsl,mpc8272-fcc-enet",
- "fsl,cpm2-fcc-enet";
- reg = <11300 20 8400 100 11390 1>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <20 8>;
- interrupt-parent = <&PIC>;
- phy-handle = <&PHY0>;
- fsl,cpm-command = <12000300>;
- };
-
- iv) MDIO
-
- Currently defined compatibles:
- fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
- fsl,cpm2-mdio-bitbang (reg is port C registers)
-
- Properties for fsl,cpm2-mdio-bitbang:
- fsl,mdio-pin : pin of port C controlling mdio data
- fsl,mdc-pin : pin of port C controlling mdio clock
-
- Example:
-
- mdio@10d40 {
- device_type = "mdio";
- compatible = "fsl,mpc8272ads-mdio-bitbang",
- "fsl,mpc8272-mdio-bitbang",
- "fsl,cpm2-mdio-bitbang";
- reg = <10d40 14>;
- #address-cells = <1>;
- #size-cells = <0>;
- fsl,mdio-pin = <12>;
- fsl,mdc-pin = <13>;
- };
-
- v) Baud Rate Generators
-
- Currently defined compatibles:
- fsl,cpm-brg
- fsl,cpm1-brg
- fsl,cpm2-brg
-
- Properties:
- - reg : There may be an arbitrary number of reg resources; BRG
- numbers are assigned to these in order.
- - clock-frequency : Specifies the base frequency driving
- the BRG.
-
- Example:
-
- brg@119f0 {
- compatible = "fsl,mpc8272-brg",
- "fsl,cpm2-brg",
- "fsl,cpm-brg";
- reg = <119f0 10 115f0 10>;
- clock-frequency = <d#25000000>;
- };
-
- vi) Interrupt Controllers
-
- Currently defined compatibles:
- - fsl,cpm1-pic
- - only one interrupt cell
- - fsl,pq1-pic
- - fsl,cpm2-pic
- - second interrupt cell is level/sense:
- - 2 is falling edge
- - 8 is active low
-
- Example:
-
- interrupt-controller@10c00 {
- #interrupt-cells = <2>;
- interrupt-controller;
- reg = <10c00 80>;
- compatible = "mpc8272-pic", "fsl,cpm2-pic";
- };
-
- vii) USB (Universal Serial Bus Controller)
-
- Properties:
- - compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
-
- Example:
- usb@11bc0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,cpm2-usb";
- reg = <11b60 18 8b00 100>;
- interrupts = <b 8>;
- interrupt-parent = <&PIC>;
- fsl,cpm-command = <2e600000>;
- };
-
- viii) Multi-User RAM (MURAM)
-
- The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
-
- Ranges must be set up subject to the following restrictions:
-
- - Children's reg nodes must be offsets from the start of all muram, even
- if the user-data area does not begin at zero.
- - If multiple range entries are used, the difference between the parent
- address and the child address must be the same in all, so that a single
- mapping can cover them all while maintaining the ability to determine
- CPM-side offsets with pointer subtraction. It is recommended that
- multiple range entries not be used.
- - A child address of zero must be translatable, even if no reg resources
- contain it.
-
- A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
- indicate the portion of muram that is usable by the OS for arbitrary
- purposes. The data node may have an arbitrary number of reg resources,
- all of which contribute to the allocatable muram pool.
-
- Example, based on mpc8272:
-
- muram@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 10000>;
-
- data@0 {
- compatible = "fsl,cpm-muram-data";
- reg = <0 2000 9800 800>;
- };
- };
-
- x) I2C
-
- The I2C controller is expressed as a bus under the CPM node.
-
- Properties:
- - compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
- - reg : On CPM2 devices, the second resource doesn't specify the I2C
- Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
- (typically 0x8afc 0x2).
- - #address-cells : Should be one. The cell is the i2c device address with
- the r/w bit set to zero.
- - #size-cells : Should be zero.
- - clock-frequency : Can be used to set the i2c clock frequency. If
- unspecified, a default frequency of 60kHz is being used.
- The following two properties are deprecated. They are only used by legacy
- i2c drivers to find the bus to probe:
- - linux,i2c-index : Can be used to hard code an i2c bus number. By default,
- the bus number is dynamically assigned by the i2c core.
- - linux,i2c-class : Can be used to override the i2c class. The class is used
- by legacy i2c device drivers to find a bus in a specific context like
- system management, video or sound. By default, I2C_CLASS_HWMON (1) is
- being used. The definition of the classes can be found in
- include/i2c/i2c.h
-
- Example, based on mpc823:
-
- i2c@860 {
- compatible = "fsl,mpc823-i2c",
- "fsl,cpm1-i2c";
- reg = <0x860 0x20 0x3c80 0x30>;
- interrupts = <16>;
- interrupt-parent = <&CPM_PIC>;
- fsl,cpm-command = <0x10>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc@68 {
- compatible = "dallas,ds1307";
- reg = <0x68>;
- };
- };
-
- m) Chipselect/Local Bus
-
- Properties:
- - name : Should be localbus
- - #address-cells : Should be either two or three. The first cell is the
- chipselect number, and the remaining cells are the
- offset into the chipselect.
- - #size-cells : Either one or two, depending on how large each chipselect
- can be.
- - ranges : Each range corresponds to a single chipselect, and cover
- the entire access window as configured.
-
- Example:
- localbus@f0010100 {
- compatible = "fsl,mpc8272-localbus",
- "fsl,pq2-localbus";
- #address-cells = <2>;
- #size-cells = <1>;
- reg = <f0010100 40>;
-
- ranges = <0 0 fe000000 02000000
- 1 0 f4500000 00008000>;
-
- flash@0,0 {
- compatible = "jedec-flash";
- reg = <0 0 2000000>;
- bank-width = <4>;
- device-width = <1>;
- };
-
- board-control@1,0 {
- reg = <1 0 20>;
- compatible = "fsl,mpc8272ads-bcsr";
- };
- };
-
-
- n) 4xx/Axon EMAC ethernet nodes
+ d) 4xx/Axon EMAC ethernet nodes
The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
the Axon bridge. To operate this needs to interact with a ths
@@ -2387,7 +1495,7 @@ platforms are moved over to use the flattened-device-tree model.
available.
For Axon: 0x0000012a
- o) Xilinx IP cores
+ e) Xilinx IP cores
The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
@@ -2681,206 +1789,7 @@ platforms are moved over to use the flattened-device-tree model.
- reg-offset : A value of 3 is required
- reg-shift : A value of 2 is required
-
- p) Freescale Synchronous Serial Interface
-
- The SSI is a serial device that communicates with audio codecs. It can
- be programmed in AC97, I2S, left-justified, or right-justified modes.
-
- Required properties:
- - compatible : compatible list, containing "fsl,ssi"
- - cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
- - reg : offset and length of the register set for the device
- - interrupts : <a b> where a is the interrupt number and b is a
- field that represents an encoding of the sense and
- level information for the interrupt. This should be
- encoded based on the information in section 2)
- depending on the type of interrupt controller you
- have.
- - interrupt-parent : the phandle for the interrupt controller that
- services interrupts for this device.
- - fsl,mode : the operating mode for the SSI interface
- "i2s-slave" - I2S mode, SSI is clock slave
- "i2s-master" - I2S mode, SSI is clock master
- "lj-slave" - left-justified mode, SSI is clock slave
- "lj-master" - l.j. mode, SSI is clock master
- "rj-slave" - right-justified mode, SSI is clock slave
- "rj-master" - r.j., SSI is clock master
- "ac97-slave" - AC97 mode, SSI is clock slave
- "ac97-master" - AC97 mode, SSI is clock master
-
- Optional properties:
- - codec-handle : phandle to a 'codec' node that defines an audio
- codec connected to this SSI. This node is typically
- a child of an I2C or other control node.
-
- Child 'codec' node required properties:
- - compatible : compatible list, contains the name of the codec
-
- Child 'codec' node optional properties:
- - clock-frequency : The frequency of the input clock, which typically
- comes from an on-board dedicated oscillator.
-
- * Freescale 83xx DMA Controller
-
- Freescale PowerPC 83xx have on chip general purpose DMA controllers.
-
- Required properties:
-
- - compatible : compatible list, contains 2 entries, first is
- "fsl,CHIP-dma", where CHIP is the processor
- (mpc8349, mpc8360, etc.) and the second is
- "fsl,elo-dma"
- - reg : <registers mapping for DMA general status reg>
- - ranges : Should be defined as specified in 1) to describe the
- DMA controller channels.
- - cell-index : controller index. 0 for controller @ 0x8100
- - interrupts : <interrupt mapping for DMA IRQ>
- - interrupt-parent : optional, if needed for interrupt mapping
-
-
- - DMA channel nodes:
- - compatible : compatible list, contains 2 entries, first is
- "fsl,CHIP-dma-channel", where CHIP is the processor
- (mpc8349, mpc8350, etc.) and the second is
- "fsl,elo-dma-channel"
- - reg : <registers mapping for channel>
- - cell-index : dma channel index starts at 0.
-
- Optional properties:
- - interrupts : <interrupt mapping for DMA channel IRQ>
- (on 83xx this is expected to be identical to
- the interrupts property of the parent node)
- - interrupt-parent : optional, if needed for interrupt mapping
-
- Example:
- dma@82a8 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
- reg = <82a8 4>;
- ranges = <0 8100 1a4>;
- interrupt-parent = <&ipic>;
- interrupts = <47 8>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- cell-index = <0>;
- reg = <0 80>;
- };
- dma-channel@80 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- cell-index = <1>;
- reg = <80 80>;
- };
- dma-channel@100 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- cell-index = <2>;
- reg = <100 80>;
- };
- dma-channel@180 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- cell-index = <3>;
- reg = <180 80>;
- };
- };
-
- * Freescale 85xx/86xx DMA Controller
-
- Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
-
- Required properties:
-
- - compatible : compatible list, contains 2 entries, first is
- "fsl,CHIP-dma", where CHIP is the processor
- (mpc8540, mpc8540, etc.) and the second is
- "fsl,eloplus-dma"
- - reg : <registers mapping for DMA general status reg>
- - cell-index : controller index. 0 for controller @ 0x21000,
- 1 for controller @ 0xc000
- - ranges : Should be defined as specified in 1) to describe the
- DMA controller channels.
-
- - DMA channel nodes:
- - compatible : compatible list, contains 2 entries, first is
- "fsl,CHIP-dma-channel", where CHIP is the processor
- (mpc8540, mpc8560, etc.) and the second is
- "fsl,eloplus-dma-channel"
- - cell-index : dma channel index starts at 0.
- - reg : <registers mapping for channel>
- - interrupts : <interrupt mapping for DMA channel IRQ>
- - interrupt-parent : optional, if needed for interrupt mapping
-
- Example:
- dma@21300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
- reg = <21300 4>;
- ranges = <0 21100 200>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
- reg = <0 80>;
- cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <14 2>;
- };
- dma-channel@80 {
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
- reg = <80 80>;
- cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <15 2>;
- };
- dma-channel@100 {
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
- reg = <100 80>;
- cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
- dma-channel@180 {
- compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
- reg = <180 80>;
- cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <17 2>;
- };
- };
-
- * Freescale 8xxx/3.0 Gb/s SATA nodes
-
- SATA nodes are defined to describe on-chip Serial ATA controllers.
- Each SATA port should have its own node.
-
- Required properties:
- - compatible : compatible list, contains 2 entries, first is
- "fsl,CHIP-sata", where CHIP is the processor
- (mpc8315, mpc8379, etc.) and the second is
- "fsl,pq-sata"
- - interrupts : <interrupt mapping for SATA IRQ>
- - cell-index : controller index.
- 1 for controller @ 0x18000
- 2 for controller @ 0x19000
- 3 for controller @ 0x1a000
- 4 for controller @ 0x1b000
-
- Optional properties:
- - interrupt-parent : optional, if needed for interrupt mapping
- - reg : <registers mapping>
-
- Example:
-
- sata@18000 {
- compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
- reg = <0x18000 0x1000>;
- cell-index = <1>;
- interrupts = <2c 8>;
- interrupt-parent = < &ipic >;
- };
-
- q) USB EHCI controllers
+ f) USB EHCI controllers
Required properties:
- compatible : should be "usb-ehci".
@@ -2906,109 +1815,6 @@ platforms are moved over to use the flattened-device-tree model.
big-endian;
};
- r) Freescale Display Interface Unit
-
- The Freescale DIU is a LCD controller, with proper hardware, it can also
- drive DVI monitors.
-
- Required properties:
- - compatible : should be "fsl-diu".
- - reg : should contain at least address and length of the DIU register
- set.
- - Interrupts : one DIU interrupt should be describe here.
-
- Example (MPC8610HPCD)
- display@2c000 {
- compatible = "fsl,diu";
- reg = <0x2c000 100>;
- interrupts = <72 2>;
- interrupt-parent = <&mpic>;
- };
-
- s) Freescale on board FPGA
-
- This is the memory-mapped registers for on board FPGA.
-
- Required properities:
- - compatible : should be "fsl,fpga-pixis".
- - reg : should contain the address and the lenght of the FPPGA register
- set.
-
- Example (MPC8610HPCD)
- board-control@e8000000 {
- compatible = "fsl,fpga-pixis";
- reg = <0xe8000000 32>;
- };
-
- t) Freescale MSI interrupt controller
-
- Reguired properities:
- - compatible : compatible list, contains 2 entries,
- first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
- etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
- the parent type.
- - reg : should contain the address and the length of the shared message
- interrupt register set.
- - msi-available-ranges: use <start count> style section to define which
- msi interrupt can be used in the 256 msi interrupts. This property is
- optional, without this, all the 256 MSI interrupts can be used.
- - interrupts : each one of the interrupts here is one entry per 32 MSIs,
- and routed to the host interrupt controller. the interrupts should
- be set as edge sensitive.
- - interrupt-parent: the phandle for the interrupt controller
- that services interrupts for this device. for 83xx cpu, the interrupts
- are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
- to MPIC.
-
- Example
- msi@41600 {
- compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
- reg = <0x41600 0x80>;
- msi-available-ranges = <0 0x100>;
- interrupts = <
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0>;
- interrupt-parent = <&mpic>;
- };
-
- u) Freescale General-purpose Timers Module
-
- Required properties:
- - compatible : should be
- "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
- "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
- "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
- - reg : should contain gtm registers location and length (0x40).
- - interrupts : should contain four interrupts.
- - interrupt-parent : interrupt source phandle.
- - clock-frequency : specifies the frequency driving the timer.
-
- Example:
-
- timer@500 {
- compatible = "fsl,mpc8360-gtm", "fsl,gtm";
- reg = <0x500 0x40>;
- interrupts = <90 8 78 8 84 8 72 8>;
- interrupt-parent = <&ipic>;
- /* filled by u-boot */
- clock-frequency = <0>;
- };
-
- timer@440 {
- compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
- reg = <0x440 0x40>;
- interrupts = <12 13 14 15>;
- interrupt-parent = <&qeic>;
- /* filled by u-boot */
- clock-frequency = <0>;
- };
-
VII - Marvell Discovery mv64[345]6x System Controller chips
===========================================================
diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
new file mode 100644
index 0000000..74ae6f1
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -0,0 +1,29 @@
+* Board Control and Status (BCSR)
+
+Required properties:
+
+ - device_type : Should be "board-control"
+ - reg : Offset and length of the register set for the device
+
+Example:
+
+ bcsr@f8000000 {
+ device_type = "board-control";
+ reg = <f8000000 8000>;
+ };
+
+* Freescale on board FPGA
+
+This is the memory-mapped registers for on board FPGA.
+
+Required properities:
+- compatible : should be "fsl,fpga-pixis".
+- reg : should contain the address and the lenght of the FPPGA register
+ set.
+
+Example (MPC8610HPCD):
+
+ board-control@e8000000 {
+ compatible = "fsl,fpga-pixis";
+ reg = <0xe8000000 32>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
new file mode 100644
index 0000000..088fc47
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
@@ -0,0 +1,67 @@
+* Freescale Communications Processor Module
+
+NOTE: This is an interim binding, and will likely change slightly,
+as more devices are supported. The QE bindings especially are
+incomplete.
+
+* Root CPM node
+
+Properties:
+- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
+- reg : A 48-byte region beginning with CPCR.
+
+Example:
+ cpm@119c0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
+ reg = <119c0 30>;
+ }
+
+* Properties common to mulitple CPM/QE devices
+
+- fsl,cpm-command : This value is ORed with the opcode and command flag
+ to specify the device on which a CPM command operates.
+
+- fsl,cpm-brg : Indicates which baud rate generator the device
+ is associated with. If absent, an unused BRG
+ should be dynamically allocated. If zero, the
+ device uses an external clock rather than a BRG.
+
+- reg : Unless otherwise specified, the first resource represents the
+ scc/fcc/ucc registers, and the second represents the device's
+ parameter RAM region (if it has one).
+
+* Multi-User RAM (MURAM)
+
+The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
+
+Ranges must be set up subject to the following restrictions:
+
+- Children's reg nodes must be offsets from the start of all muram, even
+ if the user-data area does not begin at zero.
+- If multiple range entries are used, the difference between the parent
+ address and the child address must be the same in all, so that a single
+ mapping can cover them all while maintaining the ability to determine
+ CPM-side offsets with pointer subtraction. It is recommended that
+ multiple range entries not be used.
+- A child address of zero must be translatable, even if no reg resources
+ contain it.
+
+A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
+indicate the portion of muram that is usable by the OS for arbitrary
+purposes. The data node may have an arbitrary number of reg resources,
+all of which contribute to the allocatable muram pool.
+
+Example, based on mpc8272:
+ muram@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 10000>;
+
+ data@0 {
+ compatible = "fsl,cpm-muram-data";
+ reg = <0 2000 9800 800>;
+ };
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
new file mode 100644
index 0000000..4c7d45e
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
@@ -0,0 +1,21 @@
+* Baud Rate Generators
+
+Currently defined compatibles:
+fsl,cpm-brg
+fsl,cpm1-brg
+fsl,cpm2-brg
+
+Properties:
+- reg : There may be an arbitrary number of reg resources; BRG
+ numbers are assigned to these in order.
+- clock-frequency : Specifies the base frequency driving
+ the BRG.
+
+Example:
+ brg@119f0 {
+ compatible = "fsl,mpc8272-brg",
+ "fsl,cpm2-brg",
+ "fsl,cpm-brg";
+ reg = <119f0 10 115f0 10>;
+ clock-frequency = <d#25000000>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
new file mode 100644
index 0000000..87bc604
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
@@ -0,0 +1,41 @@
+* I2C
+
+The I2C controller is expressed as a bus under the CPM node.
+
+Properties:
+- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
+- reg : On CPM2 devices, the second resource doesn't specify the I2C
+ Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
+ (typically 0x8afc 0x2).
+- #address-cells : Should be one. The cell is the i2c device address with
+ the r/w bit set to zero.
+- #size-cells : Should be zero.
+- clock-frequency : Can be used to set the i2c clock frequency. If
+ unspecified, a default frequency of 60kHz is being used.
+The following two properties are deprecated. They are only used by legacy
+i2c drivers to find the bus to probe:
+- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
+ the bus number is dynamically assigned by the i2c core.
+- linux,i2c-class : Can be used to override the i2c class. The class is used
+ by legacy i2c device drivers to find a bus in a specific context like
+ system management, video or sound. By default, I2C_CLASS_HWMON (1) is
+ being used. The definition of the classes can be found in
+ include/i2c/i2c.h
+
+Example, based on mpc823:
+
+ i2c@860 {
+ compatible = "fsl,mpc823-i2c",
+ "fsl,cpm1-i2c";
+ reg = <0x860 0x20 0x3c80 0x30>;
+ interrupts = <16>;
+ interrupt-parent = <&CPM_PIC>;
+ fsl,cpm-command = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@68 {
+ compatible = "dallas,ds1307";
+ reg = <0x68>;
+ };
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
new file mode 100644
index 0000000..8e3ee16
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
@@ -0,0 +1,18 @@
+* Interrupt Controllers
+
+Currently defined compatibles:
+- fsl,cpm1-pic
+ - only one interrupt cell
+- fsl,pq1-pic
+- fsl,cpm2-pic
+ - second interrupt cell is level/sense:
+ - 2 is falling edge
+ - 8 is active low
+
+Example:
+ interrupt-controller@10c00 {
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <10c00 80>;
+ compatible = "mpc8272-pic", "fsl,cpm2-pic";
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
new file mode 100644
index 0000000..74bfda4
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
@@ -0,0 +1,15 @@
+* USB (Universal Serial Bus Controller)
+
+Properties:
+- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
+
+Example:
+ usb@11bc0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,cpm2-usb";
+ reg = <11b60 18 8b00 100>;
+ interrupts = <b 8>;
+ interrupt-parent = <&PIC>;
+ fsl,cpm-command = <2e600000>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
new file mode 100644
index 0000000..0e42694
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
@@ -0,0 +1,45 @@
+* Network
+
+Currently defined compatibles:
+- fsl,cpm1-scc-enet
+- fsl,cpm2-scc-enet
+- fsl,cpm1-fec-enet
+- fsl,cpm2-fcc-enet (third resource is GFEMR)
+- fsl,qe-enet
+
+Example:
+
+ ethernet@11300 {
+ device_type = "network";
+ compatible = "fsl,mpc8272-fcc-enet",
+ "fsl,cpm2-fcc-enet";
+ reg = <11300 20 8400 100 11390 1>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <20 8>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&PHY0>;
+ fsl,cpm-command = <12000300>;
+ };
+
+* MDIO
+
+Currently defined compatibles:
+fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
+fsl,cpm2-mdio-bitbang (reg is port C registers)
+
+Properties for fsl,cpm2-mdio-bitbang:
+fsl,mdio-pin : pin of port C controlling mdio data
+fsl,mdc-pin : pin of port C controlling mdio clock
+
+Example:
+ mdio@10d40 {
+ device_type = "mdio";
+ compatible = "fsl,mpc8272ads-mdio-bitbang",
+ "fsl,mpc8272-mdio-bitbang",
+ "fsl,cpm2-mdio-bitbang";
+ reg = <10d40 14>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fsl,mdio-pin = <12>;
+ fsl,mdc-pin = <13>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
new file mode 100644
index 0000000..78790d5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -0,0 +1,58 @@
+* Freescale QUICC Engine module (QE)
+This represents qe module that is installed on PowerQUICC II Pro.
+
+NOTE: This is an interim binding; it should be updated to fit
+in with the CPM binding later in this document.
+
+Basically, it is a bus of devices, that could act more or less
+as a complete entity (UCC, USB etc ). All of them should be siblings on
+the "root" qe node, using the common properties from there.
+The description below applies to the qe of MPC8360 and
+more nodes and properties would be extended in the future.
+
+i) Root QE device
+
+Required properties:
+- compatible : should be "fsl,qe";
+- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
+- reg : offset and length of the device registers.
+- bus-frequency : the clock frequency for QUICC Engine.
+
+Recommended properties
+- brg-frequency : the internal clock source frequency for baud-rate
+ generators in Hz.
+
+Example:
+ qe@e0100000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ compatible = "fsl,qe";
+ ranges = <0 e0100000 00100000>;
+ reg = <e0100000 480>;
+ brg-frequency = <0>;
+ bus-frequency = <179A7B00>;
+ }
+
+* Multi-User RAM (MURAM)
+
+Required properties:
+- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
+- mode : the could be "host" or "slave".
+- ranges : Should be defined as specified in 1) to describe the
+ translation of MURAM addresses.
+- data-only : sub-node which defines the address area under MURAM
+ bus that can be allocated as data/parameter
+
+Example:
+
+ muram@10000 {
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0 00010000 0000c000>;
+
+ data-only@0{
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0 c000>;
+ };
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
new file mode 100644
index 0000000..6c238f5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
@@ -0,0 +1,24 @@
+* Uploaded QE firmware
+
+ If a new firwmare has been uploaded to the QE (usually by the
+ boot loader), then a 'firmware' child node should be added to the QE
+ node. This node provides information on the uploaded firmware that
+ device drivers may need.
+
+ Required properties:
+ - id: The string name of the firmware. This is taken from the 'id'
+ member of the qe_firmware structure of the uploaded firmware.
+ Device drivers can search this string to determine if the
+ firmware they want is already present.
+ - extended-modes: The Extended Modes bitfield, taken from the
+ firmware binary. It is a 64-bit number represented
+ as an array of two 32-bit numbers.
+ - virtual-traps: The virtual traps, taken from the firmware binary.
+ It is an array of 8 32-bit numbers.
+
+Example:
+ firmware {
+ id = "Soft-UART";
+ extended-modes = <0 0>;
+ virtual-traps = <0 0 0 0 0 0 0 0>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
new file mode 100644
index 0000000..6098426
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
@@ -0,0 +1,51 @@
+* Parallel I/O Ports
+
+This node configures Parallel I/O ports for CPUs with QE support.
+The node should reside in the "soc" node of the tree. For each
+device that using parallel I/O ports, a child node should be created.
+See the definition of the Pin configuration nodes below for more
+information.
+
+Required properties:
+- device_type : should be "par_io".
+- reg : offset to the register set and its length.
+- num-ports : number of Parallel I/O ports
+
+Example:
+par_io@1400 {
+ reg = <1400 100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "par_io";
+ num-ports = <7>;
+ ucc_pin@01 {
+ ......
+ };
+
+Note that "par_io" nodes are obsolete, and should not be used for
+the new device trees. Instead, each Par I/O bank should be represented
+via its own gpio-controller node:
+
+Required properties:
+- #gpio-cells : should be "2".
+- compatible : should be "fsl,<chip>-qe-pario-bank",
+ "fsl,mpc8323-qe-pario-bank".
+- reg : offset to the register set and its length.
+- gpio-controller : node to identify gpio controllers.
+
+Example:
+ qe_pio_a: gpio-controller@1400 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8360-qe-pario-bank",
+ "fsl,mpc8323-qe-pario-bank";
+ reg = <0x1400 0x18>;
+ gpio-controller;
+ };
+
+ qe_pio_e: gpio-controller@1460 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8360-qe-pario-bank",
+ "fsl,mpc8323-qe-pario-bank";
+ reg = <0x1460 0x18>;
+ gpio-controller;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
new file mode 100644
index 0000000..c5b4306
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
@@ -0,0 +1,60 @@
+* Pin configuration nodes
+
+Required properties:
+- linux,phandle : phandle of this node; likely referenced by a QE
+ device.
+- pio-map : array of pin configurations. Each pin is defined by 6
+ integers. The six numbers are respectively: port, pin, dir,
+ open_drain, assignment, has_irq.
+ - port : port number of the pin; 0-6 represent port A-G in UM.
+ - pin : pin number in the port.
+ - dir : direction of the pin, should encode as follows:
+
+ 0 = The pin is disabled
+ 1 = The pin is an output
+ 2 = The pin is an input
+ 3 = The pin is I/O
+
+ - open_drain : indicates the pin is normal or wired-OR:
+
+ 0 = The pin is actively driven as an output
+ 1 = The pin is an open-drain driver. As an output, the pin is
+ driven active-low, otherwise it is three-stated.
+
+ - assignment : function number of the pin according to the Pin Assignment
+ tables in User Manual. Each pin can have up to 4 possible functions in
+ QE and two options for CPM.
+ - has_irq : indicates if the pin is used as source of external
+ interrupts.
+
+Example:
+ ucc_pin@01 {
+ linux,phandle = <140001>;
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 3 1 0 1 0 /* TxD0 */
+ 0 4 1 0 1 0 /* TxD1 */
+ 0 5 1 0 1 0 /* TxD2 */
+ 0 6 1 0 1 0 /* TxD3 */
+ 1 6 1 0 3 0 /* TxD4 */
+ 1 7 1 0 1 0 /* TxD5 */
+ 1 9 1 0 2 0 /* TxD6 */
+ 1 a 1 0 2 0 /* TxD7 */
+ 0 9 2 0 1 0 /* RxD0 */
+ 0 a 2 0 1 0 /* RxD1 */
+ 0 b 2 0 1 0 /* RxD2 */
+ 0 c 2 0 1 0 /* RxD3 */
+ 0 d 2 0 1 0 /* RxD4 */
+ 1 1 2 0 2 0 /* RxD5 */
+ 1 0 2 0 2 0 /* RxD6 */
+ 1 4 2 0 2 0 /* RxD7 */
+ 0 7 1 0 1 0 /* TX_EN */
+ 0 8 1 0 1 0 /* TX_ER */
+ 0 f 2 0 1 0 /* RX_DV */
+ 0 10 2 0 1 0 /* RX_ER */
+ 0 0 2 0 1 0 /* RX_CLK */
+ 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
+ 2 8 2 0 1 0>; /* GTX125 - CLK9 */
+ };
+
+
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
new file mode 100644
index 0000000..e47734b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
@@ -0,0 +1,70 @@
+* UCC (Unified Communications Controllers)
+
+Required properties:
+- device_type : should be "network", "hldc", "uart", "transparent"
+ "bisync", "atm", or "serial".
+- compatible : could be "ucc_geth" or "fsl_atm" and so on.
+- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
+- reg : Offset and length of the register set for the device
+- interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+- interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+- pio-handle : The phandle for the Parallel I/O port configuration.
+- port-number : for UART drivers, the port number to use, between 0 and 3.
+ This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
+ The port number is added to the minor number of the device. Unlike the
+ CPM UART driver, the port-number is required for the QE UART driver.
+- soft-uart : for UART drivers, if specified this means the QE UART device
+ driver should use "Soft-UART" mode, which is needed on some SOCs that have
+ broken UART hardware. Soft-UART is provided via a microcode upload.
+- rx-clock-name: the UCC receive clock source
+ "none": clock source is disabled
+ "brg1" through "brg16": clock source is BRG1-BRG16, respectively
+ "clk1" through "clk24": clock source is CLK1-CLK24, respectively
+- tx-clock-name: the UCC transmit clock source
+ "none": clock source is disabled
+ "brg1" through "brg16": clock source is BRG1-BRG16, respectively
+ "clk1" through "clk24": clock source is CLK1-CLK24, respectively
+The following two properties are deprecated. rx-clock has been replaced
+with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
+Drivers that currently use the deprecated properties should continue to
+do so, in order to support older device trees, but they should be updated
+to check for the new properties first.
+- rx-clock : represents the UCC receive clock source.
+ 0x00 : clock source is disabled;
+ 0x1~0x10 : clock source is BRG1~BRG16 respectively;
+ 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+- tx-clock: represents the UCC transmit clock source;
+ 0x00 : clock source is disabled;
+ 0x1~0x10 : clock source is BRG1~BRG16 respectively;
+ 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+
+Required properties for network device_type:
+- mac-address : list of bytes representing the ethernet address.
+- phy-handle : The phandle for the PHY connected to this controller.
+
+Recommended properties:
+- phy-connection-type : a string naming the controller/PHY interface type,
+ i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
+ Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
+ "tbi", or "rtbi".
+
+Example:
+ ucc@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <1>;
+ reg = <2000 200>;
+ interrupts = <a0 0>;
+ interrupt-parent = <700>;
+ mac-address = [ 00 04 9f 00 23 23 ];
+ rx-clock = "none";
+ tx-clock = "clk9";
+ phy-handle = <212000>;
+ phy-connection-type = "gmii";
+ pio-handle = <140001>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
new file mode 100644
index 0000000..c8f44d6
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
@@ -0,0 +1,22 @@
+* USB (Universal Serial Bus Controller)
+
+Required properties:
+- compatible : could be "qe_udc" or "fhci-hcd".
+- mode : the could be "host" or "slave".
+- reg : Offset and length of the register set for the device
+- interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+- interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+
+Example(slave):
+ usb@6c0 {
+ compatible = "qe_udc";
+ reg = <6c0 40>;
+ interrupts = <8b 0>;
+ interrupt-parent = <700>;
+ mode = "slave";
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
new file mode 100644
index 0000000..b35f348
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
@@ -0,0 +1,21 @@
+* Serial
+
+Currently defined compatibles:
+- fsl,cpm1-smc-uart
+- fsl,cpm2-smc-uart
+- fsl,cpm1-scc-uart
+- fsl,cpm2-scc-uart
+- fsl,qe-uart
+
+Example:
+
+ serial@11a00 {
+ device_type = "serial";
+ compatible = "fsl,mpc8272-scc-uart",
+ "fsl,cpm2-scc-uart";
+ reg = <11a00 20 8000 100>;
+ interrupts = <28 8>;
+ interrupt-parent = <&PIC>;
+ fsl,cpm-brg = <1>;
+ fsl,cpm-command = <00800000>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/diu.txt b/Documentation/powerpc/dts-bindings/fsl/diu.txt
new file mode 100644
index 0000000..deb35de
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/diu.txt
@@ -0,0 +1,18 @@
+* Freescale Display Interface Unit
+
+The Freescale DIU is a LCD controller, with proper hardware, it can also
+drive DVI monitors.
+
+Required properties:
+- compatible : should be "fsl-diu".
+- reg : should contain at least address and length of the DIU register
+ set.
+- Interrupts : one DIU interrupt should be describe here.
+
+Example (MPC8610HPCD):
+ display@2c000 {
+ compatible = "fsl,diu";
+ reg = <0x2c000 100>;
+ interrupts = <72 2>;
+ interrupt-parent = <&mpic>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/dma.txt b/Documentation/powerpc/dts-bindings/fsl/dma.txt
new file mode 100644
index 0000000..86826df
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/dma.txt
@@ -0,0 +1,127 @@
+* Freescale 83xx DMA Controller
+
+Freescale PowerPC 83xx have on chip general purpose DMA controllers.
+
+Required properties:
+
+- compatible : compatible list, contains 2 entries, first is
+ "fsl,CHIP-dma", where CHIP is the processor
+ (mpc8349, mpc8360, etc.) and the second is
+ "fsl,elo-dma"
+- reg : <registers mapping for DMA general status reg>
+- ranges : Should be defined as specified in 1) to describe the
+ DMA controller channels.
+- cell-index : controller index. 0 for controller @ 0x8100
+- interrupts : <interrupt mapping for DMA IRQ>
+- interrupt-parent : optional, if needed for interrupt mapping
+
+
+- DMA channel nodes:
+ - compatible : compatible list, contains 2 entries, first is
+ "fsl,CHIP-dma-channel", where CHIP is the processor
+ (mpc8349, mpc8350, etc.) and the second is
+ "fsl,elo-dma-channel"
+ - reg : <registers mapping for channel>
+ - cell-index : dma channel index starts at 0.
+
+Optional properties:
+ - interrupts : <interrupt mapping for DMA channel IRQ>
+ (on 83xx this is expected to be identical to
+ the interrupts property of the parent node)
+ - interrupt-parent : optional, if needed for interrupt mapping
+
+Example:
+ dma@82a8 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
+ reg = <82a8 4>;
+ ranges = <0 8100 1a4>;
+ interrupt-parent = <&ipic>;
+ interrupts = <47 8>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
+ cell-index = <0>;
+ reg = <0 80>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
+ cell-index = <1>;
+ reg = <80 80>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
+ cell-index = <2>;
+ reg = <100 80>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
+ cell-index = <3>;
+ reg = <180 80>;
+ };
+ };
+
+* Freescale 85xx/86xx DMA Controller
+
+Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
+
+Required properties:
+
+- compatible : compatible list, contains 2 entries, first is
+ "fsl,CHIP-dma", where CHIP is the processor
+ (mpc8540, mpc8540, etc.) and the second is
+ "fsl,eloplus-dma"
+- reg : <registers mapping for DMA general status reg>
+- cell-index : controller index. 0 for controller @ 0x21000,
+ 1 for controller @ 0xc000
+- ranges : Should be defined as specified in 1) to describe the
+ DMA controller channels.
+
+- DMA channel nodes:
+ - compatible : compatible list, contains 2 entries, first is
+ "fsl,CHIP-dma-channel", where CHIP is the processor
+ (mpc8540, mpc8560, etc.) and the second is
+ "fsl,eloplus-dma-channel"
+ - cell-index : dma channel index starts at 0.
+ - reg : <registers mapping for channel>
+ - interrupts : <interrupt mapping for DMA channel IRQ>
+ - interrupt-parent : optional, if needed for interrupt mapping
+
+Example:
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
+ reg = <21300 4>;
+ ranges = <0 21100 200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
+ reg = <0 80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <14 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
+ reg = <80 80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <15 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
+ reg = <100 80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
+ reg = <180 80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <17 2>;
+ };
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/gtm.txt b/Documentation/powerpc/dts-bindings/fsl/gtm.txt
new file mode 100644
index 0000000..9a33efd
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/gtm.txt
@@ -0,0 +1,31 @@
+* Freescale General-purpose Timers Module
+
+Required properties:
+ - compatible : should be
+ "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
+ "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
+ "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
+ - reg : should contain gtm registers location and length (0x40).
+ - interrupts : should contain four interrupts.
+ - interrupt-parent : interrupt source phandle.
+ - clock-frequency : specifies the frequency driving the timer.
+
+Example:
+
+timer@500 {
+ compatible = "fsl,mpc8360-gtm", "fsl,gtm";
+ reg = <0x500 0x40>;
+ interrupts = <90 8 78 8 84 8 72 8>;
+ interrupt-parent = <&ipic>;
+ /* filled by u-boot */
+ clock-frequency = <0>;
+};
+
+timer@440 {
+ compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
+ reg = <0x440 0x40>;
+ interrupts = <12 13 14 15>;
+ interrupt-parent = <&qeic>;
+ /* filled by u-boot */
+ clock-frequency = <0>;
+};
diff --git a/Documentation/powerpc/dts-bindings/fsl/guts.txt b/Documentation/powerpc/dts-bindings/fsl/guts.txt
new file mode 100644
index 0000000..9e7a241
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/guts.txt
@@ -0,0 +1,25 @@
+* Global Utilities Block
+
+The global utilities block controls power management, I/O device
+enabling, power-on-reset configuration monitoring, general-purpose
+I/O signal configuration, alternate function selection for multiplexed
+signals, and clock control.
+
+Required properties:
+
+ - compatible : Should define the compatible device type for
+ global-utilities.
+ - reg : Offset and length of the register set for the device.
+
+Recommended properties:
+
+ - fsl,has-rstcr : Indicates that the global utilities register set
+ contains a functioning "reset control register" (i.e. the board
+ is wired to reset upon setting the HRESET_REQ bit in this register).
+
+Example:
+ global-utilities@e0000 { /* global utilities block */
+ compatible = "fsl,mpc8548-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
new file mode 100644
index 0000000..d0ab33e
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -0,0 +1,32 @@
+* I2C
+
+Required properties :
+
+ - device_type : Should be "i2c"
+ - reg : Offset and length of the register set for the device
+
+Recommended properties :
+
+ - compatible : Should be "fsl-i2c" for parts compatible with
+ Freescale I2C specifications.
+ - interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+ - dfsrr : boolean; if defined, indicates that this I2C device has
+ a digital filter sampling rate register
+ - fsl5200-clocking : boolean; if defined, indicated that this device
+ uses the FSL 5200 clocking mechanism.
+
+Example :
+ i2c@3000 {
+ interrupt-parent = <40000>;
+ interrupts = <1b 3>;
+ reg = <3000 18>;
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ dfsrr;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/lbc.txt b/Documentation/powerpc/dts-bindings/fsl/lbc.txt
new file mode 100644
index 0000000..3300fec
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/lbc.txt
@@ -0,0 +1,35 @@
+* Chipselect/Local Bus
+
+Properties:
+- name : Should be localbus
+- #address-cells : Should be either two or three. The first cell is the
+ chipselect number, and the remaining cells are the
+ offset into the chipselect.
+- #size-cells : Either one or two, depending on how large each chipselect
+ can be.
+- ranges : Each range corresponds to a single chipselect, and cover
+ the entire access window as configured.
+
+Example:
+ localbus@f0010100 {
+ compatible = "fsl,mpc8272-localbus",
+ "fsl,pq2-localbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <f0010100 40>;
+
+ ranges = <0 0 fe000000 02000000
+ 1 0 f4500000 00008000>;
+
+ flash@0,0 {
+ compatible = "jedec-flash";
+ reg = <0 0 2000000>;
+ bank-width = <4>;
+ device-width = <1>;
+ };
+
+ board-control@1,0 {
+ reg = <1 0 20>;
+ compatible = "fsl,mpc8272ads-bcsr";
+ };
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt b/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
new file mode 100644
index 0000000..b26b919
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
@@ -0,0 +1,36 @@
+* Freescale MSI interrupt controller
+
+Reguired properities:
+- compatible : compatible list, contains 2 entries,
+ first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
+ etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
+ the parent type.
+- reg : should contain the address and the length of the shared message
+ interrupt register set.
+- msi-available-ranges: use <start count> style section to define which
+ msi interrupt can be used in the 256 msi interrupts. This property is
+ optional, without this, all the 256 MSI interrupts can be used.
+- interrupts : each one of the interrupts here is one entry per 32 MSIs,
+ and routed to the host interrupt controller. the interrupts should
+ be set as edge sensitive.
+- interrupt-parent: the phandle for the interrupt controller
+ that services interrupts for this device. for 83xx cpu, the interrupts
+ are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
+ to MPIC.
+
+Example:
+ msi@41600 {
+ compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/sata.txt b/Documentation/powerpc/dts-bindings/fsl/sata.txt
new file mode 100644
index 0000000..b46bcf4
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/sata.txt
@@ -0,0 +1,29 @@
+* Freescale 8xxx/3.0 Gb/s SATA nodes
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA port should have its own node.
+
+Required properties:
+- compatible : compatible list, contains 2 entries, first is
+ "fsl,CHIP-sata", where CHIP is the processor
+ (mpc8315, mpc8379, etc.) and the second is
+ "fsl,pq-sata"
+- interrupts : <interrupt mapping for SATA IRQ>
+- cell-index : controller index.
+ 1 for controller @ 0x18000
+ 2 for controller @ 0x19000
+ 3 for controller @ 0x1a000
+ 4 for controller @ 0x1b000
+
+Optional properties:
+- interrupt-parent : optional, if needed for interrupt mapping
+- reg : <registers mapping>
+
+Example:
+ sata@18000 {
+ compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
+ reg = <0x18000 0x1000>;
+ cell-index = <1>;
+ interrupts = <2c 8>;
+ interrupt-parent = < &ipic >;
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt b/Documentation/powerpc/dts-bindings/fsl/spi.txt
new file mode 100644
index 0000000..e7d9a34
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -0,0 +1,24 @@
+* SPI (Serial Peripheral Interface)
+
+Required properties:
+- cell-index : SPI controller index.
+- compatible : should be "fsl,spi".
+- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
+- reg : Offset and length of the register set for the device
+- interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+- interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+
+Example:
+ spi@4c0 {
+ cell-index = <0>;
+ compatible = "fsl,spi";
+ reg = <4c0 40>;
+ interrupts = <82 0>;
+ interrupt-parent = <700>;
+ mode = "cpu";
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/ssi.txt b/Documentation/powerpc/dts-bindings/fsl/ssi.txt
new file mode 100644
index 0000000..d100555
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/ssi.txt
@@ -0,0 +1,38 @@
+Freescale Synchronous Serial Interface
+
+The SSI is a serial device that communicates with audio codecs. It can
+be programmed in AC97, I2S, left-justified, or right-justified modes.
+
+Required properties:
+- compatible : compatible list, containing "fsl,ssi"
+- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
+- reg : offset and length of the register set for the device
+- interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and
+ level information for the interrupt. This should be
+ encoded based on the information in section 2)
+ depending on the type of interrupt controller you
+ have.
+- interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+- fsl,mode : the operating mode for the SSI interface
+ "i2s-slave" - I2S mode, SSI is clock slave
+ "i2s-master" - I2S mode, SSI is clock master
+ "lj-slave" - left-justified mode, SSI is clock slave
+ "lj-master" - l.j. mode, SSI is clock master
+ "rj-slave" - right-justified mode, SSI is clock slave
+ "rj-master" - r.j., SSI is clock master
+ "ac97-slave" - AC97 mode, SSI is clock slave
+ "ac97-master" - AC97 mode, SSI is clock master
+
+Optional properties:
+- codec-handle : phandle to a 'codec' node that defines an audio
+ codec connected to this SSI. This node is typically
+ a child of an I2C or other control node.
+
+Child 'codec' node required properties:
+- compatible : compatible list, contains the name of the codec
+
+Child 'codec' node optional properties:
+- clock-frequency : The frequency of the input clock, which typically
+ comes from an on-board dedicated oscillator.
diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
new file mode 100644
index 0000000..583ef6b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
@@ -0,0 +1,69 @@
+* MDIO IO device
+
+The MDIO is a bus to which the PHY devices are connected. For each
+device that exists on this bus, a child node should be created. See
+the definition of the PHY node below for an example of how to define
+a PHY.
+
+Required properties:
+ - reg : Offset and length of the register set for the device
+ - compatible : Should define the compatible device type for the
+ mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
+
+Example:
+
+ mdio@24520 {
+ reg = <24520 20>;
+ compatible = "fsl,gianfar-mdio";
+
+ ethernet-phy@0 {
+ ......
+ };
+ };
+
+
+* Gianfar-compatible ethernet nodes
+
+Required properties:
+
+ - device_type : Should be "network"
+ - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
+ - compatible : Should be "gianfar"
+ - reg : Offset and length of the register set for the device
+ - mac-address : List of bytes representing the ethernet address of
+ this controller
+ - interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+ - phy-handle : The phandle for the PHY connected to this ethernet
+ controller.
+ - fixed-link : <a b c d e> where a is emulated phy id - choose any,
+ but unique to the all specified fixed-links, b is duplex - 0 half,
+ 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
+ pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
+
+Recommended properties:
+
+ - phy-connection-type : a string naming the controller/PHY interface type,
+ i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
+ "tbi", or "rtbi". This property is only really needed if the connection
+ is of type "rgmii-id", as all other connection types are detected by
+ hardware.
+
+
+Example:
+ ethernet@24000 {
+ #size-cells = <0>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ mac-address = [ 00 E0 0C 00 73 00 ];
+ interrupts = <d 3 e 3 12 3>;
+ interrupt-parent = <40000>;
+ phy-handle = <2452000>
+ };
diff --git a/Documentation/powerpc/dts-bindings/fsl/usb.txt b/Documentation/powerpc/dts-bindings/fsl/usb.txt
new file mode 100644
index 0000000..b001524
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/usb.txt
@@ -0,0 +1,59 @@
+Freescale SOC USB controllers
+
+The device node for a USB controller that is part of a Freescale
+SOC is as described in the document "Open Firmware Recommended
+Practice : Universal Serial Bus" with the following modifications
+and additions :
+
+Required properties :
+ - compatible : Should be "fsl-usb2-mph" for multi port host USB
+ controllers, or "fsl-usb2-dr" for dual role USB controllers
+ - phy_type : For multi port host USB controllers, should be one of
+ "ulpi", or "serial". For dual role USB controllers, should be
+ one of "ulpi", "utmi", "utmi_wide", or "serial".
+ - reg : Offset and length of the register set for the device
+ - port0 : boolean; if defined, indicates port0 is connected for
+ fsl-usb2-mph compatible controllers. Either this property or
+ "port1" (or both) must be defined for "fsl-usb2-mph" compatible
+ controllers.
+ - port1 : boolean; if defined, indicates port1 is connected for
+ fsl-usb2-mph compatible controllers. Either this property or
+ "port0" (or both) must be defined for "fsl-usb2-mph" compatible
+ controllers.
+ - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
+ controllers. Can be "host", "peripheral", or "otg". Default to
+ "host" if not defined for backward compatibility.
+
+Recommended properties :
+ - interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+
+Example multi port host USB controller device node :
+ usb@22000 {
+ compatible = "fsl-usb2-mph";
+ reg = <22000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <700>;
+ interrupts = <27 1>;
+ phy_type = "ulpi";
+ port0;
+ port1;
+ };
+
+Example dual role USB controller device node :
+ usb@23000 {
+ compatible = "fsl-usb2-dr";
+ reg = <23000 1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <700>;
+ interrupts = <26 1>;
+ dr_mode = "otg";
+ phy = "ulpi";
+ };
--
1.5.5.1
^ permalink raw reply related
* Re: [PATCH v2] Add PPC_FEATURE_PSERIES_PMU_COMPAT
From: Nathan Lynch @ 2008-07-08 22:30 UTC (permalink / raw)
To: Kumar Gala; +Cc: Olof Johansson, linuxppc-dev, Paul Mackerras
In-Reply-To: <A8423953-8153-48AD-B8C4-A6C0CBBABFB8@kernel.crashing.org>
Kumar Gala wrote:
>
> So is PMU here performance monitor unit? I think that was part of my
> confusion earlier. I was thinking Power Mgmt Unit (like on Apple HW).
Yes, PMU means performance monitor unit in the context of pseries.
> I hate make the name longer, but PPC_FEATURE_PSERIES_PERFMON_COMPAT
> would probably be clearer.
Okay.
^ permalink raw reply
* [PATCH] kill useless SMT code in prom_hold_cpus
From: Nathan Lynch @ 2008-07-08 22:36 UTC (permalink / raw)
To: linuxppc-dev
I think this code that counts SMT threads and compares against NR_CPUS
is an artifact of pre-powerpc-merge ppc64. We care about starting
only primary threads in the OF client code.
Signed-off-by: Nathan Lynch <ntl@pobox.com>
---
arch/powerpc/kernel/prom_init.c | 39 +++------------------------------------
1 files changed, 3 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 1ea8c8d..b1dd86c 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -205,8 +205,6 @@ static int __initdata mem_reserve_cnt;
static cell_t __initdata regbuf[1024];
-#define MAX_CPU_THREADS 2
-
/*
* Error results ... some OF calls will return "-1" on error, some
* will return 0, some will return either. To simplify, here are
@@ -1332,10 +1330,6 @@ static void __init prom_hold_cpus(void)
unsigned int reg;
phandle node;
char type[64];
- int cpuid = 0;
- unsigned int interrupt_server[MAX_CPU_THREADS];
- unsigned int cpu_threads, hw_cpu_num;
- int propsize;
struct prom_t *_prom = &RELOC(prom);
unsigned long *spinloop
= (void *) LOW_ADDR(__secondary_hold_spinloop);
@@ -1379,7 +1373,6 @@ static void __init prom_hold_cpus(void)
reg = -1;
prom_getprop(node, "reg", ®, sizeof(reg));
- prom_debug("\ncpuid = 0x%x\n", cpuid);
prom_debug("cpu hw idx = 0x%x\n", reg);
/* Init the acknowledge var which will be reset by
@@ -1388,28 +1381,9 @@ static void __init prom_hold_cpus(void)
*/
*acknowledge = (unsigned long)-1;
- propsize = prom_getprop(node, "ibm,ppc-interrupt-server#s",
- &interrupt_server,
- sizeof(interrupt_server));
- if (propsize < 0) {
- /* no property. old hardware has no SMT */
- cpu_threads = 1;
- interrupt_server[0] = reg; /* fake it with phys id */
- } else {
- /* We have a threaded processor */
- cpu_threads = propsize / sizeof(u32);
- if (cpu_threads > MAX_CPU_THREADS) {
- prom_printf("SMT: too many threads!\n"
- "SMT: found %x, max is %x\n",
- cpu_threads, MAX_CPU_THREADS);
- cpu_threads = 1; /* ToDo: panic? */
- }
- }
-
- hw_cpu_num = interrupt_server[0];
- if (hw_cpu_num != _prom->cpu) {
+ if (reg != _prom->cpu) {
/* Primary Thread of non-boot cpu */
- prom_printf("%x : starting cpu hw idx %x... ", cpuid, reg);
+ prom_printf("starting cpu hw idx %x... ", reg);
call_prom("start-cpu", 3, 0, node,
secondary_hold, reg);
@@ -1424,17 +1398,10 @@ static void __init prom_hold_cpus(void)
}
#ifdef CONFIG_SMP
else
- prom_printf("%x : boot cpu %x\n", cpuid, reg);
+ prom_printf("boot cpu hw idx %x\n", reg);
#endif /* CONFIG_SMP */
-
- /* Reserve cpu #s for secondary threads. They start later. */
- cpuid += cpu_threads;
}
- if (cpuid > NR_CPUS)
- prom_printf("WARNING: maximum CPUs (" __stringify(NR_CPUS)
- ") exceeded: ignoring extras\n");
-
prom_debug("prom_hold_cpus: end...\n");
}
--
1.5.6.2
^ permalink raw reply related
* RE: RAMDISK: ran out of compressed data
From: Siva Prasad @ 2008-07-08 22:54 UTC (permalink / raw)
To: Marco Stornelli; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <48730FFA.1070805@coritel.it>
Hi,
The same ramdisk works fine for 2.6.15 kernel. We are just upgrading to
a new version, and would like to get that ramdisk to work on the new one
as well.
Can you please elaborate on what you mean by compression format. Mine
currently use the standard .gz extension/compression.
Thanks
Siva
Siva Prasad ha scritto:
> Hi,
>=20
> I am getting the following error when I tried to boot with ramdisk.
Any
> specific reason or clue why this is happening?
>=20
> RAMDISK: Compressed image found at block 0
> RAMDISK: ran out of compressed data
> invalid compressed format (err=3D1)
>=20
> I am running into this on 8641D runing 2.6.24-rc6 kernel. My .config
> around block area are...
>=20
> CONFIG_BLK_DEV=3Dy
> # CONFIG_BLK_DEV_FD is not set
> # CONFIG_BLK_CPQ_DA is not set
> # CONFIG_BLK_CPQ_CISS_DA is not set
> # CONFIG_BLK_DEV_DAC960 is not set
> # CONFIG_BLK_DEV_UMEM is not set
> # CONFIG_BLK_DEV_COW_COMMON is not set
> CONFIG_BLK_DEV_LOOP=3Dy
> # CONFIG_BLK_DEV_CRYPTOLOOP is not set
> # CONFIG_BLK_DEV_NBD is not set
> # CONFIG_BLK_DEV_SX8 is not set
> CONFIG_BLK_DEV_RAM=3Dy
> CONFIG_BLK_DEV_RAM_COUNT=3D16
> CONFIG_BLK_DEV_RAM_SIZE=3D49152
> CONFIG_BLK_DEV_RAM_BLOCKSIZE=3D1024
>=20
> Thanks
> Siva
>=20
I think it's not a kernel problem but a problem related with the=20
compression method instead. Check out how you are compressing the
ramdisk.
--=20
Marco Stornelli
Embedded Software Engineer
CoRiTeL - Consorzio di Ricerca sulle Telecomunicazioni
http://www.coritel.it
marco.stornelli@coritel.it
+39 06 72582838
^ permalink raw reply
* Re: [PATCH] powerpc: i2c-ibm_iic register child nodes
From: Josh Boyer @ 2008-07-09 0:04 UTC (permalink / raw)
To: Sean MacLennan; +Cc: linuxppc-dev
In-Reply-To: <20080708162240.70b34046@lappy.seanm.ca>
On Tue, 8 Jul 2008 16:22:40 -0400
Sean MacLennan <smaclennan@pikatech.com> wrote:
> Update the warp to use the new IBM IIC driver. We no longer need to
> register the I2C devices in the platform code.
>
> Also adds a small bugfix for the i2c code if the i2c read fails.
I'll queue this up after Jean pulls in the i2c patch.
josh
^ permalink raw reply
* [PATCH v4] powerpc: update crypto node definition and device tree instances
From: Kim Phillips @ 2008-07-09 0:13 UTC (permalink / raw)
To: linuxppc-dev
delete obsolete device-type property, delete model property
(use compatible property instead), prepend "fsl," to Freescale
specific properties. Add nodes to device trees that are missing them,
and fix broken property values in other trees.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
changes from v3: sec.txt in new place following Kumar's latest
preference, cleaned up interrupt description and removed
interrupt-parent in documentation.
Documentation/powerpc/dts-bindings/fsl/sec.txt | 68 ++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8272ads.dts | 21 +++-----
arch/powerpc/boot/dts/mpc8313erdb.dts | 15 ++---
arch/powerpc/boot/dts/mpc8315erdb.dts | 15 +++---
arch/powerpc/boot/dts/mpc832x_mds.dts | 15 ++---
arch/powerpc/boot/dts/mpc832x_rdb.dts | 16 +++---
arch/powerpc/boot/dts/mpc8349emitx.dts | 12 ++---
arch/powerpc/boot/dts/mpc8349emitxgp.dts | 12 ++---
arch/powerpc/boot/dts/mpc834x_mds.dts | 15 ++----
arch/powerpc/boot/dts/mpc836x_mds.dts | 13 ++---
arch/powerpc/boot/dts/mpc8377_mds.dts | 13 ++---
arch/powerpc/boot/dts/mpc8377_rdb.dts | 14 ++---
arch/powerpc/boot/dts/mpc8378_mds.dts | 13 ++---
arch/powerpc/boot/dts/mpc8378_rdb.dts | 14 ++---
arch/powerpc/boot/dts/mpc8379_mds.dts | 13 ++---
arch/powerpc/boot/dts/mpc8379_rdb.dts | 14 ++---
arch/powerpc/boot/dts/mpc8536ds.dts | 12 ++++
arch/powerpc/boot/dts/mpc8541cds.dts | 11 ++++
arch/powerpc/boot/dts/mpc8544ds.dts | 11 ++++
arch/powerpc/boot/dts/mpc8548cds.dts | 11 ++++
arch/powerpc/boot/dts/mpc8555cds.dts | 11 ++++
arch/powerpc/boot/dts/mpc8568mds.dts | 14 ++---
arch/powerpc/boot/dts/mpc8572ds.dts | 12 ++++
arch/powerpc/boot/dts/sbc8349.dts | 14 ++---
arch/powerpc/boot/dts/sbc8548.dts | 11 ++++
arch/powerpc/boot/dts/tqm8541.dts | 11 ++++
arch/powerpc/boot/dts/tqm8555.dts | 11 ++++
27 files changed, 269 insertions(+), 143 deletions(-)
create mode 100644 Documentation/powerpc/dts-bindings/fsl/sec.txt
diff --git a/Documentation/powerpc/dts-bindings/fsl/sec.txt b/Documentation/powerpc/dts-bindings/fsl/sec.txt
new file mode 100644
index 0000000..2b6f2d4
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/sec.txt
@@ -0,0 +1,68 @@
+Freescale SoC SEC Security Engines
+
+Required properties:
+
+- compatible : Should contain entries for this and backward compatible
+ SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
+- reg : Offset and length of the register set for the device
+- interrupts : the SEC's interrupt number
+- fsl,num-channels : An integer representing the number of channels
+ available.
+- fsl,channel-fifo-len : An integer representing the number of
+ descriptor pointers each channel fetch fifo can hold.
+- fsl,exec-units-mask : The bitmask representing what execution units
+ (EUs) are available. It's a single 32-bit cell. EU information
+ should be encoded following the SEC's Descriptor Header Dword
+ EU_SEL0 field documentation, i.e. as follows:
+
+ bit 0 = reserved - should be 0
+ bit 1 = set if SEC has the ARC4 EU (AFEU)
+ bit 2 = set if SEC has the DES/3DES EU (DEU)
+ bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
+ bit 4 = set if SEC has the random number generator EU (RNG)
+ bit 5 = set if SEC has the public key EU (PKEU)
+ bit 6 = set if SEC has the AES EU (AESU)
+ bit 7 = set if SEC has the Kasumi EU (KEU)
+ bit 8 = set if SEC has the CRC EU (CRCU)
+ bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
+
+remaining bits are reserved for future SEC EUs.
+
+- fsl,descriptor-types-mask : The bitmask representing what descriptors
+ are available. It's a single 32-bit cell. Descriptor type information
+ should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
+ field documentation, i.e. as follows:
+
+ bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
+ bit 1 = set if SEC supports the ipsec_esp descriptor type
+ bit 2 = set if SEC supports the common_nonsnoop desc. type
+ bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
+ bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
+ bit 5 = set if SEC supports the srtp descriptor type
+ bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
+ bit 7 = set if SEC supports the pkeu_assemble descriptor type
+ bit 8 = set if SEC supports the aesu_key_expand_output desc.type
+ bit 9 = set if SEC supports the pkeu_ptmul descriptor type
+ bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
+ bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
+
+ ..and so on and so forth.
+
+Optional properties:
+
+- interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+
+Example:
+
+ /* MPC8548E */
+ crypto@30000 {
+ compatible = "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <29 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xfe>;
+ fsl,descriptor-types-mask = <0x12b0ebf>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8272ads.dts b/arch/powerpc/boot/dts/mpc8272ads.dts
index d27f8a7..2a1929a 100644
--- a/arch/powerpc/boot/dts/mpc8272ads.dts
+++ b/arch/powerpc/boot/dts/mpc8272ads.dts
@@ -237,22 +237,15 @@
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
};
-/* May need to remove if on a part without crypto engine */
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "fsl,mpc8272-talitos-sec2",
- "fsl,talitos-sec2",
- "fsl,talitos",
- "talitos";
- reg = <0x30000 0x10000>;
- interrupts = <11 8>;
+ compatible = "fsl,sec1.0";
+ reg = <0x40000 0x13000>;
+ interrupts = <47 0x8>;
interrupt-parent = <&PIC>;
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x7e>;
-/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
- descriptor-types-mask = <0x1010ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x1010415>;
};
};
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index b206843..3664fb5 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -254,17 +254,14 @@
};
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
- reg = <0x30000 0x7000>;
+ compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 2.2 */
- num-channels = <1>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x0000004c>;
- descriptor-types-mask = <0x0122003f>;
+ fsl,num-channels = <1>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x4c>;
+ fsl,descriptor-types-mask = <0x0122003f>;
};
/* IPIC
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index a40e806..f704513 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -241,17 +241,16 @@
};
crypto@30000 {
- model = "SEC3";
- device_type = "crypto";
- compatible = "talitos";
+ compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
+ "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
+ "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 3.0 geometry */
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x000001fe>;
- descriptor-types-mask = <0x03ab0ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x97c>;
+ fsl,descriptor-types-mask = <0x3ab0abf>;
};
sata@18000 {
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index b5968b6..7345743 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -150,17 +150,14 @@
};
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
- reg = <0x30000 0x7000>;
+ compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 2.2 */
- num-channels = <1>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x0000004c>;
- descriptor-types-mask = <0x0122003f>;
+ fsl,num-channels = <1>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x4c>;
+ fsl,descriptor-types-mask = <0x0122003f>;
};
ipic: pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index a798d86..0ebc20f 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -128,17 +128,15 @@
};
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
- reg = <0x30000 0x7000>;
+ compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 2.2 */
- num-channels = <1>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x0000004c>;
- descriptor-types-mask = <0x0122003f>;
+ interrupt-parent = <&pic>;
+ fsl,num-channels = <1>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x4c>;
+ fsl,descriptor-types-mask = <0x0122003f>;
};
ipic:pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index fc0f4c9..8dfab56 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -213,16 +213,14 @@
};
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
+ compatible = "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x0000007e>;
- descriptor-types-mask = <0x01010ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
};
ipic: pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index e6afb1d..49ca349 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -186,16 +186,14 @@
};
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
+ compatible = "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x0000007e>;
- descriptor-types-mask = <0x01010ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
};
ipic: pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 9c75c7c..ba586cb 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -228,20 +228,15 @@
interrupt-parent = <&ipic>;
};
- /* May need to remove if on a part without crypto engine */
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
+ compatible = "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x0000007e>;
- /* desc mask is for rev2.0,
- * we need runtime fixup for >2.0 */
- descriptor-types-mask = <0x01010ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
};
/* IPIC
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 8e33b15..3701dae 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -154,17 +154,14 @@
};
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
+ compatible = "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x0000007e>;
- /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
- descriptor-types-mask = <0x01010ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
};
ipic: pic@700 {
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 49a38cb..0a700cb 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -269,16 +269,15 @@
};
crypto@30000 {
- model = "SEC3";
- compatible = "talitos";
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 3.0 geometry */
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x000001fe>;
- descriptor-types-mask = <0x03ab0ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
};
sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 1f45387..ed137aa 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -248,17 +248,15 @@
};
crypto@30000 {
- model = "SEC3";
- device_type = "crypto";
- compatible = "talitos";
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 3.0 geometry */
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x000001fe>;
- descriptor-types-mask = <0x03ab0ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
};
sata@18000 {
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index 99ad49d..29c8c76 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -269,16 +269,15 @@
};
crypto@30000 {
- model = "SEC3";
- compatible = "talitos";
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 3.0 geometry */
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x000001fe>;
- descriptor-types-mask = <0x03ab0ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
};
sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 44e34d3..34a7f2f 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -248,17 +248,15 @@
};
crypto@30000 {
- model = "SEC3";
- device_type = "crypto";
- compatible = "talitos";
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 3.0 geometry */
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x000001fe>;
- descriptor-types-mask = <0x03ab0ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
};
/* IPIC
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index 980be81..d641a89 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -269,16 +269,15 @@
};
crypto@30000 {
- model = "SEC3";
- compatible = "talitos";
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 3.0 geometry */
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x000001fe>;
- descriptor-types-mask = <0x03ab0ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
};
sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index eeedf58..e4d7030 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -248,17 +248,15 @@
};
crypto@30000 {
- model = "SEC3";
- device_type = "crypto";
- compatible = "talitos";
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- /* Rev. 3.0 geometry */
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x000001fe>;
- descriptor-types-mask = <0x03ab0ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
};
sata@18000 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index 98ad27a..bf778fd 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -231,6 +231,18 @@
interrupt-parent = <&mpic>;
};
+ crypto@30000 {
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <11 0x8>;
+ interrupt-parent = <&ipic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
sata@18000 {
compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 21ad71b..c4469f1 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -189,6 +189,17 @@
interrupt-parent = <&mpic>;
};
+ crypto@30000 {
+ compatible = "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
+ };
+
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index 6cf533f..7d3829d 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -210,6 +210,17 @@
fsl,has-rstcr;
};
+ crypto@30000 {
+ compatible = "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xfe>;
+ fsl,descriptor-types-mask = <0x12b0ebf>;
+ };
+
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index d1fa6bb..d84466b 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -249,6 +249,17 @@
fsl,has-rstcr;
};
+ crypto@30000 {
+ compatible = "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xfe>;
+ fsl,descriptor-types-mask = <0x12b0ebf>;
+ };
+
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 6fc8059..e03a780 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -189,6 +189,17 @@
interrupt-parent = <&mpic>;
};
+ crypto@30000 {
+ compatible = "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
+ };
+
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index be9a289..9c30a34 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -231,16 +231,14 @@
};
crypto@30000 {
- device_type = "crypto";
- model = "SEC2";
- compatible = "talitos";
- reg = <0x30000 0xf000>;
+ compatible = "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
interrupts = <45 2>;
interrupt-parent = <&mpic>;
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0xfe>;
- descriptor-types-mask = <0x12b0ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xfe>;
+ fsl,descriptor-types-mask = <0x12b0ebf>;
};
mpic: pic@40000 {
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index cb06325..08c61e3 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -321,6 +321,18 @@
interrupt-parent = <&mpic>;
};
+ crypto@30000 {
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 5b76bb2..45f789b 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -221,19 +221,15 @@
interrupt-parent = <&ipic>;
};
- /* May need to remove if on a part without crypto engine */
crypto@30000 {
- model = "SEC2";
- compatible = "talitos";
+ compatible = "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
- num-channels = <4>;
- channel-fifo-len = <24>;
- exec-units-mask = <0x0000007e>;
- /* desc mask is for rev2.0,
- * we need runtime fixup for >2.0 */
- descriptor-types-mask = <0x01010ebf>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
};
/* IPIC
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 21cbacb..333552b 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -304,6 +304,17 @@
fsl,has-rstcr;
};
+ crypto@30000 {
+ compatible = "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xfe>;
+ fsl,descriptor-types-mask = <0x12b0ebf>;
+ };
+
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index d083a64..d76441e 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -200,6 +200,17 @@
interrupt-parent = <&mpic>;
};
+ crypto@30000 {
+ compatible = "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
+ };
+
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 96b0b94..6f7ea59 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -200,6 +200,17 @@
interrupt-parent = <&mpic>;
};
+ crypto@30000 {
+ compatible = "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
+ };
+
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
--
1.5.6
^ permalink raw reply related
* Re: [PATCH] powerpc: rework 4xx PTE access and TLB miss
From: Sean MacLennan @ 2008-07-09 0:53 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20080708055449.EDFDADDEF5@ozlabs.org>
On Tue, 08 Jul 2008 15:54:40 +1000
"Benjamin Herrenschmidt" <benh@kernel.crashing.org> wrote:
> This is some preliminary work to improve TLB management on SW loaded
> TLB powerpc platforms. This introduce support for non-atomic PTE
> operations in pgtable-ppc32.h and removes write back to the PTE from
> the TLB miss handlers. In addition, the DSI interrupt code no longer
> tries to fixup write permission, this is left to generic code, and
> _PAGE_HWWRITE is gone.
Ok, this version booted for me and passed some very rudimentary
regression tests.
Cheers,
Sean
^ permalink raw reply
* Re: [PATCH v2] Add MPC5200B base board mvBC-P
From: Grant Likely @ 2008-07-09 0:54 UTC (permalink / raw)
To: Andre Schwarz; +Cc: linux-ppc list
In-Reply-To: <48732588.8020907@matrix-vision.de>
On Tue, Jul 08, 2008 at 10:30:00AM +0200, Andre Schwarz wrote:
> David Gibson schrieb:
> > On Mon, Jul 07, 2008 at 10:14:29AM +0200, Andre Schwarz wrote:
> >
> >> The mvBlueCOUGAR-P is a MPC5200B based camera system with Intel Gigabit ethernet
> >> controller (using e1000). It's just another MPC5200_simple board.
> >>
> >
> > [snip]
> >
> >> + timer@600 { // General Purpose Timer
> >> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> >> + reg = <0x600 0x10>;
> >> + interrupts = <1 9 0>;
> >> + interrupt-parent = <&mpc5200_pic>;
> >> + fsl,has-wdt;
> >> + };
> >> +
> >> + timer@610 { // General Purpose Timer
> >> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> >> + cell-index = <1>;
> >>
> >
> > What shared resource is this cell-index value used to index?
> >
> > Also why does it not appear on the timer@600 but does on all the
> > others.
> >
> >
> Sorry - it's a copy paste problem. At first I only used timer0, i.e.
> this is the original entry.
> After Grant wanting me to have a look at the lite5200b.dts I copied over
> the rest of the dts nodes I also have on my board. On lite5200b.dts the
> cell-index is defined.
>
> If this is incorrect I'll remove it.
> Is cell-index inappropriate for the timer node ?
Yes, you can drop cell-index for fsl,mpc5200-gpt nodes.
g.
^ permalink raw reply
* [PATCH] Minor fixes for 85xxds and 8536ds board.
From: Jason Jin @ 2008-07-09 1:27 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev, Jason Jin
Remove the "uninitialized use" compile warning and
avoid potential runtime issue.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
---
arch/powerpc/platforms/85xx/mpc8536_ds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 9943816..69e2129 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -40,7 +40,7 @@ void __init mpc8536_ds_pic_init(void)
struct resource r;
struct device_node *np;
- np = of_find_node_by_type(np, "open-pic");
+ np = of_find_node_by_type(NULL, "open-pic");
if (np == NULL) {
printk(KERN_ERR "Could not find open-pic node\n");
return;
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 8b2d63d..25f41cd 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -64,7 +64,7 @@ void __init mpc85xx_ds_pic_init(void)
int cascade_irq;
#endif
- np = of_find_node_by_type(np, "open-pic");
+ np = of_find_node_by_type(NULL, "open-pic");
if (np == NULL) {
printk(KERN_ERR "Could not find open-pic node\n");
return;
--
1.5.4
^ permalink raw reply related
* Re: [PATCH] powerpc: rework 4xx PTE access and TLB miss
From: Benjamin Herrenschmidt @ 2008-07-09 1:53 UTC (permalink / raw)
To: Sean MacLennan; +Cc: linuxppc-dev
In-Reply-To: <20080708205315.4e463bdb@lappy.seanm.ca>
On Tue, 2008-07-08 at 20:53 -0400, Sean MacLennan wrote:
> On Tue, 08 Jul 2008 15:54:40 +1000
> "Benjamin Herrenschmidt" <benh@kernel.crashing.org> wrote:
>
> > This is some preliminary work to improve TLB management on SW loaded
> > TLB powerpc platforms. This introduce support for non-atomic PTE
> > operations in pgtable-ppc32.h and removes write back to the PTE from
> > the TLB miss handlers. In addition, the DSI interrupt code no longer
> > tries to fixup write permission, this is left to generic code, and
> > _PAGE_HWWRITE is gone.
>
> Ok, this version booted for me and passed some very rudimentary
> regression tests.
Thanks for testing.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v2] ibm_newemac: Add MII mode support to the EMAC RGMII bridge.
From: Benjamin Herrenschmidt @ 2008-07-09 3:23 UTC (permalink / raw)
To: Grant Erickson; +Cc: linuxppc-dev, sr, jgarzik
In-Reply-To: <1215529386-12749-1-git-send-email-gerickson@nuovations.com>
On Tue, 2008-07-08 at 08:03 -0700, Grant Erickson wrote:
> This patch adds support to the RGMII handler in the EMAC driver for
> the MII PHY mode such that device tree entries of the form `phy-mode = "mii";'
> are recognized and handled appropriately.
>
> While logically, in software, "gmii" and "mii" modes are the same,
> they are wired differently, so it makes sense to allow DTS authors to
> specify each explicitly.
>
> Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Jeff, I'd like to apply that (and other EMAC patches for 2.6.27, do you
have anything else pending ?) via my tree provided you give me your ack.
The reason is that the multicast fix one is going that way as it touches
other arch files, and subsequent ones are now likely to conflict.
Let me know if that's ok with you in which case I'll stick your ack in
there.
Cheers,
Ben.
> ---
> drivers/net/ibm_newemac/rgmii.c | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/ibm_newemac/rgmii.c b/drivers/net/ibm_newemac/rgmii.c
> index e32da3d..5acb006 100644
> --- a/drivers/net/ibm_newemac/rgmii.c
> +++ b/drivers/net/ibm_newemac/rgmii.c
> @@ -39,6 +39,7 @@
> #define RGMII_FER_RGMII(idx) (0x5 << ((idx) * 4))
> #define RGMII_FER_TBI(idx) (0x6 << ((idx) * 4))
> #define RGMII_FER_GMII(idx) (0x7 << ((idx) * 4))
> +#define RGMII_FER_MII(idx) RGMII_FER_GMII(idx)
>
> /* RGMIIx_SSR */
> #define RGMII_SSR_MASK(idx) (0x7 << ((idx) * 8))
> @@ -49,6 +50,7 @@
> static inline int rgmii_valid_mode(int phy_mode)
> {
> return phy_mode == PHY_MODE_GMII ||
> + phy_mode == PHY_MODE_MII ||
> phy_mode == PHY_MODE_RGMII ||
> phy_mode == PHY_MODE_TBI ||
> phy_mode == PHY_MODE_RTBI;
> @@ -63,6 +65,8 @@ static inline const char *rgmii_mode_name(int mode)
> return "TBI";
> case PHY_MODE_GMII:
> return "GMII";
> + case PHY_MODE_MII:
> + return "MII";
> case PHY_MODE_RTBI:
> return "RTBI";
> default:
> @@ -79,6 +83,8 @@ static inline u32 rgmii_mode_mask(int mode, int input)
> return RGMII_FER_TBI(input);
> case PHY_MODE_GMII:
> return RGMII_FER_GMII(input);
> + case PHY_MODE_MII:
> + return RGMII_FER_MII(input);
> case PHY_MODE_RTBI:
> return RGMII_FER_RTBI(input);
> default:
> --
> 1.5.4.3
^ permalink raw reply
* Re: [Cbe-oss-dev] [patch 02/02] powerpc/cell: add support for power button of future IBM cell blades
From: Benjamin Herrenschmidt @ 2008-07-09 3:35 UTC (permalink / raw)
To: Christian Krafft; +Cc: linuxppc-dev, cbe-oss-dev, arnd, Christian Krafft
In-Reply-To: <20080707185644.0d6c9757@de.ibm.com>
On Mon, 2008-07-07 at 18:56 +0200, Christian Krafft wrote:
> From: Christian Krafft <krafft@de.ibm.com>
>
> This patch adds support for the power button on future IBM cell blades.
> It actually doesn't shut down the machine. Instead it exposes an
> input device /dev/input/event0 to userspace which sends KEY_POWER
> if power button has been pressed.
> haldaemon actually recognizes the button, so a plattform independent acpid
> replacement should handle it correctly.
>
> Signed-off-by: Christian Krafft <krafft@de.ibm.com>
Sorry Christian, i'm still not too happy with this one.
There are two issues at hand here:
- The use of SELECT, that will be frowned on unfortunately.
- I'm not too sure it's very safe the way you do it. If I understand
correctly, you can get called for that sysreset at -any- time, including
when interrupts are off right ?
That means potentially, code that has interrupts off will be interrupted
by input_report/input_sync, which is really bad (may corrupt the input
layer internal list management for example).
You could solve both things with a little trick: Have the platform code
just basically set a global flag when the button was pressed and have a
module that depends on INPUT & INPUT_DEV poll for it (slowly pls) and do
the input report.
Ben.
> Index: linux.git/arch/powerpc/platforms/cell/Kconfig
> ===================================================================
> --- linux.git.orig/arch/powerpc/platforms/cell/Kconfig
> +++ linux.git/arch/powerpc/platforms/cell/Kconfig
> @@ -87,9 +87,12 @@ config PPC_IBM_CELL_BLADE_BUTTONS
> bool "IBM Cell Blade Buttons"
> depends on CBE_RAS && PPC_IBM_CELL_BLADE
> default y
> + select INPUT
> + select INPUT_EVDEV
> help
> Support Buttons on IBM Cell blades. This adds a method to
> - trigger system reset via front panel pinhole button.
> + trigger system reset via front panel pinhole button and
> + an input device for the power button.
>
> config CBE_THERM
> tristate "CBE thermal support"
> Index: linux.git/arch/powerpc/platforms/cell/ras.c
> ===================================================================
> --- linux.git.orig/arch/powerpc/platforms/cell/ras.c
> +++ linux.git/arch/powerpc/platforms/cell/ras.c
> @@ -14,6 +14,11 @@
> #include <linux/smp.h>
> #include <linux/reboot.h>
>
> +#ifdef CONFIG_PPC_IBM_CELL_BLADE_BUTTONS
> +#include <linux/input.h>
> +#include <linux/platform_device.h>
> +#endif /* CONFIG_PPC_IBM_CELL_BLADE_BUTTONS */
> +
> #include <asm/reg.h>
> #include <asm/io.h>
> #include <asm/prom.h>
> @@ -232,31 +237,76 @@ static struct notifier_block cbe_ptcal_r
>
> #ifdef CONFIG_PPC_IBM_CELL_BLADE_BUTTONS
> static int sysreset_hack;
> +static struct input_dev *button_dev;
> +static struct platform_device *button_pdev;
>
> static int __init cbe_sysreset_init(void)
> {
> + int ret = 0;
> + struct input_dev *dev;
> struct cbe_pmd_regs __iomem *regs;
>
> sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
> if (!sysreset_hack)
> - return 0;
> + goto out;
>
> regs = cbe_get_cpu_pmd_regs(0);
> if (!regs)
> - return 0;
> + goto out;
>
> /* Enable JTAG system-reset hack */
> out_be32(®s->fir_mode_reg,
> in_be32(®s->fir_mode_reg) |
> CBE_PMD_FIR_MODE_M8);
>
> - return 0;
> + dev = input_allocate_device();
> + if (!dev) {
> + ret = -ENOMEM;
> + printk(KERN_ERR "%s: Not enough memory\n", __func__);
> + goto out;
> + }
> +
> + set_bit(EV_KEY, dev->evbit);
> + set_bit(KEY_POWER, dev->keybit);
> +
> + dev->name = "Power Button";
> + dev->id.bustype = BUS_HOST;
> +
> + /* this makes the button look like an acpi power button
> + * no clue whether anyone relies on that though */
> + dev->id.product = 0x02;
> + dev->phys = "LNXPWRBN/button/input0";
> +
> + button_pdev = platform_device_register_simple("power_button", 0, NULL, 0);
> + if (IS_ERR(button_pdev)) {
> + ret = PTR_ERR(button_pdev);
> + goto out_free_input;
> + }
> +
> + dev->dev.parent = &button_pdev->dev;
> + ret = input_register_device(dev);
> +
> + if (ret) {
> + printk(KERN_ERR "%s: Failed to register device\n", __func__);
> + goto out_free_pdev;
> + }
> +
> + button_dev = dev;
> + goto out;
> +
> +out_free_pdev:
> + platform_device_unregister(button_pdev);
> +out_free_input:
> + input_free_device(dev);
> +out:
> + return ret;
> }
> device_initcall(cbe_sysreset_init);
>
> int cbe_sysreset_hack(void)
> {
> struct cbe_pmd_regs __iomem *regs;
> + u64 status;
>
> /*
> * The BMC can inject user triggered system reset exceptions,
> @@ -267,10 +317,20 @@ int cbe_sysreset_hack(void)
> regs = cbe_get_cpu_pmd_regs(0);
> if (!regs)
> return 0;
> - if (in_be64(®s->ras_esc_0) & 0x0000ffff) {
> + status = in_be64(®s->ras_esc_0);
> + if (status & 0x0000ffff) {
> out_be64(®s->ras_esc_0, 0);
> return 0;
> }
> + if (status & 0x00010000) {
> + out_be64(®s->ras_esc_0, 0);
> + if (!button_dev)
> + return 0;
> + input_report_key(button_dev, KEY_POWER, 1);
> + input_sync(button_dev);
> + input_report_key(button_dev, KEY_POWER, 0);
> + input_sync(button_dev);
> + }
> }
> return 1;
> }
>
^ permalink raw reply
* Re: powerpc/cell/cpufreq: add spu aware cpufreq governor
From: Benjamin Herrenschmidt @ 2008-07-09 3:41 UTC (permalink / raw)
To: Dave Jones
Cc: Stephen Rothwell, Arnd Bergmann, cpufreq, linuxppc-dev,
Jeremy Kerr, cbe-oss-dev
In-Reply-To: <20080708152728.GF4997@codemonkey.org.uk>
On Tue, 2008-07-08 at 11:27 -0400, Dave Jones wrote:
> On Tue, Jul 08, 2008 at 08:43:43AM +0200, Arnd Bergmann wrote:
> > On Monday 07 July 2008, Dave Jones wrote:
> > > One question I do have though, is how userspace scripts are supposed
> > > to know they're to echo cbe_spu_governor into the relevant parts of
> > > sysfs. I've not used anything with a cell. Do they expose the SPUs
> > > as regular CPUs, or do they show up in a different part of the tree?
> >
> > An SPU is very different from a CPU from the user perspective.
> > SPUs show up in /sys/devices/system/spus, and if a user wants to access
> > them, the "spufs" file system needs to be mounted in the system, by
> > convention on /spu.
>
> Ok, that should be fairly simple to write scripts for.
> All sounds good to me.
Can I add your Acked-by ?
Cheers,
Ben.
^ permalink raw reply
* Re: [patch 5/5] powerpc: Dont clear _PAGE_COHERENT when _PAGE_SAO is set
From: Benjamin Herrenschmidt @ 2008-07-09 3:46 UTC (permalink / raw)
To: Dave Kleikamp; +Cc: linuxppc-dev list
In-Reply-To: <20080707143011.729373219@linux.vnet.ibm.com>
On Mon, 2008-07-07 at 09:28 -0500, Dave Kleikamp wrote:
> plain text document attachment (dont_clobber_M.patch)
> Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
The old code looks bogus.. why clear M when G is set ? Only
I should have mattered.
I'll apply anyway as you aren't changing the existing behaviour here but
maybe you can shoot me a fixup patch that removes the _PAGE_GUARDED
condition completely here ?
It's legal to have G=1 M=1 pages and can even be useful under some
circumstances.
Cheers,
Ben.
> arch/powerpc/platforms/pseries/lpar.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> Index: b/arch/powerpc/platforms/pseries/lpar.c
> ===================================================================
> --- a/arch/powerpc/platforms/pseries/lpar.c
> +++ b/arch/powerpc/platforms/pseries/lpar.c
> @@ -305,7 +305,8 @@
> flags = 0;
>
> /* Make pHyp happy */
> - if (rflags & (_PAGE_GUARDED|_PAGE_NO_CACHE))
> + if ((rflags & _PAGE_GUARDED) ||
> + ((rflags & _PAGE_NO_CACHE) & !(rflags & _PAGE_WRITETHRU)))
> hpte_r &= ~_PAGE_COHERENT;
>
> lpar_rc = plpar_pte_enter(flags, hpte_group, hpte_v, hpte_r, &slot);
>
^ permalink raw reply
* Re: powerpc/cell/cpufreq: add spu aware cpufreq governor
From: Dave Jones @ 2008-07-09 3:57 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Stephen Rothwell, Arnd Bergmann, cpufreq, linuxppc-dev,
Jeremy Kerr, cbe-oss-dev
In-Reply-To: <1215574898.8970.308.camel@pasglop>
On Wed, Jul 09, 2008 at 01:41:38PM +1000, Ben Herrenschmidt wrote:
> On Tue, 2008-07-08 at 11:27 -0400, Dave Jones wrote:
> > On Tue, Jul 08, 2008 at 08:43:43AM +0200, Arnd Bergmann wrote:
> > > On Monday 07 July 2008, Dave Jones wrote:
> > > > One question I do have though, is how userspace scripts are supposed
> > > > to know they're to echo cbe_spu_governor into the relevant parts of
> > > > sysfs. I've not used anything with a cell. Do they expose the SPUs
> > > > as regular CPUs, or do they show up in a different part of the tree?
> > >
> > > An SPU is very different from a CPU from the user perspective.
> > > SPUs show up in /sys/devices/system/spus, and if a user wants to access
> > > them, the "spufs" file system needs to be mounted in the system, by
> > > convention on /spu.
> >
> > Ok, that should be fairly simple to write scripts for.
> > All sounds good to me.
>
> Can I add your Acked-by ?
Absolutely.
ACKed-by: Dave Jones <davej@redhat.com>
Dave
--
http://www.codemonkey.org.uk
^ permalink raw reply
* Re: Mikrotik RouterBoard 333
From: Grant Likely @ 2008-07-09 4:09 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20080708042631.GB7328@yookeroo.seuss>
On Tue, Jul 08, 2008 at 02:26:32PM +1000, David Gibson wrote:
> Does anyone on this list have contacts with the makers of this board?
>
> Its firmware apparently provides a flattened device tree to the OS.
> And while this step towards world domination is flattering, it's an
> example of what I feared when people first got enthusiastic about the
> idea of including flattened device trees in firmwares. The tree has
> not, AFAIK, been past this list, and has apparently not been reviewed
> by someone knowledgeable about device trees. In short, it's crap, and
> now that it's embedded in the firware we can't really fix it.
>
> So, to any embedded hardware/firmware vendors doing Linux ports out
> there. I certainly encourage you to use flattened device trees, but
> can I please suggest you put the blob into your kernel image (in the
> bootwrapper strictly speaking), rather than into the flashed firmware.
> It's a lot easier to fix mistakes that way.
>
> There are situations where it's nice to have the device tree in
> firmware, but there are many others where it buys little to nothing.
> People seem to be a bit overenthusaistic on the concept at the moment.
Total Ack! Allow me second that opinion.
g.
^ permalink raw reply
* libfdt: Increase namespace-pollution paranoia
From: David Gibson @ 2008-07-09 4:10 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
libfdt is supposed to easy to embed in projects all and sundry.
Often, it won't be practical to separate the embedded libfdt's
namespace from that of the surrounding project. Which means there can
be namespace conflicts between even libfdt's internal/static functions
and functions or macros coming from the surrounding project's headers
via libfdt_env.h.
This patch, therefore, renames a bunch of libfdt internal functions
and macros and makes a few other chances to reduce the chances of
namespace collisions with embedding projects. Specifically:
- Internal functions (even static ones) are now named _fdt_*()
- The type and (static) global for the error table in
fdt_strerror() gain an fdt_ prefix
- The unused macro PALIGN is removed
- The memeq and streq macros are removed and open-coded in the
users (they were only used once each)
- Other macros gain an FDT_ prefix
- To save some of the bulk from the previous change, an
FDT_TAGALIGN() macro is introduced, where FDT_TAGALIGN(x) ==
FDT_ALIGN(x, FDT_TAGSIZE)
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Index: dtc/libfdt/libfdt_internal.h
===================================================================
--- dtc.orig/libfdt/libfdt_internal.h 2008-07-09 12:09:08.000000000 +1000
+++ dtc/libfdt/libfdt_internal.h 2008-07-09 12:39:12.000000000 +1000
@@ -52,13 +52,10 @@
*/
#include <fdt.h>
-#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
-#define PALIGN(p, a) ((void *)ALIGN((unsigned long)(p), (a)))
+#define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
+#define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE))
-#define memeq(p, q, n) (memcmp((p), (q), (n)) == 0)
-#define streq(p, q) (strcmp((p), (q)) == 0)
-
-#define CHECK_HEADER(fdt) \
+#define FDT_CHECK_HEADER(fdt) \
{ \
int err; \
if ((err = fdt_check_header(fdt)) != 0) \
@@ -93,6 +90,6 @@
return (void *)(uintptr_t)_fdt_mem_rsv(fdt, n);
}
-#define SW_MAGIC (~FDT_MAGIC)
+#define FDT_SW_MAGIC (~FDT_MAGIC)
#endif /* _LIBFDT_INTERNAL_H */
Index: dtc/libfdt/fdt.c
===================================================================
--- dtc.orig/libfdt/fdt.c 2008-07-09 12:10:29.000000000 +1000
+++ dtc/libfdt/fdt.c 2008-07-09 12:39:29.000000000 +1000
@@ -63,7 +63,7 @@
return -FDT_ERR_BADVERSION;
if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)
return -FDT_ERR_BADVERSION;
- } else if (fdt_magic(fdt) == SW_MAGIC) {
+ } else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
/* Unfinished sequential-write blob */
if (fdt_size_dt_struct(fdt) == 0)
return -FDT_ERR_BADSTATE;
@@ -124,7 +124,7 @@
}
if (nextoffset)
- *nextoffset = ALIGN(offset, FDT_TAGSIZE);
+ *nextoffset = FDT_TAGALIGN(offset);
return tag;
}
@@ -184,14 +184,14 @@
const char *p;
for (p = strtab; p <= last; p++)
- if (memeq(p, s, len))
+ if (memcmp(p, s, len) == 0)
return p;
return NULL;
}
int fdt_move(const void *fdt, void *buf, int bufsize)
{
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
if (fdt_totalsize(fdt) > bufsize)
return -FDT_ERR_NOSPACE;
Index: dtc/libfdt/fdt_ro.c
===================================================================
--- dtc.orig/libfdt/fdt_ro.c 2008-07-09 12:10:02.000000000 +1000
+++ dtc/libfdt/fdt_ro.c 2008-07-09 12:16:36.000000000 +1000
@@ -55,8 +55,8 @@
#include "libfdt_internal.h"
-static int nodename_eq(const void *fdt, int offset,
- const char *s, int len)
+static int _fdt_nodename_eq(const void *fdt, int offset,
+ const char *s, int len)
{
const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1);
@@ -82,7 +82,7 @@
int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
{
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
*address = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->address);
*size = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->size);
return 0;
@@ -102,7 +102,7 @@
{
int depth;
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
for (depth = 0;
offset >= 0;
@@ -110,7 +110,7 @@
if (depth < 0)
return -FDT_ERR_NOTFOUND;
else if ((depth == 1)
- && nodename_eq(fdt, offset, name, namelen))
+ && _fdt_nodename_eq(fdt, offset, name, namelen))
return offset;
}
@@ -129,7 +129,7 @@
const char *p = path;
int offset = 0;
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
if (*path != '/')
return -FDT_ERR_BADPATH;
@@ -210,7 +210,7 @@
if (! prop)
goto fail;
namestroff = fdt32_to_cpu(prop->nameoff);
- if (streq(fdt_string(fdt, namestroff), name)) {
+ if (strcmp(fdt_string(fdt, namestroff), name) == 0) {
/* Found it! */
int len = fdt32_to_cpu(prop->len);
prop = fdt_offset_ptr(fdt, offset,
@@ -268,7 +268,7 @@
int offset, depth, namelen;
const char *name;
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
if (buflen < 2)
return -FDT_ERR_NOSPACE;
@@ -321,7 +321,7 @@
int offset, depth;
int supernodeoffset = -FDT_ERR_INTERNAL;
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
if (supernodedepth < 0)
return -FDT_ERR_NOTFOUND;
@@ -380,7 +380,7 @@
const void *val;
int len;
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
/* FIXME: The algorithm here is pretty horrible: we scan each
* property of a node in fdt_getprop(), then if that didn't
@@ -445,7 +445,7 @@
{
int offset, err;
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
/* FIXME: The algorithm here is pretty horrible: we scan each
* property of a node in fdt_node_check_compatible(), then if
Index: dtc/libfdt/fdt_rw.c
===================================================================
--- dtc.orig/libfdt/fdt_rw.c 2008-07-09 12:12:19.000000000 +1000
+++ dtc/libfdt/fdt_rw.c 2008-07-09 12:41:59.000000000 +1000
@@ -55,10 +55,10 @@
#include "libfdt_internal.h"
-static int _blocks_misordered(const void *fdt,
+static int _fdt_blocks_misordered(const void *fdt,
int mem_rsv_size, int struct_size)
{
- return (fdt_off_mem_rsvmap(fdt) < ALIGN(sizeof(struct fdt_header), 8))
+ return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))
|| (fdt_off_dt_struct(fdt) <
(fdt_off_mem_rsvmap(fdt) + mem_rsv_size))
|| (fdt_off_dt_strings(fdt) <
@@ -67,14 +67,14 @@
(fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));
}
-static int rw_check_header(void *fdt)
+static int _fdt_rw_check_header(void *fdt)
{
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
if (fdt_version(fdt) < 17)
return -FDT_ERR_BADVERSION;
- if (_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry),
- fdt_size_dt_struct(fdt)))
+ if (_fdt_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry),
+ fdt_size_dt_struct(fdt)))
return -FDT_ERR_BADLAYOUT;
if (fdt_version(fdt) > 17)
fdt_set_version(fdt, 17);
@@ -82,22 +82,22 @@
return 0;
}
-#define RW_CHECK_HEADER(fdt) \
+#define FDT_RW_CHECK_HEADER(fdt) \
{ \
int err; \
- if ((err = rw_check_header(fdt)) != 0) \
+ if ((err = _fdt_rw_check_header(fdt)) != 0) \
return err; \
}
-static inline int _blob_data_size(void *fdt)
+static inline int _fdt_data_size(void *fdt)
{
return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
}
-static int _blob_splice(void *fdt, void *splicepoint, int oldlen, int newlen)
+static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen)
{
char *p = splicepoint;
- char *end = (char *)fdt + _blob_data_size(fdt);
+ char *end = (char *)fdt + _fdt_data_size(fdt);
if (((p + oldlen) < p) || ((p + oldlen) > end))
return -FDT_ERR_BADOFFSET;
@@ -107,12 +107,12 @@
return 0;
}
-static int _blob_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p,
- int oldn, int newn)
+static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p,
+ int oldn, int newn)
{
int delta = (newn - oldn) * sizeof(*p);
int err;
- err = _blob_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
+ err = _fdt_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
if (err)
return err;
fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);
@@ -120,13 +120,13 @@
return 0;
}
-static int _blob_splice_struct(void *fdt, void *p,
- int oldlen, int newlen)
+static int _fdt_splice_struct(void *fdt, void *p,
+ int oldlen, int newlen)
{
int delta = newlen - oldlen;
int err;
- if ((err = _blob_splice(fdt, p, oldlen, newlen)))
+ if ((err = _fdt_splice(fdt, p, oldlen, newlen)))
return err;
fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);
@@ -134,20 +134,20 @@
return 0;
}
-static int _blob_splice_string(void *fdt, int newlen)
+static int _fdt_splice_string(void *fdt, int newlen)
{
void *p = (char *)fdt
+ fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
int err;
- if ((err = _blob_splice(fdt, p, 0, newlen)))
+ if ((err = _fdt_splice(fdt, p, 0, newlen)))
return err;
fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);
return 0;
}
-static int _find_add_string(void *fdt, const char *s)
+static int _fdt_find_add_string(void *fdt, const char *s)
{
char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);
const char *p;
@@ -161,7 +161,7 @@
return (p - strtab);
new = strtab + fdt_size_dt_strings(fdt);
- err = _blob_splice_string(fdt, len);
+ err = _fdt_splice_string(fdt, len);
if (err)
return err;
@@ -174,10 +174,10 @@
struct fdt_reserve_entry *re;
int err;
- RW_CHECK_HEADER(fdt);
+ FDT_RW_CHECK_HEADER(fdt);
re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt));
- err = _blob_splice_mem_rsv(fdt, re, 0, 1);
+ err = _fdt_splice_mem_rsv(fdt, re, 0, 1);
if (err)
return err;
@@ -191,19 +191,19 @@
struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n);
int err;
- RW_CHECK_HEADER(fdt);
+ FDT_RW_CHECK_HEADER(fdt);
if (n >= fdt_num_mem_rsv(fdt))
return -FDT_ERR_NOTFOUND;
- err = _blob_splice_mem_rsv(fdt, re, 1, 0);
+ err = _fdt_splice_mem_rsv(fdt, re, 1, 0);
if (err)
return err;
return 0;
}
-static int _resize_property(void *fdt, int nodeoffset, const char *name, int len,
- struct fdt_property **prop)
+static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name,
+ int len, struct fdt_property **prop)
{
int oldlen;
int err;
@@ -212,17 +212,16 @@
if (! (*prop))
return oldlen;
- if ((err = _blob_splice_struct(fdt, (*prop)->data,
- ALIGN(oldlen, FDT_TAGSIZE),
- ALIGN(len, FDT_TAGSIZE))))
+ if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
+ FDT_TAGALIGN(len))))
return err;
(*prop)->len = cpu_to_fdt32(len);
return 0;
}
-static int _add_property(void *fdt, int nodeoffset, const char *name, int len,
- struct fdt_property **prop)
+static int _fdt_add_property(void *fdt, int nodeoffset, const char *name,
+ int len, struct fdt_property **prop)
{
int proplen;
int nextoffset;
@@ -232,14 +231,14 @@
if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
return nextoffset;
- namestroff = _find_add_string(fdt, name);
+ namestroff = _fdt_find_add_string(fdt, name);
if (namestroff < 0)
return namestroff;
*prop = _fdt_offset_ptr_w(fdt, nextoffset);
- proplen = sizeof(**prop) + ALIGN(len, FDT_TAGSIZE);
+ proplen = sizeof(**prop) + FDT_TAGALIGN(len);
- err = _blob_splice_struct(fdt, *prop, 0, proplen);
+ err = _fdt_splice_struct(fdt, *prop, 0, proplen);
if (err)
return err;
@@ -255,7 +254,7 @@
int oldlen, newlen;
int err;
- RW_CHECK_HEADER(fdt);
+ FDT_RW_CHECK_HEADER(fdt);
namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);
if (!namep)
@@ -263,8 +262,8 @@
newlen = strlen(name);
- err = _blob_splice_struct(fdt, namep, ALIGN(oldlen+1, FDT_TAGSIZE),
- ALIGN(newlen+1, FDT_TAGSIZE));
+ err = _fdt_splice_struct(fdt, namep, FDT_TAGALIGN(oldlen+1),
+ FDT_TAGALIGN(newlen+1));
if (err)
return err;
@@ -278,11 +277,11 @@
struct fdt_property *prop;
int err;
- RW_CHECK_HEADER(fdt);
+ FDT_RW_CHECK_HEADER(fdt);
- err = _resize_property(fdt, nodeoffset, name, len, &prop);
+ err = _fdt_resize_property(fdt, nodeoffset, name, len, &prop);
if (err == -FDT_ERR_NOTFOUND)
- err = _add_property(fdt, nodeoffset, name, len, &prop);
+ err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
if (err)
return err;
@@ -295,14 +294,14 @@
struct fdt_property *prop;
int len, proplen;
- RW_CHECK_HEADER(fdt);
+ FDT_RW_CHECK_HEADER(fdt);
prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
if (! prop)
return len;
- proplen = sizeof(*prop) + ALIGN(len, FDT_TAGSIZE);
- return _blob_splice_struct(fdt, prop, proplen, 0);
+ proplen = sizeof(*prop) + FDT_TAGALIGN(len);
+ return _fdt_splice_struct(fdt, prop, proplen, 0);
}
int fdt_add_subnode_namelen(void *fdt, int parentoffset,
@@ -315,7 +314,7 @@
uint32_t tag;
uint32_t *endtag;
- RW_CHECK_HEADER(fdt);
+ FDT_RW_CHECK_HEADER(fdt);
offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
if (offset >= 0)
@@ -331,14 +330,14 @@
} while ((tag == FDT_PROP) || (tag == FDT_NOP));
nh = _fdt_offset_ptr_w(fdt, offset);
- nodelen = sizeof(*nh) + ALIGN(namelen+1, FDT_TAGSIZE) + FDT_TAGSIZE;
+ nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;
- err = _blob_splice_struct(fdt, nh, 0, nodelen);
+ err = _fdt_splice_struct(fdt, nh, 0, nodelen);
if (err)
return err;
nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
- memset(nh->name, 0, ALIGN(namelen+1, FDT_TAGSIZE));
+ memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
memcpy(nh->name, name, namelen);
endtag = (uint32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
*endtag = cpu_to_fdt32(FDT_END_NODE);
@@ -355,22 +354,22 @@
{
int endoffset;
- RW_CHECK_HEADER(fdt);
+ FDT_RW_CHECK_HEADER(fdt);
endoffset = _fdt_node_end_offset(fdt, nodeoffset);
if (endoffset < 0)
return endoffset;
- return _blob_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset),
- endoffset - nodeoffset, 0);
+ return _fdt_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset),
+ endoffset - nodeoffset, 0);
}
-static void _packblocks(const char *old, char *new,
- int mem_rsv_size, int struct_size)
+static void _fdt_packblocks(const char *old, char *new,
+ int mem_rsv_size, int struct_size)
{
int mem_rsv_off, struct_off, strings_off;
- mem_rsv_off = ALIGN(sizeof(struct fdt_header), 8);
+ mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);
struct_off = mem_rsv_off + mem_rsv_size;
strings_off = struct_off + struct_size;
@@ -396,7 +395,7 @@
const char *fdtend = fdtstart + fdt_totalsize(fdt);
char *tmp;
- CHECK_HEADER(fdt);
+ FDT_CHECK_HEADER(fdt);
mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
* sizeof(struct fdt_reserve_entry);
@@ -409,7 +408,7 @@
;
}
- if (!_blocks_misordered(fdt, mem_rsv_size, struct_size)) {
+ if (!_fdt_blocks_misordered(fdt, mem_rsv_size, struct_size)) {
/* no further work necessary */
err = fdt_move(fdt, buf, bufsize);
if (err)
@@ -421,7 +420,7 @@
}
/* Need to reorder */
- newsize = ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
+ newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
+ struct_size + fdt_size_dt_strings(fdt);
if (bufsize < newsize)
@@ -437,7 +436,7 @@
return -FDT_ERR_NOSPACE;
}
- _packblocks(fdt, tmp, mem_rsv_size, struct_size);
+ _fdt_packblocks(fdt, tmp, mem_rsv_size, struct_size);
memmove(buf, tmp, newsize);
fdt_set_magic(buf, FDT_MAGIC);
@@ -453,12 +452,12 @@
{
int mem_rsv_size;
- RW_CHECK_HEADER(fdt);
+ FDT_RW_CHECK_HEADER(fdt);
mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
* sizeof(struct fdt_reserve_entry);
- _packblocks(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));
- fdt_set_totalsize(fdt, _blob_data_size(fdt));
+ _fdt_packblocks(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));
+ fdt_set_totalsize(fdt, _fdt_data_size(fdt));
return 0;
}
Index: dtc/libfdt/fdt_sw.c
===================================================================
--- dtc.orig/libfdt/fdt_sw.c 2008-07-09 12:11:32.000000000 +1000
+++ dtc/libfdt/fdt_sw.c 2008-07-09 12:42:47.000000000 +1000
@@ -55,22 +55,22 @@
#include "libfdt_internal.h"
-static int sw_check_header(void *fdt)
+static int _fdt_sw_check_header(void *fdt)
{
- if (fdt_magic(fdt) != SW_MAGIC)
+ if (fdt_magic(fdt) != FDT_SW_MAGIC)
return -FDT_ERR_BADMAGIC;
/* FIXME: should check more details about the header state */
return 0;
}
-#define SW_CHECK_HEADER(fdt) \
+#define FDT_SW_CHECK_HEADER(fdt) \
{ \
int err; \
- if ((err = sw_check_header(fdt)) != 0) \
+ if ((err = _fdt_sw_check_header(fdt)) != 0) \
return err; \
}
-static void *grab_space(void *fdt, int len)
+static void *_fdt_grab_space(void *fdt, int len)
{
int offset = fdt_size_dt_struct(fdt);
int spaceleft;
@@ -94,13 +94,13 @@
memset(buf, 0, bufsize);
- fdt_set_magic(fdt, SW_MAGIC);
+ fdt_set_magic(fdt, FDT_SW_MAGIC);
fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION);
fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION);
fdt_set_totalsize(fdt, bufsize);
- fdt_set_off_mem_rsvmap(fdt, ALIGN(sizeof(struct fdt_header),
- sizeof(struct fdt_reserve_entry)));
+ fdt_set_off_mem_rsvmap(fdt, FDT_ALIGN(sizeof(struct fdt_header),
+ sizeof(struct fdt_reserve_entry)));
fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt));
fdt_set_off_dt_strings(fdt, bufsize);
@@ -112,7 +112,7 @@
struct fdt_reserve_entry *re;
int offset;
- SW_CHECK_HEADER(fdt);
+ FDT_SW_CHECK_HEADER(fdt);
if (fdt_size_dt_struct(fdt))
return -FDT_ERR_BADSTATE;
@@ -140,9 +140,9 @@
struct fdt_node_header *nh;
int namelen = strlen(name) + 1;
- SW_CHECK_HEADER(fdt);
+ FDT_SW_CHECK_HEADER(fdt);
- nh = grab_space(fdt, sizeof(*nh) + ALIGN(namelen, FDT_TAGSIZE));
+ nh = _fdt_grab_space(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen));
if (! nh)
return -FDT_ERR_NOSPACE;
@@ -155,9 +155,9 @@
{
uint32_t *en;
- SW_CHECK_HEADER(fdt);
+ FDT_SW_CHECK_HEADER(fdt);
- en = grab_space(fdt, FDT_TAGSIZE);
+ en = _fdt_grab_space(fdt, FDT_TAGSIZE);
if (! en)
return -FDT_ERR_NOSPACE;
@@ -165,7 +165,7 @@
return 0;
}
-static int find_add_string(void *fdt, const char *s)
+static int _fdt_find_add_string(void *fdt, const char *s)
{
char *strtab = (char *)fdt + fdt_totalsize(fdt);
const char *p;
@@ -193,13 +193,13 @@
struct fdt_property *prop;
int nameoff;
- SW_CHECK_HEADER(fdt);
+ FDT_SW_CHECK_HEADER(fdt);
- nameoff = find_add_string(fdt, name);
+ nameoff = _fdt_find_add_string(fdt, name);
if (nameoff == 0)
return -FDT_ERR_NOSPACE;
- prop = grab_space(fdt, sizeof(*prop) + ALIGN(len, FDT_TAGSIZE));
+ prop = _fdt_grab_space(fdt, sizeof(*prop) + FDT_TAGALIGN(len));
if (! prop)
return -FDT_ERR_NOSPACE;
@@ -218,10 +218,10 @@
uint32_t tag;
int offset, nextoffset;
- SW_CHECK_HEADER(fdt);
+ FDT_SW_CHECK_HEADER(fdt);
/* Add terminator */
- end = grab_space(fdt, sizeof(*end));
+ end = _fdt_grab_space(fdt, sizeof(*end));
if (! end)
return -FDT_ERR_NOSPACE;
*end = cpu_to_fdt32(FDT_END);
Index: dtc/libfdt/fdt_strerror.c
===================================================================
--- dtc.orig/libfdt/fdt_strerror.c 2008-07-09 12:21:10.000000000 +1000
+++ dtc/libfdt/fdt_strerror.c 2008-07-09 12:22:25.000000000 +1000
@@ -55,29 +55,29 @@
#include "libfdt_internal.h"
-struct errtabent {
+struct fdt_errtabent {
const char *str;
};
-#define ERRTABENT(val) \
+#define FDT_ERRTABENT(val) \
[(val)] = { .str = #val, }
-static struct errtabent errtable[] = {
- ERRTABENT(FDT_ERR_NOTFOUND),
- ERRTABENT(FDT_ERR_EXISTS),
- ERRTABENT(FDT_ERR_NOSPACE),
-
- ERRTABENT(FDT_ERR_BADOFFSET),
- ERRTABENT(FDT_ERR_BADPATH),
- ERRTABENT(FDT_ERR_BADSTATE),
-
- ERRTABENT(FDT_ERR_TRUNCATED),
- ERRTABENT(FDT_ERR_BADMAGIC),
- ERRTABENT(FDT_ERR_BADVERSION),
- ERRTABENT(FDT_ERR_BADSTRUCTURE),
- ERRTABENT(FDT_ERR_BADLAYOUT),
+static struct fdt_errtabent fdt_errtable[] = {
+ FDT_ERRTABENT(FDT_ERR_NOTFOUND),
+ FDT_ERRTABENT(FDT_ERR_EXISTS),
+ FDT_ERRTABENT(FDT_ERR_NOSPACE),
+
+ FDT_ERRTABENT(FDT_ERR_BADOFFSET),
+ FDT_ERRTABENT(FDT_ERR_BADPATH),
+ FDT_ERRTABENT(FDT_ERR_BADSTATE),
+
+ FDT_ERRTABENT(FDT_ERR_TRUNCATED),
+ FDT_ERRTABENT(FDT_ERR_BADMAGIC),
+ FDT_ERRTABENT(FDT_ERR_BADVERSION),
+ FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),
+ FDT_ERRTABENT(FDT_ERR_BADLAYOUT),
};
-#define ERRTABSIZE (sizeof(errtable) / sizeof(errtable[0]))
+#define FDT_ERRTABSIZE (sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))
const char *fdt_strerror(int errval)
{
@@ -85,8 +85,8 @@
return "<valid offset/length>";
else if (errval == 0)
return "<no error>";
- else if (errval > -ERRTABSIZE) {
- const char *s = errtable[-errval].str;
+ else if (errval > -FDT_ERRTABSIZE) {
+ const char *s = fdt_errtable[-errval].str;
if (s)
return s;
Index: dtc/libfdt/fdt_wip.c
===================================================================
--- dtc.orig/libfdt/fdt_wip.c 2008-07-09 12:24:04.000000000 +1000
+++ dtc/libfdt/fdt_wip.c 2008-07-09 12:24:29.000000000 +1000
@@ -72,7 +72,7 @@
return 0;
}
-static void nop_region(void *start, int len)
+static void _fdt_nop_region(void *start, int len)
{
uint32_t *p;
@@ -89,7 +89,7 @@
if (! prop)
return len;
- nop_region(prop, len + sizeof(*prop));
+ _fdt_nop_region(prop, len + sizeof(*prop));
return 0;
}
@@ -139,6 +139,7 @@
if (endoffset < 0)
return endoffset;
- nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0), endoffset - nodeoffset);
+ _fdt_nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0),
+ endoffset - nodeoffset);
return 0;
}
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* adeos support for kernel 2.6.20-ppc
From: jim.software @ 2008-07-09 4:13 UTC (permalink / raw)
To: linuxppc-embedded
I'm looking for an adeos ipipe patch for for the Linux kernel 2.6.20-ppc.
I have a MVME6100 board and its latest patch only supports the 2.6.20-ppc.
Thanks
Jim
^ permalink raw reply
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