* Re: MPC5200 PCI Issues
From: Tobias Knutsson @ 2009-02-06 20:38 UTC (permalink / raw)
To: Andre Schwarz; +Cc: linuxppc-dev
In-Reply-To: <498C3C81.7050500@matrix-vision.de>
Hi Andre,
I started the development with 2.6.28. Thanks for all of your
suggestions but I managed to find the solution today. The problem was
that the PCI-cards did not have class specified. Adding a fixup hook
to the cards in quirks.c resolved the issue.
On Fri, Feb 6, 2009 at 14:34, Andre Schwarz
<andre.schwarz@matrix-vision.de> wrote:
> Tobias,
>
> are you starting with 2.6.28 or are you upgrading ?
> My system runs very fine with 2.6.27 ....
>
> Tobias Knutsson wrote:
>>
>> I am currently trying to get an MPC5200-based board to run Linux
>> 2.6.28. Most of the devices are working, however i have some issues
>> with the PCI-bus. More precisely, the issue is that all of
>> the cards' IO-regions are mapped to address 0x0.
>> In my device tree I have the following:
>>
>> pci@f0000d00 {
>> #interrupt-cells =3D <1>;
>> #size-cells =3D <2>;
>> #address-cells =3D <3>;
>> device_type =3D "pci";
>> compatible =3D "fsl,mpc5200b-pci","fsl,mpc5200-pci";
>> reg =3D <0xf0000d00 0x100>;
>> interrupt-map-mask =3D <0xf800 0 0 7>;
>> interrupt-map =3D <0xb000 0 0 1 &mpc5200_pic 0 0 3 // MPC5=
200
>> 0xb000 0 0 2 &mpc5200_pic 0 0 3
>> 0xb000 0 0 3 &mpc5200_pic 0 0 3
>> 0xb000 0 0 4 &mpc5200_pic 0 0 3
>>
>
> What's this ? Is the MPC5200 interrupting itself ?
No, the PCI-bridge is connected to IRQ0
>>
>> 0xb800 0 0 1 &mpc5200_pic 1 1 3 // c64x0
>> 0xb800 0 0 2 &mpc5200_pic 1 1 3
>> 0xb800 0 0 3 &mpc5200_pic 1 1 3
>> 0xb800 0 0 4 &mpc5200_pic 1 1 3
>>
>
> Have you connected 4 IRQ lines to each c64x device ?
No, this is just some copy-paste leftovers that should be trimmed down
after some examination of the schematics.
>>
>> 0xc000 0 0 1 &mpc5200_pic 1 1 3 // c64x1
>> 0xc000 0 0 2 &mpc5200_pic 1 1 3
>> 0xc000 0 0 3 &mpc5200_pic 1 1 3
>> 0xc000 0 0 4 &mpc5200_pic 1 1 3
>>
>> 0xc800 0 0 1 &mpc5200_pic 1 1 3 // c64x2
>> 0xc800 0 0 2 &mpc5200_pic 1 1 3
>> 0xc800 0 0 3 &mpc5200_pic 1 1 3
>> 0xc800 0 0 4 &mpc5200_pic 1 1 3
>>
>> 0xd000 0 0 1 &mpc5200_pic 1 1 3 // c64x3
>> 0xd000 0 0 2 &mpc5200_pic 1 1 3
>> 0xd000 0 0 3 &mpc5200_pic 1 1 3
>> 0xd000 0 0 4 &mpc5200_pic 1 1 3
>>
>> 0xd800 0 0 1 &mpc5200_pic 1 1 3 // c64x4
>> 0xd800 0 0 2 &mpc5200_pic 1 1 3
>> 0xd800 0 0 3 &mpc5200_pic 1 1 3
>> 0xd800 0 0 4 &mpc5200_pic 1 1 3>;
>>
>>
>
> I'm using an external FPGA and an e1000 NIC connectedt to IRQ2 and IRQ3 :
>
> interrupt-map =3D <0x5800 0 0 1 &mpc5200_pic 1 2 3
> 0x5000 0 0 1 &mpc5200_pic =
1 3
> 3>;
>
>
>> clock-frequency =3D <0x1e84800>; //<0>; // From boot load=
er
>> interrupts =3D <2 8 0 2 9 0 2 10 0>;
>> interrupt-parent =3D <&mpc5200_pic>;
>> bus-range =3D <0 0>;
>> ranges =3D <0x02000000 0 0x50000000 0x50000000 0 0x1000000=
0
>> 0x01000000 0 0x00000000 0x60000000 0 0x01000000>=
;
>> };
>>
>
> I'm using a 3 liner :
>
> ranges =3D <0x42000000 0 0x80000000 0x80000000 0 0x20000000
> 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
> 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
>
>> The cards' memory regions are mapped out fine to different addresses
>> in the 0x50000000-0x60000000 range. However, the IO regions are all mapp=
ed
>> to zero.
>>
>>
>
> Are you c64x devices responding properly ? Is IO access enabled in the PC=
I
> command register ?
> Are they announcing a reasonable window ? How man KBytes ?
>>
>> Do you have any idea on what could be wrong or in which direction I
>> should be looking?
>>
>>
>>
>
> Hopefully something is useful to you.
>
> regards,
> Andre
>
>
> MATRIX VISION GmbH, Talstra=DFe 16, DE-71570 Oppenweiler
> Registergericht: Amtsgericht Stuttgart, HRB 271090
> Gesch=E4ftsf=FChrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner,
> Hans-Joachim Reich
>
--=20
H=E4lsningar/Regards
Tobias Knutsson
^ permalink raw reply
* [PATCH v5] Add PPC/4xx "ibm,sdram-4xx-ddr2" EDAC MC Driver
From: Grant Erickson @ 2009-02-06 21:03 UTC (permalink / raw)
To: linux-kernel; +Cc: linuxppc-dev, Andrew Morton, bluesmoke-devel, Doug Thompson
This adds support for an EDAC memory controller adaptation driver for
the "ibm,sdram-4xx-ddr2" ECC controller realized in the AMCC PowerPC
405EX[r].
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
---
At present, this driver has been developed and tested against the
controller realization in the AMCC PPC405EX[r] on the AMCC Kilauea and
Haleakala boards (256 MiB w/o ECC memory soldered onto the board) and
a proprietary board based on those designs (128 MiB ECC memory, also
soldered onto the board).
In the future, dynamic feature detection and handling needs to be
added for the other realizations of this controller found in the
440SP, 440SPe, 460EX, 460GT and 460SX.
Eventually, this driver will likely be evolved and adapted to the
above variant realizations of this controller as well as broken apart
to handle the other known ECC-capable controllers prevalent in other
PPC4xx processors:
- IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
- IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
- Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
Patch v2 removes the 'type' field from the of_device_id match
structure to reflect the corresponding removal of the 'device_type'
field from the device tree node.
Patch v3 incorporates feedback from Josh Boyer regarding compliance of
switch statements with Linux coding style, removing gratuitous printk
wrappers, and using the DCR mapping from the device tree rather than
using a fixed mapping.
Patch v4 resync's the patch against the top-of-tree as 'git apply' was
reporting "fatal: new file drivers/edac/ppc4xx_edac.h depends on old
contents".
Patch v5 incorporates feedback from Andrew Morton, including changing
the comment style from Doxygen to kernel-doc, reducing gratuitous
parameter checking in ppc4xx_edac_mc_init, eliminated an unneeded void *
cast in the ISR, changed pfn/poff to page/offset and use unsigned
int rather than size_t for loop counters with associated printf format
specifier changes.
drivers/edac/Kconfig | 9 +
drivers/edac/Makefile | 2 +-
drivers/edac/ppc4xx_edac.c | 1448 ++++++++++++++++++++++++++++++++++++++++++++
drivers/edac/ppc4xx_edac.h | 172 ++++++
4 files changed, 1630 insertions(+), 1 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index eee47fd..ad3e753 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -174,4 +174,13 @@ config EDAC_CELL
Cell Broadband Engine internal memory controller
on platform without a hypervisor
+config EDAC_PPC4XX
+ tristate "PPC4xx IBM DDR2 Memory Controller"
+ depends on EDAC_MM_EDAC && 4xx
+ help
+ This enables support for EDAC on the ECC memory used
+ with the IBM DDR2 memory controller found in various
+ PowerPC 4xx embedded processors such as the 405EX[r],
+ 440SP, 440SPe, 460EX, 460GT and 460SX.
+
endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index b751969..a5fdcf0 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -34,4 +34,4 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac.o
obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
obj-$(CONFIG_EDAC_CELL) += cell_edac.o
-
+obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c
new file mode 100644
index 0000000..d244f24
--- /dev/null
+++ b/drivers/edac/ppc4xx_edac.c
@@ -0,0 +1,1448 @@
+/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#include <linux/edac.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/types.h>
+
+#include <asm/dcr.h>
+
+#include "edac_core.h"
+#include "ppc4xx_edac.h"
+
+/*
+ * This file implements a driver for monitoring and handling events
+ * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
+ * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
+ *
+ * As realized in the 405EX[r], this controller features:
+ *
+ * - Support for registered- and non-registered DDR1 and DDR2 memory.
+ * - 32-bit or 16-bit memory interface with optional ECC.
+ *
+ * o ECC support includes:
+ *
+ * - 4-bit SEC/DED
+ * - Aligned-nibble error detect
+ * - Bypass mode
+ *
+ * - Two (2) memory banks/ranks.
+ * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
+ * bank/rank in 16-bit mode.
+ *
+ * As realized in the 440SP and 440SPe, this controller changes/adds:
+ *
+ * - 64-bit or 32-bit memory interface with optional ECC.
+ *
+ * o ECC support includes:
+ *
+ * - 8-bit SEC/DED
+ * - Aligned-nibble error detect
+ * - Bypass mode
+ *
+ * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
+ * per bank/rank in 32-bit mode.
+ *
+ * As realized in the 460EX and 460GT, this controller changes/adds:
+ *
+ * - 64-bit or 32-bit memory interface with optional ECC.
+ *
+ * o ECC support includes:
+ *
+ * - 8-bit SEC/DED
+ * - Aligned-nibble error detect
+ * - Bypass mode
+ *
+ * - Four (4) memory banks/ranks.
+ * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
+ * per bank/rank in 32-bit mode.
+ *
+ * At present, this driver has ONLY been tested against the controller
+ * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
+ * boards (256 MiB w/o ECC memory soldered onto the board) and a
+ * proprietary board based on those designs (128 MiB ECC memory, also
+ * soldered onto the board).
+ *
+ * Dynamic feature detection and handling needs to be added for the
+ * other realizations of this controller listed above.
+ *
+ * Eventually, this driver will likely be adapted to the above variant
+ * realizations of this controller as well as broken apart to handle
+ * the other known ECC-capable controllers prevalent in other 4xx
+ * processors:
+ *
+ * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
+ * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
+ * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
+ *
+ * For this controller, unfortunately, correctable errors report
+ * nothing more than the beat/cycle and byte/lane the correction
+ * occurred on and the check bit group that covered the error.
+ *
+ * In contrast, uncorrectable errors also report the failing address,
+ * the bus master and the transaction direction (i.e. read or write)
+ *
+ * Regardless of whether the error is a CE or a UE, we report the
+ * following pieces of information in the driver-unique message to the
+ * EDAC subsystem:
+ *
+ * - Device tree path
+ * - Bank(s)
+ * - Check bit error group
+ * - Beat(s)/lane(s)
+ */
+
+/* Preprocessor Definitions */
+
+#define EDAC_OPSTATE_INT_STR "interrupt"
+#define EDAC_OPSTATE_POLL_STR "polled"
+#define EDAC_OPSTATE_UNKNOWN_STR "unknown"
+
+#define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac"
+#define PPC4XX_EDAC_MODULE_REVISION "v1.0.0 " __DATE__
+
+#define PPC4XX_EDAC_MESSAGE_SIZE 256
+
+/*
+ * Kernel logging without an EDAC instance
+ */
+#define ppc4xx_edac_printk(level, fmt, arg...) \
+ edac_printk(level, "PPC4xx MC", fmt, ##arg)
+
+/*
+ * Kernel logging with an EDAC instance
+ */
+#define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
+ edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
+
+/*
+ * Macros to convert bank configuration size enumerations into MiB and
+ * page values.
+ */
+#define SDRAM_MBCF_SZ_MiB_MIN 4
+#define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \
+ << (SDRAM_MBCF_SZ_DECODE(n)))
+#define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \
+ << (20 - PAGE_SHIFT + \
+ SDRAM_MBCF_SZ_DECODE(n)))
+
+/*
+ * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
+ * indirectly acccessed and have a base and length defined by the
+ * device tree. The base can be anything; however, we expect the
+ * length to be precisely two registers, the first for the address
+ * window and the second for the data window.
+ */
+#define SDRAM_DCR_RESOURCE_LEN 2
+#define SDRAM_DCR_ADDR_OFFSET 0
+#define SDRAM_DCR_DATA_OFFSET 1
+
+/*
+ * Device tree interrupt indices
+ */
+#define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
+#define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
+
+/* Type Definitions */
+
+/*
+ * PPC4xx SDRAM memory controller private instance data
+ */
+struct ppc4xx_edac_pdata {
+ dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */
+ struct {
+ int sec; /* Single-bit correctable error IRQ assigned */
+ int ded; /* Double-bit detectable error IRQ assigned */
+ } irqs;
+};
+
+/*
+ * Various status data gathered and manipulated when checking and
+ * reporting ECC status.
+ */
+struct ppc4xx_ecc_status {
+ u32 ecces;
+ u32 besr;
+ u32 bearh;
+ u32 bearl;
+ u32 wmirq;
+};
+
+/* Function Prototypes */
+
+static int ppc4xx_edac_probe(struct of_device *device,
+ const struct of_device_id *device_id);
+static int ppc4xx_edac_remove(struct of_device *device);
+
+/* Global Variables */
+
+/*
+ * Device tree node type and compatible tuples this driver can match
+ * on.
+ */
+static struct of_device_id ppc4xx_edac_match[] = {
+ {
+ .compatible = "ibm,sdram-4xx-ddr2"
+ },
+ { }
+};
+
+static struct of_platform_driver ppc4xx_edac_driver = {
+ .match_table = ppc4xx_edac_match,
+ .probe = ppc4xx_edac_probe,
+ .remove = ppc4xx_edac_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = PPC4XX_EDAC_MODULE_NAME
+ }
+};
+
+/*
+ * TODO: The row and channel parameters likely need to be dynamically
+ * set based on the aforementioned variant controller realizations.
+ */
+static const unsigned ppc4xx_edac_nr_csrows = 2;
+static const unsigned ppc4xx_edac_nr_chans = 1;
+
+/*
+ * Strings associated with PLB master IDs capable of being posted in
+ * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors.
+ */
+static const char * const ppc4xx_plb_masters[9] = {
+ [SDRAM_PLB_M0ID_ICU] = "ICU",
+ [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
+ [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
+ [SDRAM_PLB_M0ID_DMA] = "DMA",
+ [SDRAM_PLB_M0ID_DCU] = "DCU",
+ [SDRAM_PLB_M0ID_OPB] = "OPB",
+ [SDRAM_PLB_M0ID_MAL] = "MAL",
+ [SDRAM_PLB_M0ID_SEC] = "SEC",
+ [SDRAM_PLB_M0ID_AHB] = "AHB"
+};
+
+/**
+ * mfsdram - read and return controller register data
+ * @dcr_host: A pointer to the DCR mapping.
+ * @idcr_n: The indirect DCR register to read.
+ *
+ * This routine reads and returns the data associated with the
+ * controller's specified indirect DCR register.
+ *
+ * Returns the read data.
+ */
+static inline u32
+mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n)
+{
+ return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
+ dcr_host->base + SDRAM_DCR_DATA_OFFSET,
+ idcr_n);
+}
+
+/**
+ * mtsdram - write controller register data
+ * @dcr_host: A pointer to the DCR mapping.
+ * @idcr_n: The indirect DCR register to write.
+ * @value: The data to write.
+ *
+ * This routine writes the provided data to the controller's specified
+ * indirect DCR register.
+ */
+static inline void
+mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value)
+{
+ return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
+ dcr_host->base + SDRAM_DCR_DATA_OFFSET,
+ idcr_n,
+ value);
+}
+
+/**
+ * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
+ * @status: A pointer to the ECC status structure to check for an
+ * ECC bank error.
+ * @bank: The bank to check for an ECC error.
+ *
+ * This routine determines whether the specified bank has an ECC
+ * error.
+ *
+ * Returns true if the specified bank has an ECC error; otherwise,
+ * false.
+ */
+static bool
+ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status,
+ unsigned int bank)
+{
+ switch (bank) {
+ case 0:
+ return status->ecces & SDRAM_ECCES_BK0ER;
+ case 1:
+ return status->ecces & SDRAM_ECCES_BK1ER;
+ default:
+ return false;
+ }
+}
+
+/**
+ * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
+ * @mci: A pointer to the EDAC memory controller instance associated
+ * with the bank message being generated.
+ * @status: A pointer to the ECC status structure to generate the
+ * message from.
+ * @buffer: A pointer to the buffer in which to generate the
+ * message.
+ * @size: The size, in bytes, of space available in buffer.
+ *
+ * This routine generates to the provided buffer the portion of the
+ * driver-unique report message associated with the ECCESS[BKNER]
+ * field of the specified ECC status.
+ *
+ * Returns the number of characters generated on success; otherwise, <
+ * 0 on error.
+ */
+static int
+ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status,
+ char *buffer,
+ size_t size)
+{
+ int n, total = 0;
+ unsigned int row, rows;
+
+ n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name);
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+
+ for (rows = 0, row = 0; row < mci->nr_csrows; row++)
+ if (ppc4xx_edac_check_bank_error(status, row)) {
+ n = snprintf(buffer, size,
+ "%s%u",
+ (rows++ ? ", " : ""), row);
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+ }
+
+ n = snprintf(buffer, size, "%s; ", rows ? "" : "None");
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+
+ fail:
+ return total;
+}
+
+/**
+ * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
+ * @mci: A pointer to the EDAC memory controller instance associated
+ * with the checkbit message being generated.
+ * @status: A pointer to the ECC status structure to generate the
+ * message from.
+ * @buffer: A pointer to the buffer in which to generate the
+ * message.
+ * @size: The size, in bytes, of space available in buffer.
+ *
+ * This routine generates to the provided buffer the portion of the
+ * driver-unique report message associated with the ECCESS[CKBER]
+ * field of the specified ECC status.
+ *
+ * Returns the number of characters generated on success; otherwise, <
+ * 0 on error.
+ */
+static int
+ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status,
+ char *buffer,
+ size_t size)
+{
+ const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
+ const char *ckber = NULL;
+
+ switch (status->ecces & SDRAM_ECCES_CKBER_MASK) {
+ case SDRAM_ECCES_CKBER_NONE:
+ ckber = "None";
+ break;
+ case SDRAM_ECCES_CKBER_32_ECC_0_3:
+ ckber = "ECC0:3";
+ break;
+ case SDRAM_ECCES_CKBER_32_ECC_4_8:
+ switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) &
+ SDRAM_MCOPT1_WDTH_MASK) {
+ case SDRAM_MCOPT1_WDTH_16:
+ ckber = "ECC0:3";
+ break;
+ case SDRAM_MCOPT1_WDTH_32:
+ ckber = "ECC4:8";
+ break;
+ default:
+ ckber = "Unknown";
+ break;
+ }
+ break;
+ case SDRAM_ECCES_CKBER_32_ECC_0_8:
+ ckber = "ECC0:8";
+ break;
+ default:
+ ckber = "Unknown";
+ break;
+ }
+
+ return snprintf(buffer, size, "Checkbit Error: %s", ckber);
+}
+
+/**
+ * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
+ * @mci: A pointer to the EDAC memory controller instance associated
+ * with the byte lane message being generated.
+ * @status: A pointer to the ECC status structure to generate the
+ * message from.
+ * @buffer: A pointer to the buffer in which to generate the
+ * message.
+ * @size: The size, in bytes, of space available in buffer.
+ *
+ * This routine generates to the provided buffer the portion of the
+ * driver-unique report message associated with the ECCESS[BNCE]
+ * field of the specified ECC status.
+ *
+ * Returns the number of characters generated on success; otherwise, <
+ * 0 on error.
+ */
+static int
+ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status,
+ char *buffer,
+ size_t size)
+{
+ int n, total = 0;
+ unsigned int lane, lanes;
+ const unsigned int first_lane = 0;
+ const unsigned int lane_count = 16;
+
+ n = snprintf(buffer, size, "; Byte Lane Errors: ");
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+
+ for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
+ if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
+ n = snprintf(buffer, size,
+ "%s%u",
+ (lanes++ ? ", " : ""), lane);
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+ }
+ }
+
+ n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+
+ fail:
+ return total;
+}
+
+/**
+ * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
+ * @mci: A pointer to the EDAC memory controller instance associated
+ * with the ECCES message being generated.
+ * @status: A pointer to the ECC status structure to generate the
+ * message from.
+ * @buffer: A pointer to the buffer in which to generate the
+ * message.
+ * @size: The size, in bytes, of space available in buffer.
+ *
+ * This routine generates to the provided buffer the portion of the
+ * driver-unique report message associated with the ECCESS register of
+ * the specified ECC status.
+ *
+ * Returns the number of characters generated on success; otherwise, <
+ * 0 on error.
+ */
+static int
+ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status,
+ char *buffer,
+ size_t size)
+{
+ int n, total = 0;
+
+ n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size);
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+
+ n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size);
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+
+ n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size);
+
+ if (n < 0 || n >= size)
+ goto fail;
+
+ buffer += n;
+ size -= n;
+ total += n;
+
+ fail:
+ return total;
+}
+
+/**
+ * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
+ * @mci: A pointer to the EDAC memory controller instance associated
+ * with the PLB message being generated.
+ * @status: A pointer to the ECC status structure to generate the
+ * message from.
+ * @buffer: A pointer to the buffer in which to generate the
+ * message.
+ * @size: The size, in bytes, of space available in buffer.
+ *
+ * This routine generates to the provided buffer the portion of the
+ * driver-unique report message associated with the PLB-related BESR
+ * and/or WMIRQ registers of the specified ECC status.
+ *
+ * Returns the number of characters generated on success; otherwise, <
+ * 0 on error.
+ */
+static int
+ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status,
+ char *buffer,
+ size_t size)
+{
+ unsigned int master;
+ bool read;
+
+ if ((status->besr & SDRAM_BESR_MASK) == 0)
+ return 0;
+
+ if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE)
+ return 0;
+
+ read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ);
+
+ master = SDRAM_BESR_M0ID_DECODE(status->besr);
+
+ return snprintf(buffer, size,
+ "%s error w/ PLB master %u \"%s\"; ",
+ (read ? "Read" : "Write"),
+ master,
+ (((master >= SDRAM_PLB_M0ID_FIRST) &&
+ (master <= SDRAM_PLB_M0ID_LAST)) ?
+ ppc4xx_plb_masters[master] : "UNKNOWN"));
+}
+
+/**
+ * ppc4xx_edac_generate_message - generate interpretted status message
+ * @mci: A pointer to the EDAC memory controller instance associated
+ * with the driver-unique message being generated.
+ * @status: A pointer to the ECC status structure to generate the
+ * message from.
+ * @buffer: A pointer to the buffer in which to generate the
+ * message.
+ * @size: The size, in bytes, of space available in buffer.
+ *
+ * This routine generates to the provided buffer the driver-unique
+ * EDAC report message from the specified ECC status.
+ */
+static void
+ppc4xx_edac_generate_message(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status,
+ char *buffer,
+ size_t size)
+{
+ int n;
+
+ if (buffer == NULL || size == 0)
+ return;
+
+ n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size);
+
+ if (n < 0 || n >= size)
+ return;
+
+ buffer += n;
+ size -= n;
+
+ ppc4xx_edac_generate_plb_message(mci, status, buffer, size);
+}
+
+#ifdef DEBUG
+/**
+ * ppc4xx_ecc_dump_status - dump controller ECC status registers
+ * @mci: A pointer to the EDAC memory controller instance
+ * associated with the status being dumped.
+ * @status: A pointer to the ECC status structure to generate the
+ * dump from.
+ *
+ * This routine dumps to the kernel log buffer the raw and
+ * interpretted specified ECC status.
+ */
+static void
+ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status)
+{
+ char message[PPC4XX_EDAC_MESSAGE_SIZE];
+
+ ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
+
+ ppc4xx_edac_mc_printk(KERN_INFO, mci,
+ "\n"
+ "\tECCES: 0x%08x\n"
+ "\tWMIRQ: 0x%08x\n"
+ "\tBESR: 0x%08x\n"
+ "\tBEAR: 0x%08x%08x\n"
+ "\t%s\n",
+ status->ecces,
+ status->wmirq,
+ status->besr,
+ status->bearh,
+ status->bearl,
+ message);
+}
+#endif /* DEBUG */
+
+/**
+ * ppc4xx_ecc_get_status - get controller ECC status
+ * @mci: A pointer to the EDAC memory controller instance
+ * associated with the status being retrieved.
+ * @status: A pointer to the ECC status structure to populate the
+ * ECC status with.
+ *
+ * This routine reads and masks, as appropriate, all the relevant
+ * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
+ * While we read all of them, for correctable errors, we only expect
+ * to deal with ECCES. For uncorrectable errors, we expect to deal
+ * with all of them.
+ */
+static void
+ppc4xx_ecc_get_status(const struct mem_ctl_info *mci,
+ struct ppc4xx_ecc_status *status)
+{
+ const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
+ const dcr_host_t *dcr_host = &pdata->dcr_host;
+
+ status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK;
+ status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK;
+ status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK;
+ status->bearl = mfsdram(dcr_host, SDRAM_BEARL);
+ status->bearh = mfsdram(dcr_host, SDRAM_BEARH);
+}
+
+/**
+ * ppc4xx_ecc_clear_status - clear controller ECC status
+ * @mci: A pointer to the EDAC memory controller instance
+ * associated with the status being cleared.
+ * @status: A pointer to the ECC status structure containing the
+ * values to write to clear the ECC status.
+ *
+ * This routine clears--by writing the masked (as appropriate) status
+ * values back to--the status registers that deal with
+ * ibm,sdram-4xx-ddr2 ECC errors.
+ */
+static void
+ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status)
+{
+ const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
+ const dcr_host_t *dcr_host = &pdata->dcr_host;
+
+ mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK);
+ mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK);
+ mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK);
+ mtsdram(dcr_host, SDRAM_BEARL, 0);
+ mtsdram(dcr_host, SDRAM_BEARH, 0);
+}
+
+/**
+ * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
+ * @mci: A pointer to the EDAC memory controller instance
+ * associated with the correctable error being handled and reported.
+ * @status: A pointer to the ECC status structure associated with
+ * the correctable error being handled and reported.
+ *
+ * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
+ * correctable error. Per the aforementioned discussion, there's not
+ * enough status available to use the full EDAC correctable error
+ * interface, so we just pass driver-unique message to the "no info"
+ * interface.
+ */
+static void
+ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status)
+{
+ int row;
+ char message[PPC4XX_EDAC_MESSAGE_SIZE];
+
+ ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
+
+ for (row = 0; row < mci->nr_csrows; row++)
+ if (ppc4xx_edac_check_bank_error(status, row))
+ edac_mc_handle_ce_no_info(mci, message);
+}
+
+/**
+ * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
+ * @mci: A pointer to the EDAC memory controller instance
+ * associated with the uncorrectable error being handled and
+ * reported.
+ * @status: A pointer to the ECC status structure associated with
+ * the uncorrectable error being handled and reported.
+ *
+ * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
+ * uncorrectable error.
+ */
+static void
+ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
+ const struct ppc4xx_ecc_status *status)
+{
+ const u64 bear = ((u64)status->bearh << 32 | status->bearl);
+ const unsigned long page = bear >> PAGE_SHIFT;
+ const unsigned long offset = bear & ~PAGE_MASK;
+ int row;
+ char message[PPC4XX_EDAC_MESSAGE_SIZE];
+
+ ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
+
+ for (row = 0; row < mci->nr_csrows; row++)
+ if (ppc4xx_edac_check_bank_error(status, row))
+ edac_mc_handle_ue(mci, page, offset, row, message);
+}
+
+/**
+ * ppc4xx_edac_check - check controller for ECC errors
+ * @mci: A pointer to the EDAC memory controller instance
+ * associated with the ibm,sdram-4xx-ddr2 controller being
+ * checked.
+ *
+ * This routine is used to check and post ECC errors and is called by
+ * both the EDAC polling thread and this driver's CE and UE interrupt
+ * handler.
+ */
+static void
+ppc4xx_edac_check(struct mem_ctl_info *mci)
+{
+#ifdef DEBUG
+ static unsigned int count;
+#endif
+ struct ppc4xx_ecc_status status;
+
+ ppc4xx_ecc_get_status(mci, &status);
+
+#ifdef DEBUG
+ if (count++ % 30 == 0)
+ ppc4xx_ecc_dump_status(mci, &status);
+#endif
+
+ if (status.ecces & SDRAM_ECCES_UE)
+ ppc4xx_edac_handle_ue(mci, &status);
+
+ if (status.ecces & SDRAM_ECCES_CE)
+ ppc4xx_edac_handle_ce(mci, &status);
+
+ ppc4xx_ecc_clear_status(mci, &status);
+}
+
+/**
+ * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
+ * @irq: The virtual interrupt number being serviced.
+ * @dev_id: A pointer to the EDAC memory controller instance
+ * associated with the interrupt being handled.
+ *
+ * This routine implements the interrupt handler for both correctable
+ * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
+ * controller. It simply calls through to the same routine used during
+ * polling to check, report and clear the ECC status.
+ *
+ * Unconditionally returns IRQ_HANDLED.
+ */
+static irqreturn_t
+ppc4xx_edac_isr(int irq, void *dev_id)
+{
+ struct mem_ctl_info *mci = dev_id;
+
+ ppc4xx_edac_check(mci);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * ppc4xx_edac_get_dtype - return the controller memory width
+ * @mcopt1: The 32-bit Memory Controller Option 1 register value
+ * currently set for the controller, from which the width
+ * is derived.
+ *
+ * This routine returns the EDAC device type width appropriate for the
+ * current controller configuration.
+ *
+ * TODO: This needs to be conditioned dynamically through feature
+ * flags or some such when other controller variants are supported as
+ * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
+ * 16- and 64-bit field definition/value/enumeration (b1) overloaded
+ * among them.
+ *
+ * Returns a device type width enumeration.
+ */
+static enum dev_type __devinit
+ppc4xx_edac_get_dtype(u32 mcopt1)
+{
+ switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) {
+ case SDRAM_MCOPT1_WDTH_16:
+ return DEV_X2;
+ case SDRAM_MCOPT1_WDTH_32:
+ return DEV_X4;
+ default:
+ return DEV_UNKNOWN;
+ }
+}
+
+/**
+ * ppc4xx_edac_get_mtype - return controller memory type
+ * @mcopt1: The 32-bit Memory Controller Option 1 register value
+ * currently set for the controller, from which the memory type
+ * is derived.
+ *
+ * This routine returns the EDAC memory type appropriate for the
+ * current controller configuration.
+ *
+ * Returns a memory type enumeration.
+ */
+static enum mem_type __devinit
+ppc4xx_edac_get_mtype(u32 mcopt1)
+{
+ bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN);
+
+ switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) {
+ case SDRAM_MCOPT1_DDR2_TYPE:
+ return rden ? MEM_RDDR2 : MEM_DDR2;
+ case SDRAM_MCOPT1_DDR1_TYPE:
+ return rden ? MEM_RDDR : MEM_DDR;
+ default:
+ return MEM_UNKNOWN;
+ }
+}
+
+/**
+ * ppc4xx_edac_init_csrows - intialize driver instance rows
+ * @mci: A pointer to the EDAC memory controller instance
+ * associated with the ibm,sdram-4xx-ddr2 controller for which
+ * the csrows (i.e. banks/ranks) are being initialized.
+ * @mcopt1: The 32-bit Memory Controller Option 1 register value
+ * currently set for the controller, from which bank width
+ * and memory typ information is derived.
+ *
+ * This routine intializes the virtual "chip select rows" associated
+ * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
+ * controller bank/rank is mapped to a row.
+ *
+ * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
+ * configuration cannot be determined.
+ */
+static int __devinit
+ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
+{
+ const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
+ int status = 0;
+ enum mem_type mtype;
+ enum dev_type dtype;
+ enum edac_type edac_mode;
+ int row;
+ u32 mbxcf, size;
+ static u32 ppc4xx_last_page;
+
+ /* Establish the memory type and width */
+
+ mtype = ppc4xx_edac_get_mtype(mcopt1);
+ dtype = ppc4xx_edac_get_dtype(mcopt1);
+
+ /* Establish EDAC mode */
+
+ if (mci->edac_cap & EDAC_FLAG_SECDED)
+ edac_mode = EDAC_SECDED;
+ else if (mci->edac_cap & EDAC_FLAG_EC)
+ edac_mode = EDAC_EC;
+ else
+ edac_mode = EDAC_NONE;
+
+ /*
+ * Initialize each chip select row structure which correspond
+ * 1:1 with a controller bank/rank.
+ */
+
+ for (row = 0; row < mci->nr_csrows; row++) {
+ struct csrow_info *csi = &mci->csrows[row];
+
+ /*
+ * Get the configuration settings for this
+ * row/bank/rank and skip disabled banks.
+ */
+
+ mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row));
+
+ if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE)
+ continue;
+
+ /* Map the bank configuration size setting to pages. */
+
+ size = mbxcf & SDRAM_MBCF_SZ_MASK;
+
+ switch (size) {
+ case SDRAM_MBCF_SZ_4MB:
+ case SDRAM_MBCF_SZ_8MB:
+ case SDRAM_MBCF_SZ_16MB:
+ case SDRAM_MBCF_SZ_32MB:
+ case SDRAM_MBCF_SZ_64MB:
+ case SDRAM_MBCF_SZ_128MB:
+ case SDRAM_MBCF_SZ_256MB:
+ case SDRAM_MBCF_SZ_512MB:
+ case SDRAM_MBCF_SZ_1GB:
+ case SDRAM_MBCF_SZ_2GB:
+ case SDRAM_MBCF_SZ_4GB:
+ case SDRAM_MBCF_SZ_8GB:
+ csi->nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
+ break;
+ default:
+ ppc4xx_edac_mc_printk(KERN_ERR, mci,
+ "Unrecognized memory bank %d "
+ "size 0x%08x\n",
+ row, SDRAM_MBCF_SZ_DECODE(size));
+ status = -EINVAL;
+ goto done;
+ }
+
+ csi->first_page = ppc4xx_last_page;
+ csi->last_page = csi->first_page + csi->nr_pages - 1;
+ csi->page_mask = 0;
+
+ /*
+ * It's unclear exactly what grain should be set to
+ * here. The SDRAM_ECCES register allows resolution of
+ * an error down to a nibble which would potentially
+ * argue for a grain of '1' byte, even though we only
+ * know the associated address for uncorrectable
+ * errors. This value is not used at present for
+ * anything other than error reporting so getting it
+ * wrong should be of little consequence. Other
+ * possible values would be the PLB width (16), the
+ * page size (PAGE_SIZE) or the memory width (2 or 4).
+ */
+
+ csi->grain = 1;
+
+ csi->mtype = mtype;
+ csi->dtype = dtype;
+
+ csi->edac_mode = edac_mode;
+
+ ppc4xx_last_page += csi->nr_pages;
+ }
+
+ done:
+ return status;
+}
+
+/**
+ * ppc4xx_edac_mc_init - intialize driver instance
+ * @mci: A pointer to the EDAC memory controller instance being
+ * initialized.
+ * @op: A pointer to the OpenFirmware device tree node associated
+ * with the controller this EDAC instance is bound to.
+ * @match: A pointer to the OpenFirmware device tree match
+ * information associated with the controller this EDAC instance
+ * is bound to.
+ * @dcr_host: A pointer to the DCR data containing the DCR mapping
+ * for this controller instance.
+ * @mcopt1: The 32-bit Memory Controller Option 1 register value
+ * currently set for the controller, from which ECC capabilities
+ * and scrub mode are derived.
+ *
+ * This routine performs initialization of the EDAC memory controller
+ * instance and related driver-private data associated with the
+ * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
+ *
+ * Returns 0 if OK; otherwise, < 0 on error.
+ */
+static int __devinit
+ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
+ struct of_device *op,
+ const struct of_device_id *match,
+ const dcr_host_t *dcr_host,
+ u32 mcopt1)
+{
+ int status = 0;
+ const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
+ struct ppc4xx_edac_pdata *pdata = NULL;
+ const struct device_node *np = op->node;
+
+ if (match == NULL)
+ return -EINVAL;
+
+ /* Initial driver pointers and private data */
+
+ mci->dev = &op->dev;
+
+ dev_set_drvdata(mci->dev, mci);
+
+ pdata = mci->pvt_info;
+
+ pdata->dcr_host = *dcr_host;
+ pdata->irqs.sec = NO_IRQ;
+ pdata->irqs.ded = NO_IRQ;
+
+ /* Initialize controller capabilities and configuration */
+
+ mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR |
+ MEM_FLAG_DDR2 | MEM_FLAG_RDDR2);
+
+ mci->edac_ctl_cap = (EDAC_FLAG_NONE |
+ EDAC_FLAG_EC |
+ EDAC_FLAG_SECDED);
+
+ mci->scrub_cap = SCRUB_NONE;
+ mci->scrub_mode = SCRUB_NONE;
+
+ /*
+ * Update the actual capabilites based on the MCOPT1[MCHK]
+ * settings. Scrubbing is only useful if reporting is enabled.
+ */
+
+ switch (memcheck) {
+ case SDRAM_MCOPT1_MCHK_CHK:
+ mci->edac_cap = EDAC_FLAG_EC;
+ break;
+ case SDRAM_MCOPT1_MCHK_CHK_REP:
+ mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED);
+ mci->scrub_mode = SCRUB_SW_SRC;
+ break;
+ default:
+ mci->edac_cap = EDAC_FLAG_NONE;
+ break;
+ }
+
+ /* Initialize strings */
+
+ mci->mod_name = PPC4XX_EDAC_MODULE_NAME;
+ mci->mod_ver = PPC4XX_EDAC_MODULE_REVISION;
+ mci->ctl_name = match->compatible,
+ mci->dev_name = np->full_name;
+
+ /* Initialize callbacks */
+
+ mci->edac_check = ppc4xx_edac_check;
+ mci->ctl_page_to_phys = NULL;
+
+ /* Initialize chip select rows */
+
+ status = ppc4xx_edac_init_csrows(mci, mcopt1);
+
+ if (status)
+ ppc4xx_edac_mc_printk(KERN_ERR, mci,
+ "Failed to initialize rows!\n");
+
+ return status;
+}
+
+/**
+ * ppc4xx_edac_register_irq - setup and register controller interrupts
+ * @op: A pointer to the OpenFirmware device tree node associated
+ * with the controller this EDAC instance is bound to.
+ * @mci: A pointer to the EDAC memory controller instance
+ * associated with the ibm,sdram-4xx-ddr2 controller for which
+ * interrupts are being registered.
+ *
+ * This routine parses the correctable (CE) and uncorrectable error (UE)
+ * interrupts from the device tree node and maps and assigns them to
+ * the associated EDAC memory controller instance.
+ *
+ * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
+ * mapped and assigned.
+ */
+static int __devinit
+ppc4xx_edac_register_irq(struct of_device *op, struct mem_ctl_info *mci)
+{
+ int status = 0;
+ int ded_irq, sec_irq;
+ struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
+ struct device_node *np = op->node;
+
+ ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX);
+ sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX);
+
+ if (ded_irq == NO_IRQ || sec_irq == NO_IRQ) {
+ ppc4xx_edac_mc_printk(KERN_ERR, mci,
+ "Unable to map interrupts.\n");
+ status = -ENODEV;
+ goto fail;
+ }
+
+ status = request_irq(ded_irq,
+ ppc4xx_edac_isr,
+ IRQF_DISABLED,
+ "[EDAC] MC ECCDED",
+ mci);
+
+ if (status < 0) {
+ ppc4xx_edac_mc_printk(KERN_ERR, mci,
+ "Unable to request irq %d for ECC DED",
+ ded_irq);
+ status = -ENODEV;
+ goto fail1;
+ }
+
+ status = request_irq(sec_irq,
+ ppc4xx_edac_isr,
+ IRQF_DISABLED,
+ "[EDAC] MC ECCSEC",
+ mci);
+
+ if (status < 0) {
+ ppc4xx_edac_mc_printk(KERN_ERR, mci,
+ "Unable to request irq %d for ECC SEC",
+ sec_irq);
+ status = -ENODEV;
+ goto fail2;
+ }
+
+ ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq);
+ ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq);
+
+ pdata->irqs.ded = ded_irq;
+ pdata->irqs.sec = sec_irq;
+
+ return 0;
+
+ fail2:
+ free_irq(sec_irq, mci);
+
+ fail1:
+ free_irq(ded_irq, mci);
+
+ fail:
+ return status;
+}
+
+/**
+ * ppc4xx_edac_map_dcrs - locate and map controller registers
+ * @np: A pointer to the device tree node containing the DCR
+ * resources to map.
+ * @dcr_host: A pointer to the DCR data to populate with the
+ * DCR mapping.
+ *
+ * This routine attempts to locate in the device tree and map the DCR
+ * register resources associated with the controller's indirect DCR
+ * address and data windows.
+ *
+ * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on
+ * error.
+ */
+static int __devinit
+ppc4xx_edac_map_dcrs(const struct device_node *np, dcr_host_t *dcr_host)
+{
+ unsigned int dcr_base, dcr_len;
+
+ if (np == NULL || dcr_host == NULL)
+ return -EINVAL;
+
+ /* Get the DCR resource extent and sanity check the values. */
+
+ dcr_base = dcr_resource_start(np, 0);
+ dcr_len = dcr_resource_len(np, 0);
+
+ if (dcr_base == 0 || dcr_len == 0) {
+ ppc4xx_edac_printk(KERN_ERR,
+ "Failed to obtain DCR property.\n");
+ return -ENODEV;
+ }
+
+ if (dcr_len != SDRAM_DCR_RESOURCE_LEN) {
+ ppc4xx_edac_printk(KERN_ERR,
+ "Unexpected DCR length %d, expected %d.\n",
+ dcr_len, SDRAM_DCR_RESOURCE_LEN);
+ return -ENODEV;
+ }
+
+ /* Attempt to map the DCR extent. */
+
+ *dcr_host = dcr_map(np, dcr_base, dcr_len);
+
+ if (!DCR_MAP_OK(*dcr_host)) {
+ ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+/**
+ * ppc4xx_edac_probe - check controller and bind driver
+ * @op: A pointer to the OpenFirmware device tree node associated
+ * with the controller being probed for driver binding.
+ * @match: A pointer to the OpenFirmware device tree match
+ * information associated with the controller being probed
+ * for driver binding.
+ *
+ * This routine probes a specific ibm,sdram-4xx-ddr2 controller
+ * instance for binding with the driver.
+ *
+ * Returns 0 if the controller instance was successfully bound to the
+ * driver; otherwise, < 0 on error.
+ */
+static int __devinit
+ppc4xx_edac_probe(struct of_device *op, const struct of_device_id *match)
+{
+ int status = 0;
+ u32 mcopt1, memcheck;
+ dcr_host_t dcr_host;
+ const struct device_node *np = op->node;
+ struct mem_ctl_info *mci = NULL;
+ static int ppc4xx_edac_instance;
+
+ /*
+ * At this point, we only support the controller realized on
+ * the AMCC PPC 405EX[r]. Reject anything else.
+ */
+
+ if (!of_device_is_compatible(np, "ibm,sdram-405ex") &&
+ !of_device_is_compatible(np, "ibm,sdram-405exr")) {
+ ppc4xx_edac_printk(KERN_NOTICE,
+ "Only the PPC405EX[r] is supported.\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Next, get the DCR property and attempt to map it so that we
+ * can probe the controller.
+ */
+
+ status = ppc4xx_edac_map_dcrs(np, &dcr_host);
+
+ if (status)
+ return status;
+
+ /*
+ * First determine whether ECC is enabled at all. If not,
+ * there is no useful checking or monitoring that can be done
+ * for this controller.
+ */
+
+ mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1);
+ memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
+
+ if (memcheck == SDRAM_MCOPT1_MCHK_NON) {
+ ppc4xx_edac_printk(KERN_INFO, "%s: No ECC memory detected or "
+ "ECC is disabled.\n", np->full_name);
+ status = -ENODEV;
+ goto done;
+ }
+
+ /*
+ * At this point, we know ECC is enabled, allocate an EDAC
+ * controller instance and perform the appropriate
+ * initialization.
+ */
+
+ mci = edac_mc_alloc(sizeof(struct ppc4xx_edac_pdata),
+ ppc4xx_edac_nr_csrows,
+ ppc4xx_edac_nr_chans,
+ ppc4xx_edac_instance);
+
+ if (mci == NULL) {
+ ppc4xx_edac_printk(KERN_ERR, "%s: "
+ "Failed to allocate EDAC MC instance!\n",
+ np->full_name);
+ status = -ENOMEM;
+ goto done;
+ }
+
+ status = ppc4xx_edac_mc_init(mci, op, match, &dcr_host, mcopt1);
+
+ if (status) {
+ ppc4xx_edac_mc_printk(KERN_ERR, mci,
+ "Failed to initialize instance!\n");
+ goto fail;
+ }
+
+ /*
+ * We have a valid, initialized EDAC instance bound to the
+ * controller. Attempt to register it with the EDAC subsystem
+ * and, if necessary, register interrupts.
+ */
+
+ if (edac_mc_add_mc(mci)) {
+ ppc4xx_edac_mc_printk(KERN_ERR, mci,
+ "Failed to add instance!\n");
+ status = -ENODEV;
+ goto fail;
+ }
+
+ if (edac_op_state == EDAC_OPSTATE_INT) {
+ status = ppc4xx_edac_register_irq(op, mci);
+
+ if (status)
+ goto fail1;
+ }
+
+ ppc4xx_edac_instance++;
+
+ return 0;
+
+ fail1:
+ edac_mc_del_mc(mci->dev);
+
+ fail:
+ edac_mc_free(mci);
+
+ done:
+ return status;
+}
+
+/**
+ * ppc4xx_edac_remove - unbind driver from controller
+ * @op: A pointer to the OpenFirmware device tree node associated
+ * with the controller this EDAC instance is to be unbound/removed
+ * from.
+ *
+ * This routine unbinds the EDAC memory controller instance associated
+ * with the specified ibm,sdram-4xx-ddr2 controller described by the
+ * OpenFirmware device tree node passed as a parameter.
+ *
+ * Unconditionally returns 0.
+ */
+static int
+ppc4xx_edac_remove(struct of_device *op)
+{
+ struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
+ struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
+
+ if (edac_op_state == EDAC_OPSTATE_INT) {
+ free_irq(pdata->irqs.sec, mci);
+ free_irq(pdata->irqs.ded, mci);
+ }
+
+ dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN);
+
+ edac_mc_del_mc(mci->dev);
+ edac_mc_free(mci);
+
+ return 0;
+}
+
+/**
+ * ppc4xx_edac_opstate_init - initialize EDAC reporting method
+ *
+ * This routine ensures that the EDAC memory controller reporting
+ * method is mapped to a sane value as the EDAC core defines the value
+ * to EDAC_OPSTATE_INVAL by default. We don't call the global
+ * opstate_init as that defaults to polling and we want interrupt as
+ * the default.
+ */
+static inline void __init
+ppc4xx_edac_opstate_init(void)
+{
+ switch (edac_op_state) {
+ case EDAC_OPSTATE_POLL:
+ case EDAC_OPSTATE_INT:
+ break;
+ default:
+ edac_op_state = EDAC_OPSTATE_INT;
+ break;
+ }
+
+ ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n",
+ ((edac_op_state == EDAC_OPSTATE_POLL) ?
+ EDAC_OPSTATE_POLL_STR :
+ ((edac_op_state == EDAC_OPSTATE_INT) ?
+ EDAC_OPSTATE_INT_STR :
+ EDAC_OPSTATE_UNKNOWN_STR)));
+}
+
+/**
+ * ppc4xx_edac_init - driver/module insertion entry point
+ *
+ * This routine is the driver/module insertion entry point. It
+ * initializes the EDAC memory controller reporting state and
+ * registers the driver as an OpenFirmware device tree platform
+ * driver.
+ */
+static int __init
+ppc4xx_edac_init(void)
+{
+ ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n");
+
+ ppc4xx_edac_opstate_init();
+
+ return of_register_platform_driver(&ppc4xx_edac_driver);
+}
+
+/**
+ * ppc4xx_edac_exit - driver/module removal entry point
+ *
+ * This routine is the driver/module removal entry point. It
+ * unregisters the driver as an OpenFirmware device tree platform
+ * driver.
+ */
+static void __exit
+ppc4xx_edac_exit(void)
+{
+ of_unregister_platform_driver(&ppc4xx_edac_driver);
+}
+
+module_init(ppc4xx_edac_init);
+module_exit(ppc4xx_edac_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
+MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
+module_param(edac_op_state, int, 0444);
+MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: "
+ "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);
diff --git a/drivers/edac/ppc4xx_edac.h b/drivers/edac/ppc4xx_edac.h
new file mode 100644
index 0000000..d315476
--- /dev/null
+++ b/drivers/edac/ppc4xx_edac.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ * Grant Erickson <gerickson@nuovations.com>
+ *
+ * This file defines processor mnemonics for accessing and managing
+ * the IBM DDR1/DDR2 ECC controller found in the 405EX[r], 440SP,
+ * 440SPe, 460EX, 460GT and 460SX.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ */
+
+#ifndef __PPC4XX_EDAC_H
+#define __PPC4XX_EDAC_H
+
+#include <linux/types.h>
+
+/*
+ * Macro for generating register field mnemonics
+ */
+#define PPC_REG_BITS 32
+#define PPC_REG_VAL(bit, val) ((val) << ((PPC_REG_BITS - 1) - (bit)))
+#define PPC_REG_DECODE(bit, val) ((val) >> ((PPC_REG_BITS - 1) - (bit)))
+
+/*
+ * IBM 4xx DDR1/DDR2 SDRAM memory controller registers (at least those
+ * relevant to ECC)
+ */
+#define SDRAM_BESR 0x00 /* Error status (read/clear) */
+#define SDRAM_BESRT 0x01 /* Error statuss (test/set) */
+#define SDRAM_BEARL 0x02 /* Error address low */
+#define SDRAM_BEARH 0x03 /* Error address high */
+#define SDRAM_WMIRQ 0x06 /* Write master (read/clear) */
+#define SDRAM_WMIRQT 0x07 /* Write master (test/set) */
+#define SDRAM_MCOPT1 0x20 /* Controller options 1 */
+#define SDRAM_MBXCF_BASE 0x40 /* Bank n configuration base */
+#define SDRAM_MBXCF(n) (SDRAM_MBXCF_BASE + (4 * (n)))
+#define SDRAM_MB0CF SDRAM_MBXCF(0)
+#define SDRAM_MB1CF SDRAM_MBXCF(1)
+#define SDRAM_MB2CF SDRAM_MBXCF(2)
+#define SDRAM_MB3CF SDRAM_MBXCF(3)
+#define SDRAM_ECCCR 0x98 /* ECC error status */
+#define SDRAM_ECCES SDRAM_ECCCR
+
+/*
+ * PLB Master IDs
+ */
+#define SDRAM_PLB_M0ID_FIRST 0
+#define SDRAM_PLB_M0ID_ICU SDRAM_PLB_M0ID_FIRST
+#define SDRAM_PLB_M0ID_PCIE0 1
+#define SDRAM_PLB_M0ID_PCIE1 2
+#define SDRAM_PLB_M0ID_DMA 3
+#define SDRAM_PLB_M0ID_DCU 4
+#define SDRAM_PLB_M0ID_OPB 5
+#define SDRAM_PLB_M0ID_MAL 6
+#define SDRAM_PLB_M0ID_SEC 7
+#define SDRAM_PLB_M0ID_AHB 8
+#define SDRAM_PLB_M0ID_LAST SDRAM_PLB_M0ID_AHB
+#define SDRAM_PLB_M0ID_COUNT (SDRAM_PLB_M0ID_LAST - \
+ SDRAM_PLB_M0ID_FIRST + 1)
+
+/*
+ * Memory Controller Bus Error Status Register
+ */
+#define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
+#define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
+#define SDRAM_BESR_M0ID_DECODE(n) PPC_REG_DECODE(3, n)
+#define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, SDRAM_PLB_M0ID_ICU)
+#define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE0)
+#define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE1)
+#define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, SDRAM_PLB_M0ID_DMA)
+#define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, SDRAM_PLB_M0ID_DCU)
+#define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, SDRAM_PLB_M0ID_OPB)
+#define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, SDRAM_PLB_M0ID_MAL)
+#define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, SDRAM_PLB_M0ID_SEC)
+#define SDRAM_BESR_M0ID_AHB PPC_REG_VAL(3, SDRAM_PLB_M0ID_AHB)
+#define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
+#define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0)
+#define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 1)
+#define SDRAM_BESR_M0RW_MASK PPC_REG_VAL(7, 1)
+#define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
+#define SDRAM_BESR_M0RW_READ PPC_REG_VAL(7, 1)
+
+/*
+ * Memory Controller PLB Write Master Interrupt Register
+ */
+#define SDRAM_WMIRQ_MASK PPC_REG_VAL(8, 0x1FF)
+#define SDRAM_WMIRQ_ENCODE(id) PPC_REG_VAL((id % \
+ SDRAM_PLB_M0ID_COUNT), 1)
+#define SDRAM_WMIRQ_ICU PPC_REG_VAL(SDRAM_PLB_M0ID_ICU, 1)
+#define SDRAM_WMIRQ_PCIE0 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE0, 1)
+#define SDRAM_WMIRQ_PCIE1 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE1, 1)
+#define SDRAM_WMIRQ_DMA PPC_REG_VAL(SDRAM_PLB_M0ID_DMA, 1)
+#define SDRAM_WMIRQ_DCU PPC_REG_VAL(SDRAM_PLB_M0ID_DCU, 1)
+#define SDRAM_WMIRQ_OPB PPC_REG_VAL(SDRAM_PLB_M0ID_OPB, 1)
+#define SDRAM_WMIRQ_MAL PPC_REG_VAL(SDRAM_PLB_M0ID_MAL, 1)
+#define SDRAM_WMIRQ_SEC PPC_REG_VAL(SDRAM_PLB_M0ID_SEC, 1)
+#define SDRAM_WMIRQ_AHB PPC_REG_VAL(SDRAM_PLB_M0ID_AHB, 1)
+
+/*
+ * Memory Controller Options 1 Register
+ */
+#define SDRAM_MCOPT1_MCHK_MASK PPC_REG_VAL(3, 0x3) /* ECC mask */
+#define SDRAM_MCOPT1_MCHK_NON PPC_REG_VAL(3, 0x0) /* No ECC gen */
+#define SDRAM_MCOPT1_MCHK_GEN PPC_REG_VAL(3, 0x2) /* ECC gen */
+#define SDRAM_MCOPT1_MCHK_CHK PPC_REG_VAL(3, 0x1) /* ECC gen and chk */
+#define SDRAM_MCOPT1_MCHK_CHK_REP PPC_REG_VAL(3, 0x3) /* ECC gen/chk/rpt */
+#define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3)
+#define SDRAM_MCOPT1_RDEN_MASK PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM mask */
+#define SDRAM_MCOPT1_RDEN PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM enbl */
+#define SDRAM_MCOPT1_WDTH_MASK PPC_REG_VAL(7, 0x1) /* Width mask */
+#define SDRAM_MCOPT1_WDTH_32 PPC_REG_VAL(7, 0x0) /* 32 bits */
+#define SDRAM_MCOPT1_WDTH_16 PPC_REG_VAL(7, 0x1) /* 16 bits */
+#define SDRAM_MCOPT1_DDR_TYPE_MASK PPC_REG_VAL(11, 0x1) /* DDR type mask */
+#define SDRAM_MCOPT1_DDR1_TYPE PPC_REG_VAL(11, 0x0) /* DDR1 type */
+#define SDRAM_MCOPT1_DDR2_TYPE PPC_REG_VAL(11, 0x1) /* DDR2 type */
+
+/*
+ * Memory Bank 0 - n Configuration Register
+ */
+#define SDRAM_MBCF_BA_MASK PPC_REG_VAL(12, 0x1FFF)
+#define SDRAM_MBCF_SZ_MASK PPC_REG_VAL(19, 0xF)
+#define SDRAM_MBCF_SZ_DECODE(mbxcf) PPC_REG_DECODE(19, mbxcf)
+#define SDRAM_MBCF_SZ_4MB PPC_REG_VAL(19, 0x0)
+#define SDRAM_MBCF_SZ_8MB PPC_REG_VAL(19, 0x1)
+#define SDRAM_MBCF_SZ_16MB PPC_REG_VAL(19, 0x2)
+#define SDRAM_MBCF_SZ_32MB PPC_REG_VAL(19, 0x3)
+#define SDRAM_MBCF_SZ_64MB PPC_REG_VAL(19, 0x4)
+#define SDRAM_MBCF_SZ_128MB PPC_REG_VAL(19, 0x5)
+#define SDRAM_MBCF_SZ_256MB PPC_REG_VAL(19, 0x6)
+#define SDRAM_MBCF_SZ_512MB PPC_REG_VAL(19, 0x7)
+#define SDRAM_MBCF_SZ_1GB PPC_REG_VAL(19, 0x8)
+#define SDRAM_MBCF_SZ_2GB PPC_REG_VAL(19, 0x9)
+#define SDRAM_MBCF_SZ_4GB PPC_REG_VAL(19, 0xA)
+#define SDRAM_MBCF_SZ_8GB PPC_REG_VAL(19, 0xB)
+#define SDRAM_MBCF_AM_MASK PPC_REG_VAL(23, 0xF)
+#define SDRAM_MBCF_AM_MODE0 PPC_REG_VAL(23, 0x0)
+#define SDRAM_MBCF_AM_MODE1 PPC_REG_VAL(23, 0x1)
+#define SDRAM_MBCF_AM_MODE2 PPC_REG_VAL(23, 0x2)
+#define SDRAM_MBCF_AM_MODE3 PPC_REG_VAL(23, 0x3)
+#define SDRAM_MBCF_AM_MODE4 PPC_REG_VAL(23, 0x4)
+#define SDRAM_MBCF_AM_MODE5 PPC_REG_VAL(23, 0x5)
+#define SDRAM_MBCF_AM_MODE6 PPC_REG_VAL(23, 0x6)
+#define SDRAM_MBCF_AM_MODE7 PPC_REG_VAL(23, 0x7)
+#define SDRAM_MBCF_AM_MODE8 PPC_REG_VAL(23, 0x8)
+#define SDRAM_MBCF_AM_MODE9 PPC_REG_VAL(23, 0x9)
+#define SDRAM_MBCF_BE_MASK PPC_REG_VAL(31, 0x1)
+#define SDRAM_MBCF_BE_DISABLE PPC_REG_VAL(31, 0x0)
+#define SDRAM_MBCF_BE_ENABLE PPC_REG_VAL(31, 0x1)
+
+/*
+ * ECC Error Status
+ */
+#define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
+#define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
+#define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
+#define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
+#define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
+#define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2)
+#define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1)
+#define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2)
+#define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3)
+#define SDRAM_ECCES_CE PPC_REG_VAL(18, 1)
+#define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
+#define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
+#define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1)
+#define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1)
+
+#endif /* __PPC4XX_EDAC_H */
--
1.6.1.2
^ permalink raw reply related
* [patch] powerpc/ps3: Use hard coded values for LV1 device type
From: Geoff Levand @ 2009-02-07 2:42 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Mel Gorman, linuxppc-dev, Kamalesh Babulal
In-Reply-To: <498C6C49.1010200@in.ibm.com>
Change the PS3 platform code to use hard coded numbers for its
LV1 device types.
The PS3 platform code was incorrectly using some scsi block
constants for the device type returned from the LV1 hypervisor.
Fixes build errors like these when CONFIG_BLOCK=n:
In file included from include/scsi/scsi.h:12,
from arch/powerpc/platforms/ps3/platform.h:25,
from arch/powerpc/platforms/ps3/setup.c:36:
include/scsi/scsi_cmnd.h:27:25: warning: "BLK_MAX_CDB" is not defined
include/scsi/scsi_cmnd.h:28:3: error: #error MAX_COMMAND_SIZE can not be bigger than BLK_MAX_CDB
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
Ben,
Please send upstream for 2.6.29.
-Geoff
arch/powerpc/platforms/ps3/platform.h | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
--- a/arch/powerpc/platforms/ps3/platform.h
+++ b/arch/powerpc/platforms/ps3/platform.h
@@ -22,8 +22,6 @@
#define _PS3_PLATFORM_H
#include <linux/rtc.h>
-#include <scsi/scsi.h>
-
#include <asm/ps3.h>
/* htab */
@@ -83,12 +81,12 @@ enum ps3_bus_type {
};
enum ps3_dev_type {
- PS3_DEV_TYPE_STOR_DISK = TYPE_DISK, /* 0 */
+ PS3_DEV_TYPE_STOR_DISK = 0, /* TYPE_DISK */
PS3_DEV_TYPE_SB_GELIC = 3,
PS3_DEV_TYPE_SB_USB = 4,
- PS3_DEV_TYPE_STOR_ROM = TYPE_ROM, /* 5 */
+ PS3_DEV_TYPE_STOR_ROM = 5, /* TYPE_ROM */
PS3_DEV_TYPE_SB_GPIO = 6,
- PS3_DEV_TYPE_STOR_FLASH = TYPE_RBC, /* 14 */
+ PS3_DEV_TYPE_STOR_FLASH = 14, /* TYPE_RBC */
};
int ps3_repository_read_bus_str(unsigned int bus_index, const char *bus_str,
^ permalink raw reply
* hash-table creation...
From: sumedh tirodkar @ 2009-02-07 6:13 UTC (permalink / raw)
To: linuxppc-dev
Hello,
I wanted algorithm for creating hash tables used in paging mechanism..
In the manual that i read i got algorithm to convert Effective Address
to Real Address using these hash tables that are created..but i could
not find how these hash tables are created in first place using the
Real addresses.
Is there any document available for the same?
Regards,
Sumedh
^ permalink raw reply
* Re: [PATCH] powerpc: Rework I$/D$ coherency (v2)
From: David Miller @ 2009-02-07 8:22 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <20090202001035.E1390DDF3D@ozlabs.org>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Mon, 02 Feb 2009 11:10:24 +1100
> +/* has to be a macro because of include dependencies */
> +static inline int is_exec_fault(void)
> +{
> + return current->thread.regs && TRAP(current->thread.regs) == 0x400;
> +}
Nice macro :-)
^ permalink raw reply
* Re: [PATCH] powerpc: Rework I$/D$ coherency (v2)
From: Benjamin Herrenschmidt @ 2009-02-07 10:08 UTC (permalink / raw)
To: David Miller; +Cc: linuxppc-dev
In-Reply-To: <20090207.002214.259050726.davem@davemloft.net>
On Sat, 2009-02-07 at 00:22 -0800, David Miller wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Date: Mon, 02 Feb 2009 11:10:24 +1100
>
> > +/* has to be a macro because of include dependencies */
> > +static inline int is_exec_fault(void)
> > +{
> > + return current->thread.regs && TRAP(current->thread.regs) == 0x400;
> > +}
>
> Nice macro :-)
Hehe... was a macro in my original implementation and I turned it back
into an inline later on... missed the comment obviously :-)
I'll fix it, thanks for having a look.
Cheers,
Ben.
^ permalink raw reply
* Re: [patch] powerpc/ps3: Use hard coded values for LV1 device type
From: Sachin P. Sant @ 2009-02-07 17:41 UTC (permalink / raw)
To: Geoff Levand; +Cc: Mel Gorman, Kamalesh Babulal, linuxppc-dev
In-Reply-To: <498CF52E.4040903@am.sony.com>
Geoff Levand wrote:
> Change the PS3 platform code to use hard coded numbers for its
> LV1 device types.
>
> The PS3 platform code was incorrectly using some scsi block
> constants for the device type returned from the LV1 hypervisor.
>
> Fixes build errors like these when CONFIG_BLOCK=n:
>
> In file included from include/scsi/scsi.h:12,
> from arch/powerpc/platforms/ps3/platform.h:25,
> from arch/powerpc/platforms/ps3/setup.c:36:
> include/scsi/scsi_cmnd.h:27:25: warning: "BLK_MAX_CDB" is not defined
> include/scsi/scsi_cmnd.h:28:3: error: #error MAX_COMMAND_SIZE can not be bigger than BLK_MAX_CDB
>
> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
> ---
Thanks Geoff. This fixes the issue.
Tested-by : Sachin Sant <sachinp@in.ibm.com>
--
---------------------------------
Sachin Sant
IBM Linux Technology Center
India Systems and Technology Labs
Bangalore, India
---------------------------------
^ permalink raw reply
* Re: [PATCH] bootgraph: fix for use with dot symbols
From: Michael Neuling @ 2009-02-08 0:57 UTC (permalink / raw)
To: Arjan van de Ven; +Cc: linuxppc-dev, Anton Blanchard, linux-kernel
In-Reply-To: <20090128105601.GB18368@kryten>
> > question for the ppc folks.... why does the "print symbol" magic format str
ing
> > thing print a dot symbol and not the real function name?
> > Should that be fixed instead?
>
> We have two symbols for each function, foo points to the function
> descriptor, and .foo points to the instruction text. If we were to strip
> the '.' when we print symbols then it would become harder to diagnose
> some failures (eg branching to the function descriptor instead of the
> instruction text).
Arjan,
I don't think there is much scope for removing dot symbols in the near
future.
Can you please take the patch as is for now so bootgraph will at least
work for existing systems?
Mikey
^ permalink raw reply
* Re: hash-table creation...
From: Benjamin Herrenschmidt @ 2009-02-07 21:17 UTC (permalink / raw)
To: sumedh tirodkar; +Cc: linuxppc-dev
In-Reply-To: <d2b9ccd90902062213l48c063e1gd536a347f1fbe861@mail.gmail.com>
On Sat, 2009-02-07 at 11:43 +0530, sumedh tirodkar wrote:
> Hello,
>
> I wanted algorithm for creating hash tables used in paging mechanism..
> In the manual that i read i got algorithm to convert Effective Address
> to Real Address using these hash tables that are created..but i could
> not find how these hash tables are created in first place using the
> Real addresses.
> Is there any document available for the same?
There's one MMU hash table. It's allocated & cleared by the kernel
during early boot or by the hypervisor and pointed to by the SDR1
register.
It's populated by code in arch/powerpc/mm/hash_low_64.S or
hash_low_32.S, typically as the result of a hash miss exception.
Ben.
^ permalink raw reply
* Re: Badness at kernel/time/timekeeping.c:98 in pmud (timekeeping_suspended)
From: Paul Collins @ 2009-02-08 4:35 UTC (permalink / raw)
To: Rafael J. Wysocki; +Cc: linuxppc-dev, Thomas Gleixner, linux-kernel
In-Reply-To: <87k58nda87.fsf@burly.wgtn.ondioline.org>
Paul Collins <paul@burly.ondioline.org> writes:
> "Rafael J. Wysocki" <rjw@sisk.pl> writes:
>
>> On Wednesday 21 January 2009, Paul Collins wrote:
>>> Got a couple of these on a PowerBook running 2.6.29-rc2 either during
>>> suspend or resume -- it's hard to tell. (The suspend message is
>>> timestamped in syslog with the time I resumed, so I guess it was
>>> buffered along with the subsequent "Badness" messages.)
>>
>> Please check if the patch from http://lkml.org/lkml/2009/1/13/144 fixes the
>> problem for you.
>
> It does not fix the problem.
I'm also getting this warning since 2.6.28.1, which incorporated commit
1c5745aa380efb6417b5681104b007c8612fb496 ("sched_clock: prevent
scd->clock from moving backwards, take #2") as commit
e268dcdd404f4558cdd24c8ecede3e064df8fa33, this being the patch that
introduced the WARN_ON(timekeeping_suspended) check.
--
Paul Collins
Wellington, New Zealand
Dag vijandelijk luchtschip de huismeester is dood
^ permalink raw reply
* [PATCH] ftrace, powerpc64: fix math to calculate offset in TOC
From: Steven Rostedt @ 2009-02-08 6:22 UTC (permalink / raw)
To: LKML, linuxppc-dev
Cc: Arnd Bergmann, Paul Mackerras, Remis Lima Baima, Ingo Molnar
Paul,
I found the bug that was causing large modules to fail in setting
up dynamic ftrace. It wound up being a simple math error. To calculate
the offset in the TOC, I had used an OR, but the bottom half was
a signed extended short, and it should have been an addition.
The fix is in my tree below, as well as posted here.
-- Steve
The following patch is in:
git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-2.6-trace.git
branch: ppc/ftrace
Steven Rostedt (1):
ftrace, powerpc64: fix math to calculate offset in TOC
----
arch/powerpc/kernel/ftrace.c | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
---------------------------
commit 60e611577d908119bb515ead908a46b025a4c9f9
Author: Steven Rostedt <srostedt@redhat.com>
Date: Sat Feb 7 22:00:26 2009 -0800
ftrace, powerpc64: fix math to calculate offset in TOC
Impact: fix dynamic ftrace with large modules in PPC64
The math to calculate the offset into the TOC that is taken from reading
the trampoline is incorrect. The bottom half of the offset is a signed
extended short. The current code was using an OR to create the offset
when it should have been using an addition.
Signed-off-by: Steven Rostedt <srostedt@redhat.com>
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index 88c641d..4112175 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -191,8 +191,9 @@ __ftrace_make_nop(struct module *mod,
return -EINVAL;
}
- offset = (unsigned)((unsigned short)jmp[0]) << 16 |
- (unsigned)((unsigned short)jmp[1]);
+ /* The bottom half is signed extended */
+ offset = ((unsigned)((unsigned short)jmp[0]) << 16) +
+ (int)((short)jmp[1]);
pr_debug(" %x ", offset);
^ permalink raw reply related
* Re: [patch] powerpc/ps3: Use hard coded values for LV1 device type
From: Michael Ellerman @ 2009-02-08 11:29 UTC (permalink / raw)
To: Geoff Levand; +Cc: Mel Gorman, Kamalesh Babulal, linuxppc-dev
In-Reply-To: <498CF52E.4040903@am.sony.com>
[-- Attachment #1: Type: text/plain, Size: 2128 bytes --]
On Fri, 2009-02-06 at 18:42 -0800, Geoff Levand wrote:
> Change the PS3 platform code to use hard coded numbers for its
> LV1 device types.
>
> The PS3 platform code was incorrectly using some scsi block
> constants for the device type returned from the LV1 hypervisor.
>
> Fixes build errors like these when CONFIG_BLOCK=n:
>
> In file included from include/scsi/scsi.h:12,
> from arch/powerpc/platforms/ps3/platform.h:25,
> from arch/powerpc/platforms/ps3/setup.c:36:
> include/scsi/scsi_cmnd.h:27:25: warning: "BLK_MAX_CDB" is not defined
> include/scsi/scsi_cmnd.h:28:3: error: #error MAX_COMMAND_SIZE can not be bigger than BLK_MAX_CDB
>
> Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
> ---
> Ben,
>
> Please send upstream for 2.6.29.
>
> -Geoff
>
> arch/powerpc/platforms/ps3/platform.h | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> --- a/arch/powerpc/platforms/ps3/platform.h
> +++ b/arch/powerpc/platforms/ps3/platform.h
> @@ -22,8 +22,6 @@
> #define _PS3_PLATFORM_H
>
> #include <linux/rtc.h>
> -#include <scsi/scsi.h>
> -
> #include <asm/ps3.h>
>
> /* htab */
> @@ -83,12 +81,12 @@ enum ps3_bus_type {
> };
>
> enum ps3_dev_type {
> - PS3_DEV_TYPE_STOR_DISK = TYPE_DISK, /* 0 */
> + PS3_DEV_TYPE_STOR_DISK = 0, /* TYPE_DISK */
> PS3_DEV_TYPE_SB_GELIC = 3,
> PS3_DEV_TYPE_SB_USB = 4,
> - PS3_DEV_TYPE_STOR_ROM = TYPE_ROM, /* 5 */
> + PS3_DEV_TYPE_STOR_ROM = 5, /* TYPE_ROM */
> PS3_DEV_TYPE_SB_GPIO = 6,
> - PS3_DEV_TYPE_STOR_FLASH = TYPE_RBC, /* 14 */
> + PS3_DEV_TYPE_STOR_FLASH = 14, /* TYPE_RBC */
This looks like you're just papering over the bug, by hardcoding the
same values that are in the scsi header. Or are they really independent,
in which case I'd say the comments are confusing.
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [ANN] Introducing new "test" branch in powerpc.git tree
From: Michel Dänzer @ 2009-02-08 11:56 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev list
In-Reply-To: <1233942156.5081.454.camel@thor.local>
On Fri, 2009-02-06 at 18:42 +0100, Michel D=C3=A4nzer wrote:
> On Thu, 2009-02-05 at 15:58 -0500, Josh Boyer wrote:
> > On Fri, Feb 06, 2009 at 07:56:22AM +1100, Benjamin Herrenschmidt wrote:
> > >
> > >> Which begs the question of what master is for. So far, it's just be=
en
> > >> a mirror of next from what I can tell. Maybe it should just track
> > >> Linus' tree?
> > >
> > >I've been wondering myself what to do with it ... I may just leave it =
to
> > >track linus indeed. Or maybe just delete it.
> >=20
> > I don't think you can delete it without hosing people who try to clone =
it.
>=20
> The branch to check out by git clone can be overridden via a special
> file in the .git directory in the shared repository. Unfortunately
> though, I don't remember what it's called...
According to Julien Cristau of the Debian X Strike Force (none of the
Git repos of which have a master branch), it should be .git/HEAD. Some
experiments of mine seem to confirm this.
--=20
Earthling Michel D=C3=A4nzer | http://www.vmware.c=
om
Libre software enthusiast | Debian, X and DRI developer
^ permalink raw reply
* Re: Badness at kernel/time/timekeeping.c:98 in pmud (timekeeping_suspended)
From: Rafael J. Wysocki @ 2009-02-08 13:39 UTC (permalink / raw)
To: Paul Collins, Ingo Molnar; +Cc: linuxppc-dev, Thomas Gleixner, linux-kernel
In-Reply-To: <874oz5pmvd.fsf@burly.wgtn.ondioline.org>
On Sunday 08 February 2009, Paul Collins wrote:
> Paul Collins <paul@burly.ondioline.org> writes:
>
> > "Rafael J. Wysocki" <rjw@sisk.pl> writes:
> >
> >> On Wednesday 21 January 2009, Paul Collins wrote:
> >>> Got a couple of these on a PowerBook running 2.6.29-rc2 either during
> >>> suspend or resume -- it's hard to tell. (The suspend message is
> >>> timestamped in syslog with the time I resumed, so I guess it was
> >>> buffered along with the subsequent "Badness" messages.)
> >>
> >> Please check if the patch from http://lkml.org/lkml/2009/1/13/144 fixes the
> >> problem for you.
> >
> > It does not fix the problem.
>
> I'm also getting this warning since 2.6.28.1, which incorporated commit
> 1c5745aa380efb6417b5681104b007c8612fb496 ("sched_clock: prevent
> scd->clock from moving backwards, take #2") as commit
> e268dcdd404f4558cdd24c8ecede3e064df8fa33, this being the patch that
> introduced the WARN_ON(timekeeping_suspended) check.
Hm, I thought the timekeeping suspend problem was fixed in this commit. Ingo?
^ permalink raw reply
* Re: Badness at kernel/time/timekeeping.c:98 in pmud (timekeeping_suspended)
From: Ingo Molnar @ 2009-02-08 15:11 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: linuxppc-dev, Thomas Gleixner, Paul Collins, linux-kernel
In-Reply-To: <200902081439.31548.rjw@sisk.pl>
* Rafael J. Wysocki <rjw@sisk.pl> wrote:
> On Sunday 08 February 2009, Paul Collins wrote:
> > Paul Collins <paul@burly.ondioline.org> writes:
> >
> > > "Rafael J. Wysocki" <rjw@sisk.pl> writes:
> > >
> > >> On Wednesday 21 January 2009, Paul Collins wrote:
> > >>> Got a couple of these on a PowerBook running 2.6.29-rc2 either during
> > >>> suspend or resume -- it's hard to tell. (The suspend message is
> > >>> timestamped in syslog with the time I resumed, so I guess it was
> > >>> buffered along with the subsequent "Badness" messages.)
> > >>
> > >> Please check if the patch from http://lkml.org/lkml/2009/1/13/144 fixes the
> > >> problem for you.
> > >
> > > It does not fix the problem.
> >
> > I'm also getting this warning since 2.6.28.1, which incorporated commit
> > 1c5745aa380efb6417b5681104b007c8612fb496 ("sched_clock: prevent
> > scd->clock from moving backwards, take #2") as commit
> > e268dcdd404f4558cdd24c8ecede3e064df8fa33, this being the patch that
> > introduced the WARN_ON(timekeeping_suspended) check.
>
> Hm, I thought the timekeeping suspend problem was fixed in this commit. Ingo?
Thomas? :-)
Ingo
^ permalink raw reply
* Re: [PATCH RFC 0/11] FSL eSDHC support: second call for comments
From: Pierre Ossman @ 2009-02-08 20:33 UTC (permalink / raw)
To: avorontsov
Cc: Ben Dooks, Arnd Bergmann, Liu Dave, linux-kernel, linuxppc-dev,
sdhci-devel, Pierre Ossman
In-Reply-To: <20090206180520.GA16123@oksana.dev.rtsoft.ru>
[-- Attachment #1: Type: text/plain, Size: 575 bytes --]
On Fri, 6 Feb 2009 21:05:20 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> Hi all,
>
> There were only a few comments on the previous version. So, here is
> the second call for comments.
>
Yeah sorry, haven't really had time for looking over your patches
properly. See my first comments to relevant patches now though.
Rgds
--
-- Pierre Ossman
WARNING: This correspondence is being monitored by the
Swedish government. Make sure your server uses encryption
for SMTP traffic and consider using PGP for end-to-end
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^ permalink raw reply
* Re: [PATCH 02/11] sdhci: Add support for bus-specific IO memory accessors
From: Pierre Ossman @ 2009-02-08 20:50 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Ben Dooks, Arnd Bergmann, Liu Dave, linux-kernel, linuxppc-dev,
sdhci-devel
In-Reply-To: <20090206180645.GB11548@oksana.dev.rtsoft.ru>
[-- Attachment #1: Type: text/plain, Size: 1897 bytes --]
On Fri, 6 Feb 2009 21:06:45 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
> read{l,b,w}).
>
> With this patch drivers may change memory accessors, so that we can
> support hosts with "weird" IO memory access requirments.
>
> For example, in "FSL eSDHC" SDHCI hardware all registers are 32 bit
> width, with big-endian addressing. That is, readb(0x2f) should turn
> into readb(0x2c), and readw(0x2c) should be translated to
> le16_to_cpu(readw(0x2e)).
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
I was hoping we wouldn't have to do a lot of magic in the accessors
since the spec is rather clear on the register interface. :/
Let's see if I've understood this correctly.
1. The CPU is big-endian but the register are little-endian (as the
spec requires). I was under the impression that the read*/write*
accessor handled any endian conversion between the bus and the cpu? How
do e.g. PCI work on Sparc?
2. Register access must be done 32 bits at a time. Now this is just
broken and might cause big problems as some registers cannot just be
read and written back to. OTOH you refer to readw() in your example,
not readl(). What's the deal here?
> +static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
> +{
> + host->writel(host, val, reg);
> +}
Having to override these are worst case scenario as far as I'm
concerned, so I'd prefer something like:
if (!host->ops->writel)
writel(host->ioaddr + reg, val);
else
host->ops->writel(host, val, reg);
and maybe even a likely() up there.
Rgds
--
-- Pierre Ossman
WARNING: This correspondence is being monitored by the
Swedish government. Make sure your server uses encryption
for SMTP traffic and consider using PGP for end-to-end
encryption.
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* Re: [PATCH 03/11] sdhci: Add type checking for IO memory accessors
From: Pierre Ossman @ 2009-02-08 20:53 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Ben Dooks, Arnd Bergmann, Liu Dave, linux-kernel, linuxppc-dev,
sdhci-devel, Pierre Ossman
In-Reply-To: <20090206180648.GC11548@oksana.dev.rtsoft.ru>
[-- Attachment #1: Type: text/plain, Size: 1375 bytes --]
On Fri, 6 Feb 2009 21:06:48 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> A new restricted integer type introduced: sdhci_reg_t.
>
> Header file now specifies registers via sdhci_reg() inline function.
> Only one place (not counting sdhci_def_*() accessors) need to cast
> a register back to an offset, i.e. sdhci_finish_command().
>
> From now on sparse tool will warn about IO memory accessors misuses,
> for exampple:
>
> sdhci_writeb(host, SDHCI_TIMEOUT_CONTROL, count);
>
> CHECK sdhci.c
> sdhci.c:614:21: warning: incorrect type in argument 2 (different base types)
> sdhci.c:614:21: expected unsigned char [unsigned] [usertype] val
> sdhci.c:614:21: got restricted int
> sdhci.c:614:44: warning: incorrect type in argument 3 (different base types)
> sdhci.c:614:44: expected restricted int [usertype] reg
> sdhci.c:614:44: got unsigned char [unsigned] [assigned] [usertype] count
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
Is this really a problem? It's a lot of noise in the code and I can't
really see this as a major issue, or even a minor one. :)
Rgds
--
-- Pierre Ossman
WARNING: This correspondence is being monitored by the
Swedish government. Make sure your server uses encryption
for SMTP traffic and consider using PGP for end-to-end
encryption.
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^ permalink raw reply
* Re: [PATCH 04/11] sdhci: Add support for card-detection polling
From: Pierre Ossman @ 2009-02-08 20:57 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Ben Dooks, Arnd Bergmann, Liu Dave, linux-kernel, linuxppc-dev,
sdhci-devel
In-Reply-To: <20090206180650.GD11548@oksana.dev.rtsoft.ru>
[-- Attachment #1: Type: text/plain, Size: 1802 bytes --]
On Fri, 6 Feb 2009 21:06:50 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> This patch adds SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk. When specified,
> sdhci driver will set MMC_CAP_NEEDS_POLL MMC host capability, and won't
> enable card insert/remove interrupts.
>
> This is needed for hosts with unreliable card detection, such as FSL
> eSDHC. The original eSDHC driver was tring to "debounce" card-detection
> IRQs by reading present state and disabling particular interrupts. But
> with this debouncing scheme I noticed that sometimes we miss card
> insertion/removal events.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
I guess you need to fix the check at the start of the request function
as well.
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index b7a79a0..45c5f1f 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -162,6 +162,9 @@ static void sdhci_init(struct sdhci_host *host)
> SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
> SDHCI_INT_ADMA_ERROR;
>
> + if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
> + intmask &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
> +
A matter of taste perhaps, but I think it would make more sense to not
add them in the first place than to add and then remove them.
Card detection interrupts should be handled separately anyway as they
should not be enabled before mmc_add_host() returns and should be
disabled before calling mmc_remove_host(). Patch welcome. ;)
Rgds
--
-- Pierre Ossman
WARNING: This correspondence is being monitored by the
Swedish government. Make sure your server uses encryption
for SMTP traffic and consider using PGP for end-to-end
encryption.
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^ permalink raw reply
* Re: [PATCH 07/11] sdhci: Add quirk to suppress PIO interrupts during DMA transfers
From: Pierre Ossman @ 2009-02-08 21:02 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Ben Dooks, Arnd Bergmann, Liu Dave, linux-kernel, linuxppc-dev,
sdhci-devel
In-Reply-To: <20090206180655.GG11548@oksana.dev.rtsoft.ru>
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On Fri, 6 Feb 2009 21:06:55 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> Some hosts (that is, FSL eSDHC) throw PIO interrupts during DMA
> transfers, this causes tons of unneeded interrupts, and thus highly
> degraded speed.
>
> This patch adds SDHCI_QUIRK_PIO_IRQS_DURING_DMA quirk. When specified,
> the sdhci driver will disable PIO interrupts during DMA transfers.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
It's probably better to change the interrupt handling to only enable
relevant interrupts instead of having everything on constantly. Too
many quirks just makes the driver difficult to understand.
--
-- Pierre Ossman
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* Re: [PATCH 08/11] sdhci: Add support for hosts that don't specify clocks in the cap. register
From: Pierre Ossman @ 2009-02-08 21:04 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Ben Dooks, Arnd Bergmann, Liu Dave, linux-kernel, linuxppc-dev,
sdhci-devel
In-Reply-To: <20090206180657.GH11548@oksana.dev.rtsoft.ru>
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On Fri, 6 Feb 2009 21:06:57 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> FSL eSDHC hosts don't provide clocks bits in the capabilities register,
> instead we're getting clocks values from the device tree.
>
> There is somewhat similar change[1] from Ben Dooks, the change adds
> callbacks for getting the clocks. But for eSDHC the callbacks are
> superfluous, since the clocks are static.
>
> [1] http://lkml.org/lkml/2008/12/2/157
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
As I told Ben, I prefer if we stick to the standard as much as
possible. So no external info unless the register is set to zero.
And since we know the Samsung chip needs callbacks, we might as well
add them here. It's not like this is a performance critical path.
Rgds
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* Re: [PATCH 09/11] sdhci: Add set_clock callback
From: Pierre Ossman @ 2009-02-08 21:06 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Ben Dooks, Arnd Bergmann, Liu Dave, linux-kernel, linuxppc-dev,
sdhci-devel
In-Reply-To: <20090206180659.GI11548@oksana.dev.rtsoft.ru>
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On Fri, 6 Feb 2009 21:06:59 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> FSL eSDHC hosts have incompatible register map to manage the SDCLK.
> This patch adds set_clock callback so that drivers could overwrite
> set_clock behaviour.
>
> Similar patch[1] was posted by Ben Dooks, though in Ben's version the
> callback is named change_clock, plus the patch has some unrelated bits
> that makes the patch difficult to reuse.
>
> [1] http://lkml.org/lkml/2008/12/2/160
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
A set_clock() callback is reasonable as there might be a clock source
that needs to be set up, but completely overriding the normal routine
(i.e. the "return") should be quirked IMO.
Rgds
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* Re: [PATCH 10/11] sdhci: Add quirk for Freescale eSDHC controllers
From: Pierre Ossman @ 2009-02-08 21:12 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Ben Dooks, Arnd Bergmann, Liu Dave, linux-kernel, linuxppc-dev,
sdhci-devel
In-Reply-To: <20090206180701.GJ11548@oksana.dev.rtsoft.ru>
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On Fri, 6 Feb 2009 21:07:01 +0300
Anton Vorontsov <avorontsov@ru.mvista.com> wrote:
> This patch adds SDHCI_QUIRK_FSL quirk. The quirk is used to instruct
> the sdhci driver about various FSL eSDHC host incompatibilities:
>
No device quirks please. They should be for specific bugs, not lumping
things together like this. Otherwise we'll soon have an unmanageable
mess.
> 1) FSL eSDHC controllers can support maximum block size up to 4096
> bytes. The MBL (Maximum Block Length) field in the capabilities
> register extended by one bit.
>
> (Should we implement a dedicated quirk for this? I.e.
> SDHCI_QUIRK_MAX_BLK_SZ_4096?)
>
Yes please. It would have to mean "always support 4096" though, not
"turn reserved bit 18 into a block length bit".
> 2) sdhci_init() is needed after error conditions.
>
> (Can we safely do this for all controllers?)
>
Please investigate which part of sdhci_init() is needed. How does it
break without this?
> 3) Small udelay is needed to make eSDHC work in PIO mode. Without
> the delay reading causes endless interrupt storm, and writing
> corrupts data. The first guess would be that we must wait for
> some bit in some register, but I didn't find any reliable bits
> that changes before and after the delay. Though, more investigation
> on this is in my todo list.
Please try to investigate more, but if you cannot improve it further
then a specific quirk can be added.
Rgds
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* [PATCH] powerpc/cell: add missing #include for oprofile
From: Michael Neuling @ 2009-02-08 23:04 UTC (permalink / raw)
To: Maynard Johnson, Carl Love, Arnd Bergmann; +Cc: linuxppc-dev
arch/powerpc/oprofile/cell/spu_profiler.c is missing a asm/time.h
include which is required for ppc_proc_freq. This can cause compile
failures for some config combinations.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
This is against mainline, so should be pushed up soon-ish
arch/powerpc/oprofile/cell/spu_profiler.c | 1 +
1 file changed, 1 insertion(+)
Index: linux-2.6-ozlabs/arch/powerpc/oprofile/cell/spu_profiler.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/oprofile/cell/spu_profiler.c
+++ linux-2.6-ozlabs/arch/powerpc/oprofile/cell/spu_profiler.c
@@ -16,6 +16,7 @@
#include <linux/smp.h>
#include <linux/slab.h>
#include <asm/cell-pmu.h>
+#include <asm/time.h>
#include "pr_util.h"
#define SCALE_SHIFT 14
^ permalink raw reply
* Re: [patch] powerpc/ps3: Use hard coded values for LV1 device type
From: Benjamin Herrenschmidt @ 2009-02-09 0:11 UTC (permalink / raw)
To: michael
Cc: Mel Gorman, Kamalesh Babulal, James Bottomley, linuxppc-dev,
Jens Axboe
In-Reply-To: <1234092590.10240.4.camel@localhost>
On Sun, 2009-02-08 at 22:29 +1100, Michael Ellerman wrote:
> On Fri, 2009-02-06 at 18:42 -0800, Geoff Levand wrote:
> > Change the PS3 platform code to use hard coded numbers for its
> > LV1 device types.
> >
> > The PS3 platform code was incorrectly using some scsi block
> > constants for the device type returned from the LV1 hypervisor.
> >
> > Fixes build errors like these when CONFIG_BLOCK=n:
> >
> > In file included from include/scsi/scsi.h:12,
> > from arch/powerpc/platforms/ps3/platform.h:25,
> > from arch/powerpc/platforms/ps3/setup.c:36:
> > include/scsi/scsi_cmnd.h:27:25: warning: "BLK_MAX_CDB" is not defined
> > include/scsi/scsi_cmnd.h:28:3: error: #error MAX_COMMAND_SIZE can not be bigger than BLK_MAX_CDB
Adding Jens and James on CC since I think a proper fix lies in blkdev.h
or scsi*.h
So basically, the whole of blkdev.h is inside a big ifdef
CONFIG_BLOCK... which means that scsi_cmnd.h can't build which in turn
makes scsi.h fail.
The PS3 platform code wants to use some of the standard SCSI types from
there though, as they are part of the hypervisor ABI. (And in fact it
can be argued that non-block devices using SCSI do exist, such as
scanners, no ?)
Any reason other than pre-historical to have blkdev.h shielded like
that ?
Cheers,
Ben.
> > Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
> > ---
> > Ben,
> >
> > Please send upstream for 2.6.29.
> >
> > -Geoff
> >
> > arch/powerpc/platforms/ps3/platform.h | 8 +++-----
> > 1 file changed, 3 insertions(+), 5 deletions(-)
> >
> > --- a/arch/powerpc/platforms/ps3/platform.h
> > +++ b/arch/powerpc/platforms/ps3/platform.h
> > @@ -22,8 +22,6 @@
> > #define _PS3_PLATFORM_H
> >
> > #include <linux/rtc.h>
> > -#include <scsi/scsi.h>
> > -
> > #include <asm/ps3.h>
> >
> > /* htab */
> > @@ -83,12 +81,12 @@ enum ps3_bus_type {
> > };
> >
> > enum ps3_dev_type {
> > - PS3_DEV_TYPE_STOR_DISK = TYPE_DISK, /* 0 */
> > + PS3_DEV_TYPE_STOR_DISK = 0, /* TYPE_DISK */
> > PS3_DEV_TYPE_SB_GELIC = 3,
> > PS3_DEV_TYPE_SB_USB = 4,
> > - PS3_DEV_TYPE_STOR_ROM = TYPE_ROM, /* 5 */
> > + PS3_DEV_TYPE_STOR_ROM = 5, /* TYPE_ROM */
> > PS3_DEV_TYPE_SB_GPIO = 6,
> > - PS3_DEV_TYPE_STOR_FLASH = TYPE_RBC, /* 14 */
> > + PS3_DEV_TYPE_STOR_FLASH = 14, /* TYPE_RBC */
>
> This looks like you're just papering over the bug, by hardcoding the
> same values that are in the scsi header. Or are they really independent,
> in which case I'd say the comments are confusing.
>
> cheers
>
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