* Re: [PATCH] powerpc: rework dma-noncoherent to use generic vmap/vunmap functions
From: Benjamin Herrenschmidt @ 2009-02-12 20:41 UTC (permalink / raw)
To: Ilya Yanok; +Cc: linuxppc-dev, wd, dzu
In-Reply-To: <49945EFE.8000401@emcraft.com>
> btw, ioremap doesn't provide useful 'caller').
I fixed that :-) (see patches I posted to the list, though that's
waiting for a patch to go upstream first that adds a
__get_vm_area_caller() that I need for ppc64).
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v2] powerpc/fsl-booke: Add new ISA 2.06 page sizes and MAS defines
From: Benjamin Herrenschmidt @ 2009-02-12 20:42 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list
In-Reply-To: <4B32B56D-9BCC-4ABA-A2AD-BCACFB30D18F@kernel.crashing.org>
On Thu, 2009-02-12 at 13:21 -0600, Kumar Gala wrote:
> On Feb 10, 2009, at 6:26 PM, Kumar Gala wrote:
>
> > The Power ISA 2.06 added power of two page sizes to the embedded MMU
> > architecture. Its done it such a way to be code compatiable with the
> > existing HW. Made the minor code changes to support both power of two
> > and power of four page sizes. Also added some new MAS bits and macros
> > that are defined as part of the 2.06 ISA.
> >
> > Note, its still invalid to try and use a page size that isn't
> > supported
> > by cpu.
> >
> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> > ---
> > * Fixed MAS6_ISIZE macro
> >
> > arch/powerpc/include/asm/mmu-fsl-booke.h | 54 +++++++++++++++++++
> > +----------
>
> Do you want to rename asm/mmu-fsl-booke.h => mmu-booke.h (per ISA 2.06
> changes)?
I've actually been wondering about that indeed ... No objection if you
want to move forward with that !
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: rework dma-noncoherent to use generic vmap/vunmap functions
From: Ilya Yanok @ 2009-02-12 21:03 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, wd, dzu
In-Reply-To: <1234471294.29851.59.camel@pasglop>
Hi Ben,
Benjamin Herrenschmidt wrote:
>> btw, ioremap doesn't provide useful 'caller').
>>
>
> I fixed that :-) (see patches I posted to the list, though that's
> waiting for a patch to go upstream first that adds a
> __get_vm_area_caller() that I need for ppc64).
>
Yep, I saw them. Btw, I've posted update consistent memory patch in a
new thread please take a look.
Regards, Ilya.
^ permalink raw reply
* Re: writel hangs system
From: Grant Likely @ 2009-02-12 21:18 UTC (permalink / raw)
To: Tobias Knutsson; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <ccb913ac0902100507x69113827m757f3b8fbd0ac6f4@mail.gmail.com>
On Tue, Feb 10, 2009 at 6:07 AM, Tobias Knutsson
<tobias.knutsson@gmail.com> wrote:
> Hello,
>
> I'm in the process of porting a PCI-driver for a dsp-board from 2.4 to
> 2.6. The probing of the driver goes well, IRQs are setup, resources
> are claimed and remapped without any problems. Reading from I/O
> regions also works well. However, when i try to read or write to a
> memory region using readl/writel, the system instantly hangs. No
> stacktrace or anything, it just stops.
Hmmm. Not good. Are you able to access the memory regions from the
U-Boot console?
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH v2] powerpc/fsl-booke: Add new ISA 2.06 page sizes and MAS defines
From: Kumar Gala @ 2009-02-12 21:58 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev list
In-Reply-To: <20090212203409.GA2385@yoda.jdub.homelinux.org>
On Feb 12, 2009, at 2:34 PM, Josh Boyer wrote:
> On Thu, Feb 12, 2009 at 01:21:24PM -0600, Kumar Gala wrote:
>>
>> On Feb 10, 2009, at 6:26 PM, Kumar Gala wrote:
>>
>>> The Power ISA 2.06 added power of two page sizes to the embedded MMU
>>> architecture. Its done it such a way to be code compatiable with
>>> the
>>> existing HW. Made the minor code changes to support both power of
>>> two
>>> and power of four page sizes. Also added some new MAS bits and
>>> macros
>>> that are defined as part of the 2.06 ISA.
>>>
>>> Note, its still invalid to try and use a page size that isn't
>>> supported
>>> by cpu.
>>>
>>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>>> ---
>>> * Fixed MAS6_ISIZE macro
>>>
>>> arch/powerpc/include/asm/mmu-fsl-booke.h | 54 +++++++++++++++++++
>>> +----------
>>
>> Do you want to rename asm/mmu-fsl-booke.h => mmu-booke.h (per ISA
>> 2.06
>> changes)?
>
> Misleading perhaps. ISA 2.06 is really new and we've been calling 4xx
> and FSL booke for a while now.
I can call it mmu-book3e.h if you think that might enough different to
convey the ISA 2.06 fact that the FSL style MMU is now part of the 3e
architecture.
- k
^ permalink raw reply
* Re: [PATCH v2] powerpc/fsl-booke: Add new ISA 2.06 page sizes and MAS defines
From: Benjamin Herrenschmidt @ 2009-02-12 22:04 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list
In-Reply-To: <54A20554-3C7B-4EE7-B3CF-362AEB27CA64@kernel.crashing.org>
> I can call it mmu-book3e.h if you think that might enough different to
> convey the ISA 2.06 fact that the FSL style MMU is now part of the 3e
> architecture.
That's better. book3e is what I've been using internally...
Cheers,
Ben.
^ permalink raw reply
* [PATCH] powerpc: Fix _PAGE_CHG_MASK
From: Philippe Gerum @ 2009-02-12 22:18 UTC (permalink / raw)
To: linuxppc-dev
Fix _PAGE_CHG_MASK so that pte_modify() does not affect the _PAGE_SPECIAL bit.
Signed-off-by: Philippe Gerum <rpm@xenomai.org>
--
arch/powerpc/include/asm/pgtable-4k.h | 2 +-
arch/powerpc/include/asm/pgtable-64k.h | 2 +-
arch/powerpc/include/asm/pgtable-ppc32.h | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-4k.h b/arch/powerpc/include/asm/pgtable-4k.h
index 6b18ba9..1dbca4e 100644
--- a/arch/powerpc/include/asm/pgtable-4k.h
+++ b/arch/powerpc/include/asm/pgtable-4k.h
@@ -60,7 +60,7 @@
/* It should be preserving the high 48 bits and then specifically */
/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
- _PAGE_HPTEFLAGS)
+ _PAGE_HPTEFLAGS | _PAGE_SPECIAL)
/* Bits to mask out from a PMD to get to the PTE page */
#define PMD_MASKED_BITS 0
diff --git a/arch/powerpc/include/asm/pgtable-64k.h b/arch/powerpc/include/asm/pgtable-64k.h
index 07b0d8f..7389003 100644
--- a/arch/powerpc/include/asm/pgtable-64k.h
+++ b/arch/powerpc/include/asm/pgtable-64k.h
@@ -114,7 +114,7 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
* pgprot changes
*/
#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
- _PAGE_ACCESSED)
+ _PAGE_ACCESSED | _PAGE_SPECIAL)
/* Bits to mask out from a PMD to get to the PTE page */
#define PMD_MASKED_BITS 0x1ff
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index 75dded6..8298afc 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -428,8 +428,8 @@ extern int icache_44x_need_flush;
#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
#endif
-#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_SPECIAL)
-
+#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
+ _PAGE_SPECIAL)
#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
_PAGE_WRITETHRU | _PAGE_ENDIAN | \
--
Philippe.
^ permalink raw reply related
* Re: [MPC8272ADS]Problem adding flash partitions inside the device tree
From: Scott Wood @ 2009-02-12 22:24 UTC (permalink / raw)
To: Jean-Michel Hautbois; +Cc: linuxppc-dev
In-Reply-To: <8cad0aa0902120626v733011a5u669fc30096565d86@mail.gmail.com>
On Thu, Feb 12, 2009 at 03:26:58PM +0100, Jean-Michel Hautbois wrote:
> I think that the problem is in the reg part, but I can't understand why.
> Isn't it the RAM mpping of my MTD that is the first address ?
No, it's the offset into the chipselect.
-Scott
^ permalink raw reply
* [patch] powerpc: fix numa reserve bootmem page selection
From: Geoff Levand @ 2009-02-12 22:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Linuxppc-dev, Jon Tollefson, Johannes Weiner, Dave Hansen
In-Reply-To: <49924348.5050702@am.sony.com>
From: Dave Hansen <dave@linux.vnet.ibm.com>
Fix the powerpc NUMA reserve bootmem page selection logic.
commit 8f64e1f2d1e09267ac926e15090fd505c1c0cbcb (powerpc: Reserve
in bootmem lmb reserved regions that cross NUMA nodes) changed
the logic for how the powerpc LMB reserved regions were converted
to bootmen reserved regions. As the folowing discussion reports,
the new logic was not correct.
mark_reserved_regions_for_nid() goes through each LMB on the
system that specifies a reserved area. It searches for
active regions that intersect with that LMB and are on the
specified node. It attempts to bootmem-reserve only the area
where the active region and the reserved LMB intersect. We
can not reserve things on other nodes as they may not have
bootmem structures allocated, yet.
We base the size of the bootmem reservation on two possible
things. Normally, we just make the reservation start and
stop exactly at the start and end of the LMB.
However, the LMB reservations are not aware of NUMA nodes and
on occasion a single LMB may cross into several adjacent
active regions. Those may even be on different NUMA nodes
and will require separate calls to the bootmem reserve
functions. So, the bootmem reservation must be trimmed to
fit inside the current active region.
That's all fine and dandy, but we trim the reservation
in a page-aligned fashion. That's bad because we start the
reservation at a non-page-aligned address: physbase.
The reservation may only span 2 bytes, but that those bytes
may span two pfns and cause a reserve_size of 2*PAGE_SIZE.
Take the case where you reserve 0x2 bytes at 0x0fff and
where the active region ends at 0x1000. You'll jump into
that if() statment, but node_ar.end_pfn=0x1 and
start_pfn=0x0. You'll end up with a reserve_size=0x1000,
and then call
reserve_bootmem_node(node, physbase=0xfff, size=0x1000);
0x1000 may not be on the same node as 0xfff. Oops.
In almost all the vm code, end_<anything> is not inclusive.
If you have an end_pfn of 0x1234, page 0x1234 is not
included in the range. Using PFN_UP instead of the
(>> >> PAGE_SHIFT) will make this consistent with the other VM
code.
We also need to do math for the reserved size with physbase
instead of start_pfn. node_ar.end_pfn << PAGE_SHIFT is
*precisely* the end of the node. However,
(start_pfn << PAGE_SHIFT) is *NOT* precisely the beginning
of the reserved area. That is, of course, physbase.
If we don't use physbase here, the reserve_size can be
made too large.
From: Dave Hansen <dave@linux.vnet.ibm.com>
Tested-by: Geoff Levand <geoffrey.levand@am.sony.com> Tested on PS3.
---
linux-2.6.git-dave/arch/powerpc/mm/numa.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff -puN arch/powerpc/mm/numa.c~reserve-over-fix arch/powerpc/mm/numa.c
--- a/arch/powerpc/mm/numa.c~reserve-over-fix
+++ b/arch/powerpc/mm/numa.c
@@ -19,6 +19,7 @@
#include <linux/notifier.h>
#include <linux/lmb.h>
#include <linux/of.h>
+#include <linux/pfn.h>
#include <asm/sparsemem.h>
#include <asm/prom.h>
#include <asm/system.h>
@@ -882,7 +883,7 @@ static void mark_reserved_regions_for_ni
unsigned long physbase = lmb.reserved.region[i].base;
unsigned long size = lmb.reserved.region[i].size;
unsigned long start_pfn = physbase >> PAGE_SHIFT;
- unsigned long end_pfn = ((physbase + size) >> PAGE_SHIFT);
+ unsigned long end_pfn = PFN_UP(physbase + size);
struct node_active_region node_ar;
unsigned long node_end_pfn = node->node_start_pfn +
node->node_spanned_pages;
@@ -908,7 +909,7 @@ static void mark_reserved_regions_for_ni
*/
if (end_pfn > node_ar.end_pfn)
reserve_size = (node_ar.end_pfn << PAGE_SHIFT)
- - (start_pfn << PAGE_SHIFT);
+ - physbase;
/*
* Only worry about *this* node, others may not
* yet have valid NODE_DATA().
^ permalink raw reply
* [patch] powerpc/ps3: Move ps3_mm_add_memory to device_initcall
From: Geoff Levand @ 2009-02-12 22:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Linuxppc-dev
In-Reply-To: <49935F81.7060203@am.sony.com>
Change the PS3 hotplug memory routine ps3_mm_add_memory() from
a core_initcall to a device_initcall.
core_initcall routines run before the powerpc topology_init()
startup routine, which is a subsys_initcall, resulting in
failure of ps3_mm_add_memory() when CONFIG_NUMA=y. When
ps3_mm_add_memory() fails the system will boot with just the
128 MiB of boot memory
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
---
Ben,
Please send upstream for 2.6.29, as this effects the current
Fedora 11 development kernel, and maybe other distros which
are based on 2.6.29.
arch/powerpc/platforms/ps3/mm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -328,7 +328,7 @@ static int __init ps3_mm_add_memory(void
return result;
}
-core_initcall(ps3_mm_add_memory);
+device_initcall(ps3_mm_add_memory);
/*============================================================================*/
/* dma routines */
^ permalink raw reply
* [PATCH v2 1/2] powerpc/fsl-booke: Add new ISA 2.06 page sizes and MAS defines
From: Kumar Gala @ 2009-02-12 22:46 UTC (permalink / raw)
To: linuxppc-dev
The Power ISA 2.06 added power of two page sizes to the embedded MMU
architecture. Its done it such a way to be code compatiable with the
existing HW. Made the minor code changes to support both power of two
and power of four page sizes. Also added some new MAS bits and macros
that are defined as part of the 2.06 ISA. Renamed some things to use
the 'Book-3e' concept to convey the new MMU that is based on the
Freescale Book-E MMU programming model.
Note, its still invalid to try and use a page size that isn't supported
by cpu.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Some minor changes to prime for the rename of mmu-fsl-booke.h -> mmu-book3e.h
arch/powerpc/include/asm/mmu-fsl-booke.h | 66 +++++++++++++++++++-----------
arch/powerpc/kernel/head_fsl_booke.S | 14 +++---
arch/powerpc/mm/fsl_booke_mmu.c | 2 +-
3 files changed, 50 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-fsl-booke.h b/arch/powerpc/include/asm/mmu-fsl-booke.h
index 3f941c0..c5363c3 100644
--- a/arch/powerpc/include/asm/mmu-fsl-booke.h
+++ b/arch/powerpc/include/asm/mmu-fsl-booke.h
@@ -1,26 +1,42 @@
-#ifndef _ASM_POWERPC_MMU_FSL_BOOKE_H_
-#define _ASM_POWERPC_MMU_FSL_BOOKE_H_
+#ifndef _ASM_POWERPC_MMU_BOOK3E_H_
+#define _ASM_POWERPC_MMU_BOOK3E_H_
/*
- * Freescale Book-E MMU support
+ * Freescale Book-E/Book-3e (ISA 2.06+) MMU support
*/
-/* Book-E defined page sizes */
-#define BOOKE_PAGESZ_1K 0
-#define BOOKE_PAGESZ_4K 1
-#define BOOKE_PAGESZ_16K 2
-#define BOOKE_PAGESZ_64K 3
-#define BOOKE_PAGESZ_256K 4
-#define BOOKE_PAGESZ_1M 5
-#define BOOKE_PAGESZ_4M 6
-#define BOOKE_PAGESZ_16M 7
-#define BOOKE_PAGESZ_64M 8
-#define BOOKE_PAGESZ_256M 9
-#define BOOKE_PAGESZ_1GB 10
-#define BOOKE_PAGESZ_4GB 11
-#define BOOKE_PAGESZ_16GB 12
-#define BOOKE_PAGESZ_64GB 13
-#define BOOKE_PAGESZ_256GB 14
-#define BOOKE_PAGESZ_1TB 15
+/* Book-3e defined page sizes */
+#define BOOK3E_PAGESZ_1K 0
+#define BOOK3E_PAGESZ_2K 1
+#define BOOK3E_PAGESZ_4K 2
+#define BOOK3E_PAGESZ_8K 3
+#define BOOK3E_PAGESZ_16K 4
+#define BOOK3E_PAGESZ_32K 5
+#define BOOK3E_PAGESZ_64K 6
+#define BOOK3E_PAGESZ_128K 7
+#define BOOK3E_PAGESZ_256K 8
+#define BOOK3E_PAGESZ_512K 9
+#define BOOK3E_PAGESZ_1M 10
+#define BOOK3E_PAGESZ_2M 11
+#define BOOK3E_PAGESZ_4M 12
+#define BOOK3E_PAGESZ_8M 13
+#define BOOK3E_PAGESZ_16M 14
+#define BOOK3E_PAGESZ_32M 15
+#define BOOK3E_PAGESZ_64M 16
+#define BOOK3E_PAGESZ_128M 17
+#define BOOK3E_PAGESZ_256M 18
+#define BOOK3E_PAGESZ_512M 19
+#define BOOK3E_PAGESZ_1GB 20
+#define BOOK3E_PAGESZ_2GB 21
+#define BOOK3E_PAGESZ_4GB 22
+#define BOOK3E_PAGESZ_8GB 23
+#define BOOK3E_PAGESZ_16GB 24
+#define BOOK3E_PAGESZ_32GB 25
+#define BOOK3E_PAGESZ_64GB 26
+#define BOOK3E_PAGESZ_128GB 27
+#define BOOK3E_PAGESZ_256GB 28
+#define BOOK3E_PAGESZ_512GB 29
+#define BOOK3E_PAGESZ_1TB 30
+#define BOOK3E_PAGESZ_2TB 31
#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
@@ -29,8 +45,9 @@
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
+#define MAS1_IND 0x00002000
#define MAS1_TS 0x00001000
-#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
+#define MAS1_TSIZE(x) ((x << 7) & 0x00000F80)
#define MAS2_EPN 0xFFFFF000
#define MAS2_X0 0x00000040
@@ -40,7 +57,7 @@
#define MAS2_M 0x00000004
#define MAS2_G 0x00000002
#define MAS2_E 0x00000001
-#define MAS2_EPN_MASK(size) (~0 << (2*(size) + 10))
+#define MAS2_EPN_MASK(size) (~0 << (size + 10))
#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
#define MAS3_RPN 0xFFFFF000
@@ -56,7 +73,7 @@
#define MAS3_SR 0x00000001
#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
-#define MAS4_TIDDSEL 0x000F0000
+#define MAS4_INDD 0x00008000
#define MAS4_TSIZED(x) MAS1_TSIZE(x)
#define MAS4_X0D 0x00000040
#define MAS4_X1D 0x00000020
@@ -68,6 +85,7 @@
#define MAS6_SPID0 0x3FFF0000
#define MAS6_SPID1 0x00007FFE
+#define MAS6_ISIZE(x) MAS1_TSIZE(x)
#define MAS6_SAS 0x00000001
#define MAS6_SPID MAS6_SPID0
@@ -82,4 +100,4 @@ typedef struct {
} mm_context_t;
#endif /* !__ASSEMBLY__ */
-#endif /* _ASM_POWERPC_MMU_FSL_BOOKE_H_ */
+#endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 64ecb16..4ea6e1a 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -173,7 +173,7 @@ skpinv: addi r6,r6,1 /* Increment */
/* grab and fixup the RPN */
mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
- rlwinm r6,r6,25,27,30
+ rlwinm r6,r6,25,27,31
li r8,-1
addi r6,r6,10
slw r6,r8,r6 /* convert to mask */
@@ -199,7 +199,7 @@ skpinv: addi r6,r6,1 /* Increment */
xori r6,r4,1 /* Setup TMP mapping in the other Address space */
slwi r6,r6,12
oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
- ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
+ ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
mtspr SPRN_MAS1,r6
mfspr r6,SPRN_MAS2
li r7,0 /* temp EPN = 0 */
@@ -257,10 +257,10 @@ skpinv: addi r6,r6,1 /* Increment */
lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
mtspr SPRN_MAS0,r6
lis r6,(MAS1_VALID|MAS1_IPROT)@h
- ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
+ ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
mtspr SPRN_MAS1,r6
- lis r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@h
- ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@l
+ lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
+ ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
mtspr SPRN_MAS2,r6
mtspr SPRN_MAS3,r8
tlbwe
@@ -315,7 +315,7 @@ skpinv: addi r6,r6,1 /* Increment */
mtspr SPRN_IVPR,r4
/* Setup the defaults for TLB entries */
- li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
+ li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
#ifdef CONFIG_E200
oris r2,r2,MAS4_TLBSELD(1)@h
#endif
@@ -1116,7 +1116,7 @@ __secondary_start:
mtspr SPRN_SPRG3,r4
/* Setup the defaults for TLB entries */
- li r4,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
+ li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
mtspr SPRN_MAS4,r4
/* Jump to start_secondary */
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 3d8cf01..6d38d77 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -111,7 +111,7 @@ void settlbcam(int index, unsigned long virt, phys_addr_t phys,
unsigned int tsize, lz;
asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
- tsize = (21 - lz) / 2;
+ tsize = 21 - lz;
#ifdef CONFIG_SMP
if ((flags & _PAGE_NO_CACHE) == 0)
--
1.5.6.6
^ permalink raw reply related
* [PATCH 2/2] powerpc/book-3e: Introduce concept of Book-3e MMU
From: Kumar Gala @ 2009-02-12 22:46 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1234478808-31883-1-git-send-email-galak@kernel.crashing.org>
The Power ISA 2.06 spec introduces a standard MMU programming model that
is based on the Freescale Book-E MMU programing model. The Freescale
version is pretty backwards compatiable with the ISA 2.06 definition so
we are starting to refactor some of the Freescale code so it can be
easily shared.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
.../include/asm/{mmu-fsl-booke.h => mmu-book3e.h} | 0
arch/powerpc/include/asm/mmu.h | 6 +++---
arch/powerpc/platforms/Kconfig.cputype | 4 ++++
3 files changed, 7 insertions(+), 3 deletions(-)
rename arch/powerpc/include/asm/{mmu-fsl-booke.h => mmu-book3e.h} (100%)
diff --git a/arch/powerpc/include/asm/mmu-fsl-booke.h b/arch/powerpc/include/asm/mmu-book3e.h
similarity index 100%
rename from arch/powerpc/include/asm/mmu-fsl-booke.h
rename to arch/powerpc/include/asm/mmu-book3e.h
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 6e76399..5c78079 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -71,9 +71,9 @@ extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
#elif defined(CONFIG_44x)
/* 44x-style software loaded TLB */
# include <asm/mmu-44x.h>
-#elif defined(CONFIG_FSL_BOOKE)
-/* Freescale Book-E software loaded TLB */
-# include <asm/mmu-fsl-booke.h>
+#elif defined(CONFIG_PPC_BOOK3E_MMU)
+/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
+# include <asm/mmu-book3e.h>
#elif defined (CONFIG_PPC_8xx)
/* Motorola/Freescale 8xx software loaded TLB */
# include <asm/mmu-8xx.h>
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index e868b5c..9428c0e 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -210,6 +210,10 @@ config PPC_MMU_NOHASH
def_bool y
depends on !PPC_STD_MMU
+config PPC_BOOK3E_MMU
+ def_bool y
+ depends on FSL_BOOKE
+
config PPC_MM_SLICES
bool
default y if HUGETLB_PAGE || (PPC_STD_MMU_64 && PPC_64K_PAGES)
--
1.5.6.6
^ permalink raw reply related
* Re: request_irq return errno 38
From: David Gibson @ 2009-02-12 22:49 UTC (permalink / raw)
To: Timur Tabi; +Cc: scottwood, Vijay Nikam, linuxppc-dev
In-Reply-To: <ed82fe3e0902120839q54793762uc9b180a82cad45c7@mail.gmail.com>
On Thu, Feb 12, 2009 at 10:39:36AM -0600, Timur Tabi wrote:
> On Thu, Feb 12, 2009 at 4:51 AM, Vijay Nikam <vijay.t.nikam@gmail.com> wrote:
>
> > Also how I can read the device tree binary file ? ? ?
>
> It would be a lot simpler if you just read the documentation (see
> booting-without-of.txt) and looked at other device drivers to see what
> they do.
You don't need to directly read the device tree, the provided helper
functions (irq_parse_and_map() and the like) will read the device tree
for you.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* [PATCH v2 2/2] powerpc/book-3e: Introduce concept of Book-3e MMU
From: Kumar Gala @ 2009-02-12 22:52 UTC (permalink / raw)
To: linuxppc-dev
The Power ISA 2.06 spec introduces a standard MMU programming model that
is based on the Freescale Book-E MMU programing model. The Freescale
version is pretty backwards compatiable with the ISA 2.06 definition so
we are starting to refactor some of the Freescale code so it can be
easily shared.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Changed a few more CONFIG_FSL_BOOKE -> CONFIG_PPC_BOOK3E_MMU
.../include/asm/{mmu-fsl-booke.h => mmu-book3e.h} | 0
arch/powerpc/include/asm/mmu.h | 6 +++---
arch/powerpc/kernel/entry_32.S | 6 +++---
arch/powerpc/platforms/Kconfig.cputype | 4 ++++
4 files changed, 10 insertions(+), 6 deletions(-)
rename arch/powerpc/include/asm/{mmu-fsl-booke.h => mmu-book3e.h} (100%)
diff --git a/arch/powerpc/include/asm/mmu-fsl-booke.h b/arch/powerpc/include/asm/mmu-book3e.h
similarity index 100%
rename from arch/powerpc/include/asm/mmu-fsl-booke.h
rename to arch/powerpc/include/asm/mmu-book3e.h
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 6e76399..5c78079 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -71,9 +71,9 @@ extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
#elif defined(CONFIG_44x)
/* 44x-style software loaded TLB */
# include <asm/mmu-44x.h>
-#elif defined(CONFIG_FSL_BOOKE)
-/* Freescale Book-E software loaded TLB */
-# include <asm/mmu-fsl-booke.h>
+#elif defined(CONFIG_PPC_BOOK3E_MMU)
+/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
+# include <asm/mmu-book3e.h>
#elif defined (CONFIG_PPC_8xx)
/* Motorola/Freescale 8xx software loaded TLB */
# include <asm/mmu-8xx.h>
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 6f7eb7e..301c646 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -63,7 +63,7 @@ debug_transfer_to_handler:
.globl crit_transfer_to_handler
crit_transfer_to_handler:
-#ifdef CONFIG_FSL_BOOKE
+#ifdef CONFIG_PPC_BOOK3E_MMU
mfspr r0,SPRN_MAS0
stw r0,MAS0(r11)
mfspr r0,SPRN_MAS1
@@ -78,7 +78,7 @@ crit_transfer_to_handler:
mfspr r0,SPRN_MAS7
stw r0,MAS7(r11)
#endif /* CONFIG_PHYS_64BIT */
-#endif /* CONFIG_FSL_BOOKE */
+#endif /* CONFIG_PPC_BOOK3E_MMU */
#ifdef CONFIG_44x
mfspr r0,SPRN_MMUCR
stw r0,MMUCR(r11)
@@ -914,7 +914,7 @@ exc_exit_restart_end:
mtspr SPRN_##exc_lvl_srr0,r9; \
mtspr SPRN_##exc_lvl_srr1,r10;
-#if defined(CONFIG_FSL_BOOKE)
+#if defined(CONFIG_PPC_BOOK3E_MMU)
#ifdef CONFIG_PHYS_64BIT
#define RESTORE_MAS7 \
lwz r11,MAS7(r1); \
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index e868b5c..9428c0e 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -210,6 +210,10 @@ config PPC_MMU_NOHASH
def_bool y
depends on !PPC_STD_MMU
+config PPC_BOOK3E_MMU
+ def_bool y
+ depends on FSL_BOOKE
+
config PPC_MM_SLICES
bool
default y if HUGETLB_PAGE || (PPC_STD_MMU_64 && PPC_64K_PAGES)
--
1.5.6.6
^ permalink raw reply related
* [PATCH] powerpc/fsl-booke: Fix compile warning
From: Kumar Gala @ 2009-02-12 23:15 UTC (permalink / raw)
To: linuxppc-dev
arch/powerpc/mm/fsl_booke_mmu.c: In function 'adjust_total_lowmem':
arch/powerpc/mm/fsl_booke_mmu.c:221: warning: format '%ld' expects type 'long int', but argument 3 has type 'phys_addr_t'
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/mm/fsl_booke_mmu.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 6d38d77..985b6c3 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -218,7 +218,7 @@ adjust_total_lowmem(void)
p += sprintf(p, "0/");
p[-1] = '\0';
- pr_info("Memory CAM mapping: %s Mb, residual: %ldMb\n", buf,
- (total_lowmem - __max_low_memory) >> 20);
+ pr_info("Memory CAM mapping: %s Mb, residual: %dMb\n", buf,
+ (unsigned int)((total_lowmem - __max_low_memory) >> 20));
__initial_memory_limit_addr = memstart_addr + __max_low_memory;
}
--
1.5.6.6
^ permalink raw reply related
* [PATCH] powerpc: rework dma-noncoherent to use generic vmalloc layer (3rd rev)
From: Ilya Yanok @ 2009-02-12 23:20 UTC (permalink / raw)
To: linuxppc-dev; +Cc: wd, dzu, Ilya Yanok
In-Reply-To: <1234470155-6489-1-git-send-email-yanok@emcraft.com>
This patch rewrites consistent dma allocations support to use vmalloc
layer to allocate virtual memory space from vmalloc pool and get rid
of CONFIG_CONSISTENT_{START,SIZE}.
I still use VM_IOREMAP flag for these allocations (I'll try to post
patch adding separate VM_COHERENT_DMA flag to lkml later).
Now I save pages array in vm_struct pages field and use
__builtin_return_address(1) as 'caller' argument to get usefull info
in /proc/vmallocinfo:
-bash-3.2# cat /proc/vmallocinfo
0xe1000000-0xe1002000 8192 __ioremap+0x184/0x194 ioremap
[...]
0xe1f90000-0xe1f96000 24576 PrimeIocFifos+0x3a8/0x550 pages=5 ioremap
0xe1fa0000-0xe1fb1000 69632 __ioremap+0x184/0x194 ioremap
0xe1fc0000-0xe1fd1000 69632 __ioremap+0x184/0x194 ioremap
0xe2000000-0xe2f01000 15732736 __ioremap+0x184/0x194 ioremap
0xe2f32000-0xe2f34000 8192 __ioremap+0x184/0x194 ioremap
0xe2f38000-0xe2f3d000 20480 __ioremap+0x184/0x194 ioremap
0xe2f40000-0xe2f46000 24576 PrimeIocFifos+0x3a8/0x550 pages=5 ioremap
0xe2f80000-0xe3e81000 15732736 __ioremap+0x184/0x194 ioremap
0xe3f00000-0xe3f48000 294912 PrimeIocFifos+0x204/0x550 pages=71 ioremap
0xe3f80000-0xe3fc8000 294912 PrimeIocFifos+0x204/0x550 pages=71 ioremap
0xe3fe0000-0xe3fe6000 24576 bdx_fifo_init+0x8c/0x12c pages=5 ioremap
0xe3fe8000-0xe3fee000 24576 bdx_fifo_init+0x8c/0x12c pages=5 ioremap
0xe3fef000-0xe3ff8000 36864 bdx_open+0x10c/0x60c pages=8 vmalloc
0xe4000000-0xe4006000 24576 bdx_fifo_init+0x8c/0x12c pages=5 ioremap
0xe4007000-0xe400f000 32768 bdx_open+0x1f0/0x60c pages=7 vmalloc
0xe4010000-0xe401a000 40960 bdx_fifo_init+0x8c/0x12c pages=9 ioremap
(those ioremaps with pages=)
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
---
Previous version had a memory leak in error code path.
---
arch/powerpc/Kconfig | 25 ---
arch/powerpc/lib/dma-noncoherent.c | 303 +++++++-----------------------------
2 files changed, 57 insertions(+), 271 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 74cc312..ecae53f 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -815,31 +815,6 @@ config TASK_SIZE
default "0x80000000" if PPC_PREP || PPC_8xx
default "0xc0000000"
-config CONSISTENT_START_BOOL
- bool "Set custom consistent memory pool address"
- depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
- help
- This option allows you to set the base virtual address
- of the consistent memory pool. This pool of virtual
- memory is used to make consistent memory allocations.
-
-config CONSISTENT_START
- hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL
- default "0xfd000000" if (NOT_COHERENT_CACHE && 8xx)
- default "0xff100000" if NOT_COHERENT_CACHE
-
-config CONSISTENT_SIZE_BOOL
- bool "Set custom consistent memory pool size"
- depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE
- help
- This option allows you to set the size of the
- consistent memory pool. This pool of virtual memory
- is used to make consistent memory allocations.
-
-config CONSISTENT_SIZE
- hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL
- default "0x00200000" if NOT_COHERENT_CACHE
-
config PIN_TLB
bool "Pinned Kernel TLBs (860 ONLY)"
depends on ADVANCED_OPTIONS && 8xx
diff --git a/arch/powerpc/lib/dma-noncoherent.c b/arch/powerpc/lib/dma-noncoherent.c
index b7dc4c1..005a28d 100644
--- a/arch/powerpc/lib/dma-noncoherent.c
+++ b/arch/powerpc/lib/dma-noncoherent.c
@@ -29,121 +29,11 @@
#include <linux/types.h>
#include <linux/highmem.h>
#include <linux/dma-mapping.h>
+#include <linux/vmalloc.h>
#include <asm/tlbflush.h>
/*
- * This address range defaults to a value that is safe for all
- * platforms which currently set CONFIG_NOT_COHERENT_CACHE. It
- * can be further configured for specific applications under
- * the "Advanced Setup" menu. -Matt
- */
-#define CONSISTENT_BASE (CONFIG_CONSISTENT_START)
-#define CONSISTENT_END (CONFIG_CONSISTENT_START + CONFIG_CONSISTENT_SIZE)
-#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
-
-/*
- * This is the page table (2MB) covering uncached, DMA consistent allocations
- */
-static pte_t *consistent_pte;
-static DEFINE_SPINLOCK(consistent_lock);
-
-/*
- * VM region handling support.
- *
- * This should become something generic, handling VM region allocations for
- * vmalloc and similar (ioremap, module space, etc).
- *
- * I envisage vmalloc()'s supporting vm_struct becoming:
- *
- * struct vm_struct {
- * struct vm_region region;
- * unsigned long flags;
- * struct page **pages;
- * unsigned int nr_pages;
- * unsigned long phys_addr;
- * };
- *
- * get_vm_area() would then call vm_region_alloc with an appropriate
- * struct vm_region head (eg):
- *
- * struct vm_region vmalloc_head = {
- * .vm_list = LIST_HEAD_INIT(vmalloc_head.vm_list),
- * .vm_start = VMALLOC_START,
- * .vm_end = VMALLOC_END,
- * };
- *
- * However, vmalloc_head.vm_start is variable (typically, it is dependent on
- * the amount of RAM found at boot time.) I would imagine that get_vm_area()
- * would have to initialise this each time prior to calling vm_region_alloc().
- */
-struct ppc_vm_region {
- struct list_head vm_list;
- unsigned long vm_start;
- unsigned long vm_end;
-};
-
-static struct ppc_vm_region consistent_head = {
- .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
- .vm_start = CONSISTENT_BASE,
- .vm_end = CONSISTENT_END,
-};
-
-static struct ppc_vm_region *
-ppc_vm_region_alloc(struct ppc_vm_region *head, size_t size, gfp_t gfp)
-{
- unsigned long addr = head->vm_start, end = head->vm_end - size;
- unsigned long flags;
- struct ppc_vm_region *c, *new;
-
- new = kmalloc(sizeof(struct ppc_vm_region), gfp);
- if (!new)
- goto out;
-
- spin_lock_irqsave(&consistent_lock, flags);
-
- list_for_each_entry(c, &head->vm_list, vm_list) {
- if ((addr + size) < addr)
- goto nospc;
- if ((addr + size) <= c->vm_start)
- goto found;
- addr = c->vm_end;
- if (addr > end)
- goto nospc;
- }
-
- found:
- /*
- * Insert this entry _before_ the one we found.
- */
- list_add_tail(&new->vm_list, &c->vm_list);
- new->vm_start = addr;
- new->vm_end = addr + size;
-
- spin_unlock_irqrestore(&consistent_lock, flags);
- return new;
-
- nospc:
- spin_unlock_irqrestore(&consistent_lock, flags);
- kfree(new);
- out:
- return NULL;
-}
-
-static struct ppc_vm_region *ppc_vm_region_find(struct ppc_vm_region *head, unsigned long addr)
-{
- struct ppc_vm_region *c;
-
- list_for_each_entry(c, &head->vm_list, vm_list) {
- if (c->vm_start == addr)
- goto out;
- }
- c = NULL;
- out:
- return c;
-}
-
-/*
* Allocate DMA-coherent memory space and return both the kernel remapped
* virtual and bus address for that space.
*/
@@ -151,21 +41,21 @@ void *
__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp)
{
struct page *page;
- struct ppc_vm_region *c;
unsigned long order;
+ int i;
+ unsigned int nr_pages = PAGE_ALIGN(size)>>PAGE_SHIFT;
+ unsigned int array_size = nr_pages * sizeof(struct page *);
+ struct page **pages;
+ struct page *end;
u64 mask = 0x00ffffff, limit; /* ISA default */
+ struct vm_struct *area;
- if (!consistent_pte) {
- printk(KERN_ERR "%s: not initialised\n", __func__);
- dump_stack();
- return NULL;
- }
-
+ BUG_ON(!mem_init_done);
size = PAGE_ALIGN(size);
limit = (mask + 1) & ~mask;
- if ((limit && size >= limit) || size >= (CONSISTENT_END - CONSISTENT_BASE)) {
- printk(KERN_WARNING "coherent allocation too big (requested %#x mask %#Lx)\n",
- size, mask);
+ if (limit && size >= limit) {
+ printk(KERN_WARNING "coherent allocation too big (requested "
+ "%#x mask %#Lx)\n", size, mask);
return NULL;
}
@@ -178,6 +68,8 @@ __dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp)
if (!page)
goto no_page;
+ end = page + (1 << order);
+
/*
* Invalidate any data that might be lurking in the
* kernel direct-mapped region for device DMA.
@@ -188,48 +80,59 @@ __dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp)
flush_dcache_range(kaddr, kaddr + size);
}
+ split_page(page, order);
+
/*
- * Allocate a virtual address in the consistent mapping region.
+ * Set the "dma handle"
*/
- c = ppc_vm_region_alloc(&consistent_head, size,
- gfp & ~(__GFP_DMA | __GFP_HIGHMEM));
- if (c) {
- unsigned long vaddr = c->vm_start;
- pte_t *pte = consistent_pte + CONSISTENT_OFFSET(vaddr);
- struct page *end = page + (1 << order);
-
- split_page(page, order);
-
- /*
- * Set the "dma handle"
- */
- *handle = page_to_phys(page);
+ *handle = page_to_phys(page);
+
+ area = get_vm_area_caller(size, VM_IOREMAP,
+ __builtin_return_address(1));
+ if (!area)
+ goto out_free_pages;
+
+ if (array_size > PAGE_SIZE) {
+ pages = vmalloc(array_size);
+ area->flags |= VM_VPAGES;
+ } else {
+ pages = kmalloc(array_size, GFP_KERNEL);
+ }
+ if (!pages)
+ goto out_free_area;
- do {
- BUG_ON(!pte_none(*pte));
+ area->pages = pages;
+ area->nr_pages = nr_pages;
- SetPageReserved(page);
- set_pte_at(&init_mm, vaddr,
- pte, mk_pte(page, pgprot_noncached(PAGE_KERNEL)));
- page++;
- pte++;
- vaddr += PAGE_SIZE;
- } while (size -= PAGE_SIZE);
+ for (i = 0; i < nr_pages; i++)
+ pages[i] = page + i;
- /*
- * Free the otherwise unused pages.
- */
- while (page < end) {
- __free_page(page);
- page++;
- }
+ if (map_vm_area(area, pgprot_noncached(PAGE_KERNEL), &pages))
+ goto out_unmap;
- return (void *)c->vm_start;
+ /*
+ * Free the otherwise unused pages.
+ */
+ page += nr_pages;
+ while (page < end) {
+ __free_page(page);
+ page++;
}
+ return area->addr;
+out_unmap:
+ vunmap(area->addr);
+ if (array_size > PAGE_SIZE)
+ vfree(pages);
+ else
+ kfree(pages);
+ goto out_free_pages;
+out_free_area:
+ free_vm_area(area);
+out_free_pages:
if (page)
__free_pages(page, order);
- no_page:
+no_page:
return NULL;
}
EXPORT_SYMBOL(__dma_alloc_coherent);
@@ -239,104 +142,12 @@ EXPORT_SYMBOL(__dma_alloc_coherent);
*/
void __dma_free_coherent(size_t size, void *vaddr)
{
- struct ppc_vm_region *c;
- unsigned long flags, addr;
- pte_t *ptep;
-
- size = PAGE_ALIGN(size);
-
- spin_lock_irqsave(&consistent_lock, flags);
-
- c = ppc_vm_region_find(&consistent_head, (unsigned long)vaddr);
- if (!c)
- goto no_area;
-
- if ((c->vm_end - c->vm_start) != size) {
- printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
- __func__, c->vm_end - c->vm_start, size);
- dump_stack();
- size = c->vm_end - c->vm_start;
- }
-
- ptep = consistent_pte + CONSISTENT_OFFSET(c->vm_start);
- addr = c->vm_start;
- do {
- pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
- unsigned long pfn;
-
- ptep++;
- addr += PAGE_SIZE;
+ vfree(vaddr);
- if (!pte_none(pte) && pte_present(pte)) {
- pfn = pte_pfn(pte);
-
- if (pfn_valid(pfn)) {
- struct page *page = pfn_to_page(pfn);
- ClearPageReserved(page);
-
- __free_page(page);
- continue;
- }
- }
-
- printk(KERN_CRIT "%s: bad page in kernel page table\n",
- __func__);
- } while (size -= PAGE_SIZE);
-
- flush_tlb_kernel_range(c->vm_start, c->vm_end);
-
- list_del(&c->vm_list);
-
- spin_unlock_irqrestore(&consistent_lock, flags);
-
- kfree(c);
- return;
-
- no_area:
- spin_unlock_irqrestore(&consistent_lock, flags);
- printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n",
- __func__, vaddr);
- dump_stack();
}
EXPORT_SYMBOL(__dma_free_coherent);
/*
- * Initialise the consistent memory allocation.
- */
-static int __init dma_alloc_init(void)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- pte_t *pte;
- int ret = 0;
-
- do {
- pgd = pgd_offset(&init_mm, CONSISTENT_BASE);
- pud = pud_alloc(&init_mm, pgd, CONSISTENT_BASE);
- pmd = pmd_alloc(&init_mm, pud, CONSISTENT_BASE);
- if (!pmd) {
- printk(KERN_ERR "%s: no pmd tables\n", __func__);
- ret = -ENOMEM;
- break;
- }
-
- pte = pte_alloc_kernel(pmd, CONSISTENT_BASE);
- if (!pte) {
- printk(KERN_ERR "%s: no pte tables\n", __func__);
- ret = -ENOMEM;
- break;
- }
-
- consistent_pte = pte;
- } while (0);
-
- return ret;
-}
-
-core_initcall(dma_alloc_init);
-
-/*
* make an area consistent.
*/
void __dma_sync(void *vaddr, size_t size, int direction)
--
1.6.0.6
^ permalink raw reply related
* Re: [PATCH 0/7][RFC] function graph tracer port to PowerPC
From: Geoff Levand @ 2009-02-12 23:32 UTC (permalink / raw)
To: Steven Rostedt
Cc: Frederic Weisbecker, linux-kernel, linuxppc-dev, Paul Mackerras,
Ingo Molnar, Andrew Morton
In-Reply-To: <20090212011051.265346435@goodmis.org>
On 02/11/2009 05:10 PM, Steven Rostedt wrote:
> This is the port to PowerPC of the function graph tracer that was written
> by Frederic Weisbecker for the x86 architecture. It is broken up
> into a series of logical steps.
I added these to my ps3-linux.git tree. Very casual testing shows
they seem to work OK.
Tested-by: Geoff Levand <geoffrey.levand@am.sony.com> Working OK on PS3.
^ permalink raw reply
* Re: [PATCH v2] powerpc/fsl-booke: Add new ISA 2.06 page sizes and MAS defines
From: Josh Boyer @ 2009-02-12 23:35 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list
In-Reply-To: <54A20554-3C7B-4EE7-B3CF-362AEB27CA64@kernel.crashing.org>
On Thu, Feb 12, 2009 at 03:58:15PM -0600, Kumar Gala wrote:
>
> On Feb 12, 2009, at 2:34 PM, Josh Boyer wrote:
>
>> On Thu, Feb 12, 2009 at 01:21:24PM -0600, Kumar Gala wrote:
>>>
>>> On Feb 10, 2009, at 6:26 PM, Kumar Gala wrote:
>>>
>>>> The Power ISA 2.06 added power of two page sizes to the embedded MMU
>>>> architecture. Its done it such a way to be code compatiable with
>>>> the
>>>> existing HW. Made the minor code changes to support both power of
>>>> two
>>>> and power of four page sizes. Also added some new MAS bits and
>>>> macros
>>>> that are defined as part of the 2.06 ISA.
>>>>
>>>> Note, its still invalid to try and use a page size that isn't
>>>> supported
>>>> by cpu.
>>>>
>>>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>>>> ---
>>>> * Fixed MAS6_ISIZE macro
>>>>
>>>> arch/powerpc/include/asm/mmu-fsl-booke.h | 54 +++++++++++++++++++
>>>> +----------
>>>
>>> Do you want to rename asm/mmu-fsl-booke.h => mmu-booke.h (per ISA
>>> 2.06
>>> changes)?
>>
>> Misleading perhaps. ISA 2.06 is really new and we've been calling 4xx
>> and FSL booke for a while now.
>
> I can call it mmu-book3e.h if you think that might enough different to
> convey the ISA 2.06 fact that the FSL style MMU is now part of the 3e
> architecture.
Yep, sounds great. "What's in a name..", right? :)
josh
^ permalink raw reply
* Re: [PATCH 0/7][RFC] function graph tracer port to PowerPC
From: Steven Rostedt @ 2009-02-12 23:41 UTC (permalink / raw)
To: Geoff Levand
Cc: Frederic Weisbecker, linux-kernel, linuxppc-dev, Paul Mackerras,
Ingo Molnar, Andrew Morton
In-Reply-To: <4994B1A3.8080502@am.sony.com>
On Thu, 12 Feb 2009, Geoff Levand wrote:
> On 02/11/2009 05:10 PM, Steven Rostedt wrote:
> > This is the port to PowerPC of the function graph tracer that was written
> > by Frederic Weisbecker for the x86 architecture. It is broken up
> > into a series of logical steps.
>
> I added these to my ps3-linux.git tree. Very casual testing shows
> they seem to work OK.
>
>
> Tested-by: Geoff Levand <geoffrey.levand@am.sony.com> Working OK on PS3.
Thanks!
Is the ps3 64 or 32 bit? I'll put your tested by on the appropriate
patches.
-- Steve
^ permalink raw reply
* Re: [PATCH 0/7][RFC] function graph tracer port to PowerPC
From: Josh Boyer @ 2009-02-12 23:44 UTC (permalink / raw)
To: Steven Rostedt
Cc: Frederic Weisbecker, linux-kernel, linuxppc-dev, Paul Mackerras,
Ingo Molnar, Andrew Morton
In-Reply-To: <alpine.DEB.1.10.0902121840590.15469@gandalf.stny.rr.com>
On Thu, Feb 12, 2009 at 06:41:26PM -0500, Steven Rostedt wrote:
>
>On Thu, 12 Feb 2009, Geoff Levand wrote:
>
>> On 02/11/2009 05:10 PM, Steven Rostedt wrote:
>> > This is the port to PowerPC of the function graph tracer that was written
>> > by Frederic Weisbecker for the x86 architecture. It is broken up
>> > into a series of logical steps.
>>
>> I added these to my ps3-linux.git tree. Very casual testing shows
>> they seem to work OK.
>>
>>
>> Tested-by: Geoff Levand <geoffrey.levand@am.sony.com> Working OK on PS3.
>
>Thanks!
>
>Is the ps3 64 or 32 bit? I'll put your tested by on the appropriate
>patches.
64-bit.
josh
^ permalink raw reply
* Re: [PATCH 0/7][RFC] function graph tracer port to PowerPC
From: Geoff Levand @ 2009-02-12 23:44 UTC (permalink / raw)
To: Steven Rostedt
Cc: Frederic Weisbecker, linux-kernel, linuxppc-dev, Paul Mackerras,
Ingo Molnar, Andrew Morton
In-Reply-To: <alpine.DEB.1.10.0902121840590.15469@gandalf.stny.rr.com>
On 02/12/2009 03:41 PM, Steven Rostedt wrote:
> On Thu, 12 Feb 2009, Geoff Levand wrote:
>
>> On 02/11/2009 05:10 PM, Steven Rostedt wrote:
>> > This is the port to PowerPC of the function graph tracer that was written
>> > by Frederic Weisbecker for the x86 architecture. It is broken up
>> > into a series of logical steps.
>>
>> I added these to my ps3-linux.git tree. Very casual testing shows
>> they seem to work OK.
>>
>>
>> Tested-by: Geoff Levand <geoffrey.levand@am.sony.com> Working OK on PS3.
>
> Thanks!
>
> Is the ps3 64 or 32 bit? I'll put your tested by on the appropriate
> patches.
It uses the Cell processor, which is 64 bit.
-Geoff
^ permalink raw reply
* Re: [PATCH 0/7][RFC] function graph tracer port to PowerPC
From: Steven Rostedt @ 2009-02-12 23:51 UTC (permalink / raw)
To: Geoff Levand
Cc: Frederic Weisbecker, linux-kernel, linuxppc-dev, Paul Mackerras,
Ingo Molnar, Andrew Morton
In-Reply-To: <4994B466.5050102@am.sony.com>
On Thu, 12 Feb 2009, Geoff Levand wrote:
> On 02/12/2009 03:41 PM, Steven Rostedt wrote:
> > On Thu, 12 Feb 2009, Geoff Levand wrote:
> >
> >> On 02/11/2009 05:10 PM, Steven Rostedt wrote:
> >> > This is the port to PowerPC of the function graph tracer that was written
> >> > by Frederic Weisbecker for the x86 architecture. It is broken up
> >> > into a series of logical steps.
> >>
> >> I added these to my ps3-linux.git tree. Very casual testing shows
> >> they seem to work OK.
> >>
> >>
> >> Tested-by: Geoff Levand <geoffrey.levand@am.sony.com> Working OK on PS3.
> >
> > Thanks!
> >
> > Is the ps3 64 or 32 bit? I'll put your tested by on the appropriate
> > patches.
>
> It uses the Cell processor, which is 64 bit.
Thanks guys!
-- Steve
^ permalink raw reply
* Re: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards
From: Kumar Gala @ 2009-02-12 23:51 UTC (permalink / raw)
To: Anton Vorontsov; +Cc: linuxppc-dev list
In-Reply-To: <3A45394FD742FA419B760BB8D398F9ED1D2D8B@zch01exm26.fsl.freescale.net>
On Feb 11, 2009, at 11:40 PM, Li Yang-R58472 wrote:
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Thursday, February 12, 2009 1:25 PM
>> To: Li Yang-R58472
>> Cc: linuxppc-dev list; Anton Vorontsov
>> Subject: Re: [PATCH] powerpc/83xx: Revive Marvell PHY option
>> on MPC8313E-RDB rev. C boards
>>
>>
>> On Feb 10, 2009, at 9:10 AM, Anton Vorontsov wrote:
>>
>>>
>>> Li, thanks for heads-up!
>>>
>>> One thing though: documentation says that Marvell PHY
>> address is 0x3,
>>> while old device tree and this patch:
>>>
>>>
>> http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add-
>> default-
>>> dts.patch
>>>
>>> says "0x1"... I don't have any rev. C boards, so it would
>> be great if
>>> somebody could confirm that 0x1 is the actual address.
>
> The correct address is 0x3. The previous patch in revB BSP used a
> guess
> value before the revC documentation is available. The latest BSP has
> been updated to use the correct address.
Anton, will you spin a new patch with this change?
- k
^ permalink raw reply
* [PATCH] powerpc: Add support for using doorbells for SMP IPI
From: Kumar Gala @ 2009-02-12 23:54 UTC (permalink / raw)
To: linuxppc-dev
The e500mc supports the new msgsnd/doorbell mechanisms that were added in
the Power ISA 2.05 architecture. We use the normal level doorbell for
doing SMP IPIs at this point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/include/asm/cputable.h | 4 ++-
arch/powerpc/include/asm/dbell.h | 43 +++++++++++++++++++++++++++++++++
arch/powerpc/kernel/Makefile | 2 +-
arch/powerpc/kernel/dbell.c | 44 ++++++++++++++++++++++++++++++++++
arch/powerpc/kernel/head_fsl_booke.S | 6 ++++-
arch/powerpc/kernel/traps.c | 21 ++++++++++++++++
6 files changed, 117 insertions(+), 3 deletions(-)
create mode 100644 arch/powerpc/include/asm/dbell.h
create mode 100644 arch/powerpc/kernel/dbell.c
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 4911104..fca1611 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -145,6 +145,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
+#define CPU_FTR_DBELL ASM_CONST(0x0000000000000200)
#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
@@ -373,7 +374,8 @@ extern const char *powerpc_base_platform;
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
- CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE)
+ CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
+ CPU_FTR_DBELL)
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
/* 64-bit CPUs */
diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h
new file mode 100644
index 0000000..501189a
--- /dev/null
+++ b/arch/powerpc/include/asm/dbell.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2009 Freescale Semicondutor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * provides masks and opcode images for use by code generation, emulation
+ * and for instructions that older assemblers might not know about
+ */
+#ifndef _ASM_POWERPC_DBELL_H
+#define _ASM_POWERPC_DBELL_H
+
+#include <linux/smp.h>
+#include <linux/threads.h>
+
+#include <asm/ppc-opcode.h>
+
+#define PPC_DBELL_MSG_BRDCAST (0x04000000)
+#define PPC_DBELL_TYPE(x) (((x) & 0xf) << 28)
+enum ppc_dbell {
+ PPC_DBELL = 0, /* doorbell */
+ PPC_DBELL_CRIT = 1, /* critical doorbell */
+ PPC_G_DBELL = 2, /* guest doorbell */
+ PPC_G_DBELL_CRIT = 3, /* guest critical doorbell */
+ PPC_G_DBELL_MC = 4, /* guest mcheck doorbell */
+};
+
+#ifdef CONFIG_SMP
+extern unsigned long dbell_smp_message[NR_CPUS];
+extern void smp_dbell_message_pass(int target, int msg);
+#endif
+
+static inline void ppc_msgsnd(enum ppc_dbell type, u32 flags, u32 tag)
+{
+ u32 msg = PPC_DBELL_TYPE(type) | (flags & PPC_DBELL_MSG_BRDCAST) |
+ (tag & 0x07ffffff);
+
+ __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
+}
+
+#endif /* _ASM_POWERPC_DBELL_H */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index d159921..f420844 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -61,7 +61,7 @@ obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \
obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o
obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
obj-$(CONFIG_44x) += cpu_setup_44x.o
-obj-$(CONFIG_FSL_BOOKE) += cpu_setup_fsl_booke.o
+obj-$(CONFIG_FSL_BOOKE) += cpu_setup_fsl_booke.o dbell.o
extra-$(CONFIG_PPC_STD_MMU) := head_32.o
extra-$(CONFIG_PPC64) := head_64.o
diff --git a/arch/powerpc/kernel/dbell.c b/arch/powerpc/kernel/dbell.c
new file mode 100644
index 0000000..1493734
--- /dev/null
+++ b/arch/powerpc/kernel/dbell.c
@@ -0,0 +1,44 @@
+/*
+ * Author: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/smp.h>
+#include <linux/threads.h>
+
+#include <asm/dbell.h>
+
+#ifdef CONFIG_SMP
+unsigned long dbell_smp_message[NR_CPUS];
+
+void smp_dbell_message_pass(int target, int msg)
+{
+ int i;
+
+ if(target < NR_CPUS) {
+ set_bit(msg, &dbell_smp_message[target]);
+ ppc_msgsnd(PPC_DBELL, 0, target);
+ }
+ else if(target == MSG_ALL_BUT_SELF) {
+ for_each_online_cpu(i) {
+ if (i == smp_processor_id())
+ continue;
+ set_bit(msg, &dbell_smp_message[i]);
+ ppc_msgsnd(PPC_DBELL, 0, i);
+ }
+ }
+ else { /* target == MSG_ALL */
+ for_each_online_cpu(i)
+ set_bit(msg, &dbell_smp_message[i]);
+ ppc_msgsnd(PPC_DBELL, PPC_DBELL_MSG_BRDCAST, 0);
+ }
+}
+#endif
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 4ea6e1a..4c22620 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -698,7 +698,9 @@ interrupt_base:
/* Performance Monitor */
EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
- EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_STD)
+ EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
+
+ CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
/* Debug Interrupt */
DEBUG_DEBUG_EXCEPTION
@@ -921,6 +923,8 @@ _GLOBAL(__setup_e500mc_ivors)
mtspr SPRN_IVOR35,r3
li r3,Doorbell@l
mtspr SPRN_IVOR36,r3
+ li r3,CriticalDoorbell@l
+ mtspr SPRN_IVOR37,r3
sync
blr
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 970d66e..678fbff 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -53,6 +53,9 @@
#endif
#include <asm/kexec.h>
#include <asm/ppc-opcode.h>
+#ifdef CONFIG_FSL_BOOKE
+#include <asm/dbell.h>
+#endif
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
int (*__debugger)(struct pt_regs *regs);
@@ -1122,6 +1125,24 @@ void vsx_assist_exception(struct pt_regs *regs)
#endif /* CONFIG_VSX */
#ifdef CONFIG_FSL_BOOKE
+
+void doorbell_exception(struct pt_regs *regs)
+{
+#ifdef CONFIG_SMP
+ int cpu = smp_processor_id();
+ int msg;
+
+ if (num_online_cpus() < 2)
+ return;
+
+ for (msg = 0; msg < 4; msg++)
+ if (test_and_clear_bit(msg, &dbell_smp_message[cpu]))
+ smp_message_recv(msg);
+#else
+ printk(KERN_WARNING "Received doorbell on non-smp system\n");
+#endif
+}
+
void CacheLockingException(struct pt_regs *regs, unsigned long address,
unsigned long error_code)
{
--
1.5.6.6
^ permalink raw reply related
* Re: [PATCH] powerpc/83xx: Revive Marvell PHY option on MPC8313E-RDB rev. C boards
From: Anton Vorontsov @ 2009-02-13 1:18 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list
In-Reply-To: <F0245D03-4191-4482-B007-603C3DAC8A1A@kernel.crashing.org>
On Thu, Feb 12, 2009 at 05:51:57PM -0600, Kumar Gala wrote:
> On Feb 11, 2009, at 11:40 PM, Li Yang-R58472 wrote:
>>>> Li, thanks for heads-up!
>>>>
>>>> One thing though: documentation says that Marvell PHY
>>> address is 0x3,
>>>> while old device tree and this patch:
>>>>
>>>>
>>> http://www.bitshrine.org/gpp/linux-fsl-2.6.23-MPC8313ERDB-add-
>>> default-
>>>> dts.patch
>>>>
>>>> says "0x1"... I don't have any rev. C boards, so it would
>>> be great if
>>>> somebody could confirm that 0x1 is the actual address.
>>
>> The correct address is 0x3. The previous patch in revB BSP used a
>> guess
>> value before the revC documentation is available. The latest BSP has
>> been updated to use the correct address.
>
> Anton, will you spin a new patch with this change?
Since the correct address is 0x3, that means that the old device
tree never worked on rev. C boards, thus there is no regression.
And furthermore, it appears that U-Boot doesn't support Marvell
PHY option either.
So, I don't think that adding the new device tree makes any sense
now.
I think the better option would be to implement Marvell PHY support
in U-Boot, and at the same time teach U-Boot to fixup 8313rdb's
device tree depending on the environment variable (something like
setenv marvell_phy_option yes/no), i.e. like I did for
MPC8315E-RDB's ULPI/TSEC1 options:
http://lists.denx.de/pipermail/u-boot/2008-July/036553.html
Makes sense? If not, I'll readily respin this patch with the PHY
address change.
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
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