* Re: PWM class? (was: Re: MPC52xx simple GPIO support)
From: Grant Likely @ 2009-06-11 22:00 UTC (permalink / raw)
To: avorontsov; +Cc: ppc-dev, linux-kernel, Stefan Strobl
In-Reply-To: <20090603132217.GA18353@oksana.dev.rtsoft.ru>
On Wed, Jun 3, 2009 at 7:22 AM, Anton Vorontsov<avorontsov@ru.mvista.com> w=
rote:
> On Wed, Jun 03, 2009 at 02:42:26PM +0200, Stefan Strobl wrote:
> [...]
>> The led class provides support for setting the brightness, which
>> obviously the gpio driver doesn't support. The hardware (mpc52xx_gpt)
>> would support it in PWM mode though. I'm now wandering how this could be
>> best implemented.
>>
>> 1) - Create some PWM class similar to the GPIO class
>> =A0 =A0- Add support for PWM mode in mpc52xx_gpt.c that uses that PWM cl=
ass
>> =A0 =A0- And add an interface for the LED to use the PWM class
>>
>> 2) - Create an LED driver that accesses the mpc52xx_gpt directly.
>>
>> I think I would be overwhelmed trying to implement (1) but am confident
>> to do (2). What do you think is the right approach?
>
> I'd suggest creating a generic PWM class, i.e. PWMLIB, alike to
> GPIOLIB. (2) can be an acceptable approach for now, but for the
> long-term solution (1) is the way to go.
>
> The non-lib PWM API is already there, see include/linux/pwm.h,
> and arch/arm/mach-pxa/pwm.c as an implementation example.
>
> Note that PXA implementation is SOC-specific, which is not very
> good.
>
> So I'd suggest creating drivers/pwm/pwmlib.c, borrowing
> ideas from gpiolib. And then we can reuse drivers/leds/leds-pwm.c
> driver (of course, after adding appropriate OF code into it).
Ugh. The referenced pwm api is about as trivial as it gets; it is an
anonymous context pointer (anonymous struct pwm_device *) with a set
of accessor functions. PWMs are also not nearly as common as GPIO
pins, and I am not interested in gpiolib being duplicated for PWMs, at
least not until there are more that just two examples of use to draw
from.
If anything, I'd rather struct pwm_device be non-anonymous and contain
a set of ops which call directly into the driver. That way is at
least multiplatform friendly. I don't think the gpio API is the
example to follow here. But even then I think it is premature to try
and define a PWM api. Personally, I'd modify mpc52xx_gpt to export
its own PWM interface for the time being using the existing GPIO
infrastructure to find the appropriate pin.
If you do decide to do a generic PWM api, then I think the way to go
is to build it as an extension to gpiolib.
Cheers,
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: System clock systems to be twice as fast as RTC
From: Grant Likely @ 2009-06-11 21:41 UTC (permalink / raw)
To: Subodh Nijsure; +Cc: linuxppc-dev
In-Reply-To: <008701c9eaa7$3c8336c0$8dde520a@cisco.com>
On Thu, Jun 11, 2009 at 9:13 AM, Subodh Nijsure<sunijsur@cisco.com> wrote:
>
>
> I am running system with kernel 2.6.10 with following cpuinfo
Wow, that's an old kernel version. 2.6.10 was released in 2004. Can
you move up to something more recent?
g.
> sh-2.05b# cat /proc/cpuinfo
> processor =A0 =A0 =A0 : 0
> cpu =A0 =A0 =A0 =A0 =A0 =A0 : 440 in Virtex-5 FXT
> clock =A0 =A0 =A0 =A0 =A0 : 200MHz
> revision =A0 =A0 =A0 =A0: 25.18 (pvr 7ff2 1912)
> bogomips =A0 =A0 =A0 =A0: 296.96
> machine =A0 =A0 =A0 =A0 : Xilinx ML507 PPC440 evaluation board
> plb bus clock =A0 : 100MHz
>
> The system clock seems to be running twice as as fast as RTC,
>
> sh-2.05b# date ; sleep 60 ; date
> Fri Sep 11 01:37:11 UTC 1970
> Fri Sep 11 01:37:41 UTC 1970
> sh-2.05b# date ; sleep 60 ; date
> Fri Sep 11 01:38:21 UTC 1970
> Fri Sep 11 01:38:51 UTC 1970
> sh-2.05b# date ; sleep 60 ; date
> Fri Sep 11 01:38:59 UTC 1970
> Fri Sep 11 01:39:29 UTC 1970
>
> I have tried various values of CONFIG_HZ and that didn't help. Google
> searches has shown up this issue on X86 system but not on PPC. Any hints =
as
> to what I should be looking for? I have included relevant portion of conf=
ig
> file..
>
>
> /Subodh
>
>
>
> CONFIG_MMU=3Dy
> CONFIG_GENERIC_HARDIRQS=3Dy
> CONFIG_RWSEM_GENERIC_SPINLOCK=3Dy
> CONFIG_ASM_SEMAPHORES=3Dy
> CONFIG_HAVE_DEC_LOCK=3Dy
> CONFIG_PPC=3Dy
> CONFIG_PPC32=3Dy
> CONFIG_GENERIC_NVRAM=3Dy
> CONFIG_EXPERIMENTAL=3Dy
> CONFIG_CLEAN_COMPILE=3Dy
> CONFIG_BROKEN_ON_SMP=3Dy
> CONFIG_LOCK_KERNEL=3Dy
> CONFIG_LOCALVERSION=3D""
> CONFIG_SWAP=3Dy
> CONFIG_SYSVIPC=3Dy
> CONFIG_SYSVIPC_SEMMNI=3D128
> CONFIG_SYSVIPC_SEMMSL=3D250
> CONFIG_POSIX_MQUEUE=3Dy
> CONFIG_SYSCTL=3Dy
> CONFIG_LOG_BUF_SHIFT=3D14
> CONFIG_HOTPLUG=3Dy
> CONFIG_KOBJECT_UEVENT=3Dy
> CONFIG_IKCONFIG=3Dy
> CONFIG_IKCONFIG_PROC=3Dy
> CONFIG_KALLSYMS=3Dy
> CONFIG_FUTEX=3Dy
> CONFIG_EPOLL=3Dy
> CONFIG_SHMEM=3Dy
> CONFIG_CC_ALIGN_FUNCTIONS=3D0
> CONFIG_CC_ALIGN_LABELS=3D0
> CONFIG_CC_ALIGN_LOOPS=3D0
> CONFIG_CC_ALIGN_JUMPS=3D0
> CONFIG_LTT_MAX_HANDLES=3D128
> CONFIG_LOCKLESS=3Dy
> CONFIG_BOOT_FLIGHT_BUFFERS=3D4
> CONFIG_BOOT_FLIGHT_SIZE=3D524288
> CONFIG_FLIGHT_PROC_BUFFERS=3D8
> CONFIG_FLIGHT_PROC_SIZE=3D8192
> CONFIG_NEWEV=3Dy
> CONFIG_CSTM=3Dy
> CONFIG_CREATE_DEV_CONSOLE=3Dy
> CONFIG_MODULES=3Dy
> CONFIG_MODULE_UNLOAD=3Dy
> CONFIG_MODULE_FORCE_UNLOAD=3Dy
> CONFIG_OBSOLETE_MODPARM=3Dy
> CONFIG_KMOD=3Dy
> CONFIG_44x=3Dy
> CONFIG_BOOKE=3Dy
> CONFIG_PTE_64BIT=3Dy
> CONFIG_PHYS_64BIT=3Dy
> CONFIG_MATH_EMULATION=3Dy
> CONFIG_4xx=3Dy
> CONFIG_XILINX_ML507=3Dy
> CONFIG_XILINX_OCP=3Dy
> CONFIG_XILINX_VIRTEX_5_FX=3Dy
> CONFIG_XILINX_VIRTEX=3Dy
> CONFIG_EMBEDDEDBOOT=3Dy
> CONFIG_PPC_GEN550=3Dy
> CONFIG_UART0_TTYS0=3Dy
> CONFIG_NOT_COHERENT_CACHE=3Dy
> CONFIG_PREEMPT_DESKTOP=3Dy
> CONFIG_PREEMPT=3Dy
> CONFIG_PREEMPT_BKL=3Dy
> CONFIG_HIGH_RES_TIMERS=3Dy
> CONFIG_BINFMT_ELF=3Dy
> CONFIG_CMDLINE_BOOL=3Dy
> CONFIG_CMDLINE=3D"console=3DttyS0,9600n8 initrd=3D0x1800000,32M rw root=
=3D/dev/ram
> ip=3D$(ipaddr)::(gatewayip):$(subnetmask)::eth0:none eth=3D$(ethaddr)"
> <snip>
>
>
>
>
>
>
>
>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: SD card over (xilinx_)SPI, timeout error while CID
From: Ricardo Ribalda Delgado @ 2009-06-11 21:16 UTC (permalink / raw)
To: Wolfgang Denk
Cc: jan.nikitenko, Lorenz Kolb, dbrownell, Joachim Foerster, hp,
linuxppc-dev, mike, pierre, joachim, john.linn, linuxkernel
In-Reply-To: <20090611210751.A7130832E416@gemini.denx.de>
Hello Wolfgang
>
> This is with a 4xx core, right? Is this the same SPI controller design
> like in AMCC's 40x and 44x cores, i. e. with a "FIFO" of depth 1?
It is a ppc440 but it is does not have ans spi controller as in the
amcc. The spi controller is a xilinx core allocated at the plb bus,
including a deeper fifo.
The actual version does not have a sustained speed of 33Mhz but a can
have a peak speed of 33 MHz
Thanks for your comment
--
Ricardo Ribalda
http://www.eps.uam.es/~rribalda/
^ permalink raw reply
* Re: SD card over (xilinx_)SPI, timeout error while CID
From: Wolfgang Denk @ 2009-06-11 21:07 UTC (permalink / raw)
To: Ricardo Ribalda Delgado
Cc: jan.nikitenko, Lorenz Kolb, dbrownell, Joachim Foerster, hp,
linuxppc-dev, mike, pierre, joachim, john.linn, linuxkernel
In-Reply-To: <aa76a2be0906111349s2ff947eo35149ef14e29d05a@mail.gmail.com>
Dear Ricardo Ribalda Delgado,
In message <aa76a2be0906111349s2ff947eo35149ef14e29d05a@mail.gmail.com> you wrote:
>
> > What frequency does Your SPI-Bus use?
>
> 33Mhz.... arghh. just checked is over the standard... Tomorrow I will
> test with a slower clk
Just some really stupid questions:
This is with a 4xx core, right? Is this the same SPI controller design
like in AMCC's 40x and 44x cores, i. e. with a "FIFO" of depth 1?
Assuming you're running your SPI clock at 1 MHz, you get one data
byte and thus one interrupt at a rate of 125 kHz. I doubt your CPU
can handle such a load?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
A witty saying proves nothing, but saying something pointless gets
people's attention.
^ permalink raw reply
* Re: SD card over (xilinx_)SPI, timeout error while CID
From: Ricardo Ribalda Delgado @ 2009-06-11 20:49 UTC (permalink / raw)
To: Lorenz Kolb
Cc: joachim, dbrownell, Joachim Foerster, hp, linuxppc-dev, mike,
pierre, jan.nikitenko, john.linn, linuxkernel
In-Reply-To: <4A316386.4020404@missinglinkelectronics.com>
Hello
Thanks for your reply
> Is the I/O logged from within the Xilinx-SPI-Driver or from within the
> mmc-spi-layer?
It is take from inside the spi driver.
>
> The response to CMD10 seems quite strange to me. The R1 answer to that
> command says that everything is OK, so what is done next is that the 0xfe
> token will be expected by the mmc-spi-layer. Obviously that one is not
> received within the proper time (assuming your data-logging was done from
> within xilinx-spi-driver). Also be aware of printk() taking milliseconds =
for
> printing to console, within time critical routines that might not be the
> best choice for debugging.
I will retry tomorrow removing all the spi debug and report what happens.
>
> What frequency does Your SPI-Bus use?
>
33Mhz.... arghh. just checked is over the standard... Tomorrow I will
test with a slower clk
>
> Also double check to completely disable the whole
>
> =A0if (spi->master->dev.parent->dma_mask) {
> =A0 =A0...
> =A0}
>
Tomorow morning i will double check it, but it was something we
removed from the very begining (we dont have dma for the spi and we
suppose it was an error) In my last log check:
[ 48.990098] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no
poweroff, cd polling
Anyway the problem is definitely here:
[ 52.094569] mmc0: starting CMD10 arg 00000000 flags 000000b5
[ 52.113755] mmc0: blksz 16 blocks 1 flags 00000200 tsac 0 ms nsac 64
[ 52.134240] mmc_spi spi1.0: mmc_spi: CMD10, resp R1
[ 52.152922] Xilinx SPI: cs on
[ 52.169228] Spi Transfer at 0x8A000000
[ 52.186386] Sending 9 bytes
[ 52.187978] ff 4a 00 00 00 00 1b ff ff
[ 52.218225] Received 9 bytes
[ 52.219911] ff ff ff ff ff ff ff ff 00
[ 52.249970] mmc_spi spi1.0: mmc_spi: read block, 16 bytes
[ 52.269009] Xilinx SPI: cs on
[ 52.285210] Spi Transfer at 0x8A000000
[ 52.302276] Sending 1 bytes
[ 52.303867] ff
[ 52.332598] Received 1 bytes
[ 52.334287] ff
[ 52.362345] Xilinx SPI: cs on
[ 52.377675] Spi Transfer at 0x8A000000
[ 52.393815] Sending 1 bytes
[ 52.395408] ff
[ 52.422215] Received 1 bytes
[ 52.423901] ff
It tries to read the cid and the only thing it get from the sd back
are 0xff. I have made it loop without timeout and I keep receiving
0xff
Also after the cid read the sd card dont reply to any command....
weird. lets see tomorrow with a slower clk.
Thanks for your commends
Best regards
--=20
Ricardo Ribalda
http://www.eps.uam.es/~rribalda/
^ permalink raw reply
* [PATCH] mpc5xxx_get_bus_frequency(): use common code on MPC512x and MPC52xx
From: Wolfgang Denk @ 2009-06-11 20:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Wolfgang Denk
In-Reply-To: <fa686aa40906080737h64bad3cfv32155e5b819d650b@mail.gmail.com>
So far, MPC512x used mpc512x_find_ips_freq() to get the bus frequency,
while MPC52xx used mpc52xx_find_ipb_freq(). Despite the different
clock names (IPS vs. IPB) the code was identical.
Use common code for both processor families.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Kumar Gala <galak@kernel.crashing.org>
---
This patch is not only intended to avoid code duplication, but it
will be needed in a following patch that fixes a MII speed
miscalculation in drivers/net/fs_enet/mii-fec.c - this patch allows
for a clean solution that works both on MPC512x and MPC52x systems.
arch/powerpc/include/asm/mpc512x.h | 22 -----------------
arch/powerpc/include/asm/mpc52xx.h | 2 +-
arch/powerpc/include/asm/mpc5xxx.h | 22 +++++++++++++++++
arch/powerpc/platforms/512x/clock.c | 2 +-
arch/powerpc/platforms/512x/mpc512x.h | 1 -
arch/powerpc/platforms/512x/mpc512x_shared.c | 23 ------------------
arch/powerpc/platforms/52xx/mpc52xx_common.c | 32 +------------------------
arch/powerpc/sysdev/Makefile | 3 ++
arch/powerpc/sysdev/mpc5xxx_clocks.c | 33 ++++++++++++++++++++++++++
drivers/ata/pata_mpc52xx.c | 2 +-
drivers/i2c/busses/i2c-mpc.c | 2 +-
drivers/net/fec_mpc52xx.c | 2 +-
drivers/net/fec_mpc52xx_phy.c | 2 +-
drivers/serial/mpc52xx_uart.c | 5 +--
drivers/watchdog/mpc5200_wdt.c | 2 +-
15 files changed, 68 insertions(+), 87 deletions(-)
delete mode 100644 arch/powerpc/include/asm/mpc512x.h
create mode 100644 arch/powerpc/include/asm/mpc5xxx.h
create mode 100644 arch/powerpc/sysdev/mpc5xxx_clocks.c
diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h
deleted file mode 100644
index c48a165..0000000
--- a/arch/powerpc/include/asm/mpc512x.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007
- *
- * Description:
- * MPC5121 Prototypes and definitions
- *
- * This is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_POWERPC_MPC512x_H__
-#define __ASM_POWERPC_MPC512x_H__
-
-extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
-
-#endif /* __ASM_POWERPC_MPC512x_H__ */
-
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h
index 52e049c..1b4f697 100644
--- a/arch/powerpc/include/asm/mpc52xx.h
+++ b/arch/powerpc/include/asm/mpc52xx.h
@@ -16,6 +16,7 @@
#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <asm/prom.h>
+#include <asm/mpc5xxx.h>
#endif /* __ASSEMBLY__ */
#include <linux/suspend.h>
@@ -268,7 +269,6 @@ struct mpc52xx_intr {
#ifndef __ASSEMBLY__
/* mpc52xx_common.c */
-extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
extern void mpc5200_setup_xlb_arbiter(void);
extern void mpc52xx_declare_of_platform_devices(void);
extern void mpc52xx_map_common_devices(void);
diff --git a/arch/powerpc/include/asm/mpc5xxx.h b/arch/powerpc/include/asm/mpc5xxx.h
new file mode 100644
index 0000000..5ce9c5f
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc5xxx.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: John Rigby, <jrigby@freescale.com>, Friday Apr 13 2007
+ *
+ * Description:
+ * MPC5xxx Prototypes and definitions
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_MPC5xxx_H__
+#define __ASM_POWERPC_MPC5xxx_H__
+
+extern unsigned long mpc5xxx_get_bus_frequency(struct device_node *node);
+
+#endif /* __ASM_POWERPC_MPC5xxx_H__ */
+
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 1bcff94..f4c4c6f 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -24,7 +24,7 @@
#include <linux/io.h>
#include <linux/of_platform.h>
-#include <asm/mpc512x.h>
+#include <asm/mpc5xxx.h>
#include <asm/clk_interface.h>
#undef CLK_DEBUG
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h
index 9c03693..22a5352 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -11,7 +11,6 @@
#ifndef __MPC512X_H__
#define __MPC512X_H__
-extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
extern void __init mpc512x_init_IRQ(void);
void __init mpc512x_declare_of_platform_devices(void);
#endif /* __MPC512X_H__ */
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index d8cd579..434d683 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -24,29 +24,6 @@
#include "mpc512x.h"
-unsigned long
-mpc512x_find_ips_freq(struct device_node *node)
-{
- struct device_node *np;
- const unsigned int *p_ips_freq = NULL;
-
- of_node_get(node);
- while (node) {
- p_ips_freq = of_get_property(node, "bus-frequency", NULL);
- if (p_ips_freq)
- break;
-
- np = of_get_parent(node);
- of_node_put(node);
- node = np;
- }
- if (node)
- of_node_put(node);
-
- return p_ips_freq ? *p_ips_freq : 0;
-}
-EXPORT_SYMBOL(mpc512x_find_ips_freq);
-
void __init mpc512x_init_IRQ(void)
{
struct device_node *np;
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 8e3dd5a..a46bad0 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -47,36 +47,6 @@ static DEFINE_SPINLOCK(mpc52xx_lock);
static struct mpc52xx_gpt __iomem *mpc52xx_wdt;
static struct mpc52xx_cdm __iomem *mpc52xx_cdm;
-/**
- * mpc52xx_find_ipb_freq - Find the IPB bus frequency for a device
- * @node: device node
- *
- * Returns IPB bus frequency, or 0 if the bus frequency cannot be found.
- */
-unsigned int
-mpc52xx_find_ipb_freq(struct device_node *node)
-{
- struct device_node *np;
- const unsigned int *p_ipb_freq = NULL;
-
- of_node_get(node);
- while (node) {
- p_ipb_freq = of_get_property(node, "bus-frequency", NULL);
- if (p_ipb_freq)
- break;
-
- np = of_get_parent(node);
- of_node_put(node);
- node = np;
- }
- if (node)
- of_node_put(node);
-
- return p_ipb_freq ? *p_ipb_freq : 0;
-}
-EXPORT_SYMBOL(mpc52xx_find_ipb_freq);
-
-
/*
* Configure the XLB arbiter settings to match what Linux expects.
*/
@@ -221,7 +191,7 @@ unsigned int mpc52xx_get_xtal_freq(struct device_node *node)
if (!mpc52xx_cdm)
return 0;
- freq = mpc52xx_find_ipb_freq(node);
+ freq = mpc5xxx_get_bus_frequency(node);
if (!freq)
return 0;
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index b33b28a..2a1df88 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -47,6 +47,9 @@ obj-$(CONFIG_PPC_DCR) += dcr.o
obj-$(CONFIG_8xx) += mpc8xx_pic.o cpm1.o
obj-$(CONFIG_UCODE_PATCH) += micropatch.o
+obj-$(CONFIG_PPC_MPC512x) += mpc5xxx_clocks.o
+obj-$(CONFIG_PPC_MPC52xx) += mpc5xxx_clocks.o
+
ifeq ($(CONFIG_SUSPEND),y)
obj-$(CONFIG_6xx) += 6xx-suspend.o
endif
diff --git a/arch/powerpc/sysdev/mpc5xxx_clocks.c b/arch/powerpc/sysdev/mpc5xxx_clocks.c
new file mode 100644
index 0000000..34e12f9
--- /dev/null
+++ b/arch/powerpc/sysdev/mpc5xxx_clocks.c
@@ -0,0 +1,33 @@
+/**
+ * mpc5xxx_get_bus_frequency - Find the bus frequency for a device
+ * @node: device node
+ *
+ * Returns bus frequency (IPS on MPC512x, IPB on MPC52xx),
+ * or 0 if the bus frequency cannot be found.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+
+unsigned int
+mpc5xxx_get_bus_frequency(struct device_node *node)
+{
+ struct device_node *np;
+ const unsigned int *p_bus_freq = NULL;
+
+ of_node_get(node);
+ while (node) {
+ p_bus_freq = of_get_property(node, "bus-frequency", NULL);
+ if (p_bus_freq)
+ break;
+
+ np = of_get_parent(node);
+ of_node_put(node);
+ node = np;
+ }
+ if (node)
+ of_node_put(node);
+
+ return p_bus_freq ? *p_bus_freq : 0;
+}
+EXPORT_SYMBOL(mpc5xxx_get_bus_frequency);
diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c
index 68d27bc..2bc2dbe 100644
--- a/drivers/ata/pata_mpc52xx.c
+++ b/drivers/ata/pata_mpc52xx.c
@@ -694,7 +694,7 @@ mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
struct bcom_task *dmatsk = NULL;
/* Get ipb frequency */
- ipb_freq = mpc52xx_find_ipb_freq(op->node);
+ ipb_freq = mpc5xxx_get_bus_frequency(op->node);
if (!ipb_freq) {
dev_err(&op->dev, "could not determine IPB bus frequency\n");
return -ENODEV;
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index dd778d7..d325e86 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -197,7 +197,7 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
return -EINVAL;
/* Determine divider value */
- divider = mpc52xx_find_ipb_freq(node) / clock;
+ divider = mpc5xxx_get_bus_frequency(node) / clock;
/*
* We want to choose an FDR/DFSR that generates an I2C bus speed that
diff --git a/drivers/net/fec_mpc52xx.c b/drivers/net/fec_mpc52xx.c
index 8bbe7f6..5ddf033 100644
--- a/drivers/net/fec_mpc52xx.c
+++ b/drivers/net/fec_mpc52xx.c
@@ -1006,7 +1006,7 @@ mpc52xx_fec_probe(struct of_device *op, const struct of_device_id *match)
priv->phy_addr = FEC5200_PHYADDR_NONE;
priv->speed = 100;
priv->duplex = DUPLEX_HALF;
- priv->phy_speed = ((mpc52xx_find_ipb_freq(op->node) >> 20) / 5) << 1;
+ priv->phy_speed = ((mpc5xxx_get_bus_frequency(op->node) >> 20) / 5) << 1;
/* the 7-wire property means don't use MII mode */
if (of_find_property(op->node, "fsl,7-wire-mode", NULL))
diff --git a/drivers/net/fec_mpc52xx_phy.c b/drivers/net/fec_mpc52xx_phy.c
index dd9bfa4..176e9b8 100644
--- a/drivers/net/fec_mpc52xx_phy.c
+++ b/drivers/net/fec_mpc52xx_phy.c
@@ -120,7 +120,7 @@ static int mpc52xx_fec_mdio_probe(struct of_device *of,
/* set MII speed */
out_be32(&priv->regs->mii_speed,
- ((mpc52xx_find_ipb_freq(of->node) >> 20) / 5) << 1);
+ ((mpc5xxx_get_bus_frequency(of->node) >> 20) / 5) << 1);
err = mdiobus_register(bus);
if (err)
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
index b3feb61..abbd146 100644
--- a/drivers/serial/mpc52xx_uart.c
+++ b/drivers/serial/mpc52xx_uart.c
@@ -76,7 +76,6 @@
#include <linux/of_platform.h>
#include <asm/mpc52xx.h>
-#include <asm/mpc512x.h>
#include <asm/mpc52xx_psc.h>
#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
@@ -254,7 +253,7 @@ static unsigned long mpc52xx_getuartclk(void *p)
* but the generic serial code assumes 16
* so return ipb freq / 2
*/
- return mpc52xx_find_ipb_freq(p) / 2;
+ return mpc5xxx_get_bus_frequency(p) / 2;
}
static struct psc_ops mpc52xx_psc_ops = {
@@ -391,7 +390,7 @@ static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
static unsigned long mpc512x_getuartclk(void *p)
{
- return mpc512x_find_ips_freq(p);
+ return mpc5xxx_get_bus_frequency(p);
}
static struct psc_ops mpc512x_psc_ops = {
diff --git a/drivers/watchdog/mpc5200_wdt.c b/drivers/watchdog/mpc5200_wdt.c
index 465fe36..fa9c47c 100644
--- a/drivers/watchdog/mpc5200_wdt.c
+++ b/drivers/watchdog/mpc5200_wdt.c
@@ -188,7 +188,7 @@ static int mpc5200_wdt_probe(struct of_device *op,
if (!wdt)
return -ENOMEM;
- wdt->ipb_freq = mpc52xx_find_ipb_freq(op->node);
+ wdt->ipb_freq = mpc5xxx_get_bus_frequency(op->node);
err = of_address_to_resource(op->node, 0, &wdt->mem);
if (err)
--
1.6.0.6
^ permalink raw reply related
* [PATCH RFC] fs_enet/mii-fec.c: fix MII speed calculation
From: Wolfgang Denk @ 2009-06-11 20:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Wolfgang Denk
In-Reply-To: <fa686aa40906080737h64bad3cfv32155e5b819d650b@mail.gmail.com>
The MII speed calculation was incorrectly based on the CPU clock
(ppc_proc_freq) instead of the bus clock; it worked only by chance and
for some CPU clock frequencies.
This patch makes it use the correct clock and adds some error
handling.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Kumar Gala <galak@kernel.crashing.org>
---
This is mostly a fix for an old bug - it's starnge that this went
unnoticed so far. It worked only because the incorrectly computed
value was truncated due to the fact that the MII_SPEED field in the
rebister is only 6 bits wide - but, depending on the system clock
frequency, non working systems (MII_SPEED set to zero or DIS_PREAMBLE
set to one) might result as well.
This patch is marked a RFC for the following reasons:
1) drivers/net/fs_enet/mii-fec.c now uses mpc5xxx_get_mii_speed()
which makes it 5xxx specific. I don't really like this, but did
not see a clean way to avoid it either.
2) We probably should also use mpc5xxx_get_mii_speed() in
drivers/net/fec_mpc52xx.c and drivers/net/fec_mpc52xx_phy.c, which
also contain code to calculate the MII speed. But then we should
also add some error checking to the code there, and we should make
sure that only the bits that belong to the MII_SPEED field get
written when setting the MII speed.
I'm not sure if such changes are considered necessary, and if, if
they should be added to this patch or handled in a separate one.
arch/powerpc/sysdev/mpc5xxx_clocks.c | 37 ++++++++++++++++++++++++++++++++++
drivers/net/fs_enet/mii-fec.c | 9 ++++++-
2 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/sysdev/mpc5xxx_clocks.c b/arch/powerpc/sysdev/mpc5xxx_clocks.c
index 34e12f9..3e9584b 100644
--- a/arch/powerpc/sysdev/mpc5xxx_clocks.c
+++ b/arch/powerpc/sysdev/mpc5xxx_clocks.c
@@ -31,3 +31,40 @@ mpc5xxx_get_bus_frequency(struct device_node *node)
return p_bus_freq ? *p_bus_freq : 0;
}
EXPORT_SYMBOL(mpc5xxx_get_bus_frequency);
+
+/**
+ * mpc5xxx_get_get_mii_speed - Get the MII_SPEED value
+ * @node: device node
+ *
+ * Returns the MII_SPEED value for MPC512x and MPC52xx systems.
+ * The value gets computed such that the resulting MDC frequency
+ * is 2.5 MHz or lower.
+ */
+
+int
+mpc5xxx_get_mii_speed(struct of_device *ofdev)
+{
+ unsigned int clock, speed;
+
+ clock = mpc5xxx_get_bus_frequency(ofdev->node);
+
+ if (!clock) {
+ dev_err(&ofdev->dev, "could not determine IPS/IPB clock\n");
+ return -ENODEV;
+ }
+
+ /* scale for a MII clock <= 2.5 MHz */
+ speed = (clock + 2499999) / 2500000;
+
+ /* only 6 bits available for MII speed */
+ if (speed > 0x3F) {
+ speed = 0x3F;
+ dev_err(&ofdev->dev,
+ "MII clock (%d MHz) exceeds max (2.5 MHz)\n",
+ clock / speed);
+ }
+
+ /* Field is in bits 25:30 of MII_SPEED register */
+ return speed << 1;
+}
+EXPORT_SYMBOL(mpc5xxx_get_mii_speed);
diff --git a/drivers/net/fs_enet/mii-fec.c b/drivers/net/fs_enet/mii-fec.c
index 28077cc..a2693b4 100644
--- a/drivers/net/fs_enet/mii-fec.c
+++ b/drivers/net/fs_enet/mii-fec.c
@@ -36,6 +36,7 @@
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
+#include <asm/mpc5xxx.h>
#include "fs_enet.h"
#include "fec.h"
@@ -152,13 +153,17 @@ static int __devinit fs_enet_mdio_probe(struct of_device *ofdev,
if (!fec->fecp)
goto out_fec;
- fec->mii_speed = ((ppc_proc_freq + 4999999) / 5000000) << 1;
+ i = mpc5xxx_get_mii_speed(ofdev);
+ if (i < 0)
+ goto out_unmap_regs;
+
+ fec->mii_speed = i;
setbits32(&fec->fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
setbits32(&fec->fecp->fec_ecntrl, FEC_ECNTRL_PINMUX |
FEC_ECNTRL_ETHER_EN);
out_be32(&fec->fecp->fec_ievent, FEC_ENET_MII);
- out_be32(&fec->fecp->fec_mii_speed, fec->mii_speed);
+ clrsetbits_be32(&fec->fecp->fec_mii_speed, 0x7E, fec->mii_speed);
new_bus->phy_mask = ~0;
new_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
--
1.6.0.6
^ permalink raw reply related
* [PATCH] sdhci: Add support for hosts that are only capable of 1-bit transfers
From: Anton Vorontsov @ 2009-06-11 20:15 UTC (permalink / raw)
To: Pierre Ossman; +Cc: linuxppc-dev, devicetree-discuss, sdhci-devel
Some hosts (hardware configurations, or particular SD/MMC slots) may
not support 4-bit bus. For example, on MPC8569E-MDS boards we can
switch between serial (1-bit only) and nibble (4-bit) modes, thought
we have to disable more peripherals to work in 4-bit mode.
Along with some small core changes, this patch modifies sdhci-of
driver, so that now it looks for "mode" property in the device-tree.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
Pierre, I'm not sure if a quirk would be appropriate here. If so,
I can redo the patch with FORCE_1_BIT_DATA quirk.
Thanks,
Documentation/powerpc/dts-bindings/fsl/esdhc.txt | 2 ++
drivers/mmc/host/sdhci-of.c | 7 +++++++
drivers/mmc/host/sdhci-pci.c | 1 +
drivers/mmc/host/sdhci.c | 2 +-
4 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
index 5093ddf..298b865 100644
--- a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
@@ -10,6 +10,8 @@ Required properties:
- interrupts : should contain eSDHC interrupt.
- interrupt-parent : interrupt source phandle.
- clock-frequency : specifies eSDHC base clock frequency.
+ - mode : specifies eSDHC mode, valid values are: "1-bit" and "4-bit".
+ If mode is unspecified, then 4-bit mode is assumed.
Example:
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 09cc597..12b9615 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -14,6 +14,7 @@
*/
#include <linux/module.h>
+#include <linux/string.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/interrupt.h>
@@ -212,6 +213,7 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
struct sdhci_of_data *sdhci_of_data = match->data;
struct sdhci_host *host;
struct sdhci_of_host *of_host;
+ const char *mode;
const u32 *clk;
int size;
int ret;
@@ -244,6 +246,11 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
host->ops = &sdhci_of_data->ops;
}
+ mode = of_get_property(np, "mode", &size);
+ if (!mode || (size == sizeof("4-bit") &&
+ !strncmp(mode, "4-bit", size)))
+ host->mmc->caps |= MMC_CAP_4_BIT_DATA;
+
clk = of_get_property(np, "clock-frequency", &size);
if (clk && size == sizeof(*clk) && *clk)
of_host->clock = *clk;
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index 65be279..c447d6c 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -535,6 +535,7 @@ static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
host->hw_name = "PCI";
host->ops = &sdhci_pci_ops;
host->quirks = chip->quirks;
+ host->mmc->caps = MMC_CAP_4_BIT_DATA;
host->irq = pdev->irq;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 9234be2..e31dd2a 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1721,7 +1721,7 @@ int sdhci_add_host(struct sdhci_host *host)
mmc->ops = &sdhci_ops;
mmc->f_min = host->max_clk / 256;
mmc->f_max = host->max_clk;
- mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
+ mmc->caps |= MMC_CAP_SDIO_IRQ;
if (caps & SDHCI_CAN_DO_HISPD)
mmc->caps |= MMC_CAP_SD_HIGHSPEED;
--
1.6.3.1
^ permalink raw reply related
* Re: SD card over (xilinx_)SPI, timeout error while CID
From: Lorenz Kolb @ 2009-06-11 20:05 UTC (permalink / raw)
To: Ricardo Ribalda Delgado
Cc: joachim, dbrownell, Joachim Foerster, hp, lorenz, linuxppc-dev,
mike, pierre, jan.nikitenko, john.linn, linuxkernel
In-Reply-To: <aa76a2be0906111215j15933053rf128f1985a982ca0__26561.0047536486$1244748319$gmane$org@mail.gmail.com>
Hello,
Ricardo Ribalda Delgado wrote:
> Hello,
>
> It seems that I am facing the same problem!. I attach another trace
> that also shows the sd I/O.
Is the I/O logged from within the Xilinx-SPI-Driver or from within the
mmc-spi-layer?
The response to CMD10 seems quite strange to me. The R1 answer to that
command says that everything is OK, so what is done next is that the
0xfe token will be expected by the mmc-spi-layer. Obviously that one is
not received within the proper time (assuming your data-logging was done
from within xilinx-spi-driver). Also be aware of printk() taking
milliseconds for printing to console, within time critical routines that
might not be the best choice for debugging.
What frequency does Your SPI-Bus use?
Also double check to completely disable the whole
if (spi->master->dev.parent->dma_mask) {
...
}
block within mmc_spi_probe(). That worked for us (as we already said as
an ugly workaround).
Regards,
Lorenz
^ permalink raw reply
* [PATCH -next 3/4] powerpc/85xx: Add defconfig for X-ES MPC85xx boards
From: Nate Case @ 2009-06-11 19:43 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Nate Case, David Gibson
In-Reply-To: <1244749381-17429-3-git-send-email-ncase@xes-inc.com>
Signed-off-by: Nate Case <ncase@xes-inc.com>
---
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig | 1821 +++++++++++++++++++++++
1 files changed, 1821 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
diff --git a/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
new file mode 100644
index 0000000..2552cbe
--- /dev/null
+++ b/arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
@@ -0,0 +1,1821 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30-rc6
+# Thu Jun 11 11:25:17 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+# CONFIG_6xx is not set
+CONFIG_PPC_85xx=y
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_E500=y
+# CONFIG_PPC_E500MC is not set
+CONFIG_BOOKE=y
+CONFIG_FSL_BOOKE=y
+CONFIG_FSL_EMB_PERFMON=y
+# CONFIG_PHYS_64BIT is not set
+CONFIG_SPE=y
+CONFIG_PPC_MMU_NOHASH=y
+CONFIG_PPC_BOOK3E_MMU=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+CONFIG_GENERIC_TBSYNC=y
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+CONFIG_AUDIT=y
+# CONFIG_AUDITSYSCALL is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+CONFIG_PPC_MSI_BITMAP=y
+
+#
+# Platform support
+#
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_MPC85xx=y
+# CONFIG_MPC8540_ADS is not set
+# CONFIG_MPC8560_ADS is not set
+# CONFIG_MPC85xx_CDS is not set
+# CONFIG_MPC85xx_MDS is not set
+# CONFIG_MPC8536_DS is not set
+# CONFIG_MPC85xx_DS is not set
+# CONFIG_SOCRATES is not set
+# CONFIG_KSI8560 is not set
+CONFIG_XES_MPC85xx=y
+# CONFIG_STX_GP3 is not set
+# CONFIG_TQM8540 is not set
+# CONFIG_TQM8541 is not set
+# CONFIG_TQM8548 is not set
+# CONFIG_TQM8555 is not set
+# CONFIG_TQM8560 is not set
+# CONFIG_SBC8548 is not set
+# CONFIG_SBC8560 is not set
+# CONFIG_IPIC is not set
+CONFIG_MPIC=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_CPM2 is not set
+# CONFIG_FSL_ULI1575 is not set
+CONFIG_MPC8xxx_GPIO=y
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+CONFIG_HIGHMEM=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_MATH_EMULATION=y
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_IRQ_ALL_CPUS is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_FSL_PCI=y
+CONFIG_FSL_LBC=y
+CONFIG_PPC_PCI_CHOICE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIEASPM is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+CONFIG_ADVANCED_OPTIONS=y
+CONFIG_LOWMEM_SIZE_BOOL=y
+CONFIG_LOWMEM_SIZE=0x40000000
+# CONFIG_LOWMEM_CAM_NUM_BOOL is not set
+CONFIG_LOWMEM_CAM_NUM=3
+# CONFIG_RELOCATABLE is not set
+CONFIG_PAGE_OFFSET_BOOL=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_KERNEL_START_BOOL=y
+CONFIG_KERNEL_START=0x80000000
+# CONFIG_PHYSICAL_START_BOOL is not set
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_PHYSICAL_ALIGN=0x04000000
+CONFIG_TASK_SIZE_BOOL=y
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_ARPD=y
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_NAND_FSL_UPM=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=131072
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_SATA_PMP=y
+CONFIG_SATA_AHCI=y
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_FSL is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+CONFIG_PATA_ALI=y
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+CONFIG_BROADCOM_PHY=y
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_ATL2 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+CONFIG_E1000=y
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+CONFIG_FSL_PQ_MDIO=y
+CONFIG_GIANFAR=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_XILINX_XPS_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_HVC_UDBG is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_NVRAM=y
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_XILINX is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+CONFIG_SENSORS_DS1621=y
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+CONFIG_SENSORS_LM90=y
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_BOOKE_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_REGULATOR is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_DRAGONRISE_FF is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_GREENASIA_FF is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_ISP1760_HCD=y
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+CONFIG_LEDS_GPIO_OF=y
+# CONFIG_LEDS_LP5521 is not set
+CONFIG_LEDS_PCA955X=y
+# CONFIG_LEDS_BD2802 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC=y
+
+#
+# Reporting subsystems
+#
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_MPC85XX=y
+# CONFIG_EDAC_AMD8131 is not set
+# CONFIG_EDAC_AMD8111 is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+CONFIG_RTC_DRV_CMOS=y
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_GENERIC is not set
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_FSL_DMA=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+CONFIG_NET_DMA=y
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+# CONFIG_NFSD_V3 is not set
+# CONFIG_NFSD_V4 is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+
+#
+# Tracers
+#
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_EVENT_TRACER is not set
+# CONFIG_BOOT_TRACER is not set
+# CONFIG_TRACE_BRANCH_PROFILING is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_DEBUG_STACKOVERFLOW is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_CODE_PATCHING_SELFTEST is not set
+# CONFIG_FTR_FIXUP_SELFTEST is not set
+# CONFIG_MSI_BITMAP_SELFTEST is not set
+# CONFIG_XMON is not set
+# CONFIG_IRQSTACKS is not set
+# CONFIG_BDI_SWITCH is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_CRYPTO_DEV_TALITOS is not set
+# CONFIG_PPC_CLOCK is not set
+# CONFIG_VIRTUALIZATION is not set
--
1.6.0.4
^ permalink raw reply related
* [PATCH -next 2/4] powerpc/85xx: Add dts files for X-ES MPC85xx boards
From: Nate Case @ 2009-06-11 19:42 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Nate Case, David Gibson
In-Reply-To: <1244749381-17429-2-git-send-email-ncase@xes-inc.com>
Add device tree source files for various MPC85xx boards from Extreme
Engineering Solutions. Supported boards include XPedite5370,
XPedite5200, XPedite5301, XPedite5330, and XCalibur1501.
Signed-off-by: Nate Case <ncase@xes-inc.com>
---
arch/powerpc/boot/dts/xcalibur1501.dts | 696 +++++++++++++++++++++++++++
arch/powerpc/boot/dts/xpedite5200.dts | 466 ++++++++++++++++++
arch/powerpc/boot/dts/xpedite5200_xmon.dts | 506 ++++++++++++++++++++
arch/powerpc/boot/dts/xpedite5301.dts | 640 +++++++++++++++++++++++++
arch/powerpc/boot/dts/xpedite5330.dts | 707 ++++++++++++++++++++++++++++
arch/powerpc/boot/dts/xpedite5370.dts | 638 +++++++++++++++++++++++++
6 files changed, 3653 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/xcalibur1501.dts
create mode 100644 arch/powerpc/boot/dts/xpedite5200.dts
create mode 100644 arch/powerpc/boot/dts/xpedite5200_xmon.dts
create mode 100644 arch/powerpc/boot/dts/xpedite5301.dts
create mode 100644 arch/powerpc/boot/dts/xpedite5330.dts
create mode 100644 arch/powerpc/boot/dts/xpedite5370.dts
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts
new file mode 100644
index 0000000..ac0a617
--- /dev/null
+++ b/arch/powerpc/boot/dts/xcalibur1501.dts
@@ -0,0 +1,696 @@
+/*
+ * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
+ * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
+ *
+ * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/ {
+ model = "xes,xcalibur1501";
+ compatible = "xes,xcalibur1501", "xes,MPC8572";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci2 = &pci2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8572@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,8572@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
+ };
+
+ localbus@ef005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xef005000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+ /* Local bus region mappings */
+ ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */
+ 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */
+ 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
+ 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */
+ 4 0 0 0xe9000000 0x100000>; /* CS4: USB */
+
+ nor-boot@0,0 {
+ compatible = "amd,s29gl01gp", "cfi-flash";
+ bank-width = <2>;
+ reg = <0 0 0x8000000>; /* 128MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Primary user space";
+ reg = <0x00000000 0x6f00000>; /* 111 MB */
+ };
+ partition@6f00000 {
+ label = "Primary kernel";
+ reg = <0x6f00000 0x1000000>; /* 16 MB */
+ };
+ partition@7f00000 {
+ label = "Primary DTB";
+ reg = <0x7f00000 0x40000>; /* 256 KB */
+ };
+ partition@7f40000 {
+ label = "Primary U-Boot environment";
+ reg = <0x7f40000 0x40000>; /* 256 KB */
+ };
+ partition@7f80000 {
+ label = "Primary U-Boot";
+ reg = <0x7f80000 0x80000>; /* 512 KB */
+ read-only;
+ };
+ };
+
+ nor-alternate@1,0 {
+ compatible = "amd,s29gl01gp", "cfi-flash";
+ bank-width = <2>;
+ //reg = <0xf0000000 0x08000000>; /* 128MB */
+ reg = <1 0 0x8000000>; /* 128MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Secondary user space";
+ reg = <0x00000000 0x6f00000>; /* 111 MB */
+ };
+ partition@6f00000 {
+ label = "Secondary kernel";
+ reg = <0x6f00000 0x1000000>; /* 16 MB */
+ };
+ partition@7f00000 {
+ label = "Secondary DTB";
+ reg = <0x7f00000 0x40000>; /* 256 KB */
+ };
+ partition@7f40000 {
+ label = "Secondary U-Boot environment";
+ reg = <0x7f40000 0x40000>; /* 256 KB */
+ };
+ partition@7f80000 {
+ label = "Secondary U-Boot";
+ reg = <0x7f80000 0x80000>; /* 512 KB */
+ read-only;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * Actual part could be ST Micro NAND08GW3B2A (1 GB),
+ * Micron MT29F8G08DAA (2x 512 MB), or Micron
+ * MT29F16G08FAA (2x 1 GB), depending on the build
+ * configuration
+ */
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <2 0 0x40000>;
+ /* U-Boot should fix this up if chip size > 1 GB */
+ partition@0 {
+ label = "NAND Filesystem";
+ reg = <0 0x40000000>;
+ };
+ };
+
+ usb@4,0 {
+ compatible = "nxp,usb-isp1761";
+ reg = <4 0 0x100000>;
+ bus-width = <32>;
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ };
+ };
+
+ soc8572@ef000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8572-immr", "simple-bus";
+ ranges = <0x0 0 0xef000000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ memory-controller@6000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x6000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,mpc8572-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x100000>; // L2, 1M
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ temp-sensor@48 {
+ compatible = "dallas,ds1631", "dallas,ds1621";
+ reg = <0x48>;
+ };
+
+ temp-sensor@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+
+ cpu-supervisor@51 {
+ compatible = "dallas,ds4510";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,at24c128b";
+ reg = <0x54>;
+ };
+
+ rtc@68 {
+ compatible = "stm,m41t00",
+ "dallas,ds1338";
+ reg = <0x68>;
+ };
+
+ pcie-switch@6a {
+ compatible = "plx,pex8648";
+ reg = <0x6a>;
+ };
+
+ /* On-board signals for VID, flash, serial */
+ gpio1: gpio@18 {
+ compatible = "nxp,pca9557";
+ reg = <0x18>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ /* PMC0/XMC0 signals */
+ gpio2: gpio@1c {
+ compatible = "nxp,pca9557";
+ reg = <0x1c>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ /* PMC1/XMC1 signals */
+ gpio3: gpio@1d {
+ compatible = "nxp,pca9557";
+ reg = <0x1d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ /* CompactPCI signals (sysen, GA[4:0]) */
+ gpio4: gpio@1e {
+ compatible = "nxp,pca9557";
+ reg = <0x1e>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ /* CompactPCI J5 GPIO and FAL/DEG/PRST */
+ gpio5: gpio@1f {
+ compatible = "nxp,pca9557";
+ reg = <0x1f>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ /* eTSEC 1 front panel 0 */
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <4 1>;
+ reg = <0x1>;
+ };
+ phy1: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <4 1>;
+ reg = <0x2>;
+ };
+ phy2: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
+ interrupts = <5 1>;
+ reg = <0x3>;
+ };
+ phy3: ethernet-phy@4 {
+ interrupt-parent = <&mpic>;
+ interrupts = <5 1>;
+ reg = <0x4>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC 2 front panel 1 */
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC 3 PICMG2.16 backplane port 0 */
+ enet2: ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy2>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi2: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC 4 PICMG2.16 backplane port 1 */
+ enet3: ethernet@27000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <3>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x27000 0x1000>;
+ ranges = <0x0 0x27000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <37 2 38 2 39 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi3: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* UART0 */
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ /* UART1 */
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8572-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ msi@41600 {
+ compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ gpio0: gpio@f000 {
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x1000>;
+ interrupts = <47 2>;
+ interrupt-parent = <&mpic>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ label = "Heartbeat";
+ gpios = <&gpio0 4 1>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ yellow {
+ label = "Yellow";
+ gpios = <&gpio0 5 1>;
+ };
+
+ red {
+ label = "Red";
+ gpios = <&gpio0 6 1>;
+ };
+
+ green {
+ label = "Green";
+ gpios = <&gpio0 7 1>;
+ };
+ };
+
+ /* PME (pattern-matcher) */
+ pme@10000 {
+ compatible = "fsl,mpc8572-pme", "pme8572";
+ reg = <0x10000 0x5000>;
+ interrupts = <57 2 64 2 65 2 66 2 67 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ tlu@2f000 {
+ compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+ reg = <0x2f000 0x1000>;
+ interupts = <61 2 >;
+ interrupt-parent = <&mpic>;
+ };
+
+ tlu@15000 {
+ compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+ reg = <0x15000 0x1000>;
+ interupts = <75 2>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+
+ /*
+ * PCI Express controller 3 @ ef008000 is not used.
+ * This would have been pci0 on other mpc85xx platforms.
+ *
+ * PCI Express controller 2 @ ef009000 is not used.
+ * This would have been pci1 on other mpc85xx platforms.
+ */
+
+ /* PCI Express controller 1, wired to PEX8648 PCIe switch */
+ pci2: pcie@ef00a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xef00a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
+ 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x40000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts
new file mode 100644
index 0000000..a0cf53f
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5200.dts
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
+ * Based on TQM8548 device tree
+ *
+ * XPedite5200 PrPMC/XMC module based on MPC8548E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "xes,xpedite5200";
+ compatible = "xes,xpedite5200", "xes,MPC8548";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8548@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>; // Filled in by U-Boot
+ };
+
+ soc@ef000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0x0 0xef000000 0x100000>;
+ bus-frequency = <0>;
+ compatible = "fsl,mpc8548-immr", "simple-bus";
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8548-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,mpc8548-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ /* On-card I2C */
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ /*
+ * Board GPIO:
+ * 0: BRD_CFG0 (1: P14 IO present)
+ * 1: BRD_CFG1 (1: FP ethernet present)
+ * 2: BRD_CFG2 (1: XMC IO present)
+ * 3: XMC root complex indicator
+ * 4: Flash boot device indicator
+ * 5: Flash write protect enable
+ * 6: PMC monarch indicator
+ * 7: PMC EREADY
+ */
+ gpio1: gpio@18 {
+ compatible = "nxp,pca9556";
+ reg = <0x18>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ /* P14 GPIO */
+ gpio2: gpio@19 {
+ compatible = "nxp,pca9556";
+ reg = <0x19>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,at24c16";
+ reg = <0x50>;
+ };
+
+ rtc@68 {
+ compatible = "stm,m41t00",
+ "dallas,ds1338";
+ reg = <0x68>;
+ };
+
+ dtt@48 {
+ compatible = "maxim,max1237";
+ reg = <0x34>;
+ };
+ };
+
+ /* Off-card I2C */
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8548-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8548-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8548-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8548-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ /* eTSEC1: Front panel port 0 */
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x1>;
+ };
+ phy1: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x2>;
+ };
+ phy2: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x3>;
+ };
+ phy3: ethernet-phy@4 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x4>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC2: Front panel port 1 */
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC3: Rear panel port 2 */
+ enet2: ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy2>;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi2: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC4: Rear panel port 3 */
+ enet3: ethernet@27000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <3>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x27000 0x1000>;
+ ranges = <0x0 0x27000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <37 2 38 2 39 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy3>;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi3: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ current-speed = <115200>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ current-speed = <115200>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { // global utilities reg
+ compatible = "fsl,mpc8548-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+ };
+
+ localbus@ef005000 {
+ compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
+ "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0xef005000 0x100>; // BRx, ORx, etc.
+
+ ranges = <
+ 0 0x0 0xfc000000 0x04000000 // NOR boot flash
+ 1 0x0 0xf8000000 0x04000000 // NOR expansion flash
+ 2 0x0 0xef800000 0x00010000 // NAND CE1
+ 3 0x0 0xef840000 0x00010000 // NAND CE2
+ >;
+
+ nor-boot@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0 0x0 0x4000000>;
+ bank-width = <2>;
+
+ partition@0 {
+ label = "Primary OS";
+ reg = <0x00000000 0x180000>;
+ };
+ partition@180000 {
+ label = "Secondary OS";
+ reg = <0x00180000 0x180000>;
+ };
+ partition@300000 {
+ label = "User";
+ reg = <0x00300000 0x3c80000>;
+ };
+ partition@3f80000 {
+ label = "Boot firmware";
+ reg = <0x03f80000 0x80000>;
+ };
+ };
+
+ nor-alternate@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <1 0x0 0x4000000>;
+ bank-width = <2>;
+
+ partition@0 {
+ label = "Filesystem";
+ reg = <0x00000000 0x3f80000>;
+ };
+ partition@3f80000 {
+ label = "Alternate boot firmware";
+ reg = <0x03f80000 0x80000>;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xes,address-ctl-nand";
+ reg = <2 0x0 0x10000>;
+ cle-line = <0x8>; /* CLE tied to A3 */
+ ale-line = <0x10>; /* ALE tied to A4 */
+
+ /* U-Boot should fix this up */
+ partition@0 {
+ label = "NAND Filesystem";
+ reg = <0 0x40000000>;
+ };
+ };
+ };
+
+ /* PMC interface */
+ pci0: pci@ef008000 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
+ reg = <0xef008000 0x1000>;
+ clock-frequency = <33333333>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL */
+ 0xe000 0 0 1 &mpic 2 1
+ 0xe000 0 0 2 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ bus-range = <0 0>;
+ ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
+ 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
+ };
+
+ /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
+};
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
new file mode 100644
index 0000000..c5b2975
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
@@ -0,0 +1,506 @@
+/*
+ * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
+ * Based on TQM8548 device tree
+ *
+ * XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the
+ * xMon boot loader memory map which differs from U-Boot's.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "xes,xpedite5200";
+ compatible = "xes,xpedite5200", "xes,MPC8548";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ form-factor = "PMC/XMC";
+ boot-bank = <0x0>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8548@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0>; // Filled in by boot loader
+ };
+
+ soc@ef000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ ranges = <0x0 0xef000000 0x100000>;
+ bus-frequency = <0>;
+ compatible = "fsl,mpc8548-immr", "simple-bus";
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,mpc8548-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8548-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,mpc8548-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2, 512K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ /* On-card I2C */
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ /*
+ * Board GPIO:
+ * 0: BRD_CFG0 (1: P14 IO present)
+ * 1: BRD_CFG1 (1: FP ethernet present)
+ * 2: BRD_CFG2 (1: XMC IO present)
+ * 3: XMC root complex indicator
+ * 4: Flash boot device indicator
+ * 5: Flash write protect enable
+ * 6: PMC monarch indicator
+ * 7: PMC EREADY
+ */
+ gpio1: gpio@18 {
+ compatible = "nxp,pca9556";
+ reg = <0x18>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ /* P14 GPIO */
+ gpio2: gpio@19 {
+ compatible = "nxp,pca9556";
+ reg = <0x19>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,at24c16";
+ reg = <0x50>;
+ };
+
+ rtc@68 {
+ compatible = "stm,m41t00",
+ "dallas,ds1338";
+ reg = <0x68>;
+ };
+
+ dtt@48 {
+ compatible = "maxim,max1237";
+ reg = <0x34>;
+ };
+ };
+
+ /* Off-card I2C */
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8548-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8548-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8548-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8548-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ /* eTSEC1: Front panel port 0 */
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x1>;
+ };
+ phy1: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x2>;
+ };
+ phy2: ethernet-phy@3 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x3>;
+ };
+ phy3: ethernet-phy@4 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x4>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC2: Front panel port 1 */
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC3: Rear panel port 2 */
+ enet2: ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy2>;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi2: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC4: Rear panel port 3 */
+ enet3: ethernet@27000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <3>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x27000 0x1000>;
+ ranges = <0x0 0x27000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <37 2 38 2 39 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy3>;
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi3: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ current-speed = <9600>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ current-speed = <9600>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { // global utilities reg
+ compatible = "fsl,mpc8548-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+ };
+
+ localbus@ef005000 {
+ compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
+ "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0xef005000 0x100>; // BRx, ORx, etc.
+
+ ranges = <
+ 0 0x0 0xf8000000 0x08000000 // NOR boot flash
+ 1 0x0 0xf0000000 0x08000000 // NOR expansion flash
+ 2 0x0 0xe8000000 0x00010000 // NAND CE1
+ 3 0x0 0xe8010000 0x00010000 // NAND CE2
+ >;
+
+ nor-boot@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0 0x0 0x4000000>;
+ bank-width = <2>;
+
+ partition@0 {
+ label = "Primary OS";
+ reg = <0x00000000 0x180000>;
+ };
+ partition@180000 {
+ label = "Secondary OS";
+ reg = <0x00180000 0x180000>;
+ };
+ partition@300000 {
+ label = "User";
+ reg = <0x00300000 0x3c80000>;
+ };
+ partition@3f80000 {
+ label = "Boot firmware";
+ reg = <0x03f80000 0x80000>;
+ };
+ };
+
+ nor-alternate@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <1 0x0 0x4000000>;
+ bank-width = <2>;
+
+ partition@0 {
+ label = "Filesystem";
+ reg = <0x00000000 0x3f80000>;
+ };
+ partition@3f80000 {
+ label = "Alternate boot firmware";
+ reg = <0x03f80000 0x80000>;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xes,address-ctl-nand";
+ reg = <2 0x0 0x10000>;
+ cle-line = <0x8>; /* CLE tied to A3 */
+ ale-line = <0x10>; /* ALE tied to A4 */
+
+ partition@0 {
+ label = "NAND Filesystem";
+ reg = <0 0x40000000>;
+ };
+ };
+ };
+
+ /* PMC interface */
+ pci0: pci@ef008000 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+ device_type = "pci";
+ reg = <0xef008000 0x1000>;
+ clock-frequency = <33333333>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL */
+ 0xe000 0 0 1 &mpic 2 1
+ 0xe000 0 0 2 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ bus-range = <0 0>;
+ ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>;
+ };
+
+ /* XMC PCIe */
+ pci1: pcie@ef00a000 {
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x00000 0 0 1 &mpic 0 1
+ 0x00000 0 0 2 &mpic 1 1
+ 0x00000 0 0 3 &mpic 2 1
+ 0x00000 0 0 4 &mpic 3 1>;
+
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ bus-range = <0 0xff>;
+ ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>;
+ clock-frequency = <33333333>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xef00a000 0x1000>;
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x02000000 0 0xc0000000 0x02000000 0
+ 0xc0000000 0 0x20000000
+ 0x01000000 0 0x00000000 0x01000000 0
+ 0x00000000 0 0x08000000>;
+ };
+ };
+
+ /* Needed for dtbImage boot wrapper compatibility */
+ chosen {
+ linux,stdout-path = &serial0;
+ };
+};
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts
new file mode 100644
index 0000000..db7faf5
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5301.dts
@@ -0,0 +1,640 @@
+/*
+ * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
+ * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
+ *
+ * XPedite5301 PMC/XMC module based on MPC8572E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/ {
+ model = "xes,xpedite5301";
+ compatible = "xes,xpedite5301", "xes,MPC8572";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ form-factor = "PMC/XMC";
+ boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8572@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,8572@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
+ };
+
+ localbus@ef005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xef005000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+ /* Local bus region mappings */
+ ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
+ 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
+ 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
+ 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
+
+ nor-boot@0,0 {
+ compatible = "amd,s29gl01gp", "cfi-flash";
+ bank-width = <2>;
+ reg = <0 0 0x8000000>; /* 128MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Primary user space";
+ reg = <0x00000000 0x6f00000>; /* 111 MB */
+ };
+ partition@6f00000 {
+ label = "Primary kernel";
+ reg = <0x6f00000 0x1000000>; /* 16 MB */
+ };
+ partition@7f00000 {
+ label = "Primary DTB";
+ reg = <0x7f00000 0x40000>; /* 256 KB */
+ };
+ partition@7f40000 {
+ label = "Primary U-Boot environment";
+ reg = <0x7f40000 0x40000>; /* 256 KB */
+ };
+ partition@7f80000 {
+ label = "Primary U-Boot";
+ reg = <0x7f80000 0x80000>; /* 512 KB */
+ read-only;
+ };
+ };
+
+ nor-alternate@1,0 {
+ compatible = "amd,s29gl01gp", "cfi-flash";
+ bank-width = <2>;
+ //reg = <0xf0000000 0x08000000>; /* 128MB */
+ reg = <1 0 0x8000000>; /* 128MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Secondary user space";
+ reg = <0x00000000 0x6f00000>; /* 111 MB */
+ };
+ partition@6f00000 {
+ label = "Secondary kernel";
+ reg = <0x6f00000 0x1000000>; /* 16 MB */
+ };
+ partition@7f00000 {
+ label = "Secondary DTB";
+ reg = <0x7f00000 0x40000>; /* 256 KB */
+ };
+ partition@7f40000 {
+ label = "Secondary U-Boot environment";
+ reg = <0x7f40000 0x40000>; /* 256 KB */
+ };
+ partition@7f80000 {
+ label = "Secondary U-Boot";
+ reg = <0x7f80000 0x80000>; /* 512 KB */
+ read-only;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * Actual part could be ST Micro NAND08GW3B2A (1 GB),
+ * Micron MT29F8G08DAA (2x 512 MB), or Micron
+ * MT29F16G08FAA (2x 1 GB), depending on the build
+ * configuration
+ */
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <2 0 0x40000>;
+ /* U-Boot should fix this up if chip size > 1 GB */
+ partition@0 {
+ label = "NAND Filesystem";
+ reg = <0 0x40000000>;
+ };
+ };
+
+ };
+
+ soc8572@ef000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8572-immr", "simple-bus";
+ ranges = <0x0 0 0xef000000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ memory-controller@6000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x6000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,mpc8572-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x100000>; // L2, 1M
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ temp-sensor@48 {
+ compatible = "dallas,ds1631", "dallas,ds1621";
+ reg = <0x48>;
+ };
+
+ temp-sensor@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+
+ cpu-supervisor@51 {
+ compatible = "dallas,ds4510";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,at24c128b";
+ reg = <0x54>;
+ };
+
+ rtc@68 {
+ compatible = "stm,m41t00",
+ "dallas,ds1338";
+ reg = <0x68>;
+ };
+
+ pcie-switch@70 {
+ compatible = "plx,pex8518";
+ reg = <0x70>;
+ };
+
+ gpio1: gpio@18 {
+ compatible = "nxp,pca9557";
+ reg = <0x18>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio2: gpio@1c {
+ compatible = "nxp,pca9557";
+ reg = <0x1c>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio3: gpio@1e {
+ compatible = "nxp,pca9557";
+ reg = <0x1e>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio4: gpio@1f {
+ compatible = "nxp,pca9557";
+ reg = <0x1f>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ /* eTSEC 1 */
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x1>;
+ };
+ phy1: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x2>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC 2 */
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* UART0 */
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ /* UART1 */
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8572-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ msi@41600 {
+ compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ gpio0: gpio@f000 {
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x1000>;
+ interrupts = <47 2>;
+ interrupt-parent = <&mpic>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ label = "Heartbeat";
+ gpios = <&gpio0 4 1>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ yellow {
+ label = "Yellow";
+ gpios = <&gpio0 5 1>;
+ };
+
+ red {
+ label = "Red";
+ gpios = <&gpio0 6 1>;
+ };
+
+ green {
+ label = "Green";
+ gpios = <&gpio0 7 1>;
+ };
+ };
+
+ /* PME (pattern-matcher) */
+ pme@10000 {
+ compatible = "fsl,mpc8572-pme", "pme8572";
+ reg = <0x10000 0x5000>;
+ interrupts = <57 2 64 2 65 2 66 2 67 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ tlu@2f000 {
+ compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+ reg = <0x2f000 0x1000>;
+ interupts = <61 2 >;
+ interrupt-parent = <&mpic>;
+ };
+
+ tlu@15000 {
+ compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+ reg = <0x15000 0x1000>;
+ interupts = <75 2>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+
+ /*
+ * PCI Express controller 3 @ ef008000 is not used.
+ * This would have been pci0 on other mpc85xx platforms.
+ */
+
+ /* PCI Express controller 2, wired to XMC P15 connector */
+ pci1: pcie@ef009000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xef009000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
+ 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
+ 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
+ >;
+ pcie@0 {
+ reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ /* PCI Express controller 1, wired to PEX8112 for PMC interface */
+ pci2: pcie@ef00a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xef00a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
+ 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x40000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts
new file mode 100644
index 0000000..c364ca6
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5330.dts
@@ -0,0 +1,707 @@
+/*
+ * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
+ * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
+ *
+ * XPedite5330 3U CompactPCI module based on MPC8572E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/ {
+ model = "xes,xpedite5330";
+ compatible = "xes,xpedite5330", "xes,MPC8572";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ form-factor = "3U CompactPCI";
+ boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ };
+
+ pmcslots {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmcslot@0 {
+ cell-index = <0>;
+ /*
+ * boolean properties (true if defined):
+ * monarch;
+ * module-present;
+ */
+ };
+ };
+
+ xmcslots {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ xmcslot@0 {
+ cell-index = <0>;
+ /*
+ * boolean properties (true if defined):
+ * module-present;
+ */
+ };
+ };
+
+ cpci {
+ /*
+ * boolean properties (true if defined):
+ * system-controller;
+ */
+ system-controller;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8572@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,8572@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
+ };
+
+ localbus@ef005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xef005000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+ /* Local bus region mappings */
+ ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
+ 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
+ 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
+ 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
+
+ nor-boot@0,0 {
+ compatible = "amd,s29gl01gp", "cfi-flash";
+ bank-width = <2>;
+ reg = <0 0 0x8000000>; /* 128MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Primary user space";
+ reg = <0x00000000 0x6f00000>; /* 111 MB */
+ };
+ partition@6f00000 {
+ label = "Primary kernel";
+ reg = <0x6f00000 0x1000000>; /* 16 MB */
+ };
+ partition@7f00000 {
+ label = "Primary DTB";
+ reg = <0x7f00000 0x40000>; /* 256 KB */
+ };
+ partition@7f40000 {
+ label = "Primary U-Boot environment";
+ reg = <0x7f40000 0x40000>; /* 256 KB */
+ };
+ partition@7f80000 {
+ label = "Primary U-Boot";
+ reg = <0x7f80000 0x80000>; /* 512 KB */
+ read-only;
+ };
+ };
+
+ nor-alternate@1,0 {
+ compatible = "amd,s29gl01gp", "cfi-flash";
+ bank-width = <2>;
+ //reg = <0xf0000000 0x08000000>; /* 128MB */
+ reg = <1 0 0x8000000>; /* 128MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Secondary user space";
+ reg = <0x00000000 0x6f00000>; /* 111 MB */
+ };
+ partition@6f00000 {
+ label = "Secondary kernel";
+ reg = <0x6f00000 0x1000000>; /* 16 MB */
+ };
+ partition@7f00000 {
+ label = "Secondary DTB";
+ reg = <0x7f00000 0x40000>; /* 256 KB */
+ };
+ partition@7f40000 {
+ label = "Secondary U-Boot environment";
+ reg = <0x7f40000 0x40000>; /* 256 KB */
+ };
+ partition@7f80000 {
+ label = "Secondary U-Boot";
+ reg = <0x7f80000 0x80000>; /* 512 KB */
+ read-only;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * Actual part could be ST Micro NAND08GW3B2A (1 GB),
+ * Micron MT29F8G08DAA (2x 512 MB), or Micron
+ * MT29F16G08FAA (2x 1 GB), depending on the build
+ * configuration
+ */
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <2 0 0x40000>;
+ /* U-Boot should fix this up if chip size > 1 GB */
+ partition@0 {
+ label = "NAND Filesystem";
+ reg = <0 0x40000000>;
+ };
+ };
+
+ };
+
+ soc8572@ef000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8572-immr", "simple-bus";
+ ranges = <0x0 0 0xef000000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ memory-controller@6000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x6000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,mpc8572-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x100000>; // L2, 1M
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ temp-sensor@48 {
+ compatible = "dallas,ds1631", "dallas,ds1621";
+ reg = <0x48>;
+ };
+
+ temp-sensor@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+
+ cpu-supervisor@51 {
+ compatible = "dallas,ds4510";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,at24c128b";
+ reg = <0x54>;
+ };
+
+ rtc@68 {
+ compatible = "stm,m41t00",
+ "dallas,ds1338";
+ reg = <0x68>;
+ };
+
+ pcie-switch@70 {
+ compatible = "plx,pex8518";
+ reg = <0x70>;
+ };
+
+ gpio1: gpio@18 {
+ compatible = "nxp,pca9557";
+ reg = <0x18>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio2: gpio@1c {
+ compatible = "nxp,pca9557";
+ reg = <0x1c>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio3: gpio@1e {
+ compatible = "nxp,pca9557";
+ reg = <0x1e>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio4: gpio@1f {
+ compatible = "nxp,pca9557";
+ reg = <0x1f>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ /* eTSEC 1 */
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x1>;
+ };
+ phy1: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x2>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC 2 */
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* UART0 */
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ /* UART1 */
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8572-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ msi@41600 {
+ compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ gpio0: gpio@f000 {
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x1000>;
+ interrupts = <47 2>;
+ interrupt-parent = <&mpic>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ label = "Heartbeat";
+ gpios = <&gpio0 4 1>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ yellow {
+ label = "Yellow";
+ gpios = <&gpio0 5 1>;
+ };
+
+ red {
+ label = "Red";
+ gpios = <&gpio0 6 1>;
+ };
+
+ green {
+ label = "Green";
+ gpios = <&gpio0 7 1>;
+ };
+ };
+
+ /* PME (pattern-matcher) */
+ pme@10000 {
+ compatible = "fsl,mpc8572-pme", "pme8572";
+ reg = <0x10000 0x5000>;
+ interrupts = <57 2 64 2 65 2 66 2 67 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ tlu@2f000 {
+ compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+ reg = <0x2f000 0x1000>;
+ interupts = <61 2 >;
+ interrupt-parent = <&mpic>;
+ };
+
+ tlu@15000 {
+ compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+ reg = <0x15000 0x1000>;
+ interupts = <75 2>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+
+ /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
+ pci0: pcie@ef008000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xef008000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xe9000000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0xe0000000
+ 0x02000000 0x0 0xe0000000
+ 0x0 0x10000000
+
+ 0x01000000 0x0 0x0
+ 0x01000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ /* PCI Express controller 2, PMC module via PEX8112 bridge */
+ pci1: pcie@ef009000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xef009000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
+ 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
+ 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
+ >;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ /* PCI Express controller 1, XMC P15 */
+ pci2: pcie@ef00a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xef00a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
+ 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x40000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts
new file mode 100644
index 0000000..7a8a4af
--- /dev/null
+++ b/arch/powerpc/boot/dts/xpedite5370.dts
@@ -0,0 +1,638 @@
+/*
+ * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
+ * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
+ *
+ * XPedite5370 3U VPX single-board computer based on MPC8572E
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/ {
+ model = "xes,xpedite5370";
+ compatible = "xes,xpedite5370", "xes,MPC8572";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8572@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,8572@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
+ };
+
+ localbus@ef005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xef005000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+ /* Local bus region mappings */
+ ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
+ 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
+ 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
+ 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
+
+ nor-boot@0,0 {
+ compatible = "amd,s29gl01gp", "cfi-flash";
+ bank-width = <2>;
+ reg = <0 0 0x8000000>; /* 128MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Primary user space";
+ reg = <0x00000000 0x6f00000>; /* 111 MB */
+ };
+ partition@6f00000 {
+ label = "Primary kernel";
+ reg = <0x6f00000 0x1000000>; /* 16 MB */
+ };
+ partition@7f00000 {
+ label = "Primary DTB";
+ reg = <0x7f00000 0x40000>; /* 256 KB */
+ };
+ partition@7f40000 {
+ label = "Primary U-Boot environment";
+ reg = <0x7f40000 0x40000>; /* 256 KB */
+ };
+ partition@7f80000 {
+ label = "Primary U-Boot";
+ reg = <0x7f80000 0x80000>; /* 512 KB */
+ read-only;
+ };
+ };
+
+ nor-alternate@1,0 {
+ compatible = "amd,s29gl01gp", "cfi-flash";
+ bank-width = <2>;
+ //reg = <0xf0000000 0x08000000>; /* 128MB */
+ reg = <1 0 0x8000000>; /* 128MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "Secondary user space";
+ reg = <0x00000000 0x6f00000>; /* 111 MB */
+ };
+ partition@6f00000 {
+ label = "Secondary kernel";
+ reg = <0x6f00000 0x1000000>; /* 16 MB */
+ };
+ partition@7f00000 {
+ label = "Secondary DTB";
+ reg = <0x7f00000 0x40000>; /* 256 KB */
+ };
+ partition@7f40000 {
+ label = "Secondary U-Boot environment";
+ reg = <0x7f40000 0x40000>; /* 256 KB */
+ };
+ partition@7f80000 {
+ label = "Secondary U-Boot";
+ reg = <0x7f80000 0x80000>; /* 512 KB */
+ read-only;
+ };
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * Actual part could be ST Micro NAND08GW3B2A (1 GB),
+ * Micron MT29F8G08DAA (2x 512 MB), or Micron
+ * MT29F16G08FAA (2x 1 GB), depending on the build
+ * configuration
+ */
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <2 0 0x40000>;
+ /* U-Boot should fix this up if chip size > 1 GB */
+ partition@0 {
+ label = "NAND Filesystem";
+ reg = <0 0x40000000>;
+ };
+ };
+
+ };
+
+ soc8572@ef000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8572-immr", "simple-bus";
+ ranges = <0x0 0 0xef000000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ memory-controller@6000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x6000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,mpc8572-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x100000>; // L2, 1M
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ temp-sensor@48 {
+ compatible = "dallas,ds1631", "dallas,ds1621";
+ reg = <0x48>;
+ };
+
+ temp-sensor@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+
+ cpu-supervisor@51 {
+ compatible = "dallas,ds4510";
+ reg = <0x51>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,at24c128b";
+ reg = <0x54>;
+ };
+
+ rtc@68 {
+ compatible = "stm,m41t00",
+ "dallas,ds1338";
+ reg = <0x68>;
+ };
+
+ pcie-switch@70 {
+ compatible = "plx,pex8518";
+ reg = <0x70>;
+ };
+
+ gpio1: gpio@18 {
+ compatible = "nxp,pca9557";
+ reg = <0x18>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio2: gpio@1c {
+ compatible = "nxp,pca9557";
+ reg = <0x1c>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio3: gpio@1e {
+ compatible = "nxp,pca9557";
+ reg = <0x1e>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+
+ gpio4: gpio@1f {
+ compatible = "nxp,pca9557";
+ reg = <0x1f>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ polarity = <0x00>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ /* eTSEC 1 */
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x1>;
+ };
+ phy1: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <8 1>;
+ reg = <0x2>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* eTSEC 2 */
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ /* UART0 */
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ /* UART1 */
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8572-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ msi@41600 {
+ compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ gpio0: gpio@f000 {
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x1000>;
+ interrupts = <47 2>;
+ interrupt-parent = <&mpic>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ label = "Heartbeat";
+ gpios = <&gpio0 4 1>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ yellow {
+ label = "Yellow";
+ gpios = <&gpio0 5 1>;
+ };
+
+ red {
+ label = "Red";
+ gpios = <&gpio0 6 1>;
+ };
+
+ green {
+ label = "Green";
+ gpios = <&gpio0 7 1>;
+ };
+ };
+
+ /* PME (pattern-matcher) */
+ pme@10000 {
+ compatible = "fsl,mpc8572-pme", "pme8572";
+ reg = <0x10000 0x5000>;
+ interrupts = <57 2 64 2 65 2 66 2 67 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ tlu@2f000 {
+ compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+ reg = <0x2f000 0x1000>;
+ interupts = <61 2 >;
+ interrupt-parent = <&mpic>;
+ };
+
+ tlu@15000 {
+ compatible = "fsl,mpc8572-tlu", "fsl_tlu";
+ reg = <0x15000 0x1000>;
+ interupts = <75 2>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+
+ /*
+ * PCI Express controller 3 @ ef008000 is not used.
+ * This would have been pci0 on other mpc85xx platforms.
+ */
+
+ /* PCI Express controller 2, wired to VPX P1,P2 backplane */
+ pci1: pcie@ef009000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xef009000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
+ 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
+ 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
+ >;
+ pcie@0 {
+ reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ /* PCI Express controller 1, wired to PEX8518 PCIe switch */
+ pci2: pcie@ef00a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xef00a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
+ 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x40000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
--
1.6.0.4
^ permalink raw reply related
* [PATCH -next 4/4] powerpc/bootwrapper: Custom build options for XPedite52xx targets
From: Nate Case @ 2009-06-11 19:43 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Nate Case, David Gibson
In-Reply-To: <1244749381-17429-4-git-send-email-ncase@xes-inc.com>
Some XPedite52xx boards have a legacy boot loader requiring some special
care in the boot wrapper. The use of cuboot-85xx is needed to fix
up embedded device trees, and a custom link address is specified to
accommodate the boot loader and larger kernel image sizes used on X-ES
MPC85xx platforms.
Signed-off-by: Nate Case <ncase@xes-inc.com>
---
arch/powerpc/boot/wrapper | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 3ac75ae..4db487d 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -225,6 +225,10 @@ asp834x-redboot)
platformo="$object/fixed-head.o $object/redboot-83xx.o"
binary=y
;;
+xpedite52*)
+ link_address='0x1400000'
+ platformo=$object/cuboot-85xx.o
+ ;;
esac
vmz="$tmpdir/`basename \"$kernel\"`.$ext"
--
1.6.0.4
^ permalink raw reply related
* [PATCH -next 1/4] powerpc/85xx: Add platform support for X-ES MPC85xx boards
From: Nate Case @ 2009-06-11 19:42 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Nate Case, David Gibson
In-Reply-To: <1244749381-17429-1-git-send-email-ncase@xes-inc.com>
Add support for X-ES single-board computers based on the Freescale
MPC85xx processors.
Signed-off-by: Nate Case <ncase@xes-inc.com>
---
arch/powerpc/platforms/85xx/Kconfig | 10 +
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/xes_mpc85xx.c | 282 +++++++++++++++++++++++++++++
3 files changed, 293 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/85xx/xes_mpc85xx.c
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 43d385c..e0d39bf 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -64,6 +64,16 @@ config KSI8560
help
This option enables support for the Emerson KSI8560 board
+config XES_MPC85xx
+ bool "X-ES single-board computer"
+ select DEFAULT_UIMAGE
+ help
+ This option enables support for the various single-board
+ computers from Extreme Engineering Solutions (X-ES) based on
+ Freescale MPC85xx processors.
+ Manufacturer: Extreme Engineering Solutions, Inc.
+ URL: <http://www.xes-inc.com/>
+
config STX_GP3
bool "Silicon Turnkey Express GP3"
help
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index a857b35..835733f 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_SBC8560) += sbc8560.o
obj-$(CONFIG_SBC8548) += sbc8548.o
obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
obj-$(CONFIG_KSI8560) += ksi8560.o
+obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
\ No newline at end of file
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
new file mode 100644
index 0000000..ee01532
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
+ *
+ * X-ES board-specific functionality
+ *
+ * Based on mpc85xx_ds code from Freescale Semiconductor, Inc.
+ *
+ * Author: Nate Case <ncase@xes-inc.com>
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <linux/of_platform.h>
+
+/* A few bit definitions needed for fixups on some boards */
+#define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
+#define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
+#define MPC85xx_L2CTL_L2SIZ_MASK 0x30000000 /* L2 SRAM size (R/O) */
+
+void __init xes_mpc85xx_pic_init(void)
+{
+ struct mpic *mpic;
+ struct resource r;
+ struct device_node *np;
+
+ np = of_find_node_by_type(NULL, "open-pic");
+ if (np == NULL) {
+ printk(KERN_ERR "Could not find open-pic node\n");
+ return;
+ }
+
+ if (of_address_to_resource(np, 0, &r)) {
+ printk(KERN_ERR "Failed to map mpic register space\n");
+ of_node_put(np);
+ return;
+ }
+
+ mpic = mpic_alloc(np, r.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET |
+ MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+ 0, 256, " OpenPIC ");
+ BUG_ON(mpic == NULL);
+ of_node_put(np);
+
+ mpic_init(mpic);
+}
+
+static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
+{
+ volatile uint32_t ctl, tmp;
+
+ asm volatile("msync; isync");
+ tmp = in_be32(l2_base);
+
+ /*
+ * xMon may have enabled part of L2 as SRAM, so we need to set it
+ * up for all cache mode just to be safe.
+ */
+ printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
+
+ ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
+ if (machine_is_compatible("MPC8540") ||
+ machine_is_compatible("MPC8560"))
+ /*
+ * Assume L2 SRAM is used fully for cache, so set
+ * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
+ */
+ ctl |= (tmp & MPC85xx_L2CTL_L2SIZ_MASK) >> 2;
+
+ asm volatile("msync; isync");
+ out_be32(l2_base, ctl);
+ asm volatile("msync; isync");
+}
+
+static void xes_mpc85xx_fixups(void)
+{
+ struct device_node *np;
+ int err;
+
+ /*
+ * Legacy xMon firmware on some X-ES boards does not enable L2
+ * as cache. We must ensure that they get enabled here.
+ */
+ for_each_node_by_name(np, "l2-cache-controller") {
+ struct resource r[2];
+ void __iomem *l2_base;
+
+ /* Only MPC8548, MPC8540, and MPC8560 boards are affected */
+ if (!of_device_is_compatible(np,
+ "fsl,mpc8548-l2-cache-controller") &&
+ !of_device_is_compatible(np,
+ "fsl,mpc8540-l2-cache-controller") &&
+ !of_device_is_compatible(np,
+ "fsl,mpc8560-l2-cache-controller"))
+ continue;
+
+ err = of_address_to_resource(np, 0, &r[0]);
+ if (err) {
+ printk(KERN_WARNING "xes_mpc85xx: Could not get "
+ "resource for device tree node '%s'",
+ np->full_name);
+ continue;
+ }
+
+ l2_base = ioremap(r[0].start, r[0].end - r[0].start + 1);
+
+ xes_mpc85xx_configure_l2(l2_base);
+ }
+}
+
+#ifdef CONFIG_PCI
+static int primary_phb_addr;
+#endif
+
+/*
+ * Setup the architecture
+ */
+#ifdef CONFIG_SMP
+extern void __init mpc85xx_smp_init(void);
+#endif
+static void __init xes_mpc85xx_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+ struct device_node *root;
+ const char *model = "Unknown";
+
+ root = of_find_node_by_path("/");
+ if (root == NULL)
+ return;
+
+ model = of_get_property(root, "model", NULL);
+
+ printk(KERN_INFO "X-ES MPC85xx-based single-board computer: %s\n",
+ model + strlen("xes,"));
+
+ xes_mpc85xx_fixups();
+
+#ifdef CONFIG_PCI
+ for_each_node_by_type(np, "pci") {
+ if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+ of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == primary_phb_addr)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+ }
+ }
+#endif
+
+#ifdef CONFIG_SMP
+ mpc85xx_smp_init();
+#endif
+}
+
+static struct of_device_id __initdata xes_mpc85xx_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ { .compatible = "simple-bus", },
+ { .compatible = "gianfar", },
+ {},
+};
+
+static int __init xes_mpc85xx_publish_devices(void)
+{
+ return of_platform_bus_probe(NULL, xes_mpc85xx_ids, NULL);
+}
+machine_device_initcall(xes_mpc8572, xes_mpc85xx_publish_devices);
+machine_device_initcall(xes_mpc8548, xes_mpc85xx_publish_devices);
+machine_device_initcall(xes_mpc8540, xes_mpc85xx_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init xes_mpc8572_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "xes,MPC8572")) {
+#ifdef CONFIG_PCI
+ primary_phb_addr = 0x8000;
+#endif
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static int __init xes_mpc8548_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "xes,MPC8548")) {
+#ifdef CONFIG_PCI
+ primary_phb_addr = 0xb000;
+#endif
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+static int __init xes_mpc8540_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "xes,MPC8540")) {
+#ifdef CONFIG_PCI
+ primary_phb_addr = 0xb000;
+#endif
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+define_machine(xes_mpc8572) {
+ .name = "X-ES MPC8572",
+ .probe = xes_mpc8572_probe,
+ .setup_arch = xes_mpc85xx_setup_arch,
+ .init_IRQ = xes_mpc85xx_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
+
+define_machine(xes_mpc8548) {
+ .name = "X-ES MPC8548",
+ .probe = xes_mpc8548_probe,
+ .setup_arch = xes_mpc85xx_setup_arch,
+ .init_IRQ = xes_mpc85xx_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
+
+define_machine(xes_mpc8540) {
+ .name = "X-ES MPC8540",
+ .probe = xes_mpc8540_probe,
+ .setup_arch = xes_mpc85xx_setup_arch,
+ .init_IRQ = xes_mpc85xx_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.6.0.4
^ permalink raw reply related
* [PATCH v3 -next 0/0] powerpc/85xx: Support for X-ES MPC85xx boards
From: Nate Case @ 2009-06-11 19:42 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Nate Case, David Gibson
Hello,
This is v3 of the "Add support for X-ES MPC85xx boards" patch submitted
earlier. This time it's split up as Kumar requested:
[1/4] powerpc/85xx: Add platform support for X-ES MPC85xx boards
[2/4] powerpc/85xx: Add dts files for X-ES MPC85xx boards
[3/4] powerpc/85xx: Add defconfig for X-ES MPC85xx boards
[4/4] powerpc/bootwrapper: Custom build options for XPedite52xx targets
This shouldn't be too invasive since the bulk of the changes are new
files. This version should address the items brought up by Kumar and
David Gibson.
--
Nate Case <ncase@xes-inc.com>
^ permalink raw reply
* Re: SD card over (xilinx_)SPI, timeout error while CID
From: Ricardo Ribalda Delgado @ 2009-06-11 19:15 UTC (permalink / raw)
To: Joachim Foerster
Cc: joachim, dbrownell, hp, lorenz, linuxppc-dev, mike, pierre,
jan.nikitenko, john.linn, linuxkernel
In-Reply-To: <1244568361.25223.16.camel@localhost>
Hello,
It seems that I am facing the same problem!. I attach another trace
that also shows the sd I/O.
I have also commented out the dma line at probe and no better results....
As you point, the card is unable to reply the cid. But not only
that, after that failure the card replyies allways FF!!! So it seems
that after that command the card is "dead"
I have tried with spi modes 3 and 0, having the same results.
Best regards
[ 48.539108] irq: irq 16 on host
/plb@0/interrupt-controller@87000000 mapped to virtual irq 27
[ 48.570049] xilinx-xps-spi 8a000000.xps-spi: at 0x8A000000 mapped
to 0xD93A0000, irq=27
[ 48.600625] Xilinx SPI: change mode 0, 0 bits/w, 0 cs_high
[ 48.622642] Xilins SPI: cs off
[ 48.853914] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 48.875780] Xilins SPI: cs off
[ 48.895013] mmc_spi spi1.0: ASSUMING SPI bus stays unshared!
[ 48.921849] mmc0: clock 0Hz busmode 0 powermode 0 cs 0 Vdd 0 width 0 timing 0
[ 48.945429] mmc0: clock 0Hz busmode 2 powermode 1 cs 1 Vdd 21 width
0 timing 0
[ 48.968949] mmc_spi spi1.0: mmc_spi: power up (21)
[ 48.990098] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no
poweroff, cd polling
[ 49.014178] mmc0: clock 400000Hz busmode 2 powermode 2 cs 1 Vdd 21
width 0 timing 0
[ 49.038579] mmc_spi spi1.0: mmc_spi: power on (21)
[ 49.059543] Xilinx SPI: cs on
[ 49.078528] Spi Transfer at 0x8A000000
[ 49.098000] Sending 29 bytes
[ 49.099687] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 49.119458] roff ff ff ff ff ff ff ff ff ff ff ff ff
[ 49.161376] Received 29 bytes
[ 49.163329] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 49.183066] ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 49.218076] Xilinx SPI: cs on
[ 49.235595] Spi Transfer at 0x8A000000
[ 49.254150] Sending 10 bytes
[ 49.255804] ff ff ff ff ff ff ff ff ff ff
[ 49.289548] Received 10 bytes
[ 49.291330] ff ff ff ff ff ff ff ff ff ff
[ 49.324085] Xilinx SPI: change mode 7, 8 bits/w, 4 cs_high
[ 49.343351] Xilins SPI: cs off
[ 49.359698] Xilinx SPI: cs on
[ 49.375759] Spi Transfer at 0x8A000000
[ 49.392781] Sending 18 bytes
[ 49.394467] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 49.412181] ff ff
[ 49.441053] Received 18 bytes
[ 49.442834] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 49.460487] ff ff
[ 49.489213] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 49.507989] Xilins SPI: cs off
[ 49.524119] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 49.542881] Xilins SPI: cs off
[ 49.558995] mmc_spi spi1.0: mmc_spi: clock to 400000 Hz, 0
[ 49.592549] mmc0: starting CMD0 arg 00000000 flags 000000c0
[ 49.611249] mmc_spi spi1.0: mmc_spi: CMD0, resp R1
[ 49.629037] Xilinx SPI: cs on
[ 49.644017] Spi Transfer at 0x8A000000
[ 49.660436] Sending 17 bytes
[ 49.662539] ff 40 00 00 00 00 95 ff ff ff ff ff ff ff ff ff
[ 49.679625] ff
[ 49.706964] Received 17 bytes
[ 49.709175] ff ff ff ff ff ff ff ff 01 ff ff ff ff ff ff ff
[ 49.725994] ff
[ 49.752770] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 49.770409] Xilins SPI: cs off
[ 49.785069] mmc0: req done (CMD0): 0: 00000001 00000000 00000000 00000000
[ 49.804839] mmc0: starting CMD8 arg 000001aa flags 000002f5
[ 49.822469] mmc_spi spi1.0: mmc_spi: CMD8, resp R3/R4/R7
[ 49.839895] Xilinx SPI: cs on
[ 49.854839] Spi Transfer at 0x8A000000
[ 49.870638] Sending 21 bytes
[ 49.872294] ff 48 00 00 01 aa 87 ff ff ff ff ff ff ff ff ff
[ 49.889218] ff ff ff ff ff
[ 49.916288] Received 21 bytes
[ 49.918498] ff ff ff ff ff ff ff ff 01 00 00 01 aa ff ff ff
[ 49.935246] ff ff ff ff ff
[ 49.962416] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 49.980219] Xilins SPI: cs off
[ 49.995410] mmc0: req done (CMD8): 0: 00000001 000001aa 00000000 00000000
[ 50.014912] mmc0: starting CMD5 arg 00000000 flags 000002e1
[ 50.033278] mmc_spi spi1.0: mmc_spi: CMD5, resp R3/R4/R7
[ 50.051561] Xilinx SPI: cs on
[ 50.067193] Spi Transfer at 0x8A000000
[ 50.083948] Sending 21 bytes
[ 50.086041] ff 45 00 00 00 00 5b ff ff ff ff ff ff ff ff ff
[ 50.103588] ff ff ff ff ff
[ 50.132604] Received 21 bytes
[ 50.134387] ff ff ff ff ff ff ff ff 05 ff ff ff ff ff ff ff
[ 50.151844] ff ff ff ff ff
[ 50.180735] mmc_spi spi1.0: ... CMD5 response SPI_R3/R4/R: resp
0005 ffffffff
[ 50.201467] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 50.220507] Xilins SPI: cs off
[ 50.236890] mmc0: req done (CMD5): -22: 00000005 ffffffff 00000000 00000000
[ 50.257701] mmc0: starting CMD55 arg 00000000 flags 000000f5
[ 50.277204] mmc_spi spi1.0: mmc_spi: CMD55, resp R1
[ 50.296051] Xilinx SPI: cs on
[ 50.312639] Spi Transfer at 0x8A000000
[ 50.330024] Sending 17 bytes
[ 50.331710] ff 77 00 00 00 00 65 ff ff ff ff ff ff ff ff ff
[ 50.349786] ff
[ 50.379487] Received 17 bytes
[ 50.381697] ff ff ff ff ff ff ff ff 01 ff ff ff ff ff ff ff
[ 50.399768] ff
[ 50.429230] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 50.448429] Xilins SPI: cs off
[ 50.465013] mmc0: req done (CMD55): 0: 00000001 00000000 00000000 00000000
[ 50.485866] mmc0: starting CMD41 arg 00000000 flags 000000e1
[ 50.505616] mmc_spi spi1.0: mmc_spi: CMD41, resp R1
[ 50.524494] Xilinx SPI: cs on
[ 50.541042] Spi Transfer at 0x8A000000
[ 50.558421] Sending 17 bytes
[ 50.560106] ff 69 00 00 00 00 e5 ff ff ff ff ff ff ff ff ff
[ 50.578141] ff
[ 50.607645] Received 17 bytes
[ 50.609850] ff ff ff ff ff ff ff ff 01 ff ff ff ff ff ff ff
[ 50.627891] ff
[ 50.657292] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 50.676490] Xilins SPI: cs off
[ 50.693073] mmc0: req done (CMD41): 0: 00000001 00000000 00000000 00000000
[ 50.713950] mmc0: starting CMD0 arg 00000000 flags 000000c0
[ 50.733526] mmc_spi spi1.0: mmc_spi: CMD0, resp R1
[ 50.752333] Xilinx SPI: cs on
[ 50.768877] Spi Transfer at 0x8A000000
[ 50.786234] Sending 17 bytes
[ 50.787927] ff 40 00 00 00 00 95 ff ff ff ff ff ff ff ff ff
[ 50.805943] ff
[ 50.835559] Received 17 bytes
[ 50.837768] ff ff ff ff ff ff ff ff 00 ff ff ff ff ff ff ff
[ 50.855765] ff
[ 50.885197] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 50.904434] Xilins SPI: cs off
[ 50.921092] mmc0: req done (CMD0): 0: 00000000 00000000 00000000 00000000
[ 50.942690] mmc0: starting CMD58 arg 00000000 flags 00000280
[ 50.961863] mmc_spi spi1.0: mmc_spi: CMD58, resp R3/R4/R7
[ 50.981057] Xilinx SPI: cs on
[ 50.997358] Spi Transfer at 0x8A000000
[ 51.014356] Sending 21 bytes
[ 51.016048] ff 7a 00 00 00 00 fd ff ff ff ff ff ff ff ff ff
[ 51.033727] ff ff ff ff ff
[ 51.063147] Received 21 bytes
[ 51.065361] ff ff ff ff ff ff ff ff 00 00 7f 80 00 7f ff ff
[ 51.082985] ff ff ff ff ff
[ 51.111831] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 51.130578] Xilins SPI: cs off
[ 51.146636] mmc0: req done (CMD58): 0: 00000000 007f8000 00000000 00000000
[ 51.167049] mmc0: clock 400000Hz busmode 2 powermode 2 cs 1 Vdd 20
width 0 timing 0
[ 51.188667] mmc0: starting CMD0 arg 00000000 flags 000000c0
[ 51.208074] mmc_spi spi1.0: mmc_spi: CMD0, resp R1
[ 51.226728] Xilinx SPI: cs on
[ 51.243154] Spi Transfer at 0x8A000000
[ 51.260387] Sending 17 bytes
[ 51.262487] ff 40 00 00 00 00 95 ff ff ff ff ff ff ff ff ff
[ 51.280453] ff
[ 51.309719] Received 17 bytes
[ 51.311501] ff ff ff ff ff ff ff ff 00 ff ff ff ff ff ff ff
[ 51.329336] ff
[ 51.358446] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 51.377485] Xilins SPI: cs off
[ 51.393875] mmc0: req done (CMD0): 0: 00000000 00000000 00000000 00000000
[ 51.415465] mmc0: starting CMD8 arg 000001aa flags 000002f5
[ 51.434899] mmc_spi spi1.0: mmc_spi: CMD8, resp R3/R4/R7
[ 51.454224] Xilinx SPI: cs on
[ 51.470813] Spi Transfer at 0x8A000000
[ 51.488233] Sending 21 bytes
[ 51.490336] ff 48 00 00 01 aa 87 ff ff ff ff ff ff ff ff ff
[ 51.508496] ff ff ff ff ff
[ 51.538541] Received 21 bytes
[ 51.540323] ff ff ff ff ff ff ff ff 00 00 00 00 80 7f ff ff
[ 51.558375] ff ff ff ff ff
[ 51.588247] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 51.607401] Xilins SPI: cs off
[ 51.623861] mmc0: req done (CMD8): 0: 00000000 00000080 00000000 00000000
[ 51.644516] mmc0: starting CMD55 arg 00000000 flags 000000f5
[ 51.664028] mmc_spi spi1.0: mmc_spi: CMD55, resp R1
[ 51.682831] Xilinx SPI: cs on
[ 51.699284] Spi Transfer at 0x8A000000
[ 51.716597] Sending 17 bytes
[ 51.718281] ff 77 00 00 00 00 65 ff ff ff ff ff ff ff ff ff
[ 51.736204] ff
[ 51.765505] Received 17 bytes
[ 51.767288] ff ff ff ff ff ff ff ff 00 ff ff ff ff ff ff ff
[ 51.785197] ff
[ 51.814313] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 51.833614] Xilins SPI: cs off
[ 51.850111] mmc0: req done (CMD55): 0: 00000000 00000000 00000000 00000000
[ 51.870983] mmc0: starting CMD41 arg 00000000 flags 000000e1
[ 51.890595] mmc_spi spi1.0: mmc_spi: CMD41, resp R1
[ 51.909383] Xilinx SPI: cs on
[ 51.925698] Spi Transfer at 0x8A000000
[ 51.942753] Sending 17 bytes
[ 51.944443] ff 69 00 00 00 00 e5 ff ff ff ff ff ff ff ff ff
[ 51.962122] ff
[ 51.990760] Received 17 bytes
[ 51.992969] ff ff ff ff ff ff ff ff 00 ff ff ff ff ff ff ff
[ 52.010627] ff
[ 52.039135] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 52.057943] Xilins SPI: cs off
[ 52.074081] mmc0: req done (CMD41): 0: 00000000 00000000 00000000 00000000
[ 52.094569] mmc0: starting CMD10 arg 00000000 flags 000000b5
[ 52.113755] mmc0: blksz 16 blocks 1 flags 00000200 tsac 0 ms nsac 64
[ 52.134240] mmc_spi spi1.0: mmc_spi: CMD10, resp R1
[ 52.152922] Xilinx SPI: cs on
[ 52.169228] Spi Transfer at 0x8A000000
[ 52.186386] Sending 9 bytes
[ 52.187978] ff 4a 00 00 00 00 1b ff ff
[ 52.218225] Received 9 bytes
[ 52.219911] ff ff ff ff ff ff ff ff 00
[ 52.249970] mmc_spi spi1.0: mmc_spi: read block, 16 bytes
[ 52.269009] Xilinx SPI: cs on
[ 52.285210] Spi Transfer at 0x8A000000
[ 52.302276] Sending 1 bytes
[ 52.303867] ff
[ 52.332598] Received 1 bytes
[ 52.334287] ff
[ 52.362345] Xilinx SPI: cs on
[ 52.377675] Spi Transfer at 0x8A000000
[ 52.393815] Sending 1 bytes
[ 52.395408] ff
[ 52.422215] Received 1 bytes
[ 52.423901] ff
[ 52.450210] mmc_spi spi1.0: read error ffffff92 (-110)
[ 52.467376] mmc_spi spi1.0: read status -110
[ 52.483642] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 52.501298] Xilins SPI: cs off
[ 52.516304] mmc0: req done (CMD10): 0: 00000000 00000000 00000000 00000000
[ 52.535655] mmc0: 0 bytes transferred: -110
[ 52.552762] mmc0: clock 0Hz busmode 2 powermode 0 cs 1 Vdd 0 width 0 timing 0
[ 52.572513] mmc_spi spi1.0: mmc_spi: power off (0)
[ 52.589792] mmc0: error -110 whilst initialising SD card
[ 52.607573] mmc0: clock 0Hz busmode 2 powermode 0 cs 1 Vdd 0 width 0 timing 0
[ 53.624548] mmc0: clock 0Hz busmode 2 powermode 1 cs 1 Vdd 21 width
0 timing 0
[ 53.644565] mmc_spi spi1.0: mmc_spi: power up (21)
[ 53.676546] mmc0: clock 400000Hz busmode 2 powermode 2 cs 1 Vdd 21
width 0 timing 0
[ 53.697303] mmc_spi spi1.0: mmc_spi: power on (21)
[ 53.715149] Xilinx SPI: cs on
[ 53.730775] Spi Transfer at 0x8A000000
[ 53.747808] Sending 29 bytes
[ 53.749948] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 53.767622] ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 53.798870] Received 29 bytes
[ 53.801072] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 53.818374] ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 53.848277] Xilinx SPI: cs on
[ 53.863238] Spi Transfer at 0x8A000000
[ 53.879061] Sending 10 bytes
[ 53.881166] ff ff ff ff ff ff ff ff ff ff
[ 53.909364] Received 10 bytes
[ 53.911147] ff ff ff ff ff ff ff ff ff ff
[ 53.939310] Xilinx SPI: change mode 7, 8 bits/w, 4 cs_high
[ 53.957098] Xilins SPI: cs off
[ 53.972202] Xilinx SPI: cs on
[ 53.986965] Spi Transfer at 0x8A000000
[ 54.002665] Sending 18 bytes
[ 54.004355] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 54.021148] ff ff
[ 54.047531] Received 18 bytes
[ 54.049733] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 54.066437] ff ff
[ 54.093333] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 54.111278] Xilins SPI: cs off
[ 54.140548] mmc0: starting CMD0 arg 00000000 flags 000000c0
[ 54.158933] mmc_spi spi1.0: mmc_spi: CMD0, resp R1
[ 54.176873] Xilinx SPI: cs on
[ 54.192659] Spi Transfer at 0x8A000000
[ 54.209382] Sending 17 bytes
[ 54.211069] ff 40 00 00 00 00 95 ff ff ff ff ff ff ff ff ff
[ 54.228464] ff
[ 54.256364] Received 17 bytes
[ 54.258571] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 54.275654] ff
[ 54.302586] Xilinx SPI: cs on
[ 54.317336] Spi Transfer at 0x8A000000
[ 54.332830] Sending 1 bytes
[ 54.334422] ff
[ 54.359834] Received 1 bytes
[ 54.361977] ff
[ 54.386246] Xilinx SPI: cs on
[ 54.399699] Spi Transfer at 0x8A000000
[ 54.414165] Sending 1 bytes
[ 54.415758] ff
[ 54.439100] Received 1 bytes
[ 54.441213] ff
[ 54.464491] Xilinx SPI: cs on
[ 54.477571] Spi Transfer at 0x8A000000
[ 54.491746] Sending 1 bytes
[ 54.493754] ff
[ 54.516871] Received 1 bytes
[ 54.518557] ff
[ 54.541114] Xilinx SPI: cs on
[ 54.554112] Spi Transfer at 0x8A000000
[ 54.568070] Sending 1 bytes
[ 54.570080] ff
[ 54.592080] Received 1 bytes
[ 54.594181] ff
[ 54.616269] Xilinx SPI: cs on
[ 54.628831] Spi Transfer at 0x8A000000
[ 54.642295] Sending 1 bytes
[ 54.643890] ff
[ 54.665424] Received 1 bytes
[ 54.667113] ff
[ 54.688185] Xilinx SPI: cs on
[ 54.700264] Spi Transfer at 0x8A000000
[ 54.713168] Sending 1 bytes
[ 54.714763] ff
[ 54.734877] Received 1 bytes
[ 54.736982] ff
[ 54.756293] Xilinx SPI: cs on
[ 54.767659] Spi Transfer at 0x8A000000
[ 54.779759] Sending 1 bytes
[ 54.781760] ff
[ 54.800685] Received 1 bytes
[ 54.802373] ff
[ 54.820845] Xilinx SPI: cs on
[ 54.831765] Spi Transfer at 0x8A000000
[ 54.843523] Sending 1 bytes
[ 54.845534] ff
[ 54.863879] Received 1 bytes
[ 54.865974] ff
[ 54.884263] Xilinx SPI: cs on
[ 54.895068] Spi Transfer at 0x8A000000
[ 54.906798] Sending 1 bytes
[ 54.908395] ff
[ 54.926629] Received 1 bytes
[ 54.928318] ff
[ 54.946533] Xilinx SPI: cs on
[ 54.957309] Spi Transfer at 0x8A000000
[ 54.969152] Sending 1 bytes
[ 54.970749] ff
[ 54.988934] Received 1 bytes
[ 54.990621] ff
[ 55.008869] Xilinx SPI: cs on
[ 55.019781] Spi Transfer at 0x8A000000
[ 55.031652] Sending 1 bytes
[ 55.033656] ff
[ 55.052030] Received 1 bytes
[ 55.054132] ff
[ 55.072395] Xilinx SPI: cs on
[ 55.083339] Spi Transfer at 0x8A000000
[ 55.095103] Sending 1 bytes
[ 55.097114] ff
[ 55.115411] Received 1 bytes
[ 55.117515] ff
[ 55.135872] Xilinx SPI: cs on
[ 55.146757] Spi Transfer at 0x8A000000
[ 55.158515] Sending 1 bytes
[ 55.160113] ff
[ 55.178455] Received 1 bytes
[ 55.180147] ff
[ 55.198506] Xilinx SPI: cs on
[ 55.209369] Spi Transfer at 0x8A000000
[ 55.221281] Sending 1 bytes
[ 55.222873] ff
[ 55.241289] Received 1 bytes
[ 55.242978] ff
[ 55.261376] Xilinx SPI: change mode 3, 8 bits/w, 0 cs_high
[ 55.274774] Xilins SPI: cs off
[ 55.286183] mmc0: req done (CMD0): -110: 00000000 00000000 00000000 00000000
[ 55.303059] mmc0: starting CMD8 arg 000001aa flags 000002f5
[ 55.317605] mmc_spi spi1.0: mmc_spi: CMD8, resp R3/R4/R7
[ 55.332234] Xilinx SPI: cs on
[ 55.344288] Spi Transfer at 0x8A000000
[ 55.357357] Sending 21 bytes
[ 55.359048] ff 48 00 00 01 aa 87 ff ff ff ff ff ff ff ff ff
[ 55.373268] ff ff ff ff ff
[ 55.395064] Received 21 bytes
[ 55.397272] ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 55.411374] ff ff ff ff ff
[ 55.433854] Xilinx SPI: cs on
[ 55.446394] Spi Transfer at 0x8A000000
[ 55.459800] Sending 1 bytes
[ 55.461818] ff
[ 55.483642] Received 1 bytes
[ 55.485751] ff
[ 55.507455] Xilinx SPI: cs on
[ 55.520004] Spi Transfer at 0x8A000000
[ 55.533515] Sending 1 bytes
[ 55.535105] ff
[ 55.556813] Received 1 bytes
[ 55.558502] ff
[ 55.580275] Xilinx SPI: cs on
[ 55.592791] Spi Transfer at 0x8A000000
[ 55.606171] Sending 1 bytes
[ 55.607768] ff
[ 55.629567] Received 1 bytes
[ 55.631260] ff
[ 55.653122] Xilinx SPI: cs on
[ 55.665601] Spi Transfer at 0x8A000000
[ 55.679005] Sending 1 bytes
[ 55.681015] ff
[ 55.702801] Received 1 bytes
[ 55.704492] ff
[ 55.726140] Xilinx SPI: cs on
[ 55.738660] Spi Transfer at 0x8A000000
[ 55.752158] Sending 1 bytes
[ 55.754162] ff
[ 55.775802] Received 1 bytes
[ 55.777912] ff
[ 55.799564] Xilinx SPI: cs on
[ 55.811801] Spi Transfer at 0x8A000000
[ 55.824923] Sending 1 bytes
[ 55.826514] ff
[ 55.846619] Received 1 bytes
[ 55.848304] ff
[ 55.867579] Xilinx SPI: cs on
[ 55.878762] Spi Transfer at 0x8A000000
[ 55.890810] Sending 1 bytes
[ 55.892404] ff
[ 55.911203] Received 1 bytes
[ 55.913311] ff
[ 55.931740] Xilinx SPI: cs on
[ 55.942575] Spi Transfer at 0x8A000000
[ 55.954480] Sending 1 bytes
[ 55.956073] ff
[ 55.974448] Received 1 bytes
[ 55.976134] ff
[ 55.994486] Xilinx SPI: cs on
[ 56.005406] Spi Transfer at 0x8A000000
[ 56.017305] Sending 1 bytes
[ 56.018894] ff
[ 56.037248] Received 1 bytes
[ 56.038924] ff
[ 56.057282] Xilinx SPI: cs on
--
Ricardo Ribalda
http://www.eps.uam.es/~rribalda/
^ permalink raw reply
* Re: 2.6.30-rc6: Problem with an SSD disk on Freescale PowerPC mpc8315e-rdb, works fine on x86
From: Leon Woestenberg @ 2009-06-11 18:41 UTC (permalink / raw)
To: Linux PPC, Kumar Gala, linux-ide, Ashish Kalra, Li Yang
In-Reply-To: <c384c5ea0906090226t59a2b593neb6c42f3c0d189f7@mail.gmail.com>
Hello,
I found this is a regression compared with an older kernel. I have
tested the same setup with the Freescale LTIB BSP 2008-06-27 BSP
kernel*, keeping the user space and hardware setup exactly identical.
Under that kernel, no errors occur.
Also I found the error only occurs during *reading* the SSD disk under
Linux 2.6.30-rc6, writing seems unaffected.
As the same Freescale SATA controller IP is used in the new 8536E
processor (and others), I would like to help to solve this issue
before trying 8536E hardware.
Regards,
Leon.
*
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=3DMPC8315E&n=
odeId=3D0162468rH3bTdGJk191439&fpsp=3D1&tab=3DDesign_Tools_Tab#
Split out patches available from http://www.bitshrine.org/gpp/
On Tue, Jun 9, 2009 at 11:26 AM, Leon
Woestenberg<leon.woestenberg@gmail.com> wrote:
> Adding the sata_fsl.c developers to the recipients:
>
> On Mon, Jun 8, 2009 at 4:59 PM, Leon
> Woestenberg<leon.woestenberg@gmail.com> wrote:
>> Hello,
>>
>> using 2.6.30-rc6, I get the following problems when I read from a SSD
>> disk, connected to the
>> 3.0 Gb SATA controller of the MPC8315E SoC rev 1.0 running Linux 2.6.30-=
rc6.
>>
>> Below see the output from two dd read runs.
>>
>> The disk behaves fine on a x86 box.
>>
>> What I can do to (help) pin-point the problem?
>>
>> Regards,
>>
>> Leon.
>>
>>
>> root@mpc8315e-rdb:~# dd if=3D/dev/sda of=3D/dev/null bs=3D4k
>> ata2: exception Emask 0x10 SAct 0x0 SErr 0x0 action 0x2 frozen
>> ata2.00: cmd c8/00:3e:1e:e0:01/00:00:00:00:00/e0 tag 0 dma 31744 in
>> =A0 =A0 =A0 =A0 res 50/00:3e:e0:df:01/00:00:00:00:00/e0 Emask 0x1 (devic=
e error)
>> ata2.00: status: { DRDY }
>> ata2: hard resetting link
>> ata2: Signature Update detected @ 3528 msecs
>> ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
>> ata2.00: configured for UDMA/133
>> sd 1:0:0:0: [sda] Result: hostbyte=3D0x00 driverbyte=3D0x08
>> sd 1:0:0:0: [sda] Sense Key : 0xb [current] [descriptor]
>> Descriptor sense data with sense descriptors (in hex):
>> =A0 =A0 =A0 =A072 0b 00 00 00 00 00 0c 00 0a 80 00 00 00 00 00
>> =A0 =A0 =A0 =A000 01 df e0
>> sd 1:0:0:0: [sda] ASC=3D0x0 ASCQ=3D0x0
>> end_request: I/O error, dev sda, sector 122910
>> __ratelimit: 52 callbacks suppressed
>> Buffer I/O error on device sda, logical block 122910
>> Buffer I/O error on device sda, logical block 122911
>> Buffer I/O error on device sda, logical block 122912
>> Buffer I/O error on device sda, logical block 122913
>> Buffer I/O error on device sda, logical block 122914
>> Buffer I/O error on device sda, logical block 122915
>> Buffer I/O error on device sda, logical block 122916
>> Buffer I/O error on device sda, logical block 122917
>> Buffer I/O error on device sda, logical block 122918
>> Buffer I/O error on device sda, logical block 122919
>> ata2: EH complete
>> dd: /dev/sda: Input/output error
>>
>>
>> root@mpc8315e-rdb:~# dd if=3D/dev/sda of=3D/dev/null bs=3D4k
>> ata2: exception Emask 0x10 SAct 0x0 SErr 0x0 action 0x2 frozen
>> ata2.00: cmd c8/00:32:9a:6e:00/00:00:00:00:00/e0 tag 0 dma 25600 in
>> =A0 =A0 =A0 =A0 res 50/00:3e:5c:6e:00/00:00:00:00:00/e0 Emask 0x1 (devic=
e error)
>> ata2.00: status: { DRDY }
>> ata2: hard resetting link
>> ata2: Signature Update detected @ 3528 msecs
>> ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
>> ata2.00: configured for UDMA/133
>> sd 1:0:0:0: [sda] Result: hostbyte=3D0x00 driverbyte=3D0x08
>> sd 1:0:0:0: [sda] Sense Key : 0xb [current] [descriptor]
>> Descriptor sense data with sense descriptors (in hex):
>> =A0 =A0 =A0 =A072 0b 00 00 00 00 00 0c 00 0a 80 00 00 00 00 00
>> =A0 =A0 =A0 =A000 00 6e 5c
>> sd 1:0:0:0: [sda] ASC=3D0x0 ASCQ=3D0x0
>> end_request: I/O error, dev sda, sector 28314
>> __ratelimit: 52 callbacks suppressed
>> Buffer I/O error on device sda, logical block 28314
>> Buffer I/O error on device sda, logical block 28315
>> Buffer I/O error on device sda, logical block 28316
>> Buffer I/O error on device sda, logical block 28317
>> Buffer I/O error on device sda, logical block 28318
>> Buffer I/O error on device sda, logical block 28319
>> Buffer I/O error on device sda, logical block 28320
>> Buffer I/O error on device sda, logical block 28321
>> Buffer I/O error on device sda, logical block 28322
>> Buffer I/O error on device sda, logical block 28323
>> ata2: EH complete
>> dd: /dev/sda: Input/output error
>>
>>
>> root@mpc8315e-rdb:~# uname -a
>> Linux mpc8315e-rdb 2.6.30-rc6 #1 Mon Jun 8 15:54:00 CEST 2009 ppc unknow=
n
>>
>> root@mpc8315e-rdb:~# hdparm -i /dev/sda
>>
>> /dev/sda:
>>
>> =A0Model=3DSolidata X SSD =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0, FwRev=3D0955 =A0 =A0, SerialNo=3D<...>
>> =A0Config=3D{ HardSect NotMFM HdSw>15uSec Fixed DTR>10Mbs }
>> =A0RawCHS=3D16383/16/63, TrkSize=3D0, SectSize=3D0, ECCbytes=3D0
>> =A0BuffType=3Dunknown, BuffSize=3D0kB, MaxMultSect=3D128, MultSect=3D?1?
>> =A0CurCHS=3D16383/16/63, CurSects=3D16514064, LBA=3Dno
>> =A0IORDY=3Dno, tPIO=3D{min:240,w/IORDY:120}
>> =A0PIO modes: =A0pio0 pio3 pio4
>> =A0UDMA modes: udma0 udma1 udma2 udma3 udma4 udma5
>> =A0AdvancedPM=3Dyes: disabled (255) WriteCache=3Ddisabled
>> =A0Drive conforms to: Unspecified: =A0ATA/ATAPI-4 ATA/ATAPI-5 ATA/ATAPI-=
6
>> ATA/ATAPI-7
>>
>> =A0* signifies the current active mode
>>
>>
>>
>> --
>> Leon
>>
>
>
>
> --
> Leon
>
--=20
Leon
^ permalink raw reply
* [PATCH v4] 83xx: add support for the kmeter1 board.
From: Heiko Schocher @ 2009-06-11 18:10 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <0AFEA008-BBF6-448B-844F-6EBE3DE24F7B@kernel.crashing.org>
The following series implements basic board support for
the kmeter1 board from keymile, based on a MPC8360.
This series provides the following functionality:
- The board can boot with a serial console on UART1
- Ethernet:
UCC1 in RGMII mode
UCC2 in RGMII mode
UCC4 in RMII mode
UCC5 in RMII mode
UCC6 in RMII mode
UCC7 in RMII mode
UCC8 in RMII mode
following patch is necessary for working UCC in RMII mode:
http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070804.html
- Flash accessed via MTD layer
On this hardware there is an Intel P30 flash, following patch
series is necessary for working with this hardware:
http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070624.html
- I2C using I2C Bus 1 from the MPC8360 cpu
Signed-off-by: Heiko Schocher <hs@denx.de>
---
changes since v1:
- added comments from Kumar Gala and Scott Wood
- get rid of using get_immrbase() in board specific code
changes since v2:
- added comments from Kumar Gala
- rebased against 1406de8e11eb043681297adf86d6892ff8efc27a
from git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
changes since v3:
- updated mailinglistarchivelinks for necessary patches in commit text.
$ ./scripts/checkpatch.pl 0001--83xx-add-support-for-the-kmeter1-board.patch
total: 0 errors, 0 warnings, 1618 lines checked
0001--83xx-add-support-for-the-kmeter1-board.patch has no obvious style problems and is ready for submission.
$
arch/powerpc/boot/dts/kmeter1.dts | 505 +++++++++++++++
arch/powerpc/configs/83xx/kmeter1_defconfig | 908 +++++++++++++++++++++++++++
arch/powerpc/platforms/83xx/Kconfig | 7 +
arch/powerpc/platforms/83xx/Makefile | 1 +
arch/powerpc/platforms/83xx/kmeter1.c | 188 ++++++
5 files changed, 1609 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/kmeter1.dts
create mode 100644 arch/powerpc/configs/83xx/kmeter1_defconfig
create mode 100644 arch/powerpc/platforms/83xx/kmeter1.c
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
new file mode 100644
index 0000000..768813a
--- /dev/null
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -0,0 +1,505 @@
+/*
+ * Keymile KMETER1 Device Tree Source
+ *
+ * 2008 DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "KMETER1";
+ compatible = "keymile,KMETER1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet_piggy2;
+ ethernet1 = &enet_estar1;
+ ethernet2 = &enet_estar2;
+ ethernet3 = &enet_eth1;
+ ethernet4 = &enet_eth2;
+ ethernet5 = &enet_eth3;
+ ethernet6 = &enet_eth4;
+ serial0 = &serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8360@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <32768>; // L1, 32K
+ i-cache-size = <32768>; // L1, 32K
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ bus-frequency = <0>; /* Filled in by U-Boot */
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>; /* Filled in by U-Boot */
+ };
+
+ soc8360@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8360-immr", "simple-bus";
+ ranges = <0x0 0xe0000000 0x00200000>;
+ reg = <0xe0000000 0x00000200>;
+ bus-frequency = <0>; /* Filled in by U-Boot */
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <14 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <264000000>;
+ interrupts = <9 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ dma@82a8 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
+ reg = <0x82a8 4>;
+ ranges = <0 0x8100 0x1a8>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+ reg = <0 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+ reg = <0x80 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+ reg = <0x100 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+ reg = <0x180 0x28>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ };
+
+ ipic: pic@700 {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "fsl,pq2pro-pic", "fsl,ipic";
+ interrupt-controller;
+ reg = <0x700 0x100>;
+ };
+
+ par_io@1400 {
+ reg = <0x1400 0x100>;
+ device_type = "par_io";
+ num-ports = <7>;
+
+ pio_ucc1: ucc_pin@00 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 0 3 1 0 1 0 /* TxD0 */
+ 0 4 1 0 1 0 /* TxD1 */
+ 0 5 1 0 1 0 /* TxD2 */
+ 0 6 1 0 1 0 /* TxD3 */
+ 0 9 2 0 1 0 /* RxD0 */
+ 0 10 2 0 1 0 /* RxD1 */
+ 0 11 2 0 1 0 /* RxD2 */
+ 0 12 2 0 1 0 /* RxD3 */
+ 0 7 1 0 1 0 /* TX_EN */
+ 0 8 1 0 1 0 /* TX_ER */
+ 0 15 2 0 1 0 /* RX_DV */
+ 0 16 2 0 1 0 /* RX_ER */
+ 0 0 2 0 1 0 /* RX_CLK */
+ 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
+ 2 8 2 0 1 0 /* GTX125 - CLK9 */
+ >;
+ };
+
+ pio_ucc2: ucc_pin@01 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 0 17 1 0 1 0 /* TxD0 */
+ 0 18 1 0 1 0 /* TxD1 */
+ 0 19 1 0 1 0 /* TxD2 */
+ 0 20 1 0 1 0 /* TxD3 */
+ 0 23 2 0 1 0 /* RxD0 */
+ 0 24 2 0 1 0 /* RxD1 */
+ 0 25 2 0 1 0 /* RxD2 */
+ 0 26 2 0 1 0 /* RxD3 */
+ 0 21 1 0 1 0 /* TX_EN */
+ 0 22 1 0 1 0 /* TX_ER */
+ 0 29 2 0 1 0 /* RX_DV */
+ 0 30 2 0 1 0 /* RX_ER */
+ 0 31 2 0 1 0 /* RX_CLK */
+ 2 2 1 0 2 0 /* GTX_CLK - CLK3 */
+ 2 3 2 0 1 0 /* GTX125 - CLK4 */
+ >;
+ };
+
+ pio_ucc4: ucc_pin@03 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
+ 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
+ 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
+ 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
+ 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
+ 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
+ 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
+
+ 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
+ >;
+ };
+
+ pio_ucc5: ucc_pin@04 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
+ 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
+ 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
+ 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
+ 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
+ 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
+ 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
+ >;
+ };
+
+ pio_ucc6: ucc_pin@05 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
+ 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
+ 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
+ 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
+ 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
+ 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
+ 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
+ >;
+ };
+
+ pio_ucc7: ucc_pin@06 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
+ 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
+ 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
+ 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
+ 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
+ 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
+ 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
+ >;
+ };
+
+ pio_ucc8: ucc_pin@07 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
+ 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
+ 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
+ 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
+ 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
+ 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
+ 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
+
+ 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
+ >;
+ };
+
+ };
+
+ qe@100000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe";
+ ranges = <0x0 0x100000 0x100000>;
+ reg = <0x100000 0x480>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ brg-frequency = <0>; /* Filled in by U-Boot */
+ bus-frequency = <0>; /* Filled in by U-Boot */
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x00010000 0x0000c000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0xc000>;
+ };
+ };
+
+ /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+ enet_estar1: ucc@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk9";
+ phy-handle = <&phy_estar1>;
+ phy-connection-type = "rgmii-id";
+ pio-handle = <&pio_ucc1>;
+ };
+
+ /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+ enet_estar2: ucc@3000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <2>;
+ reg = <0x3000 0x200>;
+ interrupts = <33>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk4";
+ phy-handle = <&phy_estar2>;
+ phy-connection-type = "rgmii-id";
+ pio-handle = <&pio_ucc2>;
+ };
+
+ /* Piggy2 (UCC4, MDIO 0x00, RMII) */
+ enet_piggy2: ucc@3200 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <4>;
+ reg = <0x3200 0x200>;
+ interrupts = <35>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk17";
+ phy-handle = <&phy_piggy2>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc4>;
+ };
+
+ /* Eth-1 (UCC5, MDIO 0x08, RMII) */
+ enet_eth1: ucc@2400 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <5>;
+ reg = <0x2400 0x200>;
+ interrupts = <40>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
+ phy-handle = <&phy_eth1>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc5>;
+ };
+
+ /* Eth-2 (UCC6, MDIO 0x09, RMII) */
+ enet_eth2: ucc@3400 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <6>;
+ reg = <0x3400 0x200>;
+ interrupts = <41>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
+ phy-handle = <&phy_eth2>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc6>;
+ };
+
+ /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+ enet_eth3: ucc@2600 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <7>;
+ reg = <0x2600 0x200>;
+ interrupts = <42>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
+ phy-handle = <&phy_eth3>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc7>;
+ };
+
+ /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+ enet_eth4: ucc@3600 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <8>;
+ reg = <0x3600 0x200>;
+ interrupts = <43>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
+ phy-handle = <&phy_eth4>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc8>;
+ };
+
+ mdio@3320 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3320 0x18>;
+ compatible = "fsl,ucc-mdio";
+
+ /* Piggy2 (UCC4, MDIO 0x00, RMII) */
+ phy_piggy2: ethernet-phy@00 {
+ reg = <0x0>;
+ };
+
+ /* Eth-1 (UCC5, MDIO 0x08, RMII) */
+ phy_eth1: ethernet-phy@08 {
+ reg = <0x08>;
+ };
+
+ /* Eth-2 (UCC6, MDIO 0x09, RMII) */
+ phy_eth2: ethernet-phy@09 {
+ reg = <0x09>;
+ };
+
+ /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+ phy_eth3: ethernet-phy@0a {
+ reg = <0x0a>;
+ };
+
+ /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+ phy_eth4: ethernet-phy@0b {
+ reg = <0x0b>;
+ };
+
+ /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+ phy_estar1: ethernet-phy@10 {
+ interrupt-parent = <&ipic>;
+ interrupts = <17 0x8>;
+ reg = <0x10>;
+ };
+
+ /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+ phy_estar2: ethernet-phy@11 {
+ interrupt-parent = <&ipic>;
+ interrupts = <18 0x8>;
+ reg = <0x11>;
+ };
+ };
+
+ qeic: interrupt-controller@80 {
+ interrupt-controller;
+ compatible = "fsl,qe-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ interrupts = <32 8 33 8>;
+ interrupt-parent = <&ipic>;
+ };
+ };
+ };
+
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
+ "simple-bus";
+ reg = <0xe0005000 0xd8>;
+ ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */
+
+ flash@f0000000,0 {
+ compatible = "cfi-flash";
+ /*
+ * The Intel P30 chip has 2 non-identical chips on
+ * one die, so we need to define 2 seperate regions
+ * that are scanned by physmap_of independantly.
+ */
+ reg = <0 0x00000000 0x02000000
+ 0 0x02000000 0x02000000>; /* Filled in by U-Boot */
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x40000>;
+ };
+ partition@40000 {
+ label = "env";
+ reg = <0x40000 0x40000>;
+ };
+ partition@80000 {
+ label = "dtb";
+ reg = <0x80000 0x20000>;
+ };
+ partition@a0000 {
+ label = "kernel";
+ reg = <0xa0000 0x300000>;
+ };
+ partition@3a0000 {
+ label = "ramdisk";
+ reg = <0x3a0000 0x800000>;
+ };
+ partition@ba0000 {
+ label = "user";
+ reg = <0xba0000 0x3460000>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig
new file mode 100644
index 0000000..bf0853f
--- /dev/null
+++ b/arch/powerpc/configs/83xx/kmeter1_defconfig
@@ -0,0 +1,908 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28
+# Fri Apr 3 10:34:33 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+# CONFIG_FSL_EMB_PERFMON is not set
+# CONFIG_ALTIVEC is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# Platform support
+#
+CONFIG_PPC_MULTIPLATFORM=y
+CONFIG_CLASSIC32=y
+# CONFIG_PPC_CHRP is not set
+# CONFIG_MPC5121_ADS is not set
+# CONFIG_MPC5121_GENERIC is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_PPC_83xx=y
+# CONFIG_MPC831x_RDB is not set
+# CONFIG_MPC832x_MDS is not set
+# CONFIG_MPC832x_RDB is not set
+# CONFIG_MPC834x_MDS is not set
+# CONFIG_MPC834x_ITX is not set
+# CONFIG_MPC836x_MDS is not set
+# CONFIG_MPC836x_RDK is not set
+# CONFIG_MPC837x_MDS is not set
+# CONFIG_MPC837x_RDB is not set
+# CONFIG_SBC834x is not set
+# CONFIG_ASP834x is not set
+CONFIG_KMETER1=y
+# CONFIG_PPC_86xx is not set
+# CONFIG_EMBEDDED6xx is not set
+CONFIG_IPIC=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+CONFIG_QUICC_ENGINE=y
+# CONFIG_QE_GPIO is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_KEXEC is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_FSL_SOC=y
+CONFIG_PPC_PCI_CHOICE=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_PHRAM=y
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+CONFIG_MTD_UBI_DEBUG=y
+# CONFIG_MTD_UBI_DEBUG_MSG is not set
+# CONFIG_MTD_UBI_DEBUG_PARANOID is not set
+# CONFIG_MTD_UBI_DEBUG_DISABLE_BGT is not set
+# CONFIG_MTD_UBI_DEBUG_USERSPACE_IO is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES is not set
+
+#
+# Additional UBI debugging messages
+#
+# CONFIG_MTD_UBI_DEBUG_MSG_BLD is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_EBA is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_WL is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_IO is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_GIANFAR is not set
+CONFIG_UCC_GETH=y
+# CONFIG_UGETH_MAGIC_PACKET is not set
+# CONFIG_UGETH_FILTERING is not set
+# CONFIG_UGETH_TX_ON_DEMAND is not set
+# CONFIG_MV643XX_ETH is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_WAN=y
+CONFIG_HDLC=y
+# CONFIG_HDLC_RAW is not set
+# CONFIG_HDLC_RAW_ETH is not set
+# CONFIG_HDLC_CISCO is not set
+# CONFIG_HDLC_FR is not set
+# CONFIG_HDLC_PPP is not set
+
+#
+# X.25/LAPB support is disabled
+#
+CONFIG_HDLC_KM=y
+CONFIG_FS_UCC_HDLC=y
+# CONFIG_DLCI is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+CONFIG_PPPOE=y
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SERIAL_QE is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_BOOTCOUNT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_MCU_MPC8349EMITX is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_REGULATOR is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+CONFIG_UIO=y
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_UBIFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+CONFIG_UCC_FAST=y
+CONFIG_UCC=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_IRQSTACKS is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set
+CONFIG_PPC_LIB_RHEAP=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 437d29a..083ebee 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -96,6 +96,13 @@ config ASP834x
This enables support for the Analogue & Micro ASP 83xx
board.
+config KMETER1
+ bool "Keymile KMETER1"
+ select DEFAULT_UIMAGE
+ select QUICC_ENGINE
+ help
+ This enables support for the Keymile KMETER1 board.
+
endif
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index 051777c..e139c36 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o
obj-$(CONFIG_SBC834x) += sbc834x.o
obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o
obj-$(CONFIG_ASP834x) += asp834x.o
+obj-$(CONFIG_KMETER1) += kmeter1.o
diff --git a/arch/powerpc/platforms/83xx/kmeter1.c b/arch/powerpc/platforms/83xx/kmeter1.c
new file mode 100644
index 0000000..429201a
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/kmeter1.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright 2008 DENX Software Engineering GmbH
+ * Author: Heiko Schocher <hs@denx.de>
+ *
+ * Description:
+ * Keymile KMETER1 board specific routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+
+#include "mpc83xx.h"
+
+#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init kmeter1_setup_arch(void)
+{
+ struct device_node *np;
+
+ if (ppc_md.progress)
+ ppc_md.progress("kmeter1_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
+ mpc83xx_add_bridge(np);
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+ qe_reset();
+
+ np = of_find_node_by_name(NULL, "par_io");
+ if (np != NULL) {
+ par_io_init(np);
+ of_node_put(np);
+
+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+ par_io_of_config(np);
+ }
+
+ np = of_find_compatible_node(NULL, "network", "ucc_geth");
+ if (np != NULL) {
+ uint svid;
+
+ /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
+ svid = mfspr(SPRN_SVR);
+ if (SVR_REV(svid) == 0x0021) {
+ struct device_node *np_par;
+ struct resource res;
+ void __iomem *base;
+ int ret;
+
+ np_par = of_find_node_by_name(NULL, "par_io");
+ if (np_par == NULL) {
+ printk(KERN_WARNING "%s couldn;t find par_io node\n",
+ __func__);
+ return;
+ }
+ /* Map Parallel I/O ports registers */
+ ret = of_address_to_resource(np_par, 0, &res);
+ if (ret) {
+ printk(KERN_WARNING "%s couldn;t map par_io registers\n",
+ __func__);
+ return;
+ }
+ base = ioremap(res.start, res.end - res.start + 1);
+
+ /*
+ * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+ * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+ */
+ setbits32((base + 0xa8), 0x0c003000);
+
+ /*
+ * IMMR + 0x14AC[20:27] = 10101010
+ * (data delay for both UCC's)
+ */
+ clrsetbits_be32((base + 0xac), 0xff0, 0xaa0);
+ iounmap(base);
+ of_node_put(np_par);
+ }
+ of_node_put(np);
+ }
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+static struct of_device_id kmeter_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ { .compatible = "simple-bus", },
+ { .type = "qe", },
+ { .compatible = "fsl,qe", },
+ {},
+};
+
+static int __init kmeter_declare_of_platform_devices(void)
+{
+ /* Publish the QE devices */
+ of_platform_bus_probe(NULL, kmeter_ids, NULL);
+
+ return 0;
+}
+machine_device_initcall(kmeter1, kmeter_declare_of_platform_devices);
+
+static void __init kmeter1_init_IRQ(void)
+{
+ struct device_node *np;
+
+ np = of_find_node_by_type(NULL, "ipic");
+ if (!np)
+ return;
+
+ ipic_init(np, 0);
+
+ /* Initialize the default interrupt mapping priorities,
+ * in case the boot rom changed something on us.
+ */
+ ipic_set_default_priority();
+ of_node_put(np);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+ if (!np) {
+ np = of_find_node_by_type(NULL, "qeic");
+ if (!np)
+ return;
+ }
+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
+ of_node_put(np);
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init kmeter1_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "keymile,KMETER1");
+}
+
+define_machine(kmeter1) {
+ .name = "KMETER1",
+ .probe = kmeter1_probe,
+ .setup_arch = kmeter1_setup_arch,
+ .init_IRQ = kmeter1_init_IRQ,
+ .get_irq = ipic_get_irq,
+ .restart = mpc83xx_restart,
+ .time_init = mpc83xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.6.0.6
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply related
* Re: [PATCH v3] 83xx: add support for the kmeter1 board.
From: Heiko Schocher @ 2009-06-11 18:08 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <0AFEA008-BBF6-448B-844F-6EBE3DE24F7B@kernel.crashing.org>
Hello Kumar,
Kumar Gala wrote:
> On Jun 11, 2009, at 1:16 AM, Heiko Schocher wrote:
>
>> The following series implements basic board support for
>> the kmeter1 board from keymile, based on a MPC8360.
>>
>> This series provides the following functionality:
>>
>> - The board can boot with a serial console on UART1
>> - Ethernet:
>> UCC1 in RGMII mode
>> UCC2 in RGMII mode
>> UCC4 in RMII mode
>> UCC5 in RMII mode
>> UCC6 in RMII mode
>> UCC7 in RMII mode
>> UCC8 in RMII mode
>>
>> following patch is necessary for working UCC in RMII mode:
>>
>> http://ozlabs.org/pipermail/linuxppc-dev/2009-April/070909.html
>>
>> - Flash accessed via MTD layer
>>
>> On this hardware there is an Intel P30 flash, following patch
>> series is necessary for working with this hardware:
>>
>> http://ozlabs.org/pipermail/linuxppc-dev/2009-April/070716.html
>
> the links are stale since the ozlabs.org rebuilt and moved the
> maillist.. mind updating.
Ups, sorry, copy and paste error ...
bye
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply
* Re: [PATCH] powerpc/mpc52xx/mtd: fix mtd-ram access for 16-bit Local Plus Bus
From: Grant Likely @ 2009-06-11 17:28 UTC (permalink / raw)
To: Wolfram Sang; +Cc: Albrecht Dreß, dwmw2, Linux PPC Development
In-Reply-To: <20090611165527.GB28028@pengutronix.de>
On Thu, Jun 11, 2009 at 10:55 AM, Wolfram Sang<w.sang@pengutronix.de> wrote=
:
>> Blech. =A0ugly #ifdef and not really multiplatform safe (yeah, I know it
>> shouldn't break non-5200 platforms, but it does have an undesirable
>> impact). =A0There's got to be a better way.
>
> What about putting the special memcpy in asm/io.h (like it is done for ee=
h)?
It is a beefy enough function that it is probably a net loss to make
it an inline static in the header file. It should be an exported
function.
> Will this cause too much overhead for a memcpy which does not go to the L=
PB?
It doesn't solve my concerns. bankwidth=3D=3D2 is the wrong test; plenty
of non-mpc5200 platforms could have the same property set without
needing the workaround.
inline_map_copy_to is used in exactly 2 places in drivers/mtd/* and
include/linux/mtd/*:
1) the definition of map_copy_to() in include/linux/mtd/map.h
- map_copy_to() is only used by maprap_write() which is a mtd_info hook.
2) the definition of simple_map_copy_to() in drivers/mtd/maps/map_funcs.c
- a map_info hook.
So; the solution to me seems to be on an MPC5200 platform replace the
offending hooks with MPC5200 specific variants at runtime.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH] powerpc: tiny memcpy_(to|from)io optimisation
From: Grant Likely @ 2009-06-11 17:30 UTC (permalink / raw)
To: Albrecht Dreß; +Cc: Linux PPC Development
In-Reply-To: <1243454441.3489.1@antares>
On Wed, May 27, 2009 at 2:00 PM, Albrecht Dre=DF<albrecht.dress@arcor.de> w=
rote:
> This trivial patch changes memcpy_(to|from)io as to transfer as many 32-b=
it
> words as possible in 32-bit accesses (in the current solution, the last
> 32-bit word was transferred as 4 byte accesses).
>
> Signed-off-by: Albrecht Dre=DF <albrecht.dress@arcor.de>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
> ---
>
> diff -urpN -X linux-2.6.29.1.orig/Documentation/dontdiff
> linux-2.6.29.1.orig/arch/powerpc/kernel/io.c
> linux-2.6.29.1/arch/powerpc/kernel/io.c
> --- linux-2.6.29.1.orig/arch/powerpc/kernel/io.c =A0 =A0 =A0 =A02009-04-0=
2
> 22:55:27.000000000 +0200
> +++ linux-2.6.29.1/arch/powerpc/kernel/io.c =A0 =A0 2009-05-27
> 11:36:09.000000000 +0200
> @@ -161,7 +161,7 @@ void _memcpy_fromio(void *dest, const vo
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dest++;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0n--;
> =A0 =A0 =A0 =A0}
> - =A0 =A0 =A0 while(n > 4) {
> + =A0 =A0 =A0 while(n >=3D 4) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0*((u32 *)dest) =3D *((volatile u32 *)vsrc)=
;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0eieio();
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0vsrc +=3D 4;
> @@ -190,7 +190,7 @@ void _memcpy_toio(volatile void __iomem
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0vdest++;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0n--;
> =A0 =A0 =A0 =A0}
> - =A0 =A0 =A0 while(n > 4) {
> + =A0 =A0 =A0 while(n >=3D 4) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0*((volatile u32 *)vdest) =3D *((volatile u=
32 *)src);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0src +=3D 4;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0vdest +=3D 4;
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH] powerpc: tiny memcpy_(to|from)io optimisation
From: Wolfram Sang @ 2009-06-11 17:07 UTC (permalink / raw)
To: Albrecht Dreß; +Cc: Linux PPC Development
In-Reply-To: <1243454441.3489.1@antares>
[-- Attachment #1: Type: text/plain, Size: 602 bytes --]
On Wed, May 27, 2009 at 10:00:41PM +0200, Albrecht Dreß wrote:
> This trivial patch changes memcpy_(to|from)io as to transfer as many
> 32-bit words as possible in 32-bit accesses (in the current solution,
> the last 32-bit word was transferred as 4 byte accesses).
>
> Signed-off-by: Albrecht Dreß <albrecht.dress@arcor.de>
Besides the discussion about optimizing the loop, what about the patch itself?
Looks plausible to me...
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: "next" branch update
From: Josh Boyer @ 2009-06-11 17:05 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <1244603678.2431.18.camel@pasglop>
Quoting Benjamin Herrenschmidt <benh@kernel.crashing.org>:
> Hi !
>
> I've updated my "next" branch with the following patches. We're getting
> real close to the merge window now, so if something is missing, please
> holler ASAP.
Could you please pull the 'next' branch of the 4xx tree? I haven't
had a chance to generate a formal pull request due to travel and now
an unexpected family issue.
josh
^ permalink raw reply
* Re: [PATCH] powerpc/mpc52xx/mtd: fix mtd-ram access for 16-bit Local Plus Bus
From: Wolfram Sang @ 2009-06-11 16:55 UTC (permalink / raw)
To: Grant Likely; +Cc: Albrecht Dreß, dwmw2, Linux PPC Development
In-Reply-To: <fa686aa40906110927w60a5a74alaa3420b9bf3f3e44@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 507 bytes --]
> Blech. ugly #ifdef and not really multiplatform safe (yeah, I know it
> shouldn't break non-5200 platforms, but it does have an undesirable
> impact). There's got to be a better way.
What about putting the special memcpy in asm/io.h (like it is done for eeh)?
Will this cause too much overhead for a memcpy which does not go to the LPB?
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc/mpc52xx/mtd: fix mtd-ram access for 16-bit Local Plus Bus
From: Grant Likely @ 2009-06-11 16:27 UTC (permalink / raw)
To: Albrecht Dreß; +Cc: Linux PPC Development, dwmw2
In-Reply-To: <1244576781.3455.0@antares>
On Tue, Jun 9, 2009 at 1:46 PM, Albrecht Dre=DF<albrecht.dress@arcor.de> wr=
ote:
> Hi all,
>
> this patch adds support for RAM chips connected to the Local Plus Bus of =
a
> MPC5200B in 16-bit mode. =A0As no single byte write accesses are allowed =
by
> the bus in this mode, a byte write has to be split into a word read - mod=
ify
> - write sequence (mpc52xx_memcpy2lpb16, as fix/extension for memcpy_toio;
> note that memcpy_fromio *does* work just fine). =A0It has been tested in
> conjunction with Wolfram Sang's mtd-ram [1] and Sascha Hauer's jffs
> unaligned access [2] patches on 2.6.29.1, with a Renesas static RAM
> connected in 16-bit "Large Flash" mode.
>
> [1] <http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-June/072794.html=
>
> [2] <http://article.gmane.org/gmane.linux.drivers.mtd/21521>
>
> Signed-off-by: Albrecht Dre=DF <albrecht.dress@arcor.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: linuxppc-dev@ozlabs.org
>
> ---
>
> diff -u linux-2.6.29.1.orig/arch/powerpc/platforms/52xx/mpc52xx_common.c
> linux-2.6.29.1/arch/powerpc/platforms/52xx/mpc52xx_common.c
> --- linux-2.6.29.1.orig/arch/powerpc/platforms/52xx/mpc52xx_common.c
> =A02009-04-02 22:55:27.000000000 +0200
> +++ linux-2.6.29.1/arch/powerpc/platforms/52xx/mpc52xx_common.c 2009-06-0=
9
> 21:16:22.000000000 +0200
> @@ -225,3 +225,59 @@
>
> =A0 =A0 =A0 =A0while (1);
> =A0}
> +
> +/**
> + * mpc52xx_memcpy2lpb16: copy data to the Local Plus Bus in 16-bit mode
> which
> + * doesn't allow byte accesses
> + */
> +void
> +mpc52xx_memcpy2lpb16(volatile void __iomem *dest, const void *src,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0unsigned long n)
> +{
> + =A0 =A0 =A0 void *vdest =3D (void __force *) dest;
> +
> + =A0 =A0 =A0 __asm__ __volatile__ ("sync" : : : "memory");
> +
> + =A0 =A0 =A0 if (((unsigned long) vdest & 1) !=3D 0) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 u8 buf[2];
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 *(u16 *)buf =3D *((volatile u16 *)(vdest - =
1));
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 buf[1] =3D *((u8 *)src);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 *((volatile u16 *)(vdest - 1)) =3D *(u16 *)=
buf;
what is the purpose of volatile here? If you need io barriers, then
use the in_/out_be16 macros.
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 src++;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 vdest++;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 n--;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 /* looks weird, but helps the optimiser... */
> + =A0 =A0 =A0 if (n >=3D 4) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 unsigned long chunks =3D n >> 2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 volatile u32 * _dst =3D (volatile u32 *)(vd=
est - 4);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 volatile u32 * _src =3D (volatile u32 *)(sr=
c - 4);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 vdest +=3D chunks << 2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 src +=3D chunks << 2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 do {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 *++_dst =3D *++_src;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 } while (--chunks);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 n &=3D 3;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 if (n >=3D 2) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 *((volatile u16 *)vdest) =3D *((volatile u1=
6 *)src);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 src +=3D 2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 vdest +=3D 2;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 n -=3D 2;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 if (n > 0) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 u8 buf[2];
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 *(u16 *)buf =3D *((volatile u16 *)vdest);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 buf[0] =3D *((u8 *)src);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 *((volatile u16 *)vdest) =3D *(u16 *)buf;
ditto.
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 __asm__ __volatile__ ("sync" : : : "memory");
> +}
> +EXPORT_SYMBOL(mpc52xx_memcpy2lpb16);
> diff -u linux-2.6.29.1.orig/arch/powerpc/include/asm/mpc52xx.h
> linux-2.6.29.1/arch/powerpc/include/asm/mpc52xx.h
> --- linux-2.6.29.1.orig/arch/powerpc/include/asm/mpc52xx.h =A0 =A0 =A0200=
9-04-02
> 22:55:27.000000000 +0200
> +++ linux-2.6.29.1/arch/powerpc/include/asm/mpc52xx.h =A0 2009-06-09
> 21:14:31.000000000 +0200
> @@ -274,6 +274,8 @@
> =A0extern void mpc52xx_map_common_devices(void);
> =A0extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
> =A0extern void mpc52xx_restart(char *cmd);
> +extern void mpc52xx_memcpy2lpb16(volatile void __iomem *dest, const void
> *src,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0unsigned=
long n);
>
> =A0/* mpc52xx_pic.c */
> =A0extern void mpc52xx_init_irq(void);
> diff -u linux-2.6.29.1.orig/include/linux/mtd/map.h
> linux-2.6.29.1/include/linux/mtd/map.h
> --- linux-2.6.29.1.orig/include/linux/mtd/map.h 2009-04-02
> 22:55:27.000000000 +0200
> +++ linux-2.6.29.1/include/linux/mtd/map.h =A0 =A0 =A02009-06-08
> 14:28:05.000000000 +0200
> @@ -13,6 +13,9 @@
> =A0#include <asm/unaligned.h>
> =A0#include <asm/system.h>
> =A0#include <asm/io.h>
> +#ifdef CONFIG_PPC_MPC52xx
> +#include <asm/mpc52xx.h>
> +#endif
>
> =A0#ifdef CONFIG_MTD_MAP_BANK_WIDTH_1
> =A0#define map_bankwidth(map) 1
> @@ -417,6 +420,11 @@
>
> =A0static inline void inline_map_copy_to(struct map_info *map, unsigned l=
ong
> to, const void *from, ssize_t len)
> =A0{
> +#ifdef CONFIG_PPC_MPC52xx
> + =A0 =A0 =A0 if (map->bankwidth =3D=3D 2)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc52xx_memcpy2lpb16(map->virt + to, from, =
len);
> + =A0 =A0 =A0 else
> +#endif
> =A0 =A0 =A0 =A0memcpy_toio(map->virt + to, from, len);
> =A0}
Blech. ugly #ifdef and not really multiplatform safe (yeah, I know it
shouldn't break non-5200 platforms, but it does have an undesirable
impact). There's got to be a better way.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: MPC5200B: Can't receive/handle external Interrupts
From: Grant Likely @ 2009-06-11 16:18 UTC (permalink / raw)
To: Schaller Stephan; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <C10D11C8340AFC47891731EA67CD31C20162F071EFC7@stwex.stww2k.local>
On Wed, Jun 10, 2009 at 12:03 PM, Schaller
Stephan<Stephan.Schaller@sensor-technik.de> wrote:
> So, basically two Problems:
> - ISR seems only to get called by a "Main Interrupt", not by a "IRQ Interrupt". How do I make the connection between these?
This is probably due to the way the IRQ driver reads the irq registers
to decide what interrupts are pending. I wouldn't worry about it.
> - The IRQ3 input Pin level is not shown in the status register and is not regognized by the CPU.
Odd. This shouldn't happen. Is your hardware okay?
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox