* Re: [PATCH 10/33] powerpc/cell: Extract duplicated IOPTE_* to <asm/iommu.h>
From: Arnd Bergmann @ 2009-06-15 7:05 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Geert Uytterhoeven, cbe-oss-dev, linuxppc-dev
In-Reply-To: <1245030085.19217.5.camel@pasglop>
On Monday 15 June 2009, Benjamin Herrenschmidt wrote:
> On Wed, 2009-06-10 at 16:38 +0200, Geert Uytterhoeven wrote:
> > Both arch/powerpc/platforms/cell/iommu.c and arch/powerpc/platforms/ps3/mm.c
> > contain the same Cell IOMMU page table entry definitions. Extract them and move
> > them to <asm/iommu.h>, while adding a CBE_ prefix.
> > This also allows them to be used by drivers.
>
> Are we sure include/asm/iommu.h is the right place for that ?
>
> I'm hesitating here...
Good point, that file does not contain hardware specific definitions but
only interfaces.
Geert, how about putting them into arch/powerpc/include/asm/cell-regs.h
instead?
Arnd <><
^ permalink raw reply
* Re: [PATCH][BUILD FAILURE 03/04] Next June 04:PPC64 randconfig [drivers/net/lance.o]
From: Benjamin Herrenschmidt @ 2009-06-15 7:11 UTC (permalink / raw)
To: subrata
Cc: Sachin P Sant, Stephen Rothwell, netdev, Linux-Kernel,
Linuxppc-dev, Linux-Next, Paul Mackerras, Balbir Singh
In-Reply-To: <1245048698.5239.9.camel@subratamodak.linux.ibm.com>
On Mon, 2009-06-15 at 12:21 +0530, Subrata Modak wrote:
> Benjamin,
>
> I am not sure whether you liked the following patch to solve the above
> problem. Do, you want me address some other issue(s)/fixes for this ?
I suppose ... in fact some old PReP machines can even have ISA slots
iirc, but it's not going to do good with machines that have an iommu...
IE. Nobody should use that crap, period.
Cheers,
Ben.
Cheers,
Ben.
> Regards--
> Subrata
>
> >
> > --- linux-2.6.30-rc8/arch/powerpc/include/asm/io.h.orig 2009-06-10 21:56:49.000000000 -0500
> > +++ linux-2.6.30-rc8/arch/powerpc/include/asm/io.h 2009-06-10 22:21:35.000000000 -0500
> > @@ -680,6 +680,9 @@ extern void __iounmap_at(void *ea, unsig
> > #define mmio_outsw(addr, src, count) writesw(addr, src, count)
> > #define mmio_outsl(addr, src, count) writesl(addr, src, count)
> >
> > +#define isa_virt_to_bus virt_to_phys
> > +#define isa_bus_to_virt phys_to_virt
> > +
> > /**
> > * virt_to_phys - map virtual addresses to physical
> > * @address: address to remap
> >
> > ---
> > Regards--
> > Subrata
> >
^ permalink raw reply
* Re: [PATCH 10/33] powerpc/cell: Extract duplicated IOPTE_* to <asm/iommu.h>
From: Benjamin Herrenschmidt @ 2009-06-15 7:12 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: Geert Uytterhoeven, linuxppc-dev, linuxppc-dev, cbe-oss-dev
In-Reply-To: <200906150905.30744.arnd@arndb.de>
On Mon, 2009-06-15 at 09:05 +0200, Arnd Bergmann wrote:
> Good point, that file does not contain hardware specific definitions
> but
> only interfaces.
>
> Geert, how about putting them into
> arch/powerpc/include/asm/cell-regs.h
> instead?
I've put the patch in powerpc-next for now. But you may want to send
another patch later on to move things.
Cheers,
Ben.
^ permalink raw reply
* Re: [Patch 2/6] Introduce PPC64 specific Hardware Breakpoint interfaces
From: K.Prasad @ 2009-06-15 7:18 UTC (permalink / raw)
To: David Gibson
Cc: Michael Neuling, Benjamin Herrenschmidt, linuxppc-dev, paulus,
Alan Stern, Roland McGrath
In-Reply-To: <20090615064045.GB26817@yookeroo.seuss>
On Mon, Jun 15, 2009 at 04:40:45PM +1000, David Gibson wrote:
> On Wed, Jun 10, 2009 at 12:13:49PM +0530, K.Prasad wrote:
> > On Fri, Jun 05, 2009 at 03:11:58PM +1000, David Gibson wrote:
> > > On Wed, Jun 03, 2009 at 10:05:11PM +0530, K.Prasad wrote:
> >
> > > > + else {
> > > > + /*
> > > > + * This exception is triggered not because of a memory access on
> > > > + * the monitored variable but in the double-word address range
> > > > + * in which it is contained. We will consume this exception,
> > > > + * considering it as 'noise'.
> > > > + */
> > > > + rc = NOTIFY_STOP;
> > > > + goto out;
> > > > + }
> > > > + is_one_shot = (bp->triggered == ptrace_triggered) ? 1 : 0;
> > >
> > > Ouch, explicitly special-casing ptrace_triggered is pretty nasty.
> > > Since the bp_info is already arch specific, maybe it should include a
> > > flag to indicate whether the breakpoint is one-shot or not.
> > >
> >
> > The reason to check for ptrace_triggered is to contain the one-shot
> > behaviour only to ptrace (thus retaining the semantics) and not to extend
> > them to all user-space requests through
> > register_user_hw_breakpoint().
>
> Right, but couldn't you implement that withing ptrace_triggered
> itself, without a special test here, by having it cancel the
> breakpoint.
>
A special check (either using the callback routine as above, or using a
special flag) will be required in hw_breakpoint_handler() to enable
early return (without single-stepping). I'm not sure if I got your
suggestion right, and let me know if you think so.
> > A one-shot behaviour for all user-space requests would create more work
> > for the user-space programs (such as re-registration) and will leave open
> > a small window of opportunity for debug register grabbing by kernel-space
> > requests.
> >
> > So, in effect a request through register_user_hw_breakpoint() interface
> > will behave as under:
> > - Single-step over the causative instruction that triggered the
> > breakpoint exception handler.
> > - Deliver the SIGTRAP signal to user-space after executing the causative
> > instruction.
> >
> > This behaviour is in consonance with that of kernel-space requests and
> > those on x86 processors, and helps define a consistent behaviour across
> > architectures for user-space.
> >
> > Let me know what you think on the same.
>
> I certainly see the value in consistent semantics across archs.
> However, I can also see uses for the powerpc trap-before-execute
> behaviour. That's why I'm suggesting it might be worth having an
> arch-specific flag.
>
> [snip]
So, you suggest that the 'one-shot' behaviour should be driven by
user-request and not just confined to ptrace? (The default behaviour for
all breakpoints-minus-ptrace will remain 'continuous' though).
It can be implemented through an additional flag in 'struct
arch_hw_breakpoint'. I can send a new version 7 of the patchset with this
change (with the hope that the version 6 of the patchset looks fine in
its present form!). Meanwhile, we'd like to know what uses you see in
addition to the present one if the one-shot behaviour is made
user-defined. Are those uses beyond what can be achieved through the
present ptrace interface?
> > > > +int __kprobes single_step_dabr_instruction(struct die_args *args)
> > > > +{
> > > > + struct pt_regs *regs = args->regs;
> > > > + int cpu = get_cpu();
> > > > + int ret = NOTIFY_DONE;
> > > > + siginfo_t info;
> > > > + unsigned long this_dabr_data = per_cpu(dabr_data, cpu);
> > > > +
> > > > + /*
> > > > + * Check if we are single-stepping as a result of a
> > > > + * previous HW Breakpoint exception
> > > > + */
> > > > + if (this_dabr_data == 0)
> > > > + goto out;
> > > > +
> > > > + regs->msr &= ~MSR_SE;
> > > > + /* Deliver signal to user-space */
> > > > + if (this_dabr_data < TASK_SIZE) {
> > > > + info.si_signo = SIGTRAP;
> > > > + info.si_errno = 0;
> > > > + info.si_code = TRAP_HWBKPT;
> > > > + info.si_addr = (void __user *)(per_cpu(dabr_data, cpu));
> > > > + force_sig_info(SIGTRAP, &info, current);
> > >
> > > Uh.. I recall mentioning in my previous review that in order to match
> > > previous behaviour we need to deliver the userspace signal *before*
> > > stepping over the breakpointed instruction, rather than after (which
> > > I guess is why breakpoints are one-shot in the old scheme).
> >
> > This code would implement the behaviour as stated in the comment for
> > user-space requests above.
>
> And you're relying on the old trap-sending code in do_dabr for ptrace
> requests?
>
Yes.
> --
> David Gibson | I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
> | _way_ _around_!
> http://www.ozlabs.org/~dgibson
Thanks,
K.Prasad
^ permalink raw reply
* Re: [PATCH][BUILD FAILURE 03/04] Next June 04:PPC64 randconfig [drivers/net/lance.o]
From: Subrata Modak @ 2009-06-15 7:21 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Sachin P Sant, Stephen Rothwell, netdev, Linux-Kernel,
Linuxppc-dev, Linux-Next, Paul Mackerras, Balbir Singh
In-Reply-To: <1245049899.19217.56.camel@pasglop>
On Mon, 2009-06-15 at 17:11 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2009-06-15 at 12:21 +0530, Subrata Modak wrote:
>
> > Benjamin,
> >
> > I am not sure whether you liked the following patch to solve the above
> > problem. Do, you want me address some other issue(s)/fixes for this ?
>
> I suppose ... in fact some old PReP machines can even have ISA slots
> iirc, but it's not going to do good with machines that have an iommu...
>
> IE. Nobody should use that crap, period.
Great,
Can you please make some changes at drivers/net/Kconfig so that this guy
does not build for the PPC64 systems ?
Regards--
Subrata
>
> Cheers,
> Ben.
>
> Cheers,
> Ben.
>
> > Regards--
> > Subrata
> >
> > >
> > > --- linux-2.6.30-rc8/arch/powerpc/include/asm/io.h.orig 2009-06-10 21:56:49.000000000 -0500
> > > +++ linux-2.6.30-rc8/arch/powerpc/include/asm/io.h 2009-06-10 22:21:35.000000000 -0500
> > > @@ -680,6 +680,9 @@ extern void __iounmap_at(void *ea, unsig
> > > #define mmio_outsw(addr, src, count) writesw(addr, src, count)
> > > #define mmio_outsl(addr, src, count) writesl(addr, src, count)
> > >
> > > +#define isa_virt_to_bus virt_to_phys
> > > +#define isa_bus_to_virt phys_to_virt
> > > +
> > > /**
> > > * virt_to_phys - map virtual addresses to physical
> > > * @address: address to remap
> > >
> > > ---
> > > Regards--
> > > Subrata
> > >
>
^ permalink raw reply
* Re: [PATCH] powerpc: Add configurable -Werror for arch/powerpc
From: Michael Ellerman @ 2009-06-15 7:50 UTC (permalink / raw)
To: BenjaminHerrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <adf502e7c85161d77fdcaca24f55ba6b418c7f04.1244616523.git.michael@ellerman.id.au>
[-- Attachment #1: Type: text/plain, Size: 1071 bytes --]
On Wed, 2009-06-10 at 16:48 +1000, Michael Ellerman wrote:
> Add the option to build the code under arch/powerpc with -Werror.
>
> The intention is to make it harder for people to inadvertantly introduce
> warnings in the arch/powerpc code. It needs to be configurable so that
> if a warning is introduced, people can easily work around it while it's
> being fixed.
>
> The option is a negative, ie. don't enable -Werror, so that it will be
> turned on for allyes and allmodconfig builds.
>
> The default is n, in the hope that developers will build with -Werror,
> that will probably lead to some build breaks, I am prepared to be flamed.
Currently this appears to break only one of the defconfigs, chrp32.
http://kisskb.ellerman.id.au/kisskb/head/1907/
And that's a legitimate error AFAICT:
arch/powerpc/platforms/chrp/setup.c:378: error: the frame size of 1040 bytes is larger than 1024 bytes
From:
367 void
368 chrp_event_scan(unsigned long unused)
369 {
370 unsigned char log[1024];
371 int ret = 0;
cheers
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* [PATCH v5] 83xx: add support for the kmeter1 board.
From: Heiko Schocher @ 2009-06-15 7:38 UTC (permalink / raw)
To: Heiko Schocher, Kumar Gala, Scott Wood, linuxppc-dev
In-Reply-To: <20090615024252.GC25444@yookeroo.seuss>
The following series implements basic board support for
the kmeter1 board from keymile, based on a MPC8360.
This series provides the following functionality:
- The board can boot with a serial console on UART1
- Ethernet:
UCC1 in RGMII mode
UCC2 in RGMII mode
UCC4 in RMII mode
UCC5 in RMII mode
UCC6 in RMII mode
UCC7 in RMII mode
UCC8 in RMII mode
following patch is necessary for working UCC in RMII mode:
http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070804.html
- Flash accessed via MTD layer
On this hardware there is an Intel P30 flash, following patch
series is necessary for working with this hardware:
http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070624.html
- I2C using I2C Bus 1 from the MPC8360 cpu
Signed-off-by: Heiko Schocher <hs@denx.de>
---
changes since v1:
- added comments from Kumar Gala and Scott Wood
- get rid of using get_immrbase() in board specific code
changes since v2:
- added comments from Kumar Gala
- rebased against 1406de8e11eb043681297adf86d6892ff8efc27a
from git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
changes since v3:
- updated mailinglistarchivelinks for necessary patches in commit text.
changes since v4:
- added comments from David Gibson
$ ./scripts/checkpatch.pl 0001--83xx-add-support-for-the-kmeter1-board.patch
total: 0 errors, 0 warnings, 1636 lines checked
0001--83xx-add-support-for-the-kmeter1-board.patch has no obvious style problems and is ready for submission.
$
Signed-off-by: Heiko Schocher <hs@denx.de>
---
arch/powerpc/boot/dts/kmeter1.dts | 520 +++++++++++++++
arch/powerpc/configs/83xx/kmeter1_defconfig | 908 +++++++++++++++++++++++++++
arch/powerpc/platforms/83xx/Kconfig | 7 +
arch/powerpc/platforms/83xx/Makefile | 1 +
arch/powerpc/platforms/83xx/kmeter1.c | 191 ++++++
5 files changed, 1627 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/kmeter1.dts
create mode 100644 arch/powerpc/configs/83xx/kmeter1_defconfig
create mode 100644 arch/powerpc/platforms/83xx/kmeter1.c
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
new file mode 100644
index 0000000..167044f
--- /dev/null
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -0,0 +1,520 @@
+/*
+ * Keymile KMETER1 Device Tree Source
+ *
+ * 2008 DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "KMETER1";
+ compatible = "keymile,KMETER1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet_piggy2;
+ ethernet1 = &enet_estar1;
+ ethernet2 = &enet_estar2;
+ ethernet3 = &enet_eth1;
+ ethernet4 = &enet_eth2;
+ ethernet5 = &enet_eth3;
+ ethernet6 = &enet_eth4;
+ serial0 = &serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8360@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <32768>; // L1, 32K
+ i-cache-size = <32768>; // L1, 32K
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ bus-frequency = <0>; /* Filled in by U-Boot */
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0>; /* Filled in by U-Boot */
+ };
+
+ soc8360@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,mpc8360-immr", "simple-bus";
+ ranges = <0x0 0xe0000000 0x00200000>;
+ reg = <0xe0000000 0x00000200>;
+ bus-frequency = <0>; /* Filled in by U-Boot */
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <14 0x8>;
+ interrupt-parent = <&ipic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <264000000>;
+ interrupts = <9 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
+ dma@82a8 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
+ reg = <0x82a8 4>;
+ ranges = <0 0x8100 0x1a8>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+ reg = <0 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+ reg = <0x80 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+ reg = <0x100 0x80>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
+ reg = <0x180 0x28>;
+ interrupt-parent = <&ipic>;
+ interrupts = <71 8>;
+ };
+ };
+
+ ipic: pic@700 {
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "fsl,pq2pro-pic", "fsl,ipic";
+ interrupt-controller;
+ reg = <0x700 0x100>;
+ };
+
+ par_io@1400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1400 0x100>;
+ compatible = "fsl,mpc8360-par_io";
+ num-ports = <7>;
+
+ pio_ucc1: ucc_pin@0 {
+ reg = <0>;
+
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 0 3 1 0 1 0 /* TxD0 */
+ 0 4 1 0 1 0 /* TxD1 */
+ 0 5 1 0 1 0 /* TxD2 */
+ 0 6 1 0 1 0 /* TxD3 */
+ 0 9 2 0 1 0 /* RxD0 */
+ 0 10 2 0 1 0 /* RxD1 */
+ 0 11 2 0 1 0 /* RxD2 */
+ 0 12 2 0 1 0 /* RxD3 */
+ 0 7 1 0 1 0 /* TX_EN */
+ 0 8 1 0 1 0 /* TX_ER */
+ 0 15 2 0 1 0 /* RX_DV */
+ 0 16 2 0 1 0 /* RX_ER */
+ 0 0 2 0 1 0 /* RX_CLK */
+ 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
+ 2 8 2 0 1 0 /* GTX125 - CLK9 */
+ >;
+ };
+
+ pio_ucc2: ucc_pin@1 {
+ reg = <1>;
+
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 0 17 1 0 1 0 /* TxD0 */
+ 0 18 1 0 1 0 /* TxD1 */
+ 0 19 1 0 1 0 /* TxD2 */
+ 0 20 1 0 1 0 /* TxD3 */
+ 0 23 2 0 1 0 /* RxD0 */
+ 0 24 2 0 1 0 /* RxD1 */
+ 0 25 2 0 1 0 /* RxD2 */
+ 0 26 2 0 1 0 /* RxD3 */
+ 0 21 1 0 1 0 /* TX_EN */
+ 0 22 1 0 1 0 /* TX_ER */
+ 0 29 2 0 1 0 /* RX_DV */
+ 0 30 2 0 1 0 /* RX_ER */
+ 0 31 2 0 1 0 /* RX_CLK */
+ 2 2 1 0 2 0 /* GTX_CLK - CLK3 */
+ 2 3 2 0 1 0 /* GTX125 - CLK4 */
+ >;
+ };
+
+ pio_ucc4: ucc_pin@3 {
+ reg = <3>;
+
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
+ 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
+ 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
+ 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
+ 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
+ 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
+ 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
+
+ 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
+ >;
+ };
+
+ pio_ucc5: ucc_pin@4 {
+ reg = <4>;
+
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
+ 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
+ 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
+ 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
+ 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
+ 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
+ 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
+ >;
+ };
+
+ pio_ucc6: ucc_pin@5 {
+ reg = <5>;
+
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
+ 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
+ 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
+ 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
+ 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
+ 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
+ 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
+ >;
+ };
+
+ pio_ucc7: ucc_pin@6 {
+ reg = <6>;
+
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
+ 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
+ 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
+ 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
+ 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
+ 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
+ 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
+ >;
+ };
+
+ pio_ucc8: ucc_pin@7 {
+ reg = <7>;
+
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0 /* MDC */
+
+ 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
+ 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
+ 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
+ 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
+ 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
+ 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
+ 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
+
+ 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
+ >;
+ };
+
+ };
+
+ qe@100000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe";
+ ranges = <0x0 0x100000 0x100000>;
+ reg = <0x100000 0x480>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ brg-frequency = <0>; /* Filled in by U-Boot */
+ bus-frequency = <0>; /* Filled in by U-Boot */
+
+ muram@10000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
+ ranges = <0x0 0x00010000 0x0000c000>;
+
+ data-only@0 {
+ compatible = "fsl,qe-muram-data",
+ "fsl,cpm-muram-data";
+ reg = <0x0 0xc000>;
+ };
+ };
+
+ /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+ enet_estar1: ucc@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <1>;
+ reg = <0x2000 0x200>;
+ interrupts = <32>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk9";
+ phy-handle = <&phy_estar1>;
+ phy-connection-type = "rgmii-id";
+ pio-handle = <&pio_ucc1>;
+ };
+
+ /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+ enet_estar2: ucc@3000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <2>;
+ reg = <0x3000 0x200>;
+ interrupts = <33>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk4";
+ phy-handle = <&phy_estar2>;
+ phy-connection-type = "rgmii-id";
+ pio-handle = <&pio_ucc2>;
+ };
+
+ /* Piggy2 (UCC4, MDIO 0x00, RMII) */
+ enet_piggy2: ucc@3200 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <4>;
+ reg = <0x3200 0x200>;
+ interrupts = <35>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk17";
+ phy-handle = <&phy_piggy2>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc4>;
+ };
+
+ /* Eth-1 (UCC5, MDIO 0x08, RMII) */
+ enet_eth1: ucc@2400 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <5>;
+ reg = <0x2400 0x200>;
+ interrupts = <40>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
+ phy-handle = <&phy_eth1>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc5>;
+ };
+
+ /* Eth-2 (UCC6, MDIO 0x09, RMII) */
+ enet_eth2: ucc@3400 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <6>;
+ reg = <0x3400 0x200>;
+ interrupts = <41>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
+ phy-handle = <&phy_eth2>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc6>;
+ };
+
+ /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+ enet_eth3: ucc@2600 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <7>;
+ reg = <0x2600 0x200>;
+ interrupts = <42>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
+ phy-handle = <&phy_eth3>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc7>;
+ };
+
+ /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+ enet_eth4: ucc@3600 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <8>;
+ reg = <0x3600 0x200>;
+ interrupts = <43>;
+ interrupt-parent = <&qeic>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ rx-clock-name = "none";
+ tx-clock-name = "clk16";
+ phy-handle = <&phy_eth4>;
+ phy-connection-type = "rmii";
+ pio-handle = <&pio_ucc8>;
+ };
+
+ mdio@3320 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3320 0x18>;
+ compatible = "fsl,ucc-mdio";
+
+ /* Piggy2 (UCC4, MDIO 0x00, RMII) */
+ phy_piggy2: ethernet-phy@00 {
+ reg = <0x0>;
+ };
+
+ /* Eth-1 (UCC5, MDIO 0x08, RMII) */
+ phy_eth1: ethernet-phy@08 {
+ reg = <0x08>;
+ };
+
+ /* Eth-2 (UCC6, MDIO 0x09, RMII) */
+ phy_eth2: ethernet-phy@09 {
+ reg = <0x09>;
+ };
+
+ /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
+ phy_eth3: ethernet-phy@0a {
+ reg = <0x0a>;
+ };
+
+ /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
+ phy_eth4: ethernet-phy@0b {
+ reg = <0x0b>;
+ };
+
+ /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
+ phy_estar1: ethernet-phy@10 {
+ interrupt-parent = <&ipic>;
+ interrupts = <17 0x8>;
+ reg = <0x10>;
+ };
+
+ /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
+ phy_estar2: ethernet-phy@11 {
+ interrupt-parent = <&ipic>;
+ interrupts = <18 0x8>;
+ reg = <0x11>;
+ };
+ };
+
+ qeic: interrupt-controller@80 {
+ interrupt-controller;
+ compatible = "fsl,qe-ic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x80 0x80>;
+ interrupts = <32 8 33 8>;
+ interrupt-parent = <&ipic>;
+ };
+ };
+ };
+
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
+ "simple-bus";
+ reg = <0xe0005000 0xd8>;
+ ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */
+
+ flash@f0000000,0 {
+ compatible = "cfi-flash";
+ /*
+ * The Intel P30 chip has 2 non-identical chips on
+ * one die, so we need to define 2 seperate regions
+ * that are scanned by physmap_of independantly.
+ */
+ reg = <0 0x00000000 0x02000000
+ 0 0x02000000 0x02000000>; /* Filled in by U-Boot */
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x40000>;
+ };
+ partition@40000 {
+ label = "env";
+ reg = <0x40000 0x40000>;
+ };
+ partition@80000 {
+ label = "dtb";
+ reg = <0x80000 0x20000>;
+ };
+ partition@a0000 {
+ label = "kernel";
+ reg = <0xa0000 0x300000>;
+ };
+ partition@3a0000 {
+ label = "ramdisk";
+ reg = <0x3a0000 0x800000>;
+ };
+ partition@ba0000 {
+ label = "user";
+ reg = <0xba0000 0x3460000>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig
new file mode 100644
index 0000000..bf0853f
--- /dev/null
+++ b/arch/powerpc/configs/83xx/kmeter1_defconfig
@@ -0,0 +1,908 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28
+# Fri Apr 3 10:34:33 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+# CONFIG_FSL_EMB_PERFMON is not set
+# CONFIG_ALTIVEC is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# Platform support
+#
+CONFIG_PPC_MULTIPLATFORM=y
+CONFIG_CLASSIC32=y
+# CONFIG_PPC_CHRP is not set
+# CONFIG_MPC5121_ADS is not set
+# CONFIG_MPC5121_GENERIC is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PQ2ADS is not set
+CONFIG_PPC_83xx=y
+# CONFIG_MPC831x_RDB is not set
+# CONFIG_MPC832x_MDS is not set
+# CONFIG_MPC832x_RDB is not set
+# CONFIG_MPC834x_MDS is not set
+# CONFIG_MPC834x_ITX is not set
+# CONFIG_MPC836x_MDS is not set
+# CONFIG_MPC836x_RDK is not set
+# CONFIG_MPC837x_MDS is not set
+# CONFIG_MPC837x_RDB is not set
+# CONFIG_SBC834x is not set
+# CONFIG_ASP834x is not set
+CONFIG_KMETER1=y
+# CONFIG_PPC_86xx is not set
+# CONFIG_EMBEDDED6xx is not set
+CONFIG_IPIC=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+CONFIG_QUICC_ENGINE=y
+# CONFIG_QE_GPIO is not set
+# CONFIG_FSL_ULI1575 is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+# CONFIG_PREEMPT_RCU is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_KEXEC is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_FSL_SOC=y
+CONFIG_PPC_PCI_CHOICE=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=y
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+CONFIG_MTD_PHRAM=y
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+CONFIG_MTD_UBI_DEBUG=y
+# CONFIG_MTD_UBI_DEBUG_MSG is not set
+# CONFIG_MTD_UBI_DEBUG_PARANOID is not set
+# CONFIG_MTD_UBI_DEBUG_DISABLE_BGT is not set
+# CONFIG_MTD_UBI_DEBUG_USERSPACE_IO is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES is not set
+# CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES is not set
+
+#
+# Additional UBI debugging messages
+#
+# CONFIG_MTD_UBI_DEBUG_MSG_BLD is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_EBA is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_WL is not set
+# CONFIG_MTD_UBI_DEBUG_MSG_IO is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_GIANFAR is not set
+CONFIG_UCC_GETH=y
+# CONFIG_UGETH_MAGIC_PACKET is not set
+# CONFIG_UGETH_FILTERING is not set
+# CONFIG_UGETH_TX_ON_DEMAND is not set
+# CONFIG_MV643XX_ETH is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_WAN=y
+CONFIG_HDLC=y
+# CONFIG_HDLC_RAW is not set
+# CONFIG_HDLC_RAW_ETH is not set
+# CONFIG_HDLC_CISCO is not set
+# CONFIG_HDLC_FR is not set
+# CONFIG_HDLC_PPP is not set
+
+#
+# X.25/LAPB support is disabled
+#
+CONFIG_HDLC_KM=y
+CONFIG_FS_UCC_HDLC=y
+# CONFIG_DLCI is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_MPPE is not set
+CONFIG_PPPOE=y
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SERIAL_QE is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_BOOTCOUNT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_MCU_MPC8349EMITX is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_REGULATOR is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+CONFIG_UIO=y
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_UBIFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+CONFIG_UCC_FAST=y
+CONFIG_UCC=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_IRQSTACKS is not set
+# CONFIG_VIRQ_DEBUG is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_PPC_CLOCK is not set
+CONFIG_PPC_LIB_RHEAP=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 437d29a..083ebee 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -96,6 +96,13 @@ config ASP834x
This enables support for the Analogue & Micro ASP 83xx
board.
+config KMETER1
+ bool "Keymile KMETER1"
+ select DEFAULT_UIMAGE
+ select QUICC_ENGINE
+ help
+ This enables support for the Keymile KMETER1 board.
+
endif
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index 051777c..e139c36 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o
obj-$(CONFIG_SBC834x) += sbc834x.o
obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o
obj-$(CONFIG_ASP834x) += asp834x.o
+obj-$(CONFIG_KMETER1) += kmeter1.o
diff --git a/arch/powerpc/platforms/83xx/kmeter1.c b/arch/powerpc/platforms/83xx/kmeter1.c
new file mode 100644
index 0000000..dca9df9
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/kmeter1.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2008 DENX Software Engineering GmbH
+ * Author: Heiko Schocher <hs@denx.de>
+ *
+ * Description:
+ * Keymile KMETER1 board specific routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+
+#include "mpc83xx.h"
+
+#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init kmeter1_setup_arch(void)
+{
+ struct device_node *np;
+
+ if (ppc_md.progress)
+ ppc_md.progress("kmeter1_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
+ mpc83xx_add_bridge(np);
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+ qe_reset();
+
+ np = of_find_node_by_name(NULL, "par_io");
+ if (np != NULL) {
+ par_io_init(np);
+ of_node_put(np);
+
+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+ par_io_of_config(np);
+ }
+
+ np = of_find_compatible_node(NULL, "network", "ucc_geth");
+ if (np != NULL) {
+ uint svid;
+
+ /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
+ svid = mfspr(SPRN_SVR);
+ if (SVR_REV(svid) == 0x0021) {
+ struct device_node *np_par;
+ struct resource res;
+ void __iomem *base;
+ int ret;
+
+ np_par = of_find_node_by_name(NULL, "par_io");
+ if (np_par == NULL) {
+ printk(KERN_WARNING "%s couldn;t find par_io node\n",
+ __func__);
+ return;
+ }
+ /* Map Parallel I/O ports registers */
+ ret = of_address_to_resource(np_par, 0, &res);
+ if (ret) {
+ printk(KERN_WARNING "%s couldn;t map par_io registers\n",
+ __func__);
+ return;
+ }
+ base = ioremap(res.start, res.end - res.start + 1);
+
+ /*
+ * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
+ * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+ */
+ setbits32((base + 0xa8), 0x0c003000);
+
+ /*
+ * IMMR + 0x14AC[20:27] = 10101010
+ * (data delay for both UCC's)
+ */
+ clrsetbits_be32((base + 0xac), 0xff0, 0xaa0);
+ iounmap(base);
+ of_node_put(np_par);
+ }
+ of_node_put(np);
+ }
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+static struct of_device_id kmeter_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ { .compatible = "simple-bus", },
+ { .type = "qe", },
+ { .compatible = "fsl,qe", },
+ {},
+};
+
+static int __init kmeter_declare_of_platform_devices(void)
+{
+ /* Publish the QE devices */
+ of_platform_bus_probe(NULL, kmeter_ids, NULL);
+
+ return 0;
+}
+machine_device_initcall(kmeter1, kmeter_declare_of_platform_devices);
+
+static void __init kmeter1_init_IRQ(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,pq2pro-pic");
+ if (!np) {
+ np = of_find_node_by_type(NULL, "ipic");
+ if (!np)
+ return;
+ }
+
+ ipic_init(np, 0);
+
+ /* Initialize the default interrupt mapping priorities,
+ * in case the boot rom changed something on us.
+ */
+ ipic_set_default_priority();
+ of_node_put(np);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+ if (!np) {
+ np = of_find_node_by_type(NULL, "qeic");
+ if (!np)
+ return;
+ }
+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
+ of_node_put(np);
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init kmeter1_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "keymile,KMETER1");
+}
+
+define_machine(kmeter1) {
+ .name = "KMETER1",
+ .probe = kmeter1_probe,
+ .setup_arch = kmeter1_setup_arch,
+ .init_IRQ = kmeter1_init_IRQ,
+ .get_irq = ipic_get_irq,
+ .restart = mpc83xx_restart,
+ .time_init = mpc83xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.6.0.6
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply related
* Re: [PATCH 2/2] uio: add an of_genirq driver
From: Alan Cox @ 2009-06-15 8:44 UTC (permalink / raw)
To: Hans J. Koch
Cc: devicetree-discuss, Hans J. Koch, linux-kernel, linuxppc-dev,
Greg KH
In-Reply-To: <20090614234546.GJ3639@local>
> I did it that way because I saw IRQ 0 in /proc/interrupts on every PC...
>
> >
> > It is the job of the platform to map a physical IRQ 0 to some other
> > representation if it exists outside of arch specific code.
>
> Funny.
>
> > This was
> > decided some years ago and a large part of the kernel simply doesn't
> > support any notion of a real IRQ 0.
>
> Can you tell me the reason for that decision or point me to some ml archive?
The natural C way to write "No xxx" is if (!xxx) hence
if (!dev->irq) {
polling_start();
return 0;
}
The PC "IRQ 0" is the timer - which only appears in the arch code.
Alan
^ permalink raw reply
* Re: [PATCH 23/33] net/ps3: gelic - Add missing annotations
From: David Miller @ 2009-06-15 8:50 UTC (permalink / raw)
To: benh; +Cc: Geert.Uytterhoeven, linuxppc-dev, cbe-oss-dev
In-Reply-To: <1245047484.19217.39.camel@pasglop>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Mon, 15 Jun 2009 16:31:24 +1000
> On Wed, 2009-06-10 at 16:38 +0200, Geert Uytterhoeven wrote:
>> probe functions should be __devinit
>>
>> Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
>> Cc: Geoff Levand <geoffrey.levand@am.sony.com>
>
> Please send to netdev or get an ack from davem.
Acked-by: David S. Miller <davem@davemloft.net>
:-)
^ permalink raw reply
* Re: [PATCH] powerpc: Add configurable -Werror for arch/powerpc
From: Benjamin Herrenschmidt @ 2009-06-15 9:40 UTC (permalink / raw)
To: michael; +Cc: linuxppc-dev list
In-Reply-To: <1245052241.7705.78.camel@concordia>
> Currently this appears to break only one of the defconfigs, chrp32.
>
> http://kisskb.ellerman.id.au/kisskb/head/1907/
>
> And that's a legitimate error AFAICT:
>
> arch/powerpc/platforms/chrp/setup.c:378: error: the frame size of 1040 bytes is larger than 1024 bytes
>
> From:
>
> 367 void
> 368 chrp_event_scan(unsigned long unused)
> 369 {
> 370 unsigned char log[1024];
> 371 int ret = 0;
I wonder to what extent we could merge that with the pSeries
event-scan...
We can have a closer look tomorrow. In any case, stack alloc for that is
indeed fishy.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH][BUILD FAILURE 03/04] Next June 04:PPC64 randconfig [drivers/net/lance.o]
From: Benjamin Herrenschmidt @ 2009-06-15 9:43 UTC (permalink / raw)
To: subrata
Cc: Sachin P Sant, Stephen Rothwell, netdev, Linux-Kernel,
Linuxppc-dev, Linux-Next, Paul Mackerras, Balbir Singh
In-Reply-To: <1245050509.5239.11.camel@subratamodak.linux.ibm.com>
On Mon, 2009-06-15 at 12:51 +0530, Subrata Modak wrote:
> On Mon, 2009-06-15 at 17:11 +1000, Benjamin Herrenschmidt wrote:
> > On Mon, 2009-06-15 at 12:21 +0530, Subrata Modak wrote:
> >
> > > Benjamin,
> > >
> > > I am not sure whether you liked the following patch to solve the above
> > > problem. Do, you want me address some other issue(s)/fixes for this ?
> >
> > I suppose ... in fact some old PReP machines can even have ISA slots
> > iirc, but it's not going to do good with machines that have an iommu...
> >
> > IE. Nobody should use that crap, period.
>
> Great,
>
> Can you please make some changes at drivers/net/Kconfig so that this guy
> does not build for the PPC64 systems ?
When I said "that crap" I was talking about those interfaces which I
-hope- are deprecated :-)
I suspect we never really sorted out the issue of DMA mapping for old
legacy ISA stuff... pci_map_* should work to some extent, though you
have to pass it the ISA bridge pci_dev.
Maybe it's time for somebody to start exposing a -proper- abstraction
accross all platforms for that :-)
Ben.
^ permalink raw reply
* Re: [PATCH 2/2] uio: add an of_genirq driver
From: Benjamin Herrenschmidt @ 2009-06-15 9:45 UTC (permalink / raw)
To: Alan Cox
Cc: linuxppc-dev, Hans J. Koch, linux-kernel, devicetree-discuss,
Greg KH
In-Reply-To: <20090615001207.1829e7b5@lxorguk.ukuu.org.uk>
On Mon, 2009-06-15 at 00:12 +0100, Alan Cox wrote:
> > > + if (!uioinfo->irq)
> > > + uioinfo->irq = UIO_IRQ_NONE;
> >
> > Please don't do this. It's inconsistent if all other UIO drivers require
> > people to use UIO_IRQ_NONE and you also allow zero. UIO_IRQ_NONE was
> > introduced because 0 may be a legal interrupt number on some platforms.
>
> Zero is not a valid IRQ number in the kernel (except in arch specific
> depths). IRQ numbers are also *unsigned* so -1 isn't a safe definition.
>
> Zero means no IRQ. If any old UIO code is assuming otherwise it wants
> fixing.
>
> It is the job of the platform to map a physical IRQ 0 to some other
> representation if it exists outside of arch specific code. This was
> decided some years ago and a large part of the kernel simply doesn't
> support any notion of a real IRQ 0.
Right, and powerpc complies with that rule, so 0 is fine for us.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 1/6] rapidio: add common mapping APIs for RapidIO memory access
From: Li Yang @ 2009-06-15 10:38 UTC (permalink / raw)
To: Kumar Gala; +Cc: Zhang Wei, netdev, linux-kernel, davem, linuxppc-dev, akpm
In-Reply-To: <718B5524-9FB1-4835-BAEA-C5B990F78DAC@kernel.crashing.org>
On Fri, Jun 12, 2009 at 9:58 PM, Kumar Gala<galak@kernel.crashing.org> wrot=
e:
>
> On Jun 12, 2009, at 8:27 AM, Li Yang wrote:
>
>> On Thu, Jun 11, 2009 at 9:32 PM, Kumar Gala<galak@kernel.crashing.org>
>> wrote:
>>>
>>> On Jun 11, 2009, at 4:47 AM, Li Yang-R58472 wrote:
>>>
>>>>> On May 12, 2009, at 3:35 AM, Li Yang wrote:
>>>>>
>>>>>> Add the mapping functions used to support direct IO memory access of
>>>>>> rapidIO.
>>>>>>
>>>>>> Signed-off-by: Zhang Wei <zw@zh-kernel.org>
>>>>>> Signed-off-by: Li Yang <leoli@freescale.com>
>>>>>
>>>>> Use inbnd/outbnd instead of inb/outb which make one think of
>>>>> byte level io accessors.
>>>>>
>>>>> As I look at this I don't think this is the correct API. =C2=A0I
>>>>> think we should be using the DMA mapping API to hide these
>>>>> details. =C2=A0The concept of mapping like this seems to be more a
>>>>> function of FSL's Address translation/mapping unit (ATMU) than
>>>>> anything specific to the RIO bus standard.
>>>>
>>>> This is a separate RIO block level ATMU. =C2=A0Although it looks like =
the
>>>> system level ATMU, system ATMU doesn't have the knowledge of rapidIO
>>>> target device ID. =C2=A0The mapping need to be dynamic, as it's easy t=
o have
>>>> more RIO devices than the outbound windows.
>>>
>>> I understand that. =C2=A0What I'm saying is the RIO block level ATMU is=
a
>>> Freescale specific detail and not part of any standard RIO bus
>>> programming
>>> model. =C2=A0We have mapping APIs that we can connect to for this via t=
he DMA
>>> API
>>> layer.
>>
>> Ok, I see your point now. Do you mean dma_map_*() for DMA API layer?
>> But in my understanding the current dma_map_*() APIs are preparing
>> local memory for device to access which is similar to the inbound
>> case. =C2=A0Is it suitable to also use them for mapping device's space f=
or
>> CPU access? =C2=A0Can you give an example of using this API for Address
>> Translation and Mapping purpose?
>
> Yes, I meant the dma_map_*() API. =C2=A0Any system with a true IOMMU uses=
the
> dma_map_ layer as the way to do address translation.
IOMMU case is not very similar to the RapidIO scenario. RapidIO
mapping is more like PCI address space mapping.
To be specific, the DMA API return dma_addr_t not the rapidIO address
type. And they can only handle inbound mapping not both ways. I
don't think the DMA API is competent enough to be used here for RIO
mapping. Unless we have a more universal mapping API, it can be
justified to create its own API.
- Leo
^ permalink raw reply
* Re: [PATCH] powerpc: Add configurable -Werror for arch/powerpc
From: Michael Ellerman @ 2009-06-15 12:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <1245058807.12400.0.camel@pasglop>
[-- Attachment #1: Type: text/plain, Size: 1061 bytes --]
On Mon, 2009-06-15 at 19:40 +1000, Benjamin Herrenschmidt wrote:
> > Currently this appears to break only one of the defconfigs, chrp32.
> >
> > http://kisskb.ellerman.id.au/kisskb/head/1907/
> >
> > And that's a legitimate error AFAICT:
> >
> > arch/powerpc/platforms/chrp/setup.c:378: error: the frame size of 1040 bytes is larger than 1024 bytes
> >
> > From:
> >
> > 367 void
> > 368 chrp_event_scan(unsigned long unused)
> > 369 {
> > 370 unsigned char log[1024];
> > 371 int ret = 0;
>
> I wonder to what extent we could merge that with the pSeries
> event-scan...
Yeah that occured to me, someone with a chrp machine would need to test
it, do we have one?
> We can have a closer look tomorrow. In any case, stack alloc for that is
> indeed fishy.
The obvious patch to make it static doesn't fly because it's called on
every cpu via a timer, so it needs to be a per-cpu at least I think. Or
borrow the pseries trick of calling it on each cpu in succession, or
just borrow the pseries code.
cheers
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [OOPS] hugetlbfs tests with 2.6.30-rc8-git1
From: Sachin Sant @ 2009-06-15 13:00 UTC (permalink / raw)
To: michael; +Cc: Mel Gorman, linuxppc-dev
In-Reply-To: <1245027396.7705.23.camel@concordia>
[-- Attachment #1: Type: text/plain, Size: 1712 bytes --]
Michael Ellerman wrote:
> Hi Sachin,
>
> Rather than "-git7" can you tell us the actual SHA, I don't know what
> git7 is.
>
Corresponding SHA is 44b7532b8b464f606053562400719c9c21276037.
>> Here is the supporting data.
>>
>> cpu 0x1: Vector: 300 (Data Access) at [c0000000fe9b3220]
>> pc: c00000000003d620: .hpte_need_flush+0x1bc/0x2d8
>> lr: c00000000003d4d0: .hpte_need_flush+0x6c/0x2d8
>> sp: c0000000fe9b34a0
>> msr: 8000000000009032
>> dar: c0000000283b0d78
>>
>
> This address looks pretty innocuous, but I notice you have
> DEBUG_PAGEALLOC=y, so presumably that's why it's triggering.
>
> I can't see from the snippet of disassembly you posted where in the C
> code we are, can you work it out?
>
The corresponding C code is :
278: 2f 80 00 00 cmpwi cr7,r0,0
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
vaddr = hpt_va(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
27c: eb 89 80 00 ld r28,-32768(r9)
^^^^ %pc points to the above line. ^^^^^
* Check if we have an active batch on this CPU. If not, just
* flush now and return. For now, we don global invalidates
* in that case, might be worth testing the mm cpu mask though
* and decide to use local invalidates instead...
I have attached the objdump o/p for tlb_hash64.o.
I could not recreate this issue with git8 kernel
(45e3e1935e2857c54783291107d33323b3ef33c8).
Thanks
-Sachin
--
---------------------------------
Sachin Sant
IBM Linux Technology Center
India Systems and Technology Labs
Bangalore, India
---------------------------------
[-- Attachment #2: tlb_hash64_objlist --]
[-- Type: text/plain, Size: 23282 bytes --]
arch/powerpc/mm/tlb_hash64.o: file format elf64-powerpc
Disassembly of section .text:
0000000000000000 <.__flush_tlb_pending>:
* in a batch.
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
{
0: fb e1 ff f8 std r31,-8(r1)
4: 7c 08 02 a6 mflr r0
8: f8 01 00 10 std r0,16(r1)
extern const unsigned long
cpu_bit_bitmap[BITS_PER_LONG+1][BITS_TO_LONGS(NR_CPUS)];
static inline const struct cpumask *get_cpu_mask(unsigned int cpu)
{
const unsigned long *p = cpu_bit_bitmap[1 + cpu % BITS_PER_LONG];
c: e8 02 00 00 ld r0,0(r2)
10: 7c 7f 1b 78 mr r31,r3
14: fb c1 ff f0 std r30,-16(r1)
const unsigned long *src2, int nbits)
{
if (small_const_nbits(nbits))
return ! ((*src1 ^ *src2) & BITMAP_LAST_WORD_MASK(nbits));
else
return __bitmap_equal(src1, src2, nbits);
18: 38 a0 04 00 li r5,1024
1c: f8 21 ff 81 stdu r1,-128(r1)
const struct cpumask *tmp;
int i, local = 0;
i = batch->index;
tmp = cpumask_of(smp_processor_id());
20: a0 8d 00 0a lhz r4,10(r13)
24: e8 63 00 10 ld r3,16(r3)
28: 78 89 06 a0 clrldi r9,r4,58
2c: 78 84 d1 82 rldicl r4,r4,58,6
30: 39 29 00 01 addi r9,r9,1
34: 78 84 1f 24 rldicr r4,r4,3,60
38: 79 29 3e 24 rldicr r9,r9,7,56
3c: 38 63 03 10 addi r3,r3,784
40: 7c 00 4a 14 add r0,r0,r9
void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
{
const struct cpumask *tmp;
int i, local = 0;
i = batch->index;
44: eb df 00 0e lwa r30,12(r31)
48: 7c 84 00 50 subf r4,r4,r0
4c: 48 00 00 01 bl 4c <.__flush_tlb_pending+0x4c>
50: 60 00 00 00 nop
54: 7c 69 fe 70 srawi r9,r3,31
tmp = cpumask_of(smp_processor_id());
if (cpumask_equal(mm_cpumask(batch->mm), tmp))
local = 1;
if (i == 1)
58: 2f 9e 00 01 cmpwi cr7,r30,1
5c: 7d 20 1a 78 xor r0,r9,r3
60: 7c 00 48 50 subf r0,r0,r9
64: 54 00 0f fe rlwinm r0,r0,1,31,31
68: 7c 04 07 b4 extsw r4,r0
6c: 40 9e 00 28 bne- cr7,94 <.__flush_tlb_pending+0x94>
flush_hash_page(batch->vaddr[0], batch->pte[0],
70: 7c 88 23 78 mr r8,r4
74: e8 7f 0c 18 ld r3,3096(r31)
78: e8 df 12 1a lwa r6,4632(r31)
7c: e8 ff 12 1e lwa r7,4636(r31)
80: e8 9f 00 18 ld r4,24(r31)
84: e8 bf 00 20 ld r5,32(r31)
88: 48 00 00 01 bl 88 <.__flush_tlb_pending+0x88>
8c: 60 00 00 00 nop
90: 48 00 00 10 b a0 <.__flush_tlb_pending+0xa0>
batch->psize, batch->ssize, local);
else
flush_hash_range(i, local);
94: 7f c3 f3 78 mr r3,r30
98: 48 00 00 01 bl 98 <.__flush_tlb_pending+0x98>
9c: 60 00 00 00 nop
batch->index = 0;
}
a0: 38 21 00 80 addi r1,r1,128
if (i == 1)
flush_hash_page(batch->vaddr[0], batch->pte[0],
batch->psize, batch->ssize, local);
else
flush_hash_range(i, local);
batch->index = 0;
a4: 38 00 00 00 li r0,0
a8: f8 1f 00 08 std r0,8(r31)
}
ac: e8 01 00 10 ld r0,16(r1)
b0: eb c1 ff f0 ld r30,-16(r1)
b4: 7c 08 03 a6 mtlr r0
b8: eb e1 ff f8 ld r31,-8(r1)
bc: 4e 80 00 20 blr
00000000000000c0 <.hpte_need_flush>:
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
c0: fa c1 ff b0 std r22,-80(r1)
c4: 7c 08 02 a6 mflr r0
c8: f8 01 00 10 std r0,16(r1)
* NOTE: when using special 64K mappings in 4K environment like
* for SPEs, we obtain the page size from the slice, which thus
* must still exist (and thus the VMA not reused) at the time
* of this call
*/
if (huge) {
cc: 2f a7 00 00 cmpdi cr7,r7,0
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
d0: fb 21 ff c8 std r25,-56(r1)
#else
BUG();
psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
#endif
} else
psize = pte_pagesize_index(mm, addr, pte);
d4: 6c c0 10 00 xoris r0,r6,4096
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
d8: fb 41 ff d0 std r26,-48(r1)
dc: 7c d9 33 78 mr r25,r6
e0: fb 61 ff d8 std r27,-40(r1)
e4: 7c b6 2b 78 mr r22,r5
e8: fb 81 ff e0 std r28,-32(r1)
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
ec: eb 82 00 08 ld r28,8(r2)
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
f0: fb c1 ff f0 std r30,-16(r1)
#else
BUG();
psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
#endif
} else
psize = pte_pagesize_index(mm, addr, pte);
f4: 78 1b 27 e2 rldicl r27,r0,36,63
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
f8: fb e1 ff f8 std r31,-8(r1)
fc: 7c 7a 1b 78 mr r26,r3
100: fa e1 ff b8 std r23,-72(r1)
i = batch->index;
/* We mask the address for the base page size. Huge pages will
* have applied their own masking already
*/
addr &= PAGE_MASK;
104: 78 9f 03 e4 rldicr r31,r4,0,47
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
108: fb 01 ff c0 std r24,-64(r1)
10c: fb a1 ff e8 std r29,-24(r1)
110: f8 21 ff 41 stdu r1,-192(r1)
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
114: ea ed 00 40 ld r23,64(r13)
118: 7f dc ba 14 add r30,r28,r23
unsigned int psize;
int ssize;
real_pte_t rpte;
int i;
i = batch->index;
11c: eb 1e 00 08 ld r24,8(r30)
* NOTE: when using special 64K mappings in 4K environment like
* for SPEs, we obtain the page size from the slice, which thus
* must still exist (and thus the VMA not reused) at the time
* of this call
*/
if (huge) {
120: 41 9e 00 14 beq- cr7,134 <.hpte_need_flush+0x74>
#ifdef CONFIG_HUGETLB_PAGE
psize = get_slice_psize(mm, addr);;
124: 7f e4 fb 78 mr r4,r31
128: 48 00 00 01 bl 128 <.hpte_need_flush+0x68>
12c: 60 00 00 00 nop
130: 7c 7b 1b 78 mr r27,r3
#endif
} else
psize = pte_pagesize_index(mm, addr, pte);
/* Build full vaddr */
if (!is_kernel_addr(addr)) {
134: e8 02 00 10 ld r0,16(r2)
138: 7f bf 00 40 cmpld cr7,r31,r0
13c: 41 9d 00 a8 bgt- cr7,1e4 <.hpte_need_flush+0x124>
/* Returns the segment size indicator for a user address */
static inline int user_segment_size(unsigned long addr)
{
/* Use 1T segments if possible for addresses >= 1T */
if (addr >= (1UL << SID_SHIFT_1T))
140: 38 00 ff ff li r0,-1
144: 3b a0 00 00 li r29,0
148: 78 00 06 00 clrldi r0,r0,24
14c: 7f bf 00 40 cmpld cr7,r31,r0
150: 40 9d 00 0c ble- cr7,15c <.hpte_need_flush+0x9c>
return mmu_highuser_ssize;
154: e9 22 00 18 ld r9,24(r2)
158: eb a9 00 02 lwa r29,0(r9)
/* This is only valid for user addresses (which are below 2^44) */
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
int ssize)
{
if (ssize == MMU_SEGSIZE_256M)
15c: 2f bd 00 00 cmpdi cr7,r29,0
ssize = user_segment_size(addr);
vsid = get_vsid(mm->context.id, addr, ssize);
160: e9 7a 03 90 ld r11,912(r26)
164: 40 9e 00 3c bne- cr7,1a0 <.hpte_need_flush+0xe0>
return vsid_scramble((context << USER_ESID_BITS)
168: 79 6b 83 e4 rldicr r11,r11,16,47
16c: 7b e0 27 02 rldicl r0,r31,36,28
170: 3d 20 0b f6 lis r9,3062
174: 7c 00 5b 78 or r0,r0,r11
178: 61 29 e6 1b ori r9,r9,58907
17c: 7c 00 49 d2 mulld r0,r0,r9
| (ea >> SID_SHIFT), 256M);
180: 78 09 07 00 clrldi r9,r0,28
184: 78 00 e1 20 rldicl r0,r0,28,36
188: 7d 29 02 14 add r9,r9,r0
18c: 38 09 00 01 addi r0,r9,1
190: 78 00 e1 20 rldicl r0,r0,28,36
194: 7c 00 4a 14 add r0,r0,r9
198: 78 09 07 00 clrldi r9,r0,28
19c: 48 00 00 38 b 1d4 <.hpte_need_flush+0x114>
return vsid_scramble((context << USER_ESID_BITS_1T)
1a0: 79 6b 26 e4 rldicr r11,r11,4,59
1a4: 7b e0 c2 20 rldicl r0,r31,24,40
1a8: 3d 20 00 bf lis r9,191
1ac: 7c 00 5b 78 or r0,r0,r11
1b0: 61 29 50 d9 ori r9,r9,20697
1b4: 7c 00 49 d2 mulld r0,r0,r9
| (ea >> SID_SHIFT_1T), 1T);
1b8: 78 09 02 20 clrldi r9,r0,40
1bc: 78 00 46 02 rldicl r0,r0,40,24
1c0: 7d 29 02 14 add r9,r9,r0
1c4: 38 09 00 01 addi r0,r9,1
1c8: 78 00 46 02 rldicl r0,r0,40,24
1cc: 7c 00 4a 14 add r0,r0,r9
1d0: 78 09 02 20 clrldi r9,r0,40
WARN_ON(vsid == 0);
1d4: 7d 20 00 74 cntlzd r0,r9
1d8: 78 00 d1 82 rldicl r0,r0,58,6
1dc: 0b 00 00 00 tdnei r0,0
1e0: 48 00 00 70 b 250 <.hpte_need_flush+0x190>
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
1e4: e9 22 00 20 ld r9,32(r2)
1e8: eb a9 00 02 lwa r29,0(r9)
#endif /* 1 */
/* This is only valid for addresses >= PAGE_OFFSET */
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
{
if (ssize == MMU_SEGSIZE_256M)
1ec: 2f bd 00 00 cmpdi cr7,r29,0
1f0: 40 9e 00 34 bne- cr7,224 <.hpte_need_flush+0x164>
return vsid_scramble(ea >> SID_SHIFT, 256M);
1f4: 3d 20 0b f6 lis r9,3062
1f8: 7b e0 27 02 rldicl r0,r31,36,28
1fc: 61 29 e6 1b ori r9,r9,58907
200: 7c 00 49 d2 mulld r0,r0,r9
204: 78 09 07 00 clrldi r9,r0,28
208: 78 00 e1 20 rldicl r0,r0,28,36
20c: 7d 29 02 14 add r9,r9,r0
210: 38 09 00 01 addi r0,r9,1
214: 78 00 e1 20 rldicl r0,r0,28,36
218: 7c 00 4a 14 add r0,r0,r9
21c: 78 09 07 00 clrldi r9,r0,28
220: 48 00 00 38 b 258 <.hpte_need_flush+0x198>
return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
224: 3d 20 00 bf lis r9,191
228: 7b e0 c2 20 rldicl r0,r31,24,40
22c: 61 29 50 d9 ori r9,r9,20697
230: 7c 00 49 d2 mulld r0,r0,r9
234: 78 09 02 20 clrldi r9,r0,40
238: 78 00 46 02 rldicl r0,r0,40,24
23c: 7d 29 02 14 add r9,r9,r0
240: 38 09 00 01 addi r0,r9,1
244: 78 00 46 02 rldicl r0,r0,40,24
248: 7c 00 4a 14 add r0,r0,r9
24c: 78 09 02 20 clrldi r9,r0,40
* Build a VA given VSID, EA and segment size
*/
static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
int ssize)
{
if (ssize == MMU_SEGSIZE_256M)
250: 2f bd 00 00 cmpdi cr7,r29,0
254: 40 9e 00 10 bne- cr7,264 <.hpte_need_flush+0x1a4>
return (vsid << 28) | (ea & 0xfffffffUL);
258: 79 29 e0 e4 rldicr r9,r9,28,35
25c: 7b e0 01 20 clrldi r0,r31,36
260: 48 00 00 0c b 26c <.hpte_need_flush+0x1ac>
return (vsid << 40) | (ea & 0xffffffffffUL);
264: 79 29 45 c6 rldicr r9,r9,40,23
268: 7b e0 06 00 clrldi r0,r31,24
26c: 7d 3f 03 78 or r31,r9,r0
* Check if we have an active batch on this CPU. If not, just
* flush now and return. For now, we don global invalidates
* in that case, might be worth testing the mm cpu mask though
* and decide to use local invalidates instead...
*/
if (!batch->active) {
270: 7c 1c b8 2e lwzx r0,r28,r23
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
vaddr = hpt_va(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
274: 3d 36 00 01 addis r9,r22,1
* Check if we have an active batch on this CPU. If not, just
* flush now and return. For now, we don global invalidates
* in that case, might be worth testing the mm cpu mask though
* and decide to use local invalidates instead...
*/
if (!batch->active) {
278: 2f 80 00 00 cmpwi cr7,r0,0
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
vaddr = hpt_va(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
27c: eb 89 80 00 ld r28,-32768(r9)
* Check if we have an active batch on this CPU. If not, just
* flush now and return. For now, we don global invalidates
* in that case, might be worth testing the mm cpu mask though
* and decide to use local invalidates instead...
*/
if (!batch->active) {
280: 40 9e 00 28 bne- cr7,2a8 <.hpte_need_flush+0x1e8>
flush_hash_page(vaddr, rpte, psize, ssize, 0);
284: 7f e3 fb 78 mr r3,r31
288: 7f 24 cb 78 mr r4,r25
28c: 7f 85 e3 78 mr r5,r28
290: 7f 66 07 b4 extsw r6,r27
294: 7f a7 eb 78 mr r7,r29
298: 39 00 00 00 li r8,0
29c: 48 00 00 01 bl 29c <.hpte_need_flush+0x1dc>
2a0: 60 00 00 00 nop
2a4: 48 00 00 bc b 360 <.hpte_need_flush+0x2a0>
* will change mid stream.
*
* We also need to ensure only one page size is present in a given
* batch
*/
if (i != 0 && (mm != batch->mm || batch->psize != psize ||
2a8: 7f 0b 07 b5 extsw. r11,r24
2ac: 41 82 00 30 beq- 2dc <.hpte_need_flush+0x21c>
2b0: e8 1e 00 10 ld r0,16(r30)
2b4: 7f ba 00 00 cmpd cr7,r26,r0
2b8: 40 9e 00 1c bne- cr7,2d4 <.hpte_need_flush+0x214>
2bc: 80 1e 12 18 lwz r0,4632(r30)
2c0: 7f 80 d8 00 cmpw cr7,r0,r27
2c4: 40 9e 00 10 bne- cr7,2d4 <.hpte_need_flush+0x214>
2c8: 80 1e 12 1c lwz r0,4636(r30)
2cc: 7f 80 e8 00 cmpw cr7,r0,r29
2d0: 41 9e 00 1c beq- cr7,2ec <.hpte_need_flush+0x22c>
batch->ssize != ssize)) {
__flush_tlb_pending(batch);
2d4: 7f c3 f3 78 mr r3,r30
2d8: 48 00 00 01 bl 2d8 <.hpte_need_flush+0x218>
i = 0;
}
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
2dc: 39 60 00 00 li r11,0
batch->ssize != ssize)) {
__flush_tlb_pending(batch);
i = 0;
}
if (i == 0) {
batch->mm = mm;
2e0: fb 5e 00 10 std r26,16(r30)
batch->psize = psize;
2e4: 93 7e 12 18 stw r27,4632(r30)
batch->ssize = ssize;
2e8: 93 be 12 1c stw r29,4636(r30)
}
batch->pte[i] = rpte;
batch->vaddr[i] = vaddr;
batch->index = ++i;
2ec: 38 0b 00 01 addi r0,r11,1
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
2f0: 39 2b 00 01 addi r9,r11,1
batch->vaddr[i] = vaddr;
2f4: 39 6b 01 82 addi r11,r11,386
batch->index = ++i;
2f8: 7c 00 07 b4 extsw r0,r0
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
2fc: 79 29 26 e4 rldicr r9,r9,4,59
batch->vaddr[i] = vaddr;
300: 79 6b 1f 24 rldicr r11,r11,3,60
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
304: 7d 3e 4a 14 add r9,r30,r9
batch->vaddr[i] = vaddr;
308: 7d 7e 5a 14 add r11,r30,r11
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
30c: fb 29 00 08 std r25,8(r9)
batch->vaddr[i] = vaddr;
batch->index = ++i;
if (i >= PPC64_TLB_BATCH_NR)
310: 2f 80 00 bf cmpwi cr7,r0,191
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
314: fb 89 00 10 std r28,16(r9)
batch->vaddr[i] = vaddr;
318: fb eb 00 08 std r31,8(r11)
batch->index = ++i;
31c: f8 1e 00 08 std r0,8(r30)
if (i >= PPC64_TLB_BATCH_NR)
320: 40 9d 00 40 ble- cr7,360 <.hpte_need_flush+0x2a0>
__flush_tlb_pending(batch);
}
324: 38 21 00 c0 addi r1,r1,192
}
batch->pte[i] = rpte;
batch->vaddr[i] = vaddr;
batch->index = ++i;
if (i >= PPC64_TLB_BATCH_NR)
__flush_tlb_pending(batch);
328: 7f c3 f3 78 mr r3,r30
}
32c: e8 01 00 10 ld r0,16(r1)
330: ea c1 ff b0 ld r22,-80(r1)
334: 7c 08 03 a6 mtlr r0
338: ea e1 ff b8 ld r23,-72(r1)
33c: eb 01 ff c0 ld r24,-64(r1)
340: eb 21 ff c8 ld r25,-56(r1)
344: eb 41 ff d0 ld r26,-48(r1)
348: eb 61 ff d8 ld r27,-40(r1)
34c: eb 81 ff e0 ld r28,-32(r1)
350: eb a1 ff e8 ld r29,-24(r1)
354: eb c1 ff f0 ld r30,-16(r1)
358: eb e1 ff f8 ld r31,-8(r1)
}
batch->pte[i] = rpte;
batch->vaddr[i] = vaddr;
batch->index = ++i;
if (i >= PPC64_TLB_BATCH_NR)
__flush_tlb_pending(batch);
35c: 48 00 00 00 b 35c <.hpte_need_flush+0x29c>
}
360: 38 21 00 c0 addi r1,r1,192
364: e8 01 00 10 ld r0,16(r1)
368: ea c1 ff b0 ld r22,-80(r1)
36c: 7c 08 03 a6 mtlr r0
370: ea e1 ff b8 ld r23,-72(r1)
374: eb 01 ff c0 ld r24,-64(r1)
378: eb 21 ff c8 ld r25,-56(r1)
37c: eb 41 ff d0 ld r26,-48(r1)
380: eb 61 ff d8 ld r27,-40(r1)
384: eb 81 ff e0 ld r28,-32(r1)
388: eb a1 ff e8 ld r29,-24(r1)
38c: eb c1 ff f0 ld r30,-16(r1)
390: eb e1 ff f8 ld r31,-8(r1)
394: 4e 80 00 20 blr
0000000000000398 <.__flush_hash_table_range>:
*/
#ifdef CONFIG_HOTPLUG
void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
398: fb 81 ff e0 std r28,-32(r1)
39c: 7c 08 02 a6 mflr r0
3a0: fb c1 ff f0 std r30,-16(r1)
unsigned long flags;
start = _ALIGN_DOWN(start, PAGE_SIZE);
end = _ALIGN_UP(end, PAGE_SIZE);
3a4: 3c a5 00 01 addis r5,r5,1
*/
#ifdef CONFIG_HOTPLUG
void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
3a8: f8 01 00 10 std r0,16(r1)
3ac: 7c 7e 1b 78 mr r30,r3
3b0: fb a1 ff e8 std r29,-24(r1)
unsigned long flags;
start = _ALIGN_DOWN(start, PAGE_SIZE);
end = _ALIGN_UP(end, PAGE_SIZE);
3b4: 38 a5 ff ff addi r5,r5,-1
*/
#ifdef CONFIG_HOTPLUG
void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
3b8: fb e1 ff f8 std r31,-8(r1)
3bc: f8 21 ff 71 stdu r1,-144(r1)
unsigned long flags;
start = _ALIGN_DOWN(start, PAGE_SIZE);
end = _ALIGN_UP(end, PAGE_SIZE);
3c0: 78 bc 03 e4 rldicr r28,r5,0,47
BUG_ON(!mm->pgd);
3c4: e8 03 00 48 ld r0,72(r3)
3c8: 7c 00 00 74 cntlzd r0,r0
3cc: 78 00 d1 82 rldicl r0,r0,58,6
3d0: 0b 00 00 00 tdnei r0,0
void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
unsigned long flags;
start = _ALIGN_DOWN(start, PAGE_SIZE);
3d4: 78 9f 03 e4 rldicr r31,r4,0,47
static inline unsigned long raw_local_irq_disable(void)
{
unsigned long flags, zero;
__asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
3d8: 38 00 00 00 li r0,0
3dc: 8b ad 01 da lbz r29,474(r13)
3e0: 98 0d 01 da stb r0,474(r13)
static inline void arch_enter_lazy_mmu_mode(void)
{
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
batch->active = 1;
3e4: 38 00 00 01 li r0,1
3e8: e9 6d 00 40 ld r11,64(r13)
#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
static inline void arch_enter_lazy_mmu_mode(void)
{
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
3ec: e9 22 00 08 ld r9,8(r2)
batch->active = 1;
3f0: 7c 09 59 2e stwx r0,r9,r11
3f4: 48 00 00 58 b 44c <.__flush_hash_table_range+0xb4>
pte_t *pt = NULL;
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
3f8: e9 3e 00 48 ld r9,72(r30)
3fc: 7c 09 00 2a ldx r0,r9,r0
400: 2f a0 00 00 cmpdi cr7,r0,0
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
404: 78 09 05 a4 rldicr r9,r0,0,54
pte_t *pt = NULL;
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
408: 41 9e 00 40 beq- cr7,448 <.__flush_hash_table_range+0xb0>
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
40c: 7d 2b 48 2a ldx r9,r11,r9
pt = pte_offset_kernel(pm, ea);
410: 7b e0 85 22 rldicl r0,r31,48,52
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
414: 2f a9 00 00 cmpdi cr7,r9,0
pt = pte_offset_kernel(pm, ea);
418: 78 0b 1f 24 rldicr r11,r0,3,60
41c: 79 26 05 a4 rldicr r6,r9,0,54
arch_enter_lazy_mmu_mode();
for (; start < end; start += PAGE_SIZE) {
pte_t *ptep = find_linux_pte(mm->pgd, start);
unsigned long pte;
if (ptep == NULL)
420: 7c a6 5a 15 add. r5,r6,r11
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
424: 41 9e 00 24 beq- cr7,448 <.__flush_hash_table_range+0xb0>
428: 41 c2 00 20 beq- 448 <.__flush_hash_table_range+0xb0>
continue;
pte = pte_val(*ptep);
42c: 7c c6 58 2a ldx r6,r6,r11
if (!(pte & _PAGE_HASHPTE))
430: 54 c0 01 27 rlwinm. r0,r6,0,4,19
434: 41 82 00 14 beq- 448 <.__flush_hash_table_range+0xb0>
continue;
hpte_need_flush(mm, start, ptep, pte, 0);
438: 7f e4 fb 78 mr r4,r31
43c: 7f c3 f3 78 mr r3,r30
440: 38 e0 00 00 li r7,0
444: 48 00 00 01 bl 444 <.__flush_hash_table_range+0xac>
* to being hashed). This is not the most performance oriented
* way to do things but is fine for our needs here.
*/
local_irq_save(flags);
arch_enter_lazy_mmu_mode();
for (; start < end; start += PAGE_SIZE) {
448: 3f ff 00 01 addis r31,r31,1
44c: 7f bf e0 40 cmpld cr7,r31,r28
pte_t *pt = NULL;
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
450: 7b e0 c5 e0 rldicl r0,r31,24,55
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
454: 7b e9 25 22 rldicl r9,r31,36,52
pte_t *pt = NULL;
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
458: 78 00 1f 24 rldicr r0,r0,3,60
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
45c: 79 2b 1f 24 rldicr r11,r9,3,60
460: 41 9c ff 98 blt+ cr7,3f8 <.__flush_hash_table_range+0x60>
}
static inline void arch_leave_lazy_mmu_mode(void)
{
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
464: eb cd 00 40 ld r30,64(r13)
468: eb e2 00 08 ld r31,8(r2)
46c: 7c 7f f2 14 add r3,r31,r30
if (batch->index)
470: e8 03 00 08 ld r0,8(r3)
474: 2f a0 00 00 cmpdi cr7,r0,0
478: 41 9e 00 08 beq- cr7,480 <.__flush_hash_table_range+0xe8>
__flush_tlb_pending(batch);
47c: 48 00 00 01 bl 47c <.__flush_hash_table_range+0xe4>
if (!(pte & _PAGE_HASHPTE))
continue;
hpte_need_flush(mm, start, ptep, pte, 0);
}
arch_leave_lazy_mmu_mode();
local_irq_restore(flags);
480: 2f bd 00 00 cmpdi cr7,r29,0
batch->active = 0;
484: 38 00 00 00 li r0,0
488: 38 60 00 00 li r3,0
48c: 7c 1f f1 2e stwx r0,r31,r30
490: 41 9e 00 08 beq- cr7,498 <.__flush_hash_table_range+0x100>
494: 7f a3 eb 78 mr r3,r29
498: 48 00 00 01 bl 498 <.__flush_hash_table_range+0x100>
49c: 60 00 00 00 nop
}
4a0: 38 21 00 90 addi r1,r1,144
4a4: e8 01 00 10 ld r0,16(r1)
4a8: eb 81 ff e0 ld r28,-32(r1)
4ac: 7c 08 03 a6 mtlr r0
4b0: eb a1 ff e8 ld r29,-24(r1)
4b4: eb c1 ff f0 ld r30,-16(r1)
4b8: eb e1 ff f8 ld r31,-8(r1)
4bc: 4e 80 00 20 blr
^ permalink raw reply
* Re: [PATCH] Fix oprofile sampling of marked events on POWER7
From: Maynard Johnson @ 2009-06-15 13:40 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Anton Blanchard
In-Reply-To: <49FB2EC5.4040400@us.ibm.com>
Looks like this posting got overlooked, so I'm re-posting the original patch. Ben, can you please review? BTW, Anton reported the problem that this patch fixes.
Thanks.
-Maynard
==============================================================
Description
-----------
Change ppc64 oprofile kernel driver to use the SLOT bits (MMCRA[37:39]only on
older processors where those bits are defined.
Background
----------
The performance monitor unit of the 64-bit POWER processor family has the
ability to collect accurate instruction-level samples when profiling on marked
events (i.e., "PM_MRK_<event-name>"). In processors prior to POWER6, the MMCRA
register contained "slot information" that the oprofile kernel driver used to
adjust the value latched in the SIAR at the time of a PMU interrupt. But as of
POWER6, these slot bits in MMCRA are no longer necessary for oprofile to use,
since the SIAR itself holds the accurate sampled instruction address. With
POWER6, these MMCRA slot bits were zero'ed out by hardware so oprofile's use of
these slot bits was, in effect, a NOP. But with POWER7, these bits are no
longer zero'ed out; however, they serve some other purpose rather than slot
information. Thus, using these bits on POWER7 to adjust the SIAR value results
in samples being attributed to the wrong instructions. The attached patch
changes the oprofile kernel driver to ignore these slot bits on all newer
processors starting with POWER6.
Thanks.
-Maynard
Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>
diff -paur linux/arch/powerpc/oprofile/op_model_power4.c linux-p7-oprofile-patch//arch/powerpc/oprofile/op_model_power4.c
--- linux/arch/powerpc/oprofile/op_model_power4.c 2009-05-01 08:20:21.000000000 -0500
+++ linux-p7-oprofile-patch//arch/powerpc/oprofile/op_model_power4.c 2009-05-01 08:20:05.000000000 -0500
@@ -26,6 +26,7 @@
static unsigned long reset_value[OP_MAX_COUNTER];
static int oprofile_running;
+static int use_slot_nums;
/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
static u32 mmcr0_val;
@@ -61,6 +62,12 @@ static int power4_reg_setup(struct op_co
else
mmcr0_val |= MMCR0_PROBLEM_DISABLE;
+ if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
+ __is_processor(PV_970) || __is_processor(PV_970FX) ||
+ __is_processor(PV_970MP) || __is_processor(PV_970GX) ||
+ __is_processor(PV_POWER5) || __is_processor(PV_POWER5p))
+ use_slot_nums = 1;
+
return 0;
}
@@ -206,7 +213,7 @@ static unsigned long get_pc(struct pt_re
mmcra = mfspr(SPRN_MMCRA);
- if (mmcra & MMCRA_SAMPLE_ENABLE) {
+ if (use_slot_nums && (mmcra & MMCRA_SAMPLE_ENABLE)) {
slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
if (slot > 1)
pc += 4 * (slot - 1);
^ permalink raw reply
* Re: [PATCH] powerpc: Add configurable -Werror for arch/powerpc
From: Timur Tabi @ 2009-06-15 14:54 UTC (permalink / raw)
To: michael; +Cc: linuxppc-dev list
In-Reply-To: <1245052241.7705.78.camel@concordia>
On Mon, Jun 15, 2009 at 2:50 AM, Michael Ellerman<michael@ellerman.id.au> wrote:
> arch/powerpc/platforms/chrp/setup.c:378: error: the frame size of 1040 bytes is larger than 1024 bytes
What's so bad about a frame size larger than 1024?
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* RE: [PATCH] fbdev/xilinxfb: Fix improper casting and tighen up probe path
From: John Linn @ 2009-06-15 15:16 UTC (permalink / raw)
To: Grant Likely, linuxppc-dev, linux-kernel, benh
In-Reply-To: <20090612175634.12827.12207.stgit@localhost.localdomain>
> -----Original Message-----
> From: Grant Likely [mailto:grant.likely@secretlab.ca]
> Sent: Friday, June 12, 2009 11:57 AM
> To: linuxppc-dev@ozlabs.org; linux-kernel@vger.kernel.org;
benh@kernel.crashing.org; John Linn
> Subject: [PATCH] fbdev/xilinxfb: Fix improper casting and tighen up
probe path
> =
> From: Grant Likely <grant.likely@secretlab.ca>
> =
> The xilinxfb driver is improperly casting a physical address to a
> u32, and the probe routine isn't as straight forward as it could be.
> (discovered by gcc spitting out warnings on most recent change to
> xilinxfb driver).
> =
> This patch fixes the cast and simplifies the probe path.
> =
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> =
> John, can you please test and verify this fix is correct?
I will try to test it today.
-- John
> =
> Thanks,
> g.
> =
> drivers/video/xilinxfb.c | 59
++++++++++++++++++----------------------------
> 1 files changed, 23 insertions(+), 36 deletions(-)
> =
> =
> diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
> index 7a868bd..b68b331 100644
> --- a/drivers/video/xilinxfb.c
> +++ b/drivers/video/xilinxfb.c
> @@ -124,7 +124,6 @@ struct xilinxfb_drvdata {
> registers */
> =
> dcr_host_t dcr_host;
> - unsigned int dcr_start;
> unsigned int dcr_len;
> =
> void *fb_virt; /* virt. address of the frame
buffer */
> @@ -325,8 +324,8 @@ static int xilinxfb_assign(struct device *dev,
> drvdata->regs);
> }
> /* Put a banner in the log (for DEBUG) */
> - dev_dbg(dev, "fb: phys=3D%p, virt=3D%p, size=3D%x\n",
> - (void *)drvdata->fb_phys, drvdata->fb_virt, fbsize);
> + dev_dbg(dev, "fb: phys=3D%llx, virt=3D%p, size=3D%x\n",
> + (unsigned long long)drvdata->fb_phys, drvdata->fb_virt,
fbsize);
> =
> return 0; /* success */
> =
> @@ -404,9 +403,7 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> u32 tft_access;
> struct xilinxfb_platform_data pdata;
> struct resource res;
> - int size, rc;
> - int start =3D 0, len =3D 0;
> - dcr_host_t dcr_host;
> + int size, rc, start;
> struct xilinxfb_drvdata *drvdata;
> =
> /* Copy with the default pdata (not a ptr reference!) */
> @@ -414,35 +411,39 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> =
> dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
> =
> + /* Allocate the driver data region */
> + drvdata =3D kzalloc(sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata) {
> + dev_err(&op->dev, "Couldn't allocate device private
record\n");
> + return -ENOMEM;
> + }
> +
> /*
> * To check whether the core is connected directly to DCR or PLB
> * interface and initialize the tft_access accordingly.
> */
> p =3D (u32 *)of_get_property(op->node, "xlnx,dcr-splb-slave-if",
NULL);
> -
> - if (p)
> - tft_access =3D *p;
> - else
> - tft_access =3D 0; /* For backward compatibility */
> + tft_access =3D p ? *p : 0;
> =
> /*
> * Fill the resource structure if its direct PLB interface
> * otherwise fill the dcr_host structure.
> */
> if (tft_access) {
> + drvdata->flags |=3D PLB_ACCESS_FLAG;
> rc =3D of_address_to_resource(op->node, 0, &res);
> if (rc) {
> dev_err(&op->dev, "invalid address\n");
> - return -ENODEV;
> + goto err;
> }
> -
> } else {
> + res.start =3D 0;
> start =3D dcr_resource_start(op->node, 0);
> - len =3D dcr_resource_len(op->node, 0);
> - dcr_host =3D dcr_map(op->node, start, len);
> - if (!DCR_MAP_OK(dcr_host)) {
> - dev_err(&op->dev, "invalid address\n");
> - return -ENODEV;
> + drvdata->dcr_len =3D dcr_resource_len(op->node, 0);
> + drvdata->dcr_host =3D dcr_map(op->node, start,
drvdata->len);
> + if (!DCR_MAP_OK(drvdata->dcr_host)) {
> + dev_err(&op->dev, "invalid DCR address\n");
> + goto err;
> }
> }
> =
> @@ -467,26 +468,12 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> if (of_find_property(op->node, "rotate-display", NULL))
> pdata.rotate_screen =3D 1;
> =
> - /* Allocate the driver data region */
> - drvdata =3D kzalloc(sizeof(*drvdata), GFP_KERNEL);
> - if (!drvdata) {
> - dev_err(&op->dev, "Couldn't allocate device private
record\n");
> - return -ENOMEM;
> - }
> dev_set_drvdata(&op->dev, drvdata);
> + return xilinxfb_assign(&op->dev, drvdata, res.start, &pdata);
> =
> - if (tft_access)
> - drvdata->flags |=3D PLB_ACCESS_FLAG;
> -
> - /* Arguments are passed based on the interface */
> - if (drvdata->flags & PLB_ACCESS_FLAG) {
> - return xilinxfb_assign(&op->dev, drvdata, res.start,
&pdata);
> - } else {
> - drvdata->dcr_start =3D start;
> - drvdata->dcr_len =3D len;
> - drvdata->dcr_host =3D dcr_host;
> - return xilinxfb_assign(&op->dev, drvdata, 0, &pdata);
> - }
> + err:
> + kfree(drvdata);
> + return -ENODEV;
> }
> =
> static int __devexit xilinxfb_of_remove(struct of_device *op)
> =
This email and any attachments are intended for the sole use of the named r=
ecipient(s) and contain(s) confidential information that may be proprietary=
, privileged or copyrighted under applicable law. If you are not the intend=
ed recipient, do not read, copy, or forward this email message or any attac=
hments. Delete this email message and any attachments immediately.
^ permalink raw reply
* Re: Chipselect in SPI binding with mpc5200-psc-spi
From: Kári Davíðsson @ 2009-06-15 16:36 UTC (permalink / raw)
Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <fa686aa40902130719k1d16f936o4776cff371db16ae@mail.gmail.com>
Is this true?
Grant Likely wrote:
>
> Yes, this is right. The psc_spi driver automatically registers all
> spi children that it finds in the device tree onto the SPI bus.
> Therefore registering an spi_driver() is the right thing to do.
I am writing an SPI protocol driver and I find that my driver
is never probed.
I tried to add and call to of_register_spi_devices() in the
drivers/spi/mpc52xx_psc_spi.c::mpc52xx_psc_spi_of_probe() function,
without much effect besided that the DTS node is parsed but the driver probe
is not called, actually it complains about a modalias for my node is missing.
This is with kernel 2.6.29.3.
rg
kd
^ permalink raw reply
* RE: [PATCH] fbdev/xilinxfb: Fix improper casting and tighen up probe path
From: John Linn @ 2009-06-15 17:06 UTC (permalink / raw)
To: Grant Likely, linuxppc-dev, linux-kernel, benh
In-Reply-To: <20090612175634.12827.12207.stgit@localhost.localdomain>
> -----Original Message-----
> From: Grant Likely [mailto:grant.likely@secretlab.ca]
> Sent: Friday, June 12, 2009 11:57 AM
> To: linuxppc-dev@ozlabs.org; linux-kernel@vger.kernel.org;
benh@kernel.crashing.org; John Linn
> Subject: [PATCH] fbdev/xilinxfb: Fix improper casting and tighen up
probe path
> =
> From: Grant Likely <grant.likely@secretlab.ca>
> =
> The xilinxfb driver is improperly casting a physical address to a
> u32, and the probe routine isn't as straight forward as it could be.
> (discovered by gcc spitting out warnings on most recent change to
> xilinxfb driver).
> =
> This patch fixes the cast and simplifies the probe path.
> =
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> =
> John, can you please test and verify this fix is correct?
After a small fix to get it to compile, I did some quick testing with
DCR and without and
it's working fine on the ML507.
-- John
Here's the small change to get it to compile.
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index e3d2992..596157c 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -441,7 +441,7 @@ xilinxfb_of_probe(struct of_device *op, const struct
of_device_id *match)
res.start =3D 0;
start =3D dcr_resource_start(op->node, 0);
drvdata->dcr_len =3D dcr_resource_len(op->node, 0);
- drvdata->dcr_host =3D dcr_map(op->node, start,
drvdata->len);
+ drvdata->dcr_host =3D dcr_map(op->node, start,
drvdata->dcr_len);
if (!DCR_MAP_OK(drvdata->dcr_host)) {
dev_err(&op->dev, "invalid DCR address\n");
goto err;
--
> =
> Thanks,
> g.
> =
> drivers/video/xilinxfb.c | 59
++++++++++++++++++----------------------------
> 1 files changed, 23 insertions(+), 36 deletions(-)
> =
> =
> diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
> index 7a868bd..b68b331 100644
> --- a/drivers/video/xilinxfb.c
> +++ b/drivers/video/xilinxfb.c
> @@ -124,7 +124,6 @@ struct xilinxfb_drvdata {
> registers */
> =
> dcr_host_t dcr_host;
> - unsigned int dcr_start;
> unsigned int dcr_len;
> =
> void *fb_virt; /* virt. address of the frame
buffer */
> @@ -325,8 +324,8 @@ static int xilinxfb_assign(struct device *dev,
> drvdata->regs);
> }
> /* Put a banner in the log (for DEBUG) */
> - dev_dbg(dev, "fb: phys=3D%p, virt=3D%p, size=3D%x\n",
> - (void *)drvdata->fb_phys, drvdata->fb_virt, fbsize);
> + dev_dbg(dev, "fb: phys=3D%llx, virt=3D%p, size=3D%x\n",
> + (unsigned long long)drvdata->fb_phys, drvdata->fb_virt,
fbsize);
> =
> return 0; /* success */
> =
> @@ -404,9 +403,7 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> u32 tft_access;
> struct xilinxfb_platform_data pdata;
> struct resource res;
> - int size, rc;
> - int start =3D 0, len =3D 0;
> - dcr_host_t dcr_host;
> + int size, rc, start;
> struct xilinxfb_drvdata *drvdata;
> =
> /* Copy with the default pdata (not a ptr reference!) */
> @@ -414,35 +411,39 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> =
> dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
> =
> + /* Allocate the driver data region */
> + drvdata =3D kzalloc(sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata) {
> + dev_err(&op->dev, "Couldn't allocate device private
record\n");
> + return -ENOMEM;
> + }
> +
> /*
> * To check whether the core is connected directly to DCR or PLB
> * interface and initialize the tft_access accordingly.
> */
> p =3D (u32 *)of_get_property(op->node, "xlnx,dcr-splb-slave-if",
NULL);
> -
> - if (p)
> - tft_access =3D *p;
> - else
> - tft_access =3D 0; /* For backward compatibility */
> + tft_access =3D p ? *p : 0;
> =
> /*
> * Fill the resource structure if its direct PLB interface
> * otherwise fill the dcr_host structure.
> */
> if (tft_access) {
> + drvdata->flags |=3D PLB_ACCESS_FLAG;
> rc =3D of_address_to_resource(op->node, 0, &res);
> if (rc) {
> dev_err(&op->dev, "invalid address\n");
> - return -ENODEV;
> + goto err;
> }
> -
> } else {
> + res.start =3D 0;
> start =3D dcr_resource_start(op->node, 0);
> - len =3D dcr_resource_len(op->node, 0);
> - dcr_host =3D dcr_map(op->node, start, len);
> - if (!DCR_MAP_OK(dcr_host)) {
> - dev_err(&op->dev, "invalid address\n");
> - return -ENODEV;
> + drvdata->dcr_len =3D dcr_resource_len(op->node, 0);
> + drvdata->dcr_host =3D dcr_map(op->node, start,
drvdata->len);
> + if (!DCR_MAP_OK(drvdata->dcr_host)) {
> + dev_err(&op->dev, "invalid DCR address\n");
> + goto err;
> }
> }
> =
> @@ -467,26 +468,12 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> if (of_find_property(op->node, "rotate-display", NULL))
> pdata.rotate_screen =3D 1;
> =
> - /* Allocate the driver data region */
> - drvdata =3D kzalloc(sizeof(*drvdata), GFP_KERNEL);
> - if (!drvdata) {
> - dev_err(&op->dev, "Couldn't allocate device private
record\n");
> - return -ENOMEM;
> - }
> dev_set_drvdata(&op->dev, drvdata);
> + return xilinxfb_assign(&op->dev, drvdata, res.start, &pdata);
> =
> - if (tft_access)
> - drvdata->flags |=3D PLB_ACCESS_FLAG;
> -
> - /* Arguments are passed based on the interface */
> - if (drvdata->flags & PLB_ACCESS_FLAG) {
> - return xilinxfb_assign(&op->dev, drvdata, res.start,
&pdata);
> - } else {
> - drvdata->dcr_start =3D start;
> - drvdata->dcr_len =3D len;
> - drvdata->dcr_host =3D dcr_host;
> - return xilinxfb_assign(&op->dev, drvdata, 0, &pdata);
> - }
> + err:
> + kfree(drvdata);
> + return -ENODEV;
> }
> =
> static int __devexit xilinxfb_of_remove(struct of_device *op)
> =
This email and any attachments are intended for the sole use of the named r=
ecipient(s) and contain(s) confidential information that may be proprietary=
, privileged or copyrighted under applicable law. If you are not the intend=
ed recipient, do not read, copy, or forward this email message or any attac=
hments. Delete this email message and any attachments immediately.
^ permalink raw reply related
* Re: Chipselect in SPI binding with mpc5200-psc-spi
From: Grant Likely @ 2009-06-15 17:31 UTC (permalink / raw)
To: Kári Davíðsson; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <4A3678A3.1050802@marel.com>
On Mon, Jun 15, 2009 at 10:36 AM, K=E1ri
Dav=ED=F0sson<kari.davidsson@marel.com> wrote:
> Is this true?
>
> Grant Likely wrote:
>>
>> Yes, this is right. =A0The psc_spi driver automatically registers all
>> spi children that it finds in the device tree onto the SPI bus.
>> Therefore registering an spi_driver() is the right thing to do.
>
> I am writing an SPI protocol driver and I find that my driver
> is never probed.
>
> I tried to add and call to of_register_spi_devices() in the
> drivers/spi/mpc52xx_psc_spi.c::mpc52xx_psc_spi_of_probe() function,
> without much effect besided that the DTS node is parsed but the driver pr=
obe
> is not called, actually it complains about a modalias for my node is
> missing.
What do you see when you look in /sys/bus/spi/devices? You should see
a directory for your device. What do you see in /sys/bus/spi/drivers?
In here you should see your driver. If they are both there, then you
just have a problem matching your driver name to the device name.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* [PATCH 1/3] AMCC Crypto4xx Device Driver v7
From: Shasi Pulijala @ 2009-06-15 17:25 UTC (permalink / raw)
To: herbert; +Cc: linuxppc-dev, linux-crypto
Hi,
I am re-sending this patch as a patch series of 3, I am assuming the =
earlier one did not go through the mailing lists
because it was over the size limit.
-Shasi
From: Shasi Pulijala <spulijala@amcc.com>
This is second release version for the PPC4XX Security driver that
adds aead type support and other algs to the security driver.
Signed-off-by: Shasi Pulijala <spulijala@amcc.com>
Acked-by: Loc Ho <lho@amcc.com>
---
drivers/crypto/amcc/crypto4xx_core.c | 816 =
++++++++++++++++++++++++++++++++--
drivers/crypto/amcc/crypto4xx_core.h | 92 ++++
drivers/crypto/amcc/crypto4xx_sa.c | 114 +++++
drivers/crypto/amcc/crypto4xx_sa.h | 337 ++++++++++++++-
4 files changed, 1323 insertions(+), 36 deletions(-)
diff --git a/drivers/crypto/amcc/crypto4xx_core.c =
b/drivers/crypto/amcc/crypto4xx_core.c
index 4c0dfb2..0fef1f2 100644
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -28,13 +28,18 @@
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/highmem.h>
#include <asm/dcr.h>
#include <asm/dcr-regs.h>
#include <asm/cacheflush.h>
#include <crypto/internal/hash.h>
#include <crypto/algapi.h>
#include <crypto/aes.h>
+#include <crypto/des.h>
#include <crypto/sha.h>
+#include <crypto/ctr.h>
#include "crypto4xx_reg_def.h"
#include "crypto4xx_core.h"
#include "crypto4xx_sa.h"
@@ -153,6 +158,8 @@ void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
=20
ctx->sa_in_dma_addr =3D 0;
ctx->sa_out_dma_addr =3D 0;
+ ctx->sa_in =3D NULL;
+ ctx->sa_out =3D NULL;
ctx->sa_len =3D 0;
}
=20
@@ -178,6 +185,31 @@ void crypto4xx_free_state_record(struct =
crypto4xx_ctx *ctx)
ctx->state_record_dma_addr =3D 0;
}
=20
+u32 crypto4xx_alloc_arc4_state_record(struct crypto4xx_ctx *ctx)
+{
+ ctx->arc4_state_record =3D =
dma_alloc_coherent(ctx->dev->core_dev->device,
+ sizeof(struct arc4_sr),
+ &ctx->arc4_state_record_dma_addr,
+ GFP_ATOMIC);
+ if (!ctx->arc4_state_record_dma_addr)
+ return -ENOMEM;
+
+ memset(ctx->arc4_state_record, 0, sizeof(struct arc4_sr));
+
+ return 0;
+}
+
+void crypto4xx_free_arc4_state_record(struct crypto4xx_ctx *ctx)
+{
+ if (ctx->arc4_state_record !=3D NULL) {
+ dma_free_coherent(ctx->dev->core_dev->device,
+ sizeof(struct arc4_sr),
+ ctx->arc4_state_record,
+ ctx->arc4_state_record_dma_addr);
+ }
+ ctx->arc4_state_record_dma_addr =3D 0;
+}
+
/**
* alloc memory for the gather ring
* no need to alloc buf for the ring
@@ -528,7 +560,7 @@ static u32 crypto4xx_fill_one_page(struct =
crypto4xx_device *dev,
(*idx)++;
=20
return 0;
- }
+ }
}
=20
static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
@@ -591,9 +623,25 @@ static u32 crypto4xx_copy_digest_to_dst(struct =
pd_uinfo *pd_uinfo,
struct sa_state_record *state_record =3D
(struct sa_state_record *) pd_uinfo->sr_va;
=20
- if (sa->sa_command_0.bf.hash_alg =3D=3D SA_HASH_ALG_SHA1) {
- memcpy((void *) pd_uinfo->dest_va, state_record->save_digest,
- SA_HASH_ALG_SHA1_DIGEST_SIZE);
+ switch (sa->sa_command_0.bf.hash_alg) {
+ case SA_HASH_ALG_KASUMI_f9:
+ crypto4xx_memcpy_le((void *)pd_uinfo->dest_va,
+ (u8 *)state_record->save_digest, 8);
+ break;
+ case SA_HASH_ALG_AES_XCBC_MAC_128:
+ crypto4xx_memcpy_le((void *)pd_uinfo->dest_va,
+ (u8 *) state_record->save_digest, 16);
+ break;
+ case SA_HASH_ALG_MD5:
+ crypto4xx_memcpy_le((void *)pd_uinfo->dest_va,
+ (u8 *) state_record->save_digest,
+ SA_HASH_ALG_MD5_DIGEST_SIZE);
+ break;
+ default:
+ memcpy((void *)pd_uinfo->dest_va,
+ state_record->save_digest,
+ crypto4xx_sa_hash_tbl[1][sa->sa_command_0.bf.hash_alg]);
+ break;
}
=20
return 0;
@@ -618,6 +666,57 @@ static void crypto4xx_ret_sg_desc(struct =
crypto4xx_device *dev,
}
}
=20
+void crypto4xx_append_icv_to_end(struct crypto4xx_device *dev,
+ struct scatterlist *dst,
+ struct sa_state_record *sr,
+ u32 offset,
+ u32 len)
+{
+ struct scatterlist *sg;
+ int i =3D 0;
+ u32 cp_len;
+ dma_addr_t addr;
+
+ sg =3D &dst[i];
+ while (len) {
+ while (sg->length < offset) {
+ offset -=3D sg->length;
+ i++;
+ sg =3D &sg[i];
+ }
+ /* at here, icv could be in this sg,
+ * or icv could be in the next sg
+ */
+ if (sg->length > offset) {
+ /* icv should be in middle of this sg */
+ addr =3D dma_map_page(dev->core_dev->device, sg_page(sg),
+ sg->offset,
+ sg->length, DMA_TO_DEVICE);
+ cp_len =3D (sg->length-offset >=3D len) ? len :
+ sg->length-offset;
+ len -=3D cp_len;
+ crypto4xx_memcpy_le((u32 *)(phys_to_virt(addr)
+ + offset),
+ (u8 *)sr->save_digest, cp_len);
+ } else {
+ /* start from begin of next sg*/
+ i++;
+ sg =3D &sg[i];
+ offset =3D 0;
+ addr =3D dma_map_page(dev->core_dev->device, sg_page(sg),
+ sg->offset,
+ sg->length, DMA_FROM_DEVICE);
+ cp_len =3D (sg->length >=3D len) ? len : sg->length;
+ len -=3D cp_len;
+ crypto4xx_memcpy_le((u32 *) (phys_to_virt(addr)
+ + offset),
+ (u8 *) sr->save_digest, cp_len);
+ }
+ i++;
+ sg =3D &sg[i];
+ }
+}
+
static u32 crypto4xx_ablkcipher_done(struct crypto4xx_device *dev,
struct pd_uinfo *pd_uinfo,
struct ce_pd *pd)
@@ -664,18 +763,67 @@ static u32 crypto4xx_ahash_done(struct =
crypto4xx_device *dev,
return 0;
}
=20
-static u32 crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
+static u32 crypto4xx_aead_done(struct crypto4xx_device *dev,
+ struct pd_uinfo *pd_uinfo,
+ struct ce_pd *pd)
+{
+ struct aead_request *aead_req;
+ struct crypto4xx_ctx *ctx;
+ struct scatterlist *dst;
+ dma_addr_t addr;
+ struct crypto_aead *aead;
+
+ aead_req =3D container_of(pd_uinfo->async_req,
+ struct aead_request, base);
+ aead =3D crypto_aead_reqtfm(aead_req);
+ ctx =3D crypto_tfm_ctx(aead_req->base.tfm);
+
+ if (pd_uinfo->using_sd) {
+ crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
+ pd->pd_ctl_len.bf.pkt_len,
+ aead_req->dst);
+ } else {
+ dst =3D pd_uinfo->dest_va;
+ addr =3D dma_map_page(dev->core_dev->device, sg_page(dst),
+ dst->offset,
+ dst->length, DMA_FROM_DEVICE);
+ }
+
+ if (ctx->append_icv !=3D 0) {
+ dst =3D pd_uinfo->dest_va;
+ crypto4xx_append_icv_to_end(dev, dst,
+ (struct sa_state_record *)
+ pd_uinfo->sr_va,
+ aead_req->cryptlen,
+ crypto_aead_authsize(aead));
+ }
+ crypto4xx_ret_sg_desc(dev, pd_uinfo);
+ /* call user provided callback function x */
+ if (aead_req->base.complete !=3D NULL)
+ aead_req->base.complete(&aead_req->base, 0);
+
+ return 0;
+}
+
+u32 crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
{
struct ce_pd *pd;
struct pd_uinfo *pd_uinfo;
=20
pd =3D dev->pdr + sizeof(struct ce_pd)*idx;
pd_uinfo =3D dev->pdr_uinfo + sizeof(struct pd_uinfo)*idx;
+
if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) =3D=3D
+ CRYPTO_ALG_TYPE_AEAD)
+ return crypto4xx_aead_done(dev, pd_uinfo, pd);
+ else if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) =3D=3D
CRYPTO_ALG_TYPE_ABLKCIPHER)
return crypto4xx_ablkcipher_done(dev, pd_uinfo, pd);
- else
+ else if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) =3D=3D
+ CRYPTO_ALG_TYPE_AHASH)
return crypto4xx_ahash_done(dev, pd_uinfo);
+
+ return 0;
}
=20
/**
@@ -777,12 +925,15 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
struct scatterlist *src,
struct scatterlist *dst,
unsigned int datalen,
+ struct scatterlist *assoc,
+ u32 aad_len,
void *iv, u32 iv_len)
{
struct crypto4xx_device *dev =3D ctx->dev;
dma_addr_t addr, pd_dma, sd_dma, gd_dma;
struct dynamic_sa_ctl *sa;
struct scatterlist *sg;
+ struct scatterlist *aad;
struct ce_gd *gd;
struct ce_pd *pd;
u32 num_gd, num_sd;
@@ -792,13 +943,18 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
unsigned long flags;
struct pd_uinfo *pd_uinfo =3D NULL;
unsigned int nbytes =3D datalen, idx;
- unsigned int ivlen =3D 0;
u32 gd_idx =3D 0;
+ unsigned int aadlen =3D 0;
=20
/* figure how many gd is needed */
- num_gd =3D get_sg_count(src, datalen);
- if (num_gd =3D=3D 1)
- num_gd =3D 0;
+ if (aad_len) {
+ num_gd =3D get_sg_count(assoc, aad_len) +
+ get_sg_count(src, datalen);
+ } else {
+ num_gd =3D get_sg_count(src, datalen);
+ if (num_gd =3D=3D 1)
+ num_gd =3D 0;
+ }
=20
/* figure how many sd is needed */
if (sg_is_last(dst) || ctx->is_hash) {
@@ -855,7 +1011,6 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
pd_uinfo->num_sd =3D num_sd;
=20
if (iv_len || ctx->is_hash) {
- ivlen =3D iv_len;
pd->sa =3D pd_uinfo->sa_pa;
sa =3D (struct dynamic_sa_ctl *) pd_uinfo->sa_va;
if (ctx->direction =3D=3D DIR_INBOUND)
@@ -866,8 +1021,26 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
memcpy((void *) sa + ctx->offset_to_sr_ptr,
&pd_uinfo->sr_pa, 4);
=20
- if (iv_len)
- crypto4xx_memcpy_le(pd_uinfo->sr_va, iv, iv_len);
+ if (iv_len) {
+ if (ctx->ctr_aes) {
+ /* First the nonce */
+ memcpy(pd_uinfo->sr_va, ctx->state_record,
+ CTR_RFC3686_NONCE_SIZE);
+ /* Copy the IV that is passed through
+ * each operation
+ */
+ crypto4xx_memcpy_le(pd_uinfo->sr_va +
+ CTR_RFC3686_NONCE_SIZE, iv, iv_len);
+ } else
+ crypto4xx_memcpy_le(pd_uinfo->sr_va,
+ iv, iv_len);
+ }
+ if (ctx->is_gcm || ctx->ctr_aes) {
+ u32 seq =3D 1;
+ /*For GCM and CTR(AES) algs adding the counter value*/
+ crypto4xx_memcpy_le(pd_uinfo->sr_va + 12,
+ (void *)&seq, 4);
+ }
} else {
if (ctx->direction =3D=3D DIR_INBOUND) {
pd->sa =3D ctx->sa_in_dma_addr;
@@ -888,6 +1061,35 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
/* enable gather */
sa->sa_command_0.bf.gather =3D 1;
idx =3D 0;
+ if (aad_len) {
+ aadlen =3D aad_len;
+ aad =3D assoc;
+ /* walk the sg, and setup gather array for aad*/
+ while (aadlen) {
+ sg =3D &aad[idx];
+ addr =3D dma_map_page(dev->core_dev->device,
+ sg_page(sg), sg->offset,
+ sg->length, DMA_TO_DEVICE);
+
+ gd->ptr =3D addr;
+ gd->ctl_len.len =3D sg->length;
+ gd->ctl_len.done =3D 0;
+ gd->ctl_len.ready =3D 1;
+
+ if (sg->length >=3D aadlen)
+ break;
+
+ aadlen -=3D sg->length;
+
+ gd_idx =3D get_next_gd(gd_idx);
+ gd =3D crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
+ idx++;
+ }
+ /* prepare gd for src */
+ gd_idx =3D get_next_gd(gd_idx);
+ gd =3D crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
+ }
+ idx =3D 0;
src =3D &src[0];
/* walk the sg, and setup gather array */
while (nbytes) {
@@ -972,9 +1174,10 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
}
}
=20
- sa->sa_command_1.bf.hash_crypto_offset =3D 0;
+ sa->sa_command_1.bf.hash_crypto_offset =3D (aad_len >> 2);
pd->pd_ctl.w =3D ctx->pd_ctl;
- pd->pd_ctl_len.w =3D 0x00400000 | (ctx->bypass << 24) | datalen;
+ pd->pd_ctl_len.w =3D 0x00400000 | (ctx->bypass << 24) |
+ (datalen + aad_len);
pd_uinfo->state =3D PD_ENTRY_INUSE;
wmb();
/* write any value to push engine to read a pd */
@@ -997,11 +1200,15 @@ static int crypto4xx_alg_init(struct crypto_tfm =
*tfm)
ctx->sa_in_dma_addr =3D 0;
ctx->sa_out_dma_addr =3D 0;
ctx->sa_len =3D 0;
+ ctx->is_gcm =3D 0;
+ ctx->append_icv =3D 0;
=20
if (alg->cra_type =3D=3D &crypto_ablkcipher_type)
tfm->crt_ablkcipher.reqsize =3D sizeof(struct crypto4xx_ctx);
else if (alg->cra_type =3D=3D &crypto_ahash_type)
tfm->crt_ahash.reqsize =3D sizeof(struct crypto4xx_ctx);
+ else if (alg->cra_type =3D=3D &crypto_aead_type)
+ tfm->crt_aead.reqsize =3D sizeof(struct crypto4xx_ctx);
=20
return 0;
}
@@ -1105,6 +1312,88 @@ static irqreturn_t =
crypto4xx_ce_interrupt_handler(int irq, void *data)
* Supported Crypto Algorithms
*/
struct crypto_alg crypto4xx_alg[] =3D {
+ /* Crypto DES ECB, CBC, modes */
+
+ {.cra_name =3D "cbc(des)",
+ .cra_driver_name =3D "ppc4xx-cbc-des",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D DES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D DES_KEY_SIZE,
+ .max_keysize =3D DES_KEY_SIZE,
+ .ivsize =3D DES_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_3des_cbc,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {.cra_name =3D "ecb(des)",
+ .cra_driver_name =3D "ppc4xx-ecb-des",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D DES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D DES_KEY_SIZE,
+ .max_keysize =3D DES_KEY_SIZE,
+ .setkey =3D crypto4xx_setkey_3des_ecb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+
+ /* Crypto 3DES ECB, CBC, CFB, and OFB modes */
+ {.cra_name =3D "cbc(des3_ede)",
+ .cra_driver_name =3D "ppc4xx-cbc-3des",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D DES3_EDE_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D DES3_EDE_KEY_SIZE,
+ .max_keysize =3D DES3_EDE_KEY_SIZE,
+ .ivsize =3D DES3_EDE_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_3des_cbc,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {.cra_name =3D "ecb(des3_ede)",
+ .cra_driver_name =3D "ppc4xx-ecb-3des",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D DES3_EDE_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D DES3_EDE_KEY_SIZE,
+ .max_keysize =3D DES3_EDE_KEY_SIZE,
+ .setkey =3D crypto4xx_setkey_3des_ecb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
/* Crypto AES modes */
{
.cra_name =3D "cbc(aes)",
@@ -1127,25 +1416,495 @@ struct crypto_alg crypto4xx_alg[] =3D {
}
}
},
- /* Hash SHA1 */
- {
- .cra_name =3D "sha1",
- .cra_driver_name =3D "sha1-ppc4xx",
- .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
- .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
- .cra_blocksize =3D SHA1_BLOCK_SIZE,
- .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
- .cra_alignmask =3D 0,
- .cra_type =3D &crypto_ahash_type,
- .cra_init =3D crypto4xx_sha1_alg_init,
- .cra_module =3D THIS_MODULE,
- .cra_u =3D {
+ {.cra_name =3D "ofb(aes)",
+ .cra_driver_name =3D "ppc4xx-ofb-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D AES_MIN_KEY_SIZE,
+ .max_keysize =3D AES_MAX_KEY_SIZE,
+ .ivsize =3D AES_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_aes_ofb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {.cra_name =3D "cfb(aes)",
+ .cra_driver_name =3D "ppc4xx-cfb-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D AES_MIN_KEY_SIZE,
+ .max_keysize =3D AES_MAX_KEY_SIZE,
+ .ivsize =3D AES_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_aes_cfb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ /* Crypto AES ECB, CBC, CTR, GCM, CCM, and GMAC modes */
+ {.cra_name =3D "ecb(aes)",
+ .cra_driver_name =3D "ppc4xx-ecb-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D AES_MIN_KEY_SIZE,
+ .max_keysize =3D AES_MAX_KEY_SIZE,
+ .setkey =3D crypto4xx_setkey_aes_ecb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {.cra_name =3D "rfc3686(ctr(aes))",
+ .cra_driver_name =3D "ppc4xx-ctr-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D CTR_RFC3686_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D AES_MIN_KEY_SIZE,
+ .max_keysize =3D AES_MAX_KEY_SIZE,
+ .ivsize =3D CTR_RFC3686_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_aes_ctr,
+ .encrypt =3D crypto4xx_encrypt_ctr,
+ .decrypt =3D crypto4xx_decrypt_ctr,
+ }
+ }
+ },
+ /* AEAD Algorithms */
+ {.cra_name =3D "gcm(aes)",
+ .cra_driver_name =3D "ppc4xx-gcm-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_aead_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .aead =3D {
+ .maxauthsize =3D 16,
+ .ivsize =3D 12,
+ .setkey =3D crypto4xx_setkey_aes_gcm,
+ .setauthsize =3D crypto4xx_setauthsize_aes,
+ .encrypt =3D crypto4xx_encrypt_aes_gcm,
+ .decrypt =3D crypto4xx_decrypt_aes_gcm,
+ .givencrypt =3D crypto4xx_givencrypt_aes_gcm,
+ .givdecrypt =3D crypto4xx_givdecrypt_aes_gcm,
+ }
+ }
+ },
+ {.cra_name =3D "ccm(aes)",
+ .cra_driver_name =3D "ppc4xx-ccm-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_aead_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .aead =3D {
+ .ivsize =3D AES_BLOCK_SIZE,
+ .maxauthsize =3D 16,
+ .setkey =3D crypto4xx_setkey_aes_ccm,
+ .setauthsize =3D crypto4xx_setauthsize_aes,
+ .encrypt =3D crypto4xx_encrypt_aes_ccm,
+ .decrypt =3D crypto4xx_decrypt_aes_ccm,
+ .givencrypt =3D crypto4xx_givencrypt_aes_ccm,
+ .givdecrypt =3D crypto4xx_givdecrypt_aes_ccm,
+ }
+ }
+ },
+ /* Hash MD5 */
+ {.cra_name =3D "md5",
+ .cra_driver_name =3D "ppc4xx-md5",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D 64,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_md5_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SA_HASH_ALG_MD5_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ /* Hash MD5-HMAC */
+ {.cra_name =3D "hmac(md5)",
+ .cra_driver_name =3D "ppc4xx-hmac-md5",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D 64,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SA_HASH_ALG_MD5_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_md5_hmac_setkey,
+ }
+ }
+ },
+ /* Hash SHA1, SHA2 and HMAC */
+ {.cra_name =3D "sha1",
+ .cra_driver_name =3D "ppc4xx-sha1",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA1_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha1_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA1_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha1)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha1",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA1_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
.ahash =3D {
.digestsize =3D SHA1_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha1_hmac_setkey,
+ }
+ }
+ },
+
+ {.cra_name =3D "sha224",
+ .cra_driver_name =3D "ppc4xx-sha224",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA224_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha2_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA224_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha224)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha224",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA224_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA224_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha2_hmac_setkey,
+ }
+ }
+ },
+ {.cra_name =3D "sha256",
+ .cra_driver_name =3D "ppc4xx-sha256",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA256_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha2_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA256_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha256)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha256",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA256_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA256_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha2_hmac_setkey,
+ }
+ }
+ },
+ {.cra_name =3D "sha384",
+ .cra_driver_name =3D "ppc4xx-sha384",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA384_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha2_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA384_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha384)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha384",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA384_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA384_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha2_hmac_setkey,
+ }
+ }
+ },
+ {.cra_name =3D "sha512",
+ .cra_driver_name =3D "ppc4xx-sha512",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA512_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha2_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA512_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha512)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha512",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA512_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA512_DIGEST_SIZE,
.init =3D crypto4xx_hash_init,
.update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha2_hmac_setkey,
+ }
+ }
+ },
+ /* Hash XCBC, GHASH, and Kasumi F9 */
+ {.cra_name =3D "xcbc(aes)",
+ .cra_driver_name =3D "ppc4xx-xcbc-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D 16,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
.final =3D crypto4xx_hash_final,
.digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_xcbc_setkey,
+ }
+ }
+ },
+ /* Crypto Kasumi and Kasumi F8 */
+ {.cra_name =3D "kasumi",
+ .cra_driver_name =3D "ppc4xx-kasumi",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D KASUMI_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D KASUMI_KEY_SIZE,
+ .max_keysize =3D KASUMI_KEY_SIZE,
+ .ivsize =3D KASUMI_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_kasumi_p,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {
+ .cra_name =3D "f8(kasumi)",
+ .cra_driver_name =3D "ppc4xx-f8-kasumi",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D KASUMI_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D KASUMI_KEY_SIZE,
+ .max_keysize =3D KASUMI_KEY_SIZE,
+ .ivsize =3D KASUMI_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_kasumi_f8,
+ .encrypt =3D crypto4xx_encrypt_kasumi_f8,
+ .decrypt =3D crypto4xx_decrypt_kasumi_f8,
+ }
+ }
+ },
+ {.cra_name =3D "f9(kasumi)",
+ .cra_driver_name =3D "ppc4xx-f9-kasumi",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D KASUMI_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D 8,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_kasumi_f9_digest,
+ .setkey =3D crypto4xx_kasumi_f9_setkey,
+ }
+ }
+ },
+ /* Crypto ARC4 - stateless */
+ {.cra_name =3D "ecb(arc4)",
+ .cra_driver_name =3D "ppc4xx-arc4",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D 1,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D 1,
+ .max_keysize =3D 16,
+ .setkey =3D crypto4xx_setkey_arc4,
+ .encrypt =3D crypto4xx_arc4_encrypt,
+ .decrypt =3D crypto4xx_arc4_decrypt,
+ }
+ }
+ },
+ /* Crypto ARC4 - statefull */
+ {.cra_name =3D "cbc(arc4)",
+ .cra_driver_name =3D "ppc4xx-arc4",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_BLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D 1,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D 1,
+ .max_keysize =3D 16,
+ .setkey =3D crypto4xx_setkey_arc4,
+ .encrypt =3D crypto4xx_arc4_encrypt,
+ .decrypt =3D crypto4xx_arc4_decrypt,
}
}
},
@@ -1275,7 +2034,6 @@ static int __exit crypto4xx_remove(struct =
of_device *ofdev)
crypto4xx_unregister_alg(core_dev->dev);
/* Free all allocated memory */
crypto4xx_stop_all(core_dev);
-
return 0;
}
=20
diff --git a/drivers/crypto/amcc/crypto4xx_core.h =
b/drivers/crypto/amcc/crypto4xx_core.h
index 1ef1034..f3d04b6 100644
--- a/drivers/crypto/amcc/crypto4xx_core.h
+++ b/drivers/crypto/amcc/crypto4xx_core.h
@@ -116,6 +116,8 @@ struct crypto4xx_ctx {
dma_addr_t sa_in_dma_addr;
void *sa_out;
dma_addr_t sa_out_dma_addr;
+ void *arc4_state_record;
+ dma_addr_t arc4_state_record_dma_addr;
void *state_record;
dma_addr_t state_record_dma_addr;
u32 sa_len;
@@ -125,7 +127,11 @@ struct crypto4xx_ctx {
u32 save_iv;
u32 pd_ctl_len;
u32 pd_ctl;
+ u32 append_icv;
+ u32 is_gcm;
+ u32 ctr_aes;
u32 bypass;
+ u32 init_arc4;
u32 is_hash;
u32 hash_final;
};
@@ -154,9 +160,12 @@ extern u32 crypto4xx_alloc_sa_rctx(struct =
crypto4xx_ctx *ctx,
extern void crypto4xx_free_sa_rctx(struct crypto4xx_ctx *rctx);
extern void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
extern u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx);
+extern u32 crypto4xx_alloc_arc4_state_record(struct crypto4xx_ctx =
*ctx);
+extern void crypto4xx_free_arc4_state_record(struct crypto4xx_ctx =
*ctx);
extern u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx =
*ctx);
extern u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx);
extern u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx);
+u32 get_dynamic_sa_offset_arc4_state_ptr(struct crypto4xx_ctx *ctx);
extern void crypto4xx_memcpy_le(unsigned int *dst,
const unsigned char *buf, int len);
extern u32 crypto4xx_build_pd(struct crypto_async_request *req,
@@ -164,9 +173,15 @@ extern u32 crypto4xx_build_pd(struct =
crypto_async_request *req,
struct scatterlist *src,
struct scatterlist *dst,
unsigned int datalen,
+ struct scatterlist *assoc,
+ u32 aad_len,
void *iv, u32 iv_len);
extern int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
const u8 *key, unsigned int keylen);
+extern int crypto4xx_setkey_3des_cbc(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+extern int crypto4xx_setkey_3des_ecb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
extern int crypto4xx_encrypt(struct ablkcipher_request *req);
extern int crypto4xx_decrypt(struct ablkcipher_request *req);
extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
@@ -174,4 +189,81 @@ extern int crypto4xx_hash_digest(struct =
ahash_request *req);
extern int crypto4xx_hash_final(struct ahash_request *req);
extern int crypto4xx_hash_update(struct ahash_request *req);
extern int crypto4xx_hash_init(struct ahash_request *req);
+extern int crypto4xx_md5_alg_init(struct crypto_tfm *tfm);
+extern int crypto4xx_hash_hmac_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen,
+ unsigned int sa_len,
+ unsigned char ha,
+ unsigned char hm,
+ unsigned int max_keylen);
+extern int crypto4xx_md5_hmac_setkey(struct crypto_ahash *hash, const =
u8 *key,
+ unsigned int keylen);
+extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
+extern int crypto4xx_sha2_alg_init(struct crypto_tfm *tfm);
+extern int crypto4xx_sha2_hmac_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen);
+extern int crypto4xx_sha1_hmac_setkey(struct crypto_ahash *hash, const =
u8 *key,
+ unsigned int keylen);
+extern u32 get_dynamic_sa_offset_inner_digest(struct crypto4xx_ctx =
*ctx);
+extern u32 get_dynamic_sa_offset_outer_digest(struct crypto4xx_ctx =
*ctx);
+extern int crypto4xx_pre_compute_hmac(struct crypto4xx_ctx *ctx,
+ void *key,
+ unsigned int keylen,
+ unsigned int bs,
+ unsigned char ha,
+ unsigned char digs);
+int crypto4xx_setkey_aes_ecb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_ofb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_cfb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_ctr(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_gcm(struct crypto_aead *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_ccm(struct crypto_aead *cipher,
+ const u8 *key, unsigned int keylen);
+
+int crypto4xx_encrypt_aes_gcm(struct aead_request *req);
+int crypto4xx_decrypt_aes_gcm(struct aead_request *req);
+int crypto4xx_encrypt_aes_ccm(struct aead_request *req);
+int crypto4xx_decrypt_aes_ccm(struct aead_request *req);
+int crypto4xx_encrypt_ctr(struct ablkcipher_request *req);
+int crypto4xx_decrypt_ctr(struct ablkcipher_request *req);
+int crypto4xx_setauthsize_aes(struct crypto_aead *ciper,
+ unsigned int authsize);
+int crypto4xx_givencrypt_aes_ccm(struct aead_givcrypt_request *req);
+int crypto4xx_givencrypt_aes_gcm(struct aead_givcrypt_request *req);
+int crypto4xx_givdecrypt_aes_ccm(struct aead_givcrypt_request *req);
+int crypto4xx_givdecrypt_aes_gcm(struct aead_givcrypt_request *req);
+int crypto4xx_setkey_kasumi_f8(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen);
+
+int crypto4xx_encrypt_kasumi_f8(struct ablkcipher_request *req);
+int crypto4xx_decrypt_kasumi_f8(struct ablkcipher_request *req);
+int crypto4xx_setkey_kasumi_p(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen);
+int crypto4xx_kasumi_f9_digest(struct ahash_request *req);
+int crypto4xx_kasumi_f9_setkey(struct crypto_ahash *hash,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_xcbc_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen);
+int crypto4xx_setkey_arc4(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_arc4_decrypt(struct ablkcipher_request *req);
+int crypto4xx_arc4_encrypt(struct ablkcipher_request *req);
+u32 crypto4xx_alloc_arc4_state_record(struct crypto4xx_ctx *ctx);
+int crypto4xx_setauthsize_aes_ccm(struct crypto_aead *ciper,
+ unsigned int authsize);
+
+/* From crypto/md5.c */
+extern void md5_get_immediate_hash(struct crypto_tfm *tfm, u8 *data);
+extern unsigned int crypto4xx_sa_hash_tbl[3][6];
+
#endif
diff --git a/drivers/crypto/amcc/crypto4xx_sa.c =
b/drivers/crypto/amcc/crypto4xx_sa.c
index 466fd94..fa4ff7a 100644
--- a/drivers/crypto/amcc/crypto4xx_sa.c
+++ b/drivers/crypto/amcc/crypto4xx_sa.c
@@ -84,6 +84,119 @@ u32 get_dynamic_sa_offset_state_ptr_field(struct =
crypto4xx_ctx *ctx)
return sizeof(struct dynamic_sa_ctl) + offset * 4;
}
=20
+u32 get_dynamic_sa_offset_arc4_state_ptr(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size
+ + cts.bf.outer_size
+ + cts.bf.spi
+ + cts.bf.seq_num0
+ + cts.bf.seq_num1
+ + cts.bf.seq_num_mask0
+ + cts.bf.seq_num_mask1
+ + cts.bf.seq_num_mask2
+ + cts.bf.seq_num_mask3
+ + cts.bf.iv0
+ + cts.bf.iv1
+ + cts.bf.iv2
+ + cts.bf.iv3
+ + cts.bf.state_ptr
+ + cts.bf.arc4_ij_ptr;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_inner_digest(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+ offset =3D cts.bf.key_size;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_outer_digest(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_spi(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size
+ + cts.bf.outer_size;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_seq_num(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size
+ + cts.bf.outer_size
+ + cts.bf.spi;
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_seq_num_mask(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size
+ + cts.bf.outer_size
+ + cts.bf.spi
+ + cts.bf.seq_num0
+ + cts.bf.seq_num1;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx)
{
union dynamic_sa_contents cts;
@@ -92,6 +205,7 @@ u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx)
cts.w =3D ((struct dynamic_sa_ctl *) ctx->sa_in)->sa_contents;
else
cts.w =3D ((struct dynamic_sa_ctl *) ctx->sa_out)->sa_contents;
+
return (cts.bf.iv0 + cts.bf.iv1 + cts.bf.iv2 + cts.bf.iv3) * 4;
}
=20
diff --git a/drivers/crypto/amcc/crypto4xx_sa.h =
b/drivers/crypto/amcc/crypto4xx_sa.h
index 4b83ed7..5a1e308 100644
--- a/drivers/crypto/amcc/crypto4xx_sa.h
+++ b/drivers/crypto/amcc/crypto4xx_sa.h
@@ -50,12 +50,42 @@ union dynamic_sa_contents {
u32 w;
} __attribute__((packed));
=20
+#define SA_OPCODE_ESP 0
+#define SA_OPCODE_AH 1
+#define SA_OPCODE_SSL 4
+#define SA_OPCODE_TLS 5
+#define SA_OPCODE_SRTP 7
+#define SA_OPCODE_DTLS 1
+#define SA_OPCODE_TLS1_1 6
+
+#define SA_OP_GROUP_BASIC 0
+#define SA_OP_GROUP_PROTOCOL 1
+#define SA_OP_GROUP_EXTEND_PROTOCOL 3
+
+#define SA_OPCODE_EXT_PROT_DTLS 1
+#define SA_OPCODE_EXT_PROT_MACSEC 2
+#define SA_OPCODE_EXT_PROT_SSL 4
+#define SA_OPCODE_EXT_PROT_TLS10 5
+#define SA_OPCODE_EXT_PROT_TLS11 6
+
#define DIR_OUTBOUND 0
#define DIR_INBOUND 1
-#define SA_OP_GROUP_BASIC 0
#define SA_OPCODE_ENCRYPT 0
#define SA_OPCODE_DECRYPT 0
+#define SA_OPCODE_ENCRYPT_HASH 1
+#define SA_OPCODE_HASH_DECRYPT 1
#define SA_OPCODE_HASH 3
+#define SA_OPCODE_HASH_ENCRYPT 4
+#define SA_OPCODE_DECRYPT_HASH 4
+
+#define SA_OPCODE_ESP 0
+#define SA_OPCODE_AH 1
+#define SA_OPCODE_SSL 4
+#define SA_OPCODE_TLS 5
+#define SA_OPCODE_SRTP 7
+#define SA_OPCODE_DTLS 1
+#define SA_OPCODE_TLS1_1 6
+
#define SA_CIPHER_ALG_DES 0
#define SA_CIPHER_ALG_3DES 1
#define SA_CIPHER_ALG_ARC4 2
@@ -65,8 +95,17 @@ union dynamic_sa_contents {
=20
#define SA_HASH_ALG_MD5 0
#define SA_HASH_ALG_SHA1 1
+#define SA_HASH_ALG_SHA224 2
+#define SA_HASH_ALG_SHA256 3
+#define SA_HASH_ALG_SHA384 4
+#define SA_HASH_ALG_SHA512 5
+#define HASH_ALG_MAX_CNT 6
+#define SA_HASH_ALG_AES_XCBC_MAC_128 8
+#define SA_HASH_ALG_KASUMI_f9 9
+#define SA_HASH_ALG_GHASH 12
+#define SA_HASH_ALG_GMAC 13
+#define SA_HASH_ALG_CBC_MAC 14
#define SA_HASH_ALG_NULL 15
-#define SA_HASH_ALG_SHA1_DIGEST_SIZE 20
=20
#define SA_LOAD_HASH_FROM_SA 0
#define SA_LOAD_HASH_FROM_STATE 2
@@ -87,6 +126,16 @@ union dynamic_sa_contents {
#define SA_HEADER_PROC 1
#define SA_NO_HEADER_PROC 0
=20
+#define SA_HASH_ALG_MD5_DIGEST_SIZE 16
+#define SA_HASH_ALG_SHA1_DIGEST_SIZE 20
+#define SA_HASH_ALG_SHA224_DIGEST_SIZE 28
+#define SA_HASH_ALG_SHA256_DIGEST_SIZE 32
+#define SA_HASH_ALG_SHA384_DIGEST_SIZE 48
+#define SA_HASH_ALG_SHA512_DIGEST_SIZE 64
+
+
+#define CRYPTO4XX_MAC_ALGS { "md5", "sha1", \
+ "sha224", "sha256", "sha384", "sha512" }
union sa_command_0 {
struct {
u32 scatter:1;
@@ -111,7 +160,13 @@ union sa_command_0 {
} __attribute__((packed));
=20
#define CRYPTO_MODE_ECB 0
+#define CRYPTO_MODE_KASUMI 0
#define CRYPTO_MODE_CBC 1
+#define CRYPTO_MODE_OFB 2
+#define CRYPTO_MODE_CFB 3
+#define CRYPTO_MODE_AES_CTR 4
+#define CRYPTO_MODE_KASUMI_f8 4
+#define CRYPTO_MODE_AES_ICM 5
=20
#define CRYPTO_FEEDBACK_MODE_NO_FB 0
#define CRYPTO_FEEDBACK_MODE_64BIT_OFB 0
@@ -124,7 +179,7 @@ union sa_command_0 {
#define SA_AES_KEY_LEN_256 4
=20
#define SA_REV2 1
-/**
+/*
* The follow defines bits sa_command_1
* In Basic hash mode this bit define simple hash or hmac.
* In IPsec mode, this bit define muting control.
@@ -177,13 +232,46 @@ struct dynamic_sa_ctl {
/**
* State Record for Security Association (SA)
*/
-struct sa_state_record {
+struct sa_state_record {
u32 save_iv[4];
u32 save_hash_byte_cnt[2];
u32 save_digest[16];
} __attribute__((packed));
=20
/**
+ * Arc4 State Record for Security Association (SA)
+ */
+struct arc4_sr {
+ u32 arc4_state[64];
+} __attribute__((packed));
+
+/**
+ * Security Association (SA) for DES
+ */
+struct dynamic_sa_des {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[2];
+ u32 iv[2];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_DES_LEN (sizeof(struct dynamic_sa_des)/4)
+#define SA_DES_CONTENTS 0x26000022
+
+/**
+ * Security Association (SA) for 3DES
+ */
+struct dynamic_sa_3des {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[6];
+ u32 iv[2]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_3DES_LEN (sizeof(struct dynamic_sa_3des)/4)
+#define SA_3DES_CONTENTS 0x26000062
+
+/**
* Security Association (SA) for AES128
*
*/
@@ -194,11 +282,10 @@ struct dynamic_sa_aes128 {
u32 state_ptr;
u32 reserved;
} __attribute__((packed));
-
#define SA_AES128_LEN (sizeof(struct dynamic_sa_aes128)/4)
#define SA_AES128_CONTENTS 0x3e000042
=20
-/*
+/**
* Security Association (SA) for AES192
*/
struct dynamic_sa_aes192 {
@@ -208,7 +295,6 @@ struct dynamic_sa_aes192 {
u32 state_ptr;
u32 reserved;
} __attribute__((packed));
-
#define SA_AES192_LEN (sizeof(struct dynamic_sa_aes192)/4)
#define SA_AES192_CONTENTS 0x3e000062
=20
@@ -228,6 +314,19 @@ struct dynamic_sa_aes256 {
#define SA_AES_CONTENTS 0x3e000002
=20
/**
+ * Security Association (SA) for HASH128: HMAC-MD5
+ */
+struct dynamic_sa_hash128 {
+ struct dynamic_sa_ctl ctrl;
+ u32 inner_digest[4];
+ u32 outer_digest[4];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_HASH128_LEN (sizeof(struct dynamic_sa_hash128)/4)
+#define SA_HASH128_CONTENTS 0x20008402
+
+/**
* Security Association (SA) for HASH160: HMAC-SHA1
*/
struct dynamic_sa_hash160 {
@@ -240,4 +339,228 @@ struct dynamic_sa_hash160 {
#define SA_HASH160_LEN (sizeof(struct dynamic_sa_hash160)/4)
#define SA_HASH160_CONTENTS 0x2000a502
=20
+/**
+ * Security Association (SA) for HASH256: HMAC-SHA224, HMAC-SHA256
+ */
+struct dynamic_sa_hash256 {
+ struct dynamic_sa_ctl ctrl;
+ u32 inner_digest[8];
+ u32 outer_digest[8];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_HASH256_LEN (sizeof(struct dynamic_sa_hash256)/4)
+#define SA_HASH256_CONTENTS 0x20010802
+
+/*
+ * Security Association (SA) for HASH512: HMAC-SHA512
+ */
+struct dynamic_sa_hash512 {
+ struct dynamic_sa_ctl ctrl;
+ u32 inner_digest[16];
+ u32 outer_digest[16];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_HASH512_LEN (sizeof(struct dynamic_sa_hash512)/4)
+#define SA_HASH512_CONTENTS 0x20021002
+
+/**
+ * Security Association (SA) for AES128_XCBC_MAC
+ */
+struct dynamic_sa_aes128_xcbc_mac {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 inner_digest[8];
+ u32 outer_digest[8];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES128_XCBC_MAC_LEN (sizeof(struct =
dynamic_sa_aes128_xcbc_mac)/4)
+#define SA_AES128_XCBC_MAC_CONTENTS 0x3e010842
+
+/**
+ * Security Association (SA) for AES128_GCM
+ */
+struct dynamic_sa_aes128_gcm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 inner_digest[4];
+ u32 outer_digest[4];
+ u32 spi;
+ u32 seq;
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES128_GCM_LEN (sizeof(struct dynamic_sa_aes128_gcm)/4)
+#define SA_AES128_GCM_CONTENTS 0x3e0c8442
+
+/**
+ * Security Association (SA) for AES192_XCBC_MAC
+ */
+struct dynamic_sa_aes192_xcbc_mac {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[6];
+ u32 inner_digest[8];
+ u32 outer_digest[8];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES192_XCBC_MAC_LEN (sizeof(struct =
dynamic_sa_aes192_xcbc_mac)/4)
+#define SA_AES192_XCBC_MAC_CONTENTS 0x3e010862
+
+/**
+ * Security Association (SA) for AES192_GCM
+ */
+struct dynamic_sa_aes192_gcm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[6];
+ u32 inner_digest[4];
+ u32 outer_digest[4];
+ u32 spi;
+ u32 seq;
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES192_GCM_LEN (sizeof(struct dynamic_sa_aes192_gcm)/4)
+#define SA_AES192_GCM_CONTENTS 0x3e0c8462
+
+
+/**
+ * Security Association (SA) for AES256_XCBC_MAC
+ */
+struct dynamic_sa_aes256_xcbc_mac {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[8];
+ u32 inner_digest[8];
+ u32 outer_digest[8];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES256_XCBC_MAC_LEN (sizeof(struct =
dynamic_sa_aes256_xcbc_mac)/4)
+#define SA_AES256_XCBC_MAC_CONTENTS 0x3e010882
+
+/**
+ * Security Association (SA) for AES256_GCM
+ */
+struct dynamic_sa_aes256_gcm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[8];
+ u32 inner_digest[4];
+ u32 outer_digest[4];
+ u32 spi;
+ u32 seq;
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES256_GCM_LEN (sizeof(struct dynamic_sa_aes256_gcm)/4)
+#define SA_AES256_GCM_CONTENTS 0x3e0c8482
+#define SA_AES_GCM_CONTENTS 0x3e0c8402
+
+/**
+ * Security Association (SA) for Kasumi
+ */
+struct dynamic_sa_kasumi {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_KASUMI_LEN (sizeof(struct dynamic_sa_kasumi)/4)
+#define SA_KASUMI_CONTENTS 0x20000042
+
+/**
+ * Security Association (SA) for Kasumi f8
+ */
+struct dynamic_sa_kasumi_f8 {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 iv[2];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_KASUMI_F8_LEN (sizeof(struct dynamic_sa_kasumi_f8)/4)
+#define SA_KASUMI_F8_CONTENTS 0x26000042
+
+#define KASUMI_BLOCK_SIZE 8
+#define KASUMI_KEY_SIZE 16
+
+/**
+ * Security Association (SA) for Kasumi f8
+ */
+struct dynamic_sa_kasumi_f9 {
+ struct dynamic_sa_ctl ctrl;
+ u32 inner_digest[4];
+ u32 outter_digest[3];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_KASUMI_F9_LEN (sizeof(struct dynamic_sa_kasumi_f9)/4)
+#define SA_KASUMI_F9_CONTENTS 0x20006402
+
+/**
+ * Security Association (SA) for AES256 CCM
+ */
+struct dynamic_sa_aes256_ccm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[8];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES256_CCM_LEN (sizeof(struct dynamic_sa_aes256_ccm)/4)
+#define SA_AES256_CCM_CONTENTS 0x3e000082
+#define SA_AES_CCM_CONTENTS 0x3e000002
+
+/**
+ * Security Association (SA) for AES192 CCM
+ */
+struct dynamic_sa_aes192_ccm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[6];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES192_CCM_LEN (sizeof(struct =
dynamic_sa_aes192_ccm)/4)
+#define SA_AES192_CCM_CONTENTS 0x3e000062
+
+/**
+ * Security Association (SA) for AES128 CCM
+ */
+struct dynamic_sa_aes128_ccm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES128_CCM_LEN (sizeof(struct dynamic_sa_aes128_ccm)/4)
+#define SA_AES128_CCM_CONTENTS 0x3e000042
+
+/**
+ * Security Association (SA) for ARC4
+ */
+struct arc4_ij_ptr {
+ u32 rsv:16;
+ u32 j:8;
+ u32 i:8;
+} __attribute__((packed));
+
+struct dynamic_sa_arc4 {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ struct arc4_ij_ptr ij;
+ u32 arc4_state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_ARC4_LEN (sizeof(struct dynamic_sa_arc4)/4)
+#define SA_ARC4_CONTENTS 0xc0000042
+
#endif
--=20
1.5.5
^ permalink raw reply related
* [PATCH 3/3] AMCC Crypto4xx Device Driver v7
From: Shasi Pulijala @ 2009-06-15 17:28 UTC (permalink / raw)
To: herbert; +Cc: linuxppc-dev, linux-crypto
From: Shasi Pulijala <spulijala@amcc.com>
This patch further adds immediate hash functions to md5/sha1/sha2 algs.
These immediate hash functions are used in hmac key generation in PPC =
Crypto4xx driver.
Signed-off-by: Shasi Pulijala <spulijala@amcc.com>
Acked-by: Loc Ho <lho@amcc.com>
---
crypto/md5.c | 15 +++++++++++++++
crypto/sha1_generic.c | 15 +++++++++++++++
crypto/sha256_generic.c | 15 +++++++++++++++
crypto/sha512_generic.c | 19 +++++++++++++++++++
include/crypto/sha.h | 7 +++++++
5 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/crypto/md5.c b/crypto/md5.c
index 83eb529..0c74b84 100644
--- a/crypto/md5.c
+++ b/crypto/md5.c
@@ -220,6 +220,21 @@ static int md5_final(struct shash_desc *desc, u8 =
*out)
return 0;
}
=20
+void md5_get_immediate_hash(struct crypto_tfm *tfm, u8 *data)
+{
+ struct shash_desc *desc =3D crypto_tfm_ctx(tfm);
+ struct md5_ctx *mctx =3D shash_desc_ctx(desc);
+ int i;
+
+ for (i =3D 0; i < MD5_HASH_WORDS; i++) {
+ *data++ =3D mctx->hash[i] & 0xFF;
+ *data++ =3D (mctx->hash[i] >> 8) & 0xFF;
+ *data++ =3D (mctx->hash[i] >> 16) & 0xFF;
+ *data++ =3D (mctx->hash[i] >> 24) & 0xFF;
+ }
+}
+EXPORT_SYMBOL_GPL(md5_get_immediate_hash);
+
static struct shash_alg alg =3D {
.digestsize =3D MD5_DIGEST_SIZE,
.init =3D md5_init,
diff --git a/crypto/sha1_generic.c b/crypto/sha1_generic.c
index 9efef20..e77b591 100644
--- a/crypto/sha1_generic.c
+++ b/crypto/sha1_generic.c
@@ -111,6 +111,21 @@ static int sha1_final(struct shash_desc *desc, u8 =
*out)
return 0;
}
=20
+void sha1_get_immediate_hash(struct crypto_tfm *tfm, u8 *data)
+{
+ struct shash_desc *desc =3D crypto_tfm_ctx(tfm);
+ struct sha1_ctx *sctx =3D shash_desc_ctx(desc);
+ int i;
+
+ for (i =3D 0; i < 5; i++) {
+ *data++ =3D sctx->state[i] & 0xFF;
+ *data++ =3D (sctx->state[i] >> 8) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 16) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 24) & 0xFF;
+ }
+}
+EXPORT_SYMBOL_GPL(sha1_get_immediate_hash);
+
static struct shash_alg alg =3D {
.digestsize =3D SHA1_DIGEST_SIZE,
.init =3D sha1_init,
diff --git a/crypto/sha256_generic.c b/crypto/sha256_generic.c
index 6349d83..0f5a66b 100644
--- a/crypto/sha256_generic.c
+++ b/crypto/sha256_generic.c
@@ -331,6 +331,21 @@ static int sha224_final(struct shash_desc *desc, u8 =
*hash)
return 0;
}
=20
+void sha256_get_immediate_hash(struct crypto_tfm *tfm, u8 *data)
+{
+ struct shash_desc *desc =3D crypto_tfm_ctx(tfm);
+ struct sha256_ctx *sctx =3D shash_desc_ctx(desc);
+ int i;
+
+ for (i =3D 0; i < 8; i++) {
+ *data++ =3D sctx->state[i] & 0xFF;
+ *data++ =3D (sctx->state[i] >> 8) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 16) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 24) & 0xFF;
+ }
+}
+EXPORT_SYMBOL_GPL(sha256_get_immediate_hash);
+
static struct shash_alg sha256 =3D {
.digestsize =3D SHA256_DIGEST_SIZE,
.init =3D sha256_init,
diff --git a/crypto/sha512_generic.c b/crypto/sha512_generic.c
index 3bea38d..c329903 100644
--- a/crypto/sha512_generic.c
+++ b/crypto/sha512_generic.c
@@ -257,6 +257,25 @@ static int sha384_final(struct shash_desc *desc, u8 =
*hash)
return 0;
}
=20
+void sha512_get_immediate_hash(struct crypto_tfm *tfm, u8 *data)
+{
+ struct shash_desc *desc =3D crypto_tfm_ctx(tfm);
+ struct sha512_ctx *sctx =3D shash_desc_ctx(desc);
+ int i;
+
+ for (i =3D 0; i < 8; i++) {
+ *data++ =3D (sctx->state[i] >> 32) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 40) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 48) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 56) & 0xFF;
+ *data++ =3D sctx->state[i] & 0xFF;
+ *data++ =3D (sctx->state[i] >> 8) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 16) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 24) & 0xFF;
+ }
+}
+EXPORT_SYMBOL_GPL(sha512_get_immediate_hash);
+
static struct shash_alg sha512 =3D {
.digestsize =3D SHA512_DIGEST_SIZE,
.init =3D sha512_init,
diff --git a/include/crypto/sha.h b/include/crypto/sha.h
index c0ccc2b..8894c2f 100644
--- a/include/crypto/sha.h
+++ b/include/crypto/sha.h
@@ -62,4 +62,11 @@
#define SHA512_H6 0x1f83d9abfb41bd6bULL
#define SHA512_H7 0x5be0cd19137e2179ULL
=20
+/* From crypto/sha1_generic.c */
+void sha1_get_immediate_hash(struct crypto_tfm *tfm, u8 *data);
+/* From crypto/sha256_generic.c */
+void sha256_get_immediate_hash(struct crypto_tfm *tfm, u8 *data);
+/* From crypto/sha512_generic.c */
+void sha512_get_immediate_hash(struct crypto_tfm *tfm, u8 *data);
+
#endif
--=20
1.5.5
^ permalink raw reply related
* [PATCH 2/3] AMCC Crypto4xx Device Driver v7
From: Shasi Pulijala @ 2009-06-15 17:26 UTC (permalink / raw)
To: herbert; +Cc: linuxppc-dev, linux-crypto
From: Shasi Pulijala <spulijala@amcc.com>
This patch adds further support for AMCC ppc4xx security device driver. =
This is the
second release that adds algorithms like:
des/3des
rfc3686(ctr(aes))
gcm, ccm
hmac(md5,sha1,..,sha512)
xcbc(aes), arc4 and kasumi.
Signed-off-by: Shasi Pulijala <spulijala@amcc.com>
Acked-by: Loc Ho <lho@amcc.com>
---
drivers/crypto/amcc/crypto4xx_alg.c | 1492 =
++++++++++++++++++++++++++++++++++-
1 files changed, 1476 insertions(+), 16 deletions(-)
diff --git a/drivers/crypto/amcc/crypto4xx_alg.c =
b/drivers/crypto/amcc/crypto4xx_alg.c
index 61b6e1b..fac3543 100644
--- a/drivers/crypto/amcc/crypto4xx_alg.c
+++ b/drivers/crypto/amcc/crypto4xx_alg.c
@@ -24,10 +24,13 @@
#include <linux/crypto.h>
#include <linux/hash.h>
#include <crypto/internal/hash.h>
+#include <crypto/aead.h>
#include <linux/dma-mapping.h>
#include <crypto/algapi.h>
#include <crypto/aes.h>
+#include <crypto/des.h>
#include <crypto/sha.h>
+#include <crypto/authenc.h>
#include "crypto4xx_reg_def.h"
#include "crypto4xx_sa.h"
#include "crypto4xx_core.h"
@@ -58,9 +61,10 @@ void set_dynamic_sa_command_1(struct dynamic_sa_ctl =
*sa, u32 cm, u32 hmac_mc,
{
sa->sa_command_1.w =3D 0;
sa->sa_command_1.bf.crypto_mode31 =3D (cm & 4) >> 2;
- sa->sa_command_1.bf.crypto_mode9_8 =3D cm & 3;
+ sa->sa_command_1.bf.crypto_mode9_8 =3D (cm & 3);
sa->sa_command_1.bf.feedback_mode =3D cfb,
sa->sa_command_1.bf.sa_rev =3D 1;
+ sa->sa_command_1.bf.hmac_muting =3D hmac_mc;
sa->sa_command_1.bf.extended_seq_num =3D esn;
sa->sa_command_1.bf.seq_num_mask =3D sn_mask;
sa->sa_command_1.bf.mutable_bit_proc =3D mute;
@@ -69,6 +73,338 @@ void set_dynamic_sa_command_1(struct dynamic_sa_ctl =
*sa, u32 cm, u32 hmac_mc,
sa->sa_command_1.bf.copy_hdr =3D cp_hdr;
}
=20
+/** Table lookup for SA Hash Digest length and
+ * Hash Contents (based on Hash type)
+ */
+unsigned int crypto4xx_sa_hash_tbl[3][HASH_ALG_MAX_CNT] =3D {
+ /* Hash Contents */
+ { SA_HASH128_CONTENTS, SA_HASH160_CONTENTS, SA_HASH256_CONTENTS,
+ SA_HASH256_CONTENTS, SA_HASH512_CONTENTS, SA_HASH512_CONTENTS },
+ /* Digest len */
+ {4 * 4, 5 * 4, 7 * 4, 8 * 4, 12 * 4, 16 * 4},
+ /* SA Length */
+ { SA_HASH128_LEN, SA_HASH160_LEN, SA_HASH256_LEN, SA_HASH256_LEN,
+ SA_HASH512_LEN, SA_HASH512_LEN }
+};
+
+/** Table lookup for Hash Algorithms based on Hash type, used in
+ * crypto4xx_pre_compute_hmac()
+ */
+char *crypto4xx_hash_alg_map_tbl[HASH_ALG_MAX_CNT] =3D =
CRYPTO4XX_MAC_ALGS;
+
+static void crypto4xx_sg_setbuf(unsigned char *data, size_t bufsize,
+ struct scatterlist *sg, int sg_num)
+{
+ int remainder_of_page;
+ int i =3D 0;
+
+ sg_init_table(sg, sg_num);
+ while (bufsize > 0 && i < sg_num) {
+ sg_set_buf(&sg[i], data, bufsize);
+ remainder_of_page =3D PAGE_SIZE - sg[i].offset;
+ if (bufsize > remainder_of_page) {
+ /* the buffer was split over multiple pages */
+ sg[i].length =3D remainder_of_page;
+ bufsize -=3D remainder_of_page;
+ data +=3D remainder_of_page;
+ } else {
+ bufsize =3D 0;
+ }
+ i++;
+ }
+}
+
+void crypto4xx_compute_immediate_hash(struct crypto_tfm *child_tfm, u8 =
*data,
+ unsigned char ha)
+{
+ switch (ha) {
+ case SA_HASH_ALG_MD5:
+ md5_get_immediate_hash(child_tfm, data);
+ break;
+ case SA_HASH_ALG_SHA1:
+ sha1_get_immediate_hash(child_tfm, data);
+ break;
+ case SA_HASH_ALG_SHA256:
+ case SA_HASH_ALG_SHA224:
+ sha256_get_immediate_hash(child_tfm, data);
+ break;
+ case SA_HASH_ALG_SHA384:
+ case SA_HASH_ALG_SHA512:
+ sha512_get_immediate_hash(child_tfm, data);
+ break;
+ default:
+ break;
+ }
+}
+
+int crypto4xx_pre_compute_hmac(struct crypto4xx_ctx *ctx,
+ void *key,
+ unsigned int keylen,
+ unsigned int bs,
+ unsigned char ha,
+ unsigned char digs)
+{
+ u8 *ipad =3D NULL;
+ u8 *opad;
+ struct crypto_hash *child_hash =3D NULL;
+ struct hash_desc desc;
+ struct scatterlist sg[1];
+ struct scatterlist asg[2];
+ struct crypto_tfm *child_tfm;
+ char *child_name =3D NULL;
+ int i, rc =3D 0;
+ int ds;
+
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+ child_name =3D crypto4xx_hash_alg_map_tbl[ha];
+ child_hash =3D crypto_alloc_hash(child_name, 0, 0);
+ if (IS_ERR(child_hash)) {
+ rc =3D PTR_ERR(child_hash);
+ printk(KERN_ERR "failed to load "
+ "transform for %s error %d\n",
+ child_name, rc);
+ return rc;
+ }
+
+ ipad =3D kmalloc(bs * 2, GFP_KERNEL);
+ if (ipad =3D=3D NULL) {
+ crypto_free_hash(child_hash);
+ return -ENOMEM;
+ }
+
+ opad =3D ipad + bs;
+ child_tfm =3D crypto_hash_tfm(child_hash);
+ ds =3D crypto_hash_digestsize(child_hash);
+ desc.tfm =3D child_hash;
+ desc.flags =3D 0;
+ if (keylen > bs) {
+ crypto4xx_sg_setbuf(key, keylen, asg, 2);
+ rc =3D crypto_hash_init(&desc);
+ if (rc < 0)
+ goto err_alg_hash_key;
+ rc =3D crypto_hash_update(&desc, asg, keylen);
+ if (rc < 0)
+ goto err_alg_hash_key;
+ rc =3D crypto_hash_final(&desc, ipad);
+ keylen =3D ds;
+ } else {
+ memcpy(ipad, key, keylen);
+ }
+ memset(ipad + keylen, 0, bs-keylen);
+ memcpy(opad, ipad, bs);
+
+ for (i =3D 0; i < bs; i++) {
+ ipad[i] ^=3D 0x36;
+ opad[i] ^=3D 0x5c;
+ }
+
+ sg_init_one(&sg[0], ipad, bs);
+ rc =3D crypto_hash_init(&desc);
+ if (rc < 0)
+ goto err_alg_hash_key;
+ rc =3D crypto_hash_update(&desc, sg, bs);
+ if (rc < 0)
+ goto err_alg_hash_key;
+
+ if (ha =3D=3D SA_HASH_ALG_SHA224)
+ ds =3D SHA256_DIGEST_SIZE;
+ else if (ha =3D=3D SA_HASH_ALG_SHA384)
+ ds =3D SHA512_DIGEST_SIZE;
+
+ crypto4xx_compute_immediate_hash(child_tfm, ipad, ha);
+ crypto4xx_memcpy_le(ctx->sa_in +
+ get_dynamic_sa_offset_inner_digest(ctx), ipad, ds);
+
+ sg_init_one(&sg[0], opad, bs);
+ rc =3D crypto_hash_init(&desc);
+ if (rc < 0)
+ goto err_alg_hash_key;
+
+ rc =3D crypto_hash_update(&desc, sg, bs);
+ if (rc < 0)
+ goto err_alg_hash_key;
+
+ crypto4xx_compute_immediate_hash(child_tfm, opad, ha);
+ crypto4xx_memcpy_le(ctx->sa_in +
+ get_dynamic_sa_offset_outer_digest(ctx), opad, ds);
+
+err_alg_hash_key:
+ kfree(ipad);
+ crypto_free_hash(child_hash);
+ return rc;
+}
+
+int crypto4xx_compute_gcm_hash_key_sw(struct crypto4xx_ctx *ctx,
+ const u8 *key,
+ unsigned int keylen)
+{
+ struct crypto_blkcipher *aes_tfm =3D NULL;
+ struct blkcipher_desc desc;
+ struct scatterlist sg[1];
+ char src[16];
+ int rc =3D 0;
+
+ aes_tfm =3D crypto_alloc_blkcipher("ecb(aes)", 0, CRYPTO_ALG_ASYNC);
+ if (IS_ERR(aes_tfm)) {
+ printk(KERN_ERR "failed to load transform for %ld\n",
+ PTR_ERR(aes_tfm));
+ rc =3D PTR_ERR(aes_tfm);
+ return rc;
+ }
+ desc.tfm =3D aes_tfm;
+ desc.flags =3D 0;
+
+ memset(src, 0, 16);
+ rc =3D crypto_blkcipher_setkey(aes_tfm, key, keylen);
+ if (rc) {
+ printk(KERN_ERR "setkey() failed flags=3D%x\n",
+ crypto_blkcipher_get_flags(aes_tfm));
+ goto out;
+ }
+
+ sg_init_one(sg, src, 16);
+ rc =3D crypto_blkcipher_encrypt(&desc, sg, sg, 16);
+ if (rc)
+ goto out;
+ crypto4xx_memcpy_le(ctx->sa_in +
+ get_dynamic_sa_offset_inner_digest(ctx), src, 16);
+
+out:
+ crypto_free_blkcipher(aes_tfm);
+ return rc;
+}
+
+/**
+ * 3DES/DES Functions
+ *
+ */
+static int crypto4xx_setkey_3des(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen,
+ unsigned char cm,
+ unsigned char fb)
+{
+ struct crypto_tfm *tfm =3D crypto_ablkcipher_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ int rc;
+
+ if (keylen !=3D DES_KEY_SIZE && keylen !=3D DES3_EDE_KEY_SIZE) {
+ crypto_ablkcipher_set_flags(cipher,
+ CRYPTO_TFM_RES_BAD_KEY_LEN);
+
+ return -EINVAL;
+ }
+
+ if (keylen =3D=3D DES_KEY_SIZE) {
+ u32 tmp[32];
+ rc =3D des_ekey(tmp, key);
+ if (unlikely(rc =3D=3D 0) &&
+ (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
+ crypto_ablkcipher_set_flags(cipher,
+ CRYPTO_TFM_RES_WEAK_KEY);
+ return -EINVAL;
+ }
+ }
+
+ /* Create SA */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, keylen =3D=3D 8 ? SA_DES_LEN : =
SA_3DES_LEN);
+ if (rc)
+ return rc;
+ /*
+ * state record will state in base ctx, so iv and
+ * hash result can be reused
+ * also don't need to alloc each packet coming
+ */
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ /* Setup SA */
+ ctx->direction =3D DIR_INBOUND;
+ ctx->hash_final =3D 0;
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_NULL,
+ SA_CIPHER_ALG_DES,
+ SA_PAD_TYPE_ZERO, SA_OP_GROUP_BASIC,
+ SA_OPCODE_DECRYPT, DIR_INBOUND);
+
+ set_dynamic_sa_command_1(sa, cm, SA_HASH_MODE_HASH,
+ fb, SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ if (keylen =3D=3D DES_KEY_SIZE) {
+ crypto4xx_memcpy_le(((struct dynamic_sa_des *) sa)->key,
+ key, keylen);
+ ((struct dynamic_sa_des *)sa)->ctrl.sa_contents =3D
+ SA_DES_CONTENTS;
+ sa->sa_command_0.bf.cipher_alg =3D SA_CIPHER_ALG_DES;
+ } else {
+ crypto4xx_memcpy_le(((struct dynamic_sa_3des *) sa)->key,
+ key, keylen);
+ ((struct dynamic_sa_3des *)sa)->ctrl.sa_contents =3D
+ SA_3DES_CONTENTS;
+ sa->sa_command_0.bf.cipher_alg =3D SA_CIPHER_ALG_3DES;
+ }
+
+ memcpy((void *)(ctx->sa_in +
+ get_dynamic_sa_offset_state_ptr_field(ctx)),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ ctx->is_hash =3D 0;
+ sa->sa_command_0.bf.dir =3D DIR_INBOUND;
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+}
+
+int crypto4xx_setkey_3des_cfb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_3des(cipher, key, keylen,
+ CRYPTO_MODE_CFB,
+ CRYPTO_FEEDBACK_MODE_8BIT_CFB);
+}
+
+int crypto4xx_setkey_3des_ofb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_3des(cipher, key, keylen,
+ CRYPTO_MODE_OFB,
+ CRYPTO_FEEDBACK_MODE_64BIT_OFB);
+}
+
+int crypto4xx_setkey_3des_cbc(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_3des(cipher, key, keylen,
+ CRYPTO_MODE_CBC,
+ CRYPTO_FEEDBACK_MODE_NO_FB);
+}
+
+int crypto4xx_setkey_3des_ecb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_3des(cipher, key, keylen,
+ CRYPTO_MODE_ECB,
+ CRYPTO_FEEDBACK_MODE_NO_FB);
+}
+
+
int crypto4xx_encrypt(struct ablkcipher_request *req)
{
struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
@@ -79,22 +415,54 @@ int crypto4xx_encrypt(struct ablkcipher_request =
*req)
ctx->pd_ctl =3D 0x1;
=20
return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
- req->nbytes, req->info,
- get_dynamic_sa_iv_size(ctx));
+ req->nbytes, NULL, 0, req->info,
+ get_dynamic_sa_iv_size(ctx));
}
=20
int crypto4xx_decrypt(struct ablkcipher_request *req)
{
struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
=20
+ ctx->hash_final =3D 0;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x1;
ctx->direction =3D DIR_INBOUND;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0, req->info,
+ get_dynamic_sa_iv_size(ctx));
+}
+
+int crypto4xx_encrypt_ctr(struct ablkcipher_request *req)
+{
+ struct crypto_ablkcipher *ablkcipher =3D =
crypto_ablkcipher_reqtfm(req);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
ctx->hash_final =3D 0;
ctx->is_hash =3D 0;
- ctx->pd_ctl =3D 1;
+ ctx->pd_ctl =3D 0x1;
+ ctx->direction =3D DIR_OUTBOUND;
=20
return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
- req->nbytes, req->info,
- get_dynamic_sa_iv_size(ctx));
+ req->nbytes, NULL, 0,
+ req->info,
+ crypto_ablkcipher_ivsize(ablkcipher));
+}
+
+int crypto4xx_decrypt_ctr(struct ablkcipher_request *req)
+{
+ struct crypto_ablkcipher *ablkcipher =3D =
crypto_ablkcipher_reqtfm(req);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->hash_final =3D 0;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x1;
+ ctx->direction =3D DIR_INBOUND;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0,
+ req->info,
+ crypto_ablkcipher_ivsize(ablkcipher));
}
=20
/**
@@ -166,6 +534,13 @@ static int crypto4xx_setkey_aes(struct =
crypto_ablkcipher *cipher,
return 0;
}
=20
+int crypto4xx_setkey_aes_ecb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_ECB,
+ CRYPTO_FEEDBACK_MODE_NO_FB);
+}
+
int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
const u8 *key, unsigned int keylen)
{
@@ -173,8 +548,677 @@ int crypto4xx_setkey_aes_cbc(struct =
crypto_ablkcipher *cipher,
CRYPTO_FEEDBACK_MODE_NO_FB);
}
=20
+int crypto4xx_setkey_aes_ctr(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ablkcipher_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ u32 cnt =3D 1;
+ int rc;
+ u32 cm =3D CRYPTO_MODE_AES_CTR;
+
+ keylen -=3D 4;
+ /* Create SA */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ if (keylen !=3D AES_KEYSIZE_256 &&
+ keylen !=3D AES_KEYSIZE_192 && keylen !=3D AES_KEYSIZE_128) {
+ crypto_ablkcipher_set_flags(cipher,
+ CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_AES128_LEN + (keylen-16) / 4);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ ctx->hash_final =3D 0;
+ ctx->ctr_aes =3D 1;
+ /* Setup SA */
+ set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_NULL,
+ SA_CIPHER_ALG_AES, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_ENCRYPT,
+ DIR_INBOUND);
+ set_dynamic_sa_command_1(sa, cm, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB,
+ SA_EXTENDED_SN_OFF, SA_SEQ_MASK_OFF,
+ SA_MC_ENABLE, SA_NOT_COPY_PAD,
+ SA_NOT_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+ sa->sa_contents =3D SA_AES_CONTENTS | (keylen << 2);
+ sa->sa_command_1.bf.key_len =3D keylen >> 3;
+
+ ctx->direction =3D DIR_INBOUND;
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+
+ crypto4xx_memcpy_le(ctx->state_record, key + keylen, 4);
+ crypto4xx_memcpy_le(ctx->state_record + 12, (void *)&cnt, 4);
+
+ sa->sa_command_0.bf.dir =3D DIR_INBOUND;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+}
+
+int crypto4xx_setkey_aes_cfb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_CFB,
+ CRYPTO_FEEDBACK_MODE_128BIT_CFB);
+}
+
+int crypto4xx_setkey_aes_ofb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_OFB,
+ CRYPTO_FEEDBACK_MODE_64BIT_OFB);
+}
+
+int crypto4xx_setkey_aes_icm(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_AES_ICM,
+ CRYPTO_FEEDBACK_MODE_NO_FB);
+}
+
+/**
+ * AES-GCM Functions
+ */
+static inline int crypto4xx_aes_gcm_validate_keylen(unsigned int =
keylen)
+{
+ switch (keylen) {
+ case 16:
+ case 20:
+ case 24:
+ case 30:
+ case 32:
+ case 36:
+ return 0;
+ default:
+ printk(KERN_ERR "crypto4xx_setkey_aes_gcm: "
+ "ERROR keylen =3D 0x%08x\n", keylen);
+ return -EINVAL;
+ }
+ return -EINVAL;
+}
+
+int crypto4xx_setkey_aes_gcm(struct crypto_aead *cipher,
+ const u8 *key, unsigned int keylen)
+
+{
+ struct crypto_tfm *tfm =3D crypto_aead_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ int rc =3D 0;
+
+ u32 cm =3D 4;
+
+ if (crypto4xx_aes_gcm_validate_keylen(keylen) !=3D 0) {
+ printk(KERN_ERR "crypto4xx_setkey_aes_gcm:"
+ "ERROR keylen =3D 0x%08x\n", keylen);
+ crypto_aead_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_AES128_GCM_LEN + (keylen-16) / 4);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc)
+ goto err;
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+
+ sa->sa_contents =3D SA_AES_GCM_CONTENTS | (keylen << 2);
+ sa->sa_command_1.bf.key_len =3D keylen >> 3;
+
+ ctx->direction =3D DIR_INBOUND;
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+
+ rc =3D crypto4xx_compute_gcm_hash_key_sw(ctx, key, keylen);
+ if (rc) {
+ printk(KERN_ERR "GCM hash key setting failed =3D %d\n", rc);
+ goto err;
+ }
+
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ ctx->is_gcm =3D 1;
+ ctx->hash_final =3D 1;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x11;
+
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_GHASH,
+ SA_CIPHER_ALG_AES, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_HASH_DECRYPT,
+ DIR_INBOUND);
+
+ sa->sa_command_1.bf.crypto_mode31 =3D (cm & 4) >> 2;
+ sa->sa_command_1.bf.crypto_mode9_8 =3D (cm & 3);
+ sa->sa_command_1.bf.feedback_mode =3D 0;
+
+ sa->sa_command_1.bf.hash_crypto_offset =3D 0;
+ sa->sa_command_1.bf.sa_rev =3D 1;
+ sa->sa_command_1.bf.copy_payload =3D 1;
+
+ sa->sa_command_1.bf.copy_pad =3D 0;
+ sa->sa_command_1.bf.copy_hdr =3D 0;
+ sa->sa_command_1.bf.mutable_bit_proc =3D 1;
+ sa->sa_command_1.bf.seq_num_mask =3D 1;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+ sa->sa_command_0.bf.opcode =3D SA_OPCODE_ENCRYPT_HASH;
+
+ return 0;
+err:
+ crypto4xx_free_sa(ctx);
+ return rc;
+}
+
+int crypto4xx_encrypt_aes_gcm(struct aead_request *req)
+{
+ struct crypto_aead *aead =3D crypto_aead_reqtfm(req);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->direction =3D DIR_OUTBOUND;
+ ctx->append_icv =3D 1;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->cryptlen, req->assoc, req->assoclen,
+ req->iv, crypto_aead_ivsize(aead));
+}
+
+int crypto4xx_decrypt_aes_gcm(struct aead_request *req)
+{
+ struct crypto_aead *aead =3D crypto_aead_reqtfm(req);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ int len =3D req->cryptlen - crypto_aead_authsize(aead);
+
+ ctx->direction =3D DIR_INBOUND;
+ ctx->append_icv =3D 0;
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ len, req->assoc, req->assoclen,
+ req->iv, crypto_aead_ivsize(aead));
+}
+
+int crypto4xx_givencrypt_aes_gcm(struct aead_givcrypt_request *req)
+{
+ return -ENOSYS;
+}
+
+int crypto4xx_givdecrypt_aes_gcm(struct aead_givcrypt_request *req)
+{
+ return -ENOSYS;
+}
+
/**
- * HASH SHA1 Functions
+ * AES-CCM Functions
+ */
+int crypto4xx_setauthsize_aes(struct crypto_aead *ciper,
+ unsigned int authsize)
+{
+ struct aead_tfm *tfm =3D crypto_aead_crt(ciper);
+
+ switch (authsize) {
+ case 8:
+ case 12:
+ case 16:
+ case 10:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ tfm->authsize =3D authsize;
+ return 0;
+}
+
+int crypto4xx_setkey_aes_ccm(struct crypto_aead *cipher, const u8 *key,
+ unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_aead_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ int rc =3D 0;
+
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_AES128_CCM_LEN + (keylen-16) / 4);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ /* Setup SA */
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ sa->sa_contents =3D SA_AES_CCM_CONTENTS | (keylen << 2);
+
+ set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_CBC_MAC,
+ SA_CIPHER_ALG_AES,
+ SA_PAD_TYPE_ZERO, SA_OP_GROUP_BASIC,
+ SA_OPCODE_HASH_DECRYPT, DIR_INBOUND);
+
+ sa->sa_command_0.bf.digest_len =3D 0;
+ sa->sa_command_1.bf.key_len =3D keylen >> 3;
+ ctx->direction =3D DIR_INBOUND;
+ ctx->append_icv =3D 0;
+ ctx->is_gcm =3D 0;
+ ctx->hash_final =3D 1;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x11;
+
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+
+ set_dynamic_sa_command_1(sa, CRYPTO_MODE_AES_CTR, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB, SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_CBC_MAC,
+ SA_CIPHER_ALG_AES,
+ SA_PAD_TYPE_ZERO, SA_OP_GROUP_BASIC,
+ SA_OPCODE_ENCRYPT_HASH, DIR_OUTBOUND);
+ set_dynamic_sa_command_1(sa, CRYPTO_MODE_AES_CTR, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB, SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ return 0;
+}
+
+int crypto4xx_encrypt_aes_ccm(struct aead_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ struct crypto_aead *aead =3D crypto_aead_reqtfm(req);
+ struct dynamic_sa_ctl *sa;
+
+ ctx->direction =3D DIR_OUTBOUND;
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ if (req->assoclen)
+ sa->sa_command_1.bf.hash_crypto_offset =3D req->assoclen >> 2;
+
+ sa->sa_command_0.bf.digest_len =3D (crypto_aead_authsize(aead) >> 2);
+ if ((req->iv[0] & 7) =3D=3D 1)
+ sa->sa_command_1.bf.crypto_mode9_8 =3D 1;
+
+ ctx->append_icv =3D 1;
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->cryptlen, req->assoc, req->assoclen,
+ req->iv, 16);
+}
+
+int crypto4xx_decrypt_aes_ccm(struct aead_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ struct crypto_aead *aead =3D crypto_aead_reqtfm(req);
+ struct dynamic_sa_ctl *sa;
+
+ /* Support only counter field length of 2 and 4 bytes */
+ if ((req->iv[0] & 0x7) !=3D 1 && (req->iv[0] & 0x7) !=3D 3) {
+ printk(KERN_ERR "algorithm AES-CCM "
+ "unsupported counter length %d\n",
+ req->iv[0] & 0x7);
+ return -EINVAL;
+ }
+
+ ctx->direction =3D DIR_INBOUND;
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+
+ sa->sa_command_0.bf.digest_len =3D (crypto_aead_authsize(aead) >> 2);
+ if ((req->iv[0] & 7) =3D=3D 1)
+ sa->sa_command_1.bf.crypto_mode9_8 =3D 1;
+ else
+ sa->sa_command_1.bf.crypto_mode9_8 =3D 0;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->cryptlen, req->assoc, req->assoclen,
+ req->iv, 16);
+}
+
+int crypto4xx_givencrypt_aes_ccm(struct aead_givcrypt_request *req)
+{
+ return -ENOSYS;
+}
+
+int crypto4xx_givdecrypt_aes_ccm(struct aead_givcrypt_request *req)
+{
+ return -ENOSYS;
+}
+
+/**
+ * Kasumi Functions
+ *
+ */
+int crypto4xx_setkey_kasumi(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen,
+ unsigned char cm)
+{
+ struct crypto_tfm *tfm =3D crypto_ablkcipher_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ u32 sa_len =3D 0;
+ int rc;
+
+ if (keylen !=3D 16) {
+ crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ printk(KERN_ERR "%s: keylen fail\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Create SA - SA is created here as the alg init function is
+ * common to many algorithm and it does not have the SA length
+ * as it is specify to an algorithm. See setkey function has
+ * to be called for encryption/decryption algorithm once,
+ * it is okay to do this here.
+ */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ if (cm =3D=3D CRYPTO_MODE_KASUMI)
+ sa_len =3D SA_KASUMI_LEN;
+ else if (cm =3D=3D CRYPTO_MODE_KASUMI_f8)
+ sa_len =3D SA_KASUMI_F8_LEN;
+
+ rc =3D crypto4xx_alloc_sa(ctx, sa_len);
+ if (rc)
+ return rc;
+
+ if (!ctx->state_record) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ /* Setup SA - SA is a shared resource for request operation. As
+ * crypto alg and crypto mode can not be change, it should be
+ * ok to store them there. SA control words are not used by the
+ * hardware (configured in token instead), we use it to store
+ * software algorithm and mode selected.
+ */
+
+ if (cm =3D=3D CRYPTO_MODE_KASUMI) {
+ sa->sa_contents =3D SA_KASUMI_CONTENTS;
+ sa->sa_command_0.bf.cipher_alg =3D SA_CIPHER_ALG_KASUMI;
+ sa->sa_command_0.bf.hash_alg =3D SA_HASH_ALG_NULL;
+ sa->sa_command_0.bf.pad_type =3D 3; /* set to zero padding */
+ sa->sa_command_0.bf.opcode =3D 0;
+ sa->sa_command_1.bf.crypto_mode31 =3D (cm & 4) >> 2;
+ sa->sa_command_1.bf.crypto_mode9_8 =3D (cm & 3);
+ sa->sa_command_1.bf.feedback_mode =3D 0;
+ } else {
+ sa->sa_contents =3D SA_KASUMI_F8_CONTENTS;
+ sa->sa_command_0.bf.cipher_alg =3D SA_CIPHER_ALG_KASUMI;
+ sa->sa_command_0.bf.hash_alg =3D SA_HASH_ALG_NULL;
+ sa->sa_command_0.bf.pad_type =3D 3;
+ sa->sa_command_0.bf.load_iv =3D SA_LOAD_IV_FROM_STATE;
+ sa->sa_command_0.bf.opcode =3D SA_OPCODE_ENCRYPT;
+ sa->sa_command_1.bf.crypto_mode31 =3D (cm & 4) >> 2;;
+ sa->sa_command_1.bf.crypto_mode9_8 =3D (cm & 3);
+ sa->sa_command_1.bf.feedback_mode =3D 0;
+ sa->sa_command_1.bf.mutable_bit_proc =3D 1;
+ }
+
+ ctx->direction =3D DIR_INBOUND;
+ sa->sa_command_1.bf.sa_rev =3D 1;
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+ ctx->is_hash =3D 0;
+
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ sa->sa_command_0.bf.dir =3D DIR_INBOUND;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+}
+
+int crypto4xx_setkey_kasumi_p(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen)
+{
+ return crypto4xx_setkey_kasumi(cipher, key, keylen,
+ CRYPTO_MODE_KASUMI);
+}
+
+int crypto4xx_setkey_kasumi_f8(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen)
+{
+ return crypto4xx_setkey_kasumi(cipher, key, keylen,
+ CRYPTO_MODE_KASUMI_f8);
+}
+
+/**
+ * Kasumi and Kasumi f8 work with number of bits.
+ * The crypto engine can only take number bytes as source/destination =
length
+ * User should round up bit number to byte number. When receive the =
result
+ * packet and then mask off the extra bits in the last
+ * byte.
+ */
+int crypto4xx_encrypt_kasumi(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ ctx->direction =3D DIR_OUTBOUND;
+ ctx->pd_ctl =3D 0x1;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0, NULL, 0);
+}
+
+/**
+ * Kasumi and Kasumi f8 work with number of bits.
+ * The crypto engine can only take number bytes as source/destination =
length
+ * User should round up bit number to byte number.
+ * When receive the result packet and then mask off the extra bits in =
the last
+ * byte.
+ */
+int crypto4xx_decrypt_kasumi(struct aead_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->pd_ctl =3D 0x1;
+ ctx->direction =3D DIR_INBOUND;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->cryptlen, NULL, 0, NULL, 0);
+}
+
+/**
+ * Kasumi and Kasumi f8 work with number of bits.
+ * The crypto engine can only take number bytes as source/destination =
length
+ * The user should round up bit number to byte number.
+ * When receive the result packet and then mask
+ * off the extra bits in the last byte.
+ */
+int crypto4xx_encrypt_kasumi_f8(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->direction =3D DIR_OUTBOUND;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x1;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0, req->info, 8);
+}
+
+/** Note:
+ * Kasumi and Kasumi f8 work with number of bits.
+ * The crypto engine can only take number bytes as source/destination =
length
+ * User should round up bit number to byte number.
+ * When receive the result packet and then mask off the extra bits in =
the last
+ * byte.
+ */
+int crypto4xx_decrypt_kasumi_f8(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->direction =3D DIR_INBOUND;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x1;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0, req->info, 8);
+}
+
+/**
+ * ARC4 Functions
+ *
+ */
+int crypto4xx_setkey_arc4(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ablkcipher_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ int rc =3D 0;
+
+ /* Create SA */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_ARC4_LEN);
+ if (rc)
+ return rc;
+
+ crypto4xx_alloc_arc4_state_record(ctx);
+ if (ctx->arc4_state_record =3D=3D NULL) {
+ crypto4xx_free_sa(ctx);
+ return -ENOMEM;
+ }
+
+ /* Setup SA */
+ ctx->sa_len =3D SA_ARC4_LEN;
+ ctx->init_arc4 =3D 1;
+ ctx->direction =3D DIR_INBOUND;
+
+ sa =3D ctx->sa_in;
+ memset(((struct dynamic_sa_arc4 *)sa)->key, 0, 16);
+
+ crypto4xx_memcpy_le(((struct dynamic_sa_arc4 *)sa)->key, key, keylen);
+ sa->sa_contents =3D SA_ARC4_CONTENTS;
+
+ set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_NULL,
+ SA_CIPHER_ALG_ARC4, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_ENCRYPT,
+ DIR_INBOUND);
+
+ set_dynamic_sa_command_1(sa, 0, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB,
+ SA_EXTENDED_SN_OFF, SA_SEQ_MASK_OFF,
+ SA_MC_ENABLE, SA_NOT_COPY_PAD,
+ SA_COPY_PAYLOAD, SA_NOT_COPY_HDR);
+
+ sa->sa_command_1.bf.key_len =3D keylen;
+ memcpy(sa + get_dynamic_sa_offset_arc4_state_ptr(ctx),
+ (void *)&ctx->arc4_state_record_dma_addr, 4);
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+}
+
+int crypto4xx_arc4_encrypt(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ if (ctx->init_arc4) {
+ ctx->init_arc4 =3D 0;
+ ctx->pd_ctl =3D 9;
+ } else {
+ ctx->pd_ctl =3D 0x1;
+ }
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src,
+ req->dst,
+ req->nbytes, NULL, 0, NULL, 0);
+}
+
+int crypto4xx_arc4_decrypt(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ if (ctx->init_arc4) {
+ ctx->init_arc4 =3D 0;
+ ctx->pd_ctl =3D 9;
+ } else {
+ ctx->pd_ctl =3D 0x1;
+ }
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src,
+ req->dst,
+ req->nbytes, NULL, 0, NULL, 0);
+}
+
+/**
+ * Support MD5/SHA/HMAC Hashing Algorithms
+ *
*/
static int crypto4xx_hash_alg_init(struct crypto_tfm *tfm,
unsigned int sa_len,
@@ -185,7 +1229,6 @@ static int crypto4xx_hash_alg_init(struct =
crypto_tfm *tfm,
struct crypto4xx_alg *my_alg =3D crypto_alg_to_crypto4xx_alg(alg);
struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
struct dynamic_sa_ctl *sa;
- struct dynamic_sa_hash160 *sa_in;
int rc;
=20
ctx->dev =3D my_alg->dev;
@@ -210,6 +1253,9 @@ static int crypto4xx_hash_alg_init(struct =
crypto_tfm *tfm,
=20
tfm->crt_ahash.reqsize =3D sizeof(struct crypto4xx_ctx);
sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ /*
+ * Setup hash algorithm and hash mode
+ */
set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
SA_NO_HEADER_PROC, ha, SA_CIPHER_ALG_NULL,
@@ -220,13 +1266,12 @@ static int crypto4xx_hash_alg_init(struct =
crypto_tfm *tfm,
SA_SEQ_MASK_OFF, SA_MC_ENABLE,
SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
SA_NOT_COPY_HDR);
+
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+ sa->sa_contents =3D crypto4xx_sa_hash_tbl[0][ha];
ctx->direction =3D DIR_INBOUND;
- sa->sa_contents =3D SA_HASH160_CONTENTS;
- sa_in =3D (struct dynamic_sa_hash160 *) ctx->sa_in;
- /* Need to zero hash digest in SA */
- memset(sa_in->inner_digest, 0, sizeof(sa_in->inner_digest));
- memset(sa_in->outer_digest, 0, sizeof(sa_in->outer_digest));
- sa_in->state_ptr =3D ctx->state_record_dma_addr;
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
=20
return 0;
@@ -260,7 +1305,7 @@ int crypto4xx_hash_update(struct ahash_request =
*req)
=20
return crypto4xx_build_pd(&req->base, ctx, req->src,
(struct scatterlist *) req->result,
- req->nbytes, NULL, 0);
+ req->nbytes, NULL, 0, NULL, 0);
}
=20
int crypto4xx_hash_final(struct ahash_request *req)
@@ -278,16 +1323,431 @@ int crypto4xx_hash_digest(struct ahash_request =
*req)
=20
return crypto4xx_build_pd(&req->base, ctx, req->src,
(struct scatterlist *) req->result,
- req->nbytes, NULL, 0);
+ req->nbytes, NULL, 0, NULL, 0);
}
=20
/**
* SHA1 Algorithm
*/
+
+int crypto4xx_md5_alg_init(struct crypto_tfm *tfm)
+{
+ return crypto4xx_hash_alg_init(tfm, SA_HASH128_LEN, SA_HASH_ALG_MD5,
+ SA_HASH_MODE_HASH);
+}
+
+int crypto4xx_hash_hmac_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen,
+ unsigned int sa_len,
+ unsigned char ha,
+ unsigned char hm,
+ unsigned int max_keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ahash_tfm(hash);
+ struct crypto_alg *alg =3D tfm->__crt_alg;
+ struct crypto4xx_alg *my_alg =3D crypto_alg_to_crypto4xx_alg(alg);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ int bs =3D crypto_tfm_alg_blocksize(tfm);
+ int ds =3D crypto_ahash_digestsize(hash);
+ int rc;
+
+ ctx->dev =3D my_alg->dev;
+
+ if (keylen > max_keylen) {
+ crypto_ahash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -1;
+ }
+
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ /* Create SA */
+ rc =3D crypto4xx_alloc_sa(ctx, sa_len);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc)
+ goto err;
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+
+ /*
+ * Setup hash algorithm and hash mode
+ */
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
+ SA_NO_HEADER_PROC,
+ ha, SA_CIPHER_ALG_NULL, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_HASH,
+ DIR_INBOUND);
+ set_dynamic_sa_command_1(sa, 0, hm,
+ CRYPTO_FEEDBACK_MODE_NO_FB,
+ SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+ sa->sa_contents =3D crypto4xx_sa_hash_tbl[0][ha];
+ ctx->direction =3D DIR_INBOUND;
+ memcpy((ctx->sa_in) + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ rc =3D crypto4xx_pre_compute_hmac(ctx, (void *)key, keylen, bs, ha, =
ds);
+ if (rc) {
+ printk(KERN_ERR "Hmac Initial Digest Calculation failed\n");
+ goto err;
+ }
+
+ ctx->hash_final =3D 1;
+ ctx->is_hash =3D 1;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+err:
+ crypto4xx_free_sa(ctx);
+ return rc;
+}
+
+int crypto4xx_md5_hmac_setkey(struct crypto_ahash *hash, const u8 *key,
+ unsigned int keylen)
+{
+ return crypto4xx_hash_hmac_setkey(hash, key, keylen, SA_HASH128_LEN,
+ SA_HASH_ALG_MD5, SA_HASH_MODE_HMAC,
+ 256);
+}
+
+/**
+ * SHA1 and SHA2 Algorithm
+ *
+ */
int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm)
{
return crypto4xx_hash_alg_init(tfm, SA_HASH160_LEN, SA_HASH_ALG_SHA1,
SA_HASH_MODE_HASH);
}
=20
+int crypto4xx_sha1_hmac_setkey(struct crypto_ahash *hash, const u8 =
*key,
+ unsigned int keylen)
+{
+ return crypto4xx_hash_hmac_setkey(hash, key, keylen, SA_HASH160_LEN,
+ SA_HASH_ALG_SHA1, SA_HASH_MODE_HMAC,
+ 256);
+}
+
+int crypto4xx_sha2_alg_init(struct crypto_tfm *tfm)
+{
+ int ds =3D crypto_ahash_digestsize(__crypto_ahash_cast(tfm));
+ u8 ha;
+
+ switch (ds) {
+ default:
+ case 256/8:
+ ha =3D SA_HASH_ALG_SHA256;
+ break;
+ case 224/8:
+ ha =3D SA_HASH_ALG_SHA224;
+ break;
+ case 512/8:
+ ha =3D SA_HASH_ALG_SHA512;
+ break;
+ case 384/8:
+ ha =3D SA_HASH_ALG_SHA384;
+ break;
+ }
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+
+ return crypto4xx_hash_alg_init(tfm,
+ crypto4xx_sa_hash_tbl[2][ha], ha, 0);
+}
+
+int crypto4xx_sha2_hmac_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen)
+{
+ int ds =3D crypto_ahash_digestsize(hash);
+ unsigned char ha;
+
+ switch (ds) {
+ default:
+ case 256/8:
+ ha =3D SA_HASH_ALG_SHA256;
+ break;
+ case 224/8:
+ ha =3D SA_HASH_ALG_SHA224;
+ break;
+ case 512/8:
+ ha =3D SA_HASH_ALG_SHA512;
+ break;
+ case 384/8:
+ ha =3D SA_HASH_ALG_SHA384;
+ break;
+ }
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+
+ return crypto4xx_hash_hmac_setkey(hash, key, keylen,
+ crypto4xx_sa_hash_tbl[2][ha],
+ ha,
+ SA_HASH_MODE_HMAC,
+ 512);
+}
+
+/**
+ * AES-XCBC-MAC Algorithm
+ *
+ */
+int crypto4xx_xcbc_digest(const unsigned char *key,
+ unsigned int keylen,
+ u8 *sa_hash, int bs)
+{
+ struct scatterlist sg[1];
+ struct crypto_blkcipher *aes_tfm =3D NULL;
+ struct blkcipher_desc desc;
+ int rc;
+ u8 *digest;
+
+ /* Load pre-computed key value into SA */
+ aes_tfm =3D crypto_alloc_blkcipher("ecb(aes)", 0, CRYPTO_ALG_ASYNC);
+ if (IS_ERR(aes_tfm)) {
+ rc =3D PTR_ERR(aes_tfm);
+ printk(KERN_ERR "failed to load transform"
+ " for ecb(aes) error %d\n", rc);
+ goto err_alg;
+ }
+ desc.tfm =3D aes_tfm;
+ desc.flags =3D 0;
+ rc =3D crypto_blkcipher_setkey(desc.tfm, key, keylen);
+ if (rc) {
+ printk(KERN_ERR "failed to load key error %d\n", rc);
+ goto err_alg;
+ }
+ digest =3D kmalloc(16, GFP_KERNEL);
+ if (digest =3D=3D NULL) {
+ rc =3D -ENOMEM;
+ goto err_alg;
+ }
+
+ memset(digest, 0x01, bs);
+ sg_init_one(&sg[0], digest, bs);
+ rc =3D crypto_blkcipher_encrypt(&desc, sg, sg, bs);
+ if (rc < 0) {
+ printk(KERN_ERR "failed to hash key error %d\n", rc);
+ goto err_alg;
+ }
+
+ crypto4xx_memcpy_le((void *) sa_hash, digest, bs);
+
+ memset(digest, 0x02, bs);
+ sg_init_one(&sg[0], digest, bs);
+ rc =3D crypto_blkcipher_encrypt(&desc, sg, sg, bs);
+ if (rc < 0) {
+ printk(KERN_ERR "failed to hash key error %d\n", rc);
+ goto err_alg;
+ }
+
+ sa_hash +=3D 32;
+ crypto4xx_memcpy_le((void *) sa_hash, digest, bs);
+
+ memset(digest, 0x03, bs);
+ sg_init_one(&sg[0], digest, bs);
+ rc =3D crypto_blkcipher_encrypt(&desc, sg, sg, bs);
+ if (rc < 0) {
+ printk(KERN_ERR "failed to hash key error %d\n", rc);
+ goto err_alg;
+ }
+
+ sa_hash +=3D 16;
+ crypto4xx_memcpy_le((void *) sa_hash, digest, bs);
+
+ crypto_free_blkcipher(aes_tfm);
+
+ return 0;
+err_alg:
+ if (aes_tfm)
+ crypto_free_blkcipher(aes_tfm);
+ return rc;
+}
+
+int crypto4xx_xcbc_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ahash_tfm(hash);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ int bs =3D crypto_tfm_alg_blocksize(tfm);
+ struct dynamic_sa_ctl *sa;
+ u8 *sa_hash;
+ int rc =3D 0;
+
+ if (keylen !=3D 128/8) {
+ crypto_ahash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ /* Create SA */
+ rc =3D crypto4xx_alloc_sa(ctx, SA_AES128_XCBC_MAC_LEN);
+ if (rc)
+ return rc;
=20
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ rc =3D -ENOMEM;
+ goto err;
+ }
+ }
+
+ ctx->direction =3D DIR_INBOUND;
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ /*
+ * Setup hash algorithm and hash mode
+ */
+ sa->sa_contents =3D SA_AES128_XCBC_MAC_CONTENTS;
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
+ SA_NO_HEADER_PROC,
+ SA_HASH_ALG_AES_XCBC_MAC_128,
+ SA_CIPHER_ALG_NULL, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_HASH,
+ DIR_INBOUND);
+ set_dynamic_sa_command_1(sa, 0, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB,
+ SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+
+ memcpy((void *)(ctx->sa_in +
+ get_dynamic_sa_offset_state_ptr_field(ctx)),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->is_hash =3D 1;
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ sa_hash =3D (u8 *)(&(((struct dynamic_sa_aes128_xcbc_mac *)
+ ctx->sa_in)->inner_digest));
+ rc =3D crypto4xx_xcbc_digest(key, keylen, sa_hash, bs);
+ if (rc) {
+ printk(KERN_ERR "XCBC Digest Calculation Failed %d\n", rc);
+ goto err;
+ }
+
+ ctx->is_hash =3D 1;
+ ctx->hash_final =3D 1;
+ ctx->pd_ctl =3D 0x11;
+
+ ctx->direction =3D DIR_INBOUND;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+err:
+ crypto4xx_free_sa(ctx);
+ return rc;
+}
+
+/**
+ * Kasumi F9 - Hash Algorithms
+ *
+ */
+int crypto4xx_kasumi_f9_setkey(struct crypto_ahash *hash,
+ const u8 *key, unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ahash_tfm(hash);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ int rc;
+ struct dynamic_sa_ctl *sa;
+
+ if (keylen !=3D 16) {
+ crypto_ahash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+
+ /* Create SA */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_KASUMI_F9_LEN);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ /*
+ * Setup hash algorithm and hash mode
+ */
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_KASUMI_f9,
+ SA_CIPHER_ALG_NULL, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_HASH,
+ DIR_INBOUND);
+ set_dynamic_sa_command_1(sa, 0, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB, SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+ sa->sa_contents =3D SA_KASUMI_F9_CONTENTS;
+
+ ctx->direction =3D DIR_INBOUND;
+ memcpy((void *)(ctx->sa_in +
+ get_dynamic_sa_offset_state_ptr_field(ctx)),
+ (void *)&ctx->state_record_dma_addr, 4);
+
+ crypto4xx_memcpy_le(ctx->sa_in +
+ get_dynamic_sa_offset_inner_digest(ctx), key, keylen);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ ctx->is_hash =3D 1;
+ ctx->hash_final =3D 1;
+ ctx->pd_ctl =3D 0x11;
+ ctx->bypass =3D 4;
+
+ return 0;
+}
+
+int crypto4xx_kasumi_f9_digest(struct ahash_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ struct scatterlist *src =3D req->src;
+ struct dynamic_sa_ctl *sa;
+ dma_addr_t addr;
+
+ /*
+ * We have prepended count/fresh/direction/reserv total
+ * 16byte before the plaintext
+ * so, need to modify the length.
+ * We doing so, to make use of tcrypt.c's hash_test.
+ */
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+
+ addr =3D dma_map_page(NULL, sg_page(src), src->offset,
+ src->length, DMA_TO_DEVICE);
+ crypto4xx_memcpy_le((void *)sa +
+ get_dynamic_sa_offset_outer_digest(ctx),
+ phys_to_virt(addr), 12);
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src,
+ (struct scatterlist *)req->result,
+ req->nbytes, NULL, 0, NULL, 0);
+}
--=20
1.5.5
^ permalink raw reply related
* Re: [PATCH V2 2/2] mtd/maps/mtd-ram: add an of-platform driver
From: Albrecht Dreß @ 2009-06-15 17:43 UTC (permalink / raw)
To: Wolfram Sang
Cc: linuxppc-dev, devicetree-discuss, linux-mtd, David Woodhouse,
Ben Dooks
In-Reply-To: <1244203514-12516-3-git-send-email-w.sang@pengutronix.de>
[-- Attachment #1: Type: text/plain, Size: 608 bytes --]
Am 05.06.09 14:05 schrieb(en) Wolfram Sang:
> Create an of-aware driver using the now exported generic functions
> from plat-ram.c. Also add the documentation for the binding.
> Partitions are not yet supported. Tested on a phyCORE-MPC5200B-IO.
Dumb question: what is the current status of this patch? I ask because
I re-wrote my '5200 16-bit Local Plus Bus patch' according to Grant's
suggestions, and I believe of_ram_probe() of your patch is the right
place to check if it's attached to "fsl,mpc5200-lpb", and to change the
write cb if the bankwidth equals 2.
Thanks, Albrecht.
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox