* Re: [PATCH] powerpc: Add configurable -Werror for arch/powerpc
From: Michael Ellerman @ 2009-06-15 12:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <1245058807.12400.0.camel@pasglop>
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On Mon, 2009-06-15 at 19:40 +1000, Benjamin Herrenschmidt wrote:
> > Currently this appears to break only one of the defconfigs, chrp32.
> >
> > http://kisskb.ellerman.id.au/kisskb/head/1907/
> >
> > And that's a legitimate error AFAICT:
> >
> > arch/powerpc/platforms/chrp/setup.c:378: error: the frame size of 1040 bytes is larger than 1024 bytes
> >
> > From:
> >
> > 367 void
> > 368 chrp_event_scan(unsigned long unused)
> > 369 {
> > 370 unsigned char log[1024];
> > 371 int ret = 0;
>
> I wonder to what extent we could merge that with the pSeries
> event-scan...
Yeah that occured to me, someone with a chrp machine would need to test
it, do we have one?
> We can have a closer look tomorrow. In any case, stack alloc for that is
> indeed fishy.
The obvious patch to make it static doesn't fly because it's called on
every cpu via a timer, so it needs to be a per-cpu at least I think. Or
borrow the pseries trick of calling it on each cpu in succession, or
just borrow the pseries code.
cheers
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^ permalink raw reply
* Re: [OOPS] hugetlbfs tests with 2.6.30-rc8-git1
From: Sachin Sant @ 2009-06-15 13:00 UTC (permalink / raw)
To: michael; +Cc: Mel Gorman, linuxppc-dev
In-Reply-To: <1245027396.7705.23.camel@concordia>
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Michael Ellerman wrote:
> Hi Sachin,
>
> Rather than "-git7" can you tell us the actual SHA, I don't know what
> git7 is.
>
Corresponding SHA is 44b7532b8b464f606053562400719c9c21276037.
>> Here is the supporting data.
>>
>> cpu 0x1: Vector: 300 (Data Access) at [c0000000fe9b3220]
>> pc: c00000000003d620: .hpte_need_flush+0x1bc/0x2d8
>> lr: c00000000003d4d0: .hpte_need_flush+0x6c/0x2d8
>> sp: c0000000fe9b34a0
>> msr: 8000000000009032
>> dar: c0000000283b0d78
>>
>
> This address looks pretty innocuous, but I notice you have
> DEBUG_PAGEALLOC=y, so presumably that's why it's triggering.
>
> I can't see from the snippet of disassembly you posted where in the C
> code we are, can you work it out?
>
The corresponding C code is :
278: 2f 80 00 00 cmpwi cr7,r0,0
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
vaddr = hpt_va(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
27c: eb 89 80 00 ld r28,-32768(r9)
^^^^ %pc points to the above line. ^^^^^
* Check if we have an active batch on this CPU. If not, just
* flush now and return. For now, we don global invalidates
* in that case, might be worth testing the mm cpu mask though
* and decide to use local invalidates instead...
I have attached the objdump o/p for tlb_hash64.o.
I could not recreate this issue with git8 kernel
(45e3e1935e2857c54783291107d33323b3ef33c8).
Thanks
-Sachin
--
---------------------------------
Sachin Sant
IBM Linux Technology Center
India Systems and Technology Labs
Bangalore, India
---------------------------------
[-- Attachment #2: tlb_hash64_objlist --]
[-- Type: text/plain, Size: 23282 bytes --]
arch/powerpc/mm/tlb_hash64.o: file format elf64-powerpc
Disassembly of section .text:
0000000000000000 <.__flush_tlb_pending>:
* in a batch.
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
{
0: fb e1 ff f8 std r31,-8(r1)
4: 7c 08 02 a6 mflr r0
8: f8 01 00 10 std r0,16(r1)
extern const unsigned long
cpu_bit_bitmap[BITS_PER_LONG+1][BITS_TO_LONGS(NR_CPUS)];
static inline const struct cpumask *get_cpu_mask(unsigned int cpu)
{
const unsigned long *p = cpu_bit_bitmap[1 + cpu % BITS_PER_LONG];
c: e8 02 00 00 ld r0,0(r2)
10: 7c 7f 1b 78 mr r31,r3
14: fb c1 ff f0 std r30,-16(r1)
const unsigned long *src2, int nbits)
{
if (small_const_nbits(nbits))
return ! ((*src1 ^ *src2) & BITMAP_LAST_WORD_MASK(nbits));
else
return __bitmap_equal(src1, src2, nbits);
18: 38 a0 04 00 li r5,1024
1c: f8 21 ff 81 stdu r1,-128(r1)
const struct cpumask *tmp;
int i, local = 0;
i = batch->index;
tmp = cpumask_of(smp_processor_id());
20: a0 8d 00 0a lhz r4,10(r13)
24: e8 63 00 10 ld r3,16(r3)
28: 78 89 06 a0 clrldi r9,r4,58
2c: 78 84 d1 82 rldicl r4,r4,58,6
30: 39 29 00 01 addi r9,r9,1
34: 78 84 1f 24 rldicr r4,r4,3,60
38: 79 29 3e 24 rldicr r9,r9,7,56
3c: 38 63 03 10 addi r3,r3,784
40: 7c 00 4a 14 add r0,r0,r9
void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
{
const struct cpumask *tmp;
int i, local = 0;
i = batch->index;
44: eb df 00 0e lwa r30,12(r31)
48: 7c 84 00 50 subf r4,r4,r0
4c: 48 00 00 01 bl 4c <.__flush_tlb_pending+0x4c>
50: 60 00 00 00 nop
54: 7c 69 fe 70 srawi r9,r3,31
tmp = cpumask_of(smp_processor_id());
if (cpumask_equal(mm_cpumask(batch->mm), tmp))
local = 1;
if (i == 1)
58: 2f 9e 00 01 cmpwi cr7,r30,1
5c: 7d 20 1a 78 xor r0,r9,r3
60: 7c 00 48 50 subf r0,r0,r9
64: 54 00 0f fe rlwinm r0,r0,1,31,31
68: 7c 04 07 b4 extsw r4,r0
6c: 40 9e 00 28 bne- cr7,94 <.__flush_tlb_pending+0x94>
flush_hash_page(batch->vaddr[0], batch->pte[0],
70: 7c 88 23 78 mr r8,r4
74: e8 7f 0c 18 ld r3,3096(r31)
78: e8 df 12 1a lwa r6,4632(r31)
7c: e8 ff 12 1e lwa r7,4636(r31)
80: e8 9f 00 18 ld r4,24(r31)
84: e8 bf 00 20 ld r5,32(r31)
88: 48 00 00 01 bl 88 <.__flush_tlb_pending+0x88>
8c: 60 00 00 00 nop
90: 48 00 00 10 b a0 <.__flush_tlb_pending+0xa0>
batch->psize, batch->ssize, local);
else
flush_hash_range(i, local);
94: 7f c3 f3 78 mr r3,r30
98: 48 00 00 01 bl 98 <.__flush_tlb_pending+0x98>
9c: 60 00 00 00 nop
batch->index = 0;
}
a0: 38 21 00 80 addi r1,r1,128
if (i == 1)
flush_hash_page(batch->vaddr[0], batch->pte[0],
batch->psize, batch->ssize, local);
else
flush_hash_range(i, local);
batch->index = 0;
a4: 38 00 00 00 li r0,0
a8: f8 1f 00 08 std r0,8(r31)
}
ac: e8 01 00 10 ld r0,16(r1)
b0: eb c1 ff f0 ld r30,-16(r1)
b4: 7c 08 03 a6 mtlr r0
b8: eb e1 ff f8 ld r31,-8(r1)
bc: 4e 80 00 20 blr
00000000000000c0 <.hpte_need_flush>:
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
c0: fa c1 ff b0 std r22,-80(r1)
c4: 7c 08 02 a6 mflr r0
c8: f8 01 00 10 std r0,16(r1)
* NOTE: when using special 64K mappings in 4K environment like
* for SPEs, we obtain the page size from the slice, which thus
* must still exist (and thus the VMA not reused) at the time
* of this call
*/
if (huge) {
cc: 2f a7 00 00 cmpdi cr7,r7,0
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
d0: fb 21 ff c8 std r25,-56(r1)
#else
BUG();
psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
#endif
} else
psize = pte_pagesize_index(mm, addr, pte);
d4: 6c c0 10 00 xoris r0,r6,4096
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
d8: fb 41 ff d0 std r26,-48(r1)
dc: 7c d9 33 78 mr r25,r6
e0: fb 61 ff d8 std r27,-40(r1)
e4: 7c b6 2b 78 mr r22,r5
e8: fb 81 ff e0 std r28,-32(r1)
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
ec: eb 82 00 08 ld r28,8(r2)
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
f0: fb c1 ff f0 std r30,-16(r1)
#else
BUG();
psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
#endif
} else
psize = pte_pagesize_index(mm, addr, pte);
f4: 78 1b 27 e2 rldicl r27,r0,36,63
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
f8: fb e1 ff f8 std r31,-8(r1)
fc: 7c 7a 1b 78 mr r26,r3
100: fa e1 ff b8 std r23,-72(r1)
i = batch->index;
/* We mask the address for the base page size. Huge pages will
* have applied their own masking already
*/
addr &= PAGE_MASK;
104: 78 9f 03 e4 rldicr r31,r4,0,47
*
* Must be called from within some kind of spinlock/non-preempt region...
*/
void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, unsigned long pte, int huge)
{
108: fb 01 ff c0 std r24,-64(r1)
10c: fb a1 ff e8 std r29,-24(r1)
110: f8 21 ff 41 stdu r1,-192(r1)
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
114: ea ed 00 40 ld r23,64(r13)
118: 7f dc ba 14 add r30,r28,r23
unsigned int psize;
int ssize;
real_pte_t rpte;
int i;
i = batch->index;
11c: eb 1e 00 08 ld r24,8(r30)
* NOTE: when using special 64K mappings in 4K environment like
* for SPEs, we obtain the page size from the slice, which thus
* must still exist (and thus the VMA not reused) at the time
* of this call
*/
if (huge) {
120: 41 9e 00 14 beq- cr7,134 <.hpte_need_flush+0x74>
#ifdef CONFIG_HUGETLB_PAGE
psize = get_slice_psize(mm, addr);;
124: 7f e4 fb 78 mr r4,r31
128: 48 00 00 01 bl 128 <.hpte_need_flush+0x68>
12c: 60 00 00 00 nop
130: 7c 7b 1b 78 mr r27,r3
#endif
} else
psize = pte_pagesize_index(mm, addr, pte);
/* Build full vaddr */
if (!is_kernel_addr(addr)) {
134: e8 02 00 10 ld r0,16(r2)
138: 7f bf 00 40 cmpld cr7,r31,r0
13c: 41 9d 00 a8 bgt- cr7,1e4 <.hpte_need_flush+0x124>
/* Returns the segment size indicator for a user address */
static inline int user_segment_size(unsigned long addr)
{
/* Use 1T segments if possible for addresses >= 1T */
if (addr >= (1UL << SID_SHIFT_1T))
140: 38 00 ff ff li r0,-1
144: 3b a0 00 00 li r29,0
148: 78 00 06 00 clrldi r0,r0,24
14c: 7f bf 00 40 cmpld cr7,r31,r0
150: 40 9d 00 0c ble- cr7,15c <.hpte_need_flush+0x9c>
return mmu_highuser_ssize;
154: e9 22 00 18 ld r9,24(r2)
158: eb a9 00 02 lwa r29,0(r9)
/* This is only valid for user addresses (which are below 2^44) */
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
int ssize)
{
if (ssize == MMU_SEGSIZE_256M)
15c: 2f bd 00 00 cmpdi cr7,r29,0
ssize = user_segment_size(addr);
vsid = get_vsid(mm->context.id, addr, ssize);
160: e9 7a 03 90 ld r11,912(r26)
164: 40 9e 00 3c bne- cr7,1a0 <.hpte_need_flush+0xe0>
return vsid_scramble((context << USER_ESID_BITS)
168: 79 6b 83 e4 rldicr r11,r11,16,47
16c: 7b e0 27 02 rldicl r0,r31,36,28
170: 3d 20 0b f6 lis r9,3062
174: 7c 00 5b 78 or r0,r0,r11
178: 61 29 e6 1b ori r9,r9,58907
17c: 7c 00 49 d2 mulld r0,r0,r9
| (ea >> SID_SHIFT), 256M);
180: 78 09 07 00 clrldi r9,r0,28
184: 78 00 e1 20 rldicl r0,r0,28,36
188: 7d 29 02 14 add r9,r9,r0
18c: 38 09 00 01 addi r0,r9,1
190: 78 00 e1 20 rldicl r0,r0,28,36
194: 7c 00 4a 14 add r0,r0,r9
198: 78 09 07 00 clrldi r9,r0,28
19c: 48 00 00 38 b 1d4 <.hpte_need_flush+0x114>
return vsid_scramble((context << USER_ESID_BITS_1T)
1a0: 79 6b 26 e4 rldicr r11,r11,4,59
1a4: 7b e0 c2 20 rldicl r0,r31,24,40
1a8: 3d 20 00 bf lis r9,191
1ac: 7c 00 5b 78 or r0,r0,r11
1b0: 61 29 50 d9 ori r9,r9,20697
1b4: 7c 00 49 d2 mulld r0,r0,r9
| (ea >> SID_SHIFT_1T), 1T);
1b8: 78 09 02 20 clrldi r9,r0,40
1bc: 78 00 46 02 rldicl r0,r0,40,24
1c0: 7d 29 02 14 add r9,r9,r0
1c4: 38 09 00 01 addi r0,r9,1
1c8: 78 00 46 02 rldicl r0,r0,40,24
1cc: 7c 00 4a 14 add r0,r0,r9
1d0: 78 09 02 20 clrldi r9,r0,40
WARN_ON(vsid == 0);
1d4: 7d 20 00 74 cntlzd r0,r9
1d8: 78 00 d1 82 rldicl r0,r0,58,6
1dc: 0b 00 00 00 tdnei r0,0
1e0: 48 00 00 70 b 250 <.hpte_need_flush+0x190>
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
1e4: e9 22 00 20 ld r9,32(r2)
1e8: eb a9 00 02 lwa r29,0(r9)
#endif /* 1 */
/* This is only valid for addresses >= PAGE_OFFSET */
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
{
if (ssize == MMU_SEGSIZE_256M)
1ec: 2f bd 00 00 cmpdi cr7,r29,0
1f0: 40 9e 00 34 bne- cr7,224 <.hpte_need_flush+0x164>
return vsid_scramble(ea >> SID_SHIFT, 256M);
1f4: 3d 20 0b f6 lis r9,3062
1f8: 7b e0 27 02 rldicl r0,r31,36,28
1fc: 61 29 e6 1b ori r9,r9,58907
200: 7c 00 49 d2 mulld r0,r0,r9
204: 78 09 07 00 clrldi r9,r0,28
208: 78 00 e1 20 rldicl r0,r0,28,36
20c: 7d 29 02 14 add r9,r9,r0
210: 38 09 00 01 addi r0,r9,1
214: 78 00 e1 20 rldicl r0,r0,28,36
218: 7c 00 4a 14 add r0,r0,r9
21c: 78 09 07 00 clrldi r9,r0,28
220: 48 00 00 38 b 258 <.hpte_need_flush+0x198>
return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
224: 3d 20 00 bf lis r9,191
228: 7b e0 c2 20 rldicl r0,r31,24,40
22c: 61 29 50 d9 ori r9,r9,20697
230: 7c 00 49 d2 mulld r0,r0,r9
234: 78 09 02 20 clrldi r9,r0,40
238: 78 00 46 02 rldicl r0,r0,40,24
23c: 7d 29 02 14 add r9,r9,r0
240: 38 09 00 01 addi r0,r9,1
244: 78 00 46 02 rldicl r0,r0,40,24
248: 7c 00 4a 14 add r0,r0,r9
24c: 78 09 02 20 clrldi r9,r0,40
* Build a VA given VSID, EA and segment size
*/
static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
int ssize)
{
if (ssize == MMU_SEGSIZE_256M)
250: 2f bd 00 00 cmpdi cr7,r29,0
254: 40 9e 00 10 bne- cr7,264 <.hpte_need_flush+0x1a4>
return (vsid << 28) | (ea & 0xfffffffUL);
258: 79 29 e0 e4 rldicr r9,r9,28,35
25c: 7b e0 01 20 clrldi r0,r31,36
260: 48 00 00 0c b 26c <.hpte_need_flush+0x1ac>
return (vsid << 40) | (ea & 0xffffffffffUL);
264: 79 29 45 c6 rldicr r9,r9,40,23
268: 7b e0 06 00 clrldi r0,r31,24
26c: 7d 3f 03 78 or r31,r9,r0
* Check if we have an active batch on this CPU. If not, just
* flush now and return. For now, we don global invalidates
* in that case, might be worth testing the mm cpu mask though
* and decide to use local invalidates instead...
*/
if (!batch->active) {
270: 7c 1c b8 2e lwzx r0,r28,r23
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
vaddr = hpt_va(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
274: 3d 36 00 01 addis r9,r22,1
* Check if we have an active batch on this CPU. If not, just
* flush now and return. For now, we don global invalidates
* in that case, might be worth testing the mm cpu mask though
* and decide to use local invalidates instead...
*/
if (!batch->active) {
278: 2f 80 00 00 cmpwi cr7,r0,0
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
vaddr = hpt_va(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
27c: eb 89 80 00 ld r28,-32768(r9)
* Check if we have an active batch on this CPU. If not, just
* flush now and return. For now, we don global invalidates
* in that case, might be worth testing the mm cpu mask though
* and decide to use local invalidates instead...
*/
if (!batch->active) {
280: 40 9e 00 28 bne- cr7,2a8 <.hpte_need_flush+0x1e8>
flush_hash_page(vaddr, rpte, psize, ssize, 0);
284: 7f e3 fb 78 mr r3,r31
288: 7f 24 cb 78 mr r4,r25
28c: 7f 85 e3 78 mr r5,r28
290: 7f 66 07 b4 extsw r6,r27
294: 7f a7 eb 78 mr r7,r29
298: 39 00 00 00 li r8,0
29c: 48 00 00 01 bl 29c <.hpte_need_flush+0x1dc>
2a0: 60 00 00 00 nop
2a4: 48 00 00 bc b 360 <.hpte_need_flush+0x2a0>
* will change mid stream.
*
* We also need to ensure only one page size is present in a given
* batch
*/
if (i != 0 && (mm != batch->mm || batch->psize != psize ||
2a8: 7f 0b 07 b5 extsw. r11,r24
2ac: 41 82 00 30 beq- 2dc <.hpte_need_flush+0x21c>
2b0: e8 1e 00 10 ld r0,16(r30)
2b4: 7f ba 00 00 cmpd cr7,r26,r0
2b8: 40 9e 00 1c bne- cr7,2d4 <.hpte_need_flush+0x214>
2bc: 80 1e 12 18 lwz r0,4632(r30)
2c0: 7f 80 d8 00 cmpw cr7,r0,r27
2c4: 40 9e 00 10 bne- cr7,2d4 <.hpte_need_flush+0x214>
2c8: 80 1e 12 1c lwz r0,4636(r30)
2cc: 7f 80 e8 00 cmpw cr7,r0,r29
2d0: 41 9e 00 1c beq- cr7,2ec <.hpte_need_flush+0x22c>
batch->ssize != ssize)) {
__flush_tlb_pending(batch);
2d4: 7f c3 f3 78 mr r3,r30
2d8: 48 00 00 01 bl 2d8 <.hpte_need_flush+0x218>
i = 0;
}
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
2dc: 39 60 00 00 li r11,0
batch->ssize != ssize)) {
__flush_tlb_pending(batch);
i = 0;
}
if (i == 0) {
batch->mm = mm;
2e0: fb 5e 00 10 std r26,16(r30)
batch->psize = psize;
2e4: 93 7e 12 18 stw r27,4632(r30)
batch->ssize = ssize;
2e8: 93 be 12 1c stw r29,4636(r30)
}
batch->pte[i] = rpte;
batch->vaddr[i] = vaddr;
batch->index = ++i;
2ec: 38 0b 00 01 addi r0,r11,1
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
2f0: 39 2b 00 01 addi r9,r11,1
batch->vaddr[i] = vaddr;
2f4: 39 6b 01 82 addi r11,r11,386
batch->index = ++i;
2f8: 7c 00 07 b4 extsw r0,r0
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
2fc: 79 29 26 e4 rldicr r9,r9,4,59
batch->vaddr[i] = vaddr;
300: 79 6b 1f 24 rldicr r11,r11,3,60
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
304: 7d 3e 4a 14 add r9,r30,r9
batch->vaddr[i] = vaddr;
308: 7d 7e 5a 14 add r11,r30,r11
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
30c: fb 29 00 08 std r25,8(r9)
batch->vaddr[i] = vaddr;
batch->index = ++i;
if (i >= PPC64_TLB_BATCH_NR)
310: 2f 80 00 bf cmpwi cr7,r0,191
if (i == 0) {
batch->mm = mm;
batch->psize = psize;
batch->ssize = ssize;
}
batch->pte[i] = rpte;
314: fb 89 00 10 std r28,16(r9)
batch->vaddr[i] = vaddr;
318: fb eb 00 08 std r31,8(r11)
batch->index = ++i;
31c: f8 1e 00 08 std r0,8(r30)
if (i >= PPC64_TLB_BATCH_NR)
320: 40 9d 00 40 ble- cr7,360 <.hpte_need_flush+0x2a0>
__flush_tlb_pending(batch);
}
324: 38 21 00 c0 addi r1,r1,192
}
batch->pte[i] = rpte;
batch->vaddr[i] = vaddr;
batch->index = ++i;
if (i >= PPC64_TLB_BATCH_NR)
__flush_tlb_pending(batch);
328: 7f c3 f3 78 mr r3,r30
}
32c: e8 01 00 10 ld r0,16(r1)
330: ea c1 ff b0 ld r22,-80(r1)
334: 7c 08 03 a6 mtlr r0
338: ea e1 ff b8 ld r23,-72(r1)
33c: eb 01 ff c0 ld r24,-64(r1)
340: eb 21 ff c8 ld r25,-56(r1)
344: eb 41 ff d0 ld r26,-48(r1)
348: eb 61 ff d8 ld r27,-40(r1)
34c: eb 81 ff e0 ld r28,-32(r1)
350: eb a1 ff e8 ld r29,-24(r1)
354: eb c1 ff f0 ld r30,-16(r1)
358: eb e1 ff f8 ld r31,-8(r1)
}
batch->pte[i] = rpte;
batch->vaddr[i] = vaddr;
batch->index = ++i;
if (i >= PPC64_TLB_BATCH_NR)
__flush_tlb_pending(batch);
35c: 48 00 00 00 b 35c <.hpte_need_flush+0x29c>
}
360: 38 21 00 c0 addi r1,r1,192
364: e8 01 00 10 ld r0,16(r1)
368: ea c1 ff b0 ld r22,-80(r1)
36c: 7c 08 03 a6 mtlr r0
370: ea e1 ff b8 ld r23,-72(r1)
374: eb 01 ff c0 ld r24,-64(r1)
378: eb 21 ff c8 ld r25,-56(r1)
37c: eb 41 ff d0 ld r26,-48(r1)
380: eb 61 ff d8 ld r27,-40(r1)
384: eb 81 ff e0 ld r28,-32(r1)
388: eb a1 ff e8 ld r29,-24(r1)
38c: eb c1 ff f0 ld r30,-16(r1)
390: eb e1 ff f8 ld r31,-8(r1)
394: 4e 80 00 20 blr
0000000000000398 <.__flush_hash_table_range>:
*/
#ifdef CONFIG_HOTPLUG
void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
398: fb 81 ff e0 std r28,-32(r1)
39c: 7c 08 02 a6 mflr r0
3a0: fb c1 ff f0 std r30,-16(r1)
unsigned long flags;
start = _ALIGN_DOWN(start, PAGE_SIZE);
end = _ALIGN_UP(end, PAGE_SIZE);
3a4: 3c a5 00 01 addis r5,r5,1
*/
#ifdef CONFIG_HOTPLUG
void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
3a8: f8 01 00 10 std r0,16(r1)
3ac: 7c 7e 1b 78 mr r30,r3
3b0: fb a1 ff e8 std r29,-24(r1)
unsigned long flags;
start = _ALIGN_DOWN(start, PAGE_SIZE);
end = _ALIGN_UP(end, PAGE_SIZE);
3b4: 38 a5 ff ff addi r5,r5,-1
*/
#ifdef CONFIG_HOTPLUG
void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
3b8: fb e1 ff f8 std r31,-8(r1)
3bc: f8 21 ff 71 stdu r1,-144(r1)
unsigned long flags;
start = _ALIGN_DOWN(start, PAGE_SIZE);
end = _ALIGN_UP(end, PAGE_SIZE);
3c0: 78 bc 03 e4 rldicr r28,r5,0,47
BUG_ON(!mm->pgd);
3c4: e8 03 00 48 ld r0,72(r3)
3c8: 7c 00 00 74 cntlzd r0,r0
3cc: 78 00 d1 82 rldicl r0,r0,58,6
3d0: 0b 00 00 00 tdnei r0,0
void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
unsigned long flags;
start = _ALIGN_DOWN(start, PAGE_SIZE);
3d4: 78 9f 03 e4 rldicr r31,r4,0,47
static inline unsigned long raw_local_irq_disable(void)
{
unsigned long flags, zero;
__asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
3d8: 38 00 00 00 li r0,0
3dc: 8b ad 01 da lbz r29,474(r13)
3e0: 98 0d 01 da stb r0,474(r13)
static inline void arch_enter_lazy_mmu_mode(void)
{
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
batch->active = 1;
3e4: 38 00 00 01 li r0,1
3e8: e9 6d 00 40 ld r11,64(r13)
#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
static inline void arch_enter_lazy_mmu_mode(void)
{
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
3ec: e9 22 00 08 ld r9,8(r2)
batch->active = 1;
3f0: 7c 09 59 2e stwx r0,r9,r11
3f4: 48 00 00 58 b 44c <.__flush_hash_table_range+0xb4>
pte_t *pt = NULL;
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
3f8: e9 3e 00 48 ld r9,72(r30)
3fc: 7c 09 00 2a ldx r0,r9,r0
400: 2f a0 00 00 cmpdi cr7,r0,0
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
404: 78 09 05 a4 rldicr r9,r0,0,54
pte_t *pt = NULL;
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
408: 41 9e 00 40 beq- cr7,448 <.__flush_hash_table_range+0xb0>
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
40c: 7d 2b 48 2a ldx r9,r11,r9
pt = pte_offset_kernel(pm, ea);
410: 7b e0 85 22 rldicl r0,r31,48,52
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
414: 2f a9 00 00 cmpdi cr7,r9,0
pt = pte_offset_kernel(pm, ea);
418: 78 0b 1f 24 rldicr r11,r0,3,60
41c: 79 26 05 a4 rldicr r6,r9,0,54
arch_enter_lazy_mmu_mode();
for (; start < end; start += PAGE_SIZE) {
pte_t *ptep = find_linux_pte(mm->pgd, start);
unsigned long pte;
if (ptep == NULL)
420: 7c a6 5a 15 add. r5,r6,r11
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
424: 41 9e 00 24 beq- cr7,448 <.__flush_hash_table_range+0xb0>
428: 41 c2 00 20 beq- 448 <.__flush_hash_table_range+0xb0>
continue;
pte = pte_val(*ptep);
42c: 7c c6 58 2a ldx r6,r6,r11
if (!(pte & _PAGE_HASHPTE))
430: 54 c0 01 27 rlwinm. r0,r6,0,4,19
434: 41 82 00 14 beq- 448 <.__flush_hash_table_range+0xb0>
continue;
hpte_need_flush(mm, start, ptep, pte, 0);
438: 7f e4 fb 78 mr r4,r31
43c: 7f c3 f3 78 mr r3,r30
440: 38 e0 00 00 li r7,0
444: 48 00 00 01 bl 444 <.__flush_hash_table_range+0xac>
* to being hashed). This is not the most performance oriented
* way to do things but is fine for our needs here.
*/
local_irq_save(flags);
arch_enter_lazy_mmu_mode();
for (; start < end; start += PAGE_SIZE) {
448: 3f ff 00 01 addis r31,r31,1
44c: 7f bf e0 40 cmpld cr7,r31,r28
pte_t *pt = NULL;
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
450: 7b e0 c5 e0 rldicl r0,r31,24,55
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
454: 7b e9 25 22 rldicl r9,r31,36,52
pte_t *pt = NULL;
pg = pgdir + pgd_index(ea);
if (!pgd_none(*pg)) {
pu = pud_offset(pg, ea);
if (!pud_none(*pu)) {
458: 78 00 1f 24 rldicr r0,r0,3,60
pm = pmd_offset(pu, ea);
if (pmd_present(*pm))
45c: 79 2b 1f 24 rldicr r11,r9,3,60
460: 41 9c ff 98 blt+ cr7,3f8 <.__flush_hash_table_range+0x60>
}
static inline void arch_leave_lazy_mmu_mode(void)
{
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
464: eb cd 00 40 ld r30,64(r13)
468: eb e2 00 08 ld r31,8(r2)
46c: 7c 7f f2 14 add r3,r31,r30
if (batch->index)
470: e8 03 00 08 ld r0,8(r3)
474: 2f a0 00 00 cmpdi cr7,r0,0
478: 41 9e 00 08 beq- cr7,480 <.__flush_hash_table_range+0xe8>
__flush_tlb_pending(batch);
47c: 48 00 00 01 bl 47c <.__flush_hash_table_range+0xe4>
if (!(pte & _PAGE_HASHPTE))
continue;
hpte_need_flush(mm, start, ptep, pte, 0);
}
arch_leave_lazy_mmu_mode();
local_irq_restore(flags);
480: 2f bd 00 00 cmpdi cr7,r29,0
batch->active = 0;
484: 38 00 00 00 li r0,0
488: 38 60 00 00 li r3,0
48c: 7c 1f f1 2e stwx r0,r31,r30
490: 41 9e 00 08 beq- cr7,498 <.__flush_hash_table_range+0x100>
494: 7f a3 eb 78 mr r3,r29
498: 48 00 00 01 bl 498 <.__flush_hash_table_range+0x100>
49c: 60 00 00 00 nop
}
4a0: 38 21 00 90 addi r1,r1,144
4a4: e8 01 00 10 ld r0,16(r1)
4a8: eb 81 ff e0 ld r28,-32(r1)
4ac: 7c 08 03 a6 mtlr r0
4b0: eb a1 ff e8 ld r29,-24(r1)
4b4: eb c1 ff f0 ld r30,-16(r1)
4b8: eb e1 ff f8 ld r31,-8(r1)
4bc: 4e 80 00 20 blr
^ permalink raw reply
* Re: [PATCH] Fix oprofile sampling of marked events on POWER7
From: Maynard Johnson @ 2009-06-15 13:40 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Anton Blanchard
In-Reply-To: <49FB2EC5.4040400@us.ibm.com>
Looks like this posting got overlooked, so I'm re-posting the original patch. Ben, can you please review? BTW, Anton reported the problem that this patch fixes.
Thanks.
-Maynard
==============================================================
Description
-----------
Change ppc64 oprofile kernel driver to use the SLOT bits (MMCRA[37:39]only on
older processors where those bits are defined.
Background
----------
The performance monitor unit of the 64-bit POWER processor family has the
ability to collect accurate instruction-level samples when profiling on marked
events (i.e., "PM_MRK_<event-name>"). In processors prior to POWER6, the MMCRA
register contained "slot information" that the oprofile kernel driver used to
adjust the value latched in the SIAR at the time of a PMU interrupt. But as of
POWER6, these slot bits in MMCRA are no longer necessary for oprofile to use,
since the SIAR itself holds the accurate sampled instruction address. With
POWER6, these MMCRA slot bits were zero'ed out by hardware so oprofile's use of
these slot bits was, in effect, a NOP. But with POWER7, these bits are no
longer zero'ed out; however, they serve some other purpose rather than slot
information. Thus, using these bits on POWER7 to adjust the SIAR value results
in samples being attributed to the wrong instructions. The attached patch
changes the oprofile kernel driver to ignore these slot bits on all newer
processors starting with POWER6.
Thanks.
-Maynard
Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>
diff -paur linux/arch/powerpc/oprofile/op_model_power4.c linux-p7-oprofile-patch//arch/powerpc/oprofile/op_model_power4.c
--- linux/arch/powerpc/oprofile/op_model_power4.c 2009-05-01 08:20:21.000000000 -0500
+++ linux-p7-oprofile-patch//arch/powerpc/oprofile/op_model_power4.c 2009-05-01 08:20:05.000000000 -0500
@@ -26,6 +26,7 @@
static unsigned long reset_value[OP_MAX_COUNTER];
static int oprofile_running;
+static int use_slot_nums;
/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
static u32 mmcr0_val;
@@ -61,6 +62,12 @@ static int power4_reg_setup(struct op_co
else
mmcr0_val |= MMCR0_PROBLEM_DISABLE;
+ if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
+ __is_processor(PV_970) || __is_processor(PV_970FX) ||
+ __is_processor(PV_970MP) || __is_processor(PV_970GX) ||
+ __is_processor(PV_POWER5) || __is_processor(PV_POWER5p))
+ use_slot_nums = 1;
+
return 0;
}
@@ -206,7 +213,7 @@ static unsigned long get_pc(struct pt_re
mmcra = mfspr(SPRN_MMCRA);
- if (mmcra & MMCRA_SAMPLE_ENABLE) {
+ if (use_slot_nums && (mmcra & MMCRA_SAMPLE_ENABLE)) {
slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
if (slot > 1)
pc += 4 * (slot - 1);
^ permalink raw reply
* Re: [PATCH] powerpc: Add configurable -Werror for arch/powerpc
From: Timur Tabi @ 2009-06-15 14:54 UTC (permalink / raw)
To: michael; +Cc: linuxppc-dev list
In-Reply-To: <1245052241.7705.78.camel@concordia>
On Mon, Jun 15, 2009 at 2:50 AM, Michael Ellerman<michael@ellerman.id.au> wrote:
> arch/powerpc/platforms/chrp/setup.c:378: error: the frame size of 1040 bytes is larger than 1024 bytes
What's so bad about a frame size larger than 1024?
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* RE: [PATCH] fbdev/xilinxfb: Fix improper casting and tighen up probe path
From: John Linn @ 2009-06-15 15:16 UTC (permalink / raw)
To: Grant Likely, linuxppc-dev, linux-kernel, benh
In-Reply-To: <20090612175634.12827.12207.stgit@localhost.localdomain>
> -----Original Message-----
> From: Grant Likely [mailto:grant.likely@secretlab.ca]
> Sent: Friday, June 12, 2009 11:57 AM
> To: linuxppc-dev@ozlabs.org; linux-kernel@vger.kernel.org;
benh@kernel.crashing.org; John Linn
> Subject: [PATCH] fbdev/xilinxfb: Fix improper casting and tighen up
probe path
> =
> From: Grant Likely <grant.likely@secretlab.ca>
> =
> The xilinxfb driver is improperly casting a physical address to a
> u32, and the probe routine isn't as straight forward as it could be.
> (discovered by gcc spitting out warnings on most recent change to
> xilinxfb driver).
> =
> This patch fixes the cast and simplifies the probe path.
> =
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> =
> John, can you please test and verify this fix is correct?
I will try to test it today.
-- John
> =
> Thanks,
> g.
> =
> drivers/video/xilinxfb.c | 59
++++++++++++++++++----------------------------
> 1 files changed, 23 insertions(+), 36 deletions(-)
> =
> =
> diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
> index 7a868bd..b68b331 100644
> --- a/drivers/video/xilinxfb.c
> +++ b/drivers/video/xilinxfb.c
> @@ -124,7 +124,6 @@ struct xilinxfb_drvdata {
> registers */
> =
> dcr_host_t dcr_host;
> - unsigned int dcr_start;
> unsigned int dcr_len;
> =
> void *fb_virt; /* virt. address of the frame
buffer */
> @@ -325,8 +324,8 @@ static int xilinxfb_assign(struct device *dev,
> drvdata->regs);
> }
> /* Put a banner in the log (for DEBUG) */
> - dev_dbg(dev, "fb: phys=3D%p, virt=3D%p, size=3D%x\n",
> - (void *)drvdata->fb_phys, drvdata->fb_virt, fbsize);
> + dev_dbg(dev, "fb: phys=3D%llx, virt=3D%p, size=3D%x\n",
> + (unsigned long long)drvdata->fb_phys, drvdata->fb_virt,
fbsize);
> =
> return 0; /* success */
> =
> @@ -404,9 +403,7 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> u32 tft_access;
> struct xilinxfb_platform_data pdata;
> struct resource res;
> - int size, rc;
> - int start =3D 0, len =3D 0;
> - dcr_host_t dcr_host;
> + int size, rc, start;
> struct xilinxfb_drvdata *drvdata;
> =
> /* Copy with the default pdata (not a ptr reference!) */
> @@ -414,35 +411,39 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> =
> dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
> =
> + /* Allocate the driver data region */
> + drvdata =3D kzalloc(sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata) {
> + dev_err(&op->dev, "Couldn't allocate device private
record\n");
> + return -ENOMEM;
> + }
> +
> /*
> * To check whether the core is connected directly to DCR or PLB
> * interface and initialize the tft_access accordingly.
> */
> p =3D (u32 *)of_get_property(op->node, "xlnx,dcr-splb-slave-if",
NULL);
> -
> - if (p)
> - tft_access =3D *p;
> - else
> - tft_access =3D 0; /* For backward compatibility */
> + tft_access =3D p ? *p : 0;
> =
> /*
> * Fill the resource structure if its direct PLB interface
> * otherwise fill the dcr_host structure.
> */
> if (tft_access) {
> + drvdata->flags |=3D PLB_ACCESS_FLAG;
> rc =3D of_address_to_resource(op->node, 0, &res);
> if (rc) {
> dev_err(&op->dev, "invalid address\n");
> - return -ENODEV;
> + goto err;
> }
> -
> } else {
> + res.start =3D 0;
> start =3D dcr_resource_start(op->node, 0);
> - len =3D dcr_resource_len(op->node, 0);
> - dcr_host =3D dcr_map(op->node, start, len);
> - if (!DCR_MAP_OK(dcr_host)) {
> - dev_err(&op->dev, "invalid address\n");
> - return -ENODEV;
> + drvdata->dcr_len =3D dcr_resource_len(op->node, 0);
> + drvdata->dcr_host =3D dcr_map(op->node, start,
drvdata->len);
> + if (!DCR_MAP_OK(drvdata->dcr_host)) {
> + dev_err(&op->dev, "invalid DCR address\n");
> + goto err;
> }
> }
> =
> @@ -467,26 +468,12 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> if (of_find_property(op->node, "rotate-display", NULL))
> pdata.rotate_screen =3D 1;
> =
> - /* Allocate the driver data region */
> - drvdata =3D kzalloc(sizeof(*drvdata), GFP_KERNEL);
> - if (!drvdata) {
> - dev_err(&op->dev, "Couldn't allocate device private
record\n");
> - return -ENOMEM;
> - }
> dev_set_drvdata(&op->dev, drvdata);
> + return xilinxfb_assign(&op->dev, drvdata, res.start, &pdata);
> =
> - if (tft_access)
> - drvdata->flags |=3D PLB_ACCESS_FLAG;
> -
> - /* Arguments are passed based on the interface */
> - if (drvdata->flags & PLB_ACCESS_FLAG) {
> - return xilinxfb_assign(&op->dev, drvdata, res.start,
&pdata);
> - } else {
> - drvdata->dcr_start =3D start;
> - drvdata->dcr_len =3D len;
> - drvdata->dcr_host =3D dcr_host;
> - return xilinxfb_assign(&op->dev, drvdata, 0, &pdata);
> - }
> + err:
> + kfree(drvdata);
> + return -ENODEV;
> }
> =
> static int __devexit xilinxfb_of_remove(struct of_device *op)
> =
This email and any attachments are intended for the sole use of the named r=
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^ permalink raw reply
* Re: Chipselect in SPI binding with mpc5200-psc-spi
From: Kári Davíðsson @ 2009-06-15 16:36 UTC (permalink / raw)
Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <fa686aa40902130719k1d16f936o4776cff371db16ae@mail.gmail.com>
Is this true?
Grant Likely wrote:
>
> Yes, this is right. The psc_spi driver automatically registers all
> spi children that it finds in the device tree onto the SPI bus.
> Therefore registering an spi_driver() is the right thing to do.
I am writing an SPI protocol driver and I find that my driver
is never probed.
I tried to add and call to of_register_spi_devices() in the
drivers/spi/mpc52xx_psc_spi.c::mpc52xx_psc_spi_of_probe() function,
without much effect besided that the DTS node is parsed but the driver probe
is not called, actually it complains about a modalias for my node is missing.
This is with kernel 2.6.29.3.
rg
kd
^ permalink raw reply
* RE: [PATCH] fbdev/xilinxfb: Fix improper casting and tighen up probe path
From: John Linn @ 2009-06-15 17:06 UTC (permalink / raw)
To: Grant Likely, linuxppc-dev, linux-kernel, benh
In-Reply-To: <20090612175634.12827.12207.stgit@localhost.localdomain>
> -----Original Message-----
> From: Grant Likely [mailto:grant.likely@secretlab.ca]
> Sent: Friday, June 12, 2009 11:57 AM
> To: linuxppc-dev@ozlabs.org; linux-kernel@vger.kernel.org;
benh@kernel.crashing.org; John Linn
> Subject: [PATCH] fbdev/xilinxfb: Fix improper casting and tighen up
probe path
> =
> From: Grant Likely <grant.likely@secretlab.ca>
> =
> The xilinxfb driver is improperly casting a physical address to a
> u32, and the probe routine isn't as straight forward as it could be.
> (discovered by gcc spitting out warnings on most recent change to
> xilinxfb driver).
> =
> This patch fixes the cast and simplifies the probe path.
> =
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> ---
> =
> John, can you please test and verify this fix is correct?
After a small fix to get it to compile, I did some quick testing with
DCR and without and
it's working fine on the ML507.
-- John
Here's the small change to get it to compile.
diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
index e3d2992..596157c 100644
--- a/drivers/video/xilinxfb.c
+++ b/drivers/video/xilinxfb.c
@@ -441,7 +441,7 @@ xilinxfb_of_probe(struct of_device *op, const struct
of_device_id *match)
res.start =3D 0;
start =3D dcr_resource_start(op->node, 0);
drvdata->dcr_len =3D dcr_resource_len(op->node, 0);
- drvdata->dcr_host =3D dcr_map(op->node, start,
drvdata->len);
+ drvdata->dcr_host =3D dcr_map(op->node, start,
drvdata->dcr_len);
if (!DCR_MAP_OK(drvdata->dcr_host)) {
dev_err(&op->dev, "invalid DCR address\n");
goto err;
--
> =
> Thanks,
> g.
> =
> drivers/video/xilinxfb.c | 59
++++++++++++++++++----------------------------
> 1 files changed, 23 insertions(+), 36 deletions(-)
> =
> =
> diff --git a/drivers/video/xilinxfb.c b/drivers/video/xilinxfb.c
> index 7a868bd..b68b331 100644
> --- a/drivers/video/xilinxfb.c
> +++ b/drivers/video/xilinxfb.c
> @@ -124,7 +124,6 @@ struct xilinxfb_drvdata {
> registers */
> =
> dcr_host_t dcr_host;
> - unsigned int dcr_start;
> unsigned int dcr_len;
> =
> void *fb_virt; /* virt. address of the frame
buffer */
> @@ -325,8 +324,8 @@ static int xilinxfb_assign(struct device *dev,
> drvdata->regs);
> }
> /* Put a banner in the log (for DEBUG) */
> - dev_dbg(dev, "fb: phys=3D%p, virt=3D%p, size=3D%x\n",
> - (void *)drvdata->fb_phys, drvdata->fb_virt, fbsize);
> + dev_dbg(dev, "fb: phys=3D%llx, virt=3D%p, size=3D%x\n",
> + (unsigned long long)drvdata->fb_phys, drvdata->fb_virt,
fbsize);
> =
> return 0; /* success */
> =
> @@ -404,9 +403,7 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> u32 tft_access;
> struct xilinxfb_platform_data pdata;
> struct resource res;
> - int size, rc;
> - int start =3D 0, len =3D 0;
> - dcr_host_t dcr_host;
> + int size, rc, start;
> struct xilinxfb_drvdata *drvdata;
> =
> /* Copy with the default pdata (not a ptr reference!) */
> @@ -414,35 +411,39 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> =
> dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
> =
> + /* Allocate the driver data region */
> + drvdata =3D kzalloc(sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata) {
> + dev_err(&op->dev, "Couldn't allocate device private
record\n");
> + return -ENOMEM;
> + }
> +
> /*
> * To check whether the core is connected directly to DCR or PLB
> * interface and initialize the tft_access accordingly.
> */
> p =3D (u32 *)of_get_property(op->node, "xlnx,dcr-splb-slave-if",
NULL);
> -
> - if (p)
> - tft_access =3D *p;
> - else
> - tft_access =3D 0; /* For backward compatibility */
> + tft_access =3D p ? *p : 0;
> =
> /*
> * Fill the resource structure if its direct PLB interface
> * otherwise fill the dcr_host structure.
> */
> if (tft_access) {
> + drvdata->flags |=3D PLB_ACCESS_FLAG;
> rc =3D of_address_to_resource(op->node, 0, &res);
> if (rc) {
> dev_err(&op->dev, "invalid address\n");
> - return -ENODEV;
> + goto err;
> }
> -
> } else {
> + res.start =3D 0;
> start =3D dcr_resource_start(op->node, 0);
> - len =3D dcr_resource_len(op->node, 0);
> - dcr_host =3D dcr_map(op->node, start, len);
> - if (!DCR_MAP_OK(dcr_host)) {
> - dev_err(&op->dev, "invalid address\n");
> - return -ENODEV;
> + drvdata->dcr_len =3D dcr_resource_len(op->node, 0);
> + drvdata->dcr_host =3D dcr_map(op->node, start,
drvdata->len);
> + if (!DCR_MAP_OK(drvdata->dcr_host)) {
> + dev_err(&op->dev, "invalid DCR address\n");
> + goto err;
> }
> }
> =
> @@ -467,26 +468,12 @@ xilinxfb_of_probe(struct of_device *op, const
struct of_device_id *match)
> if (of_find_property(op->node, "rotate-display", NULL))
> pdata.rotate_screen =3D 1;
> =
> - /* Allocate the driver data region */
> - drvdata =3D kzalloc(sizeof(*drvdata), GFP_KERNEL);
> - if (!drvdata) {
> - dev_err(&op->dev, "Couldn't allocate device private
record\n");
> - return -ENOMEM;
> - }
> dev_set_drvdata(&op->dev, drvdata);
> + return xilinxfb_assign(&op->dev, drvdata, res.start, &pdata);
> =
> - if (tft_access)
> - drvdata->flags |=3D PLB_ACCESS_FLAG;
> -
> - /* Arguments are passed based on the interface */
> - if (drvdata->flags & PLB_ACCESS_FLAG) {
> - return xilinxfb_assign(&op->dev, drvdata, res.start,
&pdata);
> - } else {
> - drvdata->dcr_start =3D start;
> - drvdata->dcr_len =3D len;
> - drvdata->dcr_host =3D dcr_host;
> - return xilinxfb_assign(&op->dev, drvdata, 0, &pdata);
> - }
> + err:
> + kfree(drvdata);
> + return -ENODEV;
> }
> =
> static int __devexit xilinxfb_of_remove(struct of_device *op)
> =
This email and any attachments are intended for the sole use of the named r=
ecipient(s) and contain(s) confidential information that may be proprietary=
, privileged or copyrighted under applicable law. If you are not the intend=
ed recipient, do not read, copy, or forward this email message or any attac=
hments. Delete this email message and any attachments immediately.
^ permalink raw reply related
* Re: Chipselect in SPI binding with mpc5200-psc-spi
From: Grant Likely @ 2009-06-15 17:31 UTC (permalink / raw)
To: Kári Davíðsson; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <4A3678A3.1050802@marel.com>
On Mon, Jun 15, 2009 at 10:36 AM, K=E1ri
Dav=ED=F0sson<kari.davidsson@marel.com> wrote:
> Is this true?
>
> Grant Likely wrote:
>>
>> Yes, this is right. =A0The psc_spi driver automatically registers all
>> spi children that it finds in the device tree onto the SPI bus.
>> Therefore registering an spi_driver() is the right thing to do.
>
> I am writing an SPI protocol driver and I find that my driver
> is never probed.
>
> I tried to add and call to of_register_spi_devices() in the
> drivers/spi/mpc52xx_psc_spi.c::mpc52xx_psc_spi_of_probe() function,
> without much effect besided that the DTS node is parsed but the driver pr=
obe
> is not called, actually it complains about a modalias for my node is
> missing.
What do you see when you look in /sys/bus/spi/devices? You should see
a directory for your device. What do you see in /sys/bus/spi/drivers?
In here you should see your driver. If they are both there, then you
just have a problem matching your driver name to the device name.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* [PATCH 1/3] AMCC Crypto4xx Device Driver v7
From: Shasi Pulijala @ 2009-06-15 17:25 UTC (permalink / raw)
To: herbert; +Cc: linuxppc-dev, linux-crypto
Hi,
I am re-sending this patch as a patch series of 3, I am assuming the =
earlier one did not go through the mailing lists
because it was over the size limit.
-Shasi
From: Shasi Pulijala <spulijala@amcc.com>
This is second release version for the PPC4XX Security driver that
adds aead type support and other algs to the security driver.
Signed-off-by: Shasi Pulijala <spulijala@amcc.com>
Acked-by: Loc Ho <lho@amcc.com>
---
drivers/crypto/amcc/crypto4xx_core.c | 816 =
++++++++++++++++++++++++++++++++--
drivers/crypto/amcc/crypto4xx_core.h | 92 ++++
drivers/crypto/amcc/crypto4xx_sa.c | 114 +++++
drivers/crypto/amcc/crypto4xx_sa.h | 337 ++++++++++++++-
4 files changed, 1323 insertions(+), 36 deletions(-)
diff --git a/drivers/crypto/amcc/crypto4xx_core.c =
b/drivers/crypto/amcc/crypto4xx_core.c
index 4c0dfb2..0fef1f2 100644
--- a/drivers/crypto/amcc/crypto4xx_core.c
+++ b/drivers/crypto/amcc/crypto4xx_core.c
@@ -28,13 +28,18 @@
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/highmem.h>
#include <asm/dcr.h>
#include <asm/dcr-regs.h>
#include <asm/cacheflush.h>
#include <crypto/internal/hash.h>
#include <crypto/algapi.h>
#include <crypto/aes.h>
+#include <crypto/des.h>
#include <crypto/sha.h>
+#include <crypto/ctr.h>
#include "crypto4xx_reg_def.h"
#include "crypto4xx_core.h"
#include "crypto4xx_sa.h"
@@ -153,6 +158,8 @@ void crypto4xx_free_sa(struct crypto4xx_ctx *ctx)
=20
ctx->sa_in_dma_addr =3D 0;
ctx->sa_out_dma_addr =3D 0;
+ ctx->sa_in =3D NULL;
+ ctx->sa_out =3D NULL;
ctx->sa_len =3D 0;
}
=20
@@ -178,6 +185,31 @@ void crypto4xx_free_state_record(struct =
crypto4xx_ctx *ctx)
ctx->state_record_dma_addr =3D 0;
}
=20
+u32 crypto4xx_alloc_arc4_state_record(struct crypto4xx_ctx *ctx)
+{
+ ctx->arc4_state_record =3D =
dma_alloc_coherent(ctx->dev->core_dev->device,
+ sizeof(struct arc4_sr),
+ &ctx->arc4_state_record_dma_addr,
+ GFP_ATOMIC);
+ if (!ctx->arc4_state_record_dma_addr)
+ return -ENOMEM;
+
+ memset(ctx->arc4_state_record, 0, sizeof(struct arc4_sr));
+
+ return 0;
+}
+
+void crypto4xx_free_arc4_state_record(struct crypto4xx_ctx *ctx)
+{
+ if (ctx->arc4_state_record !=3D NULL) {
+ dma_free_coherent(ctx->dev->core_dev->device,
+ sizeof(struct arc4_sr),
+ ctx->arc4_state_record,
+ ctx->arc4_state_record_dma_addr);
+ }
+ ctx->arc4_state_record_dma_addr =3D 0;
+}
+
/**
* alloc memory for the gather ring
* no need to alloc buf for the ring
@@ -528,7 +560,7 @@ static u32 crypto4xx_fill_one_page(struct =
crypto4xx_device *dev,
(*idx)++;
=20
return 0;
- }
+ }
}
=20
static void crypto4xx_copy_pkt_to_dst(struct crypto4xx_device *dev,
@@ -591,9 +623,25 @@ static u32 crypto4xx_copy_digest_to_dst(struct =
pd_uinfo *pd_uinfo,
struct sa_state_record *state_record =3D
(struct sa_state_record *) pd_uinfo->sr_va;
=20
- if (sa->sa_command_0.bf.hash_alg =3D=3D SA_HASH_ALG_SHA1) {
- memcpy((void *) pd_uinfo->dest_va, state_record->save_digest,
- SA_HASH_ALG_SHA1_DIGEST_SIZE);
+ switch (sa->sa_command_0.bf.hash_alg) {
+ case SA_HASH_ALG_KASUMI_f9:
+ crypto4xx_memcpy_le((void *)pd_uinfo->dest_va,
+ (u8 *)state_record->save_digest, 8);
+ break;
+ case SA_HASH_ALG_AES_XCBC_MAC_128:
+ crypto4xx_memcpy_le((void *)pd_uinfo->dest_va,
+ (u8 *) state_record->save_digest, 16);
+ break;
+ case SA_HASH_ALG_MD5:
+ crypto4xx_memcpy_le((void *)pd_uinfo->dest_va,
+ (u8 *) state_record->save_digest,
+ SA_HASH_ALG_MD5_DIGEST_SIZE);
+ break;
+ default:
+ memcpy((void *)pd_uinfo->dest_va,
+ state_record->save_digest,
+ crypto4xx_sa_hash_tbl[1][sa->sa_command_0.bf.hash_alg]);
+ break;
}
=20
return 0;
@@ -618,6 +666,57 @@ static void crypto4xx_ret_sg_desc(struct =
crypto4xx_device *dev,
}
}
=20
+void crypto4xx_append_icv_to_end(struct crypto4xx_device *dev,
+ struct scatterlist *dst,
+ struct sa_state_record *sr,
+ u32 offset,
+ u32 len)
+{
+ struct scatterlist *sg;
+ int i =3D 0;
+ u32 cp_len;
+ dma_addr_t addr;
+
+ sg =3D &dst[i];
+ while (len) {
+ while (sg->length < offset) {
+ offset -=3D sg->length;
+ i++;
+ sg =3D &sg[i];
+ }
+ /* at here, icv could be in this sg,
+ * or icv could be in the next sg
+ */
+ if (sg->length > offset) {
+ /* icv should be in middle of this sg */
+ addr =3D dma_map_page(dev->core_dev->device, sg_page(sg),
+ sg->offset,
+ sg->length, DMA_TO_DEVICE);
+ cp_len =3D (sg->length-offset >=3D len) ? len :
+ sg->length-offset;
+ len -=3D cp_len;
+ crypto4xx_memcpy_le((u32 *)(phys_to_virt(addr)
+ + offset),
+ (u8 *)sr->save_digest, cp_len);
+ } else {
+ /* start from begin of next sg*/
+ i++;
+ sg =3D &sg[i];
+ offset =3D 0;
+ addr =3D dma_map_page(dev->core_dev->device, sg_page(sg),
+ sg->offset,
+ sg->length, DMA_FROM_DEVICE);
+ cp_len =3D (sg->length >=3D len) ? len : sg->length;
+ len -=3D cp_len;
+ crypto4xx_memcpy_le((u32 *) (phys_to_virt(addr)
+ + offset),
+ (u8 *) sr->save_digest, cp_len);
+ }
+ i++;
+ sg =3D &sg[i];
+ }
+}
+
static u32 crypto4xx_ablkcipher_done(struct crypto4xx_device *dev,
struct pd_uinfo *pd_uinfo,
struct ce_pd *pd)
@@ -664,18 +763,67 @@ static u32 crypto4xx_ahash_done(struct =
crypto4xx_device *dev,
return 0;
}
=20
-static u32 crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
+static u32 crypto4xx_aead_done(struct crypto4xx_device *dev,
+ struct pd_uinfo *pd_uinfo,
+ struct ce_pd *pd)
+{
+ struct aead_request *aead_req;
+ struct crypto4xx_ctx *ctx;
+ struct scatterlist *dst;
+ dma_addr_t addr;
+ struct crypto_aead *aead;
+
+ aead_req =3D container_of(pd_uinfo->async_req,
+ struct aead_request, base);
+ aead =3D crypto_aead_reqtfm(aead_req);
+ ctx =3D crypto_tfm_ctx(aead_req->base.tfm);
+
+ if (pd_uinfo->using_sd) {
+ crypto4xx_copy_pkt_to_dst(dev, pd, pd_uinfo,
+ pd->pd_ctl_len.bf.pkt_len,
+ aead_req->dst);
+ } else {
+ dst =3D pd_uinfo->dest_va;
+ addr =3D dma_map_page(dev->core_dev->device, sg_page(dst),
+ dst->offset,
+ dst->length, DMA_FROM_DEVICE);
+ }
+
+ if (ctx->append_icv !=3D 0) {
+ dst =3D pd_uinfo->dest_va;
+ crypto4xx_append_icv_to_end(dev, dst,
+ (struct sa_state_record *)
+ pd_uinfo->sr_va,
+ aead_req->cryptlen,
+ crypto_aead_authsize(aead));
+ }
+ crypto4xx_ret_sg_desc(dev, pd_uinfo);
+ /* call user provided callback function x */
+ if (aead_req->base.complete !=3D NULL)
+ aead_req->base.complete(&aead_req->base, 0);
+
+ return 0;
+}
+
+u32 crypto4xx_pd_done(struct crypto4xx_device *dev, u32 idx)
{
struct ce_pd *pd;
struct pd_uinfo *pd_uinfo;
=20
pd =3D dev->pdr + sizeof(struct ce_pd)*idx;
pd_uinfo =3D dev->pdr_uinfo + sizeof(struct pd_uinfo)*idx;
+
if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) =3D=3D
+ CRYPTO_ALG_TYPE_AEAD)
+ return crypto4xx_aead_done(dev, pd_uinfo, pd);
+ else if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) =3D=3D
CRYPTO_ALG_TYPE_ABLKCIPHER)
return crypto4xx_ablkcipher_done(dev, pd_uinfo, pd);
- else
+ else if (crypto_tfm_alg_type(pd_uinfo->async_req->tfm) =3D=3D
+ CRYPTO_ALG_TYPE_AHASH)
return crypto4xx_ahash_done(dev, pd_uinfo);
+
+ return 0;
}
=20
/**
@@ -777,12 +925,15 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
struct scatterlist *src,
struct scatterlist *dst,
unsigned int datalen,
+ struct scatterlist *assoc,
+ u32 aad_len,
void *iv, u32 iv_len)
{
struct crypto4xx_device *dev =3D ctx->dev;
dma_addr_t addr, pd_dma, sd_dma, gd_dma;
struct dynamic_sa_ctl *sa;
struct scatterlist *sg;
+ struct scatterlist *aad;
struct ce_gd *gd;
struct ce_pd *pd;
u32 num_gd, num_sd;
@@ -792,13 +943,18 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
unsigned long flags;
struct pd_uinfo *pd_uinfo =3D NULL;
unsigned int nbytes =3D datalen, idx;
- unsigned int ivlen =3D 0;
u32 gd_idx =3D 0;
+ unsigned int aadlen =3D 0;
=20
/* figure how many gd is needed */
- num_gd =3D get_sg_count(src, datalen);
- if (num_gd =3D=3D 1)
- num_gd =3D 0;
+ if (aad_len) {
+ num_gd =3D get_sg_count(assoc, aad_len) +
+ get_sg_count(src, datalen);
+ } else {
+ num_gd =3D get_sg_count(src, datalen);
+ if (num_gd =3D=3D 1)
+ num_gd =3D 0;
+ }
=20
/* figure how many sd is needed */
if (sg_is_last(dst) || ctx->is_hash) {
@@ -855,7 +1011,6 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
pd_uinfo->num_sd =3D num_sd;
=20
if (iv_len || ctx->is_hash) {
- ivlen =3D iv_len;
pd->sa =3D pd_uinfo->sa_pa;
sa =3D (struct dynamic_sa_ctl *) pd_uinfo->sa_va;
if (ctx->direction =3D=3D DIR_INBOUND)
@@ -866,8 +1021,26 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
memcpy((void *) sa + ctx->offset_to_sr_ptr,
&pd_uinfo->sr_pa, 4);
=20
- if (iv_len)
- crypto4xx_memcpy_le(pd_uinfo->sr_va, iv, iv_len);
+ if (iv_len) {
+ if (ctx->ctr_aes) {
+ /* First the nonce */
+ memcpy(pd_uinfo->sr_va, ctx->state_record,
+ CTR_RFC3686_NONCE_SIZE);
+ /* Copy the IV that is passed through
+ * each operation
+ */
+ crypto4xx_memcpy_le(pd_uinfo->sr_va +
+ CTR_RFC3686_NONCE_SIZE, iv, iv_len);
+ } else
+ crypto4xx_memcpy_le(pd_uinfo->sr_va,
+ iv, iv_len);
+ }
+ if (ctx->is_gcm || ctx->ctr_aes) {
+ u32 seq =3D 1;
+ /*For GCM and CTR(AES) algs adding the counter value*/
+ crypto4xx_memcpy_le(pd_uinfo->sr_va + 12,
+ (void *)&seq, 4);
+ }
} else {
if (ctx->direction =3D=3D DIR_INBOUND) {
pd->sa =3D ctx->sa_in_dma_addr;
@@ -888,6 +1061,35 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
/* enable gather */
sa->sa_command_0.bf.gather =3D 1;
idx =3D 0;
+ if (aad_len) {
+ aadlen =3D aad_len;
+ aad =3D assoc;
+ /* walk the sg, and setup gather array for aad*/
+ while (aadlen) {
+ sg =3D &aad[idx];
+ addr =3D dma_map_page(dev->core_dev->device,
+ sg_page(sg), sg->offset,
+ sg->length, DMA_TO_DEVICE);
+
+ gd->ptr =3D addr;
+ gd->ctl_len.len =3D sg->length;
+ gd->ctl_len.done =3D 0;
+ gd->ctl_len.ready =3D 1;
+
+ if (sg->length >=3D aadlen)
+ break;
+
+ aadlen -=3D sg->length;
+
+ gd_idx =3D get_next_gd(gd_idx);
+ gd =3D crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
+ idx++;
+ }
+ /* prepare gd for src */
+ gd_idx =3D get_next_gd(gd_idx);
+ gd =3D crypto4xx_get_gdp(dev, &gd_dma, gd_idx);
+ }
+ idx =3D 0;
src =3D &src[0];
/* walk the sg, and setup gather array */
while (nbytes) {
@@ -972,9 +1174,10 @@ u32 crypto4xx_build_pd(struct crypto_async_request =
*req,
}
}
=20
- sa->sa_command_1.bf.hash_crypto_offset =3D 0;
+ sa->sa_command_1.bf.hash_crypto_offset =3D (aad_len >> 2);
pd->pd_ctl.w =3D ctx->pd_ctl;
- pd->pd_ctl_len.w =3D 0x00400000 | (ctx->bypass << 24) | datalen;
+ pd->pd_ctl_len.w =3D 0x00400000 | (ctx->bypass << 24) |
+ (datalen + aad_len);
pd_uinfo->state =3D PD_ENTRY_INUSE;
wmb();
/* write any value to push engine to read a pd */
@@ -997,11 +1200,15 @@ static int crypto4xx_alg_init(struct crypto_tfm =
*tfm)
ctx->sa_in_dma_addr =3D 0;
ctx->sa_out_dma_addr =3D 0;
ctx->sa_len =3D 0;
+ ctx->is_gcm =3D 0;
+ ctx->append_icv =3D 0;
=20
if (alg->cra_type =3D=3D &crypto_ablkcipher_type)
tfm->crt_ablkcipher.reqsize =3D sizeof(struct crypto4xx_ctx);
else if (alg->cra_type =3D=3D &crypto_ahash_type)
tfm->crt_ahash.reqsize =3D sizeof(struct crypto4xx_ctx);
+ else if (alg->cra_type =3D=3D &crypto_aead_type)
+ tfm->crt_aead.reqsize =3D sizeof(struct crypto4xx_ctx);
=20
return 0;
}
@@ -1105,6 +1312,88 @@ static irqreturn_t =
crypto4xx_ce_interrupt_handler(int irq, void *data)
* Supported Crypto Algorithms
*/
struct crypto_alg crypto4xx_alg[] =3D {
+ /* Crypto DES ECB, CBC, modes */
+
+ {.cra_name =3D "cbc(des)",
+ .cra_driver_name =3D "ppc4xx-cbc-des",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D DES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D DES_KEY_SIZE,
+ .max_keysize =3D DES_KEY_SIZE,
+ .ivsize =3D DES_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_3des_cbc,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {.cra_name =3D "ecb(des)",
+ .cra_driver_name =3D "ppc4xx-ecb-des",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D DES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D DES_KEY_SIZE,
+ .max_keysize =3D DES_KEY_SIZE,
+ .setkey =3D crypto4xx_setkey_3des_ecb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+
+ /* Crypto 3DES ECB, CBC, CFB, and OFB modes */
+ {.cra_name =3D "cbc(des3_ede)",
+ .cra_driver_name =3D "ppc4xx-cbc-3des",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D DES3_EDE_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D DES3_EDE_KEY_SIZE,
+ .max_keysize =3D DES3_EDE_KEY_SIZE,
+ .ivsize =3D DES3_EDE_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_3des_cbc,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {.cra_name =3D "ecb(des3_ede)",
+ .cra_driver_name =3D "ppc4xx-ecb-3des",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D DES3_EDE_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D DES3_EDE_KEY_SIZE,
+ .max_keysize =3D DES3_EDE_KEY_SIZE,
+ .setkey =3D crypto4xx_setkey_3des_ecb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
/* Crypto AES modes */
{
.cra_name =3D "cbc(aes)",
@@ -1127,25 +1416,495 @@ struct crypto_alg crypto4xx_alg[] =3D {
}
}
},
- /* Hash SHA1 */
- {
- .cra_name =3D "sha1",
- .cra_driver_name =3D "sha1-ppc4xx",
- .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
- .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
- .cra_blocksize =3D SHA1_BLOCK_SIZE,
- .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
- .cra_alignmask =3D 0,
- .cra_type =3D &crypto_ahash_type,
- .cra_init =3D crypto4xx_sha1_alg_init,
- .cra_module =3D THIS_MODULE,
- .cra_u =3D {
+ {.cra_name =3D "ofb(aes)",
+ .cra_driver_name =3D "ppc4xx-ofb-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D AES_MIN_KEY_SIZE,
+ .max_keysize =3D AES_MAX_KEY_SIZE,
+ .ivsize =3D AES_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_aes_ofb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {.cra_name =3D "cfb(aes)",
+ .cra_driver_name =3D "ppc4xx-cfb-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D AES_MIN_KEY_SIZE,
+ .max_keysize =3D AES_MAX_KEY_SIZE,
+ .ivsize =3D AES_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_aes_cfb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ /* Crypto AES ECB, CBC, CTR, GCM, CCM, and GMAC modes */
+ {.cra_name =3D "ecb(aes)",
+ .cra_driver_name =3D "ppc4xx-ecb-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D AES_MIN_KEY_SIZE,
+ .max_keysize =3D AES_MAX_KEY_SIZE,
+ .setkey =3D crypto4xx_setkey_aes_ecb,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {.cra_name =3D "rfc3686(ctr(aes))",
+ .cra_driver_name =3D "ppc4xx-ctr-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D CTR_RFC3686_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D AES_MIN_KEY_SIZE,
+ .max_keysize =3D AES_MAX_KEY_SIZE,
+ .ivsize =3D CTR_RFC3686_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_aes_ctr,
+ .encrypt =3D crypto4xx_encrypt_ctr,
+ .decrypt =3D crypto4xx_decrypt_ctr,
+ }
+ }
+ },
+ /* AEAD Algorithms */
+ {.cra_name =3D "gcm(aes)",
+ .cra_driver_name =3D "ppc4xx-gcm-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_aead_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .aead =3D {
+ .maxauthsize =3D 16,
+ .ivsize =3D 12,
+ .setkey =3D crypto4xx_setkey_aes_gcm,
+ .setauthsize =3D crypto4xx_setauthsize_aes,
+ .encrypt =3D crypto4xx_encrypt_aes_gcm,
+ .decrypt =3D crypto4xx_decrypt_aes_gcm,
+ .givencrypt =3D crypto4xx_givencrypt_aes_gcm,
+ .givdecrypt =3D crypto4xx_givdecrypt_aes_gcm,
+ }
+ }
+ },
+ {.cra_name =3D "ccm(aes)",
+ .cra_driver_name =3D "ppc4xx-ccm-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_aead_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .aead =3D {
+ .ivsize =3D AES_BLOCK_SIZE,
+ .maxauthsize =3D 16,
+ .setkey =3D crypto4xx_setkey_aes_ccm,
+ .setauthsize =3D crypto4xx_setauthsize_aes,
+ .encrypt =3D crypto4xx_encrypt_aes_ccm,
+ .decrypt =3D crypto4xx_decrypt_aes_ccm,
+ .givencrypt =3D crypto4xx_givencrypt_aes_ccm,
+ .givdecrypt =3D crypto4xx_givdecrypt_aes_ccm,
+ }
+ }
+ },
+ /* Hash MD5 */
+ {.cra_name =3D "md5",
+ .cra_driver_name =3D "ppc4xx-md5",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D 64,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_md5_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SA_HASH_ALG_MD5_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ /* Hash MD5-HMAC */
+ {.cra_name =3D "hmac(md5)",
+ .cra_driver_name =3D "ppc4xx-hmac-md5",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D 64,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SA_HASH_ALG_MD5_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_md5_hmac_setkey,
+ }
+ }
+ },
+ /* Hash SHA1, SHA2 and HMAC */
+ {.cra_name =3D "sha1",
+ .cra_driver_name =3D "ppc4xx-sha1",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA1_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha1_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA1_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha1)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha1",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA1_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
.ahash =3D {
.digestsize =3D SHA1_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha1_hmac_setkey,
+ }
+ }
+ },
+
+ {.cra_name =3D "sha224",
+ .cra_driver_name =3D "ppc4xx-sha224",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA224_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha2_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA224_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha224)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha224",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA224_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA224_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha2_hmac_setkey,
+ }
+ }
+ },
+ {.cra_name =3D "sha256",
+ .cra_driver_name =3D "ppc4xx-sha256",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA256_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha2_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA256_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha256)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha256",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA256_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA256_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha2_hmac_setkey,
+ }
+ }
+ },
+ {.cra_name =3D "sha384",
+ .cra_driver_name =3D "ppc4xx-sha384",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA384_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha2_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA384_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha384)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha384",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA384_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA384_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha2_hmac_setkey,
+ }
+ }
+ },
+ {.cra_name =3D "sha512",
+ .cra_driver_name =3D "ppc4xx-sha512",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA512_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_init =3D crypto4xx_sha2_alg_init,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA512_DIGEST_SIZE,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ }
+ }
+ },
+ {.cra_name =3D "hmac(sha512)",
+ .cra_driver_name =3D "ppc4xx-hmac-sha512",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D SHA512_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D SHA512_DIGEST_SIZE,
.init =3D crypto4xx_hash_init,
.update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_sha2_hmac_setkey,
+ }
+ }
+ },
+ /* Hash XCBC, GHASH, and Kasumi F9 */
+ {.cra_name =3D "xcbc(aes)",
+ .cra_driver_name =3D "ppc4xx-xcbc-aes",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D AES_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D 16,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
.final =3D crypto4xx_hash_final,
.digest =3D crypto4xx_hash_digest,
+ .setkey =3D crypto4xx_xcbc_setkey,
+ }
+ }
+ },
+ /* Crypto Kasumi and Kasumi F8 */
+ {.cra_name =3D "kasumi",
+ .cra_driver_name =3D "ppc4xx-kasumi",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D KASUMI_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D KASUMI_KEY_SIZE,
+ .max_keysize =3D KASUMI_KEY_SIZE,
+ .ivsize =3D KASUMI_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_kasumi_p,
+ .encrypt =3D crypto4xx_encrypt,
+ .decrypt =3D crypto4xx_decrypt,
+ }
+ }
+ },
+ {
+ .cra_name =3D "f8(kasumi)",
+ .cra_driver_name =3D "ppc4xx-f8-kasumi",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D KASUMI_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D KASUMI_KEY_SIZE,
+ .max_keysize =3D KASUMI_KEY_SIZE,
+ .ivsize =3D KASUMI_BLOCK_SIZE,
+ .setkey =3D crypto4xx_setkey_kasumi_f8,
+ .encrypt =3D crypto4xx_encrypt_kasumi_f8,
+ .decrypt =3D crypto4xx_decrypt_kasumi_f8,
+ }
+ }
+ },
+ {.cra_name =3D "f9(kasumi)",
+ .cra_driver_name =3D "ppc4xx-f9-kasumi",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D KASUMI_BLOCK_SIZE,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ahash_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ahash =3D {
+ .digestsize =3D 8,
+ .init =3D crypto4xx_hash_init,
+ .update =3D crypto4xx_hash_update,
+ .final =3D crypto4xx_hash_final,
+ .digest =3D crypto4xx_kasumi_f9_digest,
+ .setkey =3D crypto4xx_kasumi_f9_setkey,
+ }
+ }
+ },
+ /* Crypto ARC4 - stateless */
+ {.cra_name =3D "ecb(arc4)",
+ .cra_driver_name =3D "ppc4xx-arc4",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D 1,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D 1,
+ .max_keysize =3D 16,
+ .setkey =3D crypto4xx_setkey_arc4,
+ .encrypt =3D crypto4xx_arc4_encrypt,
+ .decrypt =3D crypto4xx_arc4_decrypt,
+ }
+ }
+ },
+ /* Crypto ARC4 - statefull */
+ {.cra_name =3D "cbc(arc4)",
+ .cra_driver_name =3D "ppc4xx-arc4",
+ .cra_priority =3D CRYPTO4XX_CRYPTO_PRIORITY,
+ .cra_flags =3D CRYPTO_ALG_TYPE_BLKCIPHER | CRYPTO_ALG_ASYNC,
+ .cra_blocksize =3D 1,
+ .cra_ctxsize =3D sizeof(struct crypto4xx_ctx),
+ .cra_alignmask =3D 0,
+ .cra_type =3D &crypto_ablkcipher_type,
+ .cra_module =3D THIS_MODULE,
+ .cra_u =3D {
+ .ablkcipher =3D {
+ .min_keysize =3D 1,
+ .max_keysize =3D 16,
+ .setkey =3D crypto4xx_setkey_arc4,
+ .encrypt =3D crypto4xx_arc4_encrypt,
+ .decrypt =3D crypto4xx_arc4_decrypt,
}
}
},
@@ -1275,7 +2034,6 @@ static int __exit crypto4xx_remove(struct =
of_device *ofdev)
crypto4xx_unregister_alg(core_dev->dev);
/* Free all allocated memory */
crypto4xx_stop_all(core_dev);
-
return 0;
}
=20
diff --git a/drivers/crypto/amcc/crypto4xx_core.h =
b/drivers/crypto/amcc/crypto4xx_core.h
index 1ef1034..f3d04b6 100644
--- a/drivers/crypto/amcc/crypto4xx_core.h
+++ b/drivers/crypto/amcc/crypto4xx_core.h
@@ -116,6 +116,8 @@ struct crypto4xx_ctx {
dma_addr_t sa_in_dma_addr;
void *sa_out;
dma_addr_t sa_out_dma_addr;
+ void *arc4_state_record;
+ dma_addr_t arc4_state_record_dma_addr;
void *state_record;
dma_addr_t state_record_dma_addr;
u32 sa_len;
@@ -125,7 +127,11 @@ struct crypto4xx_ctx {
u32 save_iv;
u32 pd_ctl_len;
u32 pd_ctl;
+ u32 append_icv;
+ u32 is_gcm;
+ u32 ctr_aes;
u32 bypass;
+ u32 init_arc4;
u32 is_hash;
u32 hash_final;
};
@@ -154,9 +160,12 @@ extern u32 crypto4xx_alloc_sa_rctx(struct =
crypto4xx_ctx *ctx,
extern void crypto4xx_free_sa_rctx(struct crypto4xx_ctx *rctx);
extern void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx);
extern u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx);
+extern u32 crypto4xx_alloc_arc4_state_record(struct crypto4xx_ctx =
*ctx);
+extern void crypto4xx_free_arc4_state_record(struct crypto4xx_ctx =
*ctx);
extern u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx =
*ctx);
extern u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx);
extern u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx);
+u32 get_dynamic_sa_offset_arc4_state_ptr(struct crypto4xx_ctx *ctx);
extern void crypto4xx_memcpy_le(unsigned int *dst,
const unsigned char *buf, int len);
extern u32 crypto4xx_build_pd(struct crypto_async_request *req,
@@ -164,9 +173,15 @@ extern u32 crypto4xx_build_pd(struct =
crypto_async_request *req,
struct scatterlist *src,
struct scatterlist *dst,
unsigned int datalen,
+ struct scatterlist *assoc,
+ u32 aad_len,
void *iv, u32 iv_len);
extern int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
const u8 *key, unsigned int keylen);
+extern int crypto4xx_setkey_3des_cbc(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+extern int crypto4xx_setkey_3des_ecb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
extern int crypto4xx_encrypt(struct ablkcipher_request *req);
extern int crypto4xx_decrypt(struct ablkcipher_request *req);
extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
@@ -174,4 +189,81 @@ extern int crypto4xx_hash_digest(struct =
ahash_request *req);
extern int crypto4xx_hash_final(struct ahash_request *req);
extern int crypto4xx_hash_update(struct ahash_request *req);
extern int crypto4xx_hash_init(struct ahash_request *req);
+extern int crypto4xx_md5_alg_init(struct crypto_tfm *tfm);
+extern int crypto4xx_hash_hmac_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen,
+ unsigned int sa_len,
+ unsigned char ha,
+ unsigned char hm,
+ unsigned int max_keylen);
+extern int crypto4xx_md5_hmac_setkey(struct crypto_ahash *hash, const =
u8 *key,
+ unsigned int keylen);
+extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm);
+extern int crypto4xx_sha2_alg_init(struct crypto_tfm *tfm);
+extern int crypto4xx_sha2_hmac_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen);
+extern int crypto4xx_sha1_hmac_setkey(struct crypto_ahash *hash, const =
u8 *key,
+ unsigned int keylen);
+extern u32 get_dynamic_sa_offset_inner_digest(struct crypto4xx_ctx =
*ctx);
+extern u32 get_dynamic_sa_offset_outer_digest(struct crypto4xx_ctx =
*ctx);
+extern int crypto4xx_pre_compute_hmac(struct crypto4xx_ctx *ctx,
+ void *key,
+ unsigned int keylen,
+ unsigned int bs,
+ unsigned char ha,
+ unsigned char digs);
+int crypto4xx_setkey_aes_ecb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_ofb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_cfb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_ctr(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_gcm(struct crypto_aead *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_setkey_aes_ccm(struct crypto_aead *cipher,
+ const u8 *key, unsigned int keylen);
+
+int crypto4xx_encrypt_aes_gcm(struct aead_request *req);
+int crypto4xx_decrypt_aes_gcm(struct aead_request *req);
+int crypto4xx_encrypt_aes_ccm(struct aead_request *req);
+int crypto4xx_decrypt_aes_ccm(struct aead_request *req);
+int crypto4xx_encrypt_ctr(struct ablkcipher_request *req);
+int crypto4xx_decrypt_ctr(struct ablkcipher_request *req);
+int crypto4xx_setauthsize_aes(struct crypto_aead *ciper,
+ unsigned int authsize);
+int crypto4xx_givencrypt_aes_ccm(struct aead_givcrypt_request *req);
+int crypto4xx_givencrypt_aes_gcm(struct aead_givcrypt_request *req);
+int crypto4xx_givdecrypt_aes_ccm(struct aead_givcrypt_request *req);
+int crypto4xx_givdecrypt_aes_gcm(struct aead_givcrypt_request *req);
+int crypto4xx_setkey_kasumi_f8(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen);
+
+int crypto4xx_encrypt_kasumi_f8(struct ablkcipher_request *req);
+int crypto4xx_decrypt_kasumi_f8(struct ablkcipher_request *req);
+int crypto4xx_setkey_kasumi_p(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen);
+int crypto4xx_kasumi_f9_digest(struct ahash_request *req);
+int crypto4xx_kasumi_f9_setkey(struct crypto_ahash *hash,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_xcbc_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen);
+int crypto4xx_setkey_arc4(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen);
+int crypto4xx_arc4_decrypt(struct ablkcipher_request *req);
+int crypto4xx_arc4_encrypt(struct ablkcipher_request *req);
+u32 crypto4xx_alloc_arc4_state_record(struct crypto4xx_ctx *ctx);
+int crypto4xx_setauthsize_aes_ccm(struct crypto_aead *ciper,
+ unsigned int authsize);
+
+/* From crypto/md5.c */
+extern void md5_get_immediate_hash(struct crypto_tfm *tfm, u8 *data);
+extern unsigned int crypto4xx_sa_hash_tbl[3][6];
+
#endif
diff --git a/drivers/crypto/amcc/crypto4xx_sa.c =
b/drivers/crypto/amcc/crypto4xx_sa.c
index 466fd94..fa4ff7a 100644
--- a/drivers/crypto/amcc/crypto4xx_sa.c
+++ b/drivers/crypto/amcc/crypto4xx_sa.c
@@ -84,6 +84,119 @@ u32 get_dynamic_sa_offset_state_ptr_field(struct =
crypto4xx_ctx *ctx)
return sizeof(struct dynamic_sa_ctl) + offset * 4;
}
=20
+u32 get_dynamic_sa_offset_arc4_state_ptr(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size
+ + cts.bf.outer_size
+ + cts.bf.spi
+ + cts.bf.seq_num0
+ + cts.bf.seq_num1
+ + cts.bf.seq_num_mask0
+ + cts.bf.seq_num_mask1
+ + cts.bf.seq_num_mask2
+ + cts.bf.seq_num_mask3
+ + cts.bf.iv0
+ + cts.bf.iv1
+ + cts.bf.iv2
+ + cts.bf.iv3
+ + cts.bf.state_ptr
+ + cts.bf.arc4_ij_ptr;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_inner_digest(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+ offset =3D cts.bf.key_size;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_outer_digest(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_spi(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size
+ + cts.bf.outer_size;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_seq_num(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size
+ + cts.bf.outer_size
+ + cts.bf.spi;
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
+u32 get_dynamic_sa_offset_seq_num_mask(struct crypto4xx_ctx *ctx)
+{
+ u32 offset;
+ union dynamic_sa_contents cts;
+
+ if (ctx->direction =3D=3D DIR_INBOUND)
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_in))->sa_contents;
+ else
+ cts.w =3D ((struct dynamic_sa_ctl *)(ctx->sa_out))->sa_contents;
+
+ offset =3D cts.bf.key_size
+ + cts.bf.inner_size
+ + cts.bf.outer_size
+ + cts.bf.spi
+ + cts.bf.seq_num0
+ + cts.bf.seq_num1;
+
+ return sizeof(struct dynamic_sa_ctl) + offset * 4;
+}
+
u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx)
{
union dynamic_sa_contents cts;
@@ -92,6 +205,7 @@ u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx)
cts.w =3D ((struct dynamic_sa_ctl *) ctx->sa_in)->sa_contents;
else
cts.w =3D ((struct dynamic_sa_ctl *) ctx->sa_out)->sa_contents;
+
return (cts.bf.iv0 + cts.bf.iv1 + cts.bf.iv2 + cts.bf.iv3) * 4;
}
=20
diff --git a/drivers/crypto/amcc/crypto4xx_sa.h =
b/drivers/crypto/amcc/crypto4xx_sa.h
index 4b83ed7..5a1e308 100644
--- a/drivers/crypto/amcc/crypto4xx_sa.h
+++ b/drivers/crypto/amcc/crypto4xx_sa.h
@@ -50,12 +50,42 @@ union dynamic_sa_contents {
u32 w;
} __attribute__((packed));
=20
+#define SA_OPCODE_ESP 0
+#define SA_OPCODE_AH 1
+#define SA_OPCODE_SSL 4
+#define SA_OPCODE_TLS 5
+#define SA_OPCODE_SRTP 7
+#define SA_OPCODE_DTLS 1
+#define SA_OPCODE_TLS1_1 6
+
+#define SA_OP_GROUP_BASIC 0
+#define SA_OP_GROUP_PROTOCOL 1
+#define SA_OP_GROUP_EXTEND_PROTOCOL 3
+
+#define SA_OPCODE_EXT_PROT_DTLS 1
+#define SA_OPCODE_EXT_PROT_MACSEC 2
+#define SA_OPCODE_EXT_PROT_SSL 4
+#define SA_OPCODE_EXT_PROT_TLS10 5
+#define SA_OPCODE_EXT_PROT_TLS11 6
+
#define DIR_OUTBOUND 0
#define DIR_INBOUND 1
-#define SA_OP_GROUP_BASIC 0
#define SA_OPCODE_ENCRYPT 0
#define SA_OPCODE_DECRYPT 0
+#define SA_OPCODE_ENCRYPT_HASH 1
+#define SA_OPCODE_HASH_DECRYPT 1
#define SA_OPCODE_HASH 3
+#define SA_OPCODE_HASH_ENCRYPT 4
+#define SA_OPCODE_DECRYPT_HASH 4
+
+#define SA_OPCODE_ESP 0
+#define SA_OPCODE_AH 1
+#define SA_OPCODE_SSL 4
+#define SA_OPCODE_TLS 5
+#define SA_OPCODE_SRTP 7
+#define SA_OPCODE_DTLS 1
+#define SA_OPCODE_TLS1_1 6
+
#define SA_CIPHER_ALG_DES 0
#define SA_CIPHER_ALG_3DES 1
#define SA_CIPHER_ALG_ARC4 2
@@ -65,8 +95,17 @@ union dynamic_sa_contents {
=20
#define SA_HASH_ALG_MD5 0
#define SA_HASH_ALG_SHA1 1
+#define SA_HASH_ALG_SHA224 2
+#define SA_HASH_ALG_SHA256 3
+#define SA_HASH_ALG_SHA384 4
+#define SA_HASH_ALG_SHA512 5
+#define HASH_ALG_MAX_CNT 6
+#define SA_HASH_ALG_AES_XCBC_MAC_128 8
+#define SA_HASH_ALG_KASUMI_f9 9
+#define SA_HASH_ALG_GHASH 12
+#define SA_HASH_ALG_GMAC 13
+#define SA_HASH_ALG_CBC_MAC 14
#define SA_HASH_ALG_NULL 15
-#define SA_HASH_ALG_SHA1_DIGEST_SIZE 20
=20
#define SA_LOAD_HASH_FROM_SA 0
#define SA_LOAD_HASH_FROM_STATE 2
@@ -87,6 +126,16 @@ union dynamic_sa_contents {
#define SA_HEADER_PROC 1
#define SA_NO_HEADER_PROC 0
=20
+#define SA_HASH_ALG_MD5_DIGEST_SIZE 16
+#define SA_HASH_ALG_SHA1_DIGEST_SIZE 20
+#define SA_HASH_ALG_SHA224_DIGEST_SIZE 28
+#define SA_HASH_ALG_SHA256_DIGEST_SIZE 32
+#define SA_HASH_ALG_SHA384_DIGEST_SIZE 48
+#define SA_HASH_ALG_SHA512_DIGEST_SIZE 64
+
+
+#define CRYPTO4XX_MAC_ALGS { "md5", "sha1", \
+ "sha224", "sha256", "sha384", "sha512" }
union sa_command_0 {
struct {
u32 scatter:1;
@@ -111,7 +160,13 @@ union sa_command_0 {
} __attribute__((packed));
=20
#define CRYPTO_MODE_ECB 0
+#define CRYPTO_MODE_KASUMI 0
#define CRYPTO_MODE_CBC 1
+#define CRYPTO_MODE_OFB 2
+#define CRYPTO_MODE_CFB 3
+#define CRYPTO_MODE_AES_CTR 4
+#define CRYPTO_MODE_KASUMI_f8 4
+#define CRYPTO_MODE_AES_ICM 5
=20
#define CRYPTO_FEEDBACK_MODE_NO_FB 0
#define CRYPTO_FEEDBACK_MODE_64BIT_OFB 0
@@ -124,7 +179,7 @@ union sa_command_0 {
#define SA_AES_KEY_LEN_256 4
=20
#define SA_REV2 1
-/**
+/*
* The follow defines bits sa_command_1
* In Basic hash mode this bit define simple hash or hmac.
* In IPsec mode, this bit define muting control.
@@ -177,13 +232,46 @@ struct dynamic_sa_ctl {
/**
* State Record for Security Association (SA)
*/
-struct sa_state_record {
+struct sa_state_record {
u32 save_iv[4];
u32 save_hash_byte_cnt[2];
u32 save_digest[16];
} __attribute__((packed));
=20
/**
+ * Arc4 State Record for Security Association (SA)
+ */
+struct arc4_sr {
+ u32 arc4_state[64];
+} __attribute__((packed));
+
+/**
+ * Security Association (SA) for DES
+ */
+struct dynamic_sa_des {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[2];
+ u32 iv[2];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_DES_LEN (sizeof(struct dynamic_sa_des)/4)
+#define SA_DES_CONTENTS 0x26000022
+
+/**
+ * Security Association (SA) for 3DES
+ */
+struct dynamic_sa_3des {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[6];
+ u32 iv[2]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_3DES_LEN (sizeof(struct dynamic_sa_3des)/4)
+#define SA_3DES_CONTENTS 0x26000062
+
+/**
* Security Association (SA) for AES128
*
*/
@@ -194,11 +282,10 @@ struct dynamic_sa_aes128 {
u32 state_ptr;
u32 reserved;
} __attribute__((packed));
-
#define SA_AES128_LEN (sizeof(struct dynamic_sa_aes128)/4)
#define SA_AES128_CONTENTS 0x3e000042
=20
-/*
+/**
* Security Association (SA) for AES192
*/
struct dynamic_sa_aes192 {
@@ -208,7 +295,6 @@ struct dynamic_sa_aes192 {
u32 state_ptr;
u32 reserved;
} __attribute__((packed));
-
#define SA_AES192_LEN (sizeof(struct dynamic_sa_aes192)/4)
#define SA_AES192_CONTENTS 0x3e000062
=20
@@ -228,6 +314,19 @@ struct dynamic_sa_aes256 {
#define SA_AES_CONTENTS 0x3e000002
=20
/**
+ * Security Association (SA) for HASH128: HMAC-MD5
+ */
+struct dynamic_sa_hash128 {
+ struct dynamic_sa_ctl ctrl;
+ u32 inner_digest[4];
+ u32 outer_digest[4];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_HASH128_LEN (sizeof(struct dynamic_sa_hash128)/4)
+#define SA_HASH128_CONTENTS 0x20008402
+
+/**
* Security Association (SA) for HASH160: HMAC-SHA1
*/
struct dynamic_sa_hash160 {
@@ -240,4 +339,228 @@ struct dynamic_sa_hash160 {
#define SA_HASH160_LEN (sizeof(struct dynamic_sa_hash160)/4)
#define SA_HASH160_CONTENTS 0x2000a502
=20
+/**
+ * Security Association (SA) for HASH256: HMAC-SHA224, HMAC-SHA256
+ */
+struct dynamic_sa_hash256 {
+ struct dynamic_sa_ctl ctrl;
+ u32 inner_digest[8];
+ u32 outer_digest[8];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_HASH256_LEN (sizeof(struct dynamic_sa_hash256)/4)
+#define SA_HASH256_CONTENTS 0x20010802
+
+/*
+ * Security Association (SA) for HASH512: HMAC-SHA512
+ */
+struct dynamic_sa_hash512 {
+ struct dynamic_sa_ctl ctrl;
+ u32 inner_digest[16];
+ u32 outer_digest[16];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_HASH512_LEN (sizeof(struct dynamic_sa_hash512)/4)
+#define SA_HASH512_CONTENTS 0x20021002
+
+/**
+ * Security Association (SA) for AES128_XCBC_MAC
+ */
+struct dynamic_sa_aes128_xcbc_mac {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 inner_digest[8];
+ u32 outer_digest[8];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES128_XCBC_MAC_LEN (sizeof(struct =
dynamic_sa_aes128_xcbc_mac)/4)
+#define SA_AES128_XCBC_MAC_CONTENTS 0x3e010842
+
+/**
+ * Security Association (SA) for AES128_GCM
+ */
+struct dynamic_sa_aes128_gcm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 inner_digest[4];
+ u32 outer_digest[4];
+ u32 spi;
+ u32 seq;
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES128_GCM_LEN (sizeof(struct dynamic_sa_aes128_gcm)/4)
+#define SA_AES128_GCM_CONTENTS 0x3e0c8442
+
+/**
+ * Security Association (SA) for AES192_XCBC_MAC
+ */
+struct dynamic_sa_aes192_xcbc_mac {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[6];
+ u32 inner_digest[8];
+ u32 outer_digest[8];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES192_XCBC_MAC_LEN (sizeof(struct =
dynamic_sa_aes192_xcbc_mac)/4)
+#define SA_AES192_XCBC_MAC_CONTENTS 0x3e010862
+
+/**
+ * Security Association (SA) for AES192_GCM
+ */
+struct dynamic_sa_aes192_gcm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[6];
+ u32 inner_digest[4];
+ u32 outer_digest[4];
+ u32 spi;
+ u32 seq;
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES192_GCM_LEN (sizeof(struct dynamic_sa_aes192_gcm)/4)
+#define SA_AES192_GCM_CONTENTS 0x3e0c8462
+
+
+/**
+ * Security Association (SA) for AES256_XCBC_MAC
+ */
+struct dynamic_sa_aes256_xcbc_mac {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[8];
+ u32 inner_digest[8];
+ u32 outer_digest[8];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES256_XCBC_MAC_LEN (sizeof(struct =
dynamic_sa_aes256_xcbc_mac)/4)
+#define SA_AES256_XCBC_MAC_CONTENTS 0x3e010882
+
+/**
+ * Security Association (SA) for AES256_GCM
+ */
+struct dynamic_sa_aes256_gcm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[8];
+ u32 inner_digest[4];
+ u32 outer_digest[4];
+ u32 spi;
+ u32 seq;
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES256_GCM_LEN (sizeof(struct dynamic_sa_aes256_gcm)/4)
+#define SA_AES256_GCM_CONTENTS 0x3e0c8482
+#define SA_AES_GCM_CONTENTS 0x3e0c8402
+
+/**
+ * Security Association (SA) for Kasumi
+ */
+struct dynamic_sa_kasumi {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_KASUMI_LEN (sizeof(struct dynamic_sa_kasumi)/4)
+#define SA_KASUMI_CONTENTS 0x20000042
+
+/**
+ * Security Association (SA) for Kasumi f8
+ */
+struct dynamic_sa_kasumi_f8 {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 iv[2];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_KASUMI_F8_LEN (sizeof(struct dynamic_sa_kasumi_f8)/4)
+#define SA_KASUMI_F8_CONTENTS 0x26000042
+
+#define KASUMI_BLOCK_SIZE 8
+#define KASUMI_KEY_SIZE 16
+
+/**
+ * Security Association (SA) for Kasumi f8
+ */
+struct dynamic_sa_kasumi_f9 {
+ struct dynamic_sa_ctl ctrl;
+ u32 inner_digest[4];
+ u32 outter_digest[3];
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_KASUMI_F9_LEN (sizeof(struct dynamic_sa_kasumi_f9)/4)
+#define SA_KASUMI_F9_CONTENTS 0x20006402
+
+/**
+ * Security Association (SA) for AES256 CCM
+ */
+struct dynamic_sa_aes256_ccm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[8];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES256_CCM_LEN (sizeof(struct dynamic_sa_aes256_ccm)/4)
+#define SA_AES256_CCM_CONTENTS 0x3e000082
+#define SA_AES_CCM_CONTENTS 0x3e000002
+
+/**
+ * Security Association (SA) for AES192 CCM
+ */
+struct dynamic_sa_aes192_ccm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[6];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES192_CCM_LEN (sizeof(struct =
dynamic_sa_aes192_ccm)/4)
+#define SA_AES192_CCM_CONTENTS 0x3e000062
+
+/**
+ * Security Association (SA) for AES128 CCM
+ */
+struct dynamic_sa_aes128_ccm {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ u32 iv[4]; /* for CBC, OFC, and CFB mode */
+ u32 state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_AES128_CCM_LEN (sizeof(struct dynamic_sa_aes128_ccm)/4)
+#define SA_AES128_CCM_CONTENTS 0x3e000042
+
+/**
+ * Security Association (SA) for ARC4
+ */
+struct arc4_ij_ptr {
+ u32 rsv:16;
+ u32 j:8;
+ u32 i:8;
+} __attribute__((packed));
+
+struct dynamic_sa_arc4 {
+ struct dynamic_sa_ctl ctrl;
+ u32 key[4];
+ struct arc4_ij_ptr ij;
+ u32 arc4_state_ptr;
+ u32 reserved;
+} __attribute__((packed));
+#define SA_ARC4_LEN (sizeof(struct dynamic_sa_arc4)/4)
+#define SA_ARC4_CONTENTS 0xc0000042
+
#endif
--=20
1.5.5
^ permalink raw reply related
* [PATCH 3/3] AMCC Crypto4xx Device Driver v7
From: Shasi Pulijala @ 2009-06-15 17:28 UTC (permalink / raw)
To: herbert; +Cc: linuxppc-dev, linux-crypto
From: Shasi Pulijala <spulijala@amcc.com>
This patch further adds immediate hash functions to md5/sha1/sha2 algs.
These immediate hash functions are used in hmac key generation in PPC =
Crypto4xx driver.
Signed-off-by: Shasi Pulijala <spulijala@amcc.com>
Acked-by: Loc Ho <lho@amcc.com>
---
crypto/md5.c | 15 +++++++++++++++
crypto/sha1_generic.c | 15 +++++++++++++++
crypto/sha256_generic.c | 15 +++++++++++++++
crypto/sha512_generic.c | 19 +++++++++++++++++++
include/crypto/sha.h | 7 +++++++
5 files changed, 71 insertions(+), 0 deletions(-)
diff --git a/crypto/md5.c b/crypto/md5.c
index 83eb529..0c74b84 100644
--- a/crypto/md5.c
+++ b/crypto/md5.c
@@ -220,6 +220,21 @@ static int md5_final(struct shash_desc *desc, u8 =
*out)
return 0;
}
=20
+void md5_get_immediate_hash(struct crypto_tfm *tfm, u8 *data)
+{
+ struct shash_desc *desc =3D crypto_tfm_ctx(tfm);
+ struct md5_ctx *mctx =3D shash_desc_ctx(desc);
+ int i;
+
+ for (i =3D 0; i < MD5_HASH_WORDS; i++) {
+ *data++ =3D mctx->hash[i] & 0xFF;
+ *data++ =3D (mctx->hash[i] >> 8) & 0xFF;
+ *data++ =3D (mctx->hash[i] >> 16) & 0xFF;
+ *data++ =3D (mctx->hash[i] >> 24) & 0xFF;
+ }
+}
+EXPORT_SYMBOL_GPL(md5_get_immediate_hash);
+
static struct shash_alg alg =3D {
.digestsize =3D MD5_DIGEST_SIZE,
.init =3D md5_init,
diff --git a/crypto/sha1_generic.c b/crypto/sha1_generic.c
index 9efef20..e77b591 100644
--- a/crypto/sha1_generic.c
+++ b/crypto/sha1_generic.c
@@ -111,6 +111,21 @@ static int sha1_final(struct shash_desc *desc, u8 =
*out)
return 0;
}
=20
+void sha1_get_immediate_hash(struct crypto_tfm *tfm, u8 *data)
+{
+ struct shash_desc *desc =3D crypto_tfm_ctx(tfm);
+ struct sha1_ctx *sctx =3D shash_desc_ctx(desc);
+ int i;
+
+ for (i =3D 0; i < 5; i++) {
+ *data++ =3D sctx->state[i] & 0xFF;
+ *data++ =3D (sctx->state[i] >> 8) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 16) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 24) & 0xFF;
+ }
+}
+EXPORT_SYMBOL_GPL(sha1_get_immediate_hash);
+
static struct shash_alg alg =3D {
.digestsize =3D SHA1_DIGEST_SIZE,
.init =3D sha1_init,
diff --git a/crypto/sha256_generic.c b/crypto/sha256_generic.c
index 6349d83..0f5a66b 100644
--- a/crypto/sha256_generic.c
+++ b/crypto/sha256_generic.c
@@ -331,6 +331,21 @@ static int sha224_final(struct shash_desc *desc, u8 =
*hash)
return 0;
}
=20
+void sha256_get_immediate_hash(struct crypto_tfm *tfm, u8 *data)
+{
+ struct shash_desc *desc =3D crypto_tfm_ctx(tfm);
+ struct sha256_ctx *sctx =3D shash_desc_ctx(desc);
+ int i;
+
+ for (i =3D 0; i < 8; i++) {
+ *data++ =3D sctx->state[i] & 0xFF;
+ *data++ =3D (sctx->state[i] >> 8) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 16) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 24) & 0xFF;
+ }
+}
+EXPORT_SYMBOL_GPL(sha256_get_immediate_hash);
+
static struct shash_alg sha256 =3D {
.digestsize =3D SHA256_DIGEST_SIZE,
.init =3D sha256_init,
diff --git a/crypto/sha512_generic.c b/crypto/sha512_generic.c
index 3bea38d..c329903 100644
--- a/crypto/sha512_generic.c
+++ b/crypto/sha512_generic.c
@@ -257,6 +257,25 @@ static int sha384_final(struct shash_desc *desc, u8 =
*hash)
return 0;
}
=20
+void sha512_get_immediate_hash(struct crypto_tfm *tfm, u8 *data)
+{
+ struct shash_desc *desc =3D crypto_tfm_ctx(tfm);
+ struct sha512_ctx *sctx =3D shash_desc_ctx(desc);
+ int i;
+
+ for (i =3D 0; i < 8; i++) {
+ *data++ =3D (sctx->state[i] >> 32) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 40) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 48) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 56) & 0xFF;
+ *data++ =3D sctx->state[i] & 0xFF;
+ *data++ =3D (sctx->state[i] >> 8) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 16) & 0xFF;
+ *data++ =3D (sctx->state[i] >> 24) & 0xFF;
+ }
+}
+EXPORT_SYMBOL_GPL(sha512_get_immediate_hash);
+
static struct shash_alg sha512 =3D {
.digestsize =3D SHA512_DIGEST_SIZE,
.init =3D sha512_init,
diff --git a/include/crypto/sha.h b/include/crypto/sha.h
index c0ccc2b..8894c2f 100644
--- a/include/crypto/sha.h
+++ b/include/crypto/sha.h
@@ -62,4 +62,11 @@
#define SHA512_H6 0x1f83d9abfb41bd6bULL
#define SHA512_H7 0x5be0cd19137e2179ULL
=20
+/* From crypto/sha1_generic.c */
+void sha1_get_immediate_hash(struct crypto_tfm *tfm, u8 *data);
+/* From crypto/sha256_generic.c */
+void sha256_get_immediate_hash(struct crypto_tfm *tfm, u8 *data);
+/* From crypto/sha512_generic.c */
+void sha512_get_immediate_hash(struct crypto_tfm *tfm, u8 *data);
+
#endif
--=20
1.5.5
^ permalink raw reply related
* [PATCH 2/3] AMCC Crypto4xx Device Driver v7
From: Shasi Pulijala @ 2009-06-15 17:26 UTC (permalink / raw)
To: herbert; +Cc: linuxppc-dev, linux-crypto
From: Shasi Pulijala <spulijala@amcc.com>
This patch adds further support for AMCC ppc4xx security device driver. =
This is the
second release that adds algorithms like:
des/3des
rfc3686(ctr(aes))
gcm, ccm
hmac(md5,sha1,..,sha512)
xcbc(aes), arc4 and kasumi.
Signed-off-by: Shasi Pulijala <spulijala@amcc.com>
Acked-by: Loc Ho <lho@amcc.com>
---
drivers/crypto/amcc/crypto4xx_alg.c | 1492 =
++++++++++++++++++++++++++++++++++-
1 files changed, 1476 insertions(+), 16 deletions(-)
diff --git a/drivers/crypto/amcc/crypto4xx_alg.c =
b/drivers/crypto/amcc/crypto4xx_alg.c
index 61b6e1b..fac3543 100644
--- a/drivers/crypto/amcc/crypto4xx_alg.c
+++ b/drivers/crypto/amcc/crypto4xx_alg.c
@@ -24,10 +24,13 @@
#include <linux/crypto.h>
#include <linux/hash.h>
#include <crypto/internal/hash.h>
+#include <crypto/aead.h>
#include <linux/dma-mapping.h>
#include <crypto/algapi.h>
#include <crypto/aes.h>
+#include <crypto/des.h>
#include <crypto/sha.h>
+#include <crypto/authenc.h>
#include "crypto4xx_reg_def.h"
#include "crypto4xx_sa.h"
#include "crypto4xx_core.h"
@@ -58,9 +61,10 @@ void set_dynamic_sa_command_1(struct dynamic_sa_ctl =
*sa, u32 cm, u32 hmac_mc,
{
sa->sa_command_1.w =3D 0;
sa->sa_command_1.bf.crypto_mode31 =3D (cm & 4) >> 2;
- sa->sa_command_1.bf.crypto_mode9_8 =3D cm & 3;
+ sa->sa_command_1.bf.crypto_mode9_8 =3D (cm & 3);
sa->sa_command_1.bf.feedback_mode =3D cfb,
sa->sa_command_1.bf.sa_rev =3D 1;
+ sa->sa_command_1.bf.hmac_muting =3D hmac_mc;
sa->sa_command_1.bf.extended_seq_num =3D esn;
sa->sa_command_1.bf.seq_num_mask =3D sn_mask;
sa->sa_command_1.bf.mutable_bit_proc =3D mute;
@@ -69,6 +73,338 @@ void set_dynamic_sa_command_1(struct dynamic_sa_ctl =
*sa, u32 cm, u32 hmac_mc,
sa->sa_command_1.bf.copy_hdr =3D cp_hdr;
}
=20
+/** Table lookup for SA Hash Digest length and
+ * Hash Contents (based on Hash type)
+ */
+unsigned int crypto4xx_sa_hash_tbl[3][HASH_ALG_MAX_CNT] =3D {
+ /* Hash Contents */
+ { SA_HASH128_CONTENTS, SA_HASH160_CONTENTS, SA_HASH256_CONTENTS,
+ SA_HASH256_CONTENTS, SA_HASH512_CONTENTS, SA_HASH512_CONTENTS },
+ /* Digest len */
+ {4 * 4, 5 * 4, 7 * 4, 8 * 4, 12 * 4, 16 * 4},
+ /* SA Length */
+ { SA_HASH128_LEN, SA_HASH160_LEN, SA_HASH256_LEN, SA_HASH256_LEN,
+ SA_HASH512_LEN, SA_HASH512_LEN }
+};
+
+/** Table lookup for Hash Algorithms based on Hash type, used in
+ * crypto4xx_pre_compute_hmac()
+ */
+char *crypto4xx_hash_alg_map_tbl[HASH_ALG_MAX_CNT] =3D =
CRYPTO4XX_MAC_ALGS;
+
+static void crypto4xx_sg_setbuf(unsigned char *data, size_t bufsize,
+ struct scatterlist *sg, int sg_num)
+{
+ int remainder_of_page;
+ int i =3D 0;
+
+ sg_init_table(sg, sg_num);
+ while (bufsize > 0 && i < sg_num) {
+ sg_set_buf(&sg[i], data, bufsize);
+ remainder_of_page =3D PAGE_SIZE - sg[i].offset;
+ if (bufsize > remainder_of_page) {
+ /* the buffer was split over multiple pages */
+ sg[i].length =3D remainder_of_page;
+ bufsize -=3D remainder_of_page;
+ data +=3D remainder_of_page;
+ } else {
+ bufsize =3D 0;
+ }
+ i++;
+ }
+}
+
+void crypto4xx_compute_immediate_hash(struct crypto_tfm *child_tfm, u8 =
*data,
+ unsigned char ha)
+{
+ switch (ha) {
+ case SA_HASH_ALG_MD5:
+ md5_get_immediate_hash(child_tfm, data);
+ break;
+ case SA_HASH_ALG_SHA1:
+ sha1_get_immediate_hash(child_tfm, data);
+ break;
+ case SA_HASH_ALG_SHA256:
+ case SA_HASH_ALG_SHA224:
+ sha256_get_immediate_hash(child_tfm, data);
+ break;
+ case SA_HASH_ALG_SHA384:
+ case SA_HASH_ALG_SHA512:
+ sha512_get_immediate_hash(child_tfm, data);
+ break;
+ default:
+ break;
+ }
+}
+
+int crypto4xx_pre_compute_hmac(struct crypto4xx_ctx *ctx,
+ void *key,
+ unsigned int keylen,
+ unsigned int bs,
+ unsigned char ha,
+ unsigned char digs)
+{
+ u8 *ipad =3D NULL;
+ u8 *opad;
+ struct crypto_hash *child_hash =3D NULL;
+ struct hash_desc desc;
+ struct scatterlist sg[1];
+ struct scatterlist asg[2];
+ struct crypto_tfm *child_tfm;
+ char *child_name =3D NULL;
+ int i, rc =3D 0;
+ int ds;
+
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+ child_name =3D crypto4xx_hash_alg_map_tbl[ha];
+ child_hash =3D crypto_alloc_hash(child_name, 0, 0);
+ if (IS_ERR(child_hash)) {
+ rc =3D PTR_ERR(child_hash);
+ printk(KERN_ERR "failed to load "
+ "transform for %s error %d\n",
+ child_name, rc);
+ return rc;
+ }
+
+ ipad =3D kmalloc(bs * 2, GFP_KERNEL);
+ if (ipad =3D=3D NULL) {
+ crypto_free_hash(child_hash);
+ return -ENOMEM;
+ }
+
+ opad =3D ipad + bs;
+ child_tfm =3D crypto_hash_tfm(child_hash);
+ ds =3D crypto_hash_digestsize(child_hash);
+ desc.tfm =3D child_hash;
+ desc.flags =3D 0;
+ if (keylen > bs) {
+ crypto4xx_sg_setbuf(key, keylen, asg, 2);
+ rc =3D crypto_hash_init(&desc);
+ if (rc < 0)
+ goto err_alg_hash_key;
+ rc =3D crypto_hash_update(&desc, asg, keylen);
+ if (rc < 0)
+ goto err_alg_hash_key;
+ rc =3D crypto_hash_final(&desc, ipad);
+ keylen =3D ds;
+ } else {
+ memcpy(ipad, key, keylen);
+ }
+ memset(ipad + keylen, 0, bs-keylen);
+ memcpy(opad, ipad, bs);
+
+ for (i =3D 0; i < bs; i++) {
+ ipad[i] ^=3D 0x36;
+ opad[i] ^=3D 0x5c;
+ }
+
+ sg_init_one(&sg[0], ipad, bs);
+ rc =3D crypto_hash_init(&desc);
+ if (rc < 0)
+ goto err_alg_hash_key;
+ rc =3D crypto_hash_update(&desc, sg, bs);
+ if (rc < 0)
+ goto err_alg_hash_key;
+
+ if (ha =3D=3D SA_HASH_ALG_SHA224)
+ ds =3D SHA256_DIGEST_SIZE;
+ else if (ha =3D=3D SA_HASH_ALG_SHA384)
+ ds =3D SHA512_DIGEST_SIZE;
+
+ crypto4xx_compute_immediate_hash(child_tfm, ipad, ha);
+ crypto4xx_memcpy_le(ctx->sa_in +
+ get_dynamic_sa_offset_inner_digest(ctx), ipad, ds);
+
+ sg_init_one(&sg[0], opad, bs);
+ rc =3D crypto_hash_init(&desc);
+ if (rc < 0)
+ goto err_alg_hash_key;
+
+ rc =3D crypto_hash_update(&desc, sg, bs);
+ if (rc < 0)
+ goto err_alg_hash_key;
+
+ crypto4xx_compute_immediate_hash(child_tfm, opad, ha);
+ crypto4xx_memcpy_le(ctx->sa_in +
+ get_dynamic_sa_offset_outer_digest(ctx), opad, ds);
+
+err_alg_hash_key:
+ kfree(ipad);
+ crypto_free_hash(child_hash);
+ return rc;
+}
+
+int crypto4xx_compute_gcm_hash_key_sw(struct crypto4xx_ctx *ctx,
+ const u8 *key,
+ unsigned int keylen)
+{
+ struct crypto_blkcipher *aes_tfm =3D NULL;
+ struct blkcipher_desc desc;
+ struct scatterlist sg[1];
+ char src[16];
+ int rc =3D 0;
+
+ aes_tfm =3D crypto_alloc_blkcipher("ecb(aes)", 0, CRYPTO_ALG_ASYNC);
+ if (IS_ERR(aes_tfm)) {
+ printk(KERN_ERR "failed to load transform for %ld\n",
+ PTR_ERR(aes_tfm));
+ rc =3D PTR_ERR(aes_tfm);
+ return rc;
+ }
+ desc.tfm =3D aes_tfm;
+ desc.flags =3D 0;
+
+ memset(src, 0, 16);
+ rc =3D crypto_blkcipher_setkey(aes_tfm, key, keylen);
+ if (rc) {
+ printk(KERN_ERR "setkey() failed flags=3D%x\n",
+ crypto_blkcipher_get_flags(aes_tfm));
+ goto out;
+ }
+
+ sg_init_one(sg, src, 16);
+ rc =3D crypto_blkcipher_encrypt(&desc, sg, sg, 16);
+ if (rc)
+ goto out;
+ crypto4xx_memcpy_le(ctx->sa_in +
+ get_dynamic_sa_offset_inner_digest(ctx), src, 16);
+
+out:
+ crypto_free_blkcipher(aes_tfm);
+ return rc;
+}
+
+/**
+ * 3DES/DES Functions
+ *
+ */
+static int crypto4xx_setkey_3des(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen,
+ unsigned char cm,
+ unsigned char fb)
+{
+ struct crypto_tfm *tfm =3D crypto_ablkcipher_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ int rc;
+
+ if (keylen !=3D DES_KEY_SIZE && keylen !=3D DES3_EDE_KEY_SIZE) {
+ crypto_ablkcipher_set_flags(cipher,
+ CRYPTO_TFM_RES_BAD_KEY_LEN);
+
+ return -EINVAL;
+ }
+
+ if (keylen =3D=3D DES_KEY_SIZE) {
+ u32 tmp[32];
+ rc =3D des_ekey(tmp, key);
+ if (unlikely(rc =3D=3D 0) &&
+ (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
+ crypto_ablkcipher_set_flags(cipher,
+ CRYPTO_TFM_RES_WEAK_KEY);
+ return -EINVAL;
+ }
+ }
+
+ /* Create SA */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, keylen =3D=3D 8 ? SA_DES_LEN : =
SA_3DES_LEN);
+ if (rc)
+ return rc;
+ /*
+ * state record will state in base ctx, so iv and
+ * hash result can be reused
+ * also don't need to alloc each packet coming
+ */
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ /* Setup SA */
+ ctx->direction =3D DIR_INBOUND;
+ ctx->hash_final =3D 0;
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_NULL,
+ SA_CIPHER_ALG_DES,
+ SA_PAD_TYPE_ZERO, SA_OP_GROUP_BASIC,
+ SA_OPCODE_DECRYPT, DIR_INBOUND);
+
+ set_dynamic_sa_command_1(sa, cm, SA_HASH_MODE_HASH,
+ fb, SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ if (keylen =3D=3D DES_KEY_SIZE) {
+ crypto4xx_memcpy_le(((struct dynamic_sa_des *) sa)->key,
+ key, keylen);
+ ((struct dynamic_sa_des *)sa)->ctrl.sa_contents =3D
+ SA_DES_CONTENTS;
+ sa->sa_command_0.bf.cipher_alg =3D SA_CIPHER_ALG_DES;
+ } else {
+ crypto4xx_memcpy_le(((struct dynamic_sa_3des *) sa)->key,
+ key, keylen);
+ ((struct dynamic_sa_3des *)sa)->ctrl.sa_contents =3D
+ SA_3DES_CONTENTS;
+ sa->sa_command_0.bf.cipher_alg =3D SA_CIPHER_ALG_3DES;
+ }
+
+ memcpy((void *)(ctx->sa_in +
+ get_dynamic_sa_offset_state_ptr_field(ctx)),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ ctx->is_hash =3D 0;
+ sa->sa_command_0.bf.dir =3D DIR_INBOUND;
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+}
+
+int crypto4xx_setkey_3des_cfb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_3des(cipher, key, keylen,
+ CRYPTO_MODE_CFB,
+ CRYPTO_FEEDBACK_MODE_8BIT_CFB);
+}
+
+int crypto4xx_setkey_3des_ofb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_3des(cipher, key, keylen,
+ CRYPTO_MODE_OFB,
+ CRYPTO_FEEDBACK_MODE_64BIT_OFB);
+}
+
+int crypto4xx_setkey_3des_cbc(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_3des(cipher, key, keylen,
+ CRYPTO_MODE_CBC,
+ CRYPTO_FEEDBACK_MODE_NO_FB);
+}
+
+int crypto4xx_setkey_3des_ecb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_3des(cipher, key, keylen,
+ CRYPTO_MODE_ECB,
+ CRYPTO_FEEDBACK_MODE_NO_FB);
+}
+
+
int crypto4xx_encrypt(struct ablkcipher_request *req)
{
struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
@@ -79,22 +415,54 @@ int crypto4xx_encrypt(struct ablkcipher_request =
*req)
ctx->pd_ctl =3D 0x1;
=20
return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
- req->nbytes, req->info,
- get_dynamic_sa_iv_size(ctx));
+ req->nbytes, NULL, 0, req->info,
+ get_dynamic_sa_iv_size(ctx));
}
=20
int crypto4xx_decrypt(struct ablkcipher_request *req)
{
struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
=20
+ ctx->hash_final =3D 0;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x1;
ctx->direction =3D DIR_INBOUND;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0, req->info,
+ get_dynamic_sa_iv_size(ctx));
+}
+
+int crypto4xx_encrypt_ctr(struct ablkcipher_request *req)
+{
+ struct crypto_ablkcipher *ablkcipher =3D =
crypto_ablkcipher_reqtfm(req);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
ctx->hash_final =3D 0;
ctx->is_hash =3D 0;
- ctx->pd_ctl =3D 1;
+ ctx->pd_ctl =3D 0x1;
+ ctx->direction =3D DIR_OUTBOUND;
=20
return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
- req->nbytes, req->info,
- get_dynamic_sa_iv_size(ctx));
+ req->nbytes, NULL, 0,
+ req->info,
+ crypto_ablkcipher_ivsize(ablkcipher));
+}
+
+int crypto4xx_decrypt_ctr(struct ablkcipher_request *req)
+{
+ struct crypto_ablkcipher *ablkcipher =3D =
crypto_ablkcipher_reqtfm(req);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->hash_final =3D 0;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x1;
+ ctx->direction =3D DIR_INBOUND;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0,
+ req->info,
+ crypto_ablkcipher_ivsize(ablkcipher));
}
=20
/**
@@ -166,6 +534,13 @@ static int crypto4xx_setkey_aes(struct =
crypto_ablkcipher *cipher,
return 0;
}
=20
+int crypto4xx_setkey_aes_ecb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_ECB,
+ CRYPTO_FEEDBACK_MODE_NO_FB);
+}
+
int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher,
const u8 *key, unsigned int keylen)
{
@@ -173,8 +548,677 @@ int crypto4xx_setkey_aes_cbc(struct =
crypto_ablkcipher *cipher,
CRYPTO_FEEDBACK_MODE_NO_FB);
}
=20
+int crypto4xx_setkey_aes_ctr(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ablkcipher_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ u32 cnt =3D 1;
+ int rc;
+ u32 cm =3D CRYPTO_MODE_AES_CTR;
+
+ keylen -=3D 4;
+ /* Create SA */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ if (keylen !=3D AES_KEYSIZE_256 &&
+ keylen !=3D AES_KEYSIZE_192 && keylen !=3D AES_KEYSIZE_128) {
+ crypto_ablkcipher_set_flags(cipher,
+ CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_AES128_LEN + (keylen-16) / 4);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ ctx->hash_final =3D 0;
+ ctx->ctr_aes =3D 1;
+ /* Setup SA */
+ set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_NULL,
+ SA_CIPHER_ALG_AES, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_ENCRYPT,
+ DIR_INBOUND);
+ set_dynamic_sa_command_1(sa, cm, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB,
+ SA_EXTENDED_SN_OFF, SA_SEQ_MASK_OFF,
+ SA_MC_ENABLE, SA_NOT_COPY_PAD,
+ SA_NOT_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+ sa->sa_contents =3D SA_AES_CONTENTS | (keylen << 2);
+ sa->sa_command_1.bf.key_len =3D keylen >> 3;
+
+ ctx->direction =3D DIR_INBOUND;
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+
+ crypto4xx_memcpy_le(ctx->state_record, key + keylen, 4);
+ crypto4xx_memcpy_le(ctx->state_record + 12, (void *)&cnt, 4);
+
+ sa->sa_command_0.bf.dir =3D DIR_INBOUND;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+}
+
+int crypto4xx_setkey_aes_cfb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_CFB,
+ CRYPTO_FEEDBACK_MODE_128BIT_CFB);
+}
+
+int crypto4xx_setkey_aes_ofb(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_OFB,
+ CRYPTO_FEEDBACK_MODE_64BIT_OFB);
+}
+
+int crypto4xx_setkey_aes_icm(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ return crypto4xx_setkey_aes(cipher, key, keylen, CRYPTO_MODE_AES_ICM,
+ CRYPTO_FEEDBACK_MODE_NO_FB);
+}
+
+/**
+ * AES-GCM Functions
+ */
+static inline int crypto4xx_aes_gcm_validate_keylen(unsigned int =
keylen)
+{
+ switch (keylen) {
+ case 16:
+ case 20:
+ case 24:
+ case 30:
+ case 32:
+ case 36:
+ return 0;
+ default:
+ printk(KERN_ERR "crypto4xx_setkey_aes_gcm: "
+ "ERROR keylen =3D 0x%08x\n", keylen);
+ return -EINVAL;
+ }
+ return -EINVAL;
+}
+
+int crypto4xx_setkey_aes_gcm(struct crypto_aead *cipher,
+ const u8 *key, unsigned int keylen)
+
+{
+ struct crypto_tfm *tfm =3D crypto_aead_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ int rc =3D 0;
+
+ u32 cm =3D 4;
+
+ if (crypto4xx_aes_gcm_validate_keylen(keylen) !=3D 0) {
+ printk(KERN_ERR "crypto4xx_setkey_aes_gcm:"
+ "ERROR keylen =3D 0x%08x\n", keylen);
+ crypto_aead_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_AES128_GCM_LEN + (keylen-16) / 4);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc)
+ goto err;
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+
+ sa->sa_contents =3D SA_AES_GCM_CONTENTS | (keylen << 2);
+ sa->sa_command_1.bf.key_len =3D keylen >> 3;
+
+ ctx->direction =3D DIR_INBOUND;
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+
+ rc =3D crypto4xx_compute_gcm_hash_key_sw(ctx, key, keylen);
+ if (rc) {
+ printk(KERN_ERR "GCM hash key setting failed =3D %d\n", rc);
+ goto err;
+ }
+
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ ctx->is_gcm =3D 1;
+ ctx->hash_final =3D 1;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x11;
+
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_GHASH,
+ SA_CIPHER_ALG_AES, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_HASH_DECRYPT,
+ DIR_INBOUND);
+
+ sa->sa_command_1.bf.crypto_mode31 =3D (cm & 4) >> 2;
+ sa->sa_command_1.bf.crypto_mode9_8 =3D (cm & 3);
+ sa->sa_command_1.bf.feedback_mode =3D 0;
+
+ sa->sa_command_1.bf.hash_crypto_offset =3D 0;
+ sa->sa_command_1.bf.sa_rev =3D 1;
+ sa->sa_command_1.bf.copy_payload =3D 1;
+
+ sa->sa_command_1.bf.copy_pad =3D 0;
+ sa->sa_command_1.bf.copy_hdr =3D 0;
+ sa->sa_command_1.bf.mutable_bit_proc =3D 1;
+ sa->sa_command_1.bf.seq_num_mask =3D 1;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+ sa->sa_command_0.bf.opcode =3D SA_OPCODE_ENCRYPT_HASH;
+
+ return 0;
+err:
+ crypto4xx_free_sa(ctx);
+ return rc;
+}
+
+int crypto4xx_encrypt_aes_gcm(struct aead_request *req)
+{
+ struct crypto_aead *aead =3D crypto_aead_reqtfm(req);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->direction =3D DIR_OUTBOUND;
+ ctx->append_icv =3D 1;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->cryptlen, req->assoc, req->assoclen,
+ req->iv, crypto_aead_ivsize(aead));
+}
+
+int crypto4xx_decrypt_aes_gcm(struct aead_request *req)
+{
+ struct crypto_aead *aead =3D crypto_aead_reqtfm(req);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ int len =3D req->cryptlen - crypto_aead_authsize(aead);
+
+ ctx->direction =3D DIR_INBOUND;
+ ctx->append_icv =3D 0;
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ len, req->assoc, req->assoclen,
+ req->iv, crypto_aead_ivsize(aead));
+}
+
+int crypto4xx_givencrypt_aes_gcm(struct aead_givcrypt_request *req)
+{
+ return -ENOSYS;
+}
+
+int crypto4xx_givdecrypt_aes_gcm(struct aead_givcrypt_request *req)
+{
+ return -ENOSYS;
+}
+
/**
- * HASH SHA1 Functions
+ * AES-CCM Functions
+ */
+int crypto4xx_setauthsize_aes(struct crypto_aead *ciper,
+ unsigned int authsize)
+{
+ struct aead_tfm *tfm =3D crypto_aead_crt(ciper);
+
+ switch (authsize) {
+ case 8:
+ case 12:
+ case 16:
+ case 10:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ tfm->authsize =3D authsize;
+ return 0;
+}
+
+int crypto4xx_setkey_aes_ccm(struct crypto_aead *cipher, const u8 *key,
+ unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_aead_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ int rc =3D 0;
+
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_AES128_CCM_LEN + (keylen-16) / 4);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ /* Setup SA */
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ sa->sa_contents =3D SA_AES_CCM_CONTENTS | (keylen << 2);
+
+ set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_CBC_MAC,
+ SA_CIPHER_ALG_AES,
+ SA_PAD_TYPE_ZERO, SA_OP_GROUP_BASIC,
+ SA_OPCODE_HASH_DECRYPT, DIR_INBOUND);
+
+ sa->sa_command_0.bf.digest_len =3D 0;
+ sa->sa_command_1.bf.key_len =3D keylen >> 3;
+ ctx->direction =3D DIR_INBOUND;
+ ctx->append_icv =3D 0;
+ ctx->is_gcm =3D 0;
+ ctx->hash_final =3D 1;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x11;
+
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+
+ set_dynamic_sa_command_1(sa, CRYPTO_MODE_AES_CTR, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB, SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_CBC_MAC,
+ SA_CIPHER_ALG_AES,
+ SA_PAD_TYPE_ZERO, SA_OP_GROUP_BASIC,
+ SA_OPCODE_ENCRYPT_HASH, DIR_OUTBOUND);
+ set_dynamic_sa_command_1(sa, CRYPTO_MODE_AES_CTR, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB, SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ return 0;
+}
+
+int crypto4xx_encrypt_aes_ccm(struct aead_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ struct crypto_aead *aead =3D crypto_aead_reqtfm(req);
+ struct dynamic_sa_ctl *sa;
+
+ ctx->direction =3D DIR_OUTBOUND;
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ if (req->assoclen)
+ sa->sa_command_1.bf.hash_crypto_offset =3D req->assoclen >> 2;
+
+ sa->sa_command_0.bf.digest_len =3D (crypto_aead_authsize(aead) >> 2);
+ if ((req->iv[0] & 7) =3D=3D 1)
+ sa->sa_command_1.bf.crypto_mode9_8 =3D 1;
+
+ ctx->append_icv =3D 1;
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->cryptlen, req->assoc, req->assoclen,
+ req->iv, 16);
+}
+
+int crypto4xx_decrypt_aes_ccm(struct aead_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ struct crypto_aead *aead =3D crypto_aead_reqtfm(req);
+ struct dynamic_sa_ctl *sa;
+
+ /* Support only counter field length of 2 and 4 bytes */
+ if ((req->iv[0] & 0x7) !=3D 1 && (req->iv[0] & 0x7) !=3D 3) {
+ printk(KERN_ERR "algorithm AES-CCM "
+ "unsupported counter length %d\n",
+ req->iv[0] & 0x7);
+ return -EINVAL;
+ }
+
+ ctx->direction =3D DIR_INBOUND;
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+
+ sa->sa_command_0.bf.digest_len =3D (crypto_aead_authsize(aead) >> 2);
+ if ((req->iv[0] & 7) =3D=3D 1)
+ sa->sa_command_1.bf.crypto_mode9_8 =3D 1;
+ else
+ sa->sa_command_1.bf.crypto_mode9_8 =3D 0;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->cryptlen, req->assoc, req->assoclen,
+ req->iv, 16);
+}
+
+int crypto4xx_givencrypt_aes_ccm(struct aead_givcrypt_request *req)
+{
+ return -ENOSYS;
+}
+
+int crypto4xx_givdecrypt_aes_ccm(struct aead_givcrypt_request *req)
+{
+ return -ENOSYS;
+}
+
+/**
+ * Kasumi Functions
+ *
+ */
+int crypto4xx_setkey_kasumi(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen,
+ unsigned char cm)
+{
+ struct crypto_tfm *tfm =3D crypto_ablkcipher_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ u32 sa_len =3D 0;
+ int rc;
+
+ if (keylen !=3D 16) {
+ crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ printk(KERN_ERR "%s: keylen fail\n", __func__);
+ return -EINVAL;
+ }
+
+ /* Create SA - SA is created here as the alg init function is
+ * common to many algorithm and it does not have the SA length
+ * as it is specify to an algorithm. See setkey function has
+ * to be called for encryption/decryption algorithm once,
+ * it is okay to do this here.
+ */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ if (cm =3D=3D CRYPTO_MODE_KASUMI)
+ sa_len =3D SA_KASUMI_LEN;
+ else if (cm =3D=3D CRYPTO_MODE_KASUMI_f8)
+ sa_len =3D SA_KASUMI_F8_LEN;
+
+ rc =3D crypto4xx_alloc_sa(ctx, sa_len);
+ if (rc)
+ return rc;
+
+ if (!ctx->state_record) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ /* Setup SA - SA is a shared resource for request operation. As
+ * crypto alg and crypto mode can not be change, it should be
+ * ok to store them there. SA control words are not used by the
+ * hardware (configured in token instead), we use it to store
+ * software algorithm and mode selected.
+ */
+
+ if (cm =3D=3D CRYPTO_MODE_KASUMI) {
+ sa->sa_contents =3D SA_KASUMI_CONTENTS;
+ sa->sa_command_0.bf.cipher_alg =3D SA_CIPHER_ALG_KASUMI;
+ sa->sa_command_0.bf.hash_alg =3D SA_HASH_ALG_NULL;
+ sa->sa_command_0.bf.pad_type =3D 3; /* set to zero padding */
+ sa->sa_command_0.bf.opcode =3D 0;
+ sa->sa_command_1.bf.crypto_mode31 =3D (cm & 4) >> 2;
+ sa->sa_command_1.bf.crypto_mode9_8 =3D (cm & 3);
+ sa->sa_command_1.bf.feedback_mode =3D 0;
+ } else {
+ sa->sa_contents =3D SA_KASUMI_F8_CONTENTS;
+ sa->sa_command_0.bf.cipher_alg =3D SA_CIPHER_ALG_KASUMI;
+ sa->sa_command_0.bf.hash_alg =3D SA_HASH_ALG_NULL;
+ sa->sa_command_0.bf.pad_type =3D 3;
+ sa->sa_command_0.bf.load_iv =3D SA_LOAD_IV_FROM_STATE;
+ sa->sa_command_0.bf.opcode =3D SA_OPCODE_ENCRYPT;
+ sa->sa_command_1.bf.crypto_mode31 =3D (cm & 4) >> 2;;
+ sa->sa_command_1.bf.crypto_mode9_8 =3D (cm & 3);
+ sa->sa_command_1.bf.feedback_mode =3D 0;
+ sa->sa_command_1.bf.mutable_bit_proc =3D 1;
+ }
+
+ ctx->direction =3D DIR_INBOUND;
+ sa->sa_command_1.bf.sa_rev =3D 1;
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+ ctx->is_hash =3D 0;
+
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ sa->sa_command_0.bf.dir =3D DIR_INBOUND;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+}
+
+int crypto4xx_setkey_kasumi_p(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen)
+{
+ return crypto4xx_setkey_kasumi(cipher, key, keylen,
+ CRYPTO_MODE_KASUMI);
+}
+
+int crypto4xx_setkey_kasumi_f8(struct crypto_ablkcipher *cipher,
+ const u8 *key,
+ unsigned int keylen)
+{
+ return crypto4xx_setkey_kasumi(cipher, key, keylen,
+ CRYPTO_MODE_KASUMI_f8);
+}
+
+/**
+ * Kasumi and Kasumi f8 work with number of bits.
+ * The crypto engine can only take number bytes as source/destination =
length
+ * User should round up bit number to byte number. When receive the =
result
+ * packet and then mask off the extra bits in the last
+ * byte.
+ */
+int crypto4xx_encrypt_kasumi(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ ctx->direction =3D DIR_OUTBOUND;
+ ctx->pd_ctl =3D 0x1;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0, NULL, 0);
+}
+
+/**
+ * Kasumi and Kasumi f8 work with number of bits.
+ * The crypto engine can only take number bytes as source/destination =
length
+ * User should round up bit number to byte number.
+ * When receive the result packet and then mask off the extra bits in =
the last
+ * byte.
+ */
+int crypto4xx_decrypt_kasumi(struct aead_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->pd_ctl =3D 0x1;
+ ctx->direction =3D DIR_INBOUND;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->cryptlen, NULL, 0, NULL, 0);
+}
+
+/**
+ * Kasumi and Kasumi f8 work with number of bits.
+ * The crypto engine can only take number bytes as source/destination =
length
+ * The user should round up bit number to byte number.
+ * When receive the result packet and then mask
+ * off the extra bits in the last byte.
+ */
+int crypto4xx_encrypt_kasumi_f8(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->direction =3D DIR_OUTBOUND;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x1;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0, req->info, 8);
+}
+
+/** Note:
+ * Kasumi and Kasumi f8 work with number of bits.
+ * The crypto engine can only take number bytes as source/destination =
length
+ * User should round up bit number to byte number.
+ * When receive the result packet and then mask off the extra bits in =
the last
+ * byte.
+ */
+int crypto4xx_decrypt_kasumi_f8(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ ctx->direction =3D DIR_INBOUND;
+ ctx->is_hash =3D 0;
+ ctx->pd_ctl =3D 0x1;
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src, req->dst,
+ req->nbytes, NULL, 0, req->info, 8);
+}
+
+/**
+ * ARC4 Functions
+ *
+ */
+int crypto4xx_setkey_arc4(struct crypto_ablkcipher *cipher,
+ const u8 *key, unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ablkcipher_tfm(cipher);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ int rc =3D 0;
+
+ /* Create SA */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_ARC4_LEN);
+ if (rc)
+ return rc;
+
+ crypto4xx_alloc_arc4_state_record(ctx);
+ if (ctx->arc4_state_record =3D=3D NULL) {
+ crypto4xx_free_sa(ctx);
+ return -ENOMEM;
+ }
+
+ /* Setup SA */
+ ctx->sa_len =3D SA_ARC4_LEN;
+ ctx->init_arc4 =3D 1;
+ ctx->direction =3D DIR_INBOUND;
+
+ sa =3D ctx->sa_in;
+ memset(((struct dynamic_sa_arc4 *)sa)->key, 0, 16);
+
+ crypto4xx_memcpy_le(((struct dynamic_sa_arc4 *)sa)->key, key, keylen);
+ sa->sa_contents =3D SA_ARC4_CONTENTS;
+
+ set_dynamic_sa_command_0(sa, SA_NOT_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_LOAD_HASH_FROM_SA, SA_LOAD_IV_FROM_STATE,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_NULL,
+ SA_CIPHER_ALG_ARC4, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_ENCRYPT,
+ DIR_INBOUND);
+
+ set_dynamic_sa_command_1(sa, 0, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB,
+ SA_EXTENDED_SN_OFF, SA_SEQ_MASK_OFF,
+ SA_MC_ENABLE, SA_NOT_COPY_PAD,
+ SA_COPY_PAYLOAD, SA_NOT_COPY_HDR);
+
+ sa->sa_command_1.bf.key_len =3D keylen;
+ memcpy(sa + get_dynamic_sa_offset_arc4_state_ptr(ctx),
+ (void *)&ctx->arc4_state_record_dma_addr, 4);
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+}
+
+int crypto4xx_arc4_encrypt(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ if (ctx->init_arc4) {
+ ctx->init_arc4 =3D 0;
+ ctx->pd_ctl =3D 9;
+ } else {
+ ctx->pd_ctl =3D 0x1;
+ }
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src,
+ req->dst,
+ req->nbytes, NULL, 0, NULL, 0);
+}
+
+int crypto4xx_arc4_decrypt(struct ablkcipher_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+
+ if (ctx->init_arc4) {
+ ctx->init_arc4 =3D 0;
+ ctx->pd_ctl =3D 9;
+ } else {
+ ctx->pd_ctl =3D 0x1;
+ }
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src,
+ req->dst,
+ req->nbytes, NULL, 0, NULL, 0);
+}
+
+/**
+ * Support MD5/SHA/HMAC Hashing Algorithms
+ *
*/
static int crypto4xx_hash_alg_init(struct crypto_tfm *tfm,
unsigned int sa_len,
@@ -185,7 +1229,6 @@ static int crypto4xx_hash_alg_init(struct =
crypto_tfm *tfm,
struct crypto4xx_alg *my_alg =3D crypto_alg_to_crypto4xx_alg(alg);
struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
struct dynamic_sa_ctl *sa;
- struct dynamic_sa_hash160 *sa_in;
int rc;
=20
ctx->dev =3D my_alg->dev;
@@ -210,6 +1253,9 @@ static int crypto4xx_hash_alg_init(struct =
crypto_tfm *tfm,
=20
tfm->crt_ahash.reqsize =3D sizeof(struct crypto4xx_ctx);
sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ /*
+ * Setup hash algorithm and hash mode
+ */
set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
SA_NO_HEADER_PROC, ha, SA_CIPHER_ALG_NULL,
@@ -220,13 +1266,12 @@ static int crypto4xx_hash_alg_init(struct =
crypto_tfm *tfm,
SA_SEQ_MASK_OFF, SA_MC_ENABLE,
SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
SA_NOT_COPY_HDR);
+
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+ sa->sa_contents =3D crypto4xx_sa_hash_tbl[0][ha];
ctx->direction =3D DIR_INBOUND;
- sa->sa_contents =3D SA_HASH160_CONTENTS;
- sa_in =3D (struct dynamic_sa_hash160 *) ctx->sa_in;
- /* Need to zero hash digest in SA */
- memset(sa_in->inner_digest, 0, sizeof(sa_in->inner_digest));
- memset(sa_in->outer_digest, 0, sizeof(sa_in->outer_digest));
- sa_in->state_ptr =3D ctx->state_record_dma_addr;
+ memcpy(ctx->sa_in + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
=20
return 0;
@@ -260,7 +1305,7 @@ int crypto4xx_hash_update(struct ahash_request =
*req)
=20
return crypto4xx_build_pd(&req->base, ctx, req->src,
(struct scatterlist *) req->result,
- req->nbytes, NULL, 0);
+ req->nbytes, NULL, 0, NULL, 0);
}
=20
int crypto4xx_hash_final(struct ahash_request *req)
@@ -278,16 +1323,431 @@ int crypto4xx_hash_digest(struct ahash_request =
*req)
=20
return crypto4xx_build_pd(&req->base, ctx, req->src,
(struct scatterlist *) req->result,
- req->nbytes, NULL, 0);
+ req->nbytes, NULL, 0, NULL, 0);
}
=20
/**
* SHA1 Algorithm
*/
+
+int crypto4xx_md5_alg_init(struct crypto_tfm *tfm)
+{
+ return crypto4xx_hash_alg_init(tfm, SA_HASH128_LEN, SA_HASH_ALG_MD5,
+ SA_HASH_MODE_HASH);
+}
+
+int crypto4xx_hash_hmac_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen,
+ unsigned int sa_len,
+ unsigned char ha,
+ unsigned char hm,
+ unsigned int max_keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ahash_tfm(hash);
+ struct crypto_alg *alg =3D tfm->__crt_alg;
+ struct crypto4xx_alg *my_alg =3D crypto_alg_to_crypto4xx_alg(alg);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ struct dynamic_sa_ctl *sa;
+ int bs =3D crypto_tfm_alg_blocksize(tfm);
+ int ds =3D crypto_ahash_digestsize(hash);
+ int rc;
+
+ ctx->dev =3D my_alg->dev;
+
+ if (keylen > max_keylen) {
+ crypto_ahash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -1;
+ }
+
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ /* Create SA */
+ rc =3D crypto4xx_alloc_sa(ctx, sa_len);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc)
+ goto err;
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+
+ /*
+ * Setup hash algorithm and hash mode
+ */
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
+ SA_NO_HEADER_PROC,
+ ha, SA_CIPHER_ALG_NULL, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_HASH,
+ DIR_INBOUND);
+ set_dynamic_sa_command_1(sa, 0, hm,
+ CRYPTO_FEEDBACK_MODE_NO_FB,
+ SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+ sa->sa_contents =3D crypto4xx_sa_hash_tbl[0][ha];
+ ctx->direction =3D DIR_INBOUND;
+ memcpy((ctx->sa_in) + get_dynamic_sa_offset_state_ptr_field(ctx),
+ (void *)&ctx->state_record_dma_addr, 4);
+
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ rc =3D crypto4xx_pre_compute_hmac(ctx, (void *)key, keylen, bs, ha, =
ds);
+ if (rc) {
+ printk(KERN_ERR "Hmac Initial Digest Calculation failed\n");
+ goto err;
+ }
+
+ ctx->hash_final =3D 1;
+ ctx->is_hash =3D 1;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+err:
+ crypto4xx_free_sa(ctx);
+ return rc;
+}
+
+int crypto4xx_md5_hmac_setkey(struct crypto_ahash *hash, const u8 *key,
+ unsigned int keylen)
+{
+ return crypto4xx_hash_hmac_setkey(hash, key, keylen, SA_HASH128_LEN,
+ SA_HASH_ALG_MD5, SA_HASH_MODE_HMAC,
+ 256);
+}
+
+/**
+ * SHA1 and SHA2 Algorithm
+ *
+ */
int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm)
{
return crypto4xx_hash_alg_init(tfm, SA_HASH160_LEN, SA_HASH_ALG_SHA1,
SA_HASH_MODE_HASH);
}
=20
+int crypto4xx_sha1_hmac_setkey(struct crypto_ahash *hash, const u8 =
*key,
+ unsigned int keylen)
+{
+ return crypto4xx_hash_hmac_setkey(hash, key, keylen, SA_HASH160_LEN,
+ SA_HASH_ALG_SHA1, SA_HASH_MODE_HMAC,
+ 256);
+}
+
+int crypto4xx_sha2_alg_init(struct crypto_tfm *tfm)
+{
+ int ds =3D crypto_ahash_digestsize(__crypto_ahash_cast(tfm));
+ u8 ha;
+
+ switch (ds) {
+ default:
+ case 256/8:
+ ha =3D SA_HASH_ALG_SHA256;
+ break;
+ case 224/8:
+ ha =3D SA_HASH_ALG_SHA224;
+ break;
+ case 512/8:
+ ha =3D SA_HASH_ALG_SHA512;
+ break;
+ case 384/8:
+ ha =3D SA_HASH_ALG_SHA384;
+ break;
+ }
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+
+ return crypto4xx_hash_alg_init(tfm,
+ crypto4xx_sa_hash_tbl[2][ha], ha, 0);
+}
+
+int crypto4xx_sha2_hmac_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen)
+{
+ int ds =3D crypto_ahash_digestsize(hash);
+ unsigned char ha;
+
+ switch (ds) {
+ default:
+ case 256/8:
+ ha =3D SA_HASH_ALG_SHA256;
+ break;
+ case 224/8:
+ ha =3D SA_HASH_ALG_SHA224;
+ break;
+ case 512/8:
+ ha =3D SA_HASH_ALG_SHA512;
+ break;
+ case 384/8:
+ ha =3D SA_HASH_ALG_SHA384;
+ break;
+ }
+ BUG_ON(ha >=3D HASH_ALG_MAX_CNT);
+
+ return crypto4xx_hash_hmac_setkey(hash, key, keylen,
+ crypto4xx_sa_hash_tbl[2][ha],
+ ha,
+ SA_HASH_MODE_HMAC,
+ 512);
+}
+
+/**
+ * AES-XCBC-MAC Algorithm
+ *
+ */
+int crypto4xx_xcbc_digest(const unsigned char *key,
+ unsigned int keylen,
+ u8 *sa_hash, int bs)
+{
+ struct scatterlist sg[1];
+ struct crypto_blkcipher *aes_tfm =3D NULL;
+ struct blkcipher_desc desc;
+ int rc;
+ u8 *digest;
+
+ /* Load pre-computed key value into SA */
+ aes_tfm =3D crypto_alloc_blkcipher("ecb(aes)", 0, CRYPTO_ALG_ASYNC);
+ if (IS_ERR(aes_tfm)) {
+ rc =3D PTR_ERR(aes_tfm);
+ printk(KERN_ERR "failed to load transform"
+ " for ecb(aes) error %d\n", rc);
+ goto err_alg;
+ }
+ desc.tfm =3D aes_tfm;
+ desc.flags =3D 0;
+ rc =3D crypto_blkcipher_setkey(desc.tfm, key, keylen);
+ if (rc) {
+ printk(KERN_ERR "failed to load key error %d\n", rc);
+ goto err_alg;
+ }
+ digest =3D kmalloc(16, GFP_KERNEL);
+ if (digest =3D=3D NULL) {
+ rc =3D -ENOMEM;
+ goto err_alg;
+ }
+
+ memset(digest, 0x01, bs);
+ sg_init_one(&sg[0], digest, bs);
+ rc =3D crypto_blkcipher_encrypt(&desc, sg, sg, bs);
+ if (rc < 0) {
+ printk(KERN_ERR "failed to hash key error %d\n", rc);
+ goto err_alg;
+ }
+
+ crypto4xx_memcpy_le((void *) sa_hash, digest, bs);
+
+ memset(digest, 0x02, bs);
+ sg_init_one(&sg[0], digest, bs);
+ rc =3D crypto_blkcipher_encrypt(&desc, sg, sg, bs);
+ if (rc < 0) {
+ printk(KERN_ERR "failed to hash key error %d\n", rc);
+ goto err_alg;
+ }
+
+ sa_hash +=3D 32;
+ crypto4xx_memcpy_le((void *) sa_hash, digest, bs);
+
+ memset(digest, 0x03, bs);
+ sg_init_one(&sg[0], digest, bs);
+ rc =3D crypto_blkcipher_encrypt(&desc, sg, sg, bs);
+ if (rc < 0) {
+ printk(KERN_ERR "failed to hash key error %d\n", rc);
+ goto err_alg;
+ }
+
+ sa_hash +=3D 16;
+ crypto4xx_memcpy_le((void *) sa_hash, digest, bs);
+
+ crypto_free_blkcipher(aes_tfm);
+
+ return 0;
+err_alg:
+ if (aes_tfm)
+ crypto_free_blkcipher(aes_tfm);
+ return rc;
+}
+
+int crypto4xx_xcbc_setkey(struct crypto_ahash *hash,
+ const u8 *key,
+ unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ahash_tfm(hash);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ int bs =3D crypto_tfm_alg_blocksize(tfm);
+ struct dynamic_sa_ctl *sa;
+ u8 *sa_hash;
+ int rc =3D 0;
+
+ if (keylen !=3D 128/8) {
+ crypto_ahash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ /* Create SA */
+ rc =3D crypto4xx_alloc_sa(ctx, SA_AES128_XCBC_MAC_LEN);
+ if (rc)
+ return rc;
=20
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ rc =3D -ENOMEM;
+ goto err;
+ }
+ }
+
+ ctx->direction =3D DIR_INBOUND;
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ /*
+ * Setup hash algorithm and hash mode
+ */
+ sa->sa_contents =3D SA_AES128_XCBC_MAC_CONTENTS;
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
+ SA_NO_HEADER_PROC,
+ SA_HASH_ALG_AES_XCBC_MAC_128,
+ SA_CIPHER_ALG_NULL, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_HASH,
+ DIR_INBOUND);
+ set_dynamic_sa_command_1(sa, 0, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB,
+ SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+ crypto4xx_memcpy_le(ctx->sa_in + get_dynamic_sa_offset_key_field(ctx),
+ key, keylen);
+
+ memcpy((void *)(ctx->sa_in +
+ get_dynamic_sa_offset_state_ptr_field(ctx)),
+ (void *)&ctx->state_record_dma_addr, 4);
+ ctx->is_hash =3D 1;
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ sa_hash =3D (u8 *)(&(((struct dynamic_sa_aes128_xcbc_mac *)
+ ctx->sa_in)->inner_digest));
+ rc =3D crypto4xx_xcbc_digest(key, keylen, sa_hash, bs);
+ if (rc) {
+ printk(KERN_ERR "XCBC Digest Calculation Failed %d\n", rc);
+ goto err;
+ }
+
+ ctx->is_hash =3D 1;
+ ctx->hash_final =3D 1;
+ ctx->pd_ctl =3D 0x11;
+
+ ctx->direction =3D DIR_INBOUND;
+
+ memcpy(ctx->sa_out, ctx->sa_in, ctx->sa_len * 4);
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_out;
+ sa->sa_command_0.bf.dir =3D DIR_OUTBOUND;
+
+ return 0;
+err:
+ crypto4xx_free_sa(ctx);
+ return rc;
+}
+
+/**
+ * Kasumi F9 - Hash Algorithms
+ *
+ */
+int crypto4xx_kasumi_f9_setkey(struct crypto_ahash *hash,
+ const u8 *key, unsigned int keylen)
+{
+ struct crypto_tfm *tfm =3D crypto_ahash_tfm(hash);
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(tfm);
+ int rc;
+ struct dynamic_sa_ctl *sa;
+
+ if (keylen !=3D 16) {
+ crypto_ahash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+
+ /* Create SA */
+ if (ctx->sa_in_dma_addr || ctx->sa_out_dma_addr)
+ crypto4xx_free_sa(ctx);
+
+ rc =3D crypto4xx_alloc_sa(ctx, SA_KASUMI_F9_LEN);
+ if (rc)
+ return rc;
+
+ if (ctx->state_record_dma_addr =3D=3D 0) {
+ rc =3D crypto4xx_alloc_state_record(ctx);
+ if (rc) {
+ crypto4xx_free_sa(ctx);
+ return rc;
+ }
+ }
+
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+ /*
+ * Setup hash algorithm and hash mode
+ */
+ set_dynamic_sa_command_0(sa, SA_SAVE_HASH, SA_NOT_SAVE_IV,
+ SA_NOT_LOAD_HASH, SA_LOAD_IV_FROM_SA,
+ SA_NO_HEADER_PROC, SA_HASH_ALG_KASUMI_f9,
+ SA_CIPHER_ALG_NULL, SA_PAD_TYPE_ZERO,
+ SA_OP_GROUP_BASIC, SA_OPCODE_HASH,
+ DIR_INBOUND);
+ set_dynamic_sa_command_1(sa, 0, SA_HASH_MODE_HASH,
+ CRYPTO_FEEDBACK_MODE_NO_FB, SA_EXTENDED_SN_OFF,
+ SA_SEQ_MASK_OFF, SA_MC_ENABLE,
+ SA_NOT_COPY_PAD, SA_NOT_COPY_PAYLOAD,
+ SA_NOT_COPY_HDR);
+ sa->sa_contents =3D SA_KASUMI_F9_CONTENTS;
+
+ ctx->direction =3D DIR_INBOUND;
+ memcpy((void *)(ctx->sa_in +
+ get_dynamic_sa_offset_state_ptr_field(ctx)),
+ (void *)&ctx->state_record_dma_addr, 4);
+
+ crypto4xx_memcpy_le(ctx->sa_in +
+ get_dynamic_sa_offset_inner_digest(ctx), key, keylen);
+ ctx->offset_to_sr_ptr =3D get_dynamic_sa_offset_state_ptr_field(ctx);
+ ctx->is_hash =3D 1;
+ ctx->hash_final =3D 1;
+ ctx->pd_ctl =3D 0x11;
+ ctx->bypass =3D 4;
+
+ return 0;
+}
+
+int crypto4xx_kasumi_f9_digest(struct ahash_request *req)
+{
+ struct crypto4xx_ctx *ctx =3D crypto_tfm_ctx(req->base.tfm);
+ struct scatterlist *src =3D req->src;
+ struct dynamic_sa_ctl *sa;
+ dma_addr_t addr;
+
+ /*
+ * We have prepended count/fresh/direction/reserv total
+ * 16byte before the plaintext
+ * so, need to modify the length.
+ * We doing so, to make use of tcrypt.c's hash_test.
+ */
+ sa =3D (struct dynamic_sa_ctl *) ctx->sa_in;
+
+ addr =3D dma_map_page(NULL, sg_page(src), src->offset,
+ src->length, DMA_TO_DEVICE);
+ crypto4xx_memcpy_le((void *)sa +
+ get_dynamic_sa_offset_outer_digest(ctx),
+ phys_to_virt(addr), 12);
+
+ return crypto4xx_build_pd(&req->base, ctx, req->src,
+ (struct scatterlist *)req->result,
+ req->nbytes, NULL, 0, NULL, 0);
+}
--=20
1.5.5
^ permalink raw reply related
* Re: [PATCH V2 2/2] mtd/maps/mtd-ram: add an of-platform driver
From: Albrecht Dreß @ 2009-06-15 17:43 UTC (permalink / raw)
To: Wolfram Sang
Cc: linuxppc-dev, devicetree-discuss, linux-mtd, David Woodhouse,
Ben Dooks
In-Reply-To: <1244203514-12516-3-git-send-email-w.sang@pengutronix.de>
[-- Attachment #1: Type: text/plain, Size: 608 bytes --]
Am 05.06.09 14:05 schrieb(en) Wolfram Sang:
> Create an of-aware driver using the now exported generic functions
> from plat-ram.c. Also add the documentation for the binding.
> Partitions are not yet supported. Tested on a phyCORE-MPC5200B-IO.
Dumb question: what is the current status of this patch? I ask because
I re-wrote my '5200 16-bit Local Plus Bus patch' according to Grant's
suggestions, and I believe of_ram_probe() of your patch is the right
place to check if it's attached to "fsl,mpc5200-lpb", and to change the
write cb if the bankwidth equals 2.
Thanks, Albrecht.
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc: Add configurable -Werror for arch/powerpc
From: Benjamin Herrenschmidt @ 2009-06-15 21:23 UTC (permalink / raw)
To: michael; +Cc: linuxppc-dev list
In-Reply-To: <1245069362.8735.15.camel@concordia>
> Yeah that occured to me, someone with a chrp machine would need to test
> it, do we have one?
Yup, I think we do. I'll check that when I'm in the office.
> > We can have a closer look tomorrow. In any case, stack alloc for that is
> > indeed fishy.
>
> The obvious patch to make it static doesn't fly because it's called on
> every cpu via a timer, so it needs to be a per-cpu at least I think. Or
> borrow the pseries trick of calling it on each cpu in succession, or
> just borrow the pseries code.
Right.
Cheers,
Ben.
^ permalink raw reply
* Re: [OOPS] hugetlbfs tests with 2.6.30-rc8-git1
From: Benjamin Herrenschmidt @ 2009-06-15 21:26 UTC (permalink / raw)
To: Sachin Sant; +Cc: Mel Gorman, linuxppc-dev
In-Reply-To: <4A3645EE.5060103@in.ibm.com>
On Mon, 2009-06-15 at 18:30 +0530, Sachin Sant wrote:
> The corresponding C code is :
>
> 278: 2f 80 00 00 cmpwi cr7,r0,0
> } else {
> vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
> ssize = mmu_kernel_ssize;
> }
> vaddr = hpt_va(addr, vsid, ssize);
> rpte = __real_pte(__pte(pte), ptep);
That's interesting... __real_pte() is used to reconstruct
a PTE two halves but maybe our huge pages page tables don't have
the second half ! In which case we are just going to peek into
la-la-land. I'm also worried by the negative offset since the second
halves are at +0x8000 iirc, unless it flipped the pointers around but
that would be strange....
I'll have a look later today.
Cheers,
Ben.
> 27c: eb 89 80 00 ld r28,-32768(r9)
> ^^^^ %pc points to the above line. ^^^^^
> * Check if we have an active batch on this CPU. If not, just
> * flush now and return. For now, we don global invalidates
> * in that case, might be worth testing the mm cpu mask though
> * and decide to use local invalidates instead...
>
> I have attached the objdump o/p for tlb_hash64.o.
>
> I could not recreate this issue with git8 kernel
> (45e3e1935e2857c54783291107d33323b3ef33c8).
>
> Thanks
> -Sachin
>
> plain text document attachment (tlb_hash64_objlist)
> arch/powerpc/mm/tlb_hash64.o: file format elf64-powerpc
>
>
> Disassembly of section .text:
>
> 0000000000000000 <.__flush_tlb_pending>:
> * in a batch.
> *
> * Must be called from within some kind of spinlock/non-preempt region...
> */
> void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
> {
> 0: fb e1 ff f8 std r31,-8(r1)
> 4: 7c 08 02 a6 mflr r0
> 8: f8 01 00 10 std r0,16(r1)
> extern const unsigned long
> cpu_bit_bitmap[BITS_PER_LONG+1][BITS_TO_LONGS(NR_CPUS)];
>
> static inline const struct cpumask *get_cpu_mask(unsigned int cpu)
> {
> const unsigned long *p = cpu_bit_bitmap[1 + cpu % BITS_PER_LONG];
> c: e8 02 00 00 ld r0,0(r2)
> 10: 7c 7f 1b 78 mr r31,r3
> 14: fb c1 ff f0 std r30,-16(r1)
> const unsigned long *src2, int nbits)
> {
> if (small_const_nbits(nbits))
> return ! ((*src1 ^ *src2) & BITMAP_LAST_WORD_MASK(nbits));
> else
> return __bitmap_equal(src1, src2, nbits);
> 18: 38 a0 04 00 li r5,1024
> 1c: f8 21 ff 81 stdu r1,-128(r1)
> const struct cpumask *tmp;
> int i, local = 0;
>
> i = batch->index;
> tmp = cpumask_of(smp_processor_id());
> 20: a0 8d 00 0a lhz r4,10(r13)
> 24: e8 63 00 10 ld r3,16(r3)
> 28: 78 89 06 a0 clrldi r9,r4,58
> 2c: 78 84 d1 82 rldicl r4,r4,58,6
> 30: 39 29 00 01 addi r9,r9,1
> 34: 78 84 1f 24 rldicr r4,r4,3,60
> 38: 79 29 3e 24 rldicr r9,r9,7,56
> 3c: 38 63 03 10 addi r3,r3,784
> 40: 7c 00 4a 14 add r0,r0,r9
> void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
> {
> const struct cpumask *tmp;
> int i, local = 0;
>
> i = batch->index;
> 44: eb df 00 0e lwa r30,12(r31)
> 48: 7c 84 00 50 subf r4,r4,r0
> 4c: 48 00 00 01 bl 4c <.__flush_tlb_pending+0x4c>
> 50: 60 00 00 00 nop
> 54: 7c 69 fe 70 srawi r9,r3,31
> tmp = cpumask_of(smp_processor_id());
> if (cpumask_equal(mm_cpumask(batch->mm), tmp))
> local = 1;
> if (i == 1)
> 58: 2f 9e 00 01 cmpwi cr7,r30,1
> 5c: 7d 20 1a 78 xor r0,r9,r3
> 60: 7c 00 48 50 subf r0,r0,r9
> 64: 54 00 0f fe rlwinm r0,r0,1,31,31
> 68: 7c 04 07 b4 extsw r4,r0
> 6c: 40 9e 00 28 bne- cr7,94 <.__flush_tlb_pending+0x94>
> flush_hash_page(batch->vaddr[0], batch->pte[0],
> 70: 7c 88 23 78 mr r8,r4
> 74: e8 7f 0c 18 ld r3,3096(r31)
> 78: e8 df 12 1a lwa r6,4632(r31)
> 7c: e8 ff 12 1e lwa r7,4636(r31)
> 80: e8 9f 00 18 ld r4,24(r31)
> 84: e8 bf 00 20 ld r5,32(r31)
> 88: 48 00 00 01 bl 88 <.__flush_tlb_pending+0x88>
> 8c: 60 00 00 00 nop
> 90: 48 00 00 10 b a0 <.__flush_tlb_pending+0xa0>
> batch->psize, batch->ssize, local);
> else
> flush_hash_range(i, local);
> 94: 7f c3 f3 78 mr r3,r30
> 98: 48 00 00 01 bl 98 <.__flush_tlb_pending+0x98>
> 9c: 60 00 00 00 nop
> batch->index = 0;
> }
> a0: 38 21 00 80 addi r1,r1,128
> if (i == 1)
> flush_hash_page(batch->vaddr[0], batch->pte[0],
> batch->psize, batch->ssize, local);
> else
> flush_hash_range(i, local);
> batch->index = 0;
> a4: 38 00 00 00 li r0,0
> a8: f8 1f 00 08 std r0,8(r31)
> }
> ac: e8 01 00 10 ld r0,16(r1)
> b0: eb c1 ff f0 ld r30,-16(r1)
> b4: 7c 08 03 a6 mtlr r0
> b8: eb e1 ff f8 ld r31,-8(r1)
> bc: 4e 80 00 20 blr
>
> 00000000000000c0 <.hpte_need_flush>:
> *
> * Must be called from within some kind of spinlock/non-preempt region...
> */
> void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
> pte_t *ptep, unsigned long pte, int huge)
> {
> c0: fa c1 ff b0 std r22,-80(r1)
> c4: 7c 08 02 a6 mflr r0
> c8: f8 01 00 10 std r0,16(r1)
> * NOTE: when using special 64K mappings in 4K environment like
> * for SPEs, we obtain the page size from the slice, which thus
> * must still exist (and thus the VMA not reused) at the time
> * of this call
> */
> if (huge) {
> cc: 2f a7 00 00 cmpdi cr7,r7,0
> *
> * Must be called from within some kind of spinlock/non-preempt region...
> */
> void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
> pte_t *ptep, unsigned long pte, int huge)
> {
> d0: fb 21 ff c8 std r25,-56(r1)
> #else
> BUG();
> psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
> #endif
> } else
> psize = pte_pagesize_index(mm, addr, pte);
> d4: 6c c0 10 00 xoris r0,r6,4096
> *
> * Must be called from within some kind of spinlock/non-preempt region...
> */
> void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
> pte_t *ptep, unsigned long pte, int huge)
> {
> d8: fb 41 ff d0 std r26,-48(r1)
> dc: 7c d9 33 78 mr r25,r6
> e0: fb 61 ff d8 std r27,-40(r1)
> e4: 7c b6 2b 78 mr r22,r5
> e8: fb 81 ff e0 std r28,-32(r1)
> struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
> ec: eb 82 00 08 ld r28,8(r2)
> *
> * Must be called from within some kind of spinlock/non-preempt region...
> */
> void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
> pte_t *ptep, unsigned long pte, int huge)
> {
> f0: fb c1 ff f0 std r30,-16(r1)
> #else
> BUG();
> psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
> #endif
> } else
> psize = pte_pagesize_index(mm, addr, pte);
> f4: 78 1b 27 e2 rldicl r27,r0,36,63
> *
> * Must be called from within some kind of spinlock/non-preempt region...
> */
> void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
> pte_t *ptep, unsigned long pte, int huge)
> {
> f8: fb e1 ff f8 std r31,-8(r1)
> fc: 7c 7a 1b 78 mr r26,r3
> 100: fa e1 ff b8 std r23,-72(r1)
> i = batch->index;
>
> /* We mask the address for the base page size. Huge pages will
> * have applied their own masking already
> */
> addr &= PAGE_MASK;
> 104: 78 9f 03 e4 rldicr r31,r4,0,47
> *
> * Must be called from within some kind of spinlock/non-preempt region...
> */
> void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
> pte_t *ptep, unsigned long pte, int huge)
> {
> 108: fb 01 ff c0 std r24,-64(r1)
> 10c: fb a1 ff e8 std r29,-24(r1)
> 110: f8 21 ff 41 stdu r1,-192(r1)
> struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
> 114: ea ed 00 40 ld r23,64(r13)
> 118: 7f dc ba 14 add r30,r28,r23
> unsigned int psize;
> int ssize;
> real_pte_t rpte;
> int i;
>
> i = batch->index;
> 11c: eb 1e 00 08 ld r24,8(r30)
> * NOTE: when using special 64K mappings in 4K environment like
> * for SPEs, we obtain the page size from the slice, which thus
> * must still exist (and thus the VMA not reused) at the time
> * of this call
> */
> if (huge) {
> 120: 41 9e 00 14 beq- cr7,134 <.hpte_need_flush+0x74>
> #ifdef CONFIG_HUGETLB_PAGE
> psize = get_slice_psize(mm, addr);;
> 124: 7f e4 fb 78 mr r4,r31
> 128: 48 00 00 01 bl 128 <.hpte_need_flush+0x68>
> 12c: 60 00 00 00 nop
> 130: 7c 7b 1b 78 mr r27,r3
> #endif
> } else
> psize = pte_pagesize_index(mm, addr, pte);
>
> /* Build full vaddr */
> if (!is_kernel_addr(addr)) {
> 134: e8 02 00 10 ld r0,16(r2)
> 138: 7f bf 00 40 cmpld cr7,r31,r0
> 13c: 41 9d 00 a8 bgt- cr7,1e4 <.hpte_need_flush+0x124>
>
> /* Returns the segment size indicator for a user address */
> static inline int user_segment_size(unsigned long addr)
> {
> /* Use 1T segments if possible for addresses >= 1T */
> if (addr >= (1UL << SID_SHIFT_1T))
> 140: 38 00 ff ff li r0,-1
> 144: 3b a0 00 00 li r29,0
> 148: 78 00 06 00 clrldi r0,r0,24
> 14c: 7f bf 00 40 cmpld cr7,r31,r0
> 150: 40 9d 00 0c ble- cr7,15c <.hpte_need_flush+0x9c>
> return mmu_highuser_ssize;
> 154: e9 22 00 18 ld r9,24(r2)
> 158: eb a9 00 02 lwa r29,0(r9)
>
> /* This is only valid for user addresses (which are below 2^44) */
> static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
> int ssize)
> {
> if (ssize == MMU_SEGSIZE_256M)
> 15c: 2f bd 00 00 cmpdi cr7,r29,0
> ssize = user_segment_size(addr);
> vsid = get_vsid(mm->context.id, addr, ssize);
> 160: e9 7a 03 90 ld r11,912(r26)
> 164: 40 9e 00 3c bne- cr7,1a0 <.hpte_need_flush+0xe0>
> return vsid_scramble((context << USER_ESID_BITS)
> 168: 79 6b 83 e4 rldicr r11,r11,16,47
> 16c: 7b e0 27 02 rldicl r0,r31,36,28
> 170: 3d 20 0b f6 lis r9,3062
> 174: 7c 00 5b 78 or r0,r0,r11
> 178: 61 29 e6 1b ori r9,r9,58907
> 17c: 7c 00 49 d2 mulld r0,r0,r9
> | (ea >> SID_SHIFT), 256M);
> 180: 78 09 07 00 clrldi r9,r0,28
> 184: 78 00 e1 20 rldicl r0,r0,28,36
> 188: 7d 29 02 14 add r9,r9,r0
> 18c: 38 09 00 01 addi r0,r9,1
> 190: 78 00 e1 20 rldicl r0,r0,28,36
> 194: 7c 00 4a 14 add r0,r0,r9
> 198: 78 09 07 00 clrldi r9,r0,28
> 19c: 48 00 00 38 b 1d4 <.hpte_need_flush+0x114>
> return vsid_scramble((context << USER_ESID_BITS_1T)
> 1a0: 79 6b 26 e4 rldicr r11,r11,4,59
> 1a4: 7b e0 c2 20 rldicl r0,r31,24,40
> 1a8: 3d 20 00 bf lis r9,191
> 1ac: 7c 00 5b 78 or r0,r0,r11
> 1b0: 61 29 50 d9 ori r9,r9,20697
> 1b4: 7c 00 49 d2 mulld r0,r0,r9
> | (ea >> SID_SHIFT_1T), 1T);
> 1b8: 78 09 02 20 clrldi r9,r0,40
> 1bc: 78 00 46 02 rldicl r0,r0,40,24
> 1c0: 7d 29 02 14 add r9,r9,r0
> 1c4: 38 09 00 01 addi r0,r9,1
> 1c8: 78 00 46 02 rldicl r0,r0,40,24
> 1cc: 7c 00 4a 14 add r0,r0,r9
> 1d0: 78 09 02 20 clrldi r9,r0,40
> WARN_ON(vsid == 0);
> 1d4: 7d 20 00 74 cntlzd r0,r9
> 1d8: 78 00 d1 82 rldicl r0,r0,58,6
> 1dc: 0b 00 00 00 tdnei r0,0
> 1e0: 48 00 00 70 b 250 <.hpte_need_flush+0x190>
> } else {
> vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
> 1e4: e9 22 00 20 ld r9,32(r2)
> 1e8: eb a9 00 02 lwa r29,0(r9)
> #endif /* 1 */
>
> /* This is only valid for addresses >= PAGE_OFFSET */
> static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
> {
> if (ssize == MMU_SEGSIZE_256M)
> 1ec: 2f bd 00 00 cmpdi cr7,r29,0
> 1f0: 40 9e 00 34 bne- cr7,224 <.hpte_need_flush+0x164>
> return vsid_scramble(ea >> SID_SHIFT, 256M);
> 1f4: 3d 20 0b f6 lis r9,3062
> 1f8: 7b e0 27 02 rldicl r0,r31,36,28
> 1fc: 61 29 e6 1b ori r9,r9,58907
> 200: 7c 00 49 d2 mulld r0,r0,r9
> 204: 78 09 07 00 clrldi r9,r0,28
> 208: 78 00 e1 20 rldicl r0,r0,28,36
> 20c: 7d 29 02 14 add r9,r9,r0
> 210: 38 09 00 01 addi r0,r9,1
> 214: 78 00 e1 20 rldicl r0,r0,28,36
> 218: 7c 00 4a 14 add r0,r0,r9
> 21c: 78 09 07 00 clrldi r9,r0,28
> 220: 48 00 00 38 b 258 <.hpte_need_flush+0x198>
> return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
> 224: 3d 20 00 bf lis r9,191
> 228: 7b e0 c2 20 rldicl r0,r31,24,40
> 22c: 61 29 50 d9 ori r9,r9,20697
> 230: 7c 00 49 d2 mulld r0,r0,r9
> 234: 78 09 02 20 clrldi r9,r0,40
> 238: 78 00 46 02 rldicl r0,r0,40,24
> 23c: 7d 29 02 14 add r9,r9,r0
> 240: 38 09 00 01 addi r0,r9,1
> 244: 78 00 46 02 rldicl r0,r0,40,24
> 248: 7c 00 4a 14 add r0,r0,r9
> 24c: 78 09 02 20 clrldi r9,r0,40
> * Build a VA given VSID, EA and segment size
> */
> static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
> int ssize)
> {
> if (ssize == MMU_SEGSIZE_256M)
> 250: 2f bd 00 00 cmpdi cr7,r29,0
> 254: 40 9e 00 10 bne- cr7,264 <.hpte_need_flush+0x1a4>
> return (vsid << 28) | (ea & 0xfffffffUL);
> 258: 79 29 e0 e4 rldicr r9,r9,28,35
> 25c: 7b e0 01 20 clrldi r0,r31,36
> 260: 48 00 00 0c b 26c <.hpte_need_flush+0x1ac>
> return (vsid << 40) | (ea & 0xffffffffffUL);
> 264: 79 29 45 c6 rldicr r9,r9,40,23
> 268: 7b e0 06 00 clrldi r0,r31,24
> 26c: 7d 3f 03 78 or r31,r9,r0
> * Check if we have an active batch on this CPU. If not, just
> * flush now and return. For now, we don global invalidates
> * in that case, might be worth testing the mm cpu mask though
> * and decide to use local invalidates instead...
> */
> if (!batch->active) {
> 270: 7c 1c b8 2e lwzx r0,r28,r23
> } else {
> vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
> ssize = mmu_kernel_ssize;
> }
> vaddr = hpt_va(addr, vsid, ssize);
> rpte = __real_pte(__pte(pte), ptep);
> 274: 3d 36 00 01 addis r9,r22,1
> * Check if we have an active batch on this CPU. If not, just
> * flush now and return. For now, we don global invalidates
> * in that case, might be worth testing the mm cpu mask though
> * and decide to use local invalidates instead...
> */
> if (!batch->active) {
> 278: 2f 80 00 00 cmpwi cr7,r0,0
> } else {
> vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
> ssize = mmu_kernel_ssize;
> }
> vaddr = hpt_va(addr, vsid, ssize);
> rpte = __real_pte(__pte(pte), ptep);
> 27c: eb 89 80 00 ld r28,-32768(r9)
> * Check if we have an active batch on this CPU. If not, just
> * flush now and return. For now, we don global invalidates
> * in that case, might be worth testing the mm cpu mask though
> * and decide to use local invalidates instead...
> */
> if (!batch->active) {
> 280: 40 9e 00 28 bne- cr7,2a8 <.hpte_need_flush+0x1e8>
> flush_hash_page(vaddr, rpte, psize, ssize, 0);
> 284: 7f e3 fb 78 mr r3,r31
> 288: 7f 24 cb 78 mr r4,r25
> 28c: 7f 85 e3 78 mr r5,r28
> 290: 7f 66 07 b4 extsw r6,r27
> 294: 7f a7 eb 78 mr r7,r29
> 298: 39 00 00 00 li r8,0
> 29c: 48 00 00 01 bl 29c <.hpte_need_flush+0x1dc>
> 2a0: 60 00 00 00 nop
> 2a4: 48 00 00 bc b 360 <.hpte_need_flush+0x2a0>
> * will change mid stream.
> *
> * We also need to ensure only one page size is present in a given
> * batch
> */
> if (i != 0 && (mm != batch->mm || batch->psize != psize ||
> 2a8: 7f 0b 07 b5 extsw. r11,r24
> 2ac: 41 82 00 30 beq- 2dc <.hpte_need_flush+0x21c>
> 2b0: e8 1e 00 10 ld r0,16(r30)
> 2b4: 7f ba 00 00 cmpd cr7,r26,r0
> 2b8: 40 9e 00 1c bne- cr7,2d4 <.hpte_need_flush+0x214>
> 2bc: 80 1e 12 18 lwz r0,4632(r30)
> 2c0: 7f 80 d8 00 cmpw cr7,r0,r27
> 2c4: 40 9e 00 10 bne- cr7,2d4 <.hpte_need_flush+0x214>
> 2c8: 80 1e 12 1c lwz r0,4636(r30)
> 2cc: 7f 80 e8 00 cmpw cr7,r0,r29
> 2d0: 41 9e 00 1c beq- cr7,2ec <.hpte_need_flush+0x22c>
> batch->ssize != ssize)) {
> __flush_tlb_pending(batch);
> 2d4: 7f c3 f3 78 mr r3,r30
> 2d8: 48 00 00 01 bl 2d8 <.hpte_need_flush+0x218>
> i = 0;
> }
> if (i == 0) {
> batch->mm = mm;
> batch->psize = psize;
> batch->ssize = ssize;
> 2dc: 39 60 00 00 li r11,0
> batch->ssize != ssize)) {
> __flush_tlb_pending(batch);
> i = 0;
> }
> if (i == 0) {
> batch->mm = mm;
> 2e0: fb 5e 00 10 std r26,16(r30)
> batch->psize = psize;
> 2e4: 93 7e 12 18 stw r27,4632(r30)
> batch->ssize = ssize;
> 2e8: 93 be 12 1c stw r29,4636(r30)
> }
> batch->pte[i] = rpte;
> batch->vaddr[i] = vaddr;
> batch->index = ++i;
> 2ec: 38 0b 00 01 addi r0,r11,1
> if (i == 0) {
> batch->mm = mm;
> batch->psize = psize;
> batch->ssize = ssize;
> }
> batch->pte[i] = rpte;
> 2f0: 39 2b 00 01 addi r9,r11,1
> batch->vaddr[i] = vaddr;
> 2f4: 39 6b 01 82 addi r11,r11,386
> batch->index = ++i;
> 2f8: 7c 00 07 b4 extsw r0,r0
> if (i == 0) {
> batch->mm = mm;
> batch->psize = psize;
> batch->ssize = ssize;
> }
> batch->pte[i] = rpte;
> 2fc: 79 29 26 e4 rldicr r9,r9,4,59
> batch->vaddr[i] = vaddr;
> 300: 79 6b 1f 24 rldicr r11,r11,3,60
> if (i == 0) {
> batch->mm = mm;
> batch->psize = psize;
> batch->ssize = ssize;
> }
> batch->pte[i] = rpte;
> 304: 7d 3e 4a 14 add r9,r30,r9
> batch->vaddr[i] = vaddr;
> 308: 7d 7e 5a 14 add r11,r30,r11
> if (i == 0) {
> batch->mm = mm;
> batch->psize = psize;
> batch->ssize = ssize;
> }
> batch->pte[i] = rpte;
> 30c: fb 29 00 08 std r25,8(r9)
> batch->vaddr[i] = vaddr;
> batch->index = ++i;
> if (i >= PPC64_TLB_BATCH_NR)
> 310: 2f 80 00 bf cmpwi cr7,r0,191
> if (i == 0) {
> batch->mm = mm;
> batch->psize = psize;
> batch->ssize = ssize;
> }
> batch->pte[i] = rpte;
> 314: fb 89 00 10 std r28,16(r9)
> batch->vaddr[i] = vaddr;
> 318: fb eb 00 08 std r31,8(r11)
> batch->index = ++i;
> 31c: f8 1e 00 08 std r0,8(r30)
> if (i >= PPC64_TLB_BATCH_NR)
> 320: 40 9d 00 40 ble- cr7,360 <.hpte_need_flush+0x2a0>
> __flush_tlb_pending(batch);
> }
> 324: 38 21 00 c0 addi r1,r1,192
> }
> batch->pte[i] = rpte;
> batch->vaddr[i] = vaddr;
> batch->index = ++i;
> if (i >= PPC64_TLB_BATCH_NR)
> __flush_tlb_pending(batch);
> 328: 7f c3 f3 78 mr r3,r30
> }
> 32c: e8 01 00 10 ld r0,16(r1)
> 330: ea c1 ff b0 ld r22,-80(r1)
> 334: 7c 08 03 a6 mtlr r0
> 338: ea e1 ff b8 ld r23,-72(r1)
> 33c: eb 01 ff c0 ld r24,-64(r1)
> 340: eb 21 ff c8 ld r25,-56(r1)
> 344: eb 41 ff d0 ld r26,-48(r1)
> 348: eb 61 ff d8 ld r27,-40(r1)
> 34c: eb 81 ff e0 ld r28,-32(r1)
> 350: eb a1 ff e8 ld r29,-24(r1)
> 354: eb c1 ff f0 ld r30,-16(r1)
> 358: eb e1 ff f8 ld r31,-8(r1)
> }
> batch->pte[i] = rpte;
> batch->vaddr[i] = vaddr;
> batch->index = ++i;
> if (i >= PPC64_TLB_BATCH_NR)
> __flush_tlb_pending(batch);
> 35c: 48 00 00 00 b 35c <.hpte_need_flush+0x29c>
> }
> 360: 38 21 00 c0 addi r1,r1,192
> 364: e8 01 00 10 ld r0,16(r1)
> 368: ea c1 ff b0 ld r22,-80(r1)
> 36c: 7c 08 03 a6 mtlr r0
> 370: ea e1 ff b8 ld r23,-72(r1)
> 374: eb 01 ff c0 ld r24,-64(r1)
> 378: eb 21 ff c8 ld r25,-56(r1)
> 37c: eb 41 ff d0 ld r26,-48(r1)
> 380: eb 61 ff d8 ld r27,-40(r1)
> 384: eb 81 ff e0 ld r28,-32(r1)
> 388: eb a1 ff e8 ld r29,-24(r1)
> 38c: eb c1 ff f0 ld r30,-16(r1)
> 390: eb e1 ff f8 ld r31,-8(r1)
> 394: 4e 80 00 20 blr
>
> 0000000000000398 <.__flush_hash_table_range>:
> */
> #ifdef CONFIG_HOTPLUG
>
> void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
> unsigned long end)
> {
> 398: fb 81 ff e0 std r28,-32(r1)
> 39c: 7c 08 02 a6 mflr r0
> 3a0: fb c1 ff f0 std r30,-16(r1)
> unsigned long flags;
>
> start = _ALIGN_DOWN(start, PAGE_SIZE);
> end = _ALIGN_UP(end, PAGE_SIZE);
> 3a4: 3c a5 00 01 addis r5,r5,1
> */
> #ifdef CONFIG_HOTPLUG
>
> void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
> unsigned long end)
> {
> 3a8: f8 01 00 10 std r0,16(r1)
> 3ac: 7c 7e 1b 78 mr r30,r3
> 3b0: fb a1 ff e8 std r29,-24(r1)
> unsigned long flags;
>
> start = _ALIGN_DOWN(start, PAGE_SIZE);
> end = _ALIGN_UP(end, PAGE_SIZE);
> 3b4: 38 a5 ff ff addi r5,r5,-1
> */
> #ifdef CONFIG_HOTPLUG
>
> void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
> unsigned long end)
> {
> 3b8: fb e1 ff f8 std r31,-8(r1)
> 3bc: f8 21 ff 71 stdu r1,-144(r1)
> unsigned long flags;
>
> start = _ALIGN_DOWN(start, PAGE_SIZE);
> end = _ALIGN_UP(end, PAGE_SIZE);
> 3c0: 78 bc 03 e4 rldicr r28,r5,0,47
>
> BUG_ON(!mm->pgd);
> 3c4: e8 03 00 48 ld r0,72(r3)
> 3c8: 7c 00 00 74 cntlzd r0,r0
> 3cc: 78 00 d1 82 rldicl r0,r0,58,6
> 3d0: 0b 00 00 00 tdnei r0,0
> void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
> unsigned long end)
> {
> unsigned long flags;
>
> start = _ALIGN_DOWN(start, PAGE_SIZE);
> 3d4: 78 9f 03 e4 rldicr r31,r4,0,47
>
> static inline unsigned long raw_local_irq_disable(void)
> {
> unsigned long flags, zero;
>
> __asm__ __volatile__("li %1,0; lbz %0,%2(13); stb %1,%2(13)"
> 3d8: 38 00 00 00 li r0,0
> 3dc: 8b ad 01 da lbz r29,474(r13)
> 3e0: 98 0d 01 da stb r0,474(r13)
>
> static inline void arch_enter_lazy_mmu_mode(void)
> {
> struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
>
> batch->active = 1;
> 3e4: 38 00 00 01 li r0,1
> 3e8: e9 6d 00 40 ld r11,64(r13)
>
> #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
>
> static inline void arch_enter_lazy_mmu_mode(void)
> {
> struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
> 3ec: e9 22 00 08 ld r9,8(r2)
>
> batch->active = 1;
> 3f0: 7c 09 59 2e stwx r0,r9,r11
> 3f4: 48 00 00 58 b 44c <.__flush_hash_table_range+0xb4>
> pte_t *pt = NULL;
>
> pg = pgdir + pgd_index(ea);
> if (!pgd_none(*pg)) {
> pu = pud_offset(pg, ea);
> if (!pud_none(*pu)) {
> 3f8: e9 3e 00 48 ld r9,72(r30)
> 3fc: 7c 09 00 2a ldx r0,r9,r0
> 400: 2f a0 00 00 cmpdi cr7,r0,0
> pm = pmd_offset(pu, ea);
> if (pmd_present(*pm))
> 404: 78 09 05 a4 rldicr r9,r0,0,54
> pte_t *pt = NULL;
>
> pg = pgdir + pgd_index(ea);
> if (!pgd_none(*pg)) {
> pu = pud_offset(pg, ea);
> if (!pud_none(*pu)) {
> 408: 41 9e 00 40 beq- cr7,448 <.__flush_hash_table_range+0xb0>
> pm = pmd_offset(pu, ea);
> if (pmd_present(*pm))
> 40c: 7d 2b 48 2a ldx r9,r11,r9
> pt = pte_offset_kernel(pm, ea);
> 410: 7b e0 85 22 rldicl r0,r31,48,52
> pg = pgdir + pgd_index(ea);
> if (!pgd_none(*pg)) {
> pu = pud_offset(pg, ea);
> if (!pud_none(*pu)) {
> pm = pmd_offset(pu, ea);
> if (pmd_present(*pm))
> 414: 2f a9 00 00 cmpdi cr7,r9,0
> pt = pte_offset_kernel(pm, ea);
> 418: 78 0b 1f 24 rldicr r11,r0,3,60
> 41c: 79 26 05 a4 rldicr r6,r9,0,54
> arch_enter_lazy_mmu_mode();
> for (; start < end; start += PAGE_SIZE) {
> pte_t *ptep = find_linux_pte(mm->pgd, start);
> unsigned long pte;
>
> if (ptep == NULL)
> 420: 7c a6 5a 15 add. r5,r6,r11
> pg = pgdir + pgd_index(ea);
> if (!pgd_none(*pg)) {
> pu = pud_offset(pg, ea);
> if (!pud_none(*pu)) {
> pm = pmd_offset(pu, ea);
> if (pmd_present(*pm))
> 424: 41 9e 00 24 beq- cr7,448 <.__flush_hash_table_range+0xb0>
> 428: 41 c2 00 20 beq- 448 <.__flush_hash_table_range+0xb0>
> continue;
> pte = pte_val(*ptep);
> 42c: 7c c6 58 2a ldx r6,r6,r11
> if (!(pte & _PAGE_HASHPTE))
> 430: 54 c0 01 27 rlwinm. r0,r6,0,4,19
> 434: 41 82 00 14 beq- 448 <.__flush_hash_table_range+0xb0>
> continue;
> hpte_need_flush(mm, start, ptep, pte, 0);
> 438: 7f e4 fb 78 mr r4,r31
> 43c: 7f c3 f3 78 mr r3,r30
> 440: 38 e0 00 00 li r7,0
> 444: 48 00 00 01 bl 444 <.__flush_hash_table_range+0xac>
> * to being hashed). This is not the most performance oriented
> * way to do things but is fine for our needs here.
> */
> local_irq_save(flags);
> arch_enter_lazy_mmu_mode();
> for (; start < end; start += PAGE_SIZE) {
> 448: 3f ff 00 01 addis r31,r31,1
> 44c: 7f bf e0 40 cmpld cr7,r31,r28
> pte_t *pt = NULL;
>
> pg = pgdir + pgd_index(ea);
> if (!pgd_none(*pg)) {
> pu = pud_offset(pg, ea);
> if (!pud_none(*pu)) {
> 450: 7b e0 c5 e0 rldicl r0,r31,24,55
> pm = pmd_offset(pu, ea);
> if (pmd_present(*pm))
> 454: 7b e9 25 22 rldicl r9,r31,36,52
> pte_t *pt = NULL;
>
> pg = pgdir + pgd_index(ea);
> if (!pgd_none(*pg)) {
> pu = pud_offset(pg, ea);
> if (!pud_none(*pu)) {
> 458: 78 00 1f 24 rldicr r0,r0,3,60
> pm = pmd_offset(pu, ea);
> if (pmd_present(*pm))
> 45c: 79 2b 1f 24 rldicr r11,r9,3,60
> 460: 41 9c ff 98 blt+ cr7,3f8 <.__flush_hash_table_range+0x60>
> }
>
> static inline void arch_leave_lazy_mmu_mode(void)
> {
> struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
> 464: eb cd 00 40 ld r30,64(r13)
> 468: eb e2 00 08 ld r31,8(r2)
> 46c: 7c 7f f2 14 add r3,r31,r30
>
> if (batch->index)
> 470: e8 03 00 08 ld r0,8(r3)
> 474: 2f a0 00 00 cmpdi cr7,r0,0
> 478: 41 9e 00 08 beq- cr7,480 <.__flush_hash_table_range+0xe8>
> __flush_tlb_pending(batch);
> 47c: 48 00 00 01 bl 47c <.__flush_hash_table_range+0xe4>
> if (!(pte & _PAGE_HASHPTE))
> continue;
> hpte_need_flush(mm, start, ptep, pte, 0);
> }
> arch_leave_lazy_mmu_mode();
> local_irq_restore(flags);
> 480: 2f bd 00 00 cmpdi cr7,r29,0
> batch->active = 0;
> 484: 38 00 00 00 li r0,0
> 488: 38 60 00 00 li r3,0
> 48c: 7c 1f f1 2e stwx r0,r31,r30
> 490: 41 9e 00 08 beq- cr7,498 <.__flush_hash_table_range+0x100>
> 494: 7f a3 eb 78 mr r3,r29
> 498: 48 00 00 01 bl 498 <.__flush_hash_table_range+0x100>
> 49c: 60 00 00 00 nop
> }
> 4a0: 38 21 00 90 addi r1,r1,144
> 4a4: e8 01 00 10 ld r0,16(r1)
> 4a8: eb 81 ff e0 ld r28,-32(r1)
> 4ac: 7c 08 03 a6 mtlr r0
> 4b0: eb a1 ff e8 ld r29,-24(r1)
> 4b4: eb c1 ff f0 ld r30,-16(r1)
> 4b8: eb e1 ff f8 ld r31,-8(r1)
> 4bc: 4e 80 00 20 blr
^ permalink raw reply
* Re: [OOPS] hugetlbfs tests with 2.6.30-rc8-git1
From: Benjamin Herrenschmidt @ 2009-06-16 1:30 UTC (permalink / raw)
To: Sachin Sant; +Cc: Mel Gorman, linuxppc-dev
In-Reply-To: <4A3645EE.5060103@in.ibm.com>
On Mon, 2009-06-15 at 18:30 +0530, Sachin Sant wrote:
> 278: 2f 80 00 00 cmpwi cr7,r0,0
> } else {
> vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
> ssize = mmu_kernel_ssize;
> }
> vaddr = hpt_va(addr, vsid, ssize);
> rpte = __real_pte(__pte(pte), ptep);
> 27c: eb 89 80 00 ld r28,-32768(r9)
I think I know what the problem is. I'll send a tentative patch as soon
as I got to test it a bit here.
Cheers,
Ben.
^ permalink raw reply
* [PATCH] powerpc/mm: Fix potential access to freed pages when using hugetlbfs
From: Benjamin Herrenschmidt @ 2009-06-16 2:53 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
When using 64k page sizes, our PTE pages are split in two halves,
the second half containing the "extension" used to keep track of
individual 4k pages when not using HW 64k pages.
However, our page tables used for hugetlb have a slightly different
format and don't carry that "second half".
Our code that batched PTEs to be invalidated unconditionally reads
the "second half" (to put it into the batch), which means that when
called to invalidate hugetlb PTEs, it will access unrelated memory.
It breaks when CONFIG_DEBUG_PAGEALLOC is enabled.
This fixes it by only accessing the second half when the _PAGE_COMBO
bit is set in the first half, which indicates that we are dealing with
a "combo" page which represents 16x4k subpages. Anything else shouldn't
have this bit set and thus not require loading from the second half.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/include/asm/pte-hash64-64k.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- linux-work.orig/arch/powerpc/include/asm/pte-hash64-64k.h 2009-06-16 11:27:05.000000000 +1000
+++ linux-work/arch/powerpc/include/asm/pte-hash64-64k.h 2009-06-16 12:03:29.000000000 +1000
@@ -47,7 +47,8 @@
* generic accessors and iterators here
*/
#define __real_pte(e,p) ((real_pte_t) { \
- (e), pte_val(*((p) + PTRS_PER_PTE)) })
+ (e), ((e) & _PAGE_COMBO) ? \
+ (pte_val(*((p) + PTRS_PER_PTE))) : 0 })
#define __rpte_to_hidx(r,index) ((pte_val((r).pte) & _PAGE_COMBO) ? \
(((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
#define __rpte_to_pte(r) ((r).pte)
^ permalink raw reply
* [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2009-06-16 3:05 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, Andrew Morton, Linux Kernel list
Hi Linus !
Here's the other batch of powerpc stuff, including adding a small
accessor to the generic BIO code (acked by Jens) and Paulus generic
atomic64 implementation. A lot of PS3 updates in there, though I held
back a couple for some purely mechanical merge reasons, so expect a 3rd
batch with these plus some bug fixes before the end of the merge window.
The following changes since commit 03347e2592078a90df818670fddf97a33eec70fb:
Linus Torvalds (1):
Merge branch 'release' of git://git.kernel.org/.../aegl/linux-2.6
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
Benjamin Herrenschmidt (2):
Merge commit 'origin/master' into next
powerpc: Don't do generic calibrate_delay()
Geert Uytterhoeven (24):
ps3vram: Fix error path (return -EIO) for short read/write
ps3vram: Use proc_create_data() instead of proc_create()
ps3fb: Remove useless debug checks in ps3fb_shutdown()
ps3fb: Inline functions in ps3fb_probe(), to ease cleanup in the error path
ps3fb: Correct handling of device opening in ps3fb_probe()
powerpc/cell: Extract duplicated IOPTE_* to <asm/iommu.h>
ps3fb: GPU memory mapping cleanup
ps3vram: GPU memory mapping cleanup
ps3fb/vram: Extract common GPU stuff into <asm/ps3gpu.h>
ps3fb: Tear down FB setup during cleanup
block: Add bio_list_peek()
ps3vram: Replace mutex by spinlock + bio_list
ps3vram: Remove no longer used ps3vram_priv.ddr_base
ps3vram: Make ps3vram_priv.reports a void *
ps3: Use dev_[gs]et_drvdata() instead of direct access for system bus devices
ps3: shorten ps3_system_bus_[gs]et_driver_data to ps3_system_bus_[gs]et_drvdata
ps3flash: Use ps3_system_bus_[gs]et_drvdata() instead of direct access
ps3fb: Use ps3_system_bus_[gs]et_drvdata() instead of direct access
drivers/ps3: Add missing annotations
ps3: Correct debug message in dma_ioc0_map_pages()
ps3: Switch ps3_os_area_[gs]et_rtc_diff to EXPORT_SYMBOL_GPL()
ps3: Replace direct file operations by callback
ps3flash: Cache the last accessed FLASH chunk
ps3flash: Always read chunks of 256 KiB, and cache them
Grant Likely (1):
powerpc/install: Bail with error code on error in install script
Jim Paris (1):
ps3vram: Correct exchanged gotos in ps3vram_probe() error path
Michael Ellerman (5):
powerpc: Fix warning in setup_64.c when CONFIG_RELOCATABLE=y
powerpc/cell: Use driver_data acessors, not platform_data in Axon MSI
powerpc: Only build prom_init.o when CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
powerpc/iseries: Fix unused function warning in iSeries DT code
powerpc/iseries: Mark signal_vsp_instruction() as maybe unused
Paul Mackerras (3):
powerpc: Add compiler memory barrier to mtmsr macro
lib: Provide generic atomic64_t implementation
powerpc: Use generic atomic64_t implementation on 32-bit processors
Roel Kluin (1):
block/ps3: remove driver_data direct access of struct device
Stephen Rothwell (1):
powerpc: Wire up sys_rt_tgsigqueueinfo
sebastian.blanes@gmail.com (1):
ps3av: Set 16:9 aspect ratio for 720p video modes
Documentation/kernel-parameters.txt | 7 +
Documentation/powerpc/dts-bindings/ecm.txt | 64 ++
.../powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 3 +
Documentation/powerpc/dts-bindings/fsl/esdhc.txt | 5 +-
Documentation/powerpc/dts-bindings/fsl/mcm.txt | 64 ++
arch/powerpc/Kconfig | 21 +-
arch/powerpc/Kconfig.debug | 13 +
arch/powerpc/Makefile | 1 +
arch/powerpc/boot/dts/gef_ppc9a.dts | 14 +-
arch/powerpc/boot/dts/gef_sbc310.dts | 14 +-
arch/powerpc/boot/dts/gef_sbc610.dts | 14 +-
arch/powerpc/boot/dts/ksi8560.dts | 13 +
arch/powerpc/boot/dts/mpc832x_mds.dts | 3 +-
arch/powerpc/boot/dts/mpc832x_rdb.dts | 3 +-
arch/powerpc/boot/dts/mpc8349emitx.dts | 2 -
arch/powerpc/boot/dts/mpc8349emitxgp.dts | 1 -
arch/powerpc/boot/dts/mpc834x_mds.dts | 2 -
arch/powerpc/boot/dts/mpc836x_mds.dts | 3 +-
arch/powerpc/boot/dts/mpc836x_rdk.dts | 2 +
arch/powerpc/boot/dts/mpc8377_mds.dts | 1 -
arch/powerpc/boot/dts/mpc8378_mds.dts | 1 -
arch/powerpc/boot/dts/mpc8379_mds.dts | 1 -
arch/powerpc/boot/dts/mpc8536ds.dts | 18 +-
arch/powerpc/boot/dts/mpc8540ads.dts | 15 +-
arch/powerpc/boot/dts/mpc8541cds.dts | 16 +-
arch/powerpc/boot/dts/mpc8544ds.dts | 18 +-
arch/powerpc/boot/dts/mpc8548cds.dts | 17 +-
arch/powerpc/boot/dts/mpc8555cds.dts | 16 +-
arch/powerpc/boot/dts/mpc8560ads.dts | 15 +-
arch/powerpc/boot/dts/mpc8568mds.dts | 51 +-
arch/powerpc/boot/dts/mpc8569mds.dts | 583 +++++++++++
arch/powerpc/boot/dts/mpc8572ds.dts | 17 +-
arch/powerpc/boot/dts/mpc8572ds_36b.dts | 39 +-
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts | 16 +-
arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts | 2 -
arch/powerpc/boot/dts/mpc8610_hpcd.dts | 16 +-
arch/powerpc/boot/dts/mpc8641_hpcn.dts | 16 +-
arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts | 609 +++++++++++
arch/powerpc/boot/dts/p2020ds.dts | 704 +++++++++++++
arch/powerpc/boot/dts/sbc8349.dts | 1 -
arch/powerpc/boot/dts/sbc8548.dts | 16 +-
arch/powerpc/boot/dts/sbc8560.dts | 15 +-
arch/powerpc/boot/dts/sbc8641d.dts | 16 +-
arch/powerpc/boot/dts/sequoia.dts | 22 +
arch/powerpc/boot/dts/socrates.dts | 15 +-
arch/powerpc/boot/dts/stx_gp3_8560.dts | 15 +-
arch/powerpc/boot/dts/tqm8540.dts | 15 +-
arch/powerpc/boot/dts/tqm8541.dts | 15 +-
arch/powerpc/boot/dts/tqm8548-bigflash.dts | 16 +-
arch/powerpc/boot/dts/tqm8548.dts | 16 +-
arch/powerpc/boot/dts/tqm8555.dts | 15 +-
arch/powerpc/boot/dts/tqm8560.dts | 15 +-
arch/powerpc/boot/dts/virtex440-ml510.dts | 465 +++++++++
arch/powerpc/boot/dts/warp.dts | 27 +-
arch/powerpc/boot/install.sh | 3 +
arch/powerpc/configs/40x/acadia_defconfig | 2 +-
arch/powerpc/configs/40x/ep405_defconfig | 2 +-
arch/powerpc/configs/40x/kilauea_defconfig | 81 ++-
arch/powerpc/configs/40x/makalu_defconfig | 81 ++-
arch/powerpc/configs/40x/virtex_defconfig | 2 +-
arch/powerpc/configs/44x/arches_defconfig | 2 +-
arch/powerpc/configs/44x/bamboo_defconfig | 2 +-
arch/powerpc/configs/44x/canyonlands_defconfig | 6 +-
arch/powerpc/configs/44x/ebony_defconfig | 2 +-
arch/powerpc/configs/44x/katmai_defconfig | 2 +-
arch/powerpc/configs/44x/rainier_defconfig | 2 +-
arch/powerpc/configs/44x/redwood_defconfig | 2 +-
arch/powerpc/configs/44x/sam440ep_defconfig | 2 +-
arch/powerpc/configs/44x/sequoia_defconfig | 111 ++-
arch/powerpc/configs/44x/taishan_defconfig | 2 +-
arch/powerpc/configs/44x/virtex5_defconfig | 2 +-
arch/powerpc/include/asm/atomic.h | 3 +
arch/powerpc/include/asm/cpm2.h | 4 -
arch/powerpc/include/asm/dma-mapping.h | 11 +
arch/powerpc/include/asm/elf.h | 4 +-
arch/powerpc/include/asm/emulated_ops.h | 73 ++
arch/powerpc/include/asm/feature-fixups.h | 25 +-
arch/powerpc/include/asm/hw_irq.h | 5 +-
arch/powerpc/include/asm/iommu.h | 10 +
arch/powerpc/include/asm/lppaca.h | 6 +
arch/powerpc/include/asm/machdep.h | 4 +
arch/powerpc/include/asm/mmu.h | 9 +-
arch/powerpc/include/asm/mpc86xx.h | 33 -
arch/powerpc/include/asm/paca.h | 12 +-
arch/powerpc/include/asm/page.h | 5 +
arch/powerpc/include/asm/pci-bridge.h | 13 +-
arch/powerpc/include/asm/pgtable-ppc64.h | 5 +
arch/powerpc/include/asm/ppc-opcode.h | 25 +-
arch/powerpc/include/asm/ppc_asm.h | 10 -
arch/powerpc/include/asm/ps3.h | 18 +-
arch/powerpc/include/asm/ps3gpu.h | 86 ++
arch/powerpc/include/asm/ptrace.h | 4 +
arch/powerpc/include/asm/qe.h | 21 +-
arch/powerpc/include/asm/reg.h | 4 +-
arch/powerpc/include/asm/scatterlist.h | 6 +-
arch/powerpc/include/asm/swiotlb.h | 27 +
arch/powerpc/include/asm/systbl.h | 1 +
arch/powerpc/include/asm/system.h | 2 +-
arch/powerpc/include/asm/unistd.h | 3 +-
arch/powerpc/include/asm/xilinx_pci.h | 21 +
arch/powerpc/kernel/Makefile | 6 +-
arch/powerpc/kernel/align.c | 20 +-
arch/powerpc/kernel/asm-offsets.c | 32 +-
arch/powerpc/kernel/cputable.c | 6 +-
arch/powerpc/kernel/dma-swiotlb.c | 163 +++
arch/powerpc/kernel/dma.c | 2 +-
arch/powerpc/kernel/exceptions-64s.S | 978 +++++++++++++++++
arch/powerpc/kernel/ftrace.c | 29 +-
arch/powerpc/kernel/head_32.S | 101 +--
arch/powerpc/kernel/head_64.S | 1095 +-------------------
arch/powerpc/kernel/head_booke.h | 10 +-
arch/powerpc/kernel/irq.c | 127 ++--
arch/powerpc/kernel/lparcfg.c | 40 +-
arch/powerpc/kernel/misc_64.S | 92 --
arch/powerpc/kernel/paca.c | 14 +-
arch/powerpc/kernel/pci-common.c | 3 +-
arch/powerpc/kernel/pci_32.c | 19 -
arch/powerpc/kernel/pci_64.c | 17 +-
arch/powerpc/kernel/pci_dn.c | 28 +-
arch/powerpc/kernel/process.c | 2 +-
arch/powerpc/kernel/prom.c | 2 +-
arch/powerpc/kernel/ptrace.c | 23 +-
arch/powerpc/kernel/rtas_pci.c | 10 +-
arch/powerpc/kernel/setup_32.c | 6 +
arch/powerpc/kernel/setup_64.c | 15 +-
arch/powerpc/kernel/time.c | 31 +-
arch/powerpc/kernel/traps.c | 130 +++-
arch/powerpc/kernel/vector.S | 210 ++++
arch/powerpc/mm/Makefile | 7 +-
arch/powerpc/mm/hash_native_64.c | 13 +-
arch/powerpc/mm/init_64.c | 2 +
arch/powerpc/mm/mmu_context_nohash.c | 19 +-
arch/powerpc/mm/numa.c | 2 +
arch/powerpc/oprofile/op_model_fsl_emb.c | 14 -
arch/powerpc/platforms/40x/Kconfig | 2 +
arch/powerpc/platforms/40x/Makefile | 2 -
arch/powerpc/platforms/40x/kilauea.c | 60 --
arch/powerpc/platforms/40x/makalu.c | 60 --
arch/powerpc/platforms/40x/ppc40x_simple.c | 5 +-
arch/powerpc/platforms/40x/virtex.c | 2 +
arch/powerpc/platforms/44x/Kconfig | 13 +-
arch/powerpc/platforms/44x/Makefile | 1 +
arch/powerpc/platforms/44x/virtex.c | 2 +
arch/powerpc/platforms/44x/virtex_ml510.c | 29 +
arch/powerpc/platforms/44x/warp.c | 76 +-
arch/powerpc/platforms/52xx/efika.c | 4 +-
arch/powerpc/platforms/52xx/mpc52xx_pci.c | 4 +-
arch/powerpc/platforms/82xx/pq2ads.h | 13 -
arch/powerpc/platforms/85xx/Kconfig | 1 +
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 43 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 52 +-
arch/powerpc/platforms/86xx/gef_ppc9a.c | 1 -
arch/powerpc/platforms/86xx/gef_sbc310.c | 1 -
arch/powerpc/platforms/86xx/gef_sbc610.c | 1 -
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 1 -
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 1 -
arch/powerpc/platforms/86xx/mpc86xx_smp.c | 8 +-
arch/powerpc/platforms/86xx/sbc8641d.c | 1 -
arch/powerpc/platforms/8xx/mpc885ads.h | 4 -
arch/powerpc/platforms/Kconfig | 4 +
arch/powerpc/platforms/Kconfig.cputype | 26 +-
arch/powerpc/platforms/cell/axon_msi.c | 4 +-
arch/powerpc/platforms/cell/celleb_pci.c | 10 +-
arch/powerpc/platforms/cell/celleb_scc_epci.c | 13 +-
arch/powerpc/platforms/cell/celleb_scc_pciex.c | 12 +-
arch/powerpc/platforms/cell/iommu.c | 37 +-
arch/powerpc/platforms/cell/spufs/inode.c | 6 -
arch/powerpc/platforms/chrp/pci.c | 8 +-
arch/powerpc/platforms/fsl_uli1575.c | 24 +-
arch/powerpc/platforms/iseries/dt.c | 3 +-
arch/powerpc/platforms/iseries/iommu.c | 2 +-
arch/powerpc/platforms/iseries/mf.c | 3 +-
arch/powerpc/platforms/iseries/pci.c | 8 +-
arch/powerpc/platforms/powermac/pic.c | 2 +-
arch/powerpc/platforms/powermac/setup.c | 2 +-
arch/powerpc/platforms/ps3/mm.c | 12 +-
arch/powerpc/platforms/ps3/os-area.c | 142 ++--
arch/powerpc/platforms/ps3/platform.h | 10 -
arch/powerpc/platforms/ps3/setup.c | 1 +
arch/powerpc/platforms/ps3/smp.c | 16 +-
arch/powerpc/platforms/ps3/system-bus.c | 15 +-
arch/powerpc/platforms/pseries/iommu.c | 4 +-
arch/powerpc/platforms/pseries/lpar.c | 52 +
arch/powerpc/platforms/pseries/rtasd.c | 76 +-
arch/powerpc/platforms/pseries/setup.c | 25 +
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/cpm2.c | 2 +-
arch/powerpc/sysdev/fsl_msi.c | 9 +-
arch/powerpc/sysdev/fsl_pci.c | 138 +++-
arch/powerpc/sysdev/fsl_pci.h | 6 +-
arch/powerpc/sysdev/fsl_rio.c | 15 +-
arch/powerpc/sysdev/fsl_soc.c | 14 +-
arch/powerpc/sysdev/indirect_pci.c | 4 +-
arch/powerpc/sysdev/mpic.c | 23 +-
arch/powerpc/sysdev/ppc4xx_pci.c | 4 +-
arch/powerpc/sysdev/qe_lib/qe.c | 75 ++-
arch/powerpc/sysdev/tsi108_pci.c | 4 +-
arch/powerpc/sysdev/xilinx_intc.c | 81 ++-
arch/powerpc/sysdev/xilinx_pci.c | 132 +++
arch/powerpc/xmon/xmon.c | 47 +
drivers/block/ps3disk.c | 18 +-
drivers/block/ps3vram.c | 168 ++--
drivers/char/ps3flash.c | 296 +++---
drivers/char/viotape.c | 2 +-
drivers/i2c/busses/i2c-ibm_iic.c | 6 +-
drivers/macintosh/therm_adt746x.c | 4 +-
drivers/net/ps3_gelic_net.c | 8 +-
drivers/net/ucc_geth.c | 24 +-
drivers/net/ucc_geth.h | 4 +-
drivers/of/base.c | 1 +
drivers/pci/Makefile | 1 -
drivers/ps3/ps3-sys-manager.c | 2 +-
drivers/ps3/ps3av.c | 8 +-
drivers/ps3/ps3av_cmd.c | 3 +-
drivers/rapidio/rio-scan.c | 6 +-
drivers/usb/host/ehci-ps3.c | 7 +-
drivers/usb/host/ohci-ps3.c | 7 +-
drivers/video/ps3fb.c | 272 ++---
drivers/video/xilinxfb.c | 290 +++---
include/asm-generic/atomic64.h | 42 +
include/linux/bio.h | 5 +
include/linux/pci_ids.h | 4 +
lib/Kconfig | 6 +
lib/Makefile | 2 +
lib/atomic64.c | 175 ++++
225 files changed, 7064 insertions(+), 2884 deletions(-)
create mode 100644 Documentation/powerpc/dts-bindings/ecm.txt
create mode 100644 Documentation/powerpc/dts-bindings/fsl/mcm.txt
create mode 100644 arch/powerpc/boot/dts/mpc8569mds.dts
create mode 100644 arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
create mode 100644 arch/powerpc/boot/dts/p2020ds.dts
create mode 100644 arch/powerpc/boot/dts/virtex440-ml510.dts
create mode 100644 arch/powerpc/include/asm/emulated_ops.h
delete mode 100644 arch/powerpc/include/asm/mpc86xx.h
create mode 100644 arch/powerpc/include/asm/ps3gpu.h
create mode 100644 arch/powerpc/include/asm/swiotlb.h
create mode 100644 arch/powerpc/include/asm/xilinx_pci.h
create mode 100644 arch/powerpc/kernel/dma-swiotlb.c
create mode 100644 arch/powerpc/kernel/exceptions-64s.S
delete mode 100644 arch/powerpc/platforms/40x/kilauea.c
delete mode 100644 arch/powerpc/platforms/40x/makalu.c
create mode 100644 arch/powerpc/platforms/44x/virtex_ml510.c
create mode 100644 arch/powerpc/sysdev/xilinx_pci.c
create mode 100644 include/asm-generic/atomic64.h
create mode 100644 lib/atomic64.c
^ permalink raw reply
* Re: [PATCH -next 1/4] powerpc/85xx: Add platform support for X-ES MPC85xx boards
From: Kumar Gala @ 2009-06-16 3:16 UTC (permalink / raw)
To: Nate Case; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1244749381-17429-2-git-send-email-ncase@xes-inc.com>
On Jun 11, 2009, at 2:42 PM, Nate Case wrote:
> Add support for X-ES single-board computers based on the Freescale
> MPC85xx processors.
>
> Signed-off-by: Nate Case <ncase@xes-inc.com>
> ---
> arch/powerpc/platforms/85xx/Kconfig | 10 +
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/xes_mpc85xx.c | 282 ++++++++++++++++++++
> +++++++++
> 3 files changed, 293 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/platforms/85xx/xes_mpc85xx.c
applied to next
- k
^ permalink raw reply
* Re: [PATCH -next 2/4] powerpc/85xx: Add dts files for X-ES MPC85xx boards
From: Kumar Gala @ 2009-06-16 3:16 UTC (permalink / raw)
To: Nate Case; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1244749381-17429-3-git-send-email-ncase@xes-inc.com>
On Jun 11, 2009, at 2:42 PM, Nate Case wrote:
> Add device tree source files for various MPC85xx boards from Extreme
> Engineering Solutions. Supported boards include XPedite5370,
> XPedite5200, XPedite5301, XPedite5330, and XCalibur1501.
>
> Signed-off-by: Nate Case <ncase@xes-inc.com>
> ---
> arch/powerpc/boot/dts/xcalibur1501.dts | 696 +++++++++++++++++++
> ++++++++
> arch/powerpc/boot/dts/xpedite5200.dts | 466 ++++++++++++++++++
> arch/powerpc/boot/dts/xpedite5200_xmon.dts | 506 ++++++++++++++++++++
> arch/powerpc/boot/dts/xpedite5301.dts | 640 +++++++++++++++++++
> ++++++
> arch/powerpc/boot/dts/xpedite5330.dts | 707 +++++++++++++++++++
> +++++++++
> arch/powerpc/boot/dts/xpedite5370.dts | 638 +++++++++++++++++++
> ++++++
> 6 files changed, 3653 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/xcalibur1501.dts
> create mode 100644 arch/powerpc/boot/dts/xpedite5200.dts
> create mode 100644 arch/powerpc/boot/dts/xpedite5200_xmon.dts
> create mode 100644 arch/powerpc/boot/dts/xpedite5301.dts
> create mode 100644 arch/powerpc/boot/dts/xpedite5330.dts
> create mode 100644 arch/powerpc/boot/dts/xpedite5370.dts
applied to next
- k
^ permalink raw reply
* Re: [PATCH -next 3/4] powerpc/85xx: Add defconfig for X-ES MPC85xx boards
From: Kumar Gala @ 2009-06-16 3:16 UTC (permalink / raw)
To: Nate Case; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1244749381-17429-4-git-send-email-ncase@xes-inc.com>
On Jun 11, 2009, at 2:43 PM, Nate Case wrote:
> Signed-off-by: Nate Case <ncase@xes-inc.com>
> ---
> arch/powerpc/configs/85xx/xes_mpc85xx_defconfig | 1821 ++++++++++++++
> +++++++++
> 1 files changed, 1821 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/configs/85xx/xes_mpc85xx_defconfig
applied to next
- k
^ permalink raw reply
* Re: [PATCH -next 4/4] powerpc/bootwrapper: Custom build options for XPedite52xx targets
From: Kumar Gala @ 2009-06-16 3:16 UTC (permalink / raw)
To: Nate Case; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1244749381-17429-5-git-send-email-ncase@xes-inc.com>
On Jun 11, 2009, at 2:43 PM, Nate Case wrote:
> Some XPedite52xx boards have a legacy boot loader requiring some
> special
> care in the boot wrapper. The use of cuboot-85xx is needed to fix
> up embedded device trees, and a custom link address is specified to
> accommodate the boot loader and larger kernel image sizes used on X-ES
> MPC85xx platforms.
>
> Signed-off-by: Nate Case <ncase@xes-inc.com>
> ---
> arch/powerpc/boot/wrapper | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH v5] 83xx: add support for the kmeter1 board.
From: Kumar Gala @ 2009-06-16 3:16 UTC (permalink / raw)
To: hs; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <4A35FA6A.60004@denx.de>
On Jun 15, 2009, at 2:38 AM, Heiko Schocher wrote:
> The following series implements basic board support for
> the kmeter1 board from keymile, based on a MPC8360.
>
> This series provides the following functionality:
>
> - The board can boot with a serial console on UART1
> - Ethernet:
> UCC1 in RGMII mode
> UCC2 in RGMII mode
> UCC4 in RMII mode
> UCC5 in RMII mode
> UCC6 in RMII mode
> UCC7 in RMII mode
> UCC8 in RMII mode
>
> following patch is necessary for working UCC in RMII mode:
>
> http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070804.html
>
> - Flash accessed via MTD layer
>
> On this hardware there is an Intel P30 flash, following patch
> series is necessary for working with this hardware:
>
> http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-April/070624.html
>
> - I2C using I2C Bus 1 from the MPC8360 cpu
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> changes since v1:
> - added comments from Kumar Gala and Scott Wood
> - get rid of using get_immrbase() in board specific code
>
> changes since v2:
> - added comments from Kumar Gala
> - rebased against 1406de8e11eb043681297adf86d6892ff8efc27a
> from git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
>
> changes since v3:
> - updated mailinglistarchivelinks for necessary patches in commit
> text.
>
> changes since v4:
> - added comments from David Gibson
>
> $ ./scripts/checkpatch.pl 0001--83xx-add-support-for-the-kmeter1-
> board.patch
> total: 0 errors, 0 warnings, 1636 lines checked
>
> 0001--83xx-add-support-for-the-kmeter1-board.patch has no obvious
> style problems and is ready for submission.
> $
>
> Signed-off-by: Heiko Schocher <hs@denx.de>
> ---
> arch/powerpc/boot/dts/kmeter1.dts | 520 +++++++++++++++
> arch/powerpc/configs/83xx/kmeter1_defconfig | 908 ++++++++++++++++++
> +++++++++
> arch/powerpc/platforms/83xx/Kconfig | 7 +
> arch/powerpc/platforms/83xx/Makefile | 1 +
> arch/powerpc/platforms/83xx/kmeter1.c | 191 ++++++
> 5 files changed, 1627 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/kmeter1.dts
> create mode 100644 arch/powerpc/configs/83xx/kmeter1_defconfig
> create mode 100644 arch/powerpc/platforms/83xx/kmeter1.c
applied to next
- k
^ permalink raw reply
* Please pull from 'next' branch for 2.6.31
From: Kumar Gala @ 2009-06-16 3:25 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
Please pull from 'next' branch of
master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git next
to receive the following updates:
arch/powerpc/boot/cuboot-85xx.c | 2
arch/powerpc/boot/dts/asp834x-redboot.dts | 2
arch/powerpc/boot/dts/gef_sbc610.dts | 10
arch/powerpc/boot/dts/kmeter1.dts | 520 ++++++
arch/powerpc/boot/dts/mpc8272ads.dts | 19
arch/powerpc/boot/dts/mpc8315erdb.dts | 15
arch/powerpc/boot/dts/mpc8349emitx.dts | 2
arch/powerpc/boot/dts/mpc834x_mds.dts | 2
arch/powerpc/boot/dts/mpc8377_mds.dts | 2
arch/powerpc/boot/dts/mpc8377_rdb.dts | 2
arch/powerpc/boot/dts/mpc8378_mds.dts | 2
arch/powerpc/boot/dts/mpc8378_rdb.dts | 2
arch/powerpc/boot/dts/mpc8379_mds.dts | 2
arch/powerpc/boot/dts/mpc8379_rdb.dts | 2
arch/powerpc/boot/dts/mpc8569mds.dts | 87 +
arch/powerpc/boot/dts/sbc8349.dts | 2
arch/powerpc/boot/dts/xcalibur1501.dts | 696 +++++++++
arch/powerpc/boot/dts/xpedite5200.dts | 466 ++++++
arch/powerpc/boot/dts/xpedite5200_xmon.dts | 506 ++++++
arch/powerpc/boot/dts/xpedite5301.dts | 640 ++++++++
arch/powerpc/boot/dts/xpedite5330.dts | 707 +++++++++
arch/powerpc/boot/dts/xpedite5370.dts | 638 ++++++++
arch/powerpc/boot/wrapper | 4
arch/powerpc/configs/83xx/kmeter1_defconfig | 908 +++++++++++
arch/powerpc/configs/85xx/xes_mpc85xx_defconfig | 1821 ++++++++++++++++++++++++
arch/powerpc/include/asm/fsl_lbc.h | 4
arch/powerpc/include/asm/reg_booke.h | 2
arch/powerpc/kernel/cpu_setup_6xx.S | 3
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 49
arch/powerpc/platforms/83xx/Kconfig | 7
arch/powerpc/platforms/83xx/Makefile | 1
arch/powerpc/platforms/83xx/kmeter1.c | 191 ++
arch/powerpc/platforms/83xx/mpc83xx.h | 4
arch/powerpc/platforms/83xx/usb.c | 10
arch/powerpc/platforms/85xx/Kconfig | 13
arch/powerpc/platforms/85xx/Makefile | 1
arch/powerpc/platforms/85xx/mpc8536_ds.c | 17
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 19
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 20
arch/powerpc/platforms/85xx/xes_mpc85xx.c | 282 +++
arch/powerpc/platforms/86xx/Kconfig | 1
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 15
drivers/rapidio/rio-scan.c | 43
drivers/rapidio/rio-sysfs.c | 6
drivers/serial/ucc_uart.c | 19
45 files changed, 7713 insertions(+), 53 deletions(-)
Anton Vorontsov (1):
powerpc/83xx: Update sdhci nodes per new bindings
Becky Bruce (1):
powerpc: Add 86xx support for SWIOTLB
Dave Liu (1):
serial: Make ucc_uart work in HW UART mode
Gerhard Pircher (1):
powerpc: Enable additional BAT registers in setup_745x_specifics()
Haiying Wang (1):
powerpc/85xx: Add UCC6 and UCC8 nodes in SGMII mode for MPC8569MDS
Heiko Schocher (1):
83xx: add support for the kmeter1 board.
Kevin Hao (1):
powerpc/85xx: Add nor flash partitions for mpc8569mds
Kumar Gala (1):
powerpc/85xx: Add SWIOTLB support to FSL boards
Martyn Welch (1):
powerpc/86xx: Add I2C device mappings in DTS for SBC610
Nate Case (6):
powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs
powerpc/85xx: cuboot - Fix up ethernet3 MAC address on MPC85xx
powerpc/85xx: Add platform support for X-ES MPC85xx boards
powerpc/85xx: Add dts files for X-ES MPC85xx boards
powerpc/85xx: Add defconfig for X-ES MPC85xx boards
powerpc/bootwrapper: Custom build options for XPedite52xx targets
Peter Korsgaard (1):
powerpc/mpc83xx: Fix usb mux setup for mpc834x
Wolfgang Denk (1):
powerpc/mpc8272ads: fix device tree for 8 MB flash size
Yang Li (1):
rio: warn_unused_result warnings fix
leon.woestenberg@gmail.com (1):
powerpc/83xx: Add MSI interrupts to DTS of MPC8315E-RDB
mware@internode.on.net (1):
powerpc/fsl: Increase the number of possible localbus banks
^ permalink raw reply
* Re: UIO: uio_mem does not handle devices above 4 GB address
From: Benjamin Herrenschmidt @ 2009-06-16 3:25 UTC (permalink / raw)
To: Steven A. Falco
Cc: linuxppc-dev@ozlabs.org, hjk, Herrera-Bendezu, Luis, linux-kernel
In-Reply-To: <49D4BB9F.8050903@harris.com>
On Thu, 2009-04-02 at 09:20 -0400, Steven A. Falco wrote:
> struct uio_mem {
> phys_addr_t addr;
> phys_addr_t size;
> int memtype;
> void __iomem *internal_addr;
> struct uio_map *map;
> };
>
> A few other changes would be needed. We'd have to use something
> other than
Use a struct resource instead.
> return sprintf(buf, "0x%lx\n", mem->addr);
>
The struct resource has a printk format string.
Cheers,
Ben.
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH v2] drivers/hvc: add missing __devexit_p()
From: Benjamin Herrenschmidt @ 2009-06-16 3:30 UTC (permalink / raw)
To: Mike Frysinger; +Cc: linuxppc-dev, Andrew Morton, linux-kernel
In-Reply-To: <1242632661-16198-1-git-send-email-vapier@gentoo.org>
On Mon, 2009-05-18 at 03:44 -0400, Mike Frysinger wrote:
> The remove function uses __devexit, so the .remove assignment needs
> __devexit_p() to fix a build error with hotplug disabled.
>
> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
> CC: linuxppc-dev@ozlabs.org
> ---
> v2
Thanks. Andrew, I'm picking this one up.
Cheers,
Ben.
> - include all hvc files
>
> drivers/char/hvc_iseries.c | 2 +-
> drivers/char/hvc_vio.c | 2 +-
> drivers/char/hvcs.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/char/hvc_iseries.c b/drivers/char/hvc_iseries.c
> index 449727b..936d05b 100644
> --- a/drivers/char/hvc_iseries.c
> +++ b/drivers/char/hvc_iseries.c
> @@ -241,7 +241,7 @@ static int __devexit hvc_vio_remove(struct vio_dev *vdev)
> static struct vio_driver hvc_vio_driver = {
> .id_table = hvc_driver_table,
> .probe = hvc_vio_probe,
> - .remove = hvc_vio_remove,
> + .remove = __devexit_p(hvc_vio_remove),
> .driver = {
> .name = hvc_driver_name,
> .owner = THIS_MODULE,
> diff --git a/drivers/char/hvc_vio.c b/drivers/char/hvc_vio.c
> index bd62dc8..c72b994 100644
> --- a/drivers/char/hvc_vio.c
> +++ b/drivers/char/hvc_vio.c
> @@ -113,7 +113,7 @@ static int __devexit hvc_vio_remove(struct vio_dev *vdev)
> static struct vio_driver hvc_vio_driver = {
> .id_table = hvc_driver_table,
> .probe = hvc_vio_probe,
> - .remove = hvc_vio_remove,
> + .remove = __devexit_p(hvc_vio_remove),
> .driver = {
> .name = hvc_driver_name,
> .owner = THIS_MODULE,
> diff --git a/drivers/char/hvcs.c b/drivers/char/hvcs.c
> index c76bccf..2724d62 100644
> --- a/drivers/char/hvcs.c
> +++ b/drivers/char/hvcs.c
> @@ -868,7 +868,7 @@ static int __devexit hvcs_remove(struct vio_dev *dev)
> static struct vio_driver hvcs_vio_driver = {
> .id_table = hvcs_driver_table,
> .probe = hvcs_probe,
> - .remove = hvcs_remove,
> + .remove = __devexit_p(hvcs_remove),
> .driver = {
> .name = hvcs_driver_name,
> .owner = THIS_MODULE,
^ permalink raw reply
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