* Re: dma_ops->map_page == NULL
From: Kumar Gala @ 2009-07-07 15:45 UTC (permalink / raw)
To: Kári Davíðsson
Cc: Mark Nelson, linuxppc-dev@ozlabs.org, Kumar Gala
In-Reply-To: <4A5368C7.9020202@marel.com>
On Jul 7, 2009, at 10:24 AM, K=E1ri Dav=ED=F0sson wrote:
> Yes the device pointer was invalid.
>
> I was passing the of_device pointer instead of
> the address of of_device->dev.
>
> But I am sure this was working (passing of_device pointer) with
> earlier kernels.
>
> Thanks for the help.
>
> rg
> kd
earlier kernels didn't care if the dev pointer was valid and thus let =20=
it pass if you didn't give the proper thing.
- k=
^ permalink raw reply
* Re: MTD OF parser problem
From: Scott Wood @ 2009-07-07 17:31 UTC (permalink / raw)
To: Roman Fietze; +Cc: linuxppc-dev
In-Reply-To: <200907071545.30121.roman.fietze@telemotive.de>
On Tue, Jul 07, 2009 at 03:45:29PM +0200, Roman Fietze wrote:
> Hallo,
>
> I tried to define my MTD partitions in a device tree as
> documented. The function of_flash_probe() inside teh file physmap_of.c
> never compiled the code below
>
> #ifdef CONFIG_MTD_OF_PARTS
>
> because when the MTD subsystem is compiled as a module I can only find
> CONFIG_MTD_OF_PARTS_MODULE beeing defined somewhere below my build
> directory.
>
> If I change the above define to
>
> #if defined(CONFIG_MTD_OF_PARTS) || defined(CONFIG_MTD_OF_PARTS_MODULE)
>
> everything is fine and MTD partition work as expected.
>
> My fault? Other solution?
That would break if MTD_PHYSMAP_OF (or any other user) is built-in but
MTD_OF_PARTS is a module.
Perhaps there's some way we could hook OF partitions into the normal
partition probing, so we don't have to refer to it by symbol? The main
obstacle would be communicating the device node.
Or we could just disallow MTD_OF_PARTS from being modularized -- like
MTD_PARTITIONS.
-Scott
^ permalink raw reply
* [PATCH] ucc_geth: Add support for skb recycling
From: Anton Vorontsov @ 2009-07-07 18:38 UTC (permalink / raw)
To: David Miller; +Cc: netdev, Li Yang, Andy Fleming, linuxppc-dev
We can reclaim transmitted skbs to use in the receive path, so-called
skb recycling support.
Also reorder ucc_geth_poll() steps, so that we'll clean tx ring firstly,
thus maybe reclaim some skbs for rx.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
drivers/net/ucc_geth.c | 40 ++++++++++++++++++++++++++++------------
drivers/net/ucc_geth.h | 2 ++
2 files changed, 30 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 40c6eba..beaa329 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -209,9 +209,10 @@ static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
{
struct sk_buff *skb = NULL;
- skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
- UCC_GETH_RX_DATA_BUF_ALIGNMENT);
-
+ skb = __skb_dequeue(&ugeth->rx_recycle);
+ if (!skb)
+ skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
+ UCC_GETH_RX_DATA_BUF_ALIGNMENT);
if (skb == NULL)
return NULL;
@@ -1986,6 +1987,8 @@ static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
iounmap(ugeth->ug_regs);
ugeth->ug_regs = NULL;
}
+
+ skb_queue_purge(&ugeth->rx_recycle);
}
static void ucc_geth_set_multi(struct net_device *dev)
@@ -2202,6 +2205,8 @@ static int ucc_struct_init(struct ucc_geth_private *ugeth)
return -ENOMEM;
}
+ skb_queue_head_init(&ugeth->rx_recycle);
+
return 0;
}
@@ -3208,8 +3213,10 @@ static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit
if (netif_msg_rx_err(ugeth))
ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
__func__, __LINE__, (u32) skb);
- if (skb)
- dev_kfree_skb_any(skb);
+ if (skb) {
+ skb->data = skb->head + NET_SKB_PAD;
+ __skb_queue_head(&ugeth->rx_recycle, skb);
+ }
ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
dev->stats.rx_dropped++;
@@ -3267,6 +3274,8 @@ static int ucc_geth_tx(struct net_device *dev, u8 txQ)
/* Normal processing. */
while ((bd_status & T_R) == 0) {
+ struct sk_buff *skb;
+
/* BD contains already transmitted buffer. */
/* Handle the transmitted buffer and release */
/* the BD to be used with the current frame */
@@ -3276,9 +3285,16 @@ static int ucc_geth_tx(struct net_device *dev, u8 txQ)
dev->stats.tx_packets++;
- /* Free the sk buffer associated with this TxBD */
- dev_kfree_skb(ugeth->
- tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]]);
+ skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
+
+ if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
+ skb_recycle_check(skb,
+ ugeth->ug_info->uf_info.max_rx_buf_length +
+ UCC_GETH_RX_DATA_BUF_ALIGNMENT))
+ __skb_queue_head(&ugeth->rx_recycle, skb);
+ else
+ dev_kfree_skb(skb);
+
ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
ugeth->skb_dirtytx[txQ] =
(ugeth->skb_dirtytx[txQ] +
@@ -3307,16 +3323,16 @@ static int ucc_geth_poll(struct napi_struct *napi, int budget)
ug_info = ugeth->ug_info;
- howmany = 0;
- for (i = 0; i < ug_info->numQueuesRx; i++)
- howmany += ucc_geth_rx(ugeth, i, budget - howmany);
-
/* Tx event processing */
spin_lock(&ugeth->lock);
for (i = 0; i < ug_info->numQueuesTx; i++)
ucc_geth_tx(ugeth->ndev, i);
spin_unlock(&ugeth->lock);
+ howmany = 0;
+ for (i = 0; i < ug_info->numQueuesRx; i++)
+ howmany += ucc_geth_rx(ugeth, i, budget - howmany);
+
if (howmany < budget) {
napi_complete(napi);
setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index 195ab26..cfb31af 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -1212,6 +1212,8 @@ struct ucc_geth_private {
/* index of the first skb which hasn't been transmitted yet. */
u16 skb_dirtytx[NUM_TX_QUEUES];
+ struct sk_buff_head rx_recycle;
+
struct ugeth_mii_info *mii_info;
struct phy_device *phydev;
phy_interface_t phy_interface;
--
1.6.3.3
^ permalink raw reply related
* Re: [PATCH] ucc_geth: Add support for skb recycling
From: Rick Jones @ 2009-07-07 18:47 UTC (permalink / raw)
To: Anton Vorontsov; +Cc: netdev, Li Yang, Andy Fleming, David Miller, linuxppc-dev
In-Reply-To: <20090707183842.GA8425@oksana.dev.rtsoft.ru>
Anton Vorontsov wrote:
> We can reclaim transmitted skbs to use in the receive path, so-called
> skb recycling support.
>
> Also reorder ucc_geth_poll() steps, so that we'll clean tx ring firstly,
> thus maybe reclaim some skbs for rx.
Admittedly, all the world is not TCP, but a big chunk is, so are you likely to
have reference counts go to zero on the tx queue for anything other than small
standalone TCP ACK segments?
rick jones
^ permalink raw reply
* Re: [PATCH] ucc_geth: Add support for skb recycling
From: Anton Vorontsov @ 2009-07-07 20:37 UTC (permalink / raw)
To: Rick Jones
Cc: netdev, linuxppc-dev, Andy Fleming, Li Yang, David Miller,
Lennert Buytenhek
In-Reply-To: <4A53984A.4050002@hp.com>
On Tue, Jul 07, 2009 at 11:47:38AM -0700, Rick Jones wrote:
> Anton Vorontsov wrote:
> >We can reclaim transmitted skbs to use in the receive path, so-called
> >skb recycling support.
> >
> >Also reorder ucc_geth_poll() steps, so that we'll clean tx ring firstly,
> >thus maybe reclaim some skbs for rx.
>
> Admittedly, all the world is not TCP, but a big chunk is, so are you
> likely to have reference counts go to zero on the tx queue for
> anything other than small standalone TCP ACK segments?
That's a generic question wrt skb recycling, right? Whether we can
always recycle transmitted skbs. No, sometimes (or mostly) we can't.
Initially, I was quite puzzled by this support... looking at how
gianfar driver works (it has the same support as of 0fd56bb5be6455d0),
I noticed that skb_recycle_check() always returns 0, and so we
don't recycle the skbs.
Though, things change when the kernel starts packets forwarding,
*then* skb recycling path actually triggers.
Lennert (skb recycling author) hints us that the gain is indeed
in forwarding/routing workload:
http://kerneltrap.org/mailarchive/linux-netdev/2008/9/28/3433514
Hope I understood everything correctly. :-)
Thanks!
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* Re: [PATCH] ucc_geth: Add support for skb recycling
From: Rick Jones @ 2009-07-07 20:46 UTC (permalink / raw)
To: avorontsov
Cc: netdev, linuxppc-dev, Andy Fleming, Li Yang, David Miller,
Lennert Buytenhek
In-Reply-To: <20090707203712.GA11157@oksana.dev.rtsoft.ru>
Anton Vorontsov wrote:
> On Tue, Jul 07, 2009 at 11:47:38AM -0700, Rick Jones wrote:
>>Admittedly, all the world is not TCP, but a big chunk is, so are you
>>likely to have reference counts go to zero on the tx queue for
>>anything other than small standalone TCP ACK segments?
>
>
> That's a generic question wrt skb recycling, right? Whether we can
> always recycle transmitted skbs. No, sometimes (or mostly) we can't.
>
> Initially, I was quite puzzled by this support... looking at how
> gianfar driver works (it has the same support as of 0fd56bb5be6455d0),
> I noticed that skb_recycle_check() always returns 0, and so we
> don't recycle the skbs.
>
> Though, things change when the kernel starts packets forwarding,
> *then* skb recycling path actually triggers.
>
> Lennert (skb recycling author) hints us that the gain is indeed
> in forwarding/routing workload:
>
> http://kerneltrap.org/mailarchive/linux-netdev/2008/9/28/3433514
>
>
> Hope I understood everything correctly. :-)
Given the text reads:
This gives a nice increase in the maximum loss-free packet forwarding
rate in routing workloads.
Your understanding is probably correct. Might have been "nice" :) to get a
definition of a "nice increase" though :)
rick jones
^ permalink raw reply
* Re: Delay on intialization ide subsystem(most likely)
From: Andrey Gusev @ 2009-07-07 21:18 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linux-ide, petkovbb, David Miller, Bartlomiej Zolnierkiewicz,
linuxppc-dev
In-Reply-To: <1246922623.22625.57.camel@pasglop>
On Tue, 07 Jul 2009 09:23:42 +1000
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> On Mon, 2009-07-06 at 17:04 +0200, Bartlomiej Zolnierkiewicz wrote:
>
> > > Delay is fixed itself in 2.6.31-rc2. Most likely it was platform
> > > specific issue. But lost interrupt still exists. There is log of
> > > 2.6.31-rc2:
> >
> > Thanks for letting us know. When it comes to the lost interrupt
> > issue I still suspect that this is pmac specific problem (though
> > Dave may have some fresh idea about it).
>
> Hard to tell. Those things generally work... maybe something is wrong
> with that disk vs. that timing. Does it work if you move it to the
> other controller (the one to which the CD drive is connected ?)
>
> Cheers,
> Ben.
I tried this drive on ide1 and ide2, there are same issue. This drive worked
on P-III before (as separate on channel, with another hard drive and with cdrom)
and I didn't have any problem with it. There are chunks of dmesg.
On the ide1 channel:
[ 1.585394] MacIO PCI driver attached to Keylargo chipset
[ 1.587134] irq: irq 32 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 32
[ 1.588076] irq: irq 19 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 19
[ 1.588113] irq: irq 11 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 16
[ 1.588449] irq: irq 20 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 20
[ 1.588485] irq: irq 12 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 17
[ 1.588838] irq: irq 5 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 18
[ 1.588873] irq: irq 6 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 21
[ 1.589335] irq: irq 7 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 24
[ 1.589370] irq: irq 8 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 29
[ 1.591439] Uniform Multi-Platform E-IDE driver
[ 1.592362] ide-pmac 0002:20:0d.0: enabling device (0000 -> 0002)
[ 2.610659] ide-pmac: Found Apple UniNorth ATA-6 controller (PCI), bus ID 3, irq 39
[ 2.610777] Probing IDE interface ide0...
[ 2.910841] hda: IBM-IC35L060AVVA07-0, ATA DISK drive
[ 3.631031] hda: host max PIO4 wanted PIO255(auto-tune) selected PIO4
[ 3.631208] hda: UDMA/100 mode selected
[ 3.631484] ide0 at 0xf10c2000-0xf10c2070,0xf10c2160 on irq 39
[ 4.660656] ide-pmac: Found Apple KeyLargo ATA-4 controller (macio), bus ID 2, irq 19
[ 4.660759] Probing IDE interface ide1...
[ 4.960962] hdc: QUANTUM FIREBALLP LM20.5, ATA DISK drive
[ 5.680974] hdc: host max PIO4 wanted PIO255(auto-tune) selected PIO4
[ 5.681248] hdc: UDMA/66 mode selected
[ 5.681698] ide1 at 0xf10ba000-0xf10ba070,0xf10ba160 on irq 19
[ 6.710656] ide-pmac: Found Apple KeyLargo ATA-3 controller (macio), bus ID 0, irq 20
[ 6.710752] Probing IDE interface ide2...
[ 7.311008] ide2 at 0xf10be000-0xf10be070,0xf10be160 on irq 20
[ 7.311361] ide-gd driver 1.18
[ 7.311548] hda: max request size: 128KiB
[ 7.340930] hda: 120103200 sectors (61492 MB) w/1863KiB Cache, CHS=65535/16/63
[ 7.341321] hda: cache flushes supported
[ 7.341637] hda: [mac] hda1 hda2 hda3 hda4
[ 7.354161] hdc: max request size: 128KiB
[ 7.383460] hdc: Host Protected Area detected.
[ 7.383463] current capacity is 40130390 sectors (20546 MB)
[ 7.383467] native capacity is 40132503 sectors (20547 MB)
[ 7.383625] hdc: 40130390 sectors (20546 MB) w/1900KiB Cache, CHS=39811/16/63
[ 7.383721] hdc: cache flushes not supported
[ 7.383965] hdc:
[ 27.380690] ide-pmac lost interrupt, dma status: 8480
[ 27.380754] hdc: lost interrupt
[ 27.380795] hdc: dma_intr: status=0x58 { DriveReady SeekComplete DataRequest }
[ 27.380911] hdc: possibly failed opcode: 0xc8
[ 27.385964] hdc: DMA disabled
[ 27.430645] ide1: reset: success
[ 27.475435] hdc1 hdc2 < hdc5 hdc6 hdc7 hdc8 >
[ 27.533836] ide-cd driver 5.00
On the ide2 channel:
[ 1.594873] MacIO PCI driver attached to Keylargo chipset
[ 1.596780] irq: irq 32 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 32
[ 1.597804] irq: irq 19 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 19
[ 1.597841] irq: irq 11 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 16
[ 1.598208] irq: irq 20 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 20
[ 1.598244] irq: irq 12 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 17
[ 1.598631] irq: irq 5 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 18
[ 1.598666] irq: irq 6 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 21
[ 1.599172] irq: irq 7 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 24
[ 1.599208] irq: irq 8 on host /pci@f2000000/mac-io@17/interrupt-controller@40000 mapped to virtual irq 29
[ 1.601387] Uniform Multi-Platform E-IDE driver
[ 1.602315] ide-pmac 0002:20:0d.0: enabling device (0000 -> 0002)
[ 2.630650] ide-pmac: Found Apple UniNorth ATA-6 controller (PCI), bus ID 3, irq 39
[ 2.630764] Probing IDE interface ide0...
[ 2.930832] hda: IBM-IC35L060AVVA07-0, ATA DISK drive
[ 3.651031] hda: host max PIO4 wanted PIO255(auto-tune) selected PIO4
[ 3.651211] hda: UDMA/100 mode selected
[ 3.651487] ide0 at 0xf10c2000-0xf10c2070,0xf10c2160 on irq 39
[ 4.680647] ide-pmac: Found Apple KeyLargo ATA-4 controller (macio), bus ID 2, irq 19
[ 4.680748] Probing IDE interface ide1...
[ 5.280995] ide1 at 0xf10ba000-0xf10ba070,0xf10ba160 on irq 19
[ 6.310646] ide-pmac: Found Apple KeyLargo ATA-3 controller (macio), bus ID 0, irq 20
[ 6.310740] Probing IDE interface ide2...
[ 6.610828] hde: QUANTUM FIREBALLP LM20.5, ATA DISK drive
[ 7.330944] hde: host max PIO4 wanted PIO255(auto-tune) selected PIO4
[ 7.331214] hde: MWDMA2 mode selected
[ 7.331613] ide2 at 0xf10be000-0xf10be070,0xf10be160 on irq 20
[ 7.332342] ide-gd driver 1.18
[ 7.332527] hda: max request size: 128KiB
[ 7.363393] hda: 120103200 sectors (61492 MB) w/1863KiB Cache, CHS=65535/16/63
[ 7.363743] hda: cache flushes supported
[ 7.364269] hda: [mac] hda1 hda2 hda3 hda4
[ 7.370602] hde: max request size: 128KiB
[ 7.403456] hde: Host Protected Area detected.
[ 7.403460] current capacity is 40130390 sectors (20546 MB)
[ 7.403464] native capacity is 40132503 sectors (20547 MB)
[ 7.403629] hde: 40130390 sectors (20546 MB) w/1900KiB Cache, CHS=39811/16/63
[ 7.403724] hde: cache flushes not supported
[ 7.403978] hde:
[ 27.400744] ide-pmac lost interrupt, dma status: 8480
[ 27.400811] hde: lost interrupt
[ 27.400851] hde: dma_intr: status=0x58 { DriveReady SeekComplete DataRequest }
[ 27.400976] hde: possibly failed opcode: 0xc8
[ 27.403945] hde: DMA disabled
[ 27.450635] ide2: reset: success
[ 27.493588] hde1 hde2 < hde5 hde6 hde7 hde8 >
[ 27.551998] ide-cd driver 5.00
^ permalink raw reply
* How to correctly reassign PCI BARs
From: Gerhard Pircher @ 2009-07-07 21:25 UTC (permalink / raw)
To: linuxppc-dev
Hi,
I'm trying to implement some PCI quirks for the AmigaOne, as the
firmware puts PCI devices with 16 bit BARs too high in the PCI I/O
space (above 64k). Currently I'm just writing new values to the BARs
before the PCI layer actually probes and allocates them:
static void quirk_vt82c686_sound_iobases(struct pci_dev *dev)
{
if (!machine_is(amigaone))
return;
pci_write_config_dword(dev, 0x10, 0x0000dc00);
pci_write_config_dword(dev, 0x14, 0x0000e000);
pci_write_config_dword(dev, 0x18, 0x00000330);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_vt82c686_sound_iobases);
I wonder, if there is a better way to reassign PCI resources. Using
ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC) seems to be an alternative,
but it also relocates the BARs of the IDE controller, which operates
in compatible mode (I would like to keep it in this mode).
Is there a way to take out some PCI devices from the reassignment?
Gerhard
--
GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT!
Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01
^ permalink raw reply
* Re: dma_ops->map_page == NULL
From: Mark Nelson @ 2009-07-08 0:44 UTC (permalink / raw)
To: linuxppc-dev
Cc: Kári Davíðsson, Kumar Gala,
linuxppc-dev@ozlabs.org
In-Reply-To: <1246964905.6066.41.camel@pasglop>
On Tuesday 07 July 2009 21:08:25 Benjamin Herrenschmidt wrote:
> On Tue, 2009-07-07 at 10:15 +1000, Mark Nelson wrote:
> >
> > When the 32 and 64bit DMA code was merged in .28 , map_/unmap_page() was
> > added in favour of map_/unmap_single() (which was later removed in .29)
> > so you'll have to replace your calls to dma_map_single() with
> > dma_map_page(). Just pass it the page and offset rather than the address.
>
> Wait a minute ... dma_map_single() should still work, it will just call
> dma_map_page() underneath. All dma_ops should have a ->map page
> callback.
Sorry my mistake - I was thinking of when we removed the map/unmap_single()
from the dma_mapping_ops.
Mark.
^ permalink raw reply
* Re: Delay on intialization ide subsystem(most likely)
From: Benjamin Herrenschmidt @ 2009-07-08 1:12 UTC (permalink / raw)
To: Andrey Gusev
Cc: linux-ide, petkovbb, David Miller, Bartlomiej Zolnierkiewicz,
linuxppc-dev
In-Reply-To: <20090708011802.74a7c21b@power-debian>
On Wed, 2009-07-08 at 01:18 +0400, Andrey Gusev wrote:
> I tried this drive on ide1 and ide2, there are same issue. This drive worked
> on P-III before (as separate on channel, with another hard drive and with cdrom)
> and I didn't have any problem with it. There are chunks of dmesg.
Wow... It also fails with MWDMA2 ! That's just plain weird. It fails as
master as well as slave too. Hrm. I wonder if it could be your cable...
Do you have other machines (non-powermac) you can try that drive again
just in case it toast itself in some way too ?
Bart, I don't suppose we know of any problem with those drive models ?
(Q. FireballP LM20.5)
Cheers,
Ben.
^ permalink raw reply
* [PATCH v2] powerpc: expose the multi-bit ops that underlie single-bit ops.
From: Geoff Thorpe @ 2009-07-08 1:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Geoff Thorpe
The bitops.h functions that operate on a single bit in a bitfield are
implemented by operating on the corresponding word location. In all
cases the inner logic is valid if the mask being applied has more than
one bit set, so this patch exposes those inner operations. Indeed,
set_bits() was already available, but it duplicated code from
set_bit() (rather than making the latter a wrapper) - it was also
missing the PPC405_ERR77() workaround and the "volatile" address
qualifier present in other APIs. This corrects that, and exposes the
other multi-bit equivalents.
One advantage of these multi-bit forms is that they allow word-sized
variables to essentially be their own spinlocks, eg. very useful for
state machines where an atomic "flags" variable can obviate the need
for any additional locking.
Signed-off-by: Geoff Thorpe <geoff@geoffthorpe.net>
---
arch/powerpc/include/asm/bitops.h | 194 ++++++++++++-------------------------
1 files changed, 61 insertions(+), 133 deletions(-)
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 897eade..56f2f2e 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -56,174 +56,102 @@
#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
+/* Macro for generating the ***_bits() functions */
+#define DEFINE_BITOP(fn, op, prefix, postfix) \
+static __inline__ void fn(unsigned long mask, \
+ volatile unsigned long *_p) \
+{ \
+ unsigned long old; \
+ unsigned long *p = (unsigned long *)_p; \
+ __asm__ __volatile__ ( \
+ prefix \
+"1:" PPC_LLARX "%0,0,%3\n" \
+ stringify_in_c(op) "%0,%0,%2\n" \
+ PPC405_ERR77(0,%3) \
+ PPC_STLCX "%0,0,%3\n" \
+ "bne- 1b\n" \
+ postfix \
+ : "=&r" (old), "+m" (*p) \
+ : "r" (mask), "r" (p) \
+ : "cc", "memory"); \
+}
+
+DEFINE_BITOP(set_bits, or, "", "")
+DEFINE_BITOP(clear_bits, andc, "", "")
+DEFINE_BITOP(clear_bits_unlock, andc, LWSYNC_ON_SMP, "")
+DEFINE_BITOP(change_bits, xor, "", "")
+
static __inline__ void set_bit(int nr, volatile unsigned long *addr)
{
- unsigned long old;
- unsigned long mask = BITOP_MASK(nr);
- unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
- __asm__ __volatile__(
-"1:" PPC_LLARX "%0,0,%3 # set_bit\n"
- "or %0,%0,%2\n"
- PPC405_ERR77(0,%3)
- PPC_STLCX "%0,0,%3\n"
- "bne- 1b"
- : "=&r" (old), "+m" (*p)
- : "r" (mask), "r" (p)
- : "cc" );
+ set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
}
static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
{
- unsigned long old;
- unsigned long mask = BITOP_MASK(nr);
- unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
- __asm__ __volatile__(
-"1:" PPC_LLARX "%0,0,%3 # clear_bit\n"
- "andc %0,%0,%2\n"
- PPC405_ERR77(0,%3)
- PPC_STLCX "%0,0,%3\n"
- "bne- 1b"
- : "=&r" (old), "+m" (*p)
- : "r" (mask), "r" (p)
- : "cc" );
+ clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
}
static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
{
- unsigned long old;
- unsigned long mask = BITOP_MASK(nr);
- unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
- __asm__ __volatile__(
- LWSYNC_ON_SMP
-"1:" PPC_LLARX "%0,0,%3 # clear_bit_unlock\n"
- "andc %0,%0,%2\n"
- PPC405_ERR77(0,%3)
- PPC_STLCX "%0,0,%3\n"
- "bne- 1b"
- : "=&r" (old), "+m" (*p)
- : "r" (mask), "r" (p)
- : "cc", "memory");
+ clear_bits_unlock(BITOP_MASK(nr), addr + BITOP_WORD(nr));
}
static __inline__ void change_bit(int nr, volatile unsigned long *addr)
{
- unsigned long old;
- unsigned long mask = BITOP_MASK(nr);
- unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
- __asm__ __volatile__(
-"1:" PPC_LLARX "%0,0,%3 # change_bit\n"
- "xor %0,%0,%2\n"
- PPC405_ERR77(0,%3)
- PPC_STLCX "%0,0,%3\n"
- "bne- 1b"
- : "=&r" (old), "+m" (*p)
- : "r" (mask), "r" (p)
- : "cc" );
+ change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
+}
+
+/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
+ * operands. */
+#define DEFINE_TESTOP(fn, op, prefix, postfix) \
+static __inline__ unsigned long fn( \
+ unsigned long mask, \
+ volatile unsigned long *_p) \
+{ \
+ unsigned long old, t; \
+ unsigned long *p = (unsigned long *)_p; \
+ __asm__ __volatile__ ( \
+ prefix \
+"1:" PPC_LLARX "%0,0,%3\n" \
+ stringify_in_c(op) "%1,%0,%2\n" \
+ PPC405_ERR77(0,%3) \
+ PPC_STLCX "%1,0,%3\n" \
+ "bne- 1b\n" \
+ postfix \
+ : "=&r" (old), "=&r" (t) \
+ : "r" (mask), "r" (p) \
+ : "cc", "memory"); \
+ return (old & mask); \
}
+DEFINE_TESTOP(test_and_set_bits, or, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_set_bits_lock, or, "", ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_clear_bits, andc, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_change_bits, xor, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+
static __inline__ int test_and_set_bit(unsigned long nr,
volatile unsigned long *addr)
{
- unsigned long old, t;
- unsigned long mask = BITOP_MASK(nr);
- unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
- __asm__ __volatile__(
- LWSYNC_ON_SMP
-"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n"
- "or %1,%0,%2 \n"
- PPC405_ERR77(0,%3)
- PPC_STLCX "%1,0,%3 \n"
- "bne- 1b"
- ISYNC_ON_SMP
- : "=&r" (old), "=&r" (t)
- : "r" (mask), "r" (p)
- : "cc", "memory");
-
- return (old & mask) != 0;
+ return test_and_set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
}
static __inline__ int test_and_set_bit_lock(unsigned long nr,
volatile unsigned long *addr)
{
- unsigned long old, t;
- unsigned long mask = BITOP_MASK(nr);
- unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
- __asm__ __volatile__(
-"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit_lock\n"
- "or %1,%0,%2 \n"
- PPC405_ERR77(0,%3)
- PPC_STLCX "%1,0,%3 \n"
- "bne- 1b"
- ISYNC_ON_SMP
- : "=&r" (old), "=&r" (t)
- : "r" (mask), "r" (p)
- : "cc", "memory");
-
- return (old & mask) != 0;
+ return test_and_set_bits_lock(BITOP_MASK(nr),
+ addr + BITOP_WORD(nr)) != 0;
}
static __inline__ int test_and_clear_bit(unsigned long nr,
volatile unsigned long *addr)
{
- unsigned long old, t;
- unsigned long mask = BITOP_MASK(nr);
- unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
- __asm__ __volatile__(
- LWSYNC_ON_SMP
-"1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n"
- "andc %1,%0,%2 \n"
- PPC405_ERR77(0,%3)
- PPC_STLCX "%1,0,%3 \n"
- "bne- 1b"
- ISYNC_ON_SMP
- : "=&r" (old), "=&r" (t)
- : "r" (mask), "r" (p)
- : "cc", "memory");
-
- return (old & mask) != 0;
+ return test_and_clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
}
static __inline__ int test_and_change_bit(unsigned long nr,
volatile unsigned long *addr)
{
- unsigned long old, t;
- unsigned long mask = BITOP_MASK(nr);
- unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
- __asm__ __volatile__(
- LWSYNC_ON_SMP
-"1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n"
- "xor %1,%0,%2 \n"
- PPC405_ERR77(0,%3)
- PPC_STLCX "%1,0,%3 \n"
- "bne- 1b"
- ISYNC_ON_SMP
- : "=&r" (old), "=&r" (t)
- : "r" (mask), "r" (p)
- : "cc", "memory");
-
- return (old & mask) != 0;
-}
-
-static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
-{
- unsigned long old;
-
- __asm__ __volatile__(
-"1:" PPC_LLARX "%0,0,%3 # set_bits\n"
- "or %0,%0,%2\n"
- PPC_STLCX "%0,0,%3\n"
- "bne- 1b"
- : "=&r" (old), "+m" (*addr)
- : "r" (mask), "r" (addr)
- : "cc");
+ return test_and_change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
}
#include <asm-generic/bitops/non-atomic.h>
--
1.6.0.4
^ permalink raw reply related
* Re: [PATCH] net: fix OF fixed-link property handling on Freescale network device drivers
From: David Miller @ 2009-07-08 2:16 UTC (permalink / raw)
To: avorontsov; +Cc: netdev, leoli, afleming, linuxppc-dev
In-Reply-To: <20090707151241.GA26831@oksana.dev.rtsoft.ru>
From: Anton Vorontsov <avorontsov@ru.mvista.com>
Date: Tue, 7 Jul 2009 19:12:41 +0400
> ->restart() will dereference phydev, which is NULL.
>
> grep for 'phydev' in fs_enet/mac-*.c.
Ok, so this patch still needs a little bit more work.
Thanks for testing!
^ permalink raw reply
* Re: [PATCH] ucc_geth: Add support for skb recycling
From: David Miller @ 2009-07-08 2:23 UTC (permalink / raw)
To: avorontsov; +Cc: netdev, leoli, afleming, linuxppc-dev
In-Reply-To: <20090707183842.GA8425@oksana.dev.rtsoft.ru>
From: Anton Vorontsov <avorontsov@ru.mvista.com>
Date: Tue, 7 Jul 2009 22:38:42 +0400
> We can reclaim transmitted skbs to use in the receive path, so-called
> skb recycling support.
>
> Also reorder ucc_geth_poll() steps, so that we'll clean tx ring firstly,
> thus maybe reclaim some skbs for rx.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Applied to net-next-2.6
^ permalink raw reply
* Re: [PATCH v2] powerpc: expose the multi-bit ops that underlie single-bit ops.
From: Benjamin Herrenschmidt @ 2009-07-08 2:55 UTC (permalink / raw)
To: Geoff Thorpe; +Cc: linuxppc-dev
In-Reply-To: <1247016236-3520-1-git-send-email-geoff@geoffthorpe.net>
On Tue, 2009-07-07 at 21:23 -0400, Geoff Thorpe wrote:
> The bitops.h functions that operate on a single bit in a bitfield are
> implemented by operating on the corresponding word location. In all
> cases the inner logic is valid if the mask being applied has more than
> one bit set, so this patch exposes those inner operations. Indeed,
> set_bits() was already available, but it duplicated code from
> set_bit() (rather than making the latter a wrapper) - it was also
> missing the PPC405_ERR77() workaround and the "volatile" address
> qualifier present in other APIs. This corrects that, and exposes the
> other multi-bit equivalents.
>
> One advantage of these multi-bit forms is that they allow word-sized
> variables to essentially be their own spinlocks, eg. very useful for
> state machines where an atomic "flags" variable can obviate the need
> for any additional locking.
Ack. I'll stick that into my -next branch as soon as it's ready.
Cheers,
Ben.
> Signed-off-by: Geoff Thorpe <geoff@geoffthorpe.net>
> ---
> arch/powerpc/include/asm/bitops.h | 194 ++++++++++++-------------------------
> 1 files changed, 61 insertions(+), 133 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
> index 897eade..56f2f2e 100644
> --- a/arch/powerpc/include/asm/bitops.h
> +++ b/arch/powerpc/include/asm/bitops.h
> @@ -56,174 +56,102 @@
> #define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
> #define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
>
> +/* Macro for generating the ***_bits() functions */
> +#define DEFINE_BITOP(fn, op, prefix, postfix) \
> +static __inline__ void fn(unsigned long mask, \
> + volatile unsigned long *_p) \
> +{ \
> + unsigned long old; \
> + unsigned long *p = (unsigned long *)_p; \
> + __asm__ __volatile__ ( \
> + prefix \
> +"1:" PPC_LLARX "%0,0,%3\n" \
> + stringify_in_c(op) "%0,%0,%2\n" \
> + PPC405_ERR77(0,%3) \
> + PPC_STLCX "%0,0,%3\n" \
> + "bne- 1b\n" \
> + postfix \
> + : "=&r" (old), "+m" (*p) \
> + : "r" (mask), "r" (p) \
> + : "cc", "memory"); \
> +}
> +
> +DEFINE_BITOP(set_bits, or, "", "")
> +DEFINE_BITOP(clear_bits, andc, "", "")
> +DEFINE_BITOP(clear_bits_unlock, andc, LWSYNC_ON_SMP, "")
> +DEFINE_BITOP(change_bits, xor, "", "")
> +
> static __inline__ void set_bit(int nr, volatile unsigned long *addr)
> {
> - unsigned long old;
> - unsigned long mask = BITOP_MASK(nr);
> - unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
> -
> - __asm__ __volatile__(
> -"1:" PPC_LLARX "%0,0,%3 # set_bit\n"
> - "or %0,%0,%2\n"
> - PPC405_ERR77(0,%3)
> - PPC_STLCX "%0,0,%3\n"
> - "bne- 1b"
> - : "=&r" (old), "+m" (*p)
> - : "r" (mask), "r" (p)
> - : "cc" );
> + set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
> }
>
> static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
> {
> - unsigned long old;
> - unsigned long mask = BITOP_MASK(nr);
> - unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
> -
> - __asm__ __volatile__(
> -"1:" PPC_LLARX "%0,0,%3 # clear_bit\n"
> - "andc %0,%0,%2\n"
> - PPC405_ERR77(0,%3)
> - PPC_STLCX "%0,0,%3\n"
> - "bne- 1b"
> - : "=&r" (old), "+m" (*p)
> - : "r" (mask), "r" (p)
> - : "cc" );
> + clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
> }
>
> static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
> {
> - unsigned long old;
> - unsigned long mask = BITOP_MASK(nr);
> - unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
> -
> - __asm__ __volatile__(
> - LWSYNC_ON_SMP
> -"1:" PPC_LLARX "%0,0,%3 # clear_bit_unlock\n"
> - "andc %0,%0,%2\n"
> - PPC405_ERR77(0,%3)
> - PPC_STLCX "%0,0,%3\n"
> - "bne- 1b"
> - : "=&r" (old), "+m" (*p)
> - : "r" (mask), "r" (p)
> - : "cc", "memory");
> + clear_bits_unlock(BITOP_MASK(nr), addr + BITOP_WORD(nr));
> }
>
> static __inline__ void change_bit(int nr, volatile unsigned long *addr)
> {
> - unsigned long old;
> - unsigned long mask = BITOP_MASK(nr);
> - unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
> -
> - __asm__ __volatile__(
> -"1:" PPC_LLARX "%0,0,%3 # change_bit\n"
> - "xor %0,%0,%2\n"
> - PPC405_ERR77(0,%3)
> - PPC_STLCX "%0,0,%3\n"
> - "bne- 1b"
> - : "=&r" (old), "+m" (*p)
> - : "r" (mask), "r" (p)
> - : "cc" );
> + change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
> +}
> +
> +/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
> + * operands. */
> +#define DEFINE_TESTOP(fn, op, prefix, postfix) \
> +static __inline__ unsigned long fn( \
> + unsigned long mask, \
> + volatile unsigned long *_p) \
> +{ \
> + unsigned long old, t; \
> + unsigned long *p = (unsigned long *)_p; \
> + __asm__ __volatile__ ( \
> + prefix \
> +"1:" PPC_LLARX "%0,0,%3\n" \
> + stringify_in_c(op) "%1,%0,%2\n" \
> + PPC405_ERR77(0,%3) \
> + PPC_STLCX "%1,0,%3\n" \
> + "bne- 1b\n" \
> + postfix \
> + : "=&r" (old), "=&r" (t) \
> + : "r" (mask), "r" (p) \
> + : "cc", "memory"); \
> + return (old & mask); \
> }
>
> +DEFINE_TESTOP(test_and_set_bits, or, LWSYNC_ON_SMP, ISYNC_ON_SMP)
> +DEFINE_TESTOP(test_and_set_bits_lock, or, "", ISYNC_ON_SMP)
> +DEFINE_TESTOP(test_and_clear_bits, andc, LWSYNC_ON_SMP, ISYNC_ON_SMP)
> +DEFINE_TESTOP(test_and_change_bits, xor, LWSYNC_ON_SMP, ISYNC_ON_SMP)
> +
> static __inline__ int test_and_set_bit(unsigned long nr,
> volatile unsigned long *addr)
> {
> - unsigned long old, t;
> - unsigned long mask = BITOP_MASK(nr);
> - unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
> -
> - __asm__ __volatile__(
> - LWSYNC_ON_SMP
> -"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n"
> - "or %1,%0,%2 \n"
> - PPC405_ERR77(0,%3)
> - PPC_STLCX "%1,0,%3 \n"
> - "bne- 1b"
> - ISYNC_ON_SMP
> - : "=&r" (old), "=&r" (t)
> - : "r" (mask), "r" (p)
> - : "cc", "memory");
> -
> - return (old & mask) != 0;
> + return test_and_set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
> }
>
> static __inline__ int test_and_set_bit_lock(unsigned long nr,
> volatile unsigned long *addr)
> {
> - unsigned long old, t;
> - unsigned long mask = BITOP_MASK(nr);
> - unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
> -
> - __asm__ __volatile__(
> -"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit_lock\n"
> - "or %1,%0,%2 \n"
> - PPC405_ERR77(0,%3)
> - PPC_STLCX "%1,0,%3 \n"
> - "bne- 1b"
> - ISYNC_ON_SMP
> - : "=&r" (old), "=&r" (t)
> - : "r" (mask), "r" (p)
> - : "cc", "memory");
> -
> - return (old & mask) != 0;
> + return test_and_set_bits_lock(BITOP_MASK(nr),
> + addr + BITOP_WORD(nr)) != 0;
> }
>
> static __inline__ int test_and_clear_bit(unsigned long nr,
> volatile unsigned long *addr)
> {
> - unsigned long old, t;
> - unsigned long mask = BITOP_MASK(nr);
> - unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
> -
> - __asm__ __volatile__(
> - LWSYNC_ON_SMP
> -"1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n"
> - "andc %1,%0,%2 \n"
> - PPC405_ERR77(0,%3)
> - PPC_STLCX "%1,0,%3 \n"
> - "bne- 1b"
> - ISYNC_ON_SMP
> - : "=&r" (old), "=&r" (t)
> - : "r" (mask), "r" (p)
> - : "cc", "memory");
> -
> - return (old & mask) != 0;
> + return test_and_clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
> }
>
> static __inline__ int test_and_change_bit(unsigned long nr,
> volatile unsigned long *addr)
> {
> - unsigned long old, t;
> - unsigned long mask = BITOP_MASK(nr);
> - unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
> -
> - __asm__ __volatile__(
> - LWSYNC_ON_SMP
> -"1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n"
> - "xor %1,%0,%2 \n"
> - PPC405_ERR77(0,%3)
> - PPC_STLCX "%1,0,%3 \n"
> - "bne- 1b"
> - ISYNC_ON_SMP
> - : "=&r" (old), "=&r" (t)
> - : "r" (mask), "r" (p)
> - : "cc", "memory");
> -
> - return (old & mask) != 0;
> -}
> -
> -static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
> -{
> - unsigned long old;
> -
> - __asm__ __volatile__(
> -"1:" PPC_LLARX "%0,0,%3 # set_bits\n"
> - "or %0,%0,%2\n"
> - PPC_STLCX "%0,0,%3\n"
> - "bne- 1b"
> - : "=&r" (old), "+m" (*addr)
> - : "r" (mask), "r" (addr)
> - : "cc");
> + return test_and_change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
> }
>
> #include <asm-generic/bitops/non-atomic.h>
^ permalink raw reply
* Re: ALSA fixes for non-coherent ppc32 again
From: Benjamin Herrenschmidt @ 2009-07-08 3:01 UTC (permalink / raw)
To: Gerhard Pircher; +Cc: Takashi Iwai, linuxppc-dev
In-Reply-To: <1245623678.16880.27.camel@pasglop>
On Mon, 2009-06-22 at 08:34 +1000, Benjamin Herrenschmidt wrote:
> On Sun, 2009-06-21 at 20:18 +0200, Gerhard Pircher wrote:
> > Hi,
> >
> > Takashi Iwai posted patches to make ALSA work on non-coherent PPC32
> > systems (almost exactly) a year ago. See here:
> > http://www.nabble.com/-PATCH-0-3--ALSA-fixes-for-non-coherent-ppc32-to17980027.html#a17980027
> >
> > As far as I can see these patches never went upstream. Where there any
> > objections or did we just forget about them? It would be cool, if the
> > patches could be merged now, as at least two platforms need this bugfix
> > (namely Sam440 and AmigaOne).
>
> I definitely forgot about those... But I'm fine with what Takashi did
> for now, I can always make the powerpc helper for dma_mmap_coherent()
> smarter later on if necessary.
BTW. Can you guys send a "final" patch for adding mmap_coherent to
powerpc ? Please make so that the dma_mmap_coherent() function doesn't
explose if dma_ops->mmap_coherent is NULL though (either fail gracefully
or fallback to some standard mmap).
Note that we probably need to add the virtual address too. IE. On
platforms with an iommu, we cannot easily go back from the dma_addr_t to
the memory address, it's easier to do that from the virtual address in
fact.
Cheers,
Ben.
^ permalink raw reply
* [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2009-07-08 6:26 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, Andrew Morton, Linux Kernel list
Hi Linus !
Here are a bunch of minor powerpc updates for 2.6.31. Mostly a few
more alloc_bootmem -> km/zalloc changes to avoid warnings at boot,
a bug or two, minor cosmetic stuffs, and some changes of a whole
bunch of pr_debug() into pr_devel() for low level stuff that really
doesn't want those built in normal kernels.
Cheers,
Ben.
The following changes since commit faf80d62e44dc627efb741f48db50c1858d1667c:
Linus Torvalds (1):
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/.../tip/linux-2.6-tip
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
Anton Vorontsov (1):
powerpc: Don't use alloc_bootmem() in init_IRQ() path
Benjamin Herrenschmidt (1):
Merge commit 'jwb/merge' into merge
Grant Likely (1):
powerpc: Fix spin_event_timeout() to be robust over context switches
Huang Weiyi (1):
powerpc/perf_counter: Remove duplicated #include
Joe Perches (1):
powerpc: Remove unnecessary semicolons
Josh Boyer (1):
powerpc/44x: Fix build error with -Werror for Warp platform
Michael Ellerman (7):
powerpc/pseries: Use pr_devel() in pseries LPAR HPTE routines
powerpc/pseries: Use pr_devel() in xics.c
powerpc: Use pr_devel() in arch/powerpc/mm/mmu_context_nohash.c
powerpc: Cleanup & use pr_devel() in arch/powerpc/mm/slb.c
powerpc: Use pr_devel() in arch/powerpc/mm/gup.c
powerpc/cell: Use pr_devel() in axon_msi.c
powerpc: Use pr_devel() in do_dcache_icache_coherency()
Sean MacLennan (2):
powerpc/44x: Update Warp defconfig
powerpc/4xx: Have Warp take advantage of GPIO LEDs default-state = keep
arch/powerpc/boot/dts/warp.dts | 3 +-
arch/powerpc/configs/44x/warp_defconfig | 200 ++++++++++++++++++++------
arch/powerpc/include/asm/delay.h | 2 +
arch/powerpc/kernel/mpc7450-pmu.c | 1 -
arch/powerpc/kernel/ppc970-pmu.c | 1 -
arch/powerpc/mm/gup.c | 10 +-
arch/powerpc/mm/mmu_context_nohash.c | 16 +-
arch/powerpc/mm/pgtable.c | 4 +-
arch/powerpc/mm/slb.c | 13 +--
arch/powerpc/mm/tlb_hash64.c | 2 +-
arch/powerpc/oprofile/cell/vma_map.c | 2 +-
arch/powerpc/platforms/44x/warp.c | 19 +--
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 2 +-
arch/powerpc/platforms/cell/axon_msi.c | 22 ++--
arch/powerpc/platforms/powermac/cpufreq_64.c | 2 +-
arch/powerpc/platforms/powermac/pic.c | 2 +-
arch/powerpc/platforms/ps3/system-bus.c | 1 -
arch/powerpc/platforms/pseries/lpar.c | 18 ++--
arch/powerpc/platforms/pseries/xics.c | 8 +-
arch/powerpc/sysdev/fsl_rio.c | 2 +-
arch/powerpc/sysdev/ipic.c | 4 +-
arch/powerpc/sysdev/mpic.c | 9 +-
arch/powerpc/sysdev/ppc4xx_pci.c | 4 +-
arch/powerpc/sysdev/qe_lib/qe_ic.c | 4 +-
arch/powerpc/sysdev/uic.c | 3 +-
25 files changed, 225 insertions(+), 129 deletions(-)
^ permalink raw reply
* Re: Chipselect in SPI binding with mpc5200-psc-spi
From: Henk Stegeman @ 2009-07-08 13:07 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <fa686aa40907070857m5b604f6fk9bd9301997938b37@mail.gmail.com>
It now works, in the dts
interrupt-controller =3D < &gpt6 >; // Use GPT6 as
should have been
interrupt-parent =3D < &gpt6 >; // Use GPT6 as
On Tue, Jul 7, 2009 at 5:57 PM, Grant Likely<grant.likely@secretlab.ca> wro=
te:
> On Tue, Jul 7, 2009 at 8:31 AM, Henk Stegeman<henk.stegeman@gmail.com> wr=
ote:
>> I tried to make use of the irq-controller mode of the GPT as
>> suggested, however I'm not getting the IRQ.
>> Does anyone have an idea what I could be missing? (I've been testing
>> with 2.6.30).
>
> Make sure the 5200 general purpose timer driver is compiled in (not a mod=
ule).
>
>>
>>
>> The driver reports from it's probe:
>> [ =A0 =A01.502853] spi_master spi32766.0 Unable to get sample IRQ from o=
f
>>
>> My driver has:
>> =A0 =A0 =A0 =A0pdata->sample_irq =3D irq_of_parse_and_map(np, 0);
>> =A0 =A0 =A0 =A0if (pdata->sample_irq =3D=3D NO_IRQ) {
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0ret =3D pdata->sample_irq;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dev_err(dev, "Unable to get sample IRQ fr=
om of\n");
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0..
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
>>
>>
>> My dts has:
>> =A0 =A0 =A0 =A0gpt6: timer@660 { =A0 =A0 =A0 // General Purpose Timer GP=
T6 in GPIO mode for
>> SMC4000IO sample irq.
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-controller;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0#interrupt-cells =3D <1>;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc5200b-gpt","fsl,mp=
c5200-gpt";
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x660 0x10>;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <1 15 0>;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D <&mpc5200_pic>;
>> =A0 =A0 =A0 =A0};
>>
>>
>> =A0 =A0 =A0 =A0io-controller@0 {
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "microkey,smc4000io";
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0linux,modalias =3D "of_smc4000io";
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0spi-max-frequency =3D <800000>;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0spi-cpha;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0>;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0word-delay-us =3D <30>;
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-controller =3D <&gpt6>; // Use =
GPT6 as the IRQ controller
>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2>; // And make it edge f=
alling
>> =A0 =A0 =A0 =A0};
>>
>>
>> Thanks in advance,
>>
>> Henk.
>>
>> On Fri, Feb 13, 2009 at 5:19 PM, Grant Likely<grant.likely@secretlab.ca>=
wrote:
>>> On Fri, Feb 13, 2009 at 3:40 AM, Henk Stegeman <henk.stegeman@gmail.com=
> wrote:
>>>> I'm busy adding support for slave deviced behind mpc52xx-psc-spi.
>>>> One complication I have is that my SPI slave device has an interrupt o=
utput
>>>> to the CPU.
>>>> My idea is to add it as a gpios property in the slave device's
>>>> configuration:
>>>>
>>>> =A0 =A0 =A0 =A0 spi@2400 { =A0 =A0 =A0 =A0// PSC3 (SPI IF to the IO-co=
ntroller )
>>>> =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "spi";
>>>> =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <0>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5200-psc-spi","fsl,mpc5=
200b-psc-spi";
>>>> =A0 =A0 =A0 =A0 =A0 =A0 cell-index =3D <2>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x2400 0x100>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 interrupts =3D <2 3 0>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 interrupt-parent =3D <&mpc5200_pic>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 gpios =3D <&gpt4 0 0>;
>>>>
>>>> =A0 =A0 =A0 =A0 =A0 =A0 io-controller@0 {
>>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "microkey,smc4000io";
>>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 spi-max-frequency =3D <1000000>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 // gpios: first is IRQ to cpu
>>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 gpios =3D <&gpt6 0 0>;
>>>> =A0 =A0 =A0 =A0 =A0 =A0 };
>>>
>>> There is a better way to do this, and driver support for it is
>>> currently merged into Ben Herrenschmidt's -next tree.
>>>
>>> Do this instead:
>>> =A0 =A0 =A0 =A0io-controller@0 {
>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "microkey,smc4000io";
>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0spi-max-frequency =3D <1000000>;
>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0>;
>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-controller =3D < &gpt6 >; =A0 =
=A0 // Use GPT6 as
>>> the IRQ controller
>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D < 1 >; =A0 =A0// And make=
it rising edge.
>>> =A0 =A0 =A0 =A0};
>>>
>>> Then add these two properties to the GPT node:
>>>
>>> =A0 =A0 =A0 =A0interrupt-controller;
>>> =A0 =A0 =A0 =A0#interrupt-cells =3D <1>;
>>>
>>> Then you can use normal irq_of_parse_and_map() to set up your handler.
>>>
>>>> How should I then register my spi slave driver? My smc4000io_probe fun=
ction
>>>> gets called correctly by of_spi support but when I register as follows=
:
>>>>
>>>> static struct spi_driver smc4000io_driver =3D {
>>>> =A0 =A0 .driver =3D {
>>>> =A0 =A0 =A0 =A0 .name =A0 =A0=3D "smc4000io",
>>>> =A0 =A0 =A0 =A0 .bus =A0 =A0=3D &spi_bus_type,
>>>> =A0 =A0 =A0 =A0 .owner =A0 =A0=3D THIS_MODULE,
>>>> =A0 =A0 },
>>>> =A0 =A0 .probe =A0 =A0 =A0 =A0=3D smc4000io_probe,
>>>> =A0 =A0 .remove =A0 =A0 =A0 =A0=3D __devexit_p(smc4000io_remove),
>>>> };
>>>>
>>>> static int __init smc4000io_init(void)
>>>> {
>>>> =A0 =A0 return spi_register_driver(&smc4000io_driver);
>>>> }
>>>>
>>>> static void __exit smc4000io_exit(void)
>>>> {
>>>> =A0 =A0 spi_unregister_driver(&smc4000io_driver);
>>>> }
>>>>
>>>> module_init(smc4000io_init);
>>>
>>> Yes, this is right. =A0The psc_spi driver automatically registers all
>>> spi children that it finds in the device tree onto the SPI bus.
>>> Therefore registering an spi_driver() is the right thing to do.
>>>
>>>> But when I do:
>>>>
>>>> static struct of_platform_driver smc4000_spi_of_driver =3D {
>>>> =A0 =A0 .name =3D "smc4000io",
>>>> =A0 =A0 .match_table =3D smc4000io_of_match,
>>>> =A0 =A0 .probe =3D smc4000io_of_probe,
>>>> =A0 =A0 .remove =A0 =A0 =A0 =A0=3D __devexit_p(smc4000io_of_remove),
>>>> };
>>>>
>>>> static int __init smc4000io_init(void)
>>>> {
>>>> =A0 =A0 return of_register_platform_driver(&smc4000_spi_of_driver);
>>>> }
>>>> module_init(smc4000io_init);
>>>>
>>>> Then my smc4000io_of_probe function never gets called.
>>>
>>> Correct. =A0of_platform_driver isn't useful in this case because the
>>> device cannot exist independently of the SPI bus. =A0Plus an
>>> of_platform_device doesn't provide any information about the SPI bus
>>> itself.
>>>
>>> g.
>>>
>>> --
>>> Grant Likely, B.Sc., P.Eng.
>>> Secret Lab Technologies Ltd.
>>>
>>
>
>
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>
^ permalink raw reply
* Re: ALSA fixes for non-coherent ppc32 again
From: Takashi Iwai @ 2009-07-08 14:13 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1247022110.6066.65.camel@pasglop>
At Wed, 08 Jul 2009 13:01:50 +1000,
Benjamin Herrenschmidt wrote:
>=20
> On Mon, 2009-06-22 at 08:34 +1000, Benjamin Herrenschmidt wrote:
> > On Sun, 2009-06-21 at 20:18 +0200, Gerhard Pircher wrote:
> > > Hi,
> > >=20
> > > Takashi Iwai posted patches to make ALSA work on non-coherent PPC32
> > > systems (almost exactly) a year ago. See here:
> > > http://www.nabble.com/-PATCH-0-3--ALSA-fixes-for-non-coherent-ppc32-t=
o17980027.html#a17980027
> > >=20
> > > As far as I can see these patches never went upstream. Where there any
> > > objections or did we just forget about them? It would be cool, if the
> > > patches could be merged now, as at least two platforms need this bugf=
ix
> > > (namely Sam440 and AmigaOne).
> >=20
> > I definitely forgot about those... But I'm fine with what Takashi did
> > for now, I can always make the powerpc helper for dma_mmap_coherent()
> > smarter later on if necessary.
>=20
> BTW. Can you guys send a "final" patch for adding mmap_coherent to
> powerpc ? Please make so that the dma_mmap_coherent() function doesn't
> explose if dma_ops->mmap_coherent is NULL though (either fail gracefully
> or fallback to some standard mmap).
The attached is the revised patch. It falls backs to the standard
mmap.
The whole patch series are found in test/dma-fix branch of sound git
tree below:
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6.git test/dm=
a-fix
I had no time to play cross-build yet, so it'd be helpful if someone
can test it...
(BTW, any good minimal gcc and binutils package for kernel builds for
PPC32?)
> Note that we probably need to add the virtual address too. IE. On
> platforms with an iommu, we cannot easily go back from the dma_addr_t to
> the memory address, it's easier to do that from the virtual address in
> fact.
Yes, the virtual address is passed as well. Which parameter to be
used is just a matter of arch-specific implementation.
thanks,
Takashi
=3D=3D=3D
=46rom a8cb7ed04595785d902d3ad20ba2fe5ccbe31690 Mon Sep 17 00:00:00 2001
From: Takashi Iwai <tiwai@suse.de>
Date: Wed, 8 Jul 2009 11:35:56 +0200
Subject: [PATCH] powerpc: implement dma_mmap_coherent()
A lazy version of dma_mmap_coherent() implementation for powerpc.
The standard mmap is used as a fallback.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
---
arch/powerpc/include/asm/dma-mapping.h | 22 ++++++++++++++++++++++
arch/powerpc/kernel/dma.c | 21 +++++++++++++++++++++
2 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/=
asm/dma-mapping.h
index b44aaab..030a4b1 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -105,6 +105,10 @@ struct dma_mapping_ops {
struct scatterlist *sg, int nelems,
enum dma_data_direction direction);
#endif
+ int (*mmap_coherent)(struct device *hwdev,
+ struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_handle,
+ size_t size);
};
=20
/*
@@ -415,6 +419,24 @@ static inline void dma_sync_single_range_for_device(st=
ruct device *dev,
}
#endif
=20
+#define ARCH_HAS_DMA_MMAP_COHERENT
+static inline int dma_mmap_coherent(struct device *dev,
+ struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_handle,
+ size_t size)
+{
+ struct dma_mapping_ops *dma_ops =3D get_dma_ops(dev);
+
+ BUG_ON(!dma_ops);
+
+ if (dma_ops->mmap_coherent)
+ return dma_ops->mmap_coherent(dev, vma, cpu_addr, dma_handle,
+ size);
+ else
+ return dma_direct_ops.mmap_coherent(dev, vma, cpu_addr,
+ dma_handle, size);
+}
+
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_add=
r)
{
#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 20a60d6..d11db99 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -140,6 +140,26 @@ static inline void dma_direct_sync_single_range(struct=
device *dev,
}
#endif
=20
+static int dma_direct_mmap_coherent(struct device *dev,
+ struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_handle,
+ size_t size)
+{
+ unsigned long pfn;
+#ifdef CONFIG_NOT_COHERENT_CACHE
+ dma_handle -=3D get_dma_direct_offset(dev);
+ /* assume dma_handle set via pfn_to_phys() in
+ * mm/dma-noncoherent.c
+ */
+ pfn =3D dma_handle >> PAGE_SHIFT;
+#else
+ pfn =3D page_to_pfn(virt_to_page(cpu_addr));
+#endif
+ vma->vm_page_prot =3D pgprot_noncached(vma->vm_page_prot);
+ return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
+ size, vma->vm_page_prot);
+}
+
struct dma_mapping_ops dma_direct_ops =3D {
.alloc_coherent =3D dma_direct_alloc_coherent,
.free_coherent =3D dma_direct_free_coherent,
@@ -154,5 +174,6 @@ struct dma_mapping_ops dma_direct_ops =3D {
.sync_sg_for_cpu =3D dma_direct_sync_sg,
.sync_sg_for_device =3D dma_direct_sync_sg,
#endif
+ .mmap_coherent =3D dma_direct_mmap_coherent,
};
EXPORT_SYMBOL(dma_direct_ops);
--=20
1.6.3.2
^ permalink raw reply related
* Re: ALSA fixes for non-coherent ppc32 again
From: Takashi Iwai @ 2009-07-08 14:14 UTC (permalink / raw)
To: Gerhard Pircher; +Cc: linuxppc-dev
In-Reply-To: <20090626131454.246580@gmx.net>
At Fri, 26 Jun 2009 15:14:54 +0200,
Gerhard Pircher wrote:
>
>
> -------- Original-Nachricht --------
> > Datum: Wed, 24 Jun 2009 11:47:13 +0200
> > Von: Takashi Iwai <tiwai@suse.de>
> > An: "Gerhard Pircher" <gerhard_pircher@gmx.net>
> > CC: benh@kernel.crashing.org, linuxppc-dev@ozlabs.org
> > Betreff: Re: ALSA fixes for non-coherent ppc32 again
>
> > At Wed, 24 Jun 2009 10:46:01 +0200,
> > Gerhard Pircher wrote:
> > >
> > >
> > > -------- Original-Nachricht --------
> > > > Datum: Tue, 23 Jun 2009 23:42:24 +0200
> > > > Von: "Gerhard Pircher" <gerhard_pircher@gmx.net>
> > > > An: benh@kernel.crashing.org, tiwai@suse.de
> > > > CC: linuxppc-dev@ozlabs.org
> > > > Betreff: Re: ALSA fixes for non-coherent ppc32 again
> > >
> > > > Okay, that's wrong. I somehow messed up the .config file. It doesn't
> > > > compile, too.
> > > I got it to compile now and it seems to work fine. I overlooked a typo
> > > in sound/core/Makefile first (ifndef CONFIG_SND_NONCOHERNT_DMA.)
> >
> > Gah, thanks, fixed now on the git tree too.
>
> The Kconfig option still needs to be fixed, otherwise SND_COHERENT_DMA
> isn't selected for my "PPC32 && NOT_COHERENT_CACHE" machine.
>
> config SND_NONCOHERENT_DMA
> def_bool n <-- should be "y"
> depends on (PPC32 && NOT_COHERENT_CACHE)...
Thanks. I changed the patch rather to add a define instead of
Kconfig so that it can detect more easily.
> BTW: Can you put me on CC: please, if you bring up this topic on
> linux-arch or so?
Sure.
Hopefully I can bring up the stuff in this week...
Takashi
^ permalink raw reply
* [PATCH] edac: mpc85xx: fix warning when building without CONFIG_PCI
From: Ira W. Snyder @ 2009-07-08 16:15 UTC (permalink / raw)
To: bluesmoke-devel, Dave Jiang, linuxppc-dev
When building without CONFIG_PCI the edac_pci_idx variable is unused,
causing a build-time warning. Wrap the variable in #ifdef CONFIG_PCI, just
like the rest of the PCI support.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
---
drivers/edac/mpc85xx_edac.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index 3f2ccfc..b4f5c63 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -26,7 +26,9 @@
#include "mpc85xx_edac.h"
static int edac_dev_idx;
+#ifdef CONFIG_PCI
static int edac_pci_idx;
+#endif
static int edac_mc_idx;
static u32 orig_ddr_err_disable;
--
1.5.4.3
^ permalink raw reply related
* [PATCH] edac: mpc85xx: add support for mpc83xx memory controller
From: Ira W. Snyder @ 2009-07-08 16:19 UTC (permalink / raw)
To: bluesmoke-devel, Dave Jiang, linuxppc-dev
Add support for the Freescale MPC83xx memory controller to the existing
driver for the Freescale MPC85xx memory controller. The only difference
between the two processors are in the CS_BNDS register parsing code.
The L2 cache controller does not exist on the MPC83xx, but the OF subsystem
will not use the driver if the device is not present in the OF device tree.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
---
This was tested on an MPC8349EMDS-based board.
I don't really like how the MCE disable works on mpc85xx (clearing the
HID1 register), but this can be revisited when mpc86xx support gets
added. It sucks to have this happen before the probe() routine is called
and we know what kind of hardware we're actually running on.
drivers/edac/Kconfig | 6 +++---
drivers/edac/mpc85xx_edac.c | 38 ++++++++++++++++++++++++++++----------
drivers/edac/mpc85xx_edac.h | 3 +++
3 files changed, 34 insertions(+), 13 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 4339b1a..78303f9 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -176,11 +176,11 @@ config EDAC_I5100
San Clemente MCH.
config EDAC_MPC85XX
- tristate "Freescale MPC85xx"
- depends on EDAC_MM_EDAC && FSL_SOC && MPC85xx
+ tristate "Freescale MPC83xx / MPC85xx"
+ depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx)
help
Support for error detection and correction on the Freescale
- MPC8560, MPC8540, MPC8548
+ MPC8349, MPC8560, MPC8540, MPC8548
config EDAC_MV64X60
tristate "Marvell MV64x60"
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index b4f5c63..3b05130 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -43,7 +43,9 @@ static u32 orig_pci_err_en;
#endif
static u32 orig_l2_err_disable;
+#ifdef CONFIG_MPC85xx
static u32 orig_hid1[2];
+#endif
/************************ MC SYSFS parts ***********************************/
@@ -738,7 +740,8 @@ static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
+static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci,
+ const struct of_device_id *match)
{
struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
struct csrow_info *csrow;
@@ -784,18 +787,26 @@ static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
}
for (index = 0; index < mci->nr_csrows; index++) {
- u32 start;
- u32 end;
+ u32 start, end, extra;
csrow = &mci->csrows[index];
cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
(index * MPC85XX_MC_CS_BNDS_OFS));
- start = (cs_bnds & 0xfff0000) << 4;
- end = ((cs_bnds & 0xfff) << 20);
+
+ if (match->data && match->data == MPC83xx) {
+ start = (cs_bnds & 0x00ff0000) << 8;
+ end = (cs_bnds & 0x000000ff) << 24;
+ extra = 0x00ffffff;
+ } else {
+ start = (cs_bnds & 0x0fff0000) << 4;
+ end = (cs_bnds & 0x00000fff) << 20;
+ extra = 0x000fffff;
+ }
+
if (start)
- start |= 0xfffff;
+ start |= extra;
if (end)
- end |= 0xfffff;
+ end |= extra;
if (start == end)
continue; /* not populated */
@@ -886,7 +897,7 @@ static int __devinit mpc85xx_mc_err_probe(struct of_device *op,
mpc85xx_set_mc_sysfs_attributes(mci);
- mpc85xx_init_csrows(mci);
+ mpc85xx_init_csrows(mci, match);
#ifdef CONFIG_EDAC_DEBUG
edac_mc_register_mcidev_debug((struct attribute **)debug_attr);
@@ -986,6 +997,7 @@ static struct of_device_id mpc85xx_mc_err_of_match[] = {
{ .compatible = "fsl,mpc8560-memory-controller", },
{ .compatible = "fsl,mpc8568-memory-controller", },
{ .compatible = "fsl,mpc8572-memory-controller", },
+ { .compatible = "fsl,mpc8349-memory-controller", .data = MPC83xx, },
{},
};
@@ -1001,13 +1013,13 @@ static struct of_platform_driver mpc85xx_mc_err_driver = {
},
};
-
+#ifdef CONFIG_MPC85xx
static void __init mpc85xx_mc_clear_rfxe(void *data)
{
orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
}
-
+#endif
static int __init mpc85xx_mc_init(void)
{
@@ -1040,26 +1052,32 @@ static int __init mpc85xx_mc_init(void)
printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
#endif
+#ifdef CONFIG_MPC85xx
/*
* need to clear HID1[RFXE] to disable machine check int
* so we can catch it
*/
if (edac_op_state == EDAC_OPSTATE_INT)
on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
+#endif
return 0;
}
module_init(mpc85xx_mc_init);
+#ifdef CONFIG_MPC85xx
static void __exit mpc85xx_mc_restore_hid1(void *data)
{
mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
}
+#endif
static void __exit mpc85xx_mc_exit(void)
{
+#ifdef CONFIG_MPC85xx
on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
+#endif
#ifdef CONFIG_PCI
of_unregister_platform_driver(&mpc85xx_pci_err_driver);
#endif
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h
index 52432ee..fb166d0 100644
--- a/drivers/edac/mpc85xx_edac.h
+++ b/drivers/edac/mpc85xx_edac.h
@@ -139,6 +139,9 @@
#define MPC85XX_PCI_GAS_TIMR 0x0020
#define MPC85XX_PCI_PCIX_TIMR 0x0024
+/* Device types */
+#define MPC83xx ((void *)1)
+
struct mpc85xx_mc_pdata {
char *name;
int edac_idx;
--
1.5.4.3
^ permalink raw reply related
* Re: [PATCH] edac: mpc85xx: fix warning when building without CONFIG_PCI
From: Dave Jiang @ 2009-07-08 16:20 UTC (permalink / raw)
To: Ira W. Snyder; +Cc: linuxppc-dev, bluesmoke-devel
In-Reply-To: <20090708161543.GB14979@ovro.caltech.edu>
Acked-by: Dave Jiang <djiang@mvista.com>
On 07/08/2009 09:15 AM, Ira W. Snyder wrote:
> When building without CONFIG_PCI the edac_pci_idx variable is unused,
> causing a build-time warning. Wrap the variable in #ifdef CONFIG_PCI, just
> like the rest of the PCI support.
>
> Signed-off-by: Ira W. Snyder<iws@ovro.caltech.edu>
> ---
> drivers/edac/mpc85xx_edac.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
> index 3f2ccfc..b4f5c63 100644
> --- a/drivers/edac/mpc85xx_edac.c
> +++ b/drivers/edac/mpc85xx_edac.c
> @@ -26,7 +26,9 @@
> #include "mpc85xx_edac.h"
>
> static int edac_dev_idx;
> +#ifdef CONFIG_PCI
> static int edac_pci_idx;
> +#endif
> static int edac_mc_idx;
>
> static u32 orig_ddr_err_disable;
^ permalink raw reply
* Re: [PATCH] edac: mpc85xx: add support for mpc83xx memory controller
From: Kumar Gala @ 2009-07-08 18:09 UTC (permalink / raw)
To: Ira W. Snyder; +Cc: linuxppc-dev, bluesmoke-devel, Dave Jiang
In-Reply-To: <20090708161954.GC14979@ovro.caltech.edu>
On Jul 8, 2009, at 11:19 AM, Ira W. Snyder wrote:
> Add support for the Freescale MPC83xx memory controller to the
> existing
> driver for the Freescale MPC85xx memory controller. The only
> difference
> between the two processors are in the CS_BNDS register parsing code.
>
> The L2 cache controller does not exist on the MPC83xx, but the OF
> subsystem
> will not use the driver if the device is not present in the OF
> device tree.
>
> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
> ---
>
> This was tested on an MPC8349EMDS-based board.
>
> I don't really like how the MCE disable works on mpc85xx (clearing the
> HID1 register), but this can be revisited when mpc86xx support gets
> added. It sucks to have this happen before the probe() routine is
> called
> and we know what kind of hardware we're actually running on.
>
> drivers/edac/Kconfig | 6 +++---
> drivers/edac/mpc85xx_edac.c | 38 +++++++++++++++++++++++++++
> +----------
> drivers/edac/mpc85xx_edac.h | 3 +++
> 3 files changed, 34 insertions(+), 13 deletions(-)
[snip]
> /************************ MC SYSFS parts
> ***********************************/
>
> @@ -738,7 +740,8 @@ static irqreturn_t mpc85xx_mc_isr(int irq, void
> *dev_id)
> return IRQ_HANDLED;
> }
>
> -static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
> +static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci,
> + const struct of_device_id *match)
> {
> struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
> struct csrow_info *csrow;
> @@ -784,18 +787,26 @@ static void __devinit
> mpc85xx_init_csrows(struct mem_ctl_info *mci)
> }
>
> for (index = 0; index < mci->nr_csrows; index++) {
> - u32 start;
> - u32 end;
> + u32 start, end, extra;
>
> csrow = &mci->csrows[index];
> cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
> (index * MPC85XX_MC_CS_BNDS_OFS));
> - start = (cs_bnds & 0xfff0000) << 4;
> - end = ((cs_bnds & 0xfff) << 20);
> +
> + if (match->data && match->data == MPC83xx) {
> + start = (cs_bnds & 0x00ff0000) << 8;
> + end = (cs_bnds & 0x000000ff) << 24;
> + extra = 0x00ffffff;
> + } else {
> + start = (cs_bnds & 0x0fff0000) << 4;
> + end = (cs_bnds & 0x00000fff) << 20;
> + extra = 0x000fffff;
> + }
I don't understand this at all.. The only difference between 83xx &
85xx is that we should have an extra 4-bits for 36-bit physical
addresses.
We should be able to write this code in such a way that it works for
both 83xx & 85xx.
start = (cs_bnds & 0xffff0000) >> 16;
end = (cs_bnds & 0xffff);
if (start == end)
continue;
start <<= (20 - PAGE_SHIFT);
end <<= (20 - PAGE_SHIFT);
end |= (1 << (20 - PAGE_SHIFT)) - 1;
- k
^ permalink raw reply
* switching from initrd to initramfs
From: Mikhail Zaturenskiy @ 2009-07-08 19:25 UTC (permalink / raw)
To: linuxppc-dev
Hello, I have a working system with an initrd ramdisk and I'm having
some trouble switching it over to initramfs.
This is for an EP88xc Embedded Planet board, now running U-Boot and
using kernel 2.6.29. I prepare my initrd using:
genext2fs -U -d rootfs -D rootfs_devices.tab -b 9700 -i 380 initrd.img
gzip -v9 initrd.img
mkimage -T ramdisk -C gzip -n 'Test Ramdisk Image' -d initrd.img.gz uInitrd
(instructions are from
http://www.denx.de/wiki/view/DULG/RootFileSystemDesignAndBuilding )
...which seems to work ok and results in the following:
************************************************************************************
U-Boot 2009.03-svn8609 (Jun 30 2009 - 11:32:48)
CPU: MPC885ZPnn at 100 MHz [40.0...133.0 MHz]
8 kB I-Cache 8 kB D-Cache FEC present
Board: EP88xC 1.1 CPLD revision 2
DRAM: 64 MB
FLASH: 32 MB
In: serial
Out: serial
Err: serial
Net: FEC ETHERNET, FEC2 ETHERNET
Hit any key to stop autoboot: 0
=>
=>
=> setenv bootargs console=ttyCPM0,9600n8 root=/dev/ram rw init=/sbin/init
=> tftp 400000 ep88x_uimage_29
Using FEC ETHERNET device
TFTP from server 10.0.54.129; our IP address is 10.0.54.150
Filename 'ep88x_uimage_29'.
Load address: 0x400000
Loading: #################################################################
##########
done
Bytes transferred = 1089141 (109e75 hex)
=> tftp 750000 ep88x_ramdisk_generated2
Using FEC ETHERNET device
TFTP from server 10.0.54.129; our IP address is 10.0.54.150
Filename 'ep88x_ramdisk_generated2'.
Load address: 0x750000
Loading: #################################################################
###############################################################
done
Bytes transferred = 1869959 (1c8887 hex)
=> tftp 1000000 ep88x_dtb
Using FEC ETHERNET device
TFTP from server 10.0.54.129; our IP address is 10.0.54.150
Filename 'ep88x_dtb'.
Load address: 0x1000000
Loading: #
done
Bytes transferred = 7643 (1ddb hex)
=> bootm 400000 750000 1000000
## Booting kernel from Legacy Image at 00400000 ...
Image Name: Linux-2.6.29.6-dirty
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1089077 Bytes = 1 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 00750000 ...
Image Name: Test Ramdisk Image
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 1869895 Bytes = 1.8 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at 01000000
Booting using the fdt blob at 0x1000000
Uncompressing Kernel Image ... OK
Loading Ramdisk to 03da5000, end 03f6d847 ... OK
Loading Device Tree to 007fb000, end 007ffdda ... OK
Using Embedded Planet EP88xC machine description
Linux version 2.6.29.6-dirty (devone@localhost.localdomain) (gcc version 4.2.2)
#1 Mon Jul 6 12:53:12 CDT 2009
Found initrd at 0xc3da5000:0xc3f6d847
Zone PFN ranges:
DMA 0x00000000 -> 0x00004000
Normal 0x00004000 -> 0x00004000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
0: 0x00000000 -> 0x00004000
MMU: Allocated 72 bytes of context maps for 16 contexts
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256
Kernel command line: console=ttyCPM0,9600n8 root=/dev/ram rw init=/sbin/init
PID hash table entries: 256 (order: 8, 1024 bytes)
Decrementer Frequency = 0x5f5e10
clocksource: timebase mult[28000000] shift[22] registered
console [ttyCPM0] enabled
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 60644k/65536k available (2124k kernel code, 4824k reserved, 88k data, 10
6k bss, 124k init)
SLUB: Genslabs=11, HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Calibrating delay loop... 12.41 BogoMIPS (lpj=62080)
Mount-cache hash table entries: 512
net_namespace: 296 bytes
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
NET: Registered protocol family 1
checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
Freeing initrd memory: 1826k freed
msgmni has been set to 122
io scheduler noop registered
io scheduler deadline registered (default)
Generic RTC Driver v1.07
f0000a80.serial: ttyCPM0 at MMIO 0xc500ea80 (irq = 19) is a CPM UART
f0000a20.serial: ttyCPM1 at MMIO 0xc5016a20 (irq = 29) is a CPM UART
brd: module loaded
loop: module loaded
eth0 (): not using net_device_ops yet
eth0: fs_enet: 00:00:00:00:00:00
eth1 (): not using net_device_ops yet
eth1: fs_enet: 00:00:00:00:00:00
FEC MII Bus: probed
fe000000.flash: Found 2 x16 devices at 0x0 in 32-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
fe000000.flash: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
TCP cubic registered
NET: Registered protocol family 17
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RAMDISK: Compressed image found at block 0
VFS: Mounted root (ext2 filesystem) on device 1:0.
Freeing unused kernel memory: 124k init
init started: BusyBox v1.7.1 (2008-04-02 09:14:47 MEST)
starting pid 208, tty '': '/etc/rc.sh'
starting pid 213, tty '': '/bin/application'
starting pid 214, tty '': '/bin/sh'
### Application running ...
~ #
*****************************************************************************
Then I tried to make an initramfs from the same root tree using:
find | cpio -ovc | gzip -v9 > ../initramfs.cpio.gz
mkimage -T ramdisk -C gzip -n 'Test Ramdisk Image' -d
../initramfs.cpio.gz ../uCpio
But the result seems to have an issue with init:
****************************************************************************
U-Boot 2009.03-svn8609 (Jun 30 2009 - 11:32:48)
CPU: MPC885ZPnn at 100 MHz [40.0...133.0 MHz]
8 kB I-Cache 8 kB D-Cache FEC present
Board: EP88xC 1.1 CPLD revision 2
DRAM: 64 MB
FLASH: 32 MB
In: serial
Out: serial
Err: serial
Net: FEC ETHERNET, FEC2 ETHERNET
Hit any key to stop autoboot: 0
=>
=>
=> setenv bootargs console=ttyCPM0,9600n8 root=/dev/ram rw init=/sbin/init
=> tftp 400000 ep88x_uimage_29
Using FEC ETHERNET device
TFTP from server 10.0.54.129; our IP address is 10.0.54.150
Filename 'ep88x_uimage_29'.
Load address: 0x400000
Loading: #################################################################
##########
done
Bytes transferred = 1089141 (109e75 hex)
=> tftp 750000 ep88x_ramfs
Using FEC ETHERNET device
TFTP from server 10.0.54.129; our IP address is 10.0.54.150
Filename 'ep88x_ramfs'.
Load address: 0x750000
Loading: #################################################################
############################################################
done
Bytes transferred = 1832735 (1bf71f hex)
=> tftp 1000000 ep88x_dtb
Using FEC ETHERNET device
TFTP from server 10.0.54.129; our IP address is 10.0.54.150
Filename 'ep88x_dtb'.
Load address: 0x1000000
Loading: #
done
Bytes transferred = 7643 (1ddb hex)
=> bootm 400000 750000 1000000
## Booting kernel from Legacy Image at 00400000 ...
Image Name: Linux-2.6.29.6-dirty
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1089077 Bytes = 1 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 00750000 ...
Image Name: Test Ramdisk Image
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 1832671 Bytes = 1.7 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at 01000000
Booting using the fdt blob at 0x1000000
Uncompressing Kernel Image ... OK
Loading Ramdisk to 03dae000, end 03f6d6df ... OK
Loading Device Tree to 007fb000, end 007ffdda ... OK
Using Embedded Planet EP88xC machine description
Linux version 2.6.29.6-dirty (devone@localhost.localdomain) (gcc version 4.2.2)
#1 Mon Jul 6 12:53:12 CDT 2009
Found initrd at 0xc3dae000:0xc3f6d6df
Zone PFN ranges:
DMA 0x00000000 -> 0x00004000
Normal 0x00004000 -> 0x00004000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
0: 0x00000000 -> 0x00004000
MMU: Allocated 72 bytes of context maps for 16 contexts
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256
Kernel command line: console=ttyCPM0,9600n8 root=/dev/ram rw init=/sbin/init
PID hash table entries: 256 (order: 8, 1024 bytes)
Decrementer Frequency = 0x5f5e10
clocksource: timebase mult[28000000] shift[22] registered
console [ttyCPM0] enabled
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 60680k/65536k available (2124k kernel code, 4788k reserved, 88k data, 10
6k bss, 124k init)
SLUB: Genslabs=11, HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Calibrating delay loop... 12.41 BogoMIPS (lpj=62080)
Mount-cache hash table entries: 512
net_namespace: 296 bytes
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
NET: Registered protocol family 1
checking if image is initramfs... it is
Freeing initrd memory: 1789k freed
msgmni has been set to 122
io scheduler noop registered
io scheduler deadline registered (default)
Generic RTC Driver v1.07
f0000a80.serial: ttyCPM0 at MMIO 0xc500ea80 (irq = 19) is a CPM UART
f0000a20.serial: ttyCPM1 at MMIO 0xc5016a20 (irq = 29) is a CPM UART
brd: module loaded
loop: module loaded
eth0 (): not using net_device_ops yet
eth0: fs_enet: 00:00:00:00:00:00
eth1 (): not using net_device_ops yet
eth1: fs_enet: 00:00:00:00:00:00
FEC MII Bus: probed
fe000000.flash: Found 2 x16 devices at 0x0 in 32-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
fe000000.flash: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
TCP cubic registered
NET: Registered protocol family 17
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
List of all partitions:
1f00 32768 mtdblock0 (driver?)
No filesystem could mount root, tried: ext2 cramfs
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(1,0)
Rebooting in 180 seconds..
**********************************************************************
I was hoping to convert this working initrd to initramfs before I try
and create my own initrd, I'm still learning about this process. I got
this to work yesterday morning, but I'm not sure what changed or what
I'm doing differently...
Can somebody help me figure out what's missing?
Thanks,
Mikhail Zaturenskiy
^ permalink raw reply
* Re: [PATCH] edac: mpc85xx: add support for mpc83xx memory controller
From: Ira W. Snyder @ 2009-07-08 19:33 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, bluesmoke-devel, Dave Jiang
In-Reply-To: <3887C2A7-3566-43A9-A863-4670B039E5DA@kernel.crashing.org>
On Wed, Jul 08, 2009 at 01:09:39PM -0500, Kumar Gala wrote:
>
> On Jul 8, 2009, at 11:19 AM, Ira W. Snyder wrote:
>
>> Add support for the Freescale MPC83xx memory controller to the
>> existing
>> driver for the Freescale MPC85xx memory controller. The only
>> difference
>> between the two processors are in the CS_BNDS register parsing code.
>>
>> The L2 cache controller does not exist on the MPC83xx, but the OF
>> subsystem
>> will not use the driver if the device is not present in the OF device
>> tree.
>>
>> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
>> ---
>>
>> This was tested on an MPC8349EMDS-based board.
>>
>> I don't really like how the MCE disable works on mpc85xx (clearing the
>> HID1 register), but this can be revisited when mpc86xx support gets
>> added. It sucks to have this happen before the probe() routine is
>> called
>> and we know what kind of hardware we're actually running on.
>>
>> drivers/edac/Kconfig | 6 +++---
>> drivers/edac/mpc85xx_edac.c | 38 +++++++++++++++++++++++++++
>> +----------
>> drivers/edac/mpc85xx_edac.h | 3 +++
>> 3 files changed, 34 insertions(+), 13 deletions(-)
>
> [snip]
>
>> /************************ MC SYSFS parts
>> ***********************************/
>>
>> @@ -738,7 +740,8 @@ static irqreturn_t mpc85xx_mc_isr(int irq, void
>> *dev_id)
>> return IRQ_HANDLED;
>> }
>>
>> -static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
>> +static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci,
>> + const struct of_device_id *match)
>> {
>> struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
>> struct csrow_info *csrow;
>> @@ -784,18 +787,26 @@ static void __devinit mpc85xx_init_csrows(struct
>> mem_ctl_info *mci)
>> }
>>
>> for (index = 0; index < mci->nr_csrows; index++) {
>> - u32 start;
>> - u32 end;
>> + u32 start, end, extra;
>>
>> csrow = &mci->csrows[index];
>> cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
>> (index * MPC85XX_MC_CS_BNDS_OFS));
>> - start = (cs_bnds & 0xfff0000) << 4;
>> - end = ((cs_bnds & 0xfff) << 20);
>> +
>> + if (match->data && match->data == MPC83xx) {
>> + start = (cs_bnds & 0x00ff0000) << 8;
>> + end = (cs_bnds & 0x000000ff) << 24;
>> + extra = 0x00ffffff;
>> + } else {
>> + start = (cs_bnds & 0x0fff0000) << 4;
>> + end = (cs_bnds & 0x00000fff) << 20;
>> + extra = 0x000fffff;
>> + }
>
> I don't understand this at all.. The only difference between 83xx & 85xx
> is that we should have an extra 4-bits for 36-bit physical addresses.
>
> We should be able to write this code in such a way that it works for
> both 83xx & 85xx.
>
> start = (cs_bnds & 0xffff0000) >> 16;
> end = (cs_bnds & 0xffff);
>
> if (start == end)
> continue;
> start <<= (20 - PAGE_SHIFT);
> end <<= (20 - PAGE_SHIFT);
> end |= (1 << (20 - PAGE_SHIFT)) - 1;
>
Sorry, I don't know a thing about PAGE_SHIFT. Looking in
arch/powerpc/platforms/Kconfig.cputype, PPC_85xx doesn't seem to imply a
change in PAGE_SIZE, which changes the PAGE_SHIFT in
arch/powerpc/include/asm/page.h.
Also, are you sure you cannot use 4K pages on an 85xx? If you can use 4K
pages on 85xx, then PAGE_SHIFT == 12, and your solution breaks.
I admit I don't know much about all of the different powerpc platforms.
Ira
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