* [PATCH] powermac: thermal control turns system off in normal temperature conditions
From: Bartlomiej Zolnierkiewicz @ 2009-08-30 18:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, linux-kernel, Lyonel Vincent
=46rom: Lyonel Vincent <lyonel@ezix.org>
Subject: [PATCH] powermac: thermal control turns system off in normal tempe=
rature conditions
On certain PowerMacs, a module (therm_windtunnel) controls various
thermal settings (it can report CPU/case temperature, change speed
of internal fans, etc.)
By default, the hardware thermal control has a temperature limit to
protect the computer from damages (the default limit seems to be 80=B0C)
but therm_windtunnel.c reduces it to an anormaly low value (65=B0C),
which means that he computer will shut down randomly when hit by direct
sun light or during summer (summer in France can be quite hot), actually
possibly losing data instead of protecting it.
The overheat limit in therm_windtunnel.c:253-254 should be set to 75=B0C
and 70=B0C instead of 65=B0C and 60=B0C respectively.
=46rom: Lyonel Vincent <lyonel@ezix.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
=2D--
Resurrected from Fedora's bugzilla (aka The Big Black Hole):
https://bugzilla.redhat.com/show_bug.cgi?id=3D171937
The patch itself seems perfectly valid to me
(especially given comments in therm_windtunnel.c).
drivers/macintosh/therm_windtunnel.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: b/drivers/macintosh/therm_windtunnel.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
=2D-- a/drivers/macintosh/therm_windtunnel.c
+++ b/drivers/macintosh/therm_windtunnel.c
@@ -239,8 +239,8 @@ setup_hardware( void )
* to be on the safe side (OSX doesn't)...
*/
if( x.overheat_temp =3D=3D (80 << 8) ) {
=2D x.overheat_temp =3D 65 << 8;
=2D x.overheat_hyst =3D 60 << 8;
+ x.overheat_temp =3D 75 << 8;
+ x.overheat_hyst =3D 70 << 8;
write_reg( x.thermostat, 2, x.overheat_hyst, 2 );
write_reg( x.thermostat, 3, x.overheat_temp, 2 );
=20
^ permalink raw reply
* [PATCH v2 0/5] Suspend/resume support for some 83xx/85xx/86xx boards
From: Anton Vorontsov @ 2009-08-30 19:36 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev, Timur Tabi
On Fri, Aug 28, 2009 at 12:38:51AM -0500, Kumar Gala wrote:
> >This patch adds suspend/resume support for MPC8540-compatible and
> >MPC8569 CPUs.
[...]
> I'd also like to get Scott's Ack on this and the device tree patches
> before accepting them.
Heh, I didn't notice that the PMC bindings for 85xx describe devdisr
registers (and thus sleep = <> properties).
So here are updated patches that should comply with the bindings.
Plus,
- It appears that 86xx PMCs registers-compatible with 85xx, so we
can support both. Thus move 85xx/suspend.c to sysdev/fsl_pmc.c;
- New patch that adds suspend/resume for MPC8610HPCD;
- New patch that adds suspend/resume for 83xx QE boards;
- Some fixes in "Make qe_reset() code path safe for repeated
invocation" patch.
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* [PATCH 1/5] powerpc/qe: Make qe_reset() code path safe for repeated invocation
From: Anton Vorontsov @ 2009-08-30 19:37 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev, Timur Tabi
In-Reply-To: <20090830193625.GA14693@oksana.dev.rtsoft.ru>
For MPC8569 CPUs we'll need to reset QE after each suspend, so make
qe_reset() code path suitable for repeated invocation, that is:
- Don't initialize rheap structures if already initialized;
- Don't allocate muram for SDMA if already allocated, just reinitialize
registers with previously allocated muram offset;
- Remove __init attributes from qe_reset() and cpm_muram_init();
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/include/asm/qe.h | 2 +-
arch/powerpc/sysdev/cpm_common.c | 5 ++++-
arch/powerpc/sysdev/qe_lib/qe.c | 12 +++++++-----
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index e8232bb..2f44754 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -87,7 +87,7 @@ extern spinlock_t cmxgcr_lock;
/* Export QE common operations */
#ifdef CONFIG_QUICC_ENGINE
-extern void __init qe_reset(void);
+extern void qe_reset(void);
#else
static inline void qe_reset(void) {}
#endif
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index e4b6d66..9de72c9 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -72,7 +72,7 @@ static phys_addr_t muram_pbase;
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
-int __init cpm_muram_init(void)
+int cpm_muram_init(void)
{
struct device_node *np;
struct resource r;
@@ -81,6 +81,9 @@ int __init cpm_muram_init(void)
int i = 0;
int ret = 0;
+ if (muram_pbase)
+ return 0;
+
spin_lock_init(&cpm_muram_lock);
/* initialize the info header */
rh_init(&cpm_muram_info, 1,
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index b06564f..4eaf2a9 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -91,7 +91,7 @@ phys_addr_t get_qe_base(void)
EXPORT_SYMBOL(get_qe_base);
-void __init qe_reset(void)
+void qe_reset(void)
{
if (qe_immr == NULL)
qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
@@ -317,16 +317,18 @@ EXPORT_SYMBOL(qe_put_snum);
static int qe_sdma_init(void)
{
struct sdma __iomem *sdma = &qe_immr->sdma;
- unsigned long sdma_buf_offset;
+ static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
if (!sdma)
return -ENODEV;
/* allocate 2 internal temporary buffers (512 bytes size each) for
* the SDMA */
- sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
- if (IS_ERR_VALUE(sdma_buf_offset))
- return -ENOMEM;
+ if (IS_ERR_VALUE(sdma_buf_offset)) {
+ sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
+ if (IS_ERR_VALUE(sdma_buf_offset))
+ return -ENOMEM;
+ }
out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
--
1.6.3.3
^ permalink raw reply related
* [PATCH 2/5] powerpc/85xx/86xx: Add suspend/resume support
From: Anton Vorontsov @ 2009-08-30 19:37 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev, Timur Tabi
In-Reply-To: <20090830193625.GA14693@oksana.dev.rtsoft.ru>
This patch adds suspend/resume support for MPC8540, MPC8569 and
MPC8641D-compatible CPUs.
MPC8540 and MPC8641D-compatible PMCs are trivial: we just write
the SLP bit into the PM control and status register.
MPC8569 is a bit trickier, QE turns off during suspend, thus on
resume we must reload QE microcode and reset QE.
So far we don't support Deep Sleep mode as found in newer MPC85xx
CPUs (i.e. MPC8536). It can be relatively easy implemented though,
and for it we reserve 'mem' suspend type.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/Kconfig | 11 +++-
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_pmc.c | 124 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 135 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_pmc.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index d00131c..a0743a7 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -212,7 +212,8 @@ config ARCH_HIBERNATION_POSSIBLE
config ARCH_SUSPEND_POSSIBLE
def_bool y
- depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx
+ depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
+ PPC_85xx || PPC_86xx
config PPC_DCR_NATIVE
bool
@@ -642,6 +643,14 @@ config FSL_PCI
select PPC_INDIRECT_PCI
select PCI_QUIRKS
+config FSL_PMC
+ bool
+ default y
+ depends on SUSPEND && (PPC_85xx || PPC_86xx)
+ help
+ Freescale MPC85xx/MPC86xx power management controller support
+ (suspend/resume). For MPC83xx see platforms/83xx/suspend.c
+
config 4xx_SOC
bool
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 9d4b174..5642924 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
+obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
new file mode 100644
index 0000000..843c284
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -0,0 +1,124 @@
+/*
+ * Suspend/resume support
+ *
+ * Copyright © 2009 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/suspend.h>
+#include <linux/device.h>
+#include <linux/of_platform.h>
+#include <linux/firmware.h>
+#include <asm/qe.h>
+
+struct pmc_regs {
+ __be32 devdisr;
+ __be32 devdisr2;
+ __be32 :32;
+ __be32 :32;
+ __be32 pmcsr;
+#define PMCSR_SLP (1 << 17)
+};
+
+struct pmc_data {
+ unsigned int flags;
+#define PMC_NEED_QE_RELOAD (1 << 0)
+
+ const char *fw_name;
+};
+
+static struct device *pmc_dev;
+static struct pmc_regs __iomem *pmc_regs;
+static const struct pmc_data *pmc_data;
+static struct qe_firmware *pmc_qefw;
+
+static int pmc_suspend_enter(suspend_state_t state)
+{
+ setbits32(&pmc_regs->pmcsr, PMCSR_SLP);
+ /* At this point, the CPU is asleep. */
+
+ /* For 86xx we need to clear the bit on resume, 85xx don't care. */
+ clrbits32(&pmc_regs->pmcsr, PMCSR_SLP);
+
+ if (pmc_qefw) {
+ int ret;
+
+ ret = qe_upload_firmware(pmc_qefw);
+ if (ret)
+ dev_err(pmc_dev, "could not upload firmware\n");
+
+ qe_reset();
+ }
+ return 0;
+}
+
+static int pmc_suspend_valid(suspend_state_t state)
+{
+ if (state != PM_SUSPEND_STANDBY)
+ return 0;
+
+ if (pmc_data && pmc_data->flags & PMC_NEED_QE_RELOAD && !pmc_qefw) {
+ const struct firmware *fw;
+ int ret;
+
+ ret = request_firmware(&fw, pmc_data->fw_name, pmc_dev);
+ if (ret) {
+ dev_err(pmc_dev, "could not request firmware %s\n",
+ pmc_data->fw_name);
+ return 0;
+ }
+
+ pmc_qefw = (struct qe_firmware *)fw->data;
+ }
+
+ return 1;
+}
+
+static struct platform_suspend_ops pmc_suspend_ops = {
+ .valid = pmc_suspend_valid,
+ .enter = pmc_suspend_enter,
+};
+
+static int pmc_probe(struct of_device *ofdev, const struct of_device_id *id)
+{
+ pmc_regs = of_iomap(ofdev->node, 0);
+ if (!pmc_regs)
+ return -ENOMEM;
+
+ pmc_dev = &ofdev->dev;
+ pmc_data = id->data;
+ suspend_set_ops(&pmc_suspend_ops);
+ return 0;
+}
+
+static struct pmc_data mpc8569_pmc_data = {
+ .flags = PMC_NEED_QE_RELOAD,
+ .fw_name = "fsl_qe_ucode_8569.bin",
+};
+
+static const struct of_device_id pmc_ids[] = {
+ { .compatible = "fsl,mpc8569-pmc", .data = &mpc8569_pmc_data, },
+ { .compatible = "fsl,mpc8548-pmc", },
+ { .compatible = "fsl,mpc8641d-pmc", },
+ { },
+};
+
+static struct of_platform_driver pmc_driver = {
+ .driver.name = "fsl-pmc",
+ .match_table = pmc_ids,
+ .probe = pmc_probe,
+};
+
+static int __init pmc_init(void)
+{
+ return of_register_platform_driver(&pmc_driver);
+}
+device_initcall(pmc_init);
--
1.6.3.3
^ permalink raw reply related
* [PATCH 3/5] powerpc/85xx: Add power management support for MPC85xxMDS boards
From: Anton Vorontsov @ 2009-08-30 19:37 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev, Timur Tabi
In-Reply-To: <20090830193625.GA14693@oksana.dev.rtsoft.ru>
- Add power management controller nodes;
- Add interrupts for RTC nodes, the RTC interrupt may be used as a
wakeup source;
- Add sleep properties and sleep-nexus nodes.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/boot/dts/mpc8568mds.dts | 119 +++++++++++++++++++----------
arch/powerpc/boot/dts/mpc8569mds.dts | 111 ++++++++++++++++++---------
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 +
3 files changed, 153 insertions(+), 78 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 00c2bbd..6d892ba 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -40,6 +40,8 @@
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
+ sleep = <&pmc 0x00008000 // core
+ &pmc 0x00004000>; // timebase
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
@@ -94,31 +96,41 @@
interrupts = <16 2>;
};
- i2c@3000 {
+ i2c-sleep-nexus {
#address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ sleep = <&pmc 0x00000004>;
+ ranges;
- rtc@68 {
- compatible = "dallas,ds1374";
- reg = <0x68>;
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ rtc@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ interrupts = <3 1>;
+ interrupt-parent = <&mpic>;
+ };
};
- };
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
};
dma@21300 {
@@ -128,6 +140,8 @@
reg = <0x21300 0x4>;
ranges = <0x0 0x21100 0x200>;
cell-index = <0>;
+ sleep = <&pmc 0x00000400>;
+
dma-channel@0 {
compatible = "fsl,mpc8568-dma-channel",
"fsl,eloplus-dma-channel";
@@ -176,6 +190,7 @@
interrupt-parent = <&mpic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy2>;
+ sleep = <&pmc 0x00000080>;
mdio@520 {
#address-cells = <1>;
@@ -228,6 +243,7 @@
interrupt-parent = <&mpic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy3>;
+ sleep = <&pmc 0x00000040>;
mdio@520 {
#address-cells = <1>;
@@ -242,30 +258,47 @@
};
};
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
+ duart-sleep-nexus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ sleep = <&pmc 0x00000002>;
+ ranges;
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
};
- global-utilities@e0000 { //global utilities block
- compatible = "fsl,mpc8548-guts";
+ global-utilities@e0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
reg = <0xe0000 0x1000>;
+ ranges = <0 0xe0000 0x1000>;
fsl,has-rstcr;
- };
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
+ pmc: power@70 {
+ compatible = "fsl,mpc8568-pmc",
+ "fsl,mpc8548-pmc";
+ reg = <0x70 0x20>;
+ };
};
crypto@30000 {
@@ -277,6 +310,7 @@
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xfe>;
fsl,descriptor-types-mask = <0x12b0ebf>;
+ sleep = <&pmc 0x01000000>;
};
mpic: pic@40000 {
@@ -376,6 +410,7 @@
compatible = "fsl,qe";
ranges = <0x0 0xe0080000 0x40000>;
reg = <0xe0080000 0x480>;
+ sleep = <&pmc 0x00000800>;
brg-frequency = <0>;
bus-frequency = <396000000>;
fsl,qe-num-riscs = <2>;
@@ -509,6 +544,7 @@
bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
+ sleep = <&pmc 0x80000000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
@@ -534,6 +570,7 @@
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
+ sleep = <&pmc 0x20000000>;
clock-frequency = <33333333>;
#interrupt-cells = <1>;
#size-cells = <2>;
@@ -570,5 +607,7 @@
55 2 /* msg2_tx */
56 2 /* msg2_rx */>;
interrupt-parent = <&mpic>;
+ sleep = <&pmc 0x00080000 /* controller */
+ &pmc 0x00040000>; /* message unit */
};
};
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 880f896..b35e62c 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -41,6 +41,8 @@
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K
i-cache-size = <0x8000>; // L1, 32K
+ sleep = <&pmc 0x00008000 // core
+ &pmc 0x00004000>; // timebase
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
@@ -59,6 +61,7 @@
reg = <0xe0005000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
+ sleep = <&pmc 0x08000000>;
ranges = <0x0 0x0 0xfe000000 0x02000000
0x1 0x0 0xf8000000 0x00008000
@@ -158,51 +161,69 @@
interrupts = <18 2>;
};
- i2c@3000 {
+ i2c-sleep-nexus {
#address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ sleep = <&pmc 0x00000004>;
+ ranges;
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+
+ rtc@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ interrupts = <3 1>;
+ interrupt-parent = <&mpic>;
+ };
+ };
- rtc@68 {
- compatible = "dallas,ds1374";
- reg = <0x68>;
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
};
};
- i2c@3100 {
+ duart-sleep-nexus {
#address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
- };
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ sleep = <&pmc 0x00000002>;
+ ranges;
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
};
L2: l2-cache-controller@20000 {
@@ -260,6 +281,7 @@
reg = <0x2e000 0x1000>;
interrupts = <72 0x8>;
interrupt-parent = <&mpic>;
+ sleep = <&pmc 0x00200000>;
/* Filled in by U-Boot */
clock-frequency = <0>;
status = "disabled";
@@ -276,6 +298,7 @@
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0xbfe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
+ sleep = <&pmc 0x01000000>;
};
mpic: pic@40000 {
@@ -304,9 +327,18 @@
};
global-utilities@e0000 {
- compatible = "fsl,mpc8569-guts";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
reg = <0xe0000 0x1000>;
+ ranges = <0 0xe0000 0x1000>;
fsl,has-rstcr;
+
+ pmc: power@70 {
+ compatible = "fsl,mpc8569-pmc",
+ "fsl,mpc8548-pmc";
+ reg = <0x70 0x20>;
+ };
};
par_io@e0100 {
@@ -422,6 +454,7 @@
compatible = "fsl,qe";
ranges = <0x0 0xe0080000 0x40000>;
reg = <0xe0080000 0x480>;
+ sleep = <&pmc 0x00000800>;
brg-frequency = <0>;
bus-frequency = <0>;
fsl,qe-num-riscs = <4>;
@@ -680,6 +713,7 @@
bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
+ sleep = <&pmc 0x20000000>;
clock-frequency = <33333333>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -710,5 +744,6 @@
55 2 /* msg2_tx */
56 2 /* msg2_rx */>;
interrupt-parent = <&mpic>;
+ sleep = <&pmc 0x00080000>;
};
};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 20a61d0..995ddad 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -300,6 +300,7 @@ static struct of_device_id mpc85xx_ids[] = {
{ .compatible = "fsl,qe", },
{ .compatible = "gianfar", },
{ .compatible = "fsl,rapidio-delta", },
+ { .compatible = "fsl,mpc8548-guts", },
{},
};
--
1.6.3.3
^ permalink raw reply related
* [PATCH 4/5] powerpc/86xx: Add power management support for MPC8610HPCD boards
From: Anton Vorontsov @ 2009-08-30 19:37 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev, Timur Tabi
In-Reply-To: <20090830193625.GA14693@oksana.dev.rtsoft.ru>
This patch adds needed nodes and properties to support suspend/resume
on the MPC8610HPCD boards.
There is a dedicated switch (SW9) that is used to wake up the boards.
By default the SW9 button is routed to IRQ8, but could be re-routed
(via PIXIS) to sreset.
With 'no_console_suspend' kernel command line argument specified, the
board is also able to wakeup upon serial port input.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
Documentation/powerpc/dts-bindings/fsl/board.txt | 4 ++
arch/powerpc/boot/dts/mpc8610_hpcd.dts | 26 ++++++++++++
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 48 ++++++++++++++++++++--
3 files changed, 74 insertions(+), 4 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
index e8b5bc2..39e9415 100644
--- a/Documentation/powerpc/dts-bindings/fsl/board.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -20,12 +20,16 @@ Required properities:
- compatible : should be "fsl,fpga-pixis".
- reg : should contain the address and the length of the FPPGA register
set.
+- interrupt-parent: should specify phandle for the interrupt controller.
+- interrupts : should specify event (wakeup) IRQ.
Example (MPC8610HPCD):
board-control@e8000000 {
compatible = "fsl,fpga-pixis";
reg = <0xe8000000 32>;
+ interrupt-parent = <&mpic>;
+ interrupts = <8 8>;
};
* Freescale BCSR GPIO banks
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index f468d21..9535ce6 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -35,6 +35,8 @@
i-cache-line-size = <32>;
d-cache-size = <32768>; // L1
i-cache-size = <32768>; // L1
+ sleep = <&pmc 0x00008000 0 // core
+ &pmc 0x00004000 0>; // timebase
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
@@ -60,6 +62,7 @@
5 0 0xe8480000 0x00008000
6 0 0xe84c0000 0x00008000
3 0 0xe8000000 0x00000020>;
+ sleep = <&pmc 0x08000000 0>;
flash@0,0 {
compatible = "cfi-flash";
@@ -105,6 +108,8 @@
compatible = "fsl,fpga-pixis";
reg = <3 0 0x20>;
ranges = <0 3 0 0x20>;
+ interrupt-parent = <&mpic>;
+ interrupts = <8 8>;
sdcsr_pio: gpio-controller@a {
#gpio-cells = <2>;
@@ -163,6 +168,7 @@
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
+ sleep = <&pmc 0x00000004 0>;
dfsrr;
};
@@ -174,6 +180,7 @@
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
+ sleep = <&pmc 0x00000002 0>;
};
serial1: serial@4600 {
@@ -184,6 +191,7 @@
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
+ sleep = <&pmc 0x00000008 0>;
};
spi@7000 {
@@ -196,6 +204,7 @@
interrupt-parent = <&mpic>;
mode = "cpu";
gpios = <&sdcsr_pio 7 0>;
+ sleep = <&pmc 0x00000800 0>;
mmc-slot@0 {
compatible = "fsl,mpc8610hpcd-mmc-slot",
@@ -213,6 +222,7 @@
reg = <0x2c000 100>;
interrupts = <72 2>;
interrupt-parent = <&mpic>;
+ sleep = <&pmc 0x04000000 0>;
};
mpic: interrupt-controller@40000 {
@@ -241,9 +251,18 @@
};
global-utilities@e0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "fsl,mpc8610-guts";
reg = <0xe0000 0x1000>;
+ ranges = <0 0xe0000 0x1000>;
fsl,has-rstcr;
+
+ pmc: power@70 {
+ compatible = "fsl,mpc8610-pmc",
+ "fsl,mpc8641d-pmc";
+ reg = <0x70 0x20>;
+ };
};
wdt@e4000 {
@@ -262,6 +281,7 @@
fsl,playback-dma = <&dma00>;
fsl,capture-dma = <&dma01>;
fsl,fifo-depth = <8>;
+ sleep = <&pmc 0 0x08000000>;
};
ssi@16100 {
@@ -271,6 +291,7 @@
interrupt-parent = <&mpic>;
interrupts = <63 2>;
fsl,fifo-depth = <8>;
+ sleep = <&pmc 0 0x04000000>;
};
dma@21300 {
@@ -280,6 +301,7 @@
cell-index = <0>;
reg = <0x21300 0x4>; /* DMA general status register */
ranges = <0x0 0x21100 0x200>;
+ sleep = <&pmc 0x00000400 0>;
dma00: dma-channel@0 {
compatible = "fsl,mpc8610-dma-channel",
@@ -322,6 +344,7 @@
cell-index = <1>;
reg = <0xc300 0x4>; /* DMA general status register */
ranges = <0x0 0xc100 0x200>;
+ sleep = <&pmc 0x00000200 0>;
dma-channel@0 {
compatible = "fsl,mpc8610-dma-channel",
@@ -369,6 +392,7 @@
bus-range = <0 0>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
+ sleep = <&pmc 0x80000000 0>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
@@ -398,6 +422,7 @@
bus-range = <1 3>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
+ sleep = <&pmc 0x40000000 0>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
@@ -474,6 +499,7 @@
0x0000 0 0 4 &mpic 7 1>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
+ sleep = <&pmc 0x20000000 0>;
clock-frequency = <33333333>;
};
};
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 627908a..5abe137 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -19,6 +19,7 @@
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/pci.h>
+#include <linux/interrupt.h>
#include <linux/kdev_t.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
@@ -41,10 +42,46 @@
#include "mpc86xx.h"
+static struct device_node *pixis_node;
static unsigned char *pixis_bdcfg0, *pixis_arch;
+#ifdef CONFIG_SUSPEND
+static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
+{
+ pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
+ return IRQ_HANDLED;
+}
+
+static void __init mpc8610_suspend_init(void)
+{
+ int irq;
+ int ret;
+
+ if (!pixis_node)
+ return;
+
+ irq = irq_of_parse_and_map(pixis_node, 0);
+ if (!irq) {
+ pr_err("%s: can't map pixis event IRQ.\n", __func__);
+ return;
+ }
+
+ ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9/wakeup", NULL);
+ if (ret) {
+ pr_err("%s: can't request pixis event IRQ: %d\n",
+ __func__, ret);
+ irq_dispose_mapping(irq);
+ }
+
+ enable_irq_wake(irq);
+}
+#else
+static inline void mpc8610_suspend_init(void) { }
+#endif /* CONFIG_SUSPEND */
+
static struct of_device_id __initdata mpc8610_ids[] = {
{ .compatible = "fsl,mpc8610-immr", },
+ { .compatible = "fsl,mpc8610-guts", },
{ .compatible = "simple-bus", },
{ .compatible = "gianfar", },
{}
@@ -55,6 +92,9 @@ static int __init mpc8610_declare_of_platform_devices(void)
/* Firstly, register PIXIS GPIOs. */
simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
+ /* Enable wakeup on PIXIS' event IRQ. */
+ mpc8610_suspend_init();
+
/* Without this call, the SSI device driver won't get probed. */
of_platform_bus_probe(NULL, mpc8610_ids, NULL);
@@ -250,10 +290,10 @@ static void __init mpc86xx_hpcd_setup_arch(void)
diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
#endif
- np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
- if (np) {
- of_address_to_resource(np, 0, &r);
- of_node_put(np);
+ pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
+ if (pixis_node) {
+ of_address_to_resource(pixis_node, 0, &r);
+ of_node_put(pixis_node);
pixis = ioremap(r.start, 32);
if (!pixis) {
printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
--
1.6.3.3
^ permalink raw reply related
* [PATCH 5/5] powerpc/83xx: Add power management support for MPC83xx QE boards
From: Anton Vorontsov @ 2009-08-30 19:37 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev, Timur Tabi
In-Reply-To: <20090830193625.GA14693@oksana.dev.rtsoft.ru>
Simply add power management controller nodes and sleep properties.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/boot/dts/kmeter1.dts | 7 +++++++
arch/powerpc/boot/dts/mpc832x_mds.dts | 9 +++++++++
arch/powerpc/boot/dts/mpc832x_rdb.dts | 9 +++++++++
arch/powerpc/boot/dts/mpc836x_mds.dts | 9 +++++++++
arch/powerpc/boot/dts/mpc836x_rdk.dts | 9 +++++++++
5 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
index 167044f..65b8b4f 100644
--- a/arch/powerpc/boot/dts/kmeter1.dts
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -59,6 +59,13 @@
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>; /* Filled in by U-Boot */
+ pmc: power@b00 {
+ compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
+ reg = <0xb00 0x100 0xa00 0x100>;
+ interrupts = <80 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 436c9c6..05ad8c9 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -79,6 +79,13 @@
reg = <0x200 0x100>;
};
+ pmc: power@b00 {
+ compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
+ reg = <0xb00 0x100 0xa00 0x100>;
+ interrupts = <80 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -163,6 +170,7 @@
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x4c>;
fsl,descriptor-types-mask = <0x0122003f>;
+ sleep = <&pmc 0x03000000>;
};
ipic: pic@700 {
@@ -428,5 +436,6 @@
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
+ sleep = <&pmc 0x00010000>;
};
};
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index 9a0952f..f4fadb2 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -62,6 +62,13 @@
reg = <0x200 0x100>;
};
+ pmc: power@b00 {
+ compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
+ reg = <0xb00 0x100 0xa00 0x100>;
+ interrupts = <80 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -141,6 +148,7 @@
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x4c>;
fsl,descriptor-types-mask = <0x0122003f>;
+ sleep = <&pmc 0x03000000>;
};
ipic:pic@700 {
@@ -360,5 +368,6 @@
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
+ sleep = <&pmc 0x00010000>;
};
};
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 39ff4c8..45cfa1c 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -99,6 +99,13 @@
reg = <0x200 0x100>;
};
+ pmc: power@b00 {
+ compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
+ reg = <0xb00 0x100 0xa00 0x100>;
+ interrupts = <80 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -194,6 +201,7 @@
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x7e>;
fsl,descriptor-types-mask = <0x01010ebf>;
+ sleep = <&pmc 0x03000000>;
};
ipic: pic@700 {
@@ -470,5 +478,6 @@
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
+ sleep = <&pmc 0x00010000>;
};
};
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index 6315d6f..bdf4459 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -71,6 +71,13 @@
reg = <0x200 0x100>;
};
+ pmc: power@b00 {
+ compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
+ reg = <0xb00 0x100 0xa00 0x100>;
+ interrupts = <80 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -161,6 +168,7 @@
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x7e>;
fsl,descriptor-types-mask = <0x01010ebf>;
+ sleep = <&pmc 0x03000000>;
};
ipic: interrupt-controller@700 {
@@ -455,6 +463,7 @@
0xa800 0 0 2 &ipic 20 8
0xa800 0 0 3 &ipic 21 8
0xa800 0 0 4 &ipic 18 8>;
+ sleep = <&pmc 0x00010000>;
/* filled by u-boot */
bus-range = <0 0>;
clock-frequency = <0>;
--
1.6.3.3
^ permalink raw reply related
* Re: [PATCH] powermac: thermal control turns system off in normal temperature conditions
From: Benjamin Herrenschmidt @ 2009-08-30 21:22 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz; +Cc: linuxppc-dev, linux-kernel, Lyonel Vincent
In-Reply-To: <200908302054.20498.bzolnier@gmail.com>
On Sun, 2009-08-30 at 20:54 +0200, Bartlomiej Zolnierkiewicz wrote:
> From: Lyonel Vincent <lyonel@ezix.org>
> Subject: [PATCH] powermac: thermal control turns system off in normal temperature conditions
>
> On certain PowerMacs, a module (therm_windtunnel) controls various
> thermal settings (it can report CPU/case temperature, change speed
> of internal fans, etc.)
>
> By default, the hardware thermal control has a temperature limit to
> protect the computer from damages (the default limit seems to be 80°C)
> but therm_windtunnel.c reduces it to an anormaly low value (65°C),
> which means that he computer will shut down randomly when hit by direct
> sun light or during summer (summer in France can be quite hot), actually
> possibly losing data instead of protecting it.
>
> The overheat limit in therm_windtunnel.c:253-254 should be set to 75°C
> and 70°C instead of 65°C and 60°C respectively.
Looks reasonable, thanks.
Ben.
> From: Lyonel Vincent <lyonel@ezix.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
> ---
> Resurrected from Fedora's bugzilla (aka The Big Black Hole):
> https://bugzilla.redhat.com/show_bug.cgi?id=171937
>
> The patch itself seems perfectly valid to me
> (especially given comments in therm_windtunnel.c).
>
> drivers/macintosh/therm_windtunnel.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Index: b/drivers/macintosh/therm_windtunnel.c
> ===================================================================
> --- a/drivers/macintosh/therm_windtunnel.c
> +++ b/drivers/macintosh/therm_windtunnel.c
> @@ -239,8 +239,8 @@ setup_hardware( void )
> * to be on the safe side (OSX doesn't)...
> */
> if( x.overheat_temp == (80 << 8) ) {
> - x.overheat_temp = 65 << 8;
> - x.overheat_hyst = 60 << 8;
> + x.overheat_temp = 75 << 8;
> + x.overheat_hyst = 70 << 8;
> write_reg( x.thermostat, 2, x.overheat_hyst, 2 );
> write_reg( x.thermostat, 3, x.overheat_temp, 2 );
>
^ permalink raw reply
* RE: [PATCH 1/5] powerpc/qe: Make qe_reset() code path safe for repeated invocation
From: Tabi Timur-B04825 @ 2009-08-31 0:36 UTC (permalink / raw)
To: Anton Vorontsov, Kumar Gala; +Cc: Wood Scott-B07421, linuxppc-dev
In-Reply-To: <20090830193715.GA17519@oksana.dev.rtsoft.ru>
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Is the need to reinitialize the QE after resume something that is unique to the 8569, or would it apply to the 8360 and 8323 also?
-----Original Message-----
From: Anton Vorontsov [mailto:avorontsov@ru.mvista.com]
Sent: Sun 8/30/2009 2:37 PM
To: Kumar Gala
Cc: Tabi Timur-B04825; Wood Scott-B07421; linuxppc-dev@ozlabs.org
Subject: [PATCH 1/5] powerpc/qe: Make qe_reset() code path safe for repeated invocation
For MPC8569 CPUs we'll need to reset QE after each suspend, so make
qe_reset() code path suitable for repeated invocation, that is:
- Don't initialize rheap structures if already initialized;
- Don't allocate muram for SDMA if already allocated, just reinitialize
registers with previously allocated muram offset;
- Remove __init attributes from qe_reset() and cpm_muram_init();
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/include/asm/qe.h | 2 +-
arch/powerpc/sysdev/cpm_common.c | 5 ++++-
arch/powerpc/sysdev/qe_lib/qe.c | 12 +++++++-----
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index e8232bb..2f44754 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -87,7 +87,7 @@ extern spinlock_t cmxgcr_lock;
/* Export QE common operations */
#ifdef CONFIG_QUICC_ENGINE
-extern void __init qe_reset(void);
+extern void qe_reset(void);
#else
static inline void qe_reset(void) {}
#endif
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index e4b6d66..9de72c9 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -72,7 +72,7 @@ static phys_addr_t muram_pbase;
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
-int __init cpm_muram_init(void)
+int cpm_muram_init(void)
{
struct device_node *np;
struct resource r;
@@ -81,6 +81,9 @@ int __init cpm_muram_init(void)
int i = 0;
int ret = 0;
+ if (muram_pbase)
+ return 0;
+
spin_lock_init(&cpm_muram_lock);
/* initialize the info header */
rh_init(&cpm_muram_info, 1,
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index b06564f..4eaf2a9 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -91,7 +91,7 @@ phys_addr_t get_qe_base(void)
EXPORT_SYMBOL(get_qe_base);
-void __init qe_reset(void)
+void qe_reset(void)
{
if (qe_immr == NULL)
qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
@@ -317,16 +317,18 @@ EXPORT_SYMBOL(qe_put_snum);
static int qe_sdma_init(void)
{
struct sdma __iomem *sdma = &qe_immr->sdma;
- unsigned long sdma_buf_offset;
+ static unsigned long sdma_buf_offset = (unsigned long)-ENOMEM;
if (!sdma)
return -ENODEV;
/* allocate 2 internal temporary buffers (512 bytes size each) for
* the SDMA */
- sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
- if (IS_ERR_VALUE(sdma_buf_offset))
- return -ENOMEM;
+ if (IS_ERR_VALUE(sdma_buf_offset)) {
+ sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
+ if (IS_ERR_VALUE(sdma_buf_offset))
+ return -ENOMEM;
+ }
out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
--
1.6.3.3
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* RE: [PATCH 2/5] powerpc/85xx/86xx: Add suspend/resume support
From: Tabi Timur-B04825 @ 2009-08-31 0:38 UTC (permalink / raw)
To: Anton Vorontsov, Kumar Gala; +Cc: Wood Scott-B07421, linuxppc-dev
In-Reply-To: <20090830193718.GB17519@oksana.dev.rtsoft.ru>
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What about the 8610?
-----Original Message-----
From: Anton Vorontsov [mailto:avorontsov@ru.mvista.com]
Sent: Sun 8/30/2009 2:37 PM
To: Kumar Gala
Cc: Tabi Timur-B04825; Wood Scott-B07421; linuxppc-dev@ozlabs.org
Subject: [PATCH 2/5] powerpc/85xx/86xx: Add suspend/resume support
This patch adds suspend/resume support for MPC8540, MPC8569 and
MPC8641D-compatible CPUs.
MPC8540 and MPC8641D-compatible PMCs are trivial: we just write
the SLP bit into the PM control and status register.
MPC8569 is a bit trickier, QE turns off during suspend, thus on
resume we must reload QE microcode and reset QE.
So far we don't support Deep Sleep mode as found in newer MPC85xx
CPUs (i.e. MPC8536). It can be relatively easy implemented though,
and for it we reserve 'mem' suspend type.
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^ permalink raw reply
* [PATCH] lmb: Also remove __init from lmb_end_of_RAM() declaration in lmb.h
From: Benjamin Herrenschmidt @ 2009-08-31 3:48 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev, Linux Kernel list, David S. Miller
Previous patch removed __init in lmb.c but missed the fact
that it was also marked as such in the .h
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
And this one I tested :-)
Cheers,
Ben.
diff --git a/include/linux/lmb.h b/include/linux/lmb.h
index c46c895..2442e3f 100644
--- a/include/linux/lmb.h
+++ b/include/linux/lmb.h
@@ -51,7 +51,7 @@ extern u64 __init lmb_alloc_base(u64 size,
extern u64 __init __lmb_alloc_base(u64 size,
u64 align, u64 max_addr);
extern u64 __init lmb_phys_mem_size(void);
-extern u64 __init lmb_end_of_DRAM(void);
+extern u64 lmb_end_of_DRAM(void);
extern void __init lmb_enforce_memory_limit(u64 memory_limit);
extern int __init lmb_is_reserved(u64 addr);
extern int lmb_find(struct lmb_property *res);
^ permalink raw reply related
* [PATCH] powerpc: Fix some late PowerMac G5 with PCIe ATI graphics
From: Benjamin Herrenschmidt @ 2009-08-31 3:48 UTC (permalink / raw)
To: linuxppc-dev list
A misconfiguration by the firmware of the U4 PCIe bridge on PowerMac G5
with the U4 bridge (latest generations, may also affect the iMac G5
"iSight") is causing us to re-assign the PCI BARs of the video card,
which can get it out of sync with the firmware, thus breaking offb.
This works around it by fixing up the bridge configuration properly
at boot time.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/platforms/powermac/pci.c | 60 +++++++++++++++++++++++++++++++++
include/linux/pci_ids.h | 1 +
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 04cdd32..7913b57 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -1286,3 +1286,63 @@ static void fixup_k2_sata(struct pci_dev* dev)
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
+/*
+ * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't
+ * configured by the firmware. The bridge itself seems to ignore them but it
+ * causes problems with Linux which then re-assigns devices below the bridge,
+ * thus changing addresses of those devices from what was in the device-tree,
+ * which sucks when those are video cards using offb
+ *
+ * We could just mark it transparent but I prefer fixing up the resources to
+ * properly show what's going on here, as I have some doubts about having them
+ * badly configured potentially being an issue for DMA.
+ *
+ * We leave PIO alone, it seems to be fine
+ */
+static void fixup_u4_pcie(struct pci_dev* dev)
+{
+ struct pci_controller *host = pci_bus_to_host(dev->bus);
+ struct resource *first = NULL, *second = NULL;
+ u32 reg;
+ int i;
+
+ /* Only do that on PowerMac */
+ if (!machine_is(powermac))
+ return;
+
+ /* Find two largest MMIO regions */
+ for (i = 0; i < 3; i++) {
+ struct resource *r = &host->mem_resources[i];
+ if (!(r->flags & IORESOURCE_MEM))
+ continue;
+ if (!first || (r->end - r->start) >
+ (first->end - first->start)) {
+ second = first;
+ first = r;
+ }
+ }
+ /* Nothing found, bail */
+ if (first == 0)
+ return;
+
+ /* Print things out */
+ printk(KERN_INFO "PCI: Fixup U4 PCIe bridge ranges\n");
+ printk(KERN_INFO " first: %pR\n", first);
+ if (second)
+ printk(KERN_INFO " second: %pR\n", second);
+
+ /* Fixup bridge config space. We know it's a Mac, resource aren't
+ * offset so let's just blast them as-is. We also know that they
+ * fit in 32 bits
+ */
+ reg = ((first->start >> 16) & 0xfff0) | (first->end & 0xfff00000);
+ pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);
+ pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
+ pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, reg);
+ if (second) {
+ reg = ((second->start >> 16) & 0xfff0) |
+ (second->end & 0xfff00000);
+ pci_write_config_dword(dev, PCI_MEMORY_BASE, reg);
+ }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 73b46b6..c86bb6e 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -877,6 +877,7 @@
#define PCI_DEVICE_ID_APPLE_SH_SUNGEM 0x0051
#define PCI_DEVICE_ID_APPLE_U3L_AGP 0x0058
#define PCI_DEVICE_ID_APPLE_U3H_AGP 0x0059
+#define PCI_DEVICE_ID_APPLE_U4_PCIE 0x005b
#define PCI_DEVICE_ID_APPLE_IPID2_AGP 0x0066
#define PCI_DEVICE_ID_APPLE_IPID2_ATA 0x0069
#define PCI_DEVICE_ID_APPLE_IPID2_FW 0x006a
--
1.6.1.2.14.gf26b5
^ permalink raw reply related
* Re: [PATCH 1/5] ucc_geth: Fix NULL pointer dereference in uec_get_ethtool_stats()
From: David Miller @ 2009-08-31 4:52 UTC (permalink / raw)
To: avorontsov; +Cc: netdev, linuxppc-dev, scottwood, timur
In-Reply-To: <20090827173547.GA1580@oksana.dev.rtsoft.ru>
All 5 patches applied to net-next-2.6
I would have liked to have seen at least one powerpc ACK for
patch #2 but these were posted more than a week ago, the
patch looks pretty reasonable, and we can't wait forever for
stuff like this.
^ permalink raw reply
* Re: [PATCH 1/1] powerpc: Fix to handle slb resize across migration
From: Benjamin Herrenschmidt @ 2009-08-31 6:22 UTC (permalink / raw)
To: Brian King; +Cc: linuxppc-dev
In-Reply-To: <200908282206.n7SM6UK1011114@d03av01.boulder.ibm.com>
On Fri, 2009-08-28 at 17:06 -0500, Brian King wrote:
> The SLB can change sizes across a live migration, which was not
> being handled, resulting in possible machine crashes during
> migration if migrating to a machine which has a smaller max SLB
> size than the source machine. Fix this by first reducing the
> SLB size to the minimum possible value, which is 32, prior to
> migration. Then during the device tree update which occurs after
> migration, we make the call to ensure the SLB gets updated. Also
> add the slb_size to the lparcfg output so that the migration
> tools can check to make sure the kernel has this capability
> before allowing migration in scenarios where the SLB size will change.
>
> Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
> ---
Thanks. I'll apply to -next hopefully tomorrow, and then we can send it
to the various -stable.
Cheers,
Ben.
> arch/powerpc/include/asm/mmu-hash64.h | 2 ++
> arch/powerpc/kernel/lparcfg.c | 3 +++
> arch/powerpc/kernel/rtas.c | 7 ++++++-
> arch/powerpc/mm/slb.c | 16 ++++++++++++----
> arch/powerpc/platforms/pseries/reconfig.c | 9 ++++++++-
> 5 files changed, 31 insertions(+), 6 deletions(-)
>
> diff -puN arch/powerpc/kernel/rtas.c~powerpc_slb_resize arch/powerpc/kernel/rtas.c
> --- linux-2.6/arch/powerpc/kernel/rtas.c~powerpc_slb_resize 2009-08-21 16:14:41.000000000 -0500
> +++ linux-2.6-bjking1/arch/powerpc/kernel/rtas.c 2009-08-21 16:14:41.000000000 -0500
> @@ -39,6 +39,7 @@
> #include <asm/smp.h>
> #include <asm/atomic.h>
> #include <asm/time.h>
> +#include <asm/mmu-hash64.h>
>
> struct rtas_t rtas = {
> .lock = __RAW_SPIN_LOCK_UNLOCKED
> @@ -713,6 +714,7 @@ static void rtas_percpu_suspend_me(void
> {
> long rc = H_SUCCESS;
> unsigned long msr_save;
> + u16 slb_size = mmu_slb_size;
> int cpu;
> struct rtas_suspend_me_data *data =
> (struct rtas_suspend_me_data *)info;
> @@ -735,13 +737,16 @@ static void rtas_percpu_suspend_me(void
> /* All other cpus are in H_JOIN, this cpu does
> * the suspend.
> */
> + slb_set_size(SLB_MIN_SIZE);
> printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n",
> smp_processor_id());
> data->error = rtas_call(data->token, 0, 1, NULL);
>
> - if (data->error)
> + if (data->error) {
> printk(KERN_DEBUG "ibm,suspend-me returned %d\n",
> data->error);
> + slb_set_size(slb_size);
> + }
> } else {
> printk(KERN_ERR "H_JOIN on cpu %i failed with rc = %ld\n",
> smp_processor_id(), rc);
> diff -puN arch/powerpc/include/asm/mmu-hash64.h~powerpc_slb_resize arch/powerpc/include/asm/mmu-hash64.h
> --- linux-2.6/arch/powerpc/include/asm/mmu-hash64.h~powerpc_slb_resize 2009-08-21 16:14:41.000000000 -0500
> +++ linux-2.6-bjking1/arch/powerpc/include/asm/mmu-hash64.h 2009-08-21 16:14:41.000000000 -0500
> @@ -41,6 +41,7 @@ extern char initial_stab[];
>
> #define SLB_NUM_BOLTED 3
> #define SLB_CACHE_ENTRIES 8
> +#define SLB_MIN_SIZE 32
>
> /* Bits in the SLB ESID word */
> #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
> @@ -296,6 +297,7 @@ extern void slb_flush_and_rebolt(void);
> extern void stab_initialize(unsigned long stab);
>
> extern void slb_vmalloc_update(void);
> +extern void slb_set_size(u16 size);
> #endif /* __ASSEMBLY__ */
>
> /*
> diff -puN arch/powerpc/mm/slb.c~powerpc_slb_resize arch/powerpc/mm/slb.c
> --- linux-2.6/arch/powerpc/mm/slb.c~powerpc_slb_resize 2009-08-21 16:14:41.000000000 -0500
> +++ linux-2.6-bjking1/arch/powerpc/mm/slb.c 2009-08-21 16:14:41.000000000 -0500
> @@ -240,14 +240,22 @@ void switch_slb(struct task_struct *tsk,
> static inline void patch_slb_encoding(unsigned int *insn_addr,
> unsigned int immed)
> {
> - /* Assume the instruction had a "0" immediate value, just
> - * "or" in the new value
> - */
> - *insn_addr |= immed;
> + *insn_addr = (*insn_addr & 0xffff0000) | immed;
> flush_icache_range((unsigned long)insn_addr, 4+
> (unsigned long)insn_addr);
> }
>
> +void slb_set_size(u16 size)
> +{
> + extern unsigned int *slb_compare_rr_to_size;
> +
> + if (mmu_slb_size == size)
> + return;
> +
> + mmu_slb_size = size;
> + patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
> +}
> +
> void slb_initialize(void)
> {
> unsigned long linear_llp, vmalloc_llp, io_llp;
> diff -puN arch/powerpc/platforms/pseries/reconfig.c~powerpc_slb_resize arch/powerpc/platforms/pseries/reconfig.c
> --- linux-2.6/arch/powerpc/platforms/pseries/reconfig.c~powerpc_slb_resize 2009-08-21 16:14:41.000000000 -0500
> +++ linux-2.6-bjking1/arch/powerpc/platforms/pseries/reconfig.c 2009-08-28 13:36:55.000000000 -0500
> @@ -20,6 +20,7 @@
> #include <asm/machdep.h>
> #include <asm/uaccess.h>
> #include <asm/pSeries_reconfig.h>
> +#include <asm/mmu-hash64.h>
>
>
>
> @@ -439,9 +440,15 @@ static int do_update_property(char *buf,
> if (!newprop)
> return -ENOMEM;
>
> + if (!strcmp(name, "slb-size") || !strcmp(name, "ibm,slb-size"))
> + slb_set_size(*(int *)value);
> +
> oldprop = of_find_property(np, name,NULL);
> - if (!oldprop)
> + if (!oldprop) {
> + if (strlen(name))
> + return prom_add_property(np, newprop);
> return -ENODEV;
> + }
>
> rc = prom_update_property(np, newprop, oldprop);
> if (rc)
> diff -puN arch/powerpc/kernel/lparcfg.c~powerpc_slb_resize arch/powerpc/kernel/lparcfg.c
> --- linux-2.6/arch/powerpc/kernel/lparcfg.c~powerpc_slb_resize 2009-08-21 16:14:41.000000000 -0500
> +++ linux-2.6-bjking1/arch/powerpc/kernel/lparcfg.c 2009-08-21 16:14:41.000000000 -0500
> @@ -35,6 +35,7 @@
> #include <asm/prom.h>
> #include <asm/vdso_datapage.h>
> #include <asm/vio.h>
> +#include <asm/mmu-hash64.h>
>
> #define MODULE_VERS "1.8"
> #define MODULE_NAME "lparcfg"
> @@ -537,6 +538,8 @@ static int pseries_lparcfg_data(struct s
>
> seq_printf(m, "shared_processor_mode=%d\n", lppaca[0].shared_proc);
>
> + seq_printf(m, "slb_size=%d\n", mmu_slb_size);
> +
> return 0;
> }
>
> _
^ permalink raw reply
* RE: [PATCH v2] powerpc/85xx: Add eSDHC support for MPC8536DS boards
From: Hu Mingkai-B21284 @ 2009-08-31 7:51 UTC (permalink / raw)
To: avorontsov
Cc: Ben Dooks, linux-kernel, sdhci-devel, linuxppc-dev, Andrew Morton,
Pierre Ossman, David Vrabel
In-Reply-To: <20090828151953.GA14776@oksana.dev.rtsoft.ru>
=20
> -----Original Message-----
> From: Anton Vorontsov [mailto:avorontsov@ru.mvista.com]=20
> Sent: Friday, August 28, 2009 11:20 PM
> To: Hu Mingkai-B21284
> Cc: Kumar Gala; Ben Dooks; linux-kernel@vger.kernel.org;=20
> sdhci-devel@lists.ossman.eu; linuxppc-dev@ozlabs.org; Andrew=20
> Morton; Pierre Ossman; David Vrabel
> Subject: Re: [PATCH v2] powerpc/85xx: Add eSDHC support for=20
> MPC8536DS boards
>=20
> On Fri, Aug 28, 2009 at 07:02:51PM +0800, Hu Mingkai-B21284 wrote:
> > > On Tue, Aug 18, 2009 at 08:24:17PM -0500, Kumar Gala wrote:
> > > >=20
> > > > On Aug 18, 2009, at 6:38 PM, Anton Vorontsov wrote:
> > > >=20
> > > > >This patch simply adds sdhci node to the device tree.
> > > > >
> > > > >We specify clock-frequency manually, so that eSDHC will
> > > work without
> > > > >upgrading U-Boot. Though, that'll only work for default setup=20
> > > > >(1500
> > > > >MHz) on new board revisions. For non-default setups, it's
> > > recommended
> > > > >to upgrade U-Boot, since it will fixup clock-frequency
> > > automatically.
> > > > >
> > > > >Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> > > >=20
> > > > out of interest the 85xx eSDHC don't need the sdhci,wp-inverted=20
> > > > property?
> > >=20
> > > Yes, eSDHC controllers in MPC85xx report normal state in its=20
> > > registers.
> > >=20
> >=20
> > Hi Anton,
> >=20
> > The eSDHC controller in different silicon version on=20
> MPC8536 reports=20
> > different WP state in the register PRSSTAT:
>=20
> Thanks a million for the heads up!
>=20
> Yes, the manual I used ("MPC8536ERM Rev. 0 10/2008") doesn't=20
> mention that, but the newer manual that I just downloaded=20
> ("MPC8536ERM Rev. 1
> 05/2009") does.
>=20
> [...]
> > For silicon 1.0, the macro=20
> SDHCI_QUIRK_INVERTED_WRITE_PROTECT is also=20
> > defined, so the dirver will report the error WP state in function=20
> > sdhci_get_ro.
>=20
> Not any longer. We don't actually define it for any 85xx CPUs.
>=20
> I need to think how should we handle all these WP inversions. :-)
>=20
> So, we have inversion in BCSR (depending on the BCSR=20
> revision), configurable inversion in CPU via GENCFGR for 1.1=20
> silicon, and non-configurable non-inverted reporting for 1.0=20
> silicon...
>=20
> Do you know if there are any plans to fix the WP inversion=20
> for MPC8569E-MDS boards, or make something like GENCFGR for=20
> MPC8569 CPUs?
>=20
> Thanks,
>=20
Sorry, I also don't know the plan to MPC8569 CPU, but if I get any info,
I'll inform you ASAP. :-)
Best regards,
Mingkai
> --
> Anton Vorontsov
> email: cbouatmailru@gmail.com
> irc://irc.freenode.net/bd2
>=20
>=20
^ permalink raw reply
* Re: [PATCH] powermac: thermal control turns system off in normal temperature conditions
From: Benjamin Herrenschmidt @ 2009-08-31 9:32 UTC (permalink / raw)
To: Linux User #330250; +Cc: linuxppc-dev, Bartlomiej Zolnierkiewicz
In-Reply-To: <200908311125.56066.linuxuser330250@gmx.net>
On Mon, 2009-08-31 at 11:25 +0200, Linux User #330250 wrote:
> Hello!
>
> First: I'm just a user. And I hope I don't cause disturbance.
>
> I've read about this when I was setting up Linux on my Power Mac G4 MDD about
> two years ago and I remember reading that the temperature might be reported
> falsely. The original author reduced the limits to be on the safe side.
>
> While Mac OS X seems to push the allowed temperature more to the limits, it
> could still be fatal to trust the reported temperatures.
>
>
> My machine had the same shut-downs due to temperature at first. Since my MDD
> was quite a few years old when I got it I cleaned the CPUs and used new
> thermal compound with the original heatsink. This fixed the "overheat" issue
> for me.
Thanks. I think pushing them a bit like this patch does still remains
within reasonably safe limits though. The CPU should cope with more
hopefully :-)
But yeah, cleaning up the dust is definitely a good idea :-)
Cheers,
Ben.
>
> Sorry to interrupt,
> Andreas aka Linux User #330250
>
>
>
> ---------- Original message ----------
> Subject: [PATCH] powermac: thermal control turns system off in normal
> temperature conditions
> Date: Sonntag, 30. August 2009N
> From: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
> To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> > From: Lyonel Vincent <lyonel@ezix.org>
> > Subject: [PATCH] powermac: thermal control turns system off in normal
> > temperature conditions
> >
> > On certain PowerMacs, a module (therm_windtunnel) controls various
> > thermal settings (it can report CPU/case temperature, change speed
> > of internal fans, etc.)
> >
> > By default, the hardware thermal control has a temperature limit to
> > protect the computer from damages (the default limit seems to be 80°C)
> > but therm_windtunnel.c reduces it to an anormaly low value (65°C),
> > which means that he computer will shut down randomly when hit by direct
> > sun light or during summer (summer in France can be quite hot), actually
> > possibly losing data instead of protecting it.
> >
> > The overheat limit in therm_windtunnel.c:253-254 should be set to 75°C
> > and 70°C instead of 65°C and 60°C respectively.
> >
> > From: Lyonel Vincent <lyonel@ezix.org>
> > Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
> > ---
> > Resurrected from Fedora's bugzilla (aka The Big Black Hole):
> > https://bugzilla.redhat.com/show_bug.cgi?id=171937
> >
> > The patch itself seems perfectly valid to me
> > (especially given comments in therm_windtunnel.c).
> >
> > drivers/macintosh/therm_windtunnel.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > Index: b/drivers/macintosh/therm_windtunnel.c
> > ===================================================================
> > --- a/drivers/macintosh/therm_windtunnel.c
> > +++ b/drivers/macintosh/therm_windtunnel.c
> > @@ -239,8 +239,8 @@ setup_hardware( void )
> > * to be on the safe side (OSX doesn't)...
> > */
> > if( x.overheat_temp == (80 << 8) ) {
> > - x.overheat_temp = 65 << 8;
> > - x.overheat_hyst = 60 << 8;
> > + x.overheat_temp = 75 << 8;
> > + x.overheat_hyst = 70 << 8;
> > write_reg( x.thermostat, 2, x.overheat_hyst, 2 );
> > write_reg( x.thermostat, 3, x.overheat_temp, 2 );
^ permalink raw reply
* Re: [PATCH] powermac: thermal control turns system off in normal temperature conditions
From: Linux User #330250 @ 2009-08-31 9:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Bartlomiej Zolnierkiewicz
In-Reply-To: <200908302054.20498.bzolnier@gmail.com>
Hello!
=46irst: I'm just a user. And I hope I don't cause disturbance.
I've read about this when I was setting up Linux on my Power Mac G4 MDD abo=
ut=20
two years ago and I remember reading that the temperature might be reported=
=20
falsely. The original author reduced the limits to be on the safe side.
While Mac OS X seems to push the allowed temperature more to the limits, it=
=20
could still be fatal to trust the reported temperatures.
My machine had the same shut-downs due to temperature at first. Since my MD=
D=20
was quite a few years old when I got it I cleaned the CPUs and used new=20
thermal compound with the original heatsink. This fixed the "overheat" issu=
e=20
for me.
Sorry to interrupt,
Andreas aka Linux User #330250
=2D--------- Original message ----------
Subject: [PATCH] powermac: thermal control turns system off in normal=20
temperature conditions
Date: Sonntag, 30. August 2009N
=46rom: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> From: Lyonel Vincent <lyonel@ezix.org>
> Subject: [PATCH] powermac: thermal control turns system off in normal
> temperature conditions
>
> On certain PowerMacs, a module (therm_windtunnel) controls various
> thermal settings (it can report CPU/case temperature, change speed
> of internal fans, etc.)
>
> By default, the hardware thermal control has a temperature limit to
> protect the computer from damages (the default limit seems to be 80=B0C)
> but therm_windtunnel.c reduces it to an anormaly low value (65=B0C),
> which means that he computer will shut down randomly when hit by direct
> sun light or during summer (summer in France can be quite hot), actually
> possibly losing data instead of protecting it.
>
> The overheat limit in therm_windtunnel.c:253-254 should be set to 75=B0C
> and 70=B0C instead of 65=B0C and 60=B0C respectively.
>
> From: Lyonel Vincent <lyonel@ezix.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
> ---
> Resurrected from Fedora's bugzilla (aka The Big Black Hole):
> https://bugzilla.redhat.com/show_bug.cgi?id=3D171937
>
> The patch itself seems perfectly valid to me
> (especially given comments in therm_windtunnel.c).
>
> drivers/macintosh/therm_windtunnel.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Index: b/drivers/macintosh/therm_windtunnel.c
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- a/drivers/macintosh/therm_windtunnel.c
> +++ b/drivers/macintosh/therm_windtunnel.c
> @@ -239,8 +239,8 @@ setup_hardware( void )
> * to be on the safe side (OSX doesn't)...
> */
> if( x.overheat_temp =3D=3D (80 << 8) ) {
> - x.overheat_temp =3D 65 << 8;
> - x.overheat_hyst =3D 60 << 8;
> + x.overheat_temp =3D 75 << 8;
> + x.overheat_hyst =3D 70 << 8;
> write_reg( x.thermostat, 2, x.overheat_hyst, 2 );
> write_reg( x.thermostat, 3, x.overheat_temp, 2 );
^ permalink raw reply
* Re: [PATCH 1/5] ucc_geth: Fix NULL pointer dereference in uec_get_ethtool_stats()
From: Benjamin Herrenschmidt @ 2009-08-31 9:35 UTC (permalink / raw)
To: David Miller; +Cc: scottwood, netdev, timur, linuxppc-dev
In-Reply-To: <20090830.215224.203201252.davem@davemloft.net>
On Sun, 2009-08-30 at 21:52 -0700, David Miller wrote:
> All 5 patches applied to net-next-2.6
>
> I would have liked to have seen at least one powerpc ACK for
> patch #2 but these were posted more than a week ago, the
> patch looks pretty reasonable, and we can't wait forever for
> stuff like this.
The qe stuff ? Well, that's entirely Kumar's domain, but Anton
patches tend to be of good quality so I wouldn't have too much
second thoughts here.
Cheers,
Ben.
^ permalink raw reply
* [PATCH][v3] powerpc/85xx: P1020RDB Support Added
From: Poonam Aggrwal @ 2009-08-31 11:52 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Poonam Aggrwal
P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new controller).
>From board perspective P1020RDB is same as P2020RDB.
* This code adds the basic basic platform support for P1020RDB.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch->next
- The patch does not contain ethernet support because P1020 contains new eTSEC
controller. The support will be added in the later patches.
arch/powerpc/boot/dts/p1020rdb.dts | 477 +++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 ++
2 files changed, 501 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020rdb.dts
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
new file mode 100644
index 0000000..de5672c
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -0,0 +1,477 @@
+/*
+ * P1020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P1020";
+ compatible = "fsl,P1020RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P1020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P1020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus@ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ /* NOR and NAND Flashes */
+ ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+ 0x1 0x0 0x0 0xffa00000 0x00040000
+ 0x2 0x0 0x0 0xffb00000 0x00020000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = <0x0 0x00040000>;
+ label = "NOR (RO) Vitesse-7385 Firmware";
+ read-only;
+ };
+
+ partition@40000 {
+ /* 256KB for DTB Image */
+ reg = <0x00040000 0x00040000>;
+ label = "NOR (RO) DTB Image";
+ read-only;
+ };
+
+ partition@80000 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = <0x00080000 0x00380000>;
+ label = "NOR (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@400000 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = <0x00400000 0x00b00000>;
+ label = "NOR (RW) JFFS2 Root File System";
+ };
+
+ partition@f00000 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = <0x00f00000 0x00100000>;
+ label = "NOR (RO) U-Boot Image";
+ read-only;
+ };
+ };
+
+ nand@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p1020-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x40000>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND (RO) U-Boot Image";
+ read-only;
+ };
+
+ partition@100000 {
+ /* 1MB for DTB Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NAND (RO) DTB Image";
+ read-only;
+ };
+
+ partition@200000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00200000 0x00400000>;
+ label = "NAND (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@600000 {
+ /* 4MB for Compressed Root file System Image */
+ reg = <0x00600000 0x00400000>;
+ label = "NAND (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ partition@a00000 {
+ /* 7MB for JFFS2 based Root file System */
+ reg = <0x00a00000 0x00700000>;
+ label = "NAND (RW) JFFS2 Root File System";
+ };
+
+ partition@1100000 {
+ /* 15MB for JFFS2 based Root file System */
+ reg = <0x01100000 0x00f00000>;
+ label = "NAND (RW) Writable User area";
+ };
+ };
+
+ L2switch@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "vitesse-7385";
+ reg = <0x2 0x0 0x20000>;
+ };
+
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p1020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <16 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p1020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+
+ fsl_m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,espi-flash";
+ reg = <0>;
+ linux,modalias = "fsl_m25p80";
+ modal = "s25sl128b";
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition@0 {
+ /* 512KB for u-boot Bootloader Image */
+ reg = <0x0 0x00080000>;
+ label = "SPI (RO) U-Boot Image";
+ read-only;
+ };
+
+ partition@80000 {
+ /* 512KB for DTB Image */
+ reg = <0x00080000 0x00080000>;
+ label = "SPI (RO) DTB Image";
+ read-only;
+ };
+
+ partition@100000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00100000 0x00400000>;
+ label = "SPI (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@500000 {
+ /* 4MB for Compressed RFS Image */
+ reg = <0x00500000 0x00400000>;
+ label = "SPI (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ partition@900000 {
+ /* 7MB for JFFS2 based RFS */
+ reg = <0x00900000 0x00700000>;
+ label = "SPI (RW) JFFS2 RFS";
+ };
+ };
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p1020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2,256K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ phy_type = "ulpi";
+ };
+
+ usb@23000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <46 0x2>;
+ phy_type = "ulpi";
+ };
+
+ sdhci@2e000 {
+ compatible = "fsl,p1020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi@41600 {
+ compatible = "fsl,p1020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,p1020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index c8468de..495bd8b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -113,6 +113,7 @@ static int __init mpc85xxrdb_publish_devices(void)
return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
}
machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
+machine_device_initcall(p1020_rdb, mpc85xxrdb_publish_devices);
/*
* Called very early, device-tree isn't unflattened
@@ -126,6 +127,15 @@ static int __init p2020_rdb_probe(void)
return 0;
}
+static int __init p1020_rdb_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "fsl,P1020RDB"))
+ return 1;
+ return 0;
+}
+
define_machine(p2020_rdb) {
.name = "P2020 RDB",
.probe = p2020_rdb_probe,
@@ -139,3 +149,17 @@ define_machine(p2020_rdb) {
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
+
+define_machine(p1020_rdb) {
+ .name = "P1020 RDB",
+ .probe = p1020_rdb_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.5.6.5
^ permalink raw reply related
* Re: [PATCH] [V3] net: add Xilinx emac lite device driver
From: Michal Simek @ 2009-08-31 13:18 UTC (permalink / raw)
To: David Miller
Cc: sadanan, netdev, linuxppc-dev, jgarzik, john.linn, john.williams
In-Reply-To: <20090820.025226.26907868.davem@davemloft.net>
Hi David,
I see that John's patch has wrong file permission
-rwxr-xr-x xilinx_emaclite.c
<http://git.kernel.org/?p=linux/kernel/git/sfr/linux-next.git;a=blob;f=drivers/net/xilinx_emaclite.c;h=7e05b40ae36b50b6eb66d9512ae3a49ba2d36a47;hb=a9a8cb1d6594037fbb23f1ce45964ec6a3b38215>
blob
<http://git.kernel.org/?p=linux/kernel/git/sfr/linux-next.git;a=blob;f=drivers/net/xilinx_emaclite.c;h=7e05b40ae36b50b6eb66d9512ae3a49ba2d36a47;hb=a9a8cb1d6594037fbb23f1ce45964ec6a3b38215>
| history
<http://git.kernel.org/?p=linux/kernel/git/sfr/linux-next.git;a=history;f=drivers/net/xilinx_emaclite.c;h=7e05b40ae36b50b6eb66d9512ae3a49ba2d36a47;hb=a9a8cb1d6594037fbb23f1ce45964ec6a3b38215>
| raw
<http://git.kernel.org/?p=linux/kernel/git/sfr/linux-next.git;a=blob_plain;f=drivers/net/xilinx_emaclite.c;hb=a9a8cb1d6594037fbb23f1ce45964ec6a3b38215>
should be 644.
Please fix it in your repo.
Thanks,
Michal
> From: John Linn <john.linn@xilinx.com>
> Date: Thu, 20 Aug 2009 03:49:51 -0600
>
>
>> This patch adds support for the Xilinx Ethernet Lite device. The
>> soft logic core from Xilinx is typically used on Virtex and Spartan
>> designs attached to either a PowerPC or a Microblaze processor.
>>
>> Signed-off-by: Sadanand M <sadanan@xilinx.com>
>> Signed-off-by: John Linn <john.linn@xilinx.com>
>>
>
> Applied, thanks.
>
--
Michal Simek, Ing. (M.Eng)
PetaLogix - Linux Solutions for a Reconfigurable World
w: www.petalogix.com p: +61-7-30090663,+42-0-721842854 f: +61-7-30090663
^ permalink raw reply
* remapping 4MB of kernel space with remap_pfn_range() and nopage()
From: john.p.price @ 2009-08-31 13:28 UTC (permalink / raw)
To: linuxppc-dev
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I'm using linux kernel 2.6.29.1 I've been using the mmap system call to
map 4MB of contiguous kernel memory (RAM), obtained by get_free_pages
with order == 10, to user space. One implementation I have uses
remap_pfn_range(), its seems to work ok, I do have other issues I just
want to make sure its reasonable to use the reamp_pfn_range call for
what I am doing.
Now in LDD3 it says not to use the remap_pfn_range() call because it
only gives access to reserved pages and physical addresses above the top
of physical memory. LDD3 makes reference to the using the nopage and
notes about maintaining proper reference counts with clusters of pages.
The material in the book on this issue seems dated.
Is there still a limitation with using remap_pfn_range() remap kernel
ram to user space?
So in a test driver I made using the "fault" (previously called nopage)
method for that purpose.
here's a snipet of the fault callback;
offset = vmf->pgoff << PAGE_SHIFT;
if( offset > dev->dma_buff_size)
{
printk("ds3b3_vm_fault: SIGBUS - my_offset: %#x vmf_pgoff: %#x
page_shift: %i \n",
offset, vmf->pgoff, PAGE_SHIFT);
return VM_FAULT_SIGBUS;
}
addr = (char *)vma->vm_start;
addr += offset;
page = virt_to_page( addr );
get_page(page);
vmf->page = page;
When the application loads the module the following is printed on the
console;
My kprintfs from the fault handler:
<4>ds3b3_vm_fault: entered - vma->vm_start: 0x48000000 vma->vm_end
0x483fd000
<4>ds3b3_vm_fault: entered - vma->vm_flags: 0x820fb vma->vm_pgoff 0x0
<4>ds3b3_vm_fault: entered - vmf->flags: 0x1 vmf->pgoff 0x0
vmf->virtual_address: 0x48000000
<4>ds3b3_vm_fault: SUCCESS - vmf->page: 0xc13d1000
Kernel output to the console:
<1>BUG: Bad page map in process dcb pte:880004d2 pmd:0c5ec400
<1>addr:48000000 vm_flags:000820fb anon_vma null) mapping:ce4927d0
index:0
<1>vma->vm_ops->fault: ds3b3_vm_fault+0x0/0xf8 [ds3b3]
<1>vma->vm_file->f_op->mmap: ds3b3_nopage_mmap+0x0/0x4c [ds3b3]
<4>Call Trace:
<4>[cd659d80] [c0006bc0] show_stack+0x44/0x16c (unreliable)
<4>[cd659dc0] [c00627c8] print_bad_pte+0x140/0x1cc
<4>[cd659df0] [c00628d0] vm_normal_page+0x7c/0xb4
<4>[cd659e00] [c00630b4] follow_page+0xf4/0x1f0
<4>[cd659e20] [c00645e4] __get_user_pages+0x130/0x3ec
<4>[cd659e80] [c0064b28] make_pages_present+0x8c/0xc4
<4>[cd659e90] [c0066780] mlock_vma_pages_range+0x74/0x9c
<4>[cd659eb0] [c0068efc] mmap_region+0x1dc/0x3c8
<4>[cd659f10] [c00037b8] sys_mmap+0x78/0x100
<4>[cd659f40] [c000e558] ret_from_syscall+0x0/0x3c
I do not understand why the first page of the buffer is determined to be
a bad page? Do I need to perform any initialization to the buffer pages
after allocation and prior to the application calling mmap or do I need
to set a specific vm flag(s)?
Any comments or advice would be appreciated.
thanks
John Price <john.p.price@l-3com.com
<blocked::mailto:john.p.price@l-3com.com> >
781-970-1743
L-3 Communications
Security & Detection Systems Division,
10E Commerce Way, Woburn, MA 01801
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^ permalink raw reply
* Please pull 'next' branch of 4xx tree
From: Josh Boyer @ 2009-08-31 16:24 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
Hi Ben,
Please pull the 'next' branch of the 4xx tree to get the following changes.
Thanks,
josh
The following changes since commit 77c0a700c1c292edafa11c1e52821ce4636f81b0:
Benjamin Herrenschmidt (1):
powerpc: Properly start decrementer on BookE secondary CPUs
are available in the git repository at:
ssh://master.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git next
Solomon Peachy (1):
powerpc/40x: Add support for the ESTeem 195E (PPC405EP) SBC
Stefan Roese (2):
powerpc/44x: Update Arches dts
powerpc/44x: Update Arches defconfig
Tiejun Chen (2):
powerpc/405ex: provide necessary fixup function to support cuImage
powerpc/405ex: support cuImage via included dtb
fkan@amcc.com (1):
powerpc/44x: Add Eiger AMCC (AppliedMicro) PPC460SX evaluation board support.
arch/powerpc/boot/4xx.c | 142 ++++
arch/powerpc/boot/4xx.h | 1 +
arch/powerpc/boot/Makefile | 6 +-
arch/powerpc/boot/cuboot-hotfoot.c | 142 ++++
arch/powerpc/boot/cuboot-kilauea.c | 49 ++
arch/powerpc/boot/dcr.h | 4 +-
arch/powerpc/boot/dts/arches.dts | 50 ++
arch/powerpc/boot/dts/eiger.dts | 421 ++++++++++
arch/powerpc/boot/dts/hotfoot.dts | 294 +++++++
arch/powerpc/boot/ppcboot-hotfoot.h | 133 +++
arch/powerpc/configs/44x/arches_defconfig | 382 ++++++++--
arch/powerpc/configs/44x/eiger_defconfig | 1252 ++++++++++++++++++++++++++++
arch/powerpc/platforms/40x/Kconfig | 10 +
arch/powerpc/platforms/40x/ppc40x_simple.c | 3 +-
arch/powerpc/platforms/44x/Kconfig | 12 +
arch/powerpc/platforms/44x/ppc44x_simple.c | 1 +
16 files changed, 2846 insertions(+), 56 deletions(-)
create mode 100644 arch/powerpc/boot/cuboot-hotfoot.c
create mode 100644 arch/powerpc/boot/cuboot-kilauea.c
create mode 100644 arch/powerpc/boot/dts/eiger.dts
create mode 100644 arch/powerpc/boot/dts/hotfoot.dts
create mode 100644 arch/powerpc/boot/ppcboot-hotfoot.h
create mode 100644 arch/powerpc/configs/44x/eiger_defconfig
^ permalink raw reply
* Re: [RFC] Clock binding
From: Stuart Yoder @ 2009-08-31 17:49 UTC (permalink / raw)
To: Grant Likely; +Cc: devicetree-discuss, linuxppc-dev list
In-Reply-To: <fa686aa40908281309g6eedcdb4neb6a96104807a3f1@mail.gmail.com>
> How about right here: =A0http://fdt.secretlab.ca/
>
> I've only just created the site. =A0I'll fill in some documentation and
> structure in the next few days. =A0Feel free to create an account and
> start adding stuff.
>
> We'll need to talk about how best to manage bindings and have some
> form of review/agreement before a binding is marked as "stable". =A0And
> the site URL could change as well. =A0But in the meantime we've got a
> sandbox to start playing in.
Unless there are better suggestions, your site is fine with me.
One other thing-- we need to clarify how the content of the wiki
is licensed.
I assume (and hope) that the intent is for the content to be freely
usable in the most flexible way. But, this has to be explicit.
An issue we ran into with the ePAPR was that on the IEEE
1275 working group site (http://playground.sun.com/1275/home.html)
that there were bindings that we wanted to include in the ePAPR,
but the stuff on 1275 site was not copyrighted and no license
was specified. This meant that we were in a legally murky
situation if we cut and pasted anything from one of those
document.
My suggestion is to specify that all content of this wiki are
released to the public domain. How to do this is a bit tricky
but Creative Commons has a license called CC0 that does
this by waving your copyright rights.
Your wiki currently has the following statement above the commit
message:
Please note that all contributions to FDTWiki may be edited, altered,
or removed by other contributors. If you do not want your writing to
be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it
from a public domain or similar free resource (see
FDTWiki:Copyrights for details). Do not submit copyrighted work
without permission!
I would suggest appending the following statement to the above
text:
You irrevocably agree to release your contribution to the public
domain. To the extent possible under law, you waive all copyright or
neighboring rights to your contribution. See [CC0|link-to-CC0].
The above language comes from generated text of the CC0 tool from
Creative Commons.
Stuart
^ permalink raw reply
* Re: [PATCH 1/5] powerpc/qe: Make qe_reset() code path safe for repeated invocation
From: Anton Vorontsov @ 2009-08-31 18:47 UTC (permalink / raw)
To: Tabi Timur-B04825; +Cc: Wood Scott-B07421, linuxppc-dev
In-Reply-To: <5610599F537DD74A8D1F5CC946A7507301DCCC8A@az33exm25.fsl.freescale.net>
On Sun, Aug 30, 2009 at 05:36:28PM -0700, Tabi Timur-B04825 wrote:
> Is the need to reinitialize the QE after resume something that
> is unique to the 8569, or would it apply to the 8360 and 8323 also?
8569 is unique in this regard, though I'm not sure if that's by design
or because of some errata.
Just as 8569 is unique that it needs QE microcode loaded externally
since the CPU doesn't have any ROM where the microcode can be stored.
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* Re: [PATCH 2/5] powerpc/85xx/86xx: Add suspend/resume support
From: Anton Vorontsov @ 2009-08-31 18:47 UTC (permalink / raw)
To: Tabi Timur-B04825; +Cc: Wood Scott-B07421, linuxppc-dev
In-Reply-To: <5610599F537DD74A8D1F5CC946A7507301DCCC8B@az33exm25.fsl.freescale.net>
On Sun, Aug 30, 2009 at 05:38:05PM -0700, Tabi Timur-B04825 wrote:
>
> What about the 8610?
Yes, it is supported. The bindings decribe that 8641d should
be used as a base match, so 8610-pmc is 8641d-compatible.
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
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