* [PATCH 3/3] ucc_geth: Fix hangs after switching from full to half duplex
From: Anton Vorontsov @ 2009-09-10 2:01 UTC (permalink / raw)
To: David Miller; +Cc: netdev, linuxppc-dev, Andy Fleming, Timur Tabi
MPC8360 QE UCC ethernet controllers hang when changing link duplex
under a load (a bit of NFS activity is enough).
PHY: mdio@e0102120:00 - Link is Up - 1000/Full
sh-3.00# ethtool -s eth0 speed 100 duplex half autoneg off
PHY: mdio@e0102120:00 - Link is Down
PHY: mdio@e0102120:00 - Link is Up - 100/Half
NETDEV WATCHDOG: eth0 (ucc_geth): transmit queue 0 timed out
------------[ cut here ]------------
Badness at c01fcbd0 [verbose debug info unavailable]
NIP: c01fcbd0 LR: c01fcbd0 CTR: c0194e44
...
The cure is to disable the controller before changing speed/duplex
and enable it afterwards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
drivers/net/ucc_geth.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 2a2c973..9ad9015 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -1631,9 +1631,13 @@ static void adjust_link(struct net_device *dev)
ugeth->oldspeed = phydev->speed;
}
+ ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
+
out_be32(&ug_regs->maccfg2, tempval);
out_be32(&uf_regs->upsmr, upsmr);
+ ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
+
if (!ugeth->oldlink) {
new_state = 1;
ugeth->oldlink = 1;
--
1.6.3.3
^ permalink raw reply related
* Re: [FTRACE] Enabling function_graph causes OOPS
From: Sachin Sant @ 2009-09-10 5:32 UTC (permalink / raw)
To: rostedt; +Cc: linuxppc-dev
In-Reply-To: <1252525364.27001.32.camel@gandalf.stny.rr.com>
Steven Rostedt wrote:
> Ah, seems the bug happens to be in the module handling. Does the call
> back always have .mod_return_to_handler?
>
Yes. Every time it ends up in .mod_return_to_handler
Thanks
-Sachin
> This doesn't surprise me any. The module code is a bit harry, and
> function graph does some crazy crap with it.
>
> -- Steve
>
--
---------------------------------
Sachin Sant
IBM Linux Technology Center
India Systems and Technology Labs
Bangalore, India
---------------------------------
^ permalink raw reply
* Re: [Uclinux-dist-devel] Removing deprecated drivers from drivers/i2c/chips
From: Wolfram Sang @ 2009-09-10 6:26 UTC (permalink / raw)
To: Mike Frysinger
Cc: linuxppc-dev, linux-mips, linux-i2c, linux-arm-kernel,
uclinux-dist-devel
In-Reply-To: <8bd0f97a0909091654h290180e5ob79178583aca143f@mail.gmail.com>
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> the Blackfin defconfigs refer to an input driver for the PCF8574, not
> the I2C client driver
Yup, I am aware of that. With the exception of:
blackfin/configs/PNAV-10_defconfig:773:CONFIG_SENSORS_PCF8574=m
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* [PATCH] powerpc: perf_counters: Reduce stack usage of power_check_constraints
From: Paul Mackerras @ 2009-09-10 6:28 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
Michael Ellerman reported stack-frame size warnings being produced
for power_check_constraints(), which uses an 8*8 array of u64 and
two 8*8 arrays of unsigned long, which are currently allocated on the
stack, along with some other smaller variables. These arrays come
to 1.5kB on 64-bit or 1kB on 32-bit, which is a bit too much for the
stack.
This fixes the problem by putting these arrays in the existing
per-cpu cpu_hw_counters struct. This is OK because two of the call
sites have interrupts disabled already; for the third call site we
use get_cpu_var, which disables preemption, so we know we won't
get a context switch while we're in power_check_constraints().
Note that power_check_constraints() can be called during context
switch but is not called from interrupts.
Reported-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
---
arch/powerpc/kernel/perf_counter.c | 55 +++++++++++++++++++++---------------
1 files changed, 32 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
index ccd6b21..7ceefaf 100644
--- a/arch/powerpc/kernel/perf_counter.c
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -32,6 +32,9 @@ struct cpu_hw_counters {
unsigned long mmcr[3];
struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];
u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
+ u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+ unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
+ unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
};
DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
@@ -239,13 +242,11 @@ static void write_pmc(int idx, unsigned long val)
* and see if any combination of alternative codes is feasible.
* The feasible set is returned in event[].
*/
-static int power_check_constraints(u64 event[], unsigned int cflags[],
+static int power_check_constraints(struct cpu_hw_counters *cpuhw,
+ u64 event[], unsigned int cflags[],
int n_ev)
{
unsigned long mask, value, nv;
- u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
- unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
- unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
int i, j;
@@ -260,21 +261,23 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
&& !ppmu->limited_pmc_event(event[i])) {
ppmu->get_alternatives(event[i], cflags[i],
- alternatives[i]);
- event[i] = alternatives[i][0];
+ cpuhw->alternatives[i]);
+ event[i] = cpuhw->alternatives[i][0];
}
- if (ppmu->get_constraint(event[i], &amasks[i][0],
- &avalues[i][0]))
+ if (ppmu->get_constraint(event[i], &cpuhw->amasks[i][0],
+ &cpuhw->avalues[i][0]))
return -1;
}
value = mask = 0;
for (i = 0; i < n_ev; ++i) {
- nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf);
+ nv = (value | cpuhw->avalues[i][0]) +
+ (value & cpuhw->avalues[i][0] & addf);
if ((((nv + tadd) ^ value) & mask) != 0 ||
- (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0)
+ (((nv + tadd) ^ cpuhw->avalues[i][0]) &
+ cpuhw->amasks[i][0]) != 0)
break;
value = nv;
- mask |= amasks[i][0];
+ mask |= cpuhw->amasks[i][0];
}
if (i == n_ev)
return 0; /* all OK */
@@ -285,10 +288,11 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
for (i = 0; i < n_ev; ++i) {
choice[i] = 0;
n_alt[i] = ppmu->get_alternatives(event[i], cflags[i],
- alternatives[i]);
+ cpuhw->alternatives[i]);
for (j = 1; j < n_alt[i]; ++j)
- ppmu->get_constraint(alternatives[i][j],
- &amasks[i][j], &avalues[i][j]);
+ ppmu->get_constraint(cpuhw->alternatives[i][j],
+ &cpuhw->amasks[i][j],
+ &cpuhw->avalues[i][j]);
}
/* enumerate all possibilities and see if any will work */
@@ -307,11 +311,11 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
* where k > j, will satisfy the constraints.
*/
while (++j < n_alt[i]) {
- nv = (value | avalues[i][j]) +
- (value & avalues[i][j] & addf);
+ nv = (value | cpuhw->avalues[i][j]) +
+ (value & cpuhw->avalues[i][j] & addf);
if ((((nv + tadd) ^ value) & mask) == 0 &&
- (((nv + tadd) ^ avalues[i][j])
- & amasks[i][j]) == 0)
+ (((nv + tadd) ^ cpuhw->avalues[i][j])
+ & cpuhw->amasks[i][j]) == 0)
break;
}
if (j >= n_alt[i]) {
@@ -333,7 +337,7 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
svalues[i] = value;
smasks[i] = mask;
value = nv;
- mask |= amasks[i][j];
+ mask |= cpuhw->amasks[i][j];
++i;
j = -1;
}
@@ -341,7 +345,7 @@ static int power_check_constraints(u64 event[], unsigned int cflags[],
/* OK, we have a feasible combination, tell the caller the solution */
for (i = 0; i < n_ev; ++i)
- event[i] = alternatives[i][choice[i]];
+ event[i] = cpuhw->alternatives[i][choice[i]];
return 0;
}
@@ -745,7 +749,7 @@ int hw_perf_group_sched_in(struct perf_counter *group_leader,
return -EAGAIN;
if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n))
return -EAGAIN;
- i = power_check_constraints(cpuhw->events, cpuhw->flags, n + n0);
+ i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n + n0);
if (i < 0)
return -EAGAIN;
cpuhw->n_counters = n0 + n;
@@ -800,7 +804,7 @@ static int power_pmu_enable(struct perf_counter *counter)
cpuhw->flags[n0] = counter->hw.counter_base;
if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1))
goto out;
- if (power_check_constraints(cpuhw->events, cpuhw->flags, n0 + 1))
+ if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
goto out;
counter->hw.config = cpuhw->events[n0];
@@ -1005,6 +1009,7 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
unsigned int cflags[MAX_HWCOUNTERS];
int n;
int err;
+ struct cpu_hw_counters *cpuhw;
if (!ppmu)
return ERR_PTR(-ENXIO);
@@ -1083,7 +1088,11 @@ const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
cflags[n] = flags;
if (check_excludes(ctrs, cflags, n, 1))
return ERR_PTR(-EINVAL);
- if (power_check_constraints(events, cflags, n + 1))
+
+ cpuhw = &get_cpu_var(cpu_hw_counters);
+ err = power_check_constraints(cpuhw, events, cflags, n + 1);
+ put_cpu_var(cpu_hw_counters);
+ if (err)
return ERR_PTR(-EINVAL);
counter->hw.config = events[n];
--
1.5.5.rc3.7.gba13
^ permalink raw reply related
* Re: [PATCH] powerpc: perf_counters: Reduce stack usage of power_check_constraints
From: Michael Ellerman @ 2009-09-10 7:03 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <19112.40097.974792.747829@drongo.ozlabs.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 937 bytes --]
On Thu, 2009-09-10 at 16:28 +1000, Paul Mackerras wrote:
> Michael Ellerman reported stack-frame size warnings being produced
> for power_check_constraints(), which uses an 8*8 array of u64 and
> two 8*8 arrays of unsigned long, which are currently allocated on the
> stack, along with some other smaller variables. These arrays come
> to 1.5kB on 64-bit or 1kB on 32-bit, which is a bit too much for the
> stack.
>
> This fixes the problem by putting these arrays in the existing
> per-cpu cpu_hw_counters struct. This is OK because two of the call
> sites have interrupts disabled already; for the third call site we
> use get_cpu_var, which disables preemption, so we know we won't
> get a context switch while we're in power_check_constraints().
> Note that power_check_constraints() can be called during context
> switch but is not called from interrupts.
Yep, it does indeed fix the build warning :D
cheers
[-- Attachment #2: This is a digitally signed message part --]
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^ permalink raw reply
* Re: [Uclinux-dist-devel] Removing deprecated drivers from drivers/i2c/chips
From: Mike Frysinger @ 2009-09-10 7:55 UTC (permalink / raw)
To: Wolfram Sang
Cc: linuxppc-dev, linux-mips, linux-i2c, linux-arm-kernel,
uclinux-dist-devel
In-Reply-To: <20090910062609.GA26454@pengutronix.de>
On Thu, Sep 10, 2009 at 02:26, Wolfram Sang wrote:
>> the Blackfin defconfigs refer to an input driver for the PCF8574, not
>> the I2C client driver
>
> Yup, I am aware of that. With the exception of:
>
> blackfin/configs/PNAV-10_defconfig:773:CONFIG_SENSORS_PCF8574=m
thanks for double checking. i'm not sure this board even has this
device. i'll review the hardware.
-mike
^ permalink raw reply
* [PATCH][v1] powerpc/85xx: Create dts for each core in CAMP mode for P2020RDB
From: Poonam Aggrwal @ 2009-09-10 8:57 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Poonam Aggrwal
This patch creates the dts files for each core and splits the devices between
the two cores for P2020RDB.
core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto, global-util, pci0
core1 has L2, dma2, eth0, pci1, msi.
MPIC is shared between two cores but each core will protect its
interrupts from other core by using "protected-sources" of mpic.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
---
- based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
- branch->next
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 365 +++++++++++++++++++++++++
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts | 186 +++++++++++++
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 10 +-
3 files changed, 560 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
new file mode 100644
index 0000000..ca072da
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -0,0 +1,365 @@
+/*
+ * P2020 RDB Core0 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
+ * eth1, eth2, sdhc, crypto, global-util, pci0.
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P2020";
+ compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ serial0 = &serial0;
+ pci0 = &pci0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P2020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p2020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p2020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p2020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+
+ fsl_m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,espi-flash";
+ reg = <0>;
+ linux,modalias = "fsl_m25p80";
+ modal = "s25sl128b";
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition@0 {
+ /* 512KB for u-boot Bootloader Image */
+ reg = <0x0 0x00080000>;
+ label = "SPI (RO) U-Boot Image";
+ read-only;
+ };
+
+ partition@80000 {
+ /* 512KB for DTB Image */
+ reg = <0x00080000 0x00080000>;
+ label = "SPI (RO) DTB Image";
+ read-only;
+ };
+
+ partition@100000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00100000 0x00400000>;
+ label = "SPI (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@500000 {
+ /* 4MB for Compressed RFS Image */
+ reg = <0x00500000 0x00400000>;
+ label = "SPI (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ partition@900000 {
+ /* 7MB for JFFS2 based RFS */
+ reg = <0x00900000 0x00700000>;
+ label = "SPI (RW) JFFS2 RFS";
+ };
+ };
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p2020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2,512K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ phy_type = "ulpi";
+ };
+
+ mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x24520 0x20>;
+
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x1>;
+ };
+ };
+
+ mdio@25520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x26520 0x20>;
+
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+
+ };
+
+ enet2: ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ sdhci@2e000 {
+ compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ protected-sources = <
+ 42 76 77 78 79 /* serial1 , dma2 */
+ 29 30 34 26 /* enet0, pci1 */
+ 0xe0 0xe1 0xe2 0xe3 /* msi */
+ 0xe4 0xe5 0xe6 0xe7
+ >;
+ };
+
+ global-utilities@e0000 {
+ compatible = "fsl,p2020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
new file mode 100644
index 0000000..c3c9da6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -0,0 +1,186 @@
+/*
+ * P2020 RDB Core1 Device Tree Source in CAMP mode.
+ *
+ * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
+ * can be shared, all the other devices must be assigned to one core only.
+ * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
+ *
+ * Please note to add "-b 1" for core1's dts compiling.
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P2020";
+ compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ serial0 = &serial0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P2020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p2020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ serial0: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p2020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2,512K
+ interrupt-parent = <&mpic>;
+ };
+
+
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ fixed-link = <1 1 1000 0 0>;
+ phy-connection-type = "rgmii-id";
+
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ protected-sources = <
+ 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
+ 16 20 21 22 23 28 /* L2, dma1, USB */
+ 03 35 36 40 31 32 33 /* mdio, enet1, enet2 */
+ 72 45 58 25 /* sdhci, crypto , pci */
+ >;
+ };
+
+ msi@41600 {
+ compatible = "fsl,p2020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 495bd8b..088f30b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -44,6 +44,7 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
struct resource r;
struct device_node *np;
+ unsigned long root = of_get_flat_dt_root();
np = of_find_node_by_type(NULL, "open-pic");
if (np == NULL) {
@@ -57,11 +58,18 @@ void __init mpc85xx_rdb_pic_init(void)
return;
}
- mpic = mpic_alloc(np, r.start,
+ if (of_flat_dt_is_compatible(root, "fsl,85XXRDB-CAMP")) {
+ mpic = mpic_alloc(np, r.start,
+ MPIC_PRIMARY |
+ MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
+ 0, 256, " OpenPIC ");
+ } else {
+ mpic = mpic_alloc(np, r.start,
MPIC_PRIMARY | MPIC_WANTS_RESET |
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
MPIC_SINGLE_DEST_CPU,
0, 256, " OpenPIC ");
+ }
BUG_ON(mpic == NULL);
of_node_put(np);
--
1.5.6.5
^ permalink raw reply related
* Re: Question about e300 core decrementer interrupt
From: Kenneth Johansson @ 2009-09-10 9:09 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Li Tao-B22598
In-Reply-To: <20090909184343.GC8215@b07421-ec1.am.freescale.net>
On Wed, 2009-09-09 at 13:43 -0500, Scott Wood wrote:
> On Wed, Sep 09, 2009 at 01:16:07PM +0200, Kenneth Johansson wrote:
> > On Tue, 2009-09-08 at 13:48 +0800, Li Tao-B22598 wrote:
> > > Dear all,
> > >
> > > I have a problem in MPC5121 sleep mode. As you know MPC5121 use e300c4
> > > core. When I make the e300c4 core into sleep mode, it will return to
> > > full power mode when the“decrementer interrupt” occurred.
> > >
> > > But in the e300 core reference manual said that the “decrementer
> > > interrupt”have no effect when e300 core in sleep mode, because the
> > > time
> > > base and decrementer are disabled while the core is in sleep mode.
> > > Can anybody explain about this procedure ?
>
> I'm not specifically familiar with MPC5121, but I'll answer from the
> perspective of MPC83xx which has a similar core:
>
> The decrementer stops ticking when the core goes to sleep. However, if a
> decrementer was already pending (but masked with MSR[EE]) before you
> enter sleep mode, it will cause a wakeup.
>
> To avoid this, the decrementer is set to a very large value prior to and
> after disabling interrupts. See generic_suspend_disable_irqs() in
> arch/powerpc/kernel/time.c. Is this not happening for you? Which kernel
> version are you using, and what mechanism are you using to go to sleep?
>
> > I'm a bit irritated that it's not as the "solution" can mean hardware
> > changes an thus it's potentially expensive.
>
> What sort of hardware changes?
I don't want to spread missinformation but this procedure has helped on
the ads5121 rev3 and two custom boards.
the gpio 28,29,30 needs to be low and gpio31 needs to be hi. regardless
of what is used as wakeup source when the device enters deep sleep
otherwise you end up in some sort of meta state where you might not wake
up on anything and you have this 42 second auto wakeup from the
decrementer.
Other weired states has also been observed. the PMC module is a bit
tempremental in this chip.
^ permalink raw reply
* Re: [PATCH][v1] powerpc/85xx: Create dts for each core in CAMP mode for P2020RDB
From: Gabriel Paubert @ 2009-09-10 9:33 UTC (permalink / raw)
To: Poonam Aggrwal; +Cc: linuxppc-dev
In-Reply-To: <1252573031-4157-1-git-send-email-poonam.aggrwal@freescale.com>
On Thu, Sep 10, 2009 at 02:27:11PM +0530, Poonam Aggrwal wrote:
> This patch creates the dts files for each core and splits the devices between
> the two cores for P2020RDB.
>
> core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto, global-util, pci0
> core1 has L2, dma2, eth0, pci1, msi.
Surely you mean eth1 and eth2 for core0, no?
At least it's what I gather from the code.
Also both cores have a node called serial0, at different addresses but with the
same interrupt!
But in the mpic comment line there is "serial1", and interrupt 42 is the only
number which appears in both lists of mpic protected interrupts.
Gabriel
> ---
> - based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> - branch->next
> arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 365 +++++++++++++++++++++++++
> arch/powerpc/boot/dts/p2020rdb_camp_core1.dts | 186 +++++++++++++
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 10 +-
> 3 files changed, 560 insertions(+), 1 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
> create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
>
> diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
> new file mode 100644
> index 0000000..ca072da
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
> @@ -0,0 +1,365 @@
> +/*
> + * P2020 RDB Core0 Device Tree Source in CAMP mode.
> + *
> + * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
> + * can be shared, all the other devices must be assigned to one core only.
> + * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
> + * eth1, eth2, sdhc, crypto, global-util, pci0.
> + *
> + * Copyright 2009 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/ {
> + model = "fsl,P2020";
> + compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
> + serial0 = &serial0;
> + pci0 = &pci0;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,P2020@0 {
> + device_type = "cpu";
> + reg = <0x0>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + };
> +
> + soc@ffe00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + compatible = "fsl,p2020-immr", "simple-bus";
> + ranges = <0x0 0x0 0xffe00000 0x100000>;
> + bus-frequency = <0>; // Filled out by uboot.
> +
> + ecm-law@0 {
> + compatible = "fsl,ecm-law";
> + reg = <0x0 0x1000>;
> + fsl,num-laws = <12>;
> + };
> +
> + ecm@1000 {
> + compatible = "fsl,p2020-ecm", "fsl,ecm";
> + reg = <0x1000 0x1000>;
> + interrupts = <17 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + memory-controller@2000 {
> + compatible = "fsl,p2020-memory-controller";
> + reg = <0x2000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <18 2>;
> + };
> +
> + i2c@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <0>;
> + compatible = "fsl-i2c";
> + reg = <0x3000 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + rtc@68 {
> + compatible = "dallas,ds1339";
> + reg = <0x68>;
> + };
> + };
> +
> + i2c@3100 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <1>;
> + compatible = "fsl-i2c";
> + reg = <0x3100 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + serial0: serial@4500 {
> + cell-index = <0>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4500 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + spi@7000 {
> + cell-index = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,espi";
> + reg = <0x7000 0x1000>;
> + interrupts = <59 0x2>;
> + interrupt-parent = <&mpic>;
> + mode = "cpu";
> +
> + fsl_m25p80@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,espi-flash";
> + reg = <0>;
> + linux,modalias = "fsl_m25p80";
> + modal = "s25sl128b";
> + spi-max-frequency = <50000000>;
> + mode = <0>;
> +
> + partition@0 {
> + /* 512KB for u-boot Bootloader Image */
> + reg = <0x0 0x00080000>;
> + label = "SPI (RO) U-Boot Image";
> + read-only;
> + };
> +
> + partition@80000 {
> + /* 512KB for DTB Image */
> + reg = <0x00080000 0x00080000>;
> + label = "SPI (RO) DTB Image";
> + read-only;
> + };
> +
> + partition@100000 {
> + /* 4MB for Linux Kernel Image */
> + reg = <0x00100000 0x00400000>;
> + label = "SPI (RO) Linux Kernel Image";
> + read-only;
> + };
> +
> + partition@500000 {
> + /* 4MB for Compressed RFS Image */
> + reg = <0x00500000 0x00400000>;
> + label = "SPI (RO) Compressed RFS Image";
> + read-only;
> + };
> +
> + partition@900000 {
> + /* 7MB for JFFS2 based RFS */
> + reg = <0x00900000 0x00700000>;
> + label = "SPI (RW) JFFS2 RFS";
> + };
> + };
> + };
> +
> + gpio: gpio-controller@f000 {
> + #gpio-cells = <2>;
> + compatible = "fsl,mpc8572-gpio";
> + reg = <0xf000 0x100>;
> + interrupts = <47 0x2>;
> + interrupt-parent = <&mpic>;
> + gpio-controller;
> + };
> +
> + L2: l2-cache-controller@20000 {
> + compatible = "fsl,p2020-l2-cache-controller";
> + reg = <0x20000 0x1000>;
> + cache-line-size = <32>; // 32 bytes
> + cache-size = <0x80000>; // L2,512K
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + dma@21300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0x21300 0x4>;
> + ranges = <0x0 0x21100 0x200>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <20 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <21 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <22 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <23 2>;
> + };
> + };
> +
> + usb@22000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x22000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <28 0x2>;
> + phy_type = "ulpi";
> + };
> +
> + mdio@24520 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,gianfar-mdio";
> + reg = <0x24520 0x20>;
> +
> + phy0: ethernet-phy@0 {
> + interrupt-parent = <&mpic>;
> + interrupts = <3 1>;
> + reg = <0x0>;
> + };
> + phy1: ethernet-phy@1 {
> + interrupt-parent = <&mpic>;
> + interrupts = <3 1>;
> + reg = <0x1>;
> + };
> + };
> +
> + mdio@25520 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,gianfar-tbi";
> + reg = <0x26520 0x20>;
> +
> + tbi0: tbi-phy@11 {
> + reg = <0x11>;
> + device_type = "tbi-phy";
> + };
> + };
> +
> + enet1: ethernet@25000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x25000 0x1000>;
> + ranges = <0x0 0x25000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <35 2 36 2 40 2>;
> + interrupt-parent = <&mpic>;
> + tbi-handle = <&tbi0>;
> + phy-handle = <&phy0>;
> + phy-connection-type = "sgmii";
> +
> + };
> +
> + enet2: ethernet@26000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <2>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x26000 0x1000>;
> + ranges = <0x0 0x26000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <31 2 32 2 33 2>;
> + interrupt-parent = <&mpic>;
> + phy-handle = <&phy1>;
> + phy-connection-type = "rgmii-id";
> + };
> +
> + sdhci@2e000 {
> + compatible = "fsl,p2020-esdhc", "fsl,esdhc";
> + reg = <0x2e000 0x1000>;
> + interrupts = <72 0x2>;
> + interrupt-parent = <&mpic>;
> + /* Filled in by U-Boot */
> + clock-frequency = <0>;
> + };
> +
> + crypto@30000 {
> + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> + reg = <0x30000 0x10000>;
> + interrupts = <45 2 58 2>;
> + interrupt-parent = <&mpic>;
> + fsl,num-channels = <4>;
> + fsl,channel-fifo-len = <24>;
> + fsl,exec-units-mask = <0xbfe>;
> + fsl,descriptor-types-mask = <0x3ab0ebf>;
> + };
> +
> + mpic: pic@40000 {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + reg = <0x40000 0x40000>;
> + compatible = "chrp,open-pic";
> + device_type = "open-pic";
> + protected-sources = <
> + 42 76 77 78 79 /* serial1 , dma2 */
> + 29 30 34 26 /* enet0, pci1 */
> + 0xe0 0xe1 0xe2 0xe3 /* msi */
> + 0xe4 0xe5 0xe6 0xe7
> + >;
> + };
> +
> + global-utilities@e0000 {
> + compatible = "fsl,p2020-guts";
> + reg = <0xe0000 0x1000>;
> + fsl,has-rstcr;
> + };
> + };
> +
> + pci0: pcie@ffe09000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe09000 0 0x1000>;
> + bus-range = <0 255>;
> + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
> + 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <25 2>;
> + pcie@0 {
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + device_type = "pci";
> + ranges = <0x2000000 0x0 0xa0000000
> + 0x2000000 0x0 0xa0000000
> + 0x0 0x20000000
> +
> + 0x1000000 0x0 0x0
> + 0x1000000 0x0 0x0
> + 0x0 0x100000>;
> + };
> + };
> +};
> diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
> new file mode 100644
> index 0000000..c3c9da6
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
> @@ -0,0 +1,186 @@
> +/*
> + * P2020 RDB Core1 Device Tree Source in CAMP mode.
> + *
> + * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
> + * can be shared, all the other devices must be assigned to one core only.
> + * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
> + *
> + * Please note to add "-b 1" for core1's dts compiling.
> + *
> + * Copyright 2009 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/ {
> + model = "fsl,P2020";
> + compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + ethernet0 = &enet0;
> + serial0 = &serial0;
> + pci1 = &pci1;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,P2020@1 {
> + device_type = "cpu";
> + reg = <0x1>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + };
> +
> + soc@ffe00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + compatible = "fsl,p2020-immr", "simple-bus";
> + ranges = <0x0 0x0 0xffe00000 0x100000>;
> + bus-frequency = <0>; // Filled out by uboot.
> +
> + serial0: serial@4600 {
> + cell-index = <1>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4600 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + dma@c300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0xc300 0x4>;
> + ranges = <0x0 0xc100 0x200>;
> + cell-index = <1>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <76 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <77 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <78 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <79 2>;
> + };
> + };
> +
> + L2: l2-cache-controller@20000 {
> + compatible = "fsl,p2020-l2-cache-controller";
> + reg = <0x20000 0x1000>;
> + cache-line-size = <32>; // 32 bytes
> + cache-size = <0x80000>; // L2,512K
> + interrupt-parent = <&mpic>;
> + };
> +
> +
> + enet0: ethernet@24000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <0>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x24000 0x1000>;
> + ranges = <0x0 0x24000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <29 2 30 2 34 2>;
> + interrupt-parent = <&mpic>;
> + fixed-link = <1 1 1000 0 0>;
> + phy-connection-type = "rgmii-id";
> +
> + };
> +
> + mpic: pic@40000 {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + reg = <0x40000 0x40000>;
> + compatible = "chrp,open-pic";
> + device_type = "open-pic";
> + protected-sources = <
> + 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
> + 16 20 21 22 23 28 /* L2, dma1, USB */
> + 03 35 36 40 31 32 33 /* mdio, enet1, enet2 */
> + 72 45 58 25 /* sdhci, crypto , pci */
> + >;
> + };
> +
> + msi@41600 {
> + compatible = "fsl,p2020-msi", "fsl,mpic-msi";
> + reg = <0x41600 0x80>;
> + msi-available-ranges = <0 0x100>;
> + interrupts = <
> + 0xe0 0
> + 0xe1 0
> + 0xe2 0
> + 0xe3 0
> + 0xe4 0
> + 0xe5 0
> + 0xe6 0
> + 0xe7 0>;
> + interrupt-parent = <&mpic>;
> + };
> + };
> +
> + pci1: pcie@ffe0a000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe0a000 0 0x1000>;
> + bus-range = <0 255>;
> + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
> + 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <26 2>;
> + pcie@0 {
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + device_type = "pci";
> + ranges = <0x2000000 0x0 0xc0000000
> + 0x2000000 0x0 0xc0000000
> + 0x0 0x20000000
> +
> + 0x1000000 0x0 0x0
> + 0x1000000 0x0 0x0
> + 0x0 0x100000>;
> + };
> + };
> +};
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> index 495bd8b..088f30b 100644
> --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> @@ -44,6 +44,7 @@ void __init mpc85xx_rdb_pic_init(void)
> struct mpic *mpic;
> struct resource r;
> struct device_node *np;
> + unsigned long root = of_get_flat_dt_root();
>
> np = of_find_node_by_type(NULL, "open-pic");
> if (np == NULL) {
> @@ -57,11 +58,18 @@ void __init mpc85xx_rdb_pic_init(void)
> return;
> }
>
> - mpic = mpic_alloc(np, r.start,
> + if (of_flat_dt_is_compatible(root, "fsl,85XXRDB-CAMP")) {
> + mpic = mpic_alloc(np, r.start,
> + MPIC_PRIMARY |
> + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
> + 0, 256, " OpenPIC ");
> + } else {
> + mpic = mpic_alloc(np, r.start,
> MPIC_PRIMARY | MPIC_WANTS_RESET |
> MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
> MPIC_SINGLE_DEST_CPU,
> 0, 256, " OpenPIC ");
> + }
>
> BUG_ON(mpic == NULL);
> of_node_put(np);
> --
> 1.5.6.5
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 2/4] i2c/chips: Remove deprecated pcf8575-driver
From: Bart Van Assche @ 2009-09-10 10:52 UTC (permalink / raw)
To: Wolfram Sang
Cc: linux-mips, linuxppc-dev, linux-i2c, Jean Delvare,
uclinux-dist-devel, linux-arm-kernel
In-Reply-To: <1252531371-14866-3-git-send-email-w.sang@pengutronix.de>
On Wed, Sep 9, 2009 at 11:22 PM, Wolfram Sang <w.sang@pengutronix.de> wrote=
:
>
> The pcf8575-driver in drivers/i2c/chips which just exports its register t=
o
> sysfs is superseeded by drivers/gpio/pcf857x.c which properly uses the gp=
iolib.
> As this driver has been deprecated for more than a year, finally remove i=
t.
>
> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
> Cc: Bart Van Assche <bart.vanassche@gmail.com>
> Cc: Jean Delvare <khali@linux-fr.org>
> ---
> =A0Documentation/i2c/chips/pcf8575 | =A0 69 --------------
> =A0drivers/i2c/chips/Kconfig =A0 =A0 =A0 | =A0 18 ----
> =A0drivers/i2c/chips/Makefile =A0 =A0 =A0| =A0 =A01 -
> =A0drivers/i2c/chips/pcf8575.c =A0 =A0 | =A0198 -------------------------=
--------------
> =A04 files changed, 0 insertions(+), 286 deletions(-)
> =A0delete mode 100644 Documentation/i2c/chips/pcf8575
> =A0delete mode 100644 drivers/i2c/chips/pcf8575.c
This patch removes the documentation file
Documentation/i2c/chips/pcf8575 while there is no documentation under
Documentation/ for the drivers/gpio/pcf857x.c driver. Shouldn't proper
documentation for the pcf857x driver be added to the kernel tree
before the pcf8575 driver is removed ?
Bart.
^ permalink raw reply
* Re: Removing deprecated drivers from drivers/i2c/chips
From: Jean Delvare @ 2009-09-10 10:49 UTC (permalink / raw)
To: Wolfram Sang
Cc: linuxppc-dev, uclinux-dist-devel, linux-i2c, linux-arm-kernel,
linux-mips
In-Reply-To: <1252531371-14866-1-git-send-email-w.sang@pengutronix.de>
Hi Wolfram,
On Wed, 9 Sep 2009 23:22:47 +0200, Wolfram Sang wrote:
> continuing the quest to clean up and ultimately remove the drivers/i2c/chips
> directory, this patch series removes three drivers for GPIO-expanders which are
> obsoleted and marked as deprecated for more than a year. The newer (and better)
> drivers can be found in drivers/gpio.
>
> As it is ensured that the newer drivers cover the same i2c_device_ids, all
> platform_devices will still match. Some defconfig updates may be necessary
> though, but according to [1] this is left to the arch|platform-maintainers
> (also as most defconfigs are quite outdated). For that reason, I put the
> relevant arch-mailing-lists to Cc. Comments are welcome.
Looks very good, I'll apply the 3 patches removing the legacy drivers.
Not sure about the patch to drivers/gpio/pcf857x.c, as there is no gpio
tree and no maintainer either AFAIK, I guess I shall pick it too?
Thanks,
--
Jean Delvare
^ permalink raw reply
* Re: [PATCH 2/4] i2c/chips: Remove deprecated pcf8575-driver
From: Wolfram Sang @ 2009-09-10 11:04 UTC (permalink / raw)
To: Bart Van Assche
Cc: linux-mips, linuxppc-dev, linux-i2c, Jean Delvare,
uclinux-dist-devel, linux-arm-kernel
In-Reply-To: <e2e108260909100352l2a30438fj9f0297c1974c0192@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1005 bytes --]
> This patch removes the documentation file
> Documentation/i2c/chips/pcf8575 while there is no documentation under
> Documentation/ for the drivers/gpio/pcf857x.c driver. Shouldn't proper
> documentation for the pcf857x driver be added to the kernel tree
> before the pcf8575 driver is removed ?
I considered moving the documentation, but realized:
1st part is URLs for datasheets. Well, URLs easily grow outdated and those
datasheets are easily to find using your favourite search engine.
2nd part is a short description of the chips which is IMHO sufficently covered
in drivers/gpio/Kconfig.
3rd part (Detection) and 4th part (sysfs-interface) are obsolete for the new
drivers. The gpiolib interface again is covered in Documentation/gpio.txt
So I concluded to simply drop the documentation.
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: Removing deprecated drivers from drivers/i2c/chips
From: Wolfram Sang @ 2009-09-10 11:07 UTC (permalink / raw)
To: Jean Delvare
Cc: linuxppc-dev, uclinux-dist-devel, linux-i2c, linux-arm-kernel,
linux-mips
In-Reply-To: <20090910124937.7b3df062@hyperion.delvare>
[-- Attachment #1: Type: text/plain, Size: 396 bytes --]
> Not sure about the patch to drivers/gpio/pcf857x.c, as there is no gpio
> tree and no maintainer either AFAIK, I guess I shall pick it too?
I'd say so. An Ack from David Brownell would be nice, though.
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: Question about e300 core decrementer interrupt
From: Li Tao @ 2009-09-10 11:53 UTC (permalink / raw)
To: Kenneth Johansson; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <1252573794.10293.13.camel@localhost>
Hi Johansson,
Thanks for your response
=E5=9C=A8 2009-09-10=E5=9B=9B=E7=9A=84 11:09 +0200=EF=BC=8CKenneth Johansso=
n=E5=86=99=E9=81=93=EF=BC=9A
> On Wed, 2009-09-09 at 13:43 -0500, Scott Wood wrote:
> > On Wed, Sep 09, 2009 at 01:16:07PM +0200, Kenneth Johansson wrote:
> > > On Tue, 2009-09-08 at 13:48 +0800, Li Tao-B22598 wrote:
> > > > Dear all,
> > > >=20
> > > > I have a problem in MPC5121 sleep mode. As you know MPC5121 use e30=
0c4
> > > > core. When I make the e300c4 core into sleep mode, it will return t=
o
> > > > full power mode when the=E2=80=9Cdecrementer interrupt=E2=80=9D occ=
urred.
> > > >=20
> > > > But in the e300 core reference manual said that the =E2=80=9Cdecrem=
enter
> > > > interrupt=E2=80=9Dhave no effect when e300 core in sleep mode, beca=
use the
> > > > time
> > > > base and decrementer are disabled while the core is in sleep mode.
> > > > Can anybody explain about this procedure ?
> >=20
> > I'm not specifically familiar with MPC5121, but I'll answer from the
> > perspective of MPC83xx which has a similar core:
> >=20
> > The decrementer stops ticking when the core goes to sleep. However, if=
a
> > decrementer was already pending (but masked with MSR[EE]) before you
> > enter sleep mode, it will cause a wakeup.
> >=20
> > To avoid this, the decrementer is set to a very large value prior to an=
d
> > after disabling interrupts. See generic_suspend_disable_irqs() in
> > arch/powerpc/kernel/time.c. Is this not happening for you? Which kern=
el
> > version are you using, and what mechanism are you using to go to sleep?=
=20
> >=20
> > > I'm a bit irritated that it's not as the "solution" can mean hardware
> > > changes an thus it's potentially expensive.
> >=20
> > What sort of hardware changes?
>=20
> I don't want to spread missinformation but this procedure has helped on
> the ads5121 rev3 and two custom boards.=20
>=20
> the gpio 28,29,30 needs to be low and gpio31 needs to be hi. regardless
> of what is used as wakeup source when the device enters deep sleep
> otherwise you end up in some sort of meta state where you might not wake
> up on anything and you have this 42 second auto wakeup from the
> decrementer.=20
I use ads5121 rev4.1 board, the gpio 28,29,30 is low and gpio31 is high.
I find that the RTC is fail too, when I use hwclock -f /dev/rtc0 cmd, it
was always "Wed Dec 31 23:59:59 1969 0.000000 seconds". I measured the
the RTC oscillator is 32.768 kHz, and the VBAT_RTC is 4.2v. I have no
idea about why RTC is fail.=20
>=20
> Other weired states has also been observed. the PMC module is a bit
> tempremental in this chip.
>=20
>=20
>=20
^ permalink raw reply
* Re: Question about e300 core decrementer interrupt
From: Li Tao @ 2009-09-10 11:58 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Kenneth Johansson
In-Reply-To: <20090909184343.GC8215@b07421-ec1.am.freescale.net>
Hi Scott Wood,
Thanks for your response
=E5=9C=A8 2009-09-09=E4=B8=89=E7=9A=84 13:43 -0500=EF=BC=8CScott Wood=E5=86=
=99=E9=81=93=EF=BC=9A
> On Wed, Sep 09, 2009 at 01:16:07PM +0200, Kenneth Johansson wrote:
> > On Tue, 2009-09-08 at 13:48 +0800, Li Tao-B22598 wrote:
> > > Dear all,
> > >=20
> > > I have a problem in MPC5121 sleep mode. As you know MPC5121 use e300c=
4
> > > core. When I make the e300c4 core into sleep mode, it will return to
> > > full power mode when the=E2=80=9Cdecrementer interrupt=E2=80=9D occur=
red.
> > >=20
> > > But in the e300 core reference manual said that the =E2=80=9Cdecremen=
ter
> > > interrupt=E2=80=9Dhave no effect when e300 core in sleep mode, becaus=
e the
> > > time
> > > base and decrementer are disabled while the core is in sleep mode.
> > > Can anybody explain about this procedure ?
>=20
> I'm not specifically familiar with MPC5121, but I'll answer from the
> perspective of MPC83xx which has a similar core:
>=20
> The decrementer stops ticking when the core goes to sleep. However, if a
> decrementer was already pending (but masked with MSR[EE]) before you
> enter sleep mode, it will cause a wakeup.
>=20
> To avoid this, the decrementer is set to a very large value prior to and
> after disabling interrupts. See generic_suspend_disable_irqs() in
> arch/powerpc/kernel/time.c. Is this not happening for you? Which kernel
> version are you using, and what mechanism are you using to go to sleep?
I use 2.6.24 kernel. The PM driver code have set decrementer to
0x7fffffff before go to sleep mode.
The driver set HID0[10]=3D1, then set MSR POW bit. PMCCR =3D 00111.
> =20
>=20
> > I'm a bit irritated that it's not as the "solution" can mean hardware
> > changes an thus it's potentially expensive.
>=20
> What sort of hardware changes?
>=20
> -Scott
^ permalink raw reply
* Re: [PATCH 2/3] ucc_geth: Rearrange some code to avoid forward declarations
From: Timur Tabi @ 2009-09-10 13:00 UTC (permalink / raw)
To: Anton Vorontsov; +Cc: netdev, linuxppc-dev, Andy Fleming, David Miller
In-Reply-To: <20090910020140.GB31083@oksana.dev.rtsoft.ru>
Anton Vorontsov wrote:
> We'll need ugeth_disable() and ugeth_enable() calls earlier in the
> file, so rearrange some code to avoid forward declarations.
>
> The patch doesn't contain any functional changes.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Timur Tabi <timur@freescale.com>
I'm generally not qualified to review ucc_geth patches, but I'm in favor of this one. I hate forward declarations.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: MPC85xx External/Internal Interrupts
From: Sebastian Andrzej Siewior @ 2009-09-10 13:15 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Alemao, linux-kernel
In-Reply-To: <20090909182857.GB8215@b07421-ec1.am.freescale.net>
* Scott Wood | 2009-09-09 13:28:57 [-0500]:
>> That's why you always have an offset of 16 between every internal
>> interupt source number in the MPC855ERM document and those weired
>> numbers in the device tree :)
>
>This seems to be a common point of confusion -- we should probably put
>something in the dts bindings that explains it. Am I correct in assuming
>that this particular internal/external split is Freescale-specific and
>not a general OpenPIC thing?
Yes it looks like this. I can see this split in all mpc85xx boards and
mpc8610 boards from Freescale. There just two boards where I don't see
this kind of split: holly & kurobox and I don't the have the reference
manual for both of them to check. I also don't have an OpenPIC spec to
check there.
So from this it looks like e500/e600 thing and FSL only so far.
>
>-Scott
Sebastian
^ permalink raw reply
* [PATCH] powerpc/boot/dts: drop obsolete 'fsl5200-clocking'
From: Wolfram Sang @ 2009-09-10 14:55 UTC (permalink / raw)
To: linuxppc-dev
The 'fsl5200-clocking'-property was dropped since
0d1cde235874b00905bce23f659690d060ebf475. Remove all occurences in dts-files.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
---
arch/powerpc/boot/dts/cm5200.dts | 1 -
arch/powerpc/boot/dts/digsy_mtc.dts | 1 -
arch/powerpc/boot/dts/lite5200.dts | 2 --
arch/powerpc/boot/dts/lite5200b.dts | 2 --
arch/powerpc/boot/dts/media5200.dts | 2 --
arch/powerpc/boot/dts/motionpro.dts | 1 -
arch/powerpc/boot/dts/mpc5121ads.dts | 3 ---
arch/powerpc/boot/dts/pcm030.dts | 2 --
arch/powerpc/boot/dts/pcm032.dts | 2 --
arch/powerpc/boot/dts/tqm5200.dts | 1 -
10 files changed, 0 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index cee8080..dd38608 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -210,7 +210,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
- fsl5200-clocking;
};
sram@8000 {
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index 4c36186..8e9be6b 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -199,7 +199,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
- fsl5200-clocking;
rtc@50 {
compatible = "at,24c08";
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index de30b3f..82ff2b1 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -247,7 +247,6 @@
compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
- fsl5200-clocking;
};
i2c@3d40 {
@@ -256,7 +255,6 @@
compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
- fsl5200-clocking;
};
sram@8000 {
compatible = "fsl,mpc5200-sram";
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index d13cb11..e45a63b 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -251,7 +251,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
- fsl5200-clocking;
};
i2c@3d40 {
@@ -260,7 +259,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
- fsl5200-clocking;
};
sram@8000 {
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index e297d8b..0c3902b 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -223,7 +223,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
- fsl5200-clocking;
};
i2c@3d40 {
@@ -232,7 +231,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
- fsl5200-clocking;
};
sram@8000 {
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 7be8ca0..6ca4fc1 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -222,7 +222,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
- fsl5200-clocking;
rtc@68 {
compatible = "dallas,ds1339";
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c2b8dbf..c353dac 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -209,7 +209,6 @@
reg = <0x1700 0x20>;
interrupts = <9 0x8>;
interrupt-parent = < &ipic >;
- fsl5200-clocking;
};
i2c@1720 {
@@ -220,7 +219,6 @@
reg = <0x1720 0x20>;
interrupts = <10 0x8>;
interrupt-parent = < &ipic >;
- fsl5200-clocking;
};
i2c@1740 {
@@ -231,7 +229,6 @@
reg = <0x1740 0x20>;
interrupts = <11 0x8>;
interrupt-parent = < &ipic >;
- fsl5200-clocking;
};
i2ccontrol@1760 {
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index 30bfdc0..8a4ec30 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -244,7 +244,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
- fsl5200-clocking;
};
i2c@3d40 {
@@ -253,7 +252,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
- fsl5200-clocking;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index 0300426..85d857a 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -244,7 +244,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d00 0x40>;
interrupts = <2 15 0>;
- fsl5200-clocking;
};
i2c@3d40 {
@@ -253,7 +252,6 @@
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
- fsl5200-clocking;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index c9590b5..1db07f6 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -160,7 +160,6 @@
compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>;
interrupts = <2 16 0>;
- fsl5200-clocking;
rtc@68 {
compatible = "dallas,ds1307";
--
1.6.3.3
^ permalink raw reply related
* Debian on MPC8572DS
From: Isaac Gomez Morales @ 2009-09-10 15:01 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 1334 bytes --]
Hello,
I'm trying to get a Linux distro such as Debian in the following system
System:
mpc8572ds HW
u-boot programmed on flash memory
vanillia linux installed on sata disk
Restrictions:
i have not apt-get resident on system
I have tried the following ways with no succeful results:
I tried to run deboostrap with chroot on mpc8572ds
I tried to run deboostrap on another machine, downloading the correct
packages for ppc enviroment and copiny those packages in a new ext2
partition of my 8572 hw. After that i executed "chroot /mnt/newpartition
/bin/bash" and it returned "Illegal instruction". At this point i can't
follow the installation and if i force to startup the machine with that rf
system, it returns a "kernel panic" with error to handling the signal 4 of
init process.
I tried to get start the machine with a debain livecd installation. I
created an uImage and initrd from cdrom's vmlinux and initrd.gz with the
uboot-mkimage tool, then i booted it from u-boot but the kernel didn't
start.
I tried to start a preinstalled Debian for a simillar architecture, in
cocnret from a mpc8561 ppc's Debian. I put its hhdd with the Debian rfs on
my machine and start it with my uImage and dtb files. The results was the
same "kernel panic" and signal 4 error.
I accept all ideas.
Thanks you all and sorry for my english
[-- Attachment #2: Type: text/html, Size: 1612 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc/boot/dts: drop obsolete 'fsl5200-clocking'
From: Grant Likely @ 2009-09-10 15:05 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linuxppc-dev
In-Reply-To: <1252594539-25202-1-git-send-email-w.sang@pengutronix.de>
On Thu, Sep 10, 2009 at 8:55 AM, Wolfram Sang <w.sang@pengutronix.de> wrote=
:
> The 'fsl5200-clocking'-property was dropped since
> 0d1cde235874b00905bce23f659690d060ebf475. Remove all occurences in dts-fi=
les.
>
> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
Looks good to me. I'll pick it up.
g.
> ---
> =A0arch/powerpc/boot/dts/cm5200.dts =A0 =A0 | =A0 =A01 -
> =A0arch/powerpc/boot/dts/digsy_mtc.dts =A0| =A0 =A01 -
> =A0arch/powerpc/boot/dts/lite5200.dts =A0 | =A0 =A02 --
> =A0arch/powerpc/boot/dts/lite5200b.dts =A0| =A0 =A02 --
> =A0arch/powerpc/boot/dts/media5200.dts =A0| =A0 =A02 --
> =A0arch/powerpc/boot/dts/motionpro.dts =A0| =A0 =A01 -
> =A0arch/powerpc/boot/dts/mpc5121ads.dts | =A0 =A03 ---
> =A0arch/powerpc/boot/dts/pcm030.dts =A0 =A0 | =A0 =A02 --
> =A0arch/powerpc/boot/dts/pcm032.dts =A0 =A0 | =A0 =A02 --
> =A0arch/powerpc/boot/dts/tqm5200.dts =A0 =A0| =A0 =A01 -
> =A010 files changed, 0 insertions(+), 17 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5=
200.dts
> index cee8080..dd38608 100644
> --- a/arch/powerpc/boot/dts/cm5200.dts
> +++ b/arch/powerpc/boot/dts/cm5200.dts
> @@ -210,7 +210,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d40 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 16 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sram@8000 {
> diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/=
digsy_mtc.dts
> index 4c36186..8e9be6b 100644
> --- a/arch/powerpc/boot/dts/digsy_mtc.dts
> +++ b/arch/powerpc/boot/dts/digsy_mtc.dts
> @@ -199,7 +199,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d00 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 15 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0rtc@50 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible=
=3D "at,24c08";
> diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/l=
ite5200.dts
> index de30b3f..82ff2b1 100644
> --- a/arch/powerpc/boot/dts/lite5200.dts
> +++ b/arch/powerpc/boot/dts/lite5200.dts
> @@ -247,7 +247,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d00 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 15 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2c@3d40 {
> @@ -256,7 +255,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d40 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 16 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sram@8000 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0-sram";
> diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/=
lite5200b.dts
> index d13cb11..e45a63b 100644
> --- a/arch/powerpc/boot/dts/lite5200b.dts
> +++ b/arch/powerpc/boot/dts/lite5200b.dts
> @@ -251,7 +251,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d00 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 15 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2c@3d40 {
> @@ -260,7 +259,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d40 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 16 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sram@8000 {
> diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/=
media5200.dts
> index e297d8b..0c3902b 100644
> --- a/arch/powerpc/boot/dts/media5200.dts
> +++ b/arch/powerpc/boot/dts/media5200.dts
> @@ -223,7 +223,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d00 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 15 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2c@3d40 {
> @@ -232,7 +231,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d40 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 16 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0sram@8000 {
> diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/=
motionpro.dts
> index 7be8ca0..6ca4fc1 100644
> --- a/arch/powerpc/boot/dts/motionpro.dts
> +++ b/arch/powerpc/boot/dts/motionpro.dts
> @@ -222,7 +222,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d40 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 16 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0rtc@68 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible=
=3D "dallas,ds1339";
> diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts=
/mpc5121ads.dts
> index c2b8dbf..c353dac 100644
> --- a/arch/powerpc/boot/dts/mpc5121ads.dts
> +++ b/arch/powerpc/boot/dts/mpc5121ads.dts
> @@ -209,7 +209,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x1700 0x20>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <9 0x8>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D < &ip=
ic >;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2c@1720 {
> @@ -220,7 +219,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x1720 0x20>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <10 0x8>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D < &ip=
ic >;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2c@1740 {
> @@ -231,7 +229,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x1740 0x20>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <11 0x8>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D < &ip=
ic >;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2ccontrol@1760 {
> diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm=
030.dts
> index 30bfdc0..8a4ec30 100644
> --- a/arch/powerpc/boot/dts/pcm030.dts
> +++ b/arch/powerpc/boot/dts/pcm030.dts
> @@ -244,7 +244,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d00 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 15 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2c@3d40 {
> @@ -253,7 +252,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d40 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 16 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0rtc@51 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible=
=3D "nxp,pcf8563";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0=
x51>;
> diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm=
032.dts
> index 0300426..85d857a 100644
> --- a/arch/powerpc/boot/dts/pcm032.dts
> +++ b/arch/powerpc/boot/dts/pcm032.dts
> @@ -244,7 +244,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d00 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 15 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2c@3d40 {
> @@ -253,7 +252,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d40 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 16 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0rtc@51 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible=
=3D "nxp,pcf8563";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0=
x51>;
> diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tq=
m5200.dts
> index c9590b5..1db07f6 100644
> --- a/arch/powerpc/boot/dts/tqm5200.dts
> +++ b/arch/powerpc/boot/dts/tqm5200.dts
> @@ -160,7 +160,6 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc520=
0-i2c","fsl-i2c";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x3d40 0x40>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <2 16 0>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 fsl5200-clocking;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rtc@68 {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible=
=3D "dallas,ds1307";
> --
> 1.6.3.3
>
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* RE: [PATCH][v1] powerpc/85xx: Create dts for each core in CAMPmode for P2020RDB
From: Aggrwal Poonam-B10812 @ 2009-09-10 15:18 UTC (permalink / raw)
To: Gabriel Paubert; +Cc: linuxppc-dev
In-Reply-To: <20090910093307.GA17117@iram.es>
=20
> -----Original Message-----
> From: Gabriel Paubert [mailto:paubert@iram.es]=20
> Sent: Thursday, September 10, 2009 3:03 PM
> To: Aggrwal Poonam-B10812
> Cc: linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH][v1] powerpc/85xx: Create dts for each=20
> core in CAMPmode for P2020RDB
>=20
> On Thu, Sep 10, 2009 at 02:27:11PM +0530, Poonam Aggrwal wrote:
> > This patch creates the dts files for each core and splits=20
> the devices=20
> > between the two cores for P2020RDB.
> >=20
> > core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto,=20
> > global-util, pci0
> > core1 has L2, dma2, eth0, pci1, msi.
>=20
> Surely you mean eth1 and eth2 for core0, no?
Yes you are right , I'll fix this.
>=20
> At least it's what I gather from the code.
>=20
> Also both cores have a node called serial0, at different=20
> addresses but with the same interrupt!
Yes both the UARTS use the same int line in shared mode.=20
>=20
> But in the mpic comment line there is "serial1", and=20
> interrupt 42 is the only number which appears in both lists=20
> of mpic protected interrupts.
I am not sure how to handle the shared interrupts in AMP scenario,
although this has been tested and both serials are working one on each
core.
>=20
Regards
Poonam
> Gabriel
>=20
> > ---
> > - based on=20
> > http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> > - branch->next
> > arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 365=20
> > +++++++++++++++++++++++++ =20
> arch/powerpc/boot/dts/p2020rdb_camp_core1.dts | 186 +++++++++++++
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 10 +-
> > 3 files changed, 560 insertions(+), 1 deletions(-) create mode=20
> > 100644 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
> > create mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
> >=20
> > diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts=20
> > b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
> > new file mode 100644
> > index 0000000..ca072da
> > --- /dev/null
> > +++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
> > @@ -0,0 +1,365 @@
> > +/*
> > + * P2020 RDB Core0 Device Tree Source in CAMP mode.
> > + *
> > + * In CAMP mode, each core needs to have its own dts. Only=20
> mpic and=20
> > +L2 cache
> > + * can be shared, all the other devices must be assigned=20
> to one core only.
> > + * This dts file allows core0 to have memory, l2, i2c, spi, gpio,=20
> > +dma1, usb,
> > + * eth1, eth2, sdhc, crypto, global-util, pci0.
> > + *
> > + * Copyright 2009 Freescale Semiconductor Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or=20
> > +modify it
> > + * under the terms of the GNU General Public License as=20
> published=20
> > +by the
> > + * Free Software Foundation; either version 2 of the License, or=20
> > +(at your
> > + * option) any later version.
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > + model =3D "fsl,P2020";
> > + compatible =3D "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
> > + #address-cells =3D <2>;
> > + #size-cells =3D <2>;
> > +
> > + aliases {
> > + ethernet1 =3D &enet1;
> > + ethernet2 =3D &enet2;
> > + serial0 =3D &serial0;
> > + pci0 =3D &pci0;
> > + };
> > +
> > + cpus {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > +
> > + PowerPC,P2020@0 {
> > + device_type =3D "cpu";
> > + reg =3D <0x0>;
> > + next-level-cache =3D <&L2>;
> > + };
> > + };
> > +
> > + memory {
> > + device_type =3D "memory";
> > + };
> > +
> > + soc@ffe00000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + device_type =3D "soc";
> > + compatible =3D "fsl,p2020-immr", "simple-bus";
> > + ranges =3D <0x0 0x0 0xffe00000 0x100000>;
> > + bus-frequency =3D <0>; // Filled out by uboot.
> > +
> > + ecm-law@0 {
> > + compatible =3D "fsl,ecm-law";
> > + reg =3D <0x0 0x1000>;
> > + fsl,num-laws =3D <12>;
> > + };
> > +
> > + ecm@1000 {
> > + compatible =3D "fsl,p2020-ecm", "fsl,ecm";
> > + reg =3D <0x1000 0x1000>;
> > + interrupts =3D <17 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + memory-controller@2000 {
> > + compatible =3D "fsl,p2020-memory-controller";
> > + reg =3D <0x2000 0x1000>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <18 2>;
> > + };
> > +
> > + i2c@3000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + cell-index =3D <0>;
> > + compatible =3D "fsl-i2c";
> > + reg =3D <0x3000 0x100>;
> > + interrupts =3D <43 2>;
> > + interrupt-parent =3D <&mpic>;
> > + dfsrr;
> > + rtc@68 {
> > + compatible =3D "dallas,ds1339";
> > + reg =3D <0x68>;
> > + };
> > + };
> > +
> > + i2c@3100 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + cell-index =3D <1>;
> > + compatible =3D "fsl-i2c";
> > + reg =3D <0x3100 0x100>;
> > + interrupts =3D <43 2>;
> > + interrupt-parent =3D <&mpic>;
> > + dfsrr;
> > + };
> > +
> > + serial0: serial@4500 {
> > + cell-index =3D <0>;
> > + device_type =3D "serial";
> > + compatible =3D "ns16550";
> > + reg =3D <0x4500 0x100>;
> > + clock-frequency =3D <0>;
> > + interrupts =3D <42 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + spi@7000 {
> > + cell-index =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,espi";
> > + reg =3D <0x7000 0x1000>;
> > + interrupts =3D <59 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + mode =3D "cpu";
> > +
> > + fsl_m25p80@0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,espi-flash";
> > + reg =3D <0>;
> > + linux,modalias =3D "fsl_m25p80";
> > + modal =3D "s25sl128b";
> > + spi-max-frequency =3D <50000000>;
> > + mode =3D <0>;
> > +
> > + partition@0 {
> > + /* 512KB for u-boot=20
> Bootloader Image */
> > + reg =3D <0x0 0x00080000>;
> > + label =3D "SPI (RO) U-Boot Image";
> > + read-only;
> > + };
> > +
> > + partition@80000 {
> > + /* 512KB for DTB Image */
> > + reg =3D <0x00080000 0x00080000>;
> > + label =3D "SPI (RO) DTB Image";
> > + read-only;
> > + };
> > +
> > + partition@100000 {
> > + /* 4MB for Linux Kernel Image */
> > + reg =3D <0x00100000 0x00400000>;
> > + label =3D "SPI (RO) Linux=20
> Kernel Image";
> > + read-only;
> > + };
> > +
> > + partition@500000 {
> > + /* 4MB for Compressed=20
> RFS Image */
> > + reg =3D <0x00500000 0x00400000>;
> > + label =3D "SPI (RO)=20
> Compressed RFS Image";
> > + read-only;
> > + };
> > +
> > + partition@900000 {
> > + /* 7MB for JFFS2 based RFS */
> > + reg =3D <0x00900000 0x00700000>;
> > + label =3D "SPI (RW) JFFS2 RFS";
> > + };
> > + };
> > + };
> > +
> > + gpio: gpio-controller@f000 {
> > + #gpio-cells =3D <2>;
> > + compatible =3D "fsl,mpc8572-gpio";
> > + reg =3D <0xf000 0x100>;
> > + interrupts =3D <47 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + gpio-controller;
> > + };
> > +
> > + L2: l2-cache-controller@20000 {
> > + compatible =3D "fsl,p2020-l2-cache-controller";
> > + reg =3D <0x20000 0x1000>;
> > + cache-line-size =3D <32>; // 32 bytes
> > + cache-size =3D <0x80000>; // L2,512K
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <16 2>;
> > + };
> > +
> > + dma@21300 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,eloplus-dma";
> > + reg =3D <0x21300 0x4>;
> > + ranges =3D <0x0 0x21100 0x200>;
> > + cell-index =3D <0>;
> > + dma-channel@0 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x0 0x80>;
> > + cell-index =3D <0>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <20 2>;
> > + };
> > + dma-channel@80 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x80 0x80>;
> > + cell-index =3D <1>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <21 2>;
> > + };
> > + dma-channel@100 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x100 0x80>;
> > + cell-index =3D <2>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <22 2>;
> > + };
> > + dma-channel@180 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x180 0x80>;
> > + cell-index =3D <3>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <23 2>;
> > + };
> > + };
> > +
> > + usb@22000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl-usb2-dr";
> > + reg =3D <0x22000 0x1000>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <28 0x2>;
> > + phy_type =3D "ulpi";
> > + };
> > +
> > + mdio@24520 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,gianfar-mdio";
> > + reg =3D <0x24520 0x20>;
> > +
> > + phy0: ethernet-phy@0 {
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <3 1>;
> > + reg =3D <0x0>;
> > + };
> > + phy1: ethernet-phy@1 {
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <3 1>;
> > + reg =3D <0x1>;
> > + };
> > + };
> > +
> > + mdio@25520 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,gianfar-tbi";
> > + reg =3D <0x26520 0x20>;
> > +
> > + tbi0: tbi-phy@11 {
> > + reg =3D <0x11>;
> > + device_type =3D "tbi-phy";
> > + };
> > + };
> > +
> > + enet1: ethernet@25000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <1>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x25000 0x1000>;
> > + ranges =3D <0x0 0x25000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <35 2 36 2 40 2>;
> > + interrupt-parent =3D <&mpic>;
> > + tbi-handle =3D <&tbi0>;
> > + phy-handle =3D <&phy0>;
> > + phy-connection-type =3D "sgmii";
> > +
> > + };
> > +
> > + enet2: ethernet@26000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <2>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x26000 0x1000>;
> > + ranges =3D <0x0 0x26000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <31 2 32 2 33 2>;
> > + interrupt-parent =3D <&mpic>;
> > + phy-handle =3D <&phy1>;
> > + phy-connection-type =3D "rgmii-id";
> > + };
> > +
> > + sdhci@2e000 {
> > + compatible =3D "fsl,p2020-esdhc", "fsl,esdhc";
> > + reg =3D <0x2e000 0x1000>;
> > + interrupts =3D <72 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + /* Filled in by U-Boot */
> > + clock-frequency =3D <0>;
> > + };
> > +
> > + crypto@30000 {
> > + compatible =3D "fsl,sec3.1",=20
> "fsl,sec3.0", "fsl,sec2.4",
> > + "fsl,sec2.2",=20
> "fsl,sec2.1", "fsl,sec2.0";
> > + reg =3D <0x30000 0x10000>;
> > + interrupts =3D <45 2 58 2>;
> > + interrupt-parent =3D <&mpic>;
> > + fsl,num-channels =3D <4>;
> > + fsl,channel-fifo-len =3D <24>;
> > + fsl,exec-units-mask =3D <0xbfe>;
> > + fsl,descriptor-types-mask =3D <0x3ab0ebf>;
> > + };
> > +
> > + mpic: pic@40000 {
> > + interrupt-controller;
> > + #address-cells =3D <0>;
> > + #interrupt-cells =3D <2>;
> > + reg =3D <0x40000 0x40000>;
> > + compatible =3D "chrp,open-pic";
> > + device_type =3D "open-pic";
> > + protected-sources =3D <
> > + 42 76 77 78 79 /* serial1 , dma2 */
> > + 29 30 34 26 /* enet0, pci1 */
> > + 0xe0 0xe1 0xe2 0xe3 /* msi */
> > + 0xe4 0xe5 0xe6 0xe7
> > + >;
> > + };
> > +
> > + global-utilities@e0000 {
> > + compatible =3D "fsl,p2020-guts";
> > + reg =3D <0xe0000 0x1000>;
> > + fsl,has-rstcr;
> > + };
> > + };
> > +
> > + pci0: pcie@ffe09000 {
> > + compatible =3D "fsl,mpc8548-pcie";
> > + device_type =3D "pci";
> > + #interrupt-cells =3D <1>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + reg =3D <0 0xffe09000 0 0x1000>;
> > + bus-range =3D <0 255>;
> > + ranges =3D <0x2000000 0x0 0xa0000000 0 0xa0000000=20
> 0x0 0x20000000
> > + 0x1000000 0x0 0x00000000 0 0xffc30000=20
> 0x0 0x10000>;
> > + clock-frequency =3D <33333333>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <25 2>;
> > + pcie@0 {
> > + reg =3D <0x0 0x0 0x0 0x0 0x0>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + device_type =3D "pci";
> > + ranges =3D <0x2000000 0x0 0xa0000000
> > + 0x2000000 0x0 0xa0000000
> > + 0x0 0x20000000
> > +
> > + 0x1000000 0x0 0x0
> > + 0x1000000 0x0 0x0
> > + 0x0 0x100000>;
> > + };
> > + };
> > +};
> > diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts=20
> > b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
> > new file mode 100644
> > index 0000000..c3c9da6
> > --- /dev/null
> > +++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
> > @@ -0,0 +1,186 @@
> > +/*
> > + * P2020 RDB Core1 Device Tree Source in CAMP mode.
> > + *
> > + * In CAMP mode, each core needs to have its own dts. Only=20
> mpic and=20
> > +L2 cache
> > + * can be shared, all the other devices must be assigned=20
> to one core only.
> > + * This dts allows core1 to have l2, dma2, eth0, pci1, msi.
> > + *
> > + * Please note to add "-b 1" for core1's dts compiling.
> > + *
> > + * Copyright 2009 Freescale Semiconductor Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or=20
> > +modify it
> > + * under the terms of the GNU General Public License as=20
> published=20
> > +by the
> > + * Free Software Foundation; either version 2 of the License, or=20
> > +(at your
> > + * option) any later version.
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > + model =3D "fsl,P2020";
> > + compatible =3D "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
> > + #address-cells =3D <2>;
> > + #size-cells =3D <2>;
> > +
> > + aliases {
> > + ethernet0 =3D &enet0;
> > + serial0 =3D &serial0;
> > + pci1 =3D &pci1;
> > + };
> > +
> > + cpus {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > +
> > + PowerPC,P2020@1 {
> > + device_type =3D "cpu";
> > + reg =3D <0x1>;
> > + next-level-cache =3D <&L2>;
> > + };
> > + };
> > +
> > + memory {
> > + device_type =3D "memory";
> > + };
> > +
> > + soc@ffe00000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + device_type =3D "soc";
> > + compatible =3D "fsl,p2020-immr", "simple-bus";
> > + ranges =3D <0x0 0x0 0xffe00000 0x100000>;
> > + bus-frequency =3D <0>; // Filled out by uboot.
> > +
> > + serial0: serial@4600 {
> > + cell-index =3D <1>;
> > + device_type =3D "serial";
> > + compatible =3D "ns16550";
> > + reg =3D <0x4600 0x100>;
> > + clock-frequency =3D <0>;
> > + interrupts =3D <42 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + dma@c300 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,eloplus-dma";
> > + reg =3D <0xc300 0x4>;
> > + ranges =3D <0x0 0xc100 0x200>;
> > + cell-index =3D <1>;
> > + dma-channel@0 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x0 0x80>;
> > + cell-index =3D <0>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <76 2>;
> > + };
> > + dma-channel@80 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x80 0x80>;
> > + cell-index =3D <1>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <77 2>;
> > + };
> > + dma-channel@100 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x100 0x80>;
> > + cell-index =3D <2>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <78 2>;
> > + };
> > + dma-channel@180 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x180 0x80>;
> > + cell-index =3D <3>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <79 2>;
> > + };
> > + };
> > +
> > + L2: l2-cache-controller@20000 {
> > + compatible =3D "fsl,p2020-l2-cache-controller";
> > + reg =3D <0x20000 0x1000>;
> > + cache-line-size =3D <32>; // 32 bytes
> > + cache-size =3D <0x80000>; // L2,512K
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > +
> > + enet0: ethernet@24000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <0>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x24000 0x1000>;
> > + ranges =3D <0x0 0x24000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <29 2 30 2 34 2>;
> > + interrupt-parent =3D <&mpic>;
> > + fixed-link =3D <1 1 1000 0 0>;
> > + phy-connection-type =3D "rgmii-id";
> > +
> > + };
> > +
> > + mpic: pic@40000 {
> > + interrupt-controller;
> > + #address-cells =3D <0>;
> > + #interrupt-cells =3D <2>;
> > + reg =3D <0x40000 0x40000>;
> > + compatible =3D "chrp,open-pic";
> > + device_type =3D "open-pic";
> > + protected-sources =3D <
> > + 17 18 43 42 59 47 /*ecm, mem, i2c,=20
> serial0, spi,gpio */
> > + 16 20 21 22 23 28 /* L2, dma1, USB */
> > + 03 35 36 40 31 32 33 /* mdio, enet1, enet2 */
> > + 72 45 58 25 /* sdhci,=20
> crypto , pci */
> > + >;
> > + };
> > +
> > + msi@41600 {
> > + compatible =3D "fsl,p2020-msi", "fsl,mpic-msi";
> > + reg =3D <0x41600 0x80>;
> > + msi-available-ranges =3D <0 0x100>;
> > + interrupts =3D <
> > + 0xe0 0
> > + 0xe1 0
> > + 0xe2 0
> > + 0xe3 0
> > + 0xe4 0
> > + 0xe5 0
> > + 0xe6 0
> > + 0xe7 0>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > + };
> > +
> > + pci1: pcie@ffe0a000 {
> > + compatible =3D "fsl,mpc8548-pcie";
> > + device_type =3D "pci";
> > + #interrupt-cells =3D <1>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + reg =3D <0 0xffe0a000 0 0x1000>;
> > + bus-range =3D <0 255>;
> > + ranges =3D <0x2000000 0x0 0xc0000000 0 0xc0000000=20
> 0x0 0x20000000
> > + 0x1000000 0x0 0x00000000 0 0xffc20000=20
> 0x0 0x10000>;
> > + clock-frequency =3D <33333333>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <26 2>;
> > + pcie@0 {
> > + reg =3D <0x0 0x0 0x0 0x0 0x0>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + device_type =3D "pci";
> > + ranges =3D <0x2000000 0x0 0xc0000000
> > + 0x2000000 0x0 0xc0000000
> > + 0x0 0x20000000
> > +
> > + 0x1000000 0x0 0x0
> > + 0x1000000 0x0 0x0
> > + 0x0 0x100000>;
> > + };
> > + };
> > +};
> > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c=20
> > b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > index 495bd8b..088f30b 100644
> > --- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > @@ -44,6 +44,7 @@ void __init mpc85xx_rdb_pic_init(void)
> > struct mpic *mpic;
> > struct resource r;
> > struct device_node *np;
> > + unsigned long root =3D of_get_flat_dt_root();
> > =20
> > np =3D of_find_node_by_type(NULL, "open-pic");
> > if (np =3D=3D NULL) {
> > @@ -57,11 +58,18 @@ void __init mpc85xx_rdb_pic_init(void)
> > return;
> > }
> > =20
> > - mpic =3D mpic_alloc(np, r.start,
> > + if (of_flat_dt_is_compatible(root, "fsl,85XXRDB-CAMP")) {
> > + mpic =3D mpic_alloc(np, r.start,
> > + MPIC_PRIMARY |
> > + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
> > + 0, 256, " OpenPIC ");
> > + } else {
> > + mpic =3D mpic_alloc(np, r.start,
> > MPIC_PRIMARY | MPIC_WANTS_RESET |
> > MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
> > MPIC_SINGLE_DEST_CPU,
> > 0, 256, " OpenPIC ");
> > + }
> > =20
> > BUG_ON(mpic =3D=3D NULL);
> > of_node_put(np);
> > --
> > 1.5.6.5
> >=20
> > _______________________________________________
> > Linuxppc-dev mailing list
> > Linuxppc-dev@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/linuxppc-dev
>=20
>=20
^ permalink raw reply
* Re: Question about e300 core decrementer interrupt
From: Scott Wood @ 2009-09-10 15:30 UTC (permalink / raw)
To: Li Tao; +Cc: linuxppc-dev, Kenneth Johansson
In-Reply-To: <1252583922.26108.23.camel@ubuntu.ubuntu-domain>
Li Tao wrote:
> Hi Scott Wood,
> Thanks for your response
>
> 在 2009-09-09三的 13:43 -0500，Scott Wood写道：
>> The decrementer stops ticking when the core goes to sleep. However, if a
>> decrementer was already pending (but masked with MSR[EE]) before you
>> enter sleep mode, it will cause a wakeup.
>>
>> To avoid this, the decrementer is set to a very large value prior to and
>> after disabling interrupts. See generic_suspend_disable_irqs() in
>> arch/powerpc/kernel/time.c. Is this not happening for you? Which kernel
>> version are you using, and what mechanism are you using to go to sleep?
> I use 2.6.24 kernel. The PM driver code have set decrementer to
> 0x7fffffff before go to sleep mode.
It looks like 2.6.24 doesn't have commit
7ac5dde99eb9fefdb526973c600075b7c5703a86 (Implement arch disable/enable
irq hooks) -- are you disabling the decrementer in a similar manner, or
is it possible that the decrementer has already fired by the time you
set it to 0x7fffffff? Could you read the value just prior to entering
sleep?
Why use such an old kernel, BTW?
> The driver set HID0[10]=1, then set MSR POW bit. PMCCR = 00111.
I was more interested in whether you were using the suspend_ops (maybe
pm_ops back then?) infrastructure (which would invoke the irq hooks) or
something custom.
-Scott
^ permalink raw reply
* Re: [PATCH][v1] powerpc/85xx: Create dts for each core in CAMPmode for P2020RDB
From: Gabriel Paubert @ 2009-09-10 16:02 UTC (permalink / raw)
To: Aggrwal Poonam-B10812; +Cc: linuxppc-dev
In-Reply-To: <1BD5CFC378ED0946B688E0C9BA2EF0951FD268@zin33exm24.fsl.freescale.net>
On Thu, Sep 10, 2009 at 08:48:38PM +0530, Aggrwal Poonam-B10812 wrote:
>
>
> > -----Original Message-----
> > From: Gabriel Paubert [mailto:paubert@iram.es]
> > Sent: Thursday, September 10, 2009 3:03 PM
> > To: Aggrwal Poonam-B10812
> > Cc: linuxppc-dev@ozlabs.org
> > Subject: Re: [PATCH][v1] powerpc/85xx: Create dts for each
> > core in CAMPmode for P2020RDB
> >
> > On Thu, Sep 10, 2009 at 02:27:11PM +0530, Poonam Aggrwal wrote:
> > > This patch creates the dts files for each core and splits
> > the devices
> > > between the two cores for P2020RDB.
> > >
> > > core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto,
> > > global-util, pci0
> > > core1 has L2, dma2, eth0, pci1, msi.
> >
> > Surely you mean eth1 and eth2 for core0, no?
> Yes you are right , I'll fix this.
> >
> > At least it's what I gather from the code.
> >
> > Also both cores have a node called serial0, at different
> > addresses but with the same interrupt!
> Yes both the UARTS use the same int line in shared mode.
> >
> > But in the mpic comment line there is "serial1", and
> > interrupt 42 is the only number which appears in both lists
> > of mpic protected interrupts.
> I am not sure how to handle the shared interrupts in AMP scenario,
> although this has been tested and both serials are working one on each
> core.
Ok, I wrongly understood protected interrupts as reserved
for one core. However, I still dislike two devices having the same
name.
Otherwise it may work if every interrupt is delivered to both
cores although statistically only one core will actually have
some work to do. Doesn't the kernel complain about unhandled irqs
however?
Regards,
Gabriel
> > > +
> > > + serial0: serial@4500 {
> > > + cell-index = <0>;
> > > + device_type = "serial";
> > > + compatible = "ns16550";
> > > + reg = <0x4500 0x100>;
> > > + clock-frequency = <0>;
> > > + interrupts = <42 2>;
> > > + interrupt-parent = <&mpic>;
> > > + };
> > > +
> > > + mpic: pic@40000 {
> > > + interrupt-controller;
> > > + #address-cells = <0>;
> > > + #interrupt-cells = <2>;
> > > + reg = <0x40000 0x40000>;
> > > + compatible = "chrp,open-pic";
> > > + device_type = "open-pic";
> > > + protected-sources = <
> > > + 42 76 77 78 79 /* serial1 , dma2 */
> > > + 29 30 34 26 /* enet0, pci1 */
> > > + 0xe0 0xe1 0xe2 0xe3 /* msi */
> > > + 0xe4 0xe5 0xe6 0xe7
> > > + >;
> > > + };
> > > +
> > > +
> > > + serial0: serial@4600 {
> > > + cell-index = <1>;
> > > + device_type = "serial";
> > > + compatible = "ns16550";
> > > + reg = <0x4600 0x100>;
> > > + clock-frequency = <0>;
> > > + interrupts = <42 2>;
> > > + interrupt-parent = <&mpic>;
> > > + };
> > > +
> > > +
> > > + mpic: pic@40000 {
> > > + interrupt-controller;
> > > + #address-cells = <0>;
> > > + #interrupt-cells = <2>;
> > > + reg = <0x40000 0x40000>;
> > > + compatible = "chrp,open-pic";
> > > + device_type = "open-pic";
> > > + protected-sources = <
> > > + 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
> > > + 16 20 21 22 23 28 /* L2, dma1, USB */
> > > + 03 35 36 40 31 32 33 /* mdio, enet1, enet2 */
> > > + 72 45 58 25 /* sdhci, crypto , pci */
> > > + >;
> > > + };
> > > +
^ permalink raw reply
* Re: Debian on MPC8572DS
From: Scott Wood @ 2009-09-10 16:32 UTC (permalink / raw)
To: Isaac Gomez Morales; +Cc: linuxppc-dev
In-Reply-To: <38a5a2d10909100801x11049cddi1799c0ed6ee44410@mail.gmail.com>
On Thu, Sep 10, 2009 at 05:01:53PM +0200, Isaac Gomez Morales wrote:
> Hello,
>
> I'm trying to get a Linux distro such as Debian in the following system
>
> System:
> mpc8572ds HW
The 8572 does not have classic PowerPC floating point. The Debian
binaries use this, so they cannot run without emulation.
Emulation is slow, so you probably want something like this instead:
http://groups.google.com/group/linux.debian.ports.powerpc/browse_thread/thread/235607517fd7ae1e/f4638a2cdef09bf7?lnk=raot
http://download.breakpoint.cc/debian/linutronix-lenny-gnuspe/
-Scott
^ permalink raw reply
* How to access DCR registers in powerpc440gx? Got err when use macro def in Linux kernel
From: g r1x @ 2009-09-10 17:24 UTC (permalink / raw)
To: Linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 2797 bytes --]
Now, I'm writing a DMA driver on powerpc
440gx platform(2.6.26.5), as the only way to set up DMA Controller is
to access it's dcr registers with 'mfdcr' and 'mtdcr'.
I've found some dma code in Linux kernel 2.6.26.5, so I copy the code
u wrote to my driver module directory, and include them, but when I
compile my driver, gcc complains following err messages:
--------------------------------------------------------
{standard input}: Assembler messages:
{standard input}:83: Error: unsupported relocation against dmanr
---------------------------------------------------------
code I copy from kernel 2.6.26.5 (arch/ppc/syslib/ppc4xx_dma.c)
--------------------------------------------
#include "dcr.h"
/* #inlcude <asm/dcr-native.h> */
ppc_dma_ch_t dma_channels[MAX_PPC4xx_DMA_CHANNELS];
int ppc4xx_get_dma_status(void)
{
return (mfdcr(DCRN_DMASR));
}
void ppc4xx_enable_dma(unsigned int dmanr)
{
unsigned int control;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
.........
/ * for other xfer modes, the addresses are already set */
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8)); <----------------err
}
void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr)
{
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("set_src_addr: bad channel: %d\n", dmanr);
return;
}
#ifdef PPC4xx_DMA_64BIT
mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32));
#else
mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr);
#endif
}
--------------------------------------------------
DCR access micro I copied:
----------------------------------
#define mfdcr(rn) \
({ \
unsigned long rval; \
asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
rval; \
})
#define mtdcr(rn, val) \
asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
-----------------------------------------------------
Makefile I worte
-------------------------
obj-m := dmatest.o
dmatest-objs += dma.o core.o
KBUILD_CFLAGS += -m440 -mregnames -Wa, -booke
KBUILD_ASFAGS += -m440 -mregnames -Wa, -booke
---------
KBUILD_CFLAGS += -m440 -mregnames -Wa, -booke
KBUILD_ASFAGS += -m440 -mregnames -Wa, -booke
I add these two sentences when I read these
http://sourceware.org/ml/binutils/2004-09/msg00161.html.
When I change it to mfdcr(DCRN_DMACR0); then everything is fine. but
from the result I got when I insmod my module driver, dcr reg is not
changed.
It seems that it's the problem with gnu assembler, my GNU assembler ver is 2.17
The attachments are the c source file I copy from linux 2.6.26.5, and
I use these dma function to directly manipulate dcr registers, but
when I make my driver module outside kernel source tree, it complains
the error I mentioned above.
Thanks!
[-- Attachment #2: ppc4xx_dma.c --]
[-- Type: application/octet-stream, Size: 18648 bytes --]
/*
* IBM PPC4xx DMA engine core library
*
* Copyright 2000-2004 MontaVista Software Inc.
*
* Cleaned up and converted to new DCR access
* Matt Porter <mporter@kernel.crashing.org>
*
* Original code by Armin Kuster <akuster@mvista.com>
* and Pete Popov <ppopov@mvista.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/init.h>
#include <linux/module.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <asm/ppc4xx_dma.h>
ppc_dma_ch_t dma_channels[MAX_PPC4xx_DMA_CHANNELS];
int
ppc4xx_get_dma_status(void)
{
return (mfdcr(DCRN_DMASR));
}
void
ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr)
{
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("set_src_addr: bad channel: %d\n", dmanr);
return;
}
#ifdef PPC4xx_DMA_64BIT
mtdcr(DCRN_DMASAH0 + dmanr*2, (u32)(src_addr >> 32));
#else
mtdcr(DCRN_DMASA0 + dmanr*2, (u32)src_addr);
#endif
}
void
ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr)
{
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("set_dst_addr: bad channel: %d\n", dmanr);
return;
}
#ifdef PPC4xx_DMA_64BIT
mtdcr(DCRN_DMADAH0 + dmanr*2, (u32)(dst_addr >> 32));
#else
mtdcr(DCRN_DMADA0 + dmanr*2, (u32)dst_addr);
#endif
}
void
ppc4xx_enable_dma(unsigned int dmanr)
{
unsigned int control;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
unsigned int status_bits[] = { DMA_CS0 | DMA_TS0 | DMA_CH0_ERR,
DMA_CS1 | DMA_TS1 | DMA_CH1_ERR,
DMA_CS2 | DMA_TS2 | DMA_CH2_ERR,
DMA_CS3 | DMA_TS3 | DMA_CH3_ERR};
if (p_dma_ch->in_use) {
printk("enable_dma: channel %d in use\n", dmanr);
return;
}
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("enable_dma: bad channel: %d\n", dmanr);
return;
}
if (p_dma_ch->mode == DMA_MODE_READ) {
/* peripheral to memory */
ppc4xx_set_src_addr(dmanr, 0);
ppc4xx_set_dst_addr(dmanr, p_dma_ch->addr);
} else if (p_dma_ch->mode == DMA_MODE_WRITE) {
/* memory to peripheral */
ppc4xx_set_src_addr(dmanr, p_dma_ch->addr);
ppc4xx_set_dst_addr(dmanr, 0);
}
/* for other xfer modes, the addresses are already set */
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
control &= ~(DMA_TM_MASK | DMA_TD); /* clear all mode bits */
if (p_dma_ch->mode == DMA_MODE_MM) {
/* software initiated memory to memory */
control |= DMA_ETD_OUTPUT | DMA_TCE_ENABLE;
}
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
/*
* Clear the CS, TS, RI bits for the channel from DMASR. This
* has been observed to happen correctly only after the mode and
* ETD/DCE bits in DMACRx are set above. Must do this before
* enabling the channel.
*/
mtdcr(DCRN_DMASR, status_bits[dmanr]);
/*
* For device-paced transfers, Terminal Count Enable apparently
* must be on, and this must be turned on after the mode, etc.
* bits are cleared above (at least on Redwood-6).
*/
if ((p_dma_ch->mode == DMA_MODE_MM_DEVATDST) ||
(p_dma_ch->mode == DMA_MODE_MM_DEVATSRC))
control |= DMA_TCE_ENABLE;
/*
* Now enable the channel.
*/
control |= (p_dma_ch->mode | DMA_CE_ENABLE);
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
p_dma_ch->in_use = 1;
}
void
ppc4xx_disable_dma(unsigned int dmanr)
{
unsigned int control;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
if (!p_dma_ch->in_use) {
printk("disable_dma: channel %d not in use\n", dmanr);
return;
}
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("disable_dma: bad channel: %d\n", dmanr);
return;
}
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
control &= ~DMA_CE_ENABLE;
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
p_dma_ch->in_use = 0;
}
/*
* Sets the dma mode for single DMA transfers only.
* For scatter/gather transfers, the mode is passed to the
* alloc_dma_handle() function as one of the parameters.
*
* The mode is simply saved and used later. This allows
* the driver to call set_dma_mode() and set_dma_addr() in
* any order.
*
* Valid mode values are:
*
* DMA_MODE_READ peripheral to memory
* DMA_MODE_WRITE memory to peripheral
* DMA_MODE_MM memory to memory
* DMA_MODE_MM_DEVATSRC device-paced memory to memory, device at src
* DMA_MODE_MM_DEVATDST device-paced memory to memory, device at dst
*/
int
ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode)
{
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("set_dma_mode: bad channel 0x%x\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
p_dma_ch->mode = mode;
return DMA_STATUS_GOOD;
}
/*
* Sets the DMA Count register. Note that 'count' is in bytes.
* However, the DMA Count register counts the number of "transfers",
* where each transfer is equal to the bus width. Thus, count
* MUST be a multiple of the bus width.
*/
void
ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count)
{
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
#ifdef DEBUG_4xxDMA
{
int error = 0;
switch (p_dma_ch->pwidth) {
case PW_8:
break;
case PW_16:
if (count & 0x1)
error = 1;
break;
case PW_32:
if (count & 0x3)
error = 1;
break;
case PW_64:
if (count & 0x7)
error = 1;
break;
default:
printk("set_dma_count: invalid bus width: 0x%x\n",
p_dma_ch->pwidth);
return;
}
if (error)
printk
("Warning: set_dma_count count 0x%x bus width %d\n",
count, p_dma_ch->pwidth);
}
#endif
count = count >> p_dma_ch->shift;
mtdcr(DCRN_DMACT0 + (dmanr * 0x8), count);
}
/*
* Returns the number of bytes left to be transferred.
* After a DMA transfer, this should return zero.
* Reading this while a DMA transfer is still in progress will return
* unpredictable results.
*/
int
ppc4xx_get_dma_residue(unsigned int dmanr)
{
unsigned int count;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_get_dma_residue: bad channel 0x%x\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
count = mfdcr(DCRN_DMACT0 + (dmanr * 0x8));
return (count << p_dma_ch->shift);
}
/*
* Sets the DMA address for a memory to peripheral or peripheral
* to memory transfer. The address is just saved in the channel
* structure for now and used later in enable_dma().
*/
void
ppc4xx_set_dma_addr(unsigned int dmanr, phys_addr_t addr)
{
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_set_dma_addr: bad channel: %d\n", dmanr);
return;
}
#ifdef DEBUG_4xxDMA
{
int error = 0;
switch (p_dma_ch->pwidth) {
case PW_8:
break;
case PW_16:
if ((unsigned) addr & 0x1)
error = 1;
break;
case PW_32:
if ((unsigned) addr & 0x3)
error = 1;
break;
case PW_64:
if ((unsigned) addr & 0x7)
error = 1;
break;
default:
printk("ppc4xx_set_dma_addr: invalid bus width: 0x%x\n",
p_dma_ch->pwidth);
return;
}
if (error)
printk("Warning: ppc4xx_set_dma_addr addr 0x%x bus width %d\n",
addr, p_dma_ch->pwidth);
}
#endif
/* save dma address and program it later after we know the xfer mode */
p_dma_ch->addr = addr;
}
/*
* Sets both DMA addresses for a memory to memory transfer.
* For memory to peripheral or peripheral to memory transfers
* the function set_dma_addr() should be used instead.
*/
void
ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
phys_addr_t dst_dma_addr)
{
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_set_dma_addr2: bad channel: %d\n", dmanr);
return;
}
#ifdef DEBUG_4xxDMA
{
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
int error = 0;
switch (p_dma_ch->pwidth) {
case PW_8:
break;
case PW_16:
if (((unsigned) src_dma_addr & 0x1) ||
((unsigned) dst_dma_addr & 0x1)
)
error = 1;
break;
case PW_32:
if (((unsigned) src_dma_addr & 0x3) ||
((unsigned) dst_dma_addr & 0x3)
)
error = 1;
break;
case PW_64:
if (((unsigned) src_dma_addr & 0x7) ||
((unsigned) dst_dma_addr & 0x7)
)
error = 1;
break;
default:
printk("ppc4xx_set_dma_addr2: invalid bus width: 0x%x\n",
p_dma_ch->pwidth);
return;
}
if (error)
printk
("Warning: ppc4xx_set_dma_addr2 src 0x%x dst 0x%x bus width %d\n",
src_dma_addr, dst_dma_addr, p_dma_ch->pwidth);
}
#endif
ppc4xx_set_src_addr(dmanr, src_dma_addr);
ppc4xx_set_dst_addr(dmanr, dst_dma_addr);
}
/*
* Enables the channel interrupt.
*
* If performing a scatter/gatter transfer, this function
* MUST be called before calling alloc_dma_handle() and building
* the sgl list. Otherwise, interrupts will not be enabled, if
* they were previously disabled.
*/
int
ppc4xx_enable_dma_interrupt(unsigned int dmanr)
{
unsigned int control;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_enable_dma_interrupt: bad channel: %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
p_dma_ch->int_enable = 1;
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
control |= DMA_CIE_ENABLE; /* Channel Interrupt Enable */
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
return DMA_STATUS_GOOD;
}
/*
* Disables the channel interrupt.
*
* If performing a scatter/gatter transfer, this function
* MUST be called before calling alloc_dma_handle() and building
* the sgl list. Otherwise, interrupts will not be disabled, if
* they were previously enabled.
*/
int
ppc4xx_disable_dma_interrupt(unsigned int dmanr)
{
unsigned int control;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_disable_dma_interrupt: bad channel: %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
p_dma_ch->int_enable = 0;
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
control &= ~DMA_CIE_ENABLE; /* Channel Interrupt Enable */
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
return DMA_STATUS_GOOD;
}
/*
* Configures a DMA channel, including the peripheral bus width, if a
* peripheral is attached to the channel, the polarity of the DMAReq and
* DMAAck signals, etc. This information should really be setup by the boot
* code, since most likely the configuration won't change dynamically.
* If the kernel has to call this function, it's recommended that it's
* called from platform specific init code. The driver should not need to
* call this function.
*/
int
ppc4xx_init_dma_channel(unsigned int dmanr, ppc_dma_ch_t * p_init)
{
unsigned int polarity;
uint32_t control = 0;
ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr];
DMA_MODE_READ = (unsigned long) DMA_TD; /* Peripheral to Memory */
DMA_MODE_WRITE = 0; /* Memory to Peripheral */
if (!p_init) {
printk("ppc4xx_init_dma_channel: NULL p_init\n");
return DMA_STATUS_NULL_POINTER;
}
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_init_dma_channel: bad channel %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
#if DCRN_POL > 0
polarity = mfdcr(DCRN_POL);
#else
polarity = 0;
#endif
/* Setup the control register based on the values passed to
* us in p_init. Then, over-write the control register with this
* new value.
*/
control |= SET_DMA_CONTROL;
/* clear all polarity signals and then "or" in new signal levels */
polarity &= ~GET_DMA_POLARITY(dmanr);
polarity |= p_init->polarity;
#if DCRN_POL > 0
mtdcr(DCRN_POL, polarity);
#endif
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
/* save these values in our dma channel structure */
memcpy(p_dma_ch, p_init, sizeof (ppc_dma_ch_t));
/*
* The peripheral width values written in the control register are:
* PW_8 0
* PW_16 1
* PW_32 2
* PW_64 3
*
* Since the DMA count register takes the number of "transfers",
* we need to divide the count sent to us in certain
* functions by the appropriate number. It so happens that our
* right shift value is equal to the peripheral width value.
*/
p_dma_ch->shift = p_init->pwidth;
/*
* Save the control word for easy access.
*/
p_dma_ch->control = control;
mtdcr(DCRN_DMASR, 0xffffffff); /* clear status register */
return DMA_STATUS_GOOD;
}
/*
* This function returns the channel configuration.
*/
int
ppc4xx_get_channel_config(unsigned int dmanr, ppc_dma_ch_t * p_dma_ch)
{
unsigned int polarity;
unsigned int control;
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_get_channel_config: bad channel %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
memcpy(p_dma_ch, &dma_channels[dmanr], sizeof (ppc_dma_ch_t));
#if DCRN_POL > 0
polarity = mfdcr(DCRN_POL);
#else
polarity = 0;
#endif
p_dma_ch->polarity = polarity & GET_DMA_POLARITY(dmanr);
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
p_dma_ch->cp = GET_DMA_PRIORITY(control);
p_dma_ch->pwidth = GET_DMA_PW(control);
p_dma_ch->psc = GET_DMA_PSC(control);
p_dma_ch->pwc = GET_DMA_PWC(control);
p_dma_ch->phc = GET_DMA_PHC(control);
p_dma_ch->ce = GET_DMA_CE_ENABLE(control);
p_dma_ch->int_enable = GET_DMA_CIE_ENABLE(control);
p_dma_ch->shift = GET_DMA_PW(control);
#ifdef CONFIG_PPC4xx_EDMA
p_dma_ch->pf = GET_DMA_PREFETCH(control);
#else
p_dma_ch->ch_enable = GET_DMA_CH(control);
p_dma_ch->ece_enable = GET_DMA_ECE(control);
p_dma_ch->tcd_disable = GET_DMA_TCD(control);
#endif
return DMA_STATUS_GOOD;
}
/*
* Sets the priority for the DMA channel dmanr.
* Since this is setup by the hardware init function, this function
* can be used to dynamically change the priority of a channel.
*
* Acceptable priorities:
*
* PRIORITY_LOW
* PRIORITY_MID_LOW
* PRIORITY_MID_HIGH
* PRIORITY_HIGH
*
*/
int
ppc4xx_set_channel_priority(unsigned int dmanr, unsigned int priority)
{
unsigned int control;
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_set_channel_priority: bad channel %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
if ((priority != PRIORITY_LOW) &&
(priority != PRIORITY_MID_LOW) &&
(priority != PRIORITY_MID_HIGH) && (priority != PRIORITY_HIGH)) {
printk("ppc4xx_set_channel_priority: bad priority: 0x%x\n", priority);
}
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
control |= SET_DMA_PRIORITY(priority);
mtdcr(DCRN_DMACR0 + (dmanr * 0x8), control);
return DMA_STATUS_GOOD;
}
/*
* Returns the width of the peripheral attached to this channel. This assumes
* that someone who knows the hardware configuration, boot code or some other
* init code, already set the width.
*
* The return value is one of:
* PW_8
* PW_16
* PW_32
* PW_64
*
* The function returns 0 on error.
*/
unsigned int
ppc4xx_get_peripheral_width(unsigned int dmanr)
{
unsigned int control;
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk("ppc4xx_get_peripheral_width: bad channel %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
control = mfdcr(DCRN_DMACR0 + (dmanr * 0x8));
return (GET_DMA_PW(control));
}
/*
* Clears the channel status bits
*/
int
ppc4xx_clr_dma_status(unsigned int dmanr)
{
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk(KERN_ERR "ppc4xx_clr_dma_status: bad channel: %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
mtdcr(DCRN_DMASR, ((u32)DMA_CH0_ERR | (u32)DMA_CS0 | (u32)DMA_TS0) >> dmanr);
return DMA_STATUS_GOOD;
}
#ifdef CONFIG_PPC4xx_EDMA
/*
* Enables the burst on the channel (BTEN bit in the control/count register)
* Note:
* For scatter/gather dma, this function MUST be called before the
* ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
* sgl list and used as each sgl element is added.
*/
int
ppc4xx_enable_burst(unsigned int dmanr)
{
unsigned int ctc;
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk(KERN_ERR "ppc4xx_enable_burst: bad channel: %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) | DMA_CTC_BTEN;
mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
return DMA_STATUS_GOOD;
}
/*
* Disables the burst on the channel (BTEN bit in the control/count register)
* Note:
* For scatter/gather dma, this function MUST be called before the
* ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
* sgl list and used as each sgl element is added.
*/
int
ppc4xx_disable_burst(unsigned int dmanr)
{
unsigned int ctc;
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk(KERN_ERR "ppc4xx_disable_burst: bad channel: %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BTEN;
mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
return DMA_STATUS_GOOD;
}
/*
* Sets the burst size (number of peripheral widths) for the channel
* (BSIZ bits in the control/count register))
* must be one of:
* DMA_CTC_BSIZ_2
* DMA_CTC_BSIZ_4
* DMA_CTC_BSIZ_8
* DMA_CTC_BSIZ_16
* Note:
* For scatter/gather dma, this function MUST be called before the
* ppc4xx_alloc_dma_handle() func as the chan count register is copied into the
* sgl list and used as each sgl element is added.
*/
int
ppc4xx_set_burst_size(unsigned int dmanr, unsigned int bsize)
{
unsigned int ctc;
if (dmanr >= MAX_PPC4xx_DMA_CHANNELS) {
printk(KERN_ERR "ppc4xx_set_burst_size: bad channel: %d\n", dmanr);
return DMA_STATUS_BAD_CHANNEL;
}
ctc = mfdcr(DCRN_DMACT0 + (dmanr * 0x8)) &~ DMA_CTC_BSIZ_MSK;
ctc |= (bsize & DMA_CTC_BSIZ_MSK);
mtdcr(DCRN_DMACT0 + (dmanr * 0x8), ctc);
return DMA_STATUS_GOOD;
}
EXPORT_SYMBOL(ppc4xx_enable_burst);
EXPORT_SYMBOL(ppc4xx_disable_burst);
EXPORT_SYMBOL(ppc4xx_set_burst_size);
#endif /* CONFIG_PPC4xx_EDMA */
EXPORT_SYMBOL(ppc4xx_init_dma_channel);
EXPORT_SYMBOL(ppc4xx_get_channel_config);
EXPORT_SYMBOL(ppc4xx_set_channel_priority);
EXPORT_SYMBOL(ppc4xx_get_peripheral_width);
EXPORT_SYMBOL(dma_channels);
EXPORT_SYMBOL(ppc4xx_set_src_addr);
EXPORT_SYMBOL(ppc4xx_set_dst_addr);
EXPORT_SYMBOL(ppc4xx_set_dma_addr);
EXPORT_SYMBOL(ppc4xx_set_dma_addr2);
EXPORT_SYMBOL(ppc4xx_enable_dma);
EXPORT_SYMBOL(ppc4xx_disable_dma);
EXPORT_SYMBOL(ppc4xx_set_dma_mode);
EXPORT_SYMBOL(ppc4xx_set_dma_count);
EXPORT_SYMBOL(ppc4xx_get_dma_residue);
EXPORT_SYMBOL(ppc4xx_enable_dma_interrupt);
EXPORT_SYMBOL(ppc4xx_disable_dma_interrupt);
EXPORT_SYMBOL(ppc4xx_get_dma_status);
EXPORT_SYMBOL(ppc4xx_clr_dma_status);
[-- Attachment #3: dcr-native.h --]
[-- Type: application/octet-stream, Size: 3320 bytes --]
/*
* (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
* <benh@kernel.crashing.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
* the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _ASM_POWERPC_DCR_NATIVE_H
#define _ASM_POWERPC_DCR_NATIVE_H
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
#include <linux/spinlock.h>
typedef struct {
unsigned int base;
} dcr_host_t;
#define DCR_MAP_OK(host) (1)
#define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) })
#define dcr_unmap(host, dcr_c) do {} while (0)
#define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base)
#define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
/* Device Control Registers */
void __mtdcr(int reg, unsigned int val);
unsigned int __mfdcr(int reg);
#define mfdcr(rn) \
({unsigned int rval; \
if (__builtin_constant_p(rn)) \
asm volatile("mfdcr %0," __stringify(rn) \
: "=r" (rval)); \
else \
rval = __mfdcr(rn); \
rval;})
#define mtdcr(rn, v) \
do { \
if (__builtin_constant_p(rn)) \
asm volatile("mtdcr " __stringify(rn) ",%0" \
: : "r" (v)); \
else \
__mtdcr(rn, v); \
} while (0)
/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
extern spinlock_t dcr_ind_lock;
static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
{
unsigned long flags;
unsigned int val;
spin_lock_irqsave(&dcr_ind_lock, flags);
__mtdcr(base_addr, reg);
val = __mfdcr(base_data);
spin_unlock_irqrestore(&dcr_ind_lock, flags);
return val;
}
static inline void __mtdcri(int base_addr, int base_data, int reg,
unsigned val)
{
unsigned long flags;
spin_lock_irqsave(&dcr_ind_lock, flags);
__mtdcr(base_addr, reg);
__mtdcr(base_data, val);
spin_unlock_irqrestore(&dcr_ind_lock, flags);
}
static inline void __dcri_clrset(int base_addr, int base_data, int reg,
unsigned clr, unsigned set)
{
unsigned long flags;
unsigned int val;
spin_lock_irqsave(&dcr_ind_lock, flags);
__mtdcr(base_addr, reg);
val = (__mfdcr(base_data) & ~clr) | set;
__mtdcr(base_data, val);
spin_unlock_irqrestore(&dcr_ind_lock, flags);
}
#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
DCRN_ ## base ## _CONFIG_DATA, \
reg)
#define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
DCRN_ ## base ## _CONFIG_DATA, \
reg, data)
#define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
DCRN_ ## base ## _CONFIG_DATA, \
reg, clr, set)
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_DCR_NATIVE_H */
[-- Attachment #4: dcr.h --]
[-- Type: application/octet-stream, Size: 6308 bytes --]
#ifndef _PPC_BOOT_DCR_H_
#define _PPC_BOOT_DCR_H_
#define mfdcr(rn) \
({ \
unsigned long rval; \
asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
rval; \
})
#define mtdcr(rn, val) \
asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
/* 440GP/440GX SDRAM controller DCRs */
#define DCRN_SDRAM0_CFGADDR 0x010
#define DCRN_SDRAM0_CFGDATA 0x011
#define SDRAM0_READ(offset) ({\
mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
mfdcr(DCRN_SDRAM0_CFGDATA); })
#define SDRAM0_WRITE(offset, data) ({\
mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
mtdcr(DCRN_SDRAM0_CFGDATA, data); })
#define SDRAM0_B0CR 0x40
#define SDRAM0_B1CR 0x44
#define SDRAM0_B2CR 0x48
#define SDRAM0_B3CR 0x4c
static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
SDRAM0_B2CR, SDRAM0_B3CR };
#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
#define SDRAM_CONFIG_BANK_SIZE(reg) \
(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
/* 440GP External Bus Controller (EBC) */
#define DCRN_EBC0_CFGADDR 0x012
#define DCRN_EBC0_CFGDATA 0x013
#define EBC_NUM_BANKS 8
#define EBC_B0CR 0x00
#define EBC_B1CR 0x01
#define EBC_B2CR 0x02
#define EBC_B3CR 0x03
#define EBC_B4CR 0x04
#define EBC_B5CR 0x05
#define EBC_B6CR 0x06
#define EBC_B7CR 0x07
#define EBC_BXCR(n) (n)
#define EBC_BXCR_BAS 0xfff00000
#define EBC_BXCR_BS 0x000e0000
#define EBC_BXCR_BANK_SIZE(reg) \
(0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
#define EBC_BXCR_BU 0x00018000
#define EBC_BXCR_BU_OFF 0x00000000
#define EBC_BXCR_BU_RO 0x00008000
#define EBC_BXCR_BU_WO 0x00010000
#define EBC_BXCR_BU_RW 0x00018000
#define EBC_BXCR_BW 0x00006000
#define EBC_B0AP 0x10
#define EBC_B1AP 0x11
#define EBC_B2AP 0x12
#define EBC_B3AP 0x13
#define EBC_B4AP 0x14
#define EBC_B5AP 0x15
#define EBC_B6AP 0x16
#define EBC_B7AP 0x17
#define EBC_BXAP(n) (0x10+(n))
#define EBC_BEAR 0x20
#define EBC_BESR 0x21
#define EBC_CFG 0x23
#define EBC_CID 0x24
/* 440GP Clock, PM, chip control */
#define DCRN_CPC0_SR 0x0b0
#define DCRN_CPC0_ER 0x0b1
#define DCRN_CPC0_FR 0x0b2
#define DCRN_CPC0_SYS0 0x0e0
#define CPC0_SYS0_TUNE 0xffc00000
#define CPC0_SYS0_FBDV_MASK 0x003c0000
#define CPC0_SYS0_FWDVA_MASK 0x00038000
#define CPC0_SYS0_FWDVB_MASK 0x00007000
#define CPC0_SYS0_OPDV_MASK 0x00000c00
#define CPC0_SYS0_EPDV_MASK 0x00000300
/* Helper macros to compute the actual clock divider values from the
* encodings in the CPC0 register */
#define CPC0_SYS0_FBDV(reg) \
((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
#define CPC0_SYS0_FWDVA(reg) \
(8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
#define CPC0_SYS0_FWDVB(reg) \
(8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
#define CPC0_SYS0_OPDV(reg) \
((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
#define CPC0_SYS0_EPDV(reg) \
((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
#define CPC0_SYS0_EXTSL 0x00000080
#define CPC0_SYS0_RW_MASK 0x00000060
#define CPC0_SYS0_RL 0x00000010
#define CPC0_SYS0_ZMIISL_MASK 0x0000000c
#define CPC0_SYS0_BYPASS 0x00000002
#define CPC0_SYS0_NTO1 0x00000001
#define DCRN_CPC0_SYS1 0x0e1
#define DCRN_CPC0_CUST0 0x0e2
#define DCRN_CPC0_CUST1 0x0e3
#define DCRN_CPC0_STRP0 0x0e4
#define DCRN_CPC0_STRP1 0x0e5
#define DCRN_CPC0_STRP2 0x0e6
#define DCRN_CPC0_STRP3 0x0e7
#define DCRN_CPC0_GPIO 0x0e8
#define DCRN_CPC0_PLB 0x0e9
#define DCRN_CPC0_CR1 0x0ea
#define DCRN_CPC0_CR0 0x0eb
#define CPC0_CR0_SWE 0x80000000
#define CPC0_CR0_CETE 0x40000000
#define CPC0_CR0_U1FCS 0x20000000
#define CPC0_CR0_U0DTE 0x10000000
#define CPC0_CR0_U0DRE 0x08000000
#define CPC0_CR0_U0DC 0x04000000
#define CPC0_CR0_U1DTE 0x02000000
#define CPC0_CR0_U1DRE 0x01000000
#define CPC0_CR0_U1DC 0x00800000
#define CPC0_CR0_U0EC 0x00400000
#define CPC0_CR0_U1EC 0x00200000
#define CPC0_CR0_UDIV_MASK 0x001f0000
#define CPC0_CR0_UDIV(reg) \
((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
#define DCRN_CPC0_MIRQ0 0x0ec
#define DCRN_CPC0_MIRQ1 0x0ed
#define DCRN_CPC0_JTAGID 0x0ef
#define DCRN_MAL0_CFG 0x180
#define MAL_RESET 0x80000000
/* 440EP Clock/Power-on Reset regs */
#define DCRN_CPR0_ADDR 0xc
#define DCRN_CPR0_DATA 0xd
#define CPR0_PLLD0 0x60
#define CPR0_OPBD0 0xc0
#define CPR0_PERD0 0xe0
#define CPR0_PRIMBD0 0xa0
#define CPR0_SCPID 0x120
#define CPR0_PLLC0 0x40
/* 405GP Clocking/Power Management/Chip Control regs */
#define DCRN_CPC0_PLLMR 0xb0
#define DCRN_405_CPC0_CR0 0xb1
#define DCRN_405_CPC0_CR1 0xb2
#define DCRN_405_CPC0_PSR 0xb4
/* 405EP Clocking/Power Management/Chip Control regs */
#define DCRN_CPC0_PLLMR0 0xf0
#define DCRN_CPC0_PLLMR1 0xf4
#define DCRN_CPC0_UCR 0xf5
/* 440GX Clock control etc */
#define DCRN_CPR0_CLKUPD 0x020
#define DCRN_CPR0_PLLC 0x040
#define DCRN_CPR0_PLLD 0x060
#define DCRN_CPR0_PRIMAD 0x080
#define DCRN_CPR0_PRIMBD 0x0a0
#define DCRN_CPR0_OPBD 0x0c0
#define DCRN_CPR0_PERD 0x0e0
#define DCRN_CPR0_MALD 0x100
#define DCRN_SDR0_CONFIG_ADDR 0xe
#define DCRN_SDR0_CONFIG_DATA 0xf
/* SDR read/write helper macros */
#define SDR0_READ(offset) ({\
mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
mfdcr(DCRN_SDR0_CONFIG_DATA); })
#define SDR0_WRITE(offset, data) ({\
mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
#define DCRN_SDR0_UART0 0x0120
#define DCRN_SDR0_UART1 0x0121
#define DCRN_SDR0_UART2 0x0122
#define DCRN_SDR0_UART3 0x0123
/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
#define DCRN_CPR0_CFGADDR 0xc
#define DCRN_CPR0_CFGDATA 0xd
#define CPR0_READ(offset) ({\
mtdcr(DCRN_CPR0_CFGADDR, offset); \
mfdcr(DCRN_CPR0_CFGDATA); })
#define CPR0_WRITE(offset, data) ({\
mtdcr(DCRN_CPR0_CFGADDR, offset); \
mtdcr(DCRN_CPR0_CFGDATA, data); })
#endif /* _PPC_BOOT_DCR_H_ */
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