* Re: powerpc: Move 64bit heap above 1TB on machines with 1TB segments
From: David Gibson @ 2009-09-23 0:03 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Mel Gorman, Anton Blanchard
In-Reply-To: <1253653702.7103.244.camel@pasglop>
On Wed, Sep 23, 2009 at 07:08:22AM +1000, Benjamin Herrenschmidt wrote:
>
> > Unfortunately, I am not sensitive to issues surrounding 1TB segments or how
> > they are currently being used. However, as this clearly helps performance
> > for large amounts of memory, is it worth providing an option to
> > libhugetlbfs to locate 16MB pages above 1TB when they are otherwise being
> > unused?
>
> AFAIK, that is already the case, at least the kernel will hand out pages
> above 1T preferentially iirc.
>
> There were talks about making huge pages below 1T not even come up
> untily you ask for them with MAP_FIXED, dunno where that went.
That was already the case as far as I remember. But it's just
possible that changed when the general slice handling code came in,
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 2/6] mtd: m25p80: Convert to device table matching
From: Andrew Morton @ 2009-09-23 0:02 UTC (permalink / raw)
To: avorontsov
Cc: ben, linux-kernel, lm-sensors, david-b, linuxppc-dev, linux-mtd,
khali, dwmw2
In-Reply-To: <20090922235534.GA3796@oksana.dev.rtsoft.ru>
On Wed, 23 Sep 2009 03:55:34 +0400
Anton Vorontsov <cbouatmailru@gmail.com> wrote:
> On Tue, Sep 22, 2009 at 04:43:47PM -0700, David Woodhouse wrote:
> > On Wed, 2009-09-23 at 03:01 +0400, Anton Vorontsov wrote:
> > >
> > > And the two patches I sent on top:
> > >
> > > http://lkml.org/lkml/2009/8/18/364
> > > http://lkml.org/lkml/2009/8/18/366
> >
> > Got versions of those which apply to the mtd-2.6.git tree (which I'm
> > about to ask Linus to pull)?
>
> I'd love to, but they depend on a bunch of SPI patches that are still
> in -mm tree.
oh, is that why I queued them up where I did. Sigh.
> As soon as SPI core changes hit Linus' tree, I think
> Andrew will send all m25p80 patches to you anyway.
Or David can ack them and I'll send 'em up.
^ permalink raw reply
* GPIO driver for MPC8313.
From: Johnny Hung @ 2009-09-23 3:55 UTC (permalink / raw)
To: linuxppc-dev, linux-embedded
Hi All:
=A0 =A0Is there a alreday written GPIO dirver or example for
MPC8313/similar ppc platform. It looks like many people need GPIO
dirver to control LED, etc... I think is it possible to write a
general gpio driver for all ppc platform and only need to modify gpio
iomap information of dtb file. Please give me a advice. Thanks in
advanced.
BRs, H. Johnny
^ permalink raw reply
* [PATCH] powerpc/mm: Fix 40x and 8xx vs. _PAGE_SPECIAL
From: Benjamin Herrenschmidt @ 2009-09-23 4:12 UTC (permalink / raw)
To: Weirich, Bernhard, Rex Feany; +Cc: linuxppc-dev list
The test to check whether we have _PAGE_SPECIAL defined is broken,
since we always define it, just not always to a meaninful value :-)
That broke 8xx and 40x under some circumstances.
This fixes it by adding _PAGE_SPECIAL for both of these since they
had a free PTE bit, and removing the condition around advertising
it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Bernhard, Rex, please let me know if that works for you.
diff --git a/arch/powerpc/include/asm/pte-40x.h b/arch/powerpc/include/asm/pte-40x.h
index 6c3e1f4..ec0b0b0 100644
--- a/arch/powerpc/include/asm/pte-40x.h
+++ b/arch/powerpc/include/asm/pte-40x.h
@@ -43,6 +43,7 @@
#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
+#define _PAGE_SPECIAL 0x020 /* software: Special page */
#define _PAGE_RW 0x040 /* software: Writes permitted */
#define _PAGE_DIRTY 0x080 /* software: dirty page */
#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index 94e9797..dd5ea95 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -32,6 +32,7 @@
#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
+#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
/* These five software bits must be masked out when the entry is loaded
* into the TLB.
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index c3b6507..f2b3701 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -25,9 +25,6 @@
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU 0
#endif
-#ifndef _PAGE_SPECIAL
-#define _PAGE_SPECIAL 0
-#endif
#ifndef _PAGE_4K_PFN
#define _PAGE_4K_PFN 0
#endif
@@ -179,7 +176,5 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define HAVE_PAGE_AGP
/* Advertise support for _PAGE_SPECIAL */
-#ifdef _PAGE_SPECIAL
#define __HAVE_ARCH_PTE_SPECIAL
-#endif
^ permalink raw reply related
* Re: NAND ECC Error with wrong SMC ording bug
From: Stefan Roese @ 2009-09-23 5:12 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linuxppc-dev, Sean MacLennan
In-Reply-To: <20090922172049.1a639b22@lappy.seanm.ca>
On Tuesday 22 September 2009 23:20:49 Sean MacLennan wrote:
> What is the status of this bug?
I've noticed that David pulled in into his repo. So I expect it to hit
mainline in this merge window.
Cheers,
Stefan
^ permalink raw reply
* Re: GPIO driver for MPC8313.
From: Peter Korsgaard @ 2009-09-23 6:57 UTC (permalink / raw)
To: Johnny Hung; +Cc: linuxppc-dev, linux-embedded
In-Reply-To: <cb9ecdfa0909222055x1d691698sb516b5b8f5f81d@mail.gmail.com>
>>>>> "Johnny" =3D=3D Johnny Hung <johnny.hacking@gmail.com> writes:
Johnny> Hi All:
Johnny> =C2=A0 =C2=A0Is there a alreday written GPIO dirver or example for
Johnny> MPC8313/similar ppc platform. It looks like many people need GPIO
Johnny> dirver to control LED, etc... I think is it possible to write a
Johnny> general gpio driver for all ppc platform and only need to modify g=
pio
Johnny> iomap information of dtb file. Please give me a advice. Thanks in
Johnny> advanced.
Sure, it's arch/powerpc/sysdev/mpc8xxx_gpio.c, included since 2.6.28. To
use it, simply enable CONFIG_MPC8xxx_GPIO and add a gpio-controller node
to your dts, similar to how it's done in
arch/powerpc/boot/dts/mpc837*_rdb.dts.
See Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt for details of
the dts bindings.
--=20
Bye, Peter Korsgaard
^ permalink raw reply
* Re: 2.6.31-git5 kernel boot hangs on powerpc
From: Sachin Sant @ 2009-09-23 8:23 UTC (permalink / raw)
To: Tejun Heo; +Cc: Linux/PPC Development, David Miller
In-Reply-To: <4AB49C37.6020003@in.ibm.com>
Sachin Sant wrote:
> Sachin Sant wrote:
>> Tejun Heo wrote:
>>> Ah... sorry about that. Sachin, is it possible for you to build the
>>> kernel with debug info and ask gdb where the stalling NIP is in the c
>>> file?
>>>
>> <6>NET: Registered protocol family 10
>> <3>BUG: soft lockup - CPU#2 stuck for 61s! [modprobe:1865]
>> <4>Modules linked in: ipv6(+) fuse loop dm_mod sg sd_mod crc_t10dif
>> ibmvscsic scsi_transport_srp scsi_tgt scsi_mod
>> <4>NIP: c00000000004198c LR: c00000000015dac8 CTR: 0000000000000040
>> <4>REGS: c0000000fbdbb6f0 TRAP: 0901 Not tainted (2.6.31-git5)
>> <4>MSR: 8000000000009032 <EE,ME,IR,DR> CR: 44224420 XER: 20000001
>> <4>TASK = c0000000fbd57840[1865] 'modprobe' THREAD: c0000000fbdb8000
>> CPU: 2
>> <4>GPR00: 0000000000000040 c0000000fbdbb970 c000000000a96d08
>> d00007fffff00000
>> <4>GPR04: 0000000000000000 0000000000000000 d00007fffff00000
>> d00007fffff00000
>> <4>GPR08: 0000000000000000 c000000001020180 c000000000b6b4e8
>> 00000000000003c0
>> <4>GPR12: 0000000048224428 c000000000b82a00
>> <4>NIP [c00000000004198c] .memset+0x60/0xfc
>> <4>LR [c00000000015dac8] .pcpu_alloc+0x758/0x960
>> <4>Call Trace:
>> <4>[c0000000fbdbb970] [c00000000015da58] .pcpu_alloc+0x6e8/0x960
>> (unreliable)
>> <4>[c0000000fbdbba90] [c000000000565664] .snmp_mib_init+0x34/0x9c
>> <4>[c0000000fbdbbb20] [d00000000212e130] .ipv6_add_dev+0x1cc/0x3dc
>> [ipv6]
>> <4>[c0000000fbdbbbc0] [d0000000021598ac] .addrconf_init+0x6c/0x194
>> [ipv6]
>> <4>[c0000000fbdbbc50] [d00000000215967c] .inet6_init+0x1bc/0x34c [ipv6]
>> <4>[c0000000fbdbbce0] [c0000000000097a4] .do_one_initcall+0x88/0x1bc
>> <4>[c0000000fbdbbd90] [c0000000000c84dc] .SyS_init_module+0x11c/0x29c
>> <4>[c0000000fbdbbe30] [c0000000000085b4] syscall_exit+0x0/0x40
>> <4>Instruction dump:
>> <4>98860000 38c60001 409e000c b0860000 38c60002 409d000c 90860000
>> 38c60004
>> <4>78a0d183 78a506a0 7c0903a6 4182002c <f8860000> f8860008 f8860010
>> f8860018
> Latest git (2.6.31-git9:78f28b7c555359c67c2a0d23f7436e915329421e)
> still has this bug.
One workaround i have found for this problem is to disable IPv6.
With IPv6 disabled the machine boots OK. Till a reliable solution
is available for this issue, i will keep IPv6 disabled in my configs.
Thanks
-Sachin
>
>
--
---------------------------------
Sachin Sant
IBM Linux Technology Center
India Systems and Technology Labs
Bangalore, India
---------------------------------
^ permalink raw reply
* Re: 2.6.31-git5 kernel boot hangs on powerpc
From: Tejun Heo @ 2009-09-23 8:34 UTC (permalink / raw)
To: Sachin Sant; +Cc: Linux/PPC Development, David Miller
In-Reply-To: <4AB9DAEC.3060309@in.ibm.com>
Sachin Sant wrote:
> Sachin Sant wrote:
>> Sachin Sant wrote:
>>> Tejun Heo wrote:
>>>> Ah... sorry about that. Sachin, is it possible for you to build the
>>>> kernel with debug info and ask gdb where the stalling NIP is in the c
>>>> file?
>>>>
>>> <6>NET: Registered protocol family 10
>>> <3>BUG: soft lockup - CPU#2 stuck for 61s! [modprobe:1865]
>>> <4>Modules linked in: ipv6(+) fuse loop dm_mod sg sd_mod crc_t10dif
>>> ibmvscsic scsi_transport_srp scsi_tgt scsi_mod
>>> <4>NIP: c00000000004198c LR: c00000000015dac8 CTR: 0000000000000040
>>> <4>REGS: c0000000fbdbb6f0 TRAP: 0901 Not tainted (2.6.31-git5)
>>> <4>MSR: 8000000000009032 <EE,ME,IR,DR> CR: 44224420 XER: 20000001
>>> <4>TASK = c0000000fbd57840[1865] 'modprobe' THREAD: c0000000fbdb8000
>>> CPU: 2
>>> <4>GPR00: 0000000000000040 c0000000fbdbb970 c000000000a96d08
>>> d00007fffff00000
>>> <4>GPR04: 0000000000000000 0000000000000000 d00007fffff00000
>>> d00007fffff00000
>>> <4>GPR08: 0000000000000000 c000000001020180 c000000000b6b4e8
>>> 00000000000003c0
>>> <4>GPR12: 0000000048224428 c000000000b82a00
>>> <4>NIP [c00000000004198c] .memset+0x60/0xfc
>>> <4>LR [c00000000015dac8] .pcpu_alloc+0x758/0x960
>>> <4>Call Trace:
>>> <4>[c0000000fbdbb970] [c00000000015da58] .pcpu_alloc+0x6e8/0x960
>>> (unreliable)
>>> <4>[c0000000fbdbba90] [c000000000565664] .snmp_mib_init+0x34/0x9c
>>> <4>[c0000000fbdbbb20] [d00000000212e130] .ipv6_add_dev+0x1cc/0x3dc
>>> [ipv6]
>>> <4>[c0000000fbdbbbc0] [d0000000021598ac] .addrconf_init+0x6c/0x194
>>> [ipv6]
>>> <4>[c0000000fbdbbc50] [d00000000215967c] .inet6_init+0x1bc/0x34c [ipv6]
>>> <4>[c0000000fbdbbce0] [c0000000000097a4] .do_one_initcall+0x88/0x1bc
>>> <4>[c0000000fbdbbd90] [c0000000000c84dc] .SyS_init_module+0x11c/0x29c
>>> <4>[c0000000fbdbbe30] [c0000000000085b4] syscall_exit+0x0/0x40
>>> <4>Instruction dump:
>>> <4>98860000 38c60001 409e000c b0860000 38c60002 409d000c 90860000
>>> 38c60004
>>> <4>78a0d183 78a506a0 7c0903a6 4182002c <f8860000> f8860008 f8860010
>>> f8860018
>> Latest git (2.6.31-git9:78f28b7c555359c67c2a0d23f7436e915329421e)
>> still has this bug.
> One workaround i have found for this problem is to disable IPv6.
> With IPv6 disabled the machine boots OK. Till a reliable solution
> is available for this issue, i will keep IPv6 disabled in my configs.
I'm think it's most likely caused by some code accessing invalid
percpu address. I'm currently writing up access validator. Should be
done in several hours. So, ipv6 it is. I couldn't reproduce your
problem here. I'll give ipv6 a shot.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH] powerpc/mm: Fix 40x and 8xx vs. _PAGE_SPECIAL
From: Weirich, Bernhard @ 2009-09-23 6:44 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list
In-Reply-To: <1253679146.7103.270.camel@pasglop>
Works perfectly here. Thank you for the patch, I was not feeling confident =
enough to play around with the page bits :)
Bernhard WEIRICH
Software Development
________________________________________
Von: Benjamin Herrenschmidt [benh@kernel.crashing.org]
Gesendet: Mittwoch, 23. September 2009 06:12
An: Weirich, Bernhard; Rex Feany
Cc: linuxppc-dev list
Betreff: [PATCH] powerpc/mm: Fix 40x and 8xx vs. _PAGE_SPECIAL
The test to check whether we have _PAGE_SPECIAL defined is broken,
since we always define it, just not always to a meaninful value :-)
That broke 8xx and 40x under some circumstances.
This fixes it by adding _PAGE_SPECIAL for both of these since they
had a free PTE bit, and removing the condition around advertising
it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Bernhard, Rex, please let me know if that works for you.
diff --git a/arch/powerpc/include/asm/pte-40x.h b/arch/powerpc/include/asm/=
pte-40x.h
index 6c3e1f4..ec0b0b0 100644
--- a/arch/powerpc/include/asm/pte-40x.h
+++ b/arch/powerpc/include/asm/pte-40x.h
@@ -43,6 +43,7 @@
#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
#define _PAGE_USER 0x010 /* matches one of the zone permissi=
on bits */
+#define _PAGE_SPECIAL 0x020 /* software: Special page */
#define _PAGE_RW 0x040 /* software: Writes permitted */
#define _PAGE_DIRTY 0x080 /* software: dirty page */
#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception *=
/
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/=
pte-8xx.h
index 94e9797..dd5ea95 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -32,6 +32,7 @@
#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
+#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
/* These five software bits must be masked out when the entry is loaded
* into the TLB.
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/a=
sm/pte-common.h
index c3b6507..f2b3701 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -25,9 +25,6 @@
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU 0
#endif
-#ifndef _PAGE_SPECIAL
-#define _PAGE_SPECIAL 0
-#endif
#ifndef _PAGE_4K_PFN
#define _PAGE_4K_PFN 0
#endif
@@ -179,7 +176,5 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define HAVE_PAGE_AGP
/* Advertise support for _PAGE_SPECIAL */
-#ifdef _PAGE_SPECIAL
#define __HAVE_ARCH_PTE_SPECIAL
-#endif
^ permalink raw reply related
* [PATCH 1/6] sdhci: Enable cache snooping
From: Gao Guanhua @ 2009-09-23 9:08 UTC (permalink / raw)
To: sdhci-devel; +Cc: linuxppc-dev, Gao Guanhua
This patch enable cache snooping when the sdhc is initialized.
---
drivers/mmc/host/sdhci.c | 3 +++
drivers/mmc/host/sdhci.h | 4 ++++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 288e40b..cc6d45c 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -178,6 +178,9 @@ static void sdhci_init(struct sdhci_host *host)
{
sdhci_reset(host, SDHCI_RESET_ALL);
+ /* Enable cache snooping */
+ sdhci_writel(host, SDHCI_CACHE_SNOOP, SDHCI_HOST_DMA_CONTROL);
+
sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index afda7f1..9ee9622 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -176,6 +176,10 @@
#define SDHCI_SPEC_100 0
#define SDHCI_SPEC_200 1
+/* 40C DMA control register*/
+#define SDHCI_HOST_DMA_CONTROL 0x40C
+#define SDHCI_CACHE_SNOOP 0x40
+
struct sdhci_ops;
struct sdhci_host {
--
1.6.4
^ permalink raw reply related
* [PATCH 2/6] P2020DS: Add sdhc support
From: Gao Guanhua @ 2009-09-23 9:08 UTC (permalink / raw)
To: sdhci-devel; +Cc: linuxppc-dev, Gao Guanhua
In-Reply-To: <1253696892-15262-1-git-send-email-B22826@freescale.com>
---
arch/powerpc/boot/dts/p2020ds.dts | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 8c1c954..be449ba 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -454,6 +454,14 @@
phy-connection-type = "rgmii-id";
};
+ sdhci@2e000 {
+ compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ clock-frequency = <0>;
+ };
+
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
--
1.6.4
^ permalink raw reply related
* [PATCH 3/6] P2020DS: Fixup sdhc to use PIO mode
From: Gao Guanhua @ 2009-09-23 9:08 UTC (permalink / raw)
To: sdhci-devel; +Cc: linuxppc-dev, Gao Guanhua
In-Reply-To: <1253696892-15262-2-git-send-email-B22826@freescale.com>
The SDHC can not work on DMA mode because of the hardware bug,
so we set a broken dma flag and use PIO mode. This patch applies
to Rev1.0.
---
arch/powerpc/boot/dts/p2020ds.dts | 1 +
drivers/mmc/host/sdhci-of.c | 3 +++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index be449ba..574ad4f 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -459,6 +459,7 @@
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
+ fsl,sdhci-dma-broken;
clock-frequency = <0>;
};
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 01ab916..5879483 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -270,6 +270,9 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
if (sdhci_of_wp_inverted(np))
host->quirks |= SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
+ if (of_get_property(np, "fsl,sdhci-dma-broken", NULL))
+ host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
+
clk = of_get_property(np, "clock-frequency", &size);
if (clk && size == sizeof(*clk) && *clk)
of_host->clock = *clk;
--
1.6.4
^ permalink raw reply related
* [PATCH 4/6] sdhci: Fixup AHB2MAG IRQ bypass hardware workaround
From: Gao Guanhua @ 2009-09-23 9:08 UTC (permalink / raw)
To: sdhci-devel; +Cc: linuxppc-dev, Gao Guanhua
In-Reply-To: <1253696892-15262-3-git-send-email-B22826@freescale.com>
This patch implemnet the workaround that the bit
DCR[DMA__AHB2MAG_IRQ_BYPASS] cannot be set automatically
when SoC reset.
---
arch/powerpc/boot/dts/p2020ds.dts | 1 +
drivers/mmc/host/sdhci-of.c | 5 ++++-
drivers/mmc/host/sdhci.c | 8 ++++++++
drivers/mmc/host/sdhci.h | 3 +++
4 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 574ad4f..8b1056d 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -460,6 +460,7 @@
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
fsl,sdhci-dma-broken;
+ fsl,sdhci-ahb2mag-irq-bypass;
clock-frequency = <0>;
};
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 5879483..0bc75b3 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -272,6 +272,9 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
if (of_get_property(np, "fsl,sdhci-dma-broken", NULL))
host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
+
+ if (of_get_property(np, "fsl,sdhci-ahb2mag-irq-bypass", NULL))
+ host->quirks |= SDHCI_QUIRK_SET_AHB2MAG_IRQ_BYPASS;
clk = of_get_property(np, "clock-frequency", &size);
if (clk && size == sizeof(*clk) && *clk)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index cc6d45c..711cbcd 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -176,11 +176,19 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
static void sdhci_init(struct sdhci_host *host)
{
+ u32 ctrl;
+
sdhci_reset(host, SDHCI_RESET_ALL);
/* Enable cache snooping */
sdhci_writel(host, SDHCI_CACHE_SNOOP, SDHCI_HOST_DMA_CONTROL);
+ if (host->quirks & SDHCI_QUIRK_SET_AHB2MAG_IRQ_BYPASS) {
+ ctrl = sdhci_readl(host, SDHCI_HOST_DMA_CONTROL);
+ ctrl |= SDHCI_AHB2MAG_IRQ_BYPASS;
+ sdhci_writel(host, ctrl, SDHCI_HOST_DMA_CONTROL);
+ }
+
sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 9ee9622..cb8beea 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -178,6 +178,7 @@
/* 40C DMA control register*/
#define SDHCI_HOST_DMA_CONTROL 0x40C
+#define SDHCI_AHB2MAG_IRQ_BYPASS 0x20
#define SDHCI_CACHE_SNOOP 0x40
struct sdhci_ops;
@@ -238,6 +239,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
/* Controller uses SDCLK instead of TMCLK for data timeouts */
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
+/* Controller cannot set DCR[DMA__AHB2MAG_IRQ_BYPASS] automatically*/
+#define SDHCI_QUIRK_SET_AHB2MAG_IRQ_BYPASS (1<<25)
int irq; /* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
1.6.4
^ permalink raw reply related
* [PATCH 5/6] sdhci-of: Set the timeout to the max value
From: Gao Guanhua @ 2009-09-23 9:08 UTC (permalink / raw)
To: sdhci-devel; +Cc: linuxppc-dev, Gao Guanhua
In-Reply-To: <1253696892-15262-4-git-send-email-B22826@freescale.com>
When access the card, the following error is reported:
mmc0: Got data interrupt 0x00000020 even though no data operation was in progress.
mmc0: Got data interrupt 0x00000020 even though no data operation was in progress.
so we skip the calculation of timeout and use the max value.
---
arch/powerpc/boot/dts/p2020ds.dts | 1 +
drivers/mmc/host/sdhci-of.c | 3 +++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 8b1056d..29989fb 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -461,6 +461,7 @@
interrupt-parent = <&mpic>;
fsl,sdhci-dma-broken;
fsl,sdhci-ahb2mag-irq-bypass;
+ fsl,sdhci-adjust-timeout;
clock-frequency = <0>;
};
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 0bc75b3..0ff95d8 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -276,6 +276,9 @@ static int __devinit sdhci_of_probe(struct of_device *ofdev,
if (of_get_property(np, "fsl,sdhci-ahb2mag-irq-bypass", NULL))
host->quirks |= SDHCI_QUIRK_SET_AHB2MAG_IRQ_BYPASS;
+ if (of_get_property(np, "fsl,sdhci-adjust-timeout", NULL))
+ host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+
clk = of_get_property(np, "clock-frequency", &size);
if (clk && size == sizeof(*clk) && *clk)
of_host->clock = *clk;
--
1.6.4
^ permalink raw reply related
* [PATCH 6/6] P2020DS: Remove sdhci-dma-broken and sdhci-ahb2mag-irq-bypass properties
From: Gao Guanhua @ 2009-09-23 9:08 UTC (permalink / raw)
To: sdhci-devel; +Cc: linuxppc-dev, Gao Guanhua
In-Reply-To: <1253696892-15262-5-git-send-email-B22826@freescale.com>
The SDHC on P2020DS board use DMA mode by default.
This patch remove the properties used in PIO mode.
---
arch/powerpc/boot/dts/p2020ds.dts | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 29989fb..3263397 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -459,8 +459,6 @@
reg = <0x2e000 0x1000>;
interrupts = <72 0x2>;
interrupt-parent = <&mpic>;
- fsl,sdhci-dma-broken;
- fsl,sdhci-ahb2mag-irq-bypass;
fsl,sdhci-adjust-timeout;
clock-frequency = <0>;
};
--
1.6.4
^ permalink raw reply related
* Re: PCI HotPlug and Adding Resources after Linux Boots
From: Benjamin Herrenschmidt @ 2009-09-23 9:42 UTC (permalink / raw)
To: Morrison, Tom; +Cc: linuxppc-dev@ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <80955630EE34634AB5030FB8CE9BDCEFD7459DF2@EXBEDCLST.empirix.com>
On Tue, 2009-09-22 at 15:36 -0400, Morrison, Tom wrote:
> I am not exactly sure who to direct this question to (general Linux
> kernel or LinuxPPC),
PCI Hotplug is reasonably arch specific at the moment so I suppose
here's is as good as anywhere else to ask :-)
> so I am directing to both – in hopes that someone will recognize this
> problem – and perhaps
>
> give me some suggestions on how to proceed…
There's a few things you can do, though I don't have time just right now
to give you a detailed answer. I'll try again later.
In the meantime, some of the answers could be around not using full
automatic resource assignment, but instead, pre-initializing the top
bridge with some resources that are going to be enough for the device.
You can also try to get the bridge to re-allocate. There's various funky
locking issues with doing that though as long as it's during boot time,
it's not too much of a problem.
There are other more or less hackish ways to do it, but I'll have to
give it more thought.
I'm quite stretched at the moment so if you don't hear back from me in
the upcoming few days, don't hesitate to ping me again.
Cheers,
Ben.
>
> I am running Linux (2.6.23x (and 2.6.27.x)) on a MPC8572 based system.
>
>
>
> I have an 8616 switch that has a Port (6) connected to a FPGA that is
>
> NOT loaded at before Linux boots (note: this port is configured for
> HOTPLUG
>
> events - which we do get after FPGA is loaded). We are NOT using a
>
> static device tree map (because the devices in the system are very
> dynamic).
>
>
> We use instead the pci auto scan mechanism(s) to scan/assign
> resources
>
> (including into the BAR registers) at bootup to all of the devices
> that are
>
> attached to this MPC8572…
>
>
>
> Here is the port that is attached to the device (note: there are NO
>
> resources assigned at this point this port):
>
>
>
> -------------------------------------------------------------------------------------------------
>
> 02:06.0 PCI bridge: PLX Technology, Inc.: Unknown device 8616 (rev bb)
> (prog-if 00 [Normal decode])
>
> Flags: bus master, fast devsel, latency 0
>
> Bus: primary=02, secondary=05, subordinate=05, sec-latency=0
>
> Capabilities: [40] Power Management version 3
>
> Capabilities: [48] Message Signalled Interrupts: 64bit+
> Queue=0/2 Enable+
>
> Capabilities: [68] #10 [0162]
>
> Capabilities: [a4] #0d [0000]
>
>
>
> root@slave7 ~ # lspci -t
>
> -+-[01]---00.0-[02-05]--+-01.0
>
> | +-04.0-[03]--
>
> | +-05.0-[04]--
>
> | \-06.0-[05]—
>
>
>
> -------------------------------------------------------------------------------------------------
>
>
>
> Later, after I detect there is an FPGA to load - I load it. At
> completion of the
>
> loading of the FPGA - the 8616 detects the FPGA – and creates a
> HotPlug
>
> event that the PCI Express HotPlug Driver handles:
>
> -------------------------------------------------------------------------------------------------
>
>
>
> root@slave7 ~ # pciehp: pcie_isr: intr_loc 8
>
> pciehp: pciehp: Presence/Notify input change.
>
> pciehp: Card present on Slot(0005_0070)
>
> pciehp: Surprise Removal
>
> pciehp: hpc_get_power_status: SLOTCTRL 80 value read 8
>
> pciehp: hpc_get_attention_status: SLOTCTRL 80, value read 8
>
> pciehp: board_added: slot device, slot offset, hp slot = 0, 0 ,0
>
> pciehp: hpc_check_lnk_status: lnk_status = 2021
>
> PCI: Found 0000:05:00.0 [1172/0004] 00ff00 00
>
> PCI: Calling quirk c0012d3c for 0000:05:00.0
>
> program_fw_provided_values: Could not get hotplug parameters
>
> entering assign resources (size: 2000000)
>
> PCI: Failed to allocate mem resource #0:2000000@0 for 0000:05:00.0
>
> bus pci: add device 0000:05:00.0
>
> entering uevent
>
> pci: Trying to Match Device 0000:05:00.0 with Driver pcieport-driver
>
> pci: Trying to Match Device 0000:05:00.0 with Driver serial
>
> pci: Trying to Match Device 0000:05:00.0 with Driver pexntb
>
> pciehp: hpc_get_power_status: SLOTCTRL 80 value read 8
>
> pciehp: hpc_get_attention_status: SLOTCTRL 80, value read 8
>
>
>
> 02:06.0 PCI bridge: PLX Technology, Inc.: Unknown device 8616 (rev bb)
> (prog-if 00 [Normal decode])
>
> Flags: bus master, fast devsel, latency 0
>
> Bus: primary=02, secondary=05, subordinate=05, sec-latency=0
>
> Capabilities: [40] Power Management version 3
>
> Capabilities: [48] Message Signalled Interrupts: 64bit+
> Queue=0/2 Enable+
>
> Capabilities: [68] #10 [0162]
>
> Capabilities: [a4] #0d [0000]
>
>
>
> 05:00.0 Class ff00: Altera Corporation: Unknown device 0004 (rev 01)
>
> Subsystem: Altera Corporation: Unknown device 0004
>
> Flags: fast devsel
>
> Capabilities: [50] Message Signalled Interrupts: 64bit+
> Queue=0/5 Enable-
>
> Capabilities: [78] Power Management version 3
>
> Capabilities: [80] #10 [0001]
>
>
>
> root@slave7 ~ # lspci -t
>
> -+-[01]---00.0-[02-05]--+-01.0
>
> | +-04.0-[03]--
>
> | +-05.0-[04]--
>
> | \-06.0-[05]----00.0
>
> \-[00]---00.0
>
>
>
> -------------------------------------------------------------------------------------------------
>
>
>
> So, as you can see – the device has been read – and it requires 32M of
> resources, but
>
> because its parent doesn’t have any resources allocated – it seemingly
> can’t allocate and
>
> use any additional resources.
>
>
>
> How do I ‘customize’ and/or add resources at this point for this
> device (using semi-standard mechanisms)?
>
>
>
> Thanks in advance for any/all ideas…
>
>
>
>
>
> I
>
>
>
> Tom Morrison
> Principal Software Engineer
>
> EMPIRIX
> 20 Crosby Drive - Bedford, MA 01730
> p: 781.266.3567 f: 781.266.3670
> email: tmorrison@empirix.com
> www.empirix.com
>
>
>
>
>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: GPIO driver for MPC8313.
From: Johnny Hung @ 2009-09-23 10:52 UTC (permalink / raw)
To: Peter Korsgaard; +Cc: linuxppc-dev, linux-embedded
In-Reply-To: <87y6o6rvvc.fsf@macbook.be.48ers.dk>
Thanks, got it. BTW, how to trigger GPIO level in user space
application? I also found arch/powerpc/platforms/52xx/mpc52xx_gpio.c
is a good example. Any reply is appreciate.
BRs, H. Johnny
2009/9/23 Peter Korsgaard <jacmet@sunsite.dk>:
>>>>>> "Johnny" =3D=3D Johnny Hung <johnny.hacking@gmail.com> writes:
>
> =A0Johnny> Hi All:
> =A0Johnny> =A0 =A0Is there a alreday written GPIO dirver or example for
> =A0Johnny> MPC8313/similar ppc platform. It looks like many people need G=
PIO
> =A0Johnny> dirver to control LED, etc... I think is it possible to write =
a
> =A0Johnny> general gpio driver for all ppc platform and only need to modi=
fy gpio
> =A0Johnny> iomap information of dtb file. Please give me a advice. Thanks=
in
> =A0Johnny> advanced.
>
> Sure, it's arch/powerpc/sysdev/mpc8xxx_gpio.c, included since 2.6.28. To
> use it, simply enable CONFIG_MPC8xxx_GPIO and add a gpio-controller node
> to your dts, similar to how it's done in
> arch/powerpc/boot/dts/mpc837*_rdb.dts.
>
> See Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt for details of
> the dts bindings.
>
> --
> Bye, Peter Korsgaard
>
^ permalink raw reply
* 2.6.31: powerpc build errors with include/linux/perf_counter.h
From: Mahajan Vivek-B08308 @ 2009-09-23 11:05 UTC (permalink / raw)
To: linuxppc-dev; +Cc: markus.t.metzger
[-- Attachment #1: Type: text/plain, Size: 1070 bytes --]
Hello Markus,
Apparently this
http://git.kernel.org/?p=linux/kernel/git/benh/powerpc.git;a=commitdiff;
h=5622f295b53fb60dbf9bed3e2c89d182490a8b7f breaks the powerpc build as
under when built from
http://git.kernel.org/?p=linux/kernel/git/benh/powerpc.git;a=summary
with latest commit ebc79c4f8da0f92efa968e0328f32334a2ce80cf
cc1: warnings being treated as errors
In file included from arch/powerpc/kernel/irq.c:56:
include/linux/perf_counter.h: In function 'perf_output_begin':
include/linux/perf_counter.h:854: warning: no return statement in
function returning non-void
include/linux/perf_counter.h: At top level:
include/linux/perf_counter.h:863: warning: 'struct perf_sample_data'
declared inside parameter list
include/linux/perf_counter.h:863: warning: its scope is only this
definition or declaration, which is probably not what
include/linux/perf_counter.h:868: warning: 'struct perf_sample_data'
declared inside parameter list
make[1]: *** [arch/powerpc/kernel/irq.o] Error 1
make: *** [arch/powerpc/kernel] Error 2
Thanks,
Vivek
[-- Attachment #2: Type: text/html, Size: 2193 bytes --]
^ permalink raw reply
* Re: GPIO driver for MPC8313.
From: Peter Korsgaard @ 2009-09-23 11:04 UTC (permalink / raw)
To: Johnny Hung; +Cc: linuxppc-dev, linux-embedded
In-Reply-To: <cb9ecdfa0909230352w77a37f59h3c7f1e146121f9f6@mail.gmail.com>
>>>>> "Johnny" == Johnny Hung <johnny.hacking@gmail.com> writes:
Johnny> Thanks, got it. BTW, how to trigger GPIO level in user space
Johnny> application? I also found
Johnny> arch/powerpc/platforms/52xx/mpc52xx_gpio.c is a good
Johnny> example. Any reply is appreciate.
Through sysfs. See 'Sysfs Interface for Userspace' section of
Documentation/gpio.txt
--
Bye, Peter Korsgaard
^ permalink raw reply
* RE: 2.6.31: powerpc build errors with include/linux/perf_counter.h
From: Metzger, Markus T @ 2009-09-23 11:10 UTC (permalink / raw)
To: Mahajan Vivek-B08308, linuxppc-dev@ozlabs.org
In-Reply-To: <F2F605B667B24B489C904986E0D60A08FF6167@zin33exm23.fsl.freescale.net>
Hi Vivek,
The build errors have been fixed with commit cd74c86bdf705f824d494a2bbda393=
d1d562b40a.
thanks and regards,
markus.
From: Mahajan Vivek-B08308 [mailto:Vivek.Mahajan@freescale.com]=20
Sent: Wednesday, September 23, 2009 1:05 PM
To: linuxppc-dev@ozlabs.org
Cc: Metzger, Markus T
Subject: 2.6.31: powerpc build errors with include/linux/perf_counter.h
Hello Markus,
=A0
Apparently this http://git.kernel.org/?p=3Dlinux/kernel/git/benh/powerpc.gi=
t;a=3Dcommitdiff;h=3D5622f295b53fb60dbf9bed3e2c89d182490a8b7f=A0breaks the =
powerpc build as under when built from http://git.kernel.org/?p=3Dlinux/ker=
nel/git/benh/powerpc.git;a=3Dsummary=A0with latest commit=A0ebc79c4f8da0f92=
efa968e0328f32334a2ce80cf
=A0
cc1: warnings being treated as errors
In file included from arch/powerpc/kernel/irq.c:56:
include/linux/perf_counter.h: In function 'perf_output_begin':
include/linux/perf_counter.h:854: warning: no return statement in function =
returning non-void
include/linux/perf_counter.h: At top level:
include/linux/perf_counter.h:863: warning: 'struct perf_sample_data' declar=
ed inside parameter list
include/linux/perf_counter.h:863: warning: its scope is only this definitio=
n or declaration, which is probably not what
include/linux/perf_counter.h:868: warning: 'struct perf_sample_data' declar=
ed inside parameter list
make[1]: *** [arch/powerpc/kernel/irq.o] Error 1
make: *** [arch/powerpc/kernel] Error 2
Thanks,
Vivek
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^ permalink raw reply
* [PATCH 1/4] powerpc/fsl: 85xx: document cache-sram size as a kernel parametric option
From: Vivek Mahajan @ 2009-09-23 11:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kumar.gala, Vivek Mahajan
Adds documentation for the size parameter of Freescale's QorIQ
based cache-sram
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
Documentation/kernel-parameters.txt | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 0f17d16..3213844 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -412,6 +412,9 @@ and is between 256 and 4096 characters. It is defined in the file
c101= [NET] Moxa C101 synchronous serial card
+ cache-sram-size= [PPC] Size of Freescale's QorIQ Cache SRAM
+ See Documentation/powerpc/fsl_85xx_cache_sram.txt.
+
cachesize= [BUGS=X86-32] Override level 2 CPU cache size detection.
Sometimes CPU hardware bugs make them report the cache
size incorrectly. The kernel will attempt work arounds
--
1.5.6.5
^ permalink raw reply related
* [PATCH 2/4] powerpc/fsl: 85xx: document cache-sram
From: Vivek Mahajan @ 2009-09-23 11:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kumar.gala, Vivek Mahajan
In-Reply-To: <1253705604-1986-1-git-send-email-vivek.mahajan@freescale.com>
Adds documentation for Freescale's QorIQ based cache-sram as under:-
* How to enable it from a low level driver
* How to set its size
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
Documentation/powerpc/fsl_85xx_cache_sram.txt | 31 +++++++++++++++++++++++++
1 files changed, 31 insertions(+), 0 deletions(-)
create mode 100644 Documentation/powerpc/fsl_85xx_cache_sram.txt
diff --git a/Documentation/powerpc/fsl_85xx_cache_sram.txt b/Documentation/powerpc/fsl_85xx_cache_sram.txt
new file mode 100644
index 0000000..628607d
--- /dev/null
+++ b/Documentation/powerpc/fsl_85xx_cache_sram.txt
@@ -0,0 +1,31 @@
+* Freescale QorIQ based Cache SRAM
+
+Freescale's QorIQ platforms provide an option of configuring
+a part of (or full) cache memory as SRAM. Any low level
+driver can use its APIs via selecting FSL_85XX_CACHE_SRAM as
+under for the case of gianfar ethernet driver:-
+
+In drivers/net/Kconfig:-
+
+config GIANFAR
+ ....
+ select FSL_85XX_CACHE_SRAM if MPC85xx
+ ....
+
+FSL_85XX_CACHE_SRAM and its base address are defined in
+arch/powerpc/sysdev/Kconfig as under:-
+
+config FSL_85XX_CACHE_SRAM
+ bool
+ select PPC_LIB_RHEAP
+
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default "0xfff00000"
+
+The size of the above cache SRAM memory window is passed via the
+kernel command line as <cache-sram-size=....>
+
+Absence of the above parameter in the kernel command line is
+treated as no cache SRAM.
--
1.5.6.5
^ permalink raw reply related
* [PATCH 3/4] powerpc/fsl: 85xx: add mbar()
From: Vivek Mahajan @ 2009-09-23 11:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kumar.gala, Vivek Mahajan
In-Reply-To: <1253705604-1986-2-git-send-email-vivek.mahajan@freescale.com>
Adds e500/85xx based memory barrier
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
arch/powerpc/include/asm/synch.h | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
index 28f6ddb..8298089 100644
--- a/arch/powerpc/include/asm/synch.h
+++ b/arch/powerpc/include/asm/synch.h
@@ -23,6 +23,11 @@ static inline void isync(void)
{
__asm__ __volatile__ ("isync" : : : "memory");
}
+
+static inline void mbar(int mo)
+{
+ __asm__ __volatile__ ("mbar %0" : : "i" (mo) : "memory");
+}
#endif /* __ASSEMBLY__ */
#if defined(__powerpc64__)
--
1.5.6.5
^ permalink raw reply related
* [PATCH 4/4] powerpc/fsl: 85xx: add cache-sram support
From: Vivek Mahajan @ 2009-09-23 11:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kumar.gala, Vivek Mahajan
In-Reply-To: <1253705604-1986-3-git-send-email-vivek.mahajan@freescale.com>
This adds QorIQ based Cache-SRAM support as under:-
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Defines FSL_85XX_CACHE_SRAM and its base address
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
arch/powerpc/include/asm/fsl_85xx_cache_sram.h | 48 ++++++
arch/powerpc/platforms/85xx/Kconfig | 9 ++
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h | 95 ++++++++++++
arch/powerpc/sysdev/fsl_85xx_cache_sram.c | 141 ++++++++++++++++++
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 184 ++++++++++++++++++++++++
6 files changed, 478 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_85xx_cache_sram.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_sram.c
create mode 100644 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
diff --git a/arch/powerpc/include/asm/fsl_85xx_cache_sram.h b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
new file mode 100644
index 0000000..2af2bdc
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Cache SRAM handling for QorIQ platform
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+
+ * This file is derived from the original work done
+ * by Sylvain Munaut for the Bestcomm SRAM allocator.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+
+#include <asm/rheap.h>
+#include <linux/spinlock.h>
+
+/*
+ * Cache-SRAM
+ */
+
+struct mpc85xx_cache_sram {
+ phys_addr_t base_phys;
+ void *base_virt;
+ unsigned int size;
+ rh_info_t *rh;
+ spinlock_t lock;
+};
+
+extern void mpc85xx_cache_sram_free(void *ptr);
+extern void *mpc85xx_cache_sram_alloc(unsigned int size,
+ phys_addr_t *phys, unsigned int align);
+
+#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d3a975e..b6f23c3 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -144,6 +144,15 @@ config SBC8560
help
This option enables support for the Wind River SBC8560 board
+config FSL_85XX_CACHE_SRAM
+ bool
+ select PPC_LIB_RHEAP
+
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default "0xfff00000"
+
endif # MPC85xx
config TQM85xx
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 9d4b174..745994c 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
+obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
obj-$(CONFIG_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
new file mode 100644
index 0000000..8c4a4ac
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc
+ *
+ * QorIQ based Cache Controller Memory Mapped Registers
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __FSL_85XX_CACHE_CTLR_H__
+#define __FSL_85XX_CACHE_CTLR_H__
+
+#define L2CR_L2FI 0x40000000 /* L2 flash invalidate */
+#define L2CR_L2IO 0x00200000 /* L2 instruction only */
+#define L2CR_SRAM_ZERO 0x00000000 /* L2SRAM zero size */
+#define L2CR_SRAM_FULL 0x00010000 /* L2SRAM full size */
+#define L2CR_SRAM_HALF 0x00020000 /* L2SRAM half size */
+#define L2CR_SRAM_TWO_HALFS 0x00030000 /* L2SRAM two half sizes */
+#define L2CR_SRAM_QUART 0x00040000 /* L2SRAM one quarter size */
+#define L2CR_SRAM_TWO_QUARTS 0x00050000 /* L2SRAM two quarter size */
+#define L2CR_SRAM_EIGHTH 0x00060000 /* L2SRAM one eighth size */
+#define L2CR_SRAM_TWO_EIGHTH 0x00070000 /* L2SRAM two eighth size */
+
+#define L2SRAM_OPTIMAL_SZ_SHIFT 0x00000003 /* Optimum size for L2SRAM */
+
+#define L2SRAM_BAR_MSK_LO18 0xFFFFC000 /* Lower 18 bits */
+#define L2SRAM_BARE_MSK_HI4 0x0000000F /* Upper 4 bits */
+
+enum cache_sram_lock_ways {
+ LOCK_WAYS_ZERO,
+ LOCK_WAYS_EIGHTH,
+ LOCK_WAYS_TWO_EIGHTH,
+ LOCK_WAYS_HALF = 4,
+ LOCK_WAYS_FULL = 8,
+};
+
+struct mpc85xx_l2ctlr {
+ u32 ctl; /* 0x000 - L2 control */
+ u8 res1[0xC];
+ u32 ewar0; /* 0x010 - External write address 0 */
+ u32 ewarea0; /* 0x014 - External write address extended 0 */
+ u32 ewcr0; /* 0x018 - External write ctrl */
+ u8 res2[4];
+ u32 ewar1; /* 0x020 - External write address 1 */
+ u32 ewarea1; /* 0x024 - External write address extended 1 */
+ u32 ewcr1; /* 0x028 - External write ctrl 1 */
+ u8 res3[4];
+ u32 ewar2; /* 0x030 - External write address 2 */
+ u32 ewarea2; /* 0x034 - External write address extended 2 */
+ u32 ewcr2; /* 0x038 - External write ctrl 2 */
+ u8 res4[4];
+ u32 ewar3; /* 0x040 - External write address 3 */
+ u32 ewarea3; /* 0x044 - External write address extended 3 */
+ u32 ewcr3; /* 0x048 - External write ctrl 3 */
+ u8 res5[0xB4];
+ u32 srbar0; /* 0x100 - SRAM base address 0 */
+ u32 srbarea0; /* 0x104 - SRAM base addr reg ext address 0 */
+ u32 srbar1; /* 0x108 - SRAM base address 1 */
+ u32 srbarea1; /* 0x10C - SRAM base addr reg ext address 1 */
+ u8 res6[0xCF0];
+ u32 errinjhi; /* 0xE00 - Error injection mask high */
+ u32 errinjlo; /* 0xE04 - Error injection mask low */
+ u32 errinjctl; /* 0xE08 - Error injection tag/ecc control */
+ u8 res7[0x14];
+ u32 captdatahi; /* 0xE20 - Error data high capture */
+ u32 captdatalo; /* 0xE24 - Error data low capture */
+ u32 captecc; /* 0xE28 - Error syndrome */
+ u8 res8[0x14];
+ u32 errdet; /* 0xE40 - Error detect */
+ u32 errdis; /* 0xE44 - Error disable */
+ u32 errinten; /* 0xE48 - Error interrupt enable */
+ u32 errattr; /* 0xE4c - Error attribute capture */
+ u32 erradrrl; /* 0xE50 - Error address capture low */
+ u32 erradrrh; /* 0xE54 - Error address capture high */
+ u32 errctl; /* 0xE58 - Error control */
+ u8 res9[0x1A4];
+};
+
+extern int instantiate_cache_sram(struct of_device *dev, unsigned int size);
+extern void remove_cache_sram(struct of_device *dev);
+
+#endif /* __FSL_85XX_CACHE_CTLR_H__ */
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
new file mode 100644
index 0000000..6744083
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Simple memory allocator abstraction for QorIQ (P1/P2) based Cache-SRAM
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+ *
+ * This file is derived from the original work done
+ * by Sylvain Munaut for the Bestcomm SRAM allocator.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <asm/pgtable.h>
+#include <asm/fsl_85xx_cache_sram.h>
+
+struct mpc85xx_cache_sram *cache_sram;
+
+void *mpc85xx_cache_sram_alloc(unsigned int size,
+ phys_addr_t *phys, unsigned int align)
+{
+ unsigned long offset;
+ unsigned long flags;
+
+ if (!size || (size > cache_sram->size) || (align > cache_sram->size)) {
+ pr_err("%s(): size(=%x) or align(=%x) zero or too big\n",
+ __func__, size, align);
+ return NULL;
+ }
+
+ if ((align & (align - 1)) || align <= 1) {
+ pr_err("%s(): align(=%x) must be power of two and >1\n",
+ __func__, align);
+ return NULL;
+ }
+
+ spin_lock_irqsave(&cache_sram->lock, flags);
+ offset = rh_alloc_align(cache_sram->rh, size, align, NULL);
+ spin_unlock_irqrestore(&cache_sram->lock, flags);
+
+ if (IS_ERR_VALUE(offset))
+ return NULL;
+
+ *phys = cache_sram->base_phys + offset;
+
+ return (unsigned char *)cache_sram->base_virt + offset;
+}
+EXPORT_SYMBOL(mpc85xx_cache_sram_alloc);
+
+void mpc85xx_cache_sram_free(void *ptr)
+{
+ unsigned long flags;
+ BUG_ON(!ptr);
+
+ spin_lock_irqsave(&cache_sram->lock, flags);
+ rh_free(cache_sram->rh, ptr - cache_sram->base_virt);
+ spin_unlock_irqrestore(&cache_sram->lock, flags);
+}
+EXPORT_SYMBOL(mpc85xx_cache_sram_free);
+
+int __init instantiate_cache_sram(struct of_device *dev, unsigned int size)
+{
+ if (cache_sram) {
+ dev_err(&dev->dev, "Already initialized cache-sram\n");
+ return -EBUSY;
+ }
+
+ cache_sram = kzalloc(sizeof(struct mpc85xx_cache_sram), GFP_KERNEL);
+ if (!cache_sram) {
+ dev_err(&dev->dev, "Out of memory for cache_sram structure\n");
+ return -ENOMEM;
+ }
+
+ cache_sram->base_phys = CONFIG_FSL_85XX_CACHE_SRAM_BASE;
+ cache_sram->size = size;
+
+ if (!request_mem_region(cache_sram->base_phys, cache_sram->size,
+ "fsl_85xx_cache_sram")) {
+ dev_err(&dev->dev, "%s: request memory failed\n",
+ dev->node->full_name);
+ kfree(cache_sram);
+ return -ENXIO;
+ }
+
+ cache_sram->base_virt = ioremap_flags(cache_sram->base_phys,
+ cache_sram->size, _PAGE_COHERENT | PAGE_KERNEL);
+ if (!cache_sram->base_virt) {
+ dev_err(&dev->dev, "%s: ioremap_flags failed\n",
+ dev->node->full_name);
+ release_mem_region(cache_sram->base_phys, cache_sram->size);
+ kfree(cache_sram);
+ return -ENOMEM;
+ }
+
+ cache_sram->rh = rh_create(sizeof(unsigned int));
+ if (IS_ERR(cache_sram->rh)) {
+ dev_err(&dev->dev, "%s: Unable to create remote heap\n",
+ dev->node->full_name);
+ iounmap(cache_sram->base_virt);
+ release_mem_region(cache_sram->base_phys, cache_sram->size);
+ kfree(cache_sram);
+ return PTR_ERR(cache_sram->rh);
+ }
+
+ rh_attach_region(cache_sram->rh, 0, cache_sram->size);
+ spin_lock_init(&cache_sram->lock);
+
+ dev_info(&dev->dev, "[base:0x%x, size:0x%x] configured and loaded\n",
+ cache_sram->base_phys, cache_sram->size);
+ return 0;
+}
+
+void remove_cache_sram(struct of_device *dev)
+{
+ BUG_ON(!cache_sram);
+
+ rh_detach_region(cache_sram->rh, 0, cache_sram->size);
+ rh_destroy(cache_sram->rh);
+
+ iounmap(cache_sram->base_virt);
+ release_mem_region(cache_sram->base_phys, cache_sram->size);
+
+ kfree(cache_sram);
+ cache_sram = NULL;
+
+ dev_info(&dev->dev, "MPC85xx Cache-SRAM driver unloaded\n");
+}
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
new file mode 100644
index 0000000..1d36971
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <asm/io.h>
+
+#include "fsl_85xx_cache_ctlr.h"
+
+static char *param;
+struct mpc85xx_l2ctlr __iomem *l2ctlr;
+
+static long get_cache_sram_size(void)
+{
+ unsigned long val;
+
+ if (!param || (strict_strtoul(param, 0, &val) < 0))
+ return -EINVAL;
+
+ return val;
+}
+
+static int __init get_cmdline_param(char *str)
+{
+ if (!str)
+ return 0;
+
+ param = str;
+ return 1;
+}
+
+__setup("cache-sram-size=", get_cmdline_param);
+
+static int __devinit mpc85xx_l2ctlr_of_probe(struct of_device *dev,
+ const struct of_device_id *match)
+{
+ long rval;
+ unsigned int rem;
+ unsigned char ways;
+ const unsigned int *prop;
+ unsigned int l2cache_size;
+ unsigned int sram_size;
+
+ if (!dev->node) {
+ dev_err(&dev->dev, "Device's OF-node is NULL\n");
+ return -EINVAL;
+ }
+
+ prop = of_get_property(dev->node, "cache-size", NULL);
+ if (!prop) {
+ dev_err(&dev->dev, "Missing L2 cache-size\n");
+ return -EINVAL;
+ }
+ l2cache_size = *prop;
+
+ rval = get_cache_sram_size();
+ if (rval <= 0) {
+ dev_err(&dev->dev,
+ "Entire L2 as cache, Aborting Cache-SRAM stuff\n");
+ return -EINVAL;
+ }
+
+ rem = l2cache_size % (unsigned int)rval;
+ ways = l2cache_size / (unsigned int)rval;
+ if (rem || (ways & (ways - 1))) {
+ dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
+ return -EINVAL;
+ }
+
+ sram_size = (unsigned int)rval;
+
+ l2ctlr = of_iomap(dev->node, 0);
+ if (!l2ctlr) {
+ dev_err(&dev->dev, "Can't map L2 controller\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Write bits[0-17] to srbar0
+ */
+ out_be32(&l2ctlr->srbar0,
+ CONFIG_FSL_85XX_CACHE_SRAM_BASE & L2SRAM_BAR_MSK_LO18);
+
+ /*
+ * Write bits[18-21] to srbare0
+ */
+ out_be32(&l2ctlr->srbarea0,
+ (CONFIG_FSL_85XX_CACHE_SRAM_BASE >> 10) & L2SRAM_BARE_MSK_HI4);
+
+ clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
+
+ switch (ways) {
+ case LOCK_WAYS_EIGHTH:
+ setbits32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
+ break;
+
+ case LOCK_WAYS_TWO_EIGHTH:
+ setbits32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_TWO_EIGHTH);
+ break;
+
+ case LOCK_WAYS_HALF:
+ setbits32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
+ break;
+
+ case LOCK_WAYS_FULL:
+ default:
+ setbits32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
+ break;
+ }
+ mbar(1);
+
+ rval = instantiate_cache_sram(dev, sram_size);
+ if (rval < 0) {
+ dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
+ iounmap(l2ctlr);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int __devexit mpc85xx_l2ctlr_of_remove(struct of_device *dev)
+{
+ BUG_ON(!l2ctlr);
+
+ iounmap(l2ctlr);
+ remove_cache_sram(dev);
+ dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
+
+ return 0;
+}
+
+static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
+ {
+ .compatible = "fsl,p2020-l2-cache-controller",
+ },
+ {},
+};
+
+static struct of_platform_driver mpc85xx_l2ctlr_of_platform_driver = {
+ .name = "fsl-l2ctlr",
+ .match_table = mpc85xx_l2ctlr_of_match,
+ .probe = mpc85xx_l2ctlr_of_probe,
+ .remove = __devexit_p(mpc85xx_l2ctlr_of_remove),
+};
+
+static __init int mpc85xx_l2ctlr_of_init(void)
+{
+ return of_register_platform_driver(&mpc85xx_l2ctlr_of_platform_driver);
+}
+
+static void __exit mpc85xx_l2ctlr_of_exit(void)
+{
+ of_unregister_platform_driver(&mpc85xx_l2ctlr_of_platform_driver);
+}
+
+subsys_initcall(mpc85xx_l2ctlr_of_init);
+module_exit(mpc85xx_l2ctlr_of_exit);
+
+MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
+MODULE_LICENSE("GPL v2");
--
1.5.6.5
^ permalink raw reply related
* Re: [PATCH 1/6] sdhci: Enable cache snooping
From: Anton Vorontsov @ 2009-09-23 11:52 UTC (permalink / raw)
To: Gao Guanhua; +Cc: linuxppc-dev, sdhci-devel
In-Reply-To: <1253696892-15262-1-git-send-email-B22826@freescale.com>
On Wed, Sep 23, 2009 at 05:08:07PM +0800, Gao Guanhua wrote:
> This patch enable cache snooping when the sdhc is initialized.
> ---
> drivers/mmc/host/sdhci.c | 3 +++
> drivers/mmc/host/sdhci.h | 4 ++++
> 2 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 288e40b..cc6d45c 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -178,6 +178,9 @@ static void sdhci_init(struct sdhci_host *host)
> {
> sdhci_reset(host, SDHCI_RESET_ALL);
>
> + /* Enable cache snooping */
> + sdhci_writel(host, SDHCI_CACHE_SNOOP, SDHCI_HOST_DMA_CONTROL);
> +
> sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
> SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
> SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index afda7f1..9ee9622 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -176,6 +176,10 @@
> #define SDHCI_SPEC_100 0
> #define SDHCI_SPEC_200 1
>
> +/* 40C DMA control register*/
> +#define SDHCI_HOST_DMA_CONTROL 0x40C
SDHCI Specification doesn't mention this register, it isn't standard.
Plus, we have this register and bit set already in sdhci-of.c:
static int esdhc_enable_dma(struct sdhci_host *host)
{
setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
return 0;
}
Do p2020 need this bit set for PIO mode too?
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
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