* Re: [PATCH 0/6] PowerPc 8xx TLB/MMU fixes
From: Joakim Tjernlund @ 2009-10-05 23:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <1254782248.7122.49.camel@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 06/10/2009 00:37:28:
>
> On Tue, 2009-10-06 at 00:31 +0200, Joakim Tjernlund wrote:
> >
> > regs or regs->nip is NULL? Either one does not make sense
> > In any case it might be a secondary problem as DAR is NULL already
> > when you
> > enter the page fault.
> > >
> > > insn = *((unsigned long *)regs->nip);
> > > c000e110: 80 a9 00 00 lwz r5,0(r9)
> > >
> > > fails.
> >
> > hmm, I wonder if you managed to invalidate the a kernel TLB?
> > Are you using pinned kernel TLBs?
>
> You should not dereference a user address like that. Use get_user !
So how does this look? Does it change anything?
It should as the previous way was way off :(
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index c33c6de..08a392f 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -153,7 +153,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
#ifdef DEBUG_DCBX
const char *istr = NULL;
- insn = *((unsigned long *)regs->nip);
+ __get_user(insn, (unsigned long __user *)regs->nip);
if (((insn >> (31-5)) & 0x3f) == 31) {
if (((insn >> 1) & 0x3ff) == 1014) /* dcbz ? 0x3f6 */
istr = "dcbz";
@@ -178,11 +178,12 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
ra, rb, dar);
is_write = 0;
}
-
+#if 0
if (trap == 0x300 && address != dar) {
__asm__ ("mtdar %0" : : "r" (dar));
return 0;
}
+#endif
}
}
#endif
@@ -191,7 +192,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
/* This is from a dcbX or icbi insn gone bad, these
* insn do not set DAR so we have to do it here instead */
- insn = *((unsigned long *)regs->nip);
+ __get_user(insn, (unsigned long __user *)regs->nip);
ra = (insn >> (31-15)) & 0x1f; /* Reg RA */
rb = (insn >> (31-20)) & 0x1f; /* Reg RB */
^ permalink raw reply related
* Re: [PATCH 3/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
From: Benjamin Herrenschmidt @ 2009-10-06 0:34 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <OFB8E4035A.83748CF0-ONC1257646.0080A097-C1257646.00819DD6@transmode.se>
On Tue, 2009-10-06 at 01:35 +0200, Joakim Tjernlund wrote:
>
> > Well, if the HW has the ability to enforce trap when store with !
> DIRTY,
>
> Yes, provided that the kernel invalidates the TLB too so the next
> access
> will provoke a TLB Miss, which will then provoke a TLB error. The TLB
> error routine checks VALID, RW and USER(if not a kernel access), then
> sets
> ACCESSED & DIRTY and writes the TLB(RPN reg).
>
> Perhaps the missing invalidate is haunting us here?
No, the kernel will invalidate when clearing dirty or accessed, I don't
think that's our problem.
This is still all inefficient, we end up basically with two traps.
8xx provides backup GPRs when doing TLB misses ? What does it cost to
jump out of a TLB miss back into "normal" context ?
IE. What I do on 440 is I set a mask of required bits, basically
_PAGE_PRESENT | _PAGE_ACCESSED is the base. The DTLB miss also sticks
in _PAGE_RW | _PAGE_DIRTY when it's a store fault.
Then, I andc. the PTE value off that mask, and if the result is non-0
(which means one of the required bits is missing), I get out of the TLB
miss immediately and go to the data (or instruction) access interrupt.
Once you've done that, you should be able to have data and instruction
access go straight to C. Missing _PAGE_ACCESSED and _PAGE_DIRTY are
going to be fixed up by generic code.
> > then that's fine, just map it that way, but you shouldn't have to
> handle
> > it in the DTLB error neither, the kernel will fix it up for you in
> > handle_pte_fault().
>
> Does not all ppc have the Changed bit?
No. BookE doesn't.
> Please do, get the mpc862 users manual :)
Ok :-)
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 0/6] PowerPc 8xx TLB/MMU fixes
From: Benjamin Herrenschmidt @ 2009-10-06 1:52 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <OF2DE63E1A.21EA8BF0-ONC1257646.0082A7F0-C1257646.0082E281@transmode.se>
\
> So how does this look? Does it change anything?
> It should as the previous way was way off :(
>
> diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
> index c33c6de..08a392f 100644
> --- a/arch/powerpc/mm/fault.c
> +++ b/arch/powerpc/mm/fault.c
> @@ -153,7 +153,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
> #ifdef DEBUG_DCBX
> const char *istr = NULL;
>
> - insn = *((unsigned long *)regs->nip);
> + __get_user(insn, (unsigned long __user *)regs->nip);
No, use get_user() not __get_user() or if you use the later, also use
access_ok(), and test the result in case it errors (if it does, you
probably want to just goto bad access and SEGV).
Cheers,
Ben.
> if (((insn >> (31-5)) & 0x3f) == 31) {
> if (((insn >> 1) & 0x3ff) == 1014) /* dcbz ? 0x3f6 */
> istr = "dcbz";
> @@ -178,11 +178,12 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
> ra, rb, dar);
> is_write = 0;
> }
> -
> +#if 0
> if (trap == 0x300 && address != dar) {
> __asm__ ("mtdar %0" : : "r" (dar));
> return 0;
> }
> +#endif
> }
> }
> #endif
> @@ -191,7 +192,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
>
> /* This is from a dcbX or icbi insn gone bad, these
> * insn do not set DAR so we have to do it here instead */
> - insn = *((unsigned long *)regs->nip);
> + __get_user(insn, (unsigned long __user *)regs->nip);
>
> ra = (insn >> (31-15)) & 0x1f; /* Reg RA */
> rb = (insn >> (31-20)) & 0x1f; /* Reg RB */
>
>
^ permalink raw reply
* [PATCH] powerpc: tracing: Add powerpc tracepoints for interrupt entry and exit
From: Anton Blanchard @ 2009-10-06 2:19 UTC (permalink / raw)
To: Steven Rostedt, Frederic Weisbecker, Ingo Molnar, benh; +Cc: linuxppc-dev
This patch adds powerpc specific tracepoints for interrupt entry and exit.
While we already have generic irq_handler_entry and irq_handler_exit
tracepoints there are cases on our virtualised powerpc machines where an
interrupt is presented to the OS, but subsequently handled by the hypervisor.
This means no OS interrupt handler is invoked.
Here is an example on a POWER6 machine with the patch below applied:
<idle>-0 [006] 3243.949840744: irq_entry: pt_regs=c0000000ce31fb10
<idle>-0 [006] 3243.949850520: irq_exit: pt_regs=c0000000ce31fb10
<idle>-0 [007] 3243.950218208: irq_entry: pt_regs=c0000000ce323b10
<idle>-0 [007] 3243.950224080: irq_exit: pt_regs=c0000000ce323b10
<idle>-0 [000] 3244.021879320: irq_entry: pt_regs=c000000000a63aa0
<idle>-0 [000] 3244.021883616: irq_handler_entry: irq=87 handler=eth0
<idle>-0 [000] 3244.021887328: irq_handler_exit: irq=87 return=handled
<idle>-0 [000] 3244.021897408: irq_exit: pt_regs=c000000000a63aa0
Here we see two phantom interrupts (no handler was invoked), followed
by a real interrupt for eth0. Without the tracepoints in this patch we
would have missed the phantom interrupts.
Since these would be the first arch specific tracepoints, I'd like to make
sure we agree on naming. The tracepoints live in events/powerpc/*, but I'm
wondering if the tracepoint name should also contain the arch name, eg
powerpc_irq_entry/powerpc_irq_exit. Thoughts?
Signed-off-by: Anton Blanchard <anton@samba.org>
--
Index: linux.trees.git/arch/powerpc/kernel/irq.c
===================================================================
--- linux.trees.git.orig/arch/powerpc/kernel/irq.c 2009-10-06 11:11:44.000000000 +1100
+++ linux.trees.git/arch/powerpc/kernel/irq.c 2009-10-06 11:15:09.000000000 +1100
@@ -54,6 +54,8 @@
#include <linux/pci.h>
#include <linux/debugfs.h>
#include <linux/perf_event.h>
+#define CREATE_TRACE_POINTS
+#include <trace/events/powerpc.h>
#include <asm/uaccess.h>
#include <asm/system.h>
@@ -325,6 +327,8 @@ void do_IRQ(struct pt_regs *regs)
struct pt_regs *old_regs = set_irq_regs(regs);
unsigned int irq;
+ trace_irq_entry(regs);
+
irq_enter();
check_stack_overflow();
@@ -348,6 +352,8 @@ void do_IRQ(struct pt_regs *regs)
timer_interrupt(regs);
}
#endif
+
+ trace_irq_exit(regs);
}
void __init init_IRQ(void)
Index: linux.trees.git/include/trace/events/powerpc.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux.trees.git/include/trace/events/powerpc.h 2009-10-06 11:14:05.000000000 +1100
@@ -0,0 +1,47 @@
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM powerpc
+
+#if !defined(_TRACE_POWERPC_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_POWERPC_H
+
+#include <linux/ptrace.h>
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(irq_entry,
+
+ TP_PROTO(struct pt_regs *regs),
+
+ TP_ARGS(regs),
+
+ TP_STRUCT__entry(
+ __field(struct pt_regs *, regs)
+ ),
+
+ TP_fast_assign(
+ __entry->regs = regs;
+ ),
+
+ TP_printk("pt_regs=%p", __entry->regs)
+);
+
+TRACE_EVENT(irq_exit,
+
+ TP_PROTO(struct pt_regs *regs),
+
+ TP_ARGS(regs),
+
+ TP_STRUCT__entry(
+ __field(struct pt_regs *, regs)
+ ),
+
+ TP_fast_assign(
+ __entry->regs = regs;
+ ),
+
+ TP_printk("pt_regs=%p", __entry->regs)
+);
+
+#endif /* _TRACE_POWERPC_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
^ permalink raw reply
* Re: [PATCH] powerpc: tracing: Add powerpc tracepoints for interrupt entry and exit
From: Steven Rostedt @ 2009-10-06 2:34 UTC (permalink / raw)
To: Anton Blanchard; +Cc: Frederic Weisbecker, Ingo Molnar, linuxppc-dev
In-Reply-To: <20091006021903.GC16073@kryten>
On Tue, 2009-10-06 at 13:19 +1100, Anton Blanchard wrote:
> This patch adds powerpc specific tracepoints for interrupt entry and exit.
>
> While we already have generic irq_handler_entry and irq_handler_exit
> tracepoints there are cases on our virtualised powerpc machines where an
> interrupt is presented to the OS, but subsequently handled by the hypervisor.
> This means no OS interrupt handler is invoked.
>
> Here is an example on a POWER6 machine with the patch below applied:
Hi Anton,
Thanks for the patch.
>
> <idle>-0 [006] 3243.949840744: irq_entry: pt_regs=c0000000ce31fb10
> <idle>-0 [006] 3243.949850520: irq_exit: pt_regs=c0000000ce31fb10
>
> <idle>-0 [007] 3243.950218208: irq_entry: pt_regs=c0000000ce323b10
> <idle>-0 [007] 3243.950224080: irq_exit: pt_regs=c0000000ce323b10
>
> <idle>-0 [000] 3244.021879320: irq_entry: pt_regs=c000000000a63aa0
> <idle>-0 [000] 3244.021883616: irq_handler_entry: irq=87 handler=eth0
> <idle>-0 [000] 3244.021887328: irq_handler_exit: irq=87 return=handled
> <idle>-0 [000] 3244.021897408: irq_exit: pt_regs=c000000000a63aa0
>
> Here we see two phantom interrupts (no handler was invoked), followed
> by a real interrupt for eth0. Without the tracepoints in this patch we
> would have missed the phantom interrupts.
>
> Since these would be the first arch specific tracepoints, I'd like to make
> sure we agree on naming. The tracepoints live in events/powerpc/*, but I'm
> wondering if the tracepoint name should also contain the arch name, eg
> powerpc_irq_entry/powerpc_irq_exit. Thoughts?
>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> --
>
> Index: linux.trees.git/arch/powerpc/kernel/irq.c
> ===================================================================
> --- linux.trees.git.orig/arch/powerpc/kernel/irq.c 2009-10-06 11:11:44.000000000 +1100
> +++ linux.trees.git/arch/powerpc/kernel/irq.c 2009-10-06 11:15:09.000000000 +1100
> @@ -54,6 +54,8 @@
> #include <linux/pci.h>
> #include <linux/debugfs.h>
> #include <linux/perf_event.h>
> +#define CREATE_TRACE_POINTS
> +#include <trace/events/powerpc.h>
>
> #include <asm/uaccess.h>
> #include <asm/system.h>
> @@ -325,6 +327,8 @@ void do_IRQ(struct pt_regs *regs)
> struct pt_regs *old_regs = set_irq_regs(regs);
> unsigned int irq;
>
> + trace_irq_entry(regs);
> +
> irq_enter();
>
> check_stack_overflow();
> @@ -348,6 +352,8 @@ void do_IRQ(struct pt_regs *regs)
> timer_interrupt(regs);
> }
> #endif
> +
> + trace_irq_exit(regs);
> }
>
> void __init init_IRQ(void)
> Index: linux.trees.git/include/trace/events/powerpc.h
> ===================================================================
> --- /dev/null 1970-01-01 00:00:00.000000000 +0000
> +++ linux.trees.git/include/trace/events/powerpc.h 2009-10-06 11:14:05.000000000 +1100
I think this may do better in a file like:
arch/powerpc/kernel/trace.h
You can look at the sample code and Makefile in samples/trace_events/
that shows how to make it work outside the include/trace/events
directory.
I really would like to avoid placing arch specific files in a generic
directory, especially when there's a way to do it in the arch directory
itself.
This also contains the arch code a bit better.
Thanks,
-- Steve
> @@ -0,0 +1,47 @@
> +#undef TRACE_SYSTEM
> +#define TRACE_SYSTEM powerpc
> +
> +#if !defined(_TRACE_POWERPC_H) || defined(TRACE_HEADER_MULTI_READ)
> +#define _TRACE_POWERPC_H
> +
> +#include <linux/ptrace.h>
> +#include <linux/tracepoint.h>
> +
> +TRACE_EVENT(irq_entry,
> +
> + TP_PROTO(struct pt_regs *regs),
> +
> + TP_ARGS(regs),
> +
> + TP_STRUCT__entry(
> + __field(struct pt_regs *, regs)
> + ),
> +
> + TP_fast_assign(
> + __entry->regs = regs;
> + ),
> +
> + TP_printk("pt_regs=%p", __entry->regs)
> +);
> +
> +TRACE_EVENT(irq_exit,
> +
> + TP_PROTO(struct pt_regs *regs),
> +
> + TP_ARGS(regs),
> +
> + TP_STRUCT__entry(
> + __field(struct pt_regs *, regs)
> + ),
> +
> + TP_fast_assign(
> + __entry->regs = regs;
> + ),
> +
> + TP_printk("pt_regs=%p", __entry->regs)
> +);
> +
> +#endif /* _TRACE_POWERPC_H */
> +
> +/* This part must be outside protection */
> +#include <trace/define_trace.h>
^ permalink raw reply
* Re: [PATCH] powerpc: tracing: Add powerpc tracepoints for interrupt entry and exit
From: Anton Blanchard @ 2009-10-06 4:05 UTC (permalink / raw)
To: Steven Rostedt; +Cc: Frederic Weisbecker, Ingo Molnar, linuxppc-dev
In-Reply-To: <1254796492.13160.218.camel@gandalf.stny.rr.com>
Hi Steve,
> I think this may do better in a file like:
>
> arch/powerpc/kernel/trace.h
>
> You can look at the sample code and Makefile in samples/trace_events/
> that shows how to make it work outside the include/trace/events
> directory.
>
> I really would like to avoid placing arch specific files in a generic
> directory, especially when there's a way to do it in the arch directory
> itself.
>
> This also contains the arch code a bit better.
Much nicer! I put the header file into include/asm/trace.h so an out of
tree kernel module can find it easily. Does that sound reasonable?
Also, I ended up with an interesting include issue in trace-events.c:
In file included from include/linux/slab.h:162,
from include/linux/percpu.h:5,
from /root/linux-tip/arch/powerpc/include/asm/tlbflush.h:86,
from /root/linux-tip/arch/powerpc/include/asm/pgtable-ppc64.h:121,
from /root/linux-tip/arch/powerpc/include/asm/pgtable.h:23,
from include/linux/mm.h:39,
from include/linux/ring_buffer.h:5,
from include/linux/ftrace_event.h:4,
from include/trace/ftrace.h:19,
from include/trace/define_trace.h:61,
from /root/linux-tip/arch/powerpc/include/asm/trace.h:52,
from arch/powerpc/kernel/trace-events.c:2:
include/linux/slub_def.h: In function ‘kmalloc_large’:
include/linux/slub_def.h:236: error: implicit declaration of function ‘trace_kmalloc’
include/linux/slub_def.h: In function ‘kmalloc_node’:
include/linux/slub_def.h:296: error: implicit declaration of function ‘trace_kmalloc_node’
Which I could work around by including linux/slab.h before creating
the asm/trace.h tracepoints. I assume we don't see this elsewhere because
any non trivial file includes linux/slab.h somewhere :)
Anton
--
This patch adds powerpc specific tracepoints for interrupt entry and exit.
While we already have generic irq_handler_entry and irq_handler_exit
tracepoints there are cases on our virtualised powerpc machines where an
interrupt is presented to the OS, but subsequently handled by the hypervisor.
This means no OS interrupt handler is invoked.
Here is an example on a POWER6 machine with the patch below applied:
<idle>-0 [006] 3243.949840744: irq_entry: pt_regs=c0000000ce31fb10
<idle>-0 [006] 3243.949850520: irq_exit: pt_regs=c0000000ce31fb10
<idle>-0 [007] 3243.950218208: irq_entry: pt_regs=c0000000ce323b10
<idle>-0 [007] 3243.950224080: irq_exit: pt_regs=c0000000ce323b10
<idle>-0 [000] 3244.021879320: irq_entry: pt_regs=c000000000a63aa0
<idle>-0 [000] 3244.021883616: irq_handler_entry: irq=87 handler=eth0
<idle>-0 [000] 3244.021887328: irq_handler_exit: irq=87 return=handled
<idle>-0 [000] 3244.021897408: irq_exit: pt_regs=c000000000a63aa0
Here we see two phantom interrupts (no handler was invoked), followed
by a real interrupt for eth0. Without the tracepoints in this patch we
would have missed the phantom interrupts.
Since these would be the first arch specific tracepoints, I'd like to make
sure we agree on naming. The tracepoints live in events/powerpc/*, but I'm
wondering if the tracepoint name should also contain the arch name, eg
powerpc_irq_entry/powerpc_irq_exit. Thoughts?
Signed-off-by: Anton Blanchard <anton@samba.org>
--
Index: linux.trees.git/arch/powerpc/include/asm/trace.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux.trees.git/arch/powerpc/include/asm/trace.h 2009-10-06 14:54:25.000000000 +1100
@@ -0,0 +1,53 @@
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM powerpc
+
+#if !defined(_TRACE_POWERPC_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_POWERPC_H
+
+#include <linux/tracepoint.h>
+
+struct pt_regs;
+
+TRACE_EVENT(irq_entry,
+
+ TP_PROTO(struct pt_regs *regs),
+
+ TP_ARGS(regs),
+
+ TP_STRUCT__entry(
+ __field(struct pt_regs *, regs)
+ ),
+
+ TP_fast_assign(
+ __entry->regs = regs;
+ ),
+
+ TP_printk("pt_regs=%p", __entry->regs)
+);
+
+TRACE_EVENT(irq_exit,
+
+ TP_PROTO(struct pt_regs *regs),
+
+ TP_ARGS(regs),
+
+ TP_STRUCT__entry(
+ __field(struct pt_regs *, regs)
+ ),
+
+ TP_fast_assign(
+ __entry->regs = regs;
+ ),
+
+ TP_printk("pt_regs=%p", __entry->regs)
+);
+
+#endif /* _TRACE_POWERPC_H */
+
+#undef TRACE_INCLUDE_PATH
+#undef TRACE_INCLUDE_FILE
+
+#define TRACE_INCLUDE_PATH asm
+#define TRACE_INCLUDE_FILE trace
+
+#include <trace/define_trace.h>
Index: linux.trees.git/arch/powerpc/kernel/Makefile
===================================================================
--- linux.trees.git.orig/arch/powerpc/kernel/Makefile 2009-10-06 14:02:03.000000000 +1100
+++ linux.trees.git/arch/powerpc/kernel/Makefile 2009-10-06 14:38:51.000000000 +1100
@@ -115,6 +115,8 @@ ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC),)
obj-y += ppc_save_regs.o
endif
+obj-$(CONFIG_TRACEPOINTS) += trace-events.o
+
# Disable GCOV in odd or sensitive code
GCOV_PROFILE_prom_init.o := n
GCOV_PROFILE_ftrace.o := n
Index: linux.trees.git/arch/powerpc/kernel/trace-events.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux.trees.git/arch/powerpc/kernel/trace-events.c 2009-10-06 14:44:57.000000000 +1100
@@ -0,0 +1,3 @@
+#include <linux/slab.h>
+#define CREATE_TRACE_POINTS
+#include <asm/trace.h>
Index: linux.trees.git/arch/powerpc/kernel/irq.c
===================================================================
--- linux.trees.git.orig/arch/powerpc/kernel/irq.c 2009-10-06 14:02:15.000000000 +1100
+++ linux.trees.git/arch/powerpc/kernel/irq.c 2009-10-06 14:13:08.000000000 +1100
@@ -54,6 +54,7 @@
#include <linux/pci.h>
#include <linux/debugfs.h>
#include <linux/perf_event.h>
+#include <asm/trace.h>
#include <asm/uaccess.h>
#include <asm/system.h>
@@ -325,6 +326,8 @@ void do_IRQ(struct pt_regs *regs)
struct pt_regs *old_regs = set_irq_regs(regs);
unsigned int irq;
+ trace_irq_entry(regs);
+
irq_enter();
check_stack_overflow();
@@ -348,6 +351,8 @@ void do_IRQ(struct pt_regs *regs)
timer_interrupt(regs);
}
#endif
+
+ trace_irq_exit(regs);
}
void __init init_IRQ(void)
^ permalink raw reply
* Re: [PATCH v2] mpc5200: support for the MAN mpc5200 based board uc101
From: Heiko Schocher @ 2009-10-06 5:19 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev
In-Reply-To: <fa686aa40910050646p168c2bbfi4b432778827102c9@mail.gmail.com>
Hello Grant,
Grant Likely wrote:
> On Mon, Oct 5, 2009 at 4:12 AM, Heiko Schocher <hs@denx.de> wrote:
>> Wolfram Sang wrote:
>>> Is this an official binding? I also did an gpio-watchdog a while ago and there
>>> were some issues with the binding, IIRC. Would be nice if this has been solved
>>> meanwhile.
>> Oh, sorry, no. I remove it.
>
> You don't need to remove it, but choose a compatible value within the
> board/manufacturer namespace. ie. 'manroland,uc101-watchdog'. You
Hmm.. currently I prefer to remove it, because it is not a uc101 special
wdt driver. When this wdt driver go in mainline, it is easy to readd it
to this board support.
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply
* Re: [PATCH 3/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
From: Joakim Tjernlund @ 2009-10-06 6:15 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <1254789255.7122.95.camel@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 06/10/2009 02:34:15:
>
> On Tue, 2009-10-06 at 01:35 +0200, Joakim Tjernlund wrote:
> >
> > > Well, if the HW has the ability to enforce trap when store with !
> > DIRTY,
> >
> > Yes, provided that the kernel invalidates the TLB too so the next
> > access
> > will provoke a TLB Miss, which will then provoke a TLB error. The TLB
> > error routine checks VALID, RW and USER(if not a kernel access), then
> > sets
> > ACCESSED & DIRTY and writes the TLB(RPN reg).
> >
> > Perhaps the missing invalidate is haunting us here?
>
> No, the kernel will invalidate when clearing dirty or accessed, I don't
> think that's our problem.
>
> This is still all inefficient, we end up basically with two traps.
Yes, but once the 2 traps is over, it gets much cheaper plus I don't
get a choice, see below.
>
> 8xx provides backup GPRs when doing TLB misses ? What does it cost to
> jump out of a TLB miss back into "normal" context ?
Nope, there is just one TLB scratch register. I have been meaning to
ask you about SPRG2, it seems unused?
There is a leftover from 2.4 that inits G2 to something but the
it appears unused otherwise.
>
> IE. What I do on 440 is I set a mask of required bits, basically
> _PAGE_PRESENT | _PAGE_ACCESSED is the base. The DTLB miss also sticks
> in _PAGE_RW | _PAGE_DIRTY when it's a store fault.
Yes, I would too but TLB Miss knows nothing about load/store, protection etc.
because DSISR isn't set. So I cannot see any other way than the TLB Error way.
>
> Then, I andc. the PTE value off that mask, and if the result is non-0
> (which means one of the required bits is missing), I get out of the TLB
> miss immediately and go to the data (or instruction) access interrupt.
>
> Once you've done that, you should be able to have data and instruction
> access go straight to C. Missing _PAGE_ACCESSED and _PAGE_DIRTY are
> going to be fixed up by generic code.
>
> > > then that's fine, just map it that way, but you shouldn't have to
> > handle
> > > it in the DTLB error neither, the kernel will fix it up for you in
> > > handle_pte_fault().
> >
> > Does not all ppc have the Changed bit?
>
> No. BookE doesn't.
But I guess BookE knows if it is a load or store in TLB Miss?
Then it can emulate changed bit I guess.
^ permalink raw reply
* Re: [PATCH 0/6] PowerPc 8xx TLB/MMU fixes
From: Joakim Tjernlund @ 2009-10-06 6:25 UTC (permalink / raw)
To: Rex Feany; +Cc: Scott Wood, linuxppc-dev@ozlabs.org
In-Reply-To: <20091005224218.GA5273@compile2.chatsunix.int.mrv.com>
Rex Feany <RFeany@mrv.com> wrote on 06/10/2009 00:42:18:
>
> Thus spake Joakim Tjernlund (joakim.tjernlund@transmode.se):
>
> > > I got this oops:
> > >
> > > Unable to handle kernel paging request for data at address 0x00000000
> > > Faulting instruction address: 0xc000e110
> > > Oops: Kernel access of bad area, sig: 11 [#1]
> > > MRV NM2
> > > NIP: c000e110 LR: c000d520 CTR: 1006bf40
> > > REGS: c2203dd0 TRAP: 0300 Not tainted (2.6.32-rc3-00014-gcea49b0-dirty)
> > > MSR: 00009032 <EE,ME,IR,DR> CR: 44022422 XER: 20000000
> > > DAR: 00000000, DSISR: c0000000
> > > TASK = c21c18c0[69] 'rc.sysinit' THREAD: c2202000
> > > GPR00: 00000401 c2203e80 c21c18c0 c2203f50 00000000 4000d032 00000000 00000000
> > > GPR08: 10093eb4 00000000 00009032 c000d514 021c1ad0 10095c50 03ffb000 10006500
> > > GPR16: 10006508 00000000 00000000 00000000 100a2fc8 021c4238 00000000 00000400
> > > GPR24: c21a2700 00000002 40000000 00000000 00000000 c2203f50 00000000 00000011
> > > NIP [c000e110] do_page_fault+0x44/0x5fc
> > > LR [c000d520] handle_page_fault+0xc/0x80
> > > Call Trace:
> > > [c2203e80] [c000e58c] do_page_fault+0x4c0/0x5fc (unreliable)
> > > [c2203f40] [c000d520] handle_page_fault+0xc/0x80
> > > Instruction dump:
> > > 800300a0 7cba2b78 54170036 2f970400 7c9c2378 830200e0 54b6018c 40be000c
> > > 74ba4820 3ac00000 813d0080 3bc00000 <80a90000> 54a036be 2f80001f 40be0100
> > > ---[ end trace 99a4d88f7e2f1b60 ]---
> > >
> > > this happens in do_page_fault becaose regs->nip is null, so
> >
> > regs or regs->nip is NULL? Either one does not make sense
> > In any case it might be a secondary problem as DAR is NULL already when you
> > enter the page fault.
>
> I assumed it was NIP because ... I'm not sure why. TRAP() above
> dereferences regs, and that didn't fail, but I didn't see that until
> now.
Yes, it is a bit strange though that the kernel isn't allowed to read from
NULL. Is that expected?
Jocke
^ permalink raw reply
* [PATCH] powerpc/iseries: remove compiler version dependent hack
From: Stephen Rothwell @ 2009-10-06 6:28 UTC (permalink / raw)
To: ppc-dev
The creation of the flattened device tree depended on the compiler
putting the constant strings for an object in a section with a
particular name. This was changed with recent compilers. Do this
explicitly instead.
Without this patch, iseries kernels may silently not boot when built with
some compilers.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/platforms/iseries/Makefile | 11 +-----
arch/powerpc/platforms/iseries/dt.c | 56 +++++++++++++-----------------
2 files changed, 25 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/platforms/iseries/Makefile b/arch/powerpc/platforms/iseries/Makefile
index cc7161f..ce01492 100644
--- a/arch/powerpc/platforms/iseries/Makefile
+++ b/arch/powerpc/platforms/iseries/Makefile
@@ -1,18 +1,9 @@
EXTRA_CFLAGS += -mno-minimal-toc
-extra-y += dt.o
-
obj-y += exception.o
-obj-y += hvlog.o hvlpconfig.o lpardata.o setup.o dt_mod.o mf.o lpevents.o \
+obj-y += hvlog.o hvlpconfig.o lpardata.o setup.o dt.o mf.o lpevents.o \
hvcall.o proc.o htab.o iommu.o misc.o irq.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_VIOPATH) += viopath.o vio.o
obj-$(CONFIG_MODULES) += ksyms.o
-
-quiet_cmd_dt_strings = DT_STR $@
- cmd_dt_strings = $(OBJCOPY) --rename-section .rodata.str1.8=.dt_strings \
- $< $@
-
-$(obj)/dt_mod.o: $(obj)/dt.o
- $(call if_changed,dt_strings)
diff --git a/arch/powerpc/platforms/iseries/dt.c b/arch/powerpc/platforms/iseries/dt.c
index c5a87a7..7f45a51 100644
--- a/arch/powerpc/platforms/iseries/dt.c
+++ b/arch/powerpc/platforms/iseries/dt.c
@@ -51,11 +51,16 @@
/*
* These are created by the linker script at the start and end
- * of the section containing all the strings from this file.
+ * of the section containing all the strings marked with the DS macro.
*/
extern char __dt_strings_start[];
extern char __dt_strings_end[];
+#define DS(s) ({ \
+ static const char __s[] __attribute__((section(".dt_strings"))) = s; \
+ __s; \
+})
+
struct iseries_flat_dt {
struct boot_param_header header;
u64 reserve_map[2];
@@ -64,9 +69,8 @@ struct iseries_flat_dt {
static void * __initdata dt_data;
/*
- * Putting these strings here keeps them out of the section
- * that we rename to .dt_strings using objcopy and capture
- * for the strings blob of the flattened device tree.
+ * Putting these strings here keeps them out of the .dt_strings section
+ * that we capture for the strings blob of the flattened device tree.
*/
static char __initdata device_type_cpu[] = "cpu";
static char __initdata device_type_memory[] = "memory";
@@ -173,7 +177,7 @@ static void __init dt_start_node(struct iseries_flat_dt *dt, const char *name)
#define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE)
-static void __init dt_prop(struct iseries_flat_dt *dt, const char *name,
+static void __init __dt_prop(struct iseries_flat_dt *dt, const char *name,
const void *data, int len)
{
unsigned long offset;
@@ -191,44 +195,32 @@ static void __init dt_prop(struct iseries_flat_dt *dt, const char *name,
/* The actual data. */
dt_push_bytes(dt, data, len);
}
+#define dt_prop(dt, name, data, len) __dt_prop((dt), DS(name), (data), (len))
-static void __init dt_prop_str(struct iseries_flat_dt *dt, const char *name,
- const char *data)
-{
- dt_prop(dt, name, data, strlen(data) + 1); /* + 1 for NULL */
-}
+#define dt_prop_str(dt, name, data) \
+ dt_prop((dt), name, (data), strlen((data)) + 1); /* + 1 for NULL */
-static void __init dt_prop_u32(struct iseries_flat_dt *dt, const char *name,
+static void __init __dt_prop_u32(struct iseries_flat_dt *dt, const char *name,
u32 data)
{
- dt_prop(dt, name, &data, sizeof(u32));
+ __dt_prop(dt, name, &data, sizeof(u32));
}
+#define dt_prop_u32(dt, name, data) __dt_prop_u32((dt), DS(name), (data))
-static void __init __maybe_unused dt_prop_u64(struct iseries_flat_dt *dt,
- const char *name,
- u64 data)
+static void __init __maybe_unused __dt_prop_u64(struct iseries_flat_dt *dt,
+ const char *name, u64 data)
{
- dt_prop(dt, name, &data, sizeof(u64));
+ __dt_prop(dt, name, &data, sizeof(u64));
}
+#define dt_prop_u64(dt, name, data) __dt_prop_u64((dt), DS(name), (data))
-static void __init dt_prop_u64_list(struct iseries_flat_dt *dt,
- const char *name, u64 *data, int n)
-{
- dt_prop(dt, name, data, sizeof(u64) * n);
-}
+#define dt_prop_u64_list(dt, name, data, n) \
+ dt_prop((dt), name, (data), sizeof(u64) * (n))
-static void __init dt_prop_u32_list(struct iseries_flat_dt *dt,
- const char *name, u32 *data, int n)
-{
- dt_prop(dt, name, data, sizeof(u32) * n);
-}
+#define dt_prop_u32_list(dt, name, data, n) \
+ dt_prop((dt), name, (data), sizeof(u32) * (n))
-#ifdef notyet
-static void __init dt_prop_empty(struct iseries_flat_dt *dt, const char *name)
-{
- dt_prop(dt, name, NULL, 0);
-}
-#endif
+#define dt_prop_empty(dt, name) dt_prop((dt), name, NULL, 0)
static void __init dt_cpus(struct iseries_flat_dt *dt)
{
--
1.6.4.3
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
^ permalink raw reply related
* Re: [PATCH 0/6] PowerPc 8xx TLB/MMU fixes
From: Benjamin Herrenschmidt @ 2009-10-06 6:44 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <OFDFE80DD9.19502D87-ONC1257647.0022C31E-C1257647.00235079@transmode.se>
> > I assumed it was NIP because ... I'm not sure why. TRAP() above
> > dereferences regs, and that didn't fail, but I didn't see that until
> > now.
>
> Yes, it is a bit strange though that the kernel isn't allowed to read from
> NULL. Is that expected?
Yes, that's absolutely expected :-) You really want any NULL deref to
blow up asap.
0 is actually part of the address space assigned to user processes. By
default they don't have anything there neither though, but if the
current process do have something mapped there, then the kernel would
read that when doing a NULL deref.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 3/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
From: Benjamin Herrenschmidt @ 2009-10-06 6:45 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <OFC7D289B7.88EECA01-ONC1257647.001E8F29-C1257647.002265AF@transmode.se>
On Tue, 2009-10-06 at 08:15 +0200, Joakim Tjernlund wrote:
> Yes, I would too but TLB Miss knows nothing about load/store, protection etc.
> because DSISR isn't set. So I cannot see any other way than the TLB Error way.
Hrm... that MMU really sucks more than I thought :-(
I'll go read the manual and think about that a bit more.
> But I guess BookE knows if it is a load or store in TLB Miss?
> Then it can emulate changed bit I guess.
Yes, it knows.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc/iseries: remove compiler version dependent hack
From: Stephen Rothwell @ 2009-10-06 6:46 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: ppc-dev
In-Reply-To: <20091006172847.440e8798.sfr@canb.auug.org.au>
[-- Attachment #1: Type: text/plain, Size: 645 bytes --]
Hi Ben,
On Tue, 6 Oct 2009 17:28:47 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> The creation of the flattened device tree depended on the compiler
> putting the constant strings for an object in a section with a
> particular name. This was changed with recent compilers. Do this
> explicitly instead.
>
> Without this patch, iseries kernels may silently not boot when built with
> some compilers.
So this is probably a candidate for 2.6.32 and maybe some of the stable
releases (if anyone cares enough).
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply
* [PATCH v2 1/3] powerpc/fsl: 85xx: document cache-sram size as a kernel parametric option
From: Vivek Mahajan @ 2009-10-06 6:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kumar.gala, Vivek Mahajan
Adds documentation for the size parameter of Freescale's QorIQ
based cache-sram
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
v2: No change
Documentation/kernel-parameters.txt | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 6fa7292..8767f36 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -412,6 +412,9 @@ and is between 256 and 4096 characters. It is defined in the file
c101= [NET] Moxa C101 synchronous serial card
+ cache-sram-size= [PPC] Size of Freescale's QorIQ Cache SRAM
+ See Documentation/powerpc/fsl_85xx_cache_sram.txt.
+
cachesize= [BUGS=X86-32] Override level 2 CPU cache size detection.
Sometimes CPU hardware bugs make them report the cache
size incorrectly. The kernel will attempt work arounds
--
1.5.6.5
^ permalink raw reply related
* [PATCH v2 2/3] powerpc/fsl: 85xx: document cache-sram
From: Vivek Mahajan @ 2009-10-06 6:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kumar.gala, Vivek Mahajan
In-Reply-To: <1254811766-30903-1-git-send-email-vivek.mahajan@freescale.com>
Adds documentation for Freescale's QorIQ based cache-sram as under:-
* How to enable it from a low level driver
* How to set its size
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
v2: No change
Documentation/powerpc/fsl_85xx_cache_sram.txt | 31 +++++++++++++++++++++++++
1 files changed, 31 insertions(+), 0 deletions(-)
create mode 100644 Documentation/powerpc/fsl_85xx_cache_sram.txt
diff --git a/Documentation/powerpc/fsl_85xx_cache_sram.txt b/Documentation/powerpc/fsl_85xx_cache_sram.txt
new file mode 100644
index 0000000..7f43e2a
--- /dev/null
+++ b/Documentation/powerpc/fsl_85xx_cache_sram.txt
@@ -0,0 +1,31 @@
+* Freescale QorIQ based Cache SRAM
+
+Freescale's QorIQ platforms provide an option of configuring
+a part of (or full) cache memory as SRAM. Any low level
+driver can use its APIs via selecting FSL_85XX_CACHE_SRAM as
+under for the case of gianfar ethernet driver:-
+
+In drivers/net/Kconfig:-
+
+config GIANFAR
+ ....
+ select FSL_85XX_CACHE_SRAM if MPC85xx
+ ....
+
+FSL_85XX_CACHE_SRAM and its base address are defined in
+arch/powerpc/platforms/85xx/Kconfig as under:-
+
+config FSL_85XX_CACHE_SRAM
+ bool
+ select PPC_LIB_RHEAP
+
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default "0xfff00000"
+
+The size of the above cache SRAM memory window is passed via the
+kernel command line as <cache-sram-size=....>
+
+Absence of the above parameter in the kernel command line is
+treated as no cache SRAM.
--
1.5.6.5
^ permalink raw reply related
* [PATCH v2 3/3] powerpc/fsl: 85xx: add cache-sram support
From: Vivek Mahajan @ 2009-10-06 6:49 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kumar.gala, Vivek Mahajan
In-Reply-To: <1254811766-30903-2-git-send-email-vivek.mahajan@freescale.com>
This adds QorIQ based Cache-SRAM support as under:-
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Defines FSL_85XX_CACHE_SRAM and its base address
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
---
v2: mbar(1) -> eieio() as per Kumar G.
arch/powerpc/include/asm/fsl_85xx_cache_sram.h | 48 ++++++
arch/powerpc/platforms/85xx/Kconfig | 9 ++
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h | 95 ++++++++++++
arch/powerpc/sysdev/fsl_85xx_cache_sram.c | 141 ++++++++++++++++++
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 184 ++++++++++++++++++++++++
6 files changed, 478 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_85xx_cache_sram.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_sram.c
create mode 100644 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
diff --git a/arch/powerpc/include/asm/fsl_85xx_cache_sram.h b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
new file mode 100644
index 0000000..2af2bdc
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Cache SRAM handling for QorIQ platform
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+
+ * This file is derived from the original work done
+ * by Sylvain Munaut for the Bestcomm SRAM allocator.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+
+#include <asm/rheap.h>
+#include <linux/spinlock.h>
+
+/*
+ * Cache-SRAM
+ */
+
+struct mpc85xx_cache_sram {
+ phys_addr_t base_phys;
+ void *base_virt;
+ unsigned int size;
+ rh_info_t *rh;
+ spinlock_t lock;
+};
+
+extern void mpc85xx_cache_sram_free(void *ptr);
+extern void *mpc85xx_cache_sram_alloc(unsigned int size,
+ phys_addr_t *phys, unsigned int align);
+
+#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d3a975e..b6f23c3 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -144,6 +144,15 @@ config SBC8560
help
This option enables support for the Wind River SBC8560 board
+config FSL_85XX_CACHE_SRAM
+ bool
+ select PPC_LIB_RHEAP
+
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default "0xfff00000"
+
endif # MPC85xx
config TQM85xx
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 9d4b174..745994c 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
+obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
obj-$(CONFIG_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
new file mode 100644
index 0000000..8c4a4ac
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc
+ *
+ * QorIQ based Cache Controller Memory Mapped Registers
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __FSL_85XX_CACHE_CTLR_H__
+#define __FSL_85XX_CACHE_CTLR_H__
+
+#define L2CR_L2FI 0x40000000 /* L2 flash invalidate */
+#define L2CR_L2IO 0x00200000 /* L2 instruction only */
+#define L2CR_SRAM_ZERO 0x00000000 /* L2SRAM zero size */
+#define L2CR_SRAM_FULL 0x00010000 /* L2SRAM full size */
+#define L2CR_SRAM_HALF 0x00020000 /* L2SRAM half size */
+#define L2CR_SRAM_TWO_HALFS 0x00030000 /* L2SRAM two half sizes */
+#define L2CR_SRAM_QUART 0x00040000 /* L2SRAM one quarter size */
+#define L2CR_SRAM_TWO_QUARTS 0x00050000 /* L2SRAM two quarter size */
+#define L2CR_SRAM_EIGHTH 0x00060000 /* L2SRAM one eighth size */
+#define L2CR_SRAM_TWO_EIGHTH 0x00070000 /* L2SRAM two eighth size */
+
+#define L2SRAM_OPTIMAL_SZ_SHIFT 0x00000003 /* Optimum size for L2SRAM */
+
+#define L2SRAM_BAR_MSK_LO18 0xFFFFC000 /* Lower 18 bits */
+#define L2SRAM_BARE_MSK_HI4 0x0000000F /* Upper 4 bits */
+
+enum cache_sram_lock_ways {
+ LOCK_WAYS_ZERO,
+ LOCK_WAYS_EIGHTH,
+ LOCK_WAYS_TWO_EIGHTH,
+ LOCK_WAYS_HALF = 4,
+ LOCK_WAYS_FULL = 8,
+};
+
+struct mpc85xx_l2ctlr {
+ u32 ctl; /* 0x000 - L2 control */
+ u8 res1[0xC];
+ u32 ewar0; /* 0x010 - External write address 0 */
+ u32 ewarea0; /* 0x014 - External write address extended 0 */
+ u32 ewcr0; /* 0x018 - External write ctrl */
+ u8 res2[4];
+ u32 ewar1; /* 0x020 - External write address 1 */
+ u32 ewarea1; /* 0x024 - External write address extended 1 */
+ u32 ewcr1; /* 0x028 - External write ctrl 1 */
+ u8 res3[4];
+ u32 ewar2; /* 0x030 - External write address 2 */
+ u32 ewarea2; /* 0x034 - External write address extended 2 */
+ u32 ewcr2; /* 0x038 - External write ctrl 2 */
+ u8 res4[4];
+ u32 ewar3; /* 0x040 - External write address 3 */
+ u32 ewarea3; /* 0x044 - External write address extended 3 */
+ u32 ewcr3; /* 0x048 - External write ctrl 3 */
+ u8 res5[0xB4];
+ u32 srbar0; /* 0x100 - SRAM base address 0 */
+ u32 srbarea0; /* 0x104 - SRAM base addr reg ext address 0 */
+ u32 srbar1; /* 0x108 - SRAM base address 1 */
+ u32 srbarea1; /* 0x10C - SRAM base addr reg ext address 1 */
+ u8 res6[0xCF0];
+ u32 errinjhi; /* 0xE00 - Error injection mask high */
+ u32 errinjlo; /* 0xE04 - Error injection mask low */
+ u32 errinjctl; /* 0xE08 - Error injection tag/ecc control */
+ u8 res7[0x14];
+ u32 captdatahi; /* 0xE20 - Error data high capture */
+ u32 captdatalo; /* 0xE24 - Error data low capture */
+ u32 captecc; /* 0xE28 - Error syndrome */
+ u8 res8[0x14];
+ u32 errdet; /* 0xE40 - Error detect */
+ u32 errdis; /* 0xE44 - Error disable */
+ u32 errinten; /* 0xE48 - Error interrupt enable */
+ u32 errattr; /* 0xE4c - Error attribute capture */
+ u32 erradrrl; /* 0xE50 - Error address capture low */
+ u32 erradrrh; /* 0xE54 - Error address capture high */
+ u32 errctl; /* 0xE58 - Error control */
+ u8 res9[0x1A4];
+};
+
+extern int instantiate_cache_sram(struct of_device *dev, unsigned int size);
+extern void remove_cache_sram(struct of_device *dev);
+
+#endif /* __FSL_85XX_CACHE_CTLR_H__ */
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
new file mode 100644
index 0000000..6744083
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Simple memory allocator abstraction for QorIQ (P1/P2) based Cache-SRAM
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+ *
+ * This file is derived from the original work done
+ * by Sylvain Munaut for the Bestcomm SRAM allocator.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <asm/pgtable.h>
+#include <asm/fsl_85xx_cache_sram.h>
+
+struct mpc85xx_cache_sram *cache_sram;
+
+void *mpc85xx_cache_sram_alloc(unsigned int size,
+ phys_addr_t *phys, unsigned int align)
+{
+ unsigned long offset;
+ unsigned long flags;
+
+ if (!size || (size > cache_sram->size) || (align > cache_sram->size)) {
+ pr_err("%s(): size(=%x) or align(=%x) zero or too big\n",
+ __func__, size, align);
+ return NULL;
+ }
+
+ if ((align & (align - 1)) || align <= 1) {
+ pr_err("%s(): align(=%x) must be power of two and >1\n",
+ __func__, align);
+ return NULL;
+ }
+
+ spin_lock_irqsave(&cache_sram->lock, flags);
+ offset = rh_alloc_align(cache_sram->rh, size, align, NULL);
+ spin_unlock_irqrestore(&cache_sram->lock, flags);
+
+ if (IS_ERR_VALUE(offset))
+ return NULL;
+
+ *phys = cache_sram->base_phys + offset;
+
+ return (unsigned char *)cache_sram->base_virt + offset;
+}
+EXPORT_SYMBOL(mpc85xx_cache_sram_alloc);
+
+void mpc85xx_cache_sram_free(void *ptr)
+{
+ unsigned long flags;
+ BUG_ON(!ptr);
+
+ spin_lock_irqsave(&cache_sram->lock, flags);
+ rh_free(cache_sram->rh, ptr - cache_sram->base_virt);
+ spin_unlock_irqrestore(&cache_sram->lock, flags);
+}
+EXPORT_SYMBOL(mpc85xx_cache_sram_free);
+
+int __init instantiate_cache_sram(struct of_device *dev, unsigned int size)
+{
+ if (cache_sram) {
+ dev_err(&dev->dev, "Already initialized cache-sram\n");
+ return -EBUSY;
+ }
+
+ cache_sram = kzalloc(sizeof(struct mpc85xx_cache_sram), GFP_KERNEL);
+ if (!cache_sram) {
+ dev_err(&dev->dev, "Out of memory for cache_sram structure\n");
+ return -ENOMEM;
+ }
+
+ cache_sram->base_phys = CONFIG_FSL_85XX_CACHE_SRAM_BASE;
+ cache_sram->size = size;
+
+ if (!request_mem_region(cache_sram->base_phys, cache_sram->size,
+ "fsl_85xx_cache_sram")) {
+ dev_err(&dev->dev, "%s: request memory failed\n",
+ dev->node->full_name);
+ kfree(cache_sram);
+ return -ENXIO;
+ }
+
+ cache_sram->base_virt = ioremap_flags(cache_sram->base_phys,
+ cache_sram->size, _PAGE_COHERENT | PAGE_KERNEL);
+ if (!cache_sram->base_virt) {
+ dev_err(&dev->dev, "%s: ioremap_flags failed\n",
+ dev->node->full_name);
+ release_mem_region(cache_sram->base_phys, cache_sram->size);
+ kfree(cache_sram);
+ return -ENOMEM;
+ }
+
+ cache_sram->rh = rh_create(sizeof(unsigned int));
+ if (IS_ERR(cache_sram->rh)) {
+ dev_err(&dev->dev, "%s: Unable to create remote heap\n",
+ dev->node->full_name);
+ iounmap(cache_sram->base_virt);
+ release_mem_region(cache_sram->base_phys, cache_sram->size);
+ kfree(cache_sram);
+ return PTR_ERR(cache_sram->rh);
+ }
+
+ rh_attach_region(cache_sram->rh, 0, cache_sram->size);
+ spin_lock_init(&cache_sram->lock);
+
+ dev_info(&dev->dev, "[base:0x%x, size:0x%x] configured and loaded\n",
+ cache_sram->base_phys, cache_sram->size);
+ return 0;
+}
+
+void remove_cache_sram(struct of_device *dev)
+{
+ BUG_ON(!cache_sram);
+
+ rh_detach_region(cache_sram->rh, 0, cache_sram->size);
+ rh_destroy(cache_sram->rh);
+
+ iounmap(cache_sram->base_virt);
+ release_mem_region(cache_sram->base_phys, cache_sram->size);
+
+ kfree(cache_sram);
+ cache_sram = NULL;
+
+ dev_info(&dev->dev, "MPC85xx Cache-SRAM driver unloaded\n");
+}
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
new file mode 100644
index 0000000..e10e2ba
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
+ *
+ * Author: Vivek Mahajan <vivek.mahajan@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <asm/io.h>
+
+#include "fsl_85xx_cache_ctlr.h"
+
+static char *param;
+struct mpc85xx_l2ctlr __iomem *l2ctlr;
+
+static long get_cache_sram_size(void)
+{
+ unsigned long val;
+
+ if (!param || (strict_strtoul(param, 0, &val) < 0))
+ return -EINVAL;
+
+ return val;
+}
+
+static int __init get_cmdline_param(char *str)
+{
+ if (!str)
+ return 0;
+
+ param = str;
+ return 1;
+}
+
+__setup("cache-sram-size=", get_cmdline_param);
+
+static int __devinit mpc85xx_l2ctlr_of_probe(struct of_device *dev,
+ const struct of_device_id *match)
+{
+ long rval;
+ unsigned int rem;
+ unsigned char ways;
+ const unsigned int *prop;
+ unsigned int l2cache_size;
+ unsigned int sram_size;
+
+ if (!dev->node) {
+ dev_err(&dev->dev, "Device's OF-node is NULL\n");
+ return -EINVAL;
+ }
+
+ prop = of_get_property(dev->node, "cache-size", NULL);
+ if (!prop) {
+ dev_err(&dev->dev, "Missing L2 cache-size\n");
+ return -EINVAL;
+ }
+ l2cache_size = *prop;
+
+ rval = get_cache_sram_size();
+ if (rval <= 0) {
+ dev_err(&dev->dev,
+ "Entire L2 as cache, Aborting Cache-SRAM stuff\n");
+ return -EINVAL;
+ }
+
+ rem = l2cache_size % (unsigned int)rval;
+ ways = l2cache_size / (unsigned int)rval;
+ if (rem || (ways & (ways - 1))) {
+ dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
+ return -EINVAL;
+ }
+
+ sram_size = (unsigned int)rval;
+
+ l2ctlr = of_iomap(dev->node, 0);
+ if (!l2ctlr) {
+ dev_err(&dev->dev, "Can't map L2 controller\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Write bits[0-17] to srbar0
+ */
+ out_be32(&l2ctlr->srbar0,
+ CONFIG_FSL_85XX_CACHE_SRAM_BASE & L2SRAM_BAR_MSK_LO18);
+
+ /*
+ * Write bits[18-21] to srbare0
+ */
+ out_be32(&l2ctlr->srbarea0,
+ (CONFIG_FSL_85XX_CACHE_SRAM_BASE >> 10) & L2SRAM_BARE_MSK_HI4);
+
+ clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
+
+ switch (ways) {
+ case LOCK_WAYS_EIGHTH:
+ setbits32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
+ break;
+
+ case LOCK_WAYS_TWO_EIGHTH:
+ setbits32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_TWO_EIGHTH);
+ break;
+
+ case LOCK_WAYS_HALF:
+ setbits32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
+ break;
+
+ case LOCK_WAYS_FULL:
+ default:
+ setbits32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
+ break;
+ }
+ eieio();
+
+ rval = instantiate_cache_sram(dev, sram_size);
+ if (rval < 0) {
+ dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
+ iounmap(l2ctlr);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int __devexit mpc85xx_l2ctlr_of_remove(struct of_device *dev)
+{
+ BUG_ON(!l2ctlr);
+
+ iounmap(l2ctlr);
+ remove_cache_sram(dev);
+ dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
+
+ return 0;
+}
+
+static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
+ {
+ .compatible = "fsl,p2020-l2-cache-controller",
+ },
+ {},
+};
+
+static struct of_platform_driver mpc85xx_l2ctlr_of_platform_driver = {
+ .name = "fsl-l2ctlr",
+ .match_table = mpc85xx_l2ctlr_of_match,
+ .probe = mpc85xx_l2ctlr_of_probe,
+ .remove = __devexit_p(mpc85xx_l2ctlr_of_remove),
+};
+
+static __init int mpc85xx_l2ctlr_of_init(void)
+{
+ return of_register_platform_driver(&mpc85xx_l2ctlr_of_platform_driver);
+}
+
+static void __exit mpc85xx_l2ctlr_of_exit(void)
+{
+ of_unregister_platform_driver(&mpc85xx_l2ctlr_of_platform_driver);
+}
+
+subsys_initcall(mpc85xx_l2ctlr_of_init);
+module_exit(mpc85xx_l2ctlr_of_exit);
+
+MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
+MODULE_LICENSE("GPL v2");
--
1.5.6.5
^ permalink raw reply related
* Re: [PATCH 3/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
From: Joakim Tjernlund @ 2009-10-06 7:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <1254811547.6035.3.camel@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 06/10/2009 08:45:47:
>
> On Tue, 2009-10-06 at 08:15 +0200, Joakim Tjernlund wrote:
>
> > Yes, I would too but TLB Miss knows nothing about load/store, protection etc.
> > because DSISR isn't set. So I cannot see any other way than the TLB Error way.
>
> Hrm... that MMU really sucks more than I thought :-(
Yeah, but at least it got a Changed bit as opposed to some other
arch mention in this mail thread :)
>
> I'll go read the manual and think about that a bit more.
Thanks
I wonder if not much of the problems Scott and Rex are seeing are from
dcbX insn and that my fixup isn't quite working yet. I am tempted
to get the asm version working again as then I don't have to worry about
permission and get_user() et. all :)
^ permalink raw reply
* Re: [PATCH v2] mpc5200: support for the MAN mpc5200 based board uc101
From: Wolfram Sang @ 2009-10-06 8:06 UTC (permalink / raw)
To: Heiko Schocher; +Cc: linuxppc-dev
In-Reply-To: <4ACAD35D.4060904@denx.de>
[-- Attachment #1: Type: text/plain, Size: 521 bytes --]
> Hmm.. currently I prefer to remove it, because it is not a uc101 special
> wdt driver. When this wdt driver go in mainline, it is easy to readd it
> to this board support.
Great, another one interested in a mainline GPIO-WDT-driver :) I'll check again
what happened last time and summarize it later this day. The we can hopefully
work out something.
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [PATCH 0/6] PowerPc 8xx TLB/MMU fixes
From: Joakim Tjernlund @ 2009-10-06 8:06 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <1254793935.1959.1.camel@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote on 06/10/2009 03:52:15:
>
> \
> > So how does this look? Does it change anything?
> > It should as the previous way was way off :(
> >
> > diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
> > index c33c6de..08a392f 100644
> > --- a/arch/powerpc/mm/fault.c
> > +++ b/arch/powerpc/mm/fault.c
> > @@ -153,7 +153,7 @@ int __kprobes do_page_fault(struct pt_regs *regs,
> unsigned long address,
> > #ifdef DEBUG_DCBX
> > const char *istr = NULL;
> >
> > - insn = *((unsigned long *)regs->nip);
> > + __get_user(insn, (unsigned long __user *)regs->nip);
>
> No, use get_user() not __get_user() or if you use the later, also use
> access_ok(), and test the result in case it errors (if it does, you
> probably want to just goto bad access and SEGV).
OK, lets see what this gives us:
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index c33c6de..1bf91d3 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -153,7 +153,8 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
#ifdef DEBUG_DCBX
const char *istr = NULL;
- insn = *((unsigned long *)regs->nip);
+ insn = 0;
+ __get_user(insn, (unsigned long __user *)regs->nip);
if (((insn >> (31-5)) & 0x3f) == 31) {
if (((insn >> 1) & 0x3ff) == 1014) /* dcbz ? 0x3f6 */
istr = "dcbz";
@@ -171,27 +172,32 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
dar = regs->gpr[rb];
if (ra)
dar += regs->gpr[ra];
- if (dar != address && address != 0x00f0 && trap == 0x300)
+ if (dar != address && trap == 0x300)
printk(KERN_CRIT "%s: address:%lx, dar:%lx!\n", istr, address, dar);
if (!strcmp(istr, "dcbst") && is_write) {
printk(KERN_CRIT "dcbst R%ld,R%ld = %lx as a store, fixing!\n",
ra, rb, dar);
is_write = 0;
}
-
+#if 0
if (trap == 0x300 && address != dar) {
__asm__ ("mtdar %0" : : "r" (dar));
return 0;
}
+#endif
}
}
#endif
if (address == 0x00f0 && trap == 0x300) {
- pte_t *ptep;
+ //pte_t *ptep;
/* This is from a dcbX or icbi insn gone bad, these
* insn do not set DAR so we have to do it here instead */
- insn = *((unsigned long *)regs->nip);
+ if (get_user(insn, (unsigned long __user *)regs->nip)) {
+ printk(KERN_CRIT "get_user failed, NIP:%lx\n",
+ regs->nip);
+ goto bad_area_nosemaphore;
+ }
ra = (insn >> (31-15)) & 0x1f; /* Reg RA */
rb = (insn >> (31-20)) & 0x1f; /* Reg RB */
@@ -206,7 +212,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
trap, address, dar, error_code, istr);
#endif
address = dar;
-#if 1
+#if 0
if (is_write && get_pteptr(mm, dar, &ptep, NULL)) {
pte_t my_pte = *ptep;
@@ -216,7 +222,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
}
}
#else
- return 0;
+ //return 0;
#endif
}
}
^ permalink raw reply related
* XILINX memory layout <-> physical memory
From: Thomas Rinder @ 2009-10-06 9:29 UTC (permalink / raw)
To: linuxppc-dev
Betreff: XILINX memory layout <-> physical memory
Hello,
I'm newbie in PPCLinux, don't know I'm right here.
I made a ports to an AVNET FX12 minimodul and custom board (FX40/FX60) =
based
on linuxppc found on http://git.xilinx.com/ (ppc405 processor).
All works fine, but I can use/configure only the half memory size =
available
in the dts (for instance 32Mbytes of 64Mbytes on Avnet minimodul).
Otherwise the kernel crashes if tries to mount the root file system =
(ext2
ramdisk).
I expect my problem is the physical memory layout and its control. I =
want to
understand and control the physical memory layout.
But I didn't not found documentation how the memory layout is organized =
in
linuxppc and
how do I control were kernel, ramdisk etc. resides in physical memory.
Could anyone give me a hint please, how-to start?
Thanks a lot,
Thomas
Ausgehende eMail ist virenfrei.
Von AVG =FCberpr=FCft - www.avg.de=20
Version: 8.5.420 / Virendatenbank: 270.14.4/2416 - Ausgabedatum: =
10/05/09
18:23:00=20
Ausgehende eMail ist virenfrei.
Von AVG =FCberpr=FCft - www.avg.de=20
Version: 8.5.420 / Virendatenbank: 270.14.4/2416 - Ausgabedatum: =
10/05/09
18:23:00=20
^ permalink raw reply
* Re: [PATCH 0/6] PowerPc 8xx TLB/MMU fixes
From: Benjamin Herrenschmidt @ 2009-10-06 8:32 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <OFAEE03401.0C51FEE2-ONC1257647.002C29FE-C1257647.002C917A@transmode.se>
> > No, use get_user() not __get_user() or if you use the later, also use
> > access_ok(), and test the result in case it errors (if it does, you
> > probably want to just goto bad access and SEGV).
>
> OK, lets see what this gives us:
Hrm... did you change anything ? :-)
Ben.
> diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
> index c33c6de..1bf91d3 100644
> --- a/arch/powerpc/mm/fault.c
> +++ b/arch/powerpc/mm/fault.c
> @@ -153,7 +153,8 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
> #ifdef DEBUG_DCBX
> const char *istr = NULL;
>
> - insn = *((unsigned long *)regs->nip);
> + insn = 0;
> + __get_user(insn, (unsigned long __user *)regs->nip);
> if (((insn >> (31-5)) & 0x3f) == 31) {
> if (((insn >> 1) & 0x3ff) == 1014) /* dcbz ? 0x3f6 */
> istr = "dcbz";
> @@ -171,27 +172,32 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
> dar = regs->gpr[rb];
> if (ra)
> dar += regs->gpr[ra];
> - if (dar != address && address != 0x00f0 && trap == 0x300)
> + if (dar != address && trap == 0x300)
> printk(KERN_CRIT "%s: address:%lx, dar:%lx!\n", istr, address, dar);
> if (!strcmp(istr, "dcbst") && is_write) {
> printk(KERN_CRIT "dcbst R%ld,R%ld = %lx as a store, fixing!\n",
> ra, rb, dar);
> is_write = 0;
> }
> -
> +#if 0
> if (trap == 0x300 && address != dar) {
> __asm__ ("mtdar %0" : : "r" (dar));
> return 0;
> }
> +#endif
> }
> }
> #endif
> if (address == 0x00f0 && trap == 0x300) {
> - pte_t *ptep;
> + //pte_t *ptep;
>
> /* This is from a dcbX or icbi insn gone bad, these
> * insn do not set DAR so we have to do it here instead */
> - insn = *((unsigned long *)regs->nip);
> + if (get_user(insn, (unsigned long __user *)regs->nip)) {
> + printk(KERN_CRIT "get_user failed, NIP:%lx\n",
> + regs->nip);
> + goto bad_area_nosemaphore;
> + }
>
> ra = (insn >> (31-15)) & 0x1f; /* Reg RA */
> rb = (insn >> (31-20)) & 0x1f; /* Reg RB */
> @@ -206,7 +212,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
> trap, address, dar, error_code, istr);
> #endif
> address = dar;
> -#if 1
> +#if 0
> if (is_write && get_pteptr(mm, dar, &ptep, NULL)) {
> pte_t my_pte = *ptep;
>
> @@ -216,7 +222,7 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
> }
> }
> #else
> - return 0;
> + //return 0;
> #endif
> }
> }
^ permalink raw reply
* XILINX memory layout <-> physical memory
From: Thomas Rinder @ 2009-10-06 9:06 UTC (permalink / raw)
To: Linuxppc-dev
In-Reply-To: <6D81C181-23BF-4FA7-B016-779919D61957@freescale.com>
Hello,
I'm newbie in PPCLinux, don't know I'm right here.
I made a ports to an AVNET FX12 minimodul and custom board (FX40/FX60) based
on linuxppc found on http://git.xilinx.com/ (ppc405 processor).
All works fine, but I can use/configure only the half memory size available
in the dts (for instance 32Mbytes of 64Mbytes on Avnet minimodul).
Otherwise the kernel crashes if tries to mount the root file system (ext2
ramdisk).
I expect my problem is the physical memory layout and its control. I want to
understand and control the physical memory layout.
But I didn't not found documentation how the memory layout is organized in
linuxppc and
how do I control were kernel, ramdisk etc. resides in physical memory.
Could anyone give me a hint please, how-to start?
Thanks a lot,
Thomas
Ausgehende eMail ist virenfrei.
Von AVG uberpruft - www.avg.de
Version: 8.5.420 / Virendatenbank: 270.14.4/2416 - Ausgabedatum: 10/05/09
18:23:00
^ permalink raw reply
* SMU-base PowerMac and server_mode
From: Romain Goyet @ 2009-10-06 9:16 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 413 bytes --]
Hi there,
I have this Quad G5 here, running GentooPPC64. Runs fine. Had a hard time
getting it to boot without a screen attached, but I eventually managed to
(yaboot was the culprit). However, this machine is SMU-based, and I couldn't
find a way to enable the equivalent of the PMU's "server_mode" (i.e.
automatically reboot after a power failure). Is there any known way to do
that ?
Kind regards,
- Romain
[-- Attachment #2: Type: text/html, Size: 525 bytes --]
^ permalink raw reply
* Re: SMU-base PowerMac and server_mode
From: Benjamin Herrenschmidt @ 2009-10-06 10:11 UTC (permalink / raw)
To: Romain Goyet; +Cc: linuxppc-dev
In-Reply-To: <8028e5750910060216x134a8a9cm461fa5a6e87eb6bb@mail.gmail.com>
On Tue, 2009-10-06 at 11:16 +0200, Romain Goyet wrote:
> Hi there,
>
>
> I have this Quad G5 here, running GentooPPC64. Runs fine. Had a hard
> time getting it to boot without a screen attached, but I eventually
> managed to (yaboot was the culprit). However, this machine is
> SMU-based, and I couldn't find a way to enable the equivalent of the
> PMU's "server_mode" (i.e. automatically reboot after a power failure).
> Is there any known way to do that ?
I'm pretty sure I reverse engineered the necessary command a while back
and somebody wrote a userland tool to set it, but I can't find it
anymore :-)
Google may help. Let me know if you can't find it.
Cheers,
Ben.
^ permalink raw reply
* Re: SMU-base PowerMac and server_mode
From: Romain Goyet @ 2009-10-06 10:31 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1254823882.6035.5.camel@pasglop>
[-- Attachment #1: Type: text/plain, Size: 1198 bytes --]
Hi Benjamin !
Actually I saw a post where you mentioned this tool on Google. I then
searched it for like an hour or so, but really couldn't find it. That's why
I ended up posting on this mailing list. I'm really glad you're on it by the
way ! Anyway, like I said : I really looked for this tool, but couldn't find
it…
Thanks a lot !
- Romain
On Tue, Oct 6, 2009 at 12:11 PM, Benjamin Herrenschmidt <
benh@kernel.crashing.org> wrote:
> On Tue, 2009-10-06 at 11:16 +0200, Romain Goyet wrote:
> > Hi there,
> >
> >
> > I have this Quad G5 here, running GentooPPC64. Runs fine. Had a hard
> > time getting it to boot without a screen attached, but I eventually
> > managed to (yaboot was the culprit). However, this machine is
> > SMU-based, and I couldn't find a way to enable the equivalent of the
> > PMU's "server_mode" (i.e. automatically reboot after a power failure).
> > Is there any known way to do that ?
>
> I'm pretty sure I reverse engineered the necessary command a while back
> and somebody wrote a userland tool to set it, but I can't find it
> anymore :-)
>
> Google may help. Let me know if you can't find it.
>
> Cheers,
> Ben.
>
>
>
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^ permalink raw reply
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