* Re: [PATCH 1/5] powerpc/macio: Add devres support to macio_device
From: Tejun Heo @ 2009-12-01 7:20 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linux-ide, linuxppc-dev, jeff
In-Reply-To: <20091201070832.37EB8B7B65@ozlabs.org>
On 12/01/2009 04:08 PM, Benjamin Herrenschmidt wrote:
> This adds some basic devres support. When enabled via macio_enable_devres()
> resources requested by drivers will be automatically released.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Tejun Heo <tj@kernel.org>
--
tejun
^ permalink raw reply
* [PATCH 5/5] libata/drivers: Add pata_macio, driver Apple PowerMac/PowerBook IDE controller
From: Benjamin Herrenschmidt @ 2009-12-01 7:08 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
This is a libata driver for the "macio" IDE controller used on most Apple
PowerMac and PowerBooks. It's a libata equivalent of drivers/ide/ppc/pmac.c
It supports all the features of its predecessor, including mediabay hotplug
and suspend/resume. It should also support module load/unload.
The timing calculations have been simplified to use pre-calculated tables
compared to drivers/ide/pmac.c and it uses the new mediabay interface
provided by a previous patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Only lightly tested so far, this is for review, NOT for merge.
I would like to merge it eventually via the powerpc tree since there's a
few dependent patches, though I would need the libata "fix" for
bmdma_stop to go in first, unless I carry it as well with appropriate
acks.
I have addressed some of the comments from the previous version (almost a
year ago I think). I have kept the single function for the PIO and DMA
timings due to the one bit overlap between the fields in the HW register
on the shasta chipset. It seems to work fine.
drivers/ata/Kconfig | 10
drivers/ata/Makefile | 1
drivers/ata/pata_macio.c | 1390 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1401 insertions(+)
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/drivers/ata/pata_macio.c 2009-12-01 17:48:48.000000000 +1100
@@ -0,0 +1,1390 @@
+/*
+ * Libata based driver for Apple "macio" family of PATA controllers
+ *
+ * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
+ * <benh@kernel.crashing.org>
+ *
+ * Some bits and pieces from drivers/ide/ppc/pmac.c
+ *
+ */
+
+#undef DEBUG
+#undef DEBUG_DMA
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/blkdev.h>
+#include <linux/ata.h>
+#include <linux/libata.h>
+#include <linux/adb.h>
+#include <linux/pmu.h>
+#include <linux/scatterlist.h>
+#include <linux/of.h>
+
+#include <scsi/scsi.h>
+#include <scsi/scsi_host.h>
+#include <scsi/scsi_device.h>
+
+#include <asm/macio.h>
+#include <asm/io.h>
+#include <asm/dbdma.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <asm/pmac_feature.h>
+#include <asm/mediabay.h>
+
+#ifdef DEBUG_DMA
+#define dev_dbgdma(dev, format, arg...) \
+ dev_printk(KERN_DEBUG , dev , format , ## arg)
+#else
+#define dev_dbgdma(dev, format, arg...) \
+ ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
+#endif
+
+#define DRV_NAME "pata_macio"
+#define DRV_VERSION "0.9"
+
+/* Models of macio ATA controller */
+enum {
+ controller_ohare, /* OHare based */
+ controller_heathrow, /* Heathrow/Paddington */
+ controller_kl_ata3, /* KeyLargo ATA-3 */
+ controller_kl_ata4, /* KeyLargo ATA-4 */
+ controller_un_ata6, /* UniNorth2 ATA-6 */
+ controller_k2_ata6, /* K2 ATA-6 */
+ controller_sh_ata6, /* Shasta ATA-6 */
+};
+
+static const char* macio_ata_names[] = {
+ "OHare ATA", /* OHare based */
+ "Heathrow ATA", /* Heathrow/Paddington */
+ "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
+ "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
+ "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
+ "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
+ "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
+};
+
+/*
+ * Extra registers, both 32-bit little-endian
+ */
+#define IDE_TIMING_CONFIG 0x200
+#define IDE_INTERRUPT 0x300
+
+/* Kauai (U2) ATA has different register setup */
+#define IDE_KAUAI_PIO_CONFIG 0x200
+#define IDE_KAUAI_ULTRA_CONFIG 0x210
+#define IDE_KAUAI_POLL_CONFIG 0x220
+
+/*
+ * Timing configuration register definitions
+ */
+
+/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
+#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
+#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
+#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
+#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
+
+/* 133Mhz cell, found in shasta.
+ * See comments about 100 Mhz Uninorth 2...
+ * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
+ * weird and I don't now why .. at this stage
+ */
+#define TR_133_PIOREG_PIO_MASK 0xff000fff
+#define TR_133_PIOREG_MDMA_MASK 0x00fff800
+#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
+#define TR_133_UDMAREG_UDMA_EN 0x00000001
+
+/* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
+ * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
+ * controlled like gem or fw. It appears to be an evolution of keylargo
+ * ATA4 with a timing register extended to 2x32bits registers (one
+ * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
+ * It has it's own local feature control register as well.
+ *
+ * After scratching my mind over the timing values, at least for PIO
+ * and MDMA, I think I've figured the format of the timing register,
+ * though I use pre-calculated tables for UDMA as usual...
+ */
+#define TR_100_PIO_ADDRSETUP_MASK 0xff000000 /* Size of field unknown */
+#define TR_100_PIO_ADDRSETUP_SHIFT 24
+#define TR_100_MDMA_MASK 0x00fff000
+#define TR_100_MDMA_RECOVERY_MASK 0x00fc0000
+#define TR_100_MDMA_RECOVERY_SHIFT 18
+#define TR_100_MDMA_ACCESS_MASK 0x0003f000
+#define TR_100_MDMA_ACCESS_SHIFT 12
+#define TR_100_PIO_MASK 0xff000fff
+#define TR_100_PIO_RECOVERY_MASK 0x00000fc0
+#define TR_100_PIO_RECOVERY_SHIFT 6
+#define TR_100_PIO_ACCESS_MASK 0x0000003f
+#define TR_100_PIO_ACCESS_SHIFT 0
+
+#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
+#define TR_100_UDMAREG_UDMA_EN 0x00000001
+
+
+/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
+ * 40 connector cable and to 4 on 80 connector one.
+ * Clock unit is 15ns (66Mhz)
+ *
+ * 3 Values can be programmed:
+ * - Write data setup, which appears to match the cycle time. They
+ * also call it DIOW setup.
+ * - Ready to pause time (from spec)
+ * - Address setup. That one is weird. I don't see where exactly
+ * it fits in UDMA cycles, I got it's name from an obscure piece
+ * of commented out code in Darwin. They leave it to 0, we do as
+ * well, despite a comment that would lead to think it has a
+ * min value of 45ns.
+ * Apple also add 60ns to the write data setup (or cycle time ?) on
+ * reads.
+ */
+#define TR_66_UDMA_MASK 0xfff00000
+#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
+#define TR_66_PIO_ADDRSETUP_MASK 0xe0000000 /* Address setup */
+#define TR_66_PIO_ADDRSETUP_SHIFT 29
+#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
+#define TR_66_UDMA_RDY2PAUS_SHIFT 25
+#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
+#define TR_66_UDMA_WRDATASETUP_SHIFT 21
+#define TR_66_MDMA_MASK 0x000ffc00
+#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
+#define TR_66_MDMA_RECOVERY_SHIFT 15
+#define TR_66_MDMA_ACCESS_MASK 0x00007c00
+#define TR_66_MDMA_ACCESS_SHIFT 10
+#define TR_66_PIO_MASK 0xe00003ff
+#define TR_66_PIO_RECOVERY_MASK 0x000003e0
+#define TR_66_PIO_RECOVERY_SHIFT 5
+#define TR_66_PIO_ACCESS_MASK 0x0000001f
+#define TR_66_PIO_ACCESS_SHIFT 0
+
+/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
+ * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
+ *
+ * The access time and recovery time can be programmed. Some older
+ * Darwin code base limit OHare to 150ns cycle time. I decided to do
+ * the same here fore safety against broken old hardware ;)
+ * The HalfTick bit, when set, adds half a clock (15ns) to the access
+ * time and removes one from recovery. It's not supported on KeyLargo
+ * implementation afaik. The E bit appears to be set for PIO mode 0 and
+ * is used to reach long timings used in this mode.
+ */
+#define TR_33_MDMA_MASK 0x003ff800
+#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
+#define TR_33_MDMA_RECOVERY_SHIFT 16
+#define TR_33_MDMA_ACCESS_MASK 0x0000f800
+#define TR_33_MDMA_ACCESS_SHIFT 11
+#define TR_33_MDMA_HALFTICK 0x00200000
+#define TR_33_PIO_MASK 0x000007ff
+#define TR_33_PIO_E 0x00000400
+#define TR_33_PIO_RECOVERY_MASK 0x000003e0
+#define TR_33_PIO_RECOVERY_SHIFT 5
+#define TR_33_PIO_ACCESS_MASK 0x0000001f
+#define TR_33_PIO_ACCESS_SHIFT 0
+
+/*
+ * Interrupt register definitions
+ */
+#define IDE_INTR_DMA 0x80000000
+#define IDE_INTR_DEVICE 0x40000000
+
+/*
+ * FCR Register on Kauai. Not sure what bit 0x4 is ...
+ */
+#define KAUAI_FCR_UATA_MAGIC 0x00000004
+#define KAUAI_FCR_UATA_RESET_N 0x00000002
+#define KAUAI_FCR_UATA_ENABLE 0x00000001
+
+
+/* Allow up to 256 DBDMA commands per xfer */
+#define MAX_DCMDS 256
+
+/* Don't let a DMA segment go all the way to 64K */
+#define MAX_DBDMA_SEG 0xff00
+
+
+/*
+ * Wait 1s for disk to answer on IDE bus after a hard reset
+ * of the device (via GPIO/FCR).
+ *
+ * Some devices seem to "pollute" the bus even after dropping
+ * the BSY bit (typically some combo drives slave on the UDMA
+ * bus) after a hard reset. Since we hard reset all drives on
+ * KeyLargo ATA66, we have to keep that delay around. I may end
+ * up not hard resetting anymore on these and keep the delay only
+ * for older interfaces instead (we have to reset when coming
+ * from MacOS...) --BenH.
+ */
+#define IDE_WAKEUP_DELAY (1*HZ)
+
+struct pata_macio_timing;
+
+struct pata_macio_priv {
+ int kind;
+ int aapl_bus_id;
+ int cable_80 : 1;
+ int mediabay : 1;
+ struct device_node *node;
+ struct macio_dev *mdev;
+ struct pci_dev *pdev;
+ struct device *dev;
+ int irq;
+ u32 treg[2][2];
+ void __iomem *tfregs;
+ void __iomem *kauai_fcr;
+ struct dbdma_cmd * dma_table_cpu;
+ dma_addr_t dma_table_dma;
+ struct ata_host *host;
+ const struct pata_macio_timing *timings;
+};
+
+/* Previous variants of this driver used to calculate timings
+ * for various variants of the chip and use tables for others.
+ *
+ * Not only was this confusing, but in addition, it isn't clear
+ * whether our calculation code was correct. It didn't entirely
+ * match the darwin code and whatever documentation I could find
+ * on these cells
+ *
+ * I decided to entirely rely on a table instead for this version
+ * of the driver. Also, because I don't really care about derated
+ * modes and really old HW other than making it work, I'm not going
+ * to calculate / snoop timing values for something else than the
+ * standard modes.
+ */
+struct pata_macio_timing {
+ int mode;
+ u32 reg1; /* Bits to set in first timing reg */
+ u32 reg2; /* Bits to set in second timing reg */
+};
+
+static const struct pata_macio_timing pata_macio_ohare_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00074000, 0, },
+ { XFER_MW_DMA_1, 0x00221000, 0, },
+ { XFER_MW_DMA_2, 0x00211000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00074000, 0, },
+ { XFER_MW_DMA_1, 0x00221000, 0, },
+ { XFER_MW_DMA_2, 0x00211000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kl33_timings[] = {
+ { XFER_PIO_0, 0x00000526, 0, },
+ { XFER_PIO_1, 0x00000085, 0, },
+ { XFER_PIO_2, 0x00000025, 0, },
+ { XFER_PIO_3, 0x00000025, 0, },
+ { XFER_PIO_4, 0x00000025, 0, },
+ { XFER_MW_DMA_0, 0x00084000, 0, },
+ { XFER_MW_DMA_1, 0x00021800, 0, },
+ { XFER_MW_DMA_2, 0x00011800, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kl66_timings[] = {
+ { XFER_PIO_0, 0x0000038c, 0, },
+ { XFER_PIO_1, 0x0000020a, 0, },
+ { XFER_PIO_2, 0x00000127, 0, },
+ { XFER_PIO_3, 0x000000c6, 0, },
+ { XFER_PIO_4, 0x00000065, 0, },
+ { XFER_MW_DMA_0, 0x00084000, 0, },
+ { XFER_MW_DMA_1, 0x00029800, 0, },
+ { XFER_MW_DMA_2, 0x00019400, 0, },
+ { XFER_UDMA_0, 0x19100000, 0, },
+ { XFER_UDMA_1, 0x14d00000, 0, },
+ { XFER_UDMA_2, 0x10900000, 0, },
+ { XFER_UDMA_3, 0x0c700000, 0, },
+ { XFER_UDMA_4, 0x0c500000, 0, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_kauai_timings[] = {
+ { XFER_PIO_0, 0x08000a92, 0, },
+ { XFER_PIO_1, 0x0800060f, 0, },
+ { XFER_PIO_2, 0x0800038b, 0, },
+ { XFER_PIO_3, 0x05000249, 0, },
+ { XFER_PIO_4, 0x04000148, 0, },
+ { XFER_MW_DMA_0, 0x00618000, 0, },
+ { XFER_MW_DMA_1, 0x00209000, 0, },
+ { XFER_MW_DMA_2, 0x00148000, 0, },
+ { XFER_UDMA_0, 0, 0x000070c1, },
+ { XFER_UDMA_1, 0, 0x00005d81, },
+ { XFER_UDMA_2, 0, 0x00004a61, },
+ { XFER_UDMA_3, 0, 0x00003a51, },
+ { XFER_UDMA_4, 0, 0x00002a31, },
+ { XFER_UDMA_5, 0, 0x00002921, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing pata_macio_shasta_timings[] = {
+ { XFER_PIO_0, 0x0a000c97, 0, },
+ { XFER_PIO_1, 0x07000712, 0, },
+ { XFER_PIO_2, 0x040003cd, 0, },
+ { XFER_PIO_3, 0x0500028b, 0, },
+ { XFER_PIO_4, 0x0400010a, 0, },
+ { XFER_MW_DMA_0, 0x00820800, 0, },
+ { XFER_MW_DMA_1, 0x0028b000, 0, },
+ { XFER_MW_DMA_2, 0x001ca000, 0, },
+ { XFER_UDMA_0, 0, 0x00035901, },
+ { XFER_UDMA_1, 0, 0x000348b1, },
+ { XFER_UDMA_2, 0, 0x00033881, },
+ { XFER_UDMA_3, 0, 0x00033861, },
+ { XFER_UDMA_4, 0, 0x00033841, },
+ { XFER_UDMA_5, 0, 0x00033031, },
+ { XFER_UDMA_6, 0, 0x00033021, },
+ { -1, 0, 0 }
+};
+
+static const struct pata_macio_timing *pata_macio_find_timing(
+ struct pata_macio_priv *priv,
+ int mode)
+{
+ int i = 0;
+
+ while (priv->timings[i].mode > 0) {
+ if (priv->timings[i].mode == mode)
+ return &priv->timings[i];
+ i++;
+ }
+ return NULL;
+}
+
+
+static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ void __iomem *rbase = ap->ioaddr.cmd_addr;
+
+ if (priv->kind == controller_sh_ata6 ||
+ priv->kind == controller_un_ata6 ||
+ priv->kind == controller_k2_ata6) {
+ writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
+ writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
+ } else
+ writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
+}
+
+static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
+{
+ ata_sff_dev_select(ap, device);
+
+ /* Apply timings */
+ pata_macio_apply_timings(ap, device);
+}
+
+static void pata_macio_set_timings(struct ata_port *ap,
+ struct ata_device *adev)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ const struct pata_macio_timing *t;
+
+ dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
+ adev->devno,
+ adev->pio_mode,
+ ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
+ adev->dma_mode,
+ ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
+
+ /* First clear timings */
+ priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
+
+ /* Now get the PIO timings */
+ t = pata_macio_find_timing(priv, adev->pio_mode);
+ if (t == NULL) {
+ dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
+ adev->pio_mode);
+ t = pata_macio_find_timing(priv, XFER_PIO_0);
+ }
+ BUG_ON(t == NULL);
+
+ /* PIO timings only ever use the first treg */
+ priv->treg[adev->devno][0] |= t->reg1;
+
+ /* Now get DMA timings */
+ t = pata_macio_find_timing(priv, adev->dma_mode);
+ if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
+ dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
+ t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
+ }
+ BUG_ON(t == NULL);
+
+ /* DMA timings can use both tregs */
+ priv->treg[adev->devno][0] |= t->reg1;
+ priv->treg[adev->devno][1] |= t->reg2;
+
+ dev_dbg(priv->dev, " -> %08x %08x\n",
+ priv->treg[adev->devno][0],
+ priv->treg[adev->devno][1]);
+
+ /* Apply to hardware */
+ pata_macio_apply_timings(ap, adev->devno);
+}
+
+/*
+ * Blast some well known "safe" values to the timing registers at init or
+ * wakeup from sleep time, before we do real calculation
+ */
+static void pata_macio_default_timings(struct pata_macio_priv *priv)
+{
+ unsigned int value, value2 = 0;
+
+ switch(priv->kind) {
+ case controller_sh_ata6:
+ value = 0x0a820c97;
+ value2 = 0x00033031;
+ break;
+ case controller_un_ata6:
+ case controller_k2_ata6:
+ value = 0x08618a92;
+ value2 = 0x00002921;
+ break;
+ case controller_kl_ata4:
+ value = 0x0008438c;
+ break;
+ case controller_kl_ata3:
+ value = 0x00084526;
+ break;
+ case controller_heathrow:
+ case controller_ohare:
+ default:
+ value = 0x00074526;
+ break;
+ }
+ priv->treg[0][0] = priv->treg[1][0] = value;
+ priv->treg[0][1] = priv->treg[1][1] = value2;
+}
+
+static int pata_macio_cable_detect(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+
+ return priv->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
+}
+
+static void pata_macio_qc_prep(struct ata_queued_cmd *qc)
+{
+ unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct scatterlist *sg;
+ struct dbdma_cmd *table;
+ unsigned int si, pi;
+
+ dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
+ __func__, qc, qc->flags, write, qc->dev->devno);
+
+ if (!(qc->flags & ATA_QCFLAG_DMAMAP))
+ return;
+
+ table = (struct dbdma_cmd *) priv->dma_table_cpu;
+
+ pi = 0;
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
+ u32 addr, sg_len, len;
+
+ /* determine if physical DMA addr spans 64K boundary.
+ * Note h/w doesn't support 64-bit, so we unconditionally
+ * truncate dma_addr_t to u32.
+ */
+ addr = (u32) sg_dma_address(sg);
+ sg_len = sg_dma_len(sg);
+
+ while (sg_len) {
+ /* table overflow should never happen */
+ BUG_ON (pi++ >= MAX_DCMDS);
+
+ len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
+ st_le16(&table->command, write ? OUTPUT_MORE: INPUT_MORE);
+ st_le16(&table->req_count, len);
+ st_le32(&table->phy_addr, addr);
+ table->cmd_dep = 0;
+ table->xfer_status = 0;
+ table->res_count = 0;
+ addr += len;
+ sg_len -= len;
+ ++table;
+ }
+ }
+
+ /* Should never happen according to Tejun */
+ BUG_ON(!pi);
+
+ /* Convert the last command to an input/output */
+ table--;
+ st_le16(&table->command, write ? OUTPUT_LAST: INPUT_LAST);
+ table++;
+
+ /* Add the stop command to the end of the list */
+ memset(table, 0, sizeof(struct dbdma_cmd));
+ st_le16(&table->command, DBDMA_STOP);
+
+ dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
+}
+
+static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+ int dev = qc->dev->devno;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ /* Make sure DMA commands updates are visible */
+ writel(priv->dma_table_dma, &dma_regs->cmdptr);
+
+ /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
+ * UDMA reads
+ */
+ if (priv->kind == controller_kl_ata4 &&
+ (priv->treg[dev][0] & TR_66_UDMA_EN)) {
+ void __iomem *rbase = ap->ioaddr.cmd_addr;
+ u32 reg = priv->treg[dev][0];
+
+ if (!(qc->tf.flags & ATA_TFLAG_WRITE))
+ reg += 0x00800000;
+ writel(reg, rbase + IDE_TIMING_CONFIG);
+ }
+
+ /* issue r/w command */
+ ap->ops->sff_exec_command(ap, &qc->tf);
+}
+
+static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ writel((RUN << 16) | RUN, &dma_regs->control);
+ /* Make sure it gets to the controller right now */
+ (void)readl(&dma_regs->control);
+}
+
+static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
+{
+ struct ata_port *ap = qc->ap;
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+
+ dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
+
+ /* Stop the DMA engine and wait for it to full halt */
+ writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
+ while (readl(&dma_regs->status) & RUN)
+ udelay(1);
+}
+
+static u8 pata_macio_bmdma_status(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+ u32 dstat, rstat = ATA_DMA_INTR;
+ unsigned long timeout = 0;
+
+ dstat = readl(&dma_regs->status);
+
+ dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
+
+ /* We have to things to deal with here:
+ *
+ * - The dbdma won't stop if the command was started
+ * but completed with an error without transferring all
+ * datas. This happens when bad blocks are met during
+ * a multi-block transfer.
+ *
+ * - The dbdma fifo hasn't yet finished flushing to
+ * to system memory when the disk interrupt occurs.
+ *
+ */
+
+ /* First check for errors */
+ if ((dstat & (RUN|DEAD)) != RUN)
+ rstat |= ATA_DMA_ERR;
+
+ /* If ACTIVE is cleared, the STOP command has been hit and
+ * the transfer is complete. If not, we have to flush the
+ * channel.
+ */
+ if ((dstat & ACTIVE) == 0)
+ return rstat;
+
+ dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
+
+ /* If dbdma didn't execute the STOP command yet, the
+ * active bit is still set. We consider that we aren't
+ * sharing interrupts (which is hopefully the case with
+ * those controllers) and so we just try to flush the
+ * channel for pending data in the fifo
+ */
+ udelay(1);
+ writel((FLUSH << 16) | FLUSH, &dma_regs->control);
+ for (;;) {
+ udelay(1);
+ dstat = readl(&dma_regs->status);
+ if ((dstat & FLUSH) == 0)
+ break;
+ if (++timeout > 1000) {
+ dev_warn(priv->dev, "timeout flushing DMA\n");
+ rstat |= ATA_DMA_ERR;
+ break;
+ }
+ }
+ return rstat;
+}
+
+/* port_start is when we allocate the DMA command list */
+static int pata_macio_port_start(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+ struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
+
+ if (dma_regs == NULL)
+ return 0;
+
+ /* Make sure DMA controller is stopped */
+ writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
+ while (readl(&dma_regs->status) & RUN)
+ udelay(1);
+
+ /* Allocate space for the DBDMA commands.
+ *
+ * The +2 is +1 for the stop command and +1 to allow for
+ * aligning the start address to a multiple of 16 bytes.
+ */
+ priv->dma_table_cpu =
+ dmam_alloc_coherent(priv->dev,
+ (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
+ &priv->dma_table_dma, GFP_KERNEL);
+ if (priv->dma_table_cpu == NULL) {
+ dev_err(priv->dev, "Unable to allocate DMA command list\n");
+ ap->ioaddr.bmdma_addr = NULL;
+ }
+ return 0;
+}
+
+static void pata_macio_irq_clear(struct ata_port *ap)
+{
+ struct pata_macio_priv *priv = ap->private_data;
+
+ /* Nothing to do here */
+
+ dev_dbgdma(priv->dev, "%s\n", __func__);
+}
+
+static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
+{
+ dev_dbg(priv->dev, "Enabling & resetting... \n");
+
+ if (priv->mediabay)
+ return;
+
+ if (priv->kind == controller_ohare && !resume) {
+ /* The code below is having trouble on some ohare machines
+ * (timing related ?). Until I can put my hand on one of these
+ * units, I keep the old way
+ */
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
+ } else {
+ int rc;
+
+ /* Reset and enable controller */
+ rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET, priv->node, priv->aapl_bus_id, 1);
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, priv->aapl_bus_id, 1);
+ msleep(10);
+ /* Only bother waiting if there's a reset control */
+ if (rc == 0) {
+ ppc_md.feature_call(PMAC_FTR_IDE_RESET, priv->node, priv->aapl_bus_id, 0);
+ msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
+ }
+ }
+
+ /* If resuming a PCI device, restore the config space here */
+ if (priv->pdev && resume) {
+ int rc;
+
+ pci_restore_state(priv->pdev);
+ rc = pcim_enable_device(priv->pdev);
+ if (rc)
+ dev_printk(KERN_ERR, &priv->pdev->dev,
+ "Failed to enable device after resume (%d)\n", rc);
+ else
+ pci_set_master(priv->pdev);
+ }
+
+ /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
+ * seem necessary and speeds up the boot process
+ */
+ if (priv->kauai_fcr)
+ writel(KAUAI_FCR_UATA_MAGIC |
+ KAUAI_FCR_UATA_RESET_N |
+ KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
+}
+
+/* Hook the standard slave config to fixup some HW related alignment
+ * restrictions
+ */
+static int pata_macio_slave_config(struct scsi_device *sdev)
+{
+ struct ata_port *ap = ata_shost_to_port(sdev->host);
+ struct pata_macio_priv *priv = ap->private_data;
+ struct ata_device *dev;
+ u16 cmd;
+ int rc;
+
+ /* First call original */
+ rc = ata_scsi_slave_config(sdev);
+ if (rc)
+ return rc;
+
+ /* This is lifted from sata_nv */
+ dev = &ap->link.device[sdev->id];
+
+ /* OHare has issues with non cache aligned DMA on some chipsets */
+ if (priv->kind == controller_ohare) {
+ blk_queue_update_dma_alignment(sdev->request_queue, 31);
+ blk_queue_update_dma_pad(sdev->request_queue, 31);
+
+ /* Tell the world about it */
+ ata_dev_printk(dev, KERN_INFO, "OHare alignment limits applied\n");
+ return 0;
+ }
+
+ /* We only have issues with ATAPI */
+ if (dev->class != ATA_DEV_ATAPI)
+ return 0;
+
+ /* Shasta and K2 seem to have "issues" with reads ... */
+ if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
+ /* Allright these are bad, apply restrictions */
+ blk_queue_update_dma_alignment(sdev->request_queue, 15);
+ blk_queue_update_dma_pad(sdev->request_queue, 15);
+
+ /* We enable MWI and hack cache line size directly here, this
+ * is specific to this chipset and not normal values, we happen
+ * to somewhat know what we are doing here (which is basically
+ * to do the same Apple does and pray they did not get it wrong :-)
+ */
+ BUG_ON(!priv->pdev);
+ pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
+ pci_write_config_word(priv->pdev, PCI_COMMAND,
+ cmd | PCI_COMMAND_INVALIDATE);
+
+ /* Tell the world about it */
+ ata_dev_printk(dev, KERN_INFO, "K2/Shasta alignment limits applied\n");
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
+{
+ int rc;
+
+ /* First, core libata suspend to do most of the work */
+ rc = ata_host_suspend(priv->host, mesg);
+ if (rc)
+ return rc;
+
+ /* Restore to default timings */
+ pata_macio_default_timings(priv);
+
+ /* Mask interrupt. Not strictly necessary but old driver did
+ * it and I'd rather not change that here */
+ disable_irq(priv->irq);
+
+ /* The media bay will handle itself just fine */
+ if (priv->mediabay)
+ return 0;
+
+ /* Kauai has bus control FCRs directly here */
+ if (priv->kauai_fcr) {
+ u32 fcr = readl(priv->kauai_fcr);
+ fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
+ writel(fcr, priv->kauai_fcr);
+ }
+
+ /* For PCI, save state and disable DMA. No need to call
+ * pci_set_power_state(), the HW doesn't do D states that
+ * way, the platform code will take care of suspending the
+ * ASIC properly
+ */
+ if (priv->pdev) {
+ pci_save_state(priv->pdev);
+ pci_disable_device(priv->pdev);
+ }
+
+ /* Disable the bus on older machines and the cell on kauai */
+ ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
+ priv->aapl_bus_id, 0);
+
+ return 0;
+}
+
+static int pata_macio_do_resume(struct pata_macio_priv *priv)
+{
+ /* Reset and re-enable the HW */
+ pata_macio_reset_hw(priv, 1);
+
+ /* Sanitize drive timings */
+ pata_macio_apply_timings(priv->host->ports[0], 0);
+
+ /* We want our IRQ back ! */
+ enable_irq(priv->irq);
+
+ /* Let the libata core take it from there */
+ ata_host_resume(priv->host);
+
+ return 0;
+}
+
+#endif /* CONFIG_PM */
+
+static struct scsi_host_template pata_macio_sht = {
+ ATA_BASE_SHT(DRV_NAME),
+ .sg_tablesize = MAX_DCMDS,
+ .dma_boundary = ATA_DMA_BOUNDARY, /* We may not need that strict one */
+ .slave_configure = pata_macio_slave_config,
+};
+
+static struct ata_port_operations pata_macio_ops = {
+ .inherits = &ata_sff_port_ops,
+
+ .set_piomode = pata_macio_set_timings,
+ .set_dmamode = pata_macio_set_timings,
+ .cable_detect = pata_macio_cable_detect,
+ .sff_dev_select = pata_macio_dev_select,
+ .qc_prep = pata_macio_qc_prep,
+ .mode_filter = ata_bmdma_mode_filter,
+ .bmdma_setup = pata_macio_bmdma_setup,
+ .bmdma_start = pata_macio_bmdma_start,
+ .bmdma_stop = pata_macio_bmdma_stop,
+ .bmdma_status = pata_macio_bmdma_status,
+ .port_start = pata_macio_port_start,
+ .sff_irq_clear = pata_macio_irq_clear,
+};
+
+static void __devinit pata_macio_invariants(struct pata_macio_priv *priv)
+{
+ const int *bidp;
+
+ /* Identify the type of controller */
+ if (of_device_is_compatible(priv->node, "shasta-ata")) {
+ priv->kind = controller_sh_ata6;
+ priv->timings = pata_macio_shasta_timings;
+ } else if (of_device_is_compatible(priv->node, "kauai-ata")) {
+ priv->kind = controller_un_ata6;
+ priv->timings = pata_macio_kauai_timings;
+ } else if (of_device_is_compatible(priv->node, "K2-UATA")) {
+ priv->kind = controller_k2_ata6;
+ priv->timings = pata_macio_kauai_timings;
+ } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
+ if (strcmp(priv->node->name, "ata-4") == 0) {
+ priv->kind = controller_kl_ata4;
+ priv->timings = pata_macio_kl66_timings;
+ } else {
+ priv->kind = controller_kl_ata3;
+ priv->timings = pata_macio_kl33_timings;
+ }
+ } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
+ priv->kind = controller_heathrow;
+ priv->timings = pata_macio_heathrow_timings;
+ } else {
+ priv->kind = controller_ohare;
+ priv->timings = pata_macio_ohare_timings;
+ }
+
+ /* XXX FIXME --- setup priv->mediabay here */
+
+ /* Get Apple bus ID (for clock and ASIC control) */
+ bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
+ priv->aapl_bus_id = bidp ? *bidp : 0;
+
+ /* Fixup missing Apple bus ID in case of media-bay */
+ if (priv->mediabay && bidp == 0)
+ priv->aapl_bus_id = 1;
+
+ /* Get cable type from device-tree */
+ if (priv->kind == controller_kl_ata4 ||
+ priv->kind == controller_un_ata6 ||
+ priv->kind == controller_k2_ata6 ||
+ priv->kind == controller_sh_ata6) {
+ const char* cable = of_get_property(priv->node, "cable-type",
+ NULL);
+ if (cable && !strncmp(cable, "80-", 3))
+ priv->cable_80 = 1;
+ }
+
+ /* G5's seem to have incorrect cable type in device-tree.
+ * Let's assume they always have a 80 conductor cable, this seem to
+ * be always the case unless the user mucked around
+ */
+ if (of_device_is_compatible(priv->node, "K2-UATA") ||
+ of_device_is_compatible(priv->node, "shasta-ata"))
+ priv->cable_80 = 1;
+}
+
+static void __devinit pata_macio_setup_ios(struct ata_ioports *ioaddr,
+ void __iomem * base,
+ void __iomem * dma)
+{
+ /* cmd_addr is the base of regs for that port */
+ ioaddr->cmd_addr = base;
+
+ /* taskfile registers */
+ ioaddr->data_addr = base + (ATA_REG_DATA << 4);
+ ioaddr->error_addr = base + (ATA_REG_ERR << 4);
+ ioaddr->feature_addr = base + (ATA_REG_FEATURE << 4);
+ ioaddr->nsect_addr = base + (ATA_REG_NSECT << 4);
+ ioaddr->lbal_addr = base + (ATA_REG_LBAL << 4);
+ ioaddr->lbam_addr = base + (ATA_REG_LBAM << 4);
+ ioaddr->lbah_addr = base + (ATA_REG_LBAH << 4);
+ ioaddr->device_addr = base + (ATA_REG_DEVICE << 4);
+ ioaddr->status_addr = base + (ATA_REG_STATUS << 4);
+ ioaddr->command_addr = base + (ATA_REG_CMD << 4);
+ ioaddr->altstatus_addr = base + 0x160;
+ ioaddr->ctl_addr = base + 0x160;
+ ioaddr->bmdma_addr = dma;
+}
+
+static void __devinit pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
+ struct ata_port_info *pinfo)
+{
+ int i = 0;
+
+ pinfo->pio_mask = 0;
+ pinfo->mwdma_mask = 0;
+ pinfo->udma_mask = 0;
+
+ while (priv->timings[i].mode > 0) {
+ unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
+ switch(priv->timings[i].mode & 0xf0) {
+ case 0x00: /* PIO */
+ pinfo->pio_mask |= (mask >> 8);
+ break;
+ case 0x20: /* MWDMA */
+ pinfo->mwdma_mask |= mask;
+ break;
+ case 0x40: /* UDMA */
+ pinfo->udma_mask |= mask;
+ break;
+ }
+ i++;
+ }
+ dev_dbg(priv->dev, "Supported masks: PIO=%lx, MWDMA=%lx, UDMA=%lx\n",
+ pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
+}
+
+static int __devinit pata_macio_common_init(struct pata_macio_priv *priv,
+ resource_size_t tfregs,
+ resource_size_t dmaregs,
+ resource_size_t fcregs,
+ unsigned long irq)
+{
+ struct ata_port_info pinfo;
+ const struct ata_port_info *ppi[] = { &pinfo, NULL };
+ void __iomem *dma_regs = NULL;
+ int rc;
+
+ /* Fill up privates with various invariants collected from the
+ * device-tree
+ */
+ pata_macio_invariants(priv);
+
+ /* Make sure we have sane initial timings in the cache */
+ pata_macio_default_timings(priv);
+
+ /* Not sure what the real max is but we know it's less than 64K, let's
+ * use 64K minus 256
+ */
+ dma_set_max_seg_size(priv->dev, MAX_DBDMA_SEG);
+
+ /* Allocate libata host for 1 port */
+ memset(&pinfo, 0, sizeof(struct ata_port_info));
+ pmac_macio_calc_timing_masks(priv, &pinfo);
+ pinfo.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO |
+ ATA_FLAG_NO_LEGACY;
+ pinfo.port_ops = &pata_macio_ops;
+ pinfo.private_data = priv;
+
+ priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
+ if (priv->host == NULL) {
+ dev_err(priv->dev, "Failed to allocate ATA port structure\n");
+ return -ENOMEM;
+ }
+
+ lock_media_bay(priv->mdev->media_bay);
+
+ /* Setup the private data in host too */
+ priv->host->private_data = priv;
+
+ /* Map base registers */
+ priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
+ if (priv->tfregs == NULL) {
+ dev_err(priv->dev, "Failed to map ATA ports\n");
+ unlock_media_bay(priv->mdev->media_bay);
+ return -ENOMEM;
+ }
+ priv->host->iomap = &priv->tfregs;
+
+ /* Map DMA regs */
+ if (dmaregs != 0) {
+ dma_regs = devm_ioremap(priv->dev, dmaregs,
+ sizeof(struct dbdma_regs));
+ if (dma_regs == NULL)
+ dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
+ }
+
+ /* If chip has local feature control, map those regs too */
+ if (fcregs != 0) {
+ priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
+ if (priv->kauai_fcr == NULL) {
+ dev_err(priv->dev, "Failed to map ATA FCR register\n");
+ unlock_media_bay(priv->mdev->media_bay);
+ return -ENOMEM;
+ }
+ }
+
+ /* Setup port data structure */
+ pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
+ priv->tfregs, dma_regs);
+ priv->host->ports[0]->private_data = priv;
+
+ /* hard-reset the controller */
+ pata_macio_reset_hw(priv, 0);
+ pata_macio_apply_timings(priv->host->ports[0], 0);
+
+ /* Enable bus master if necessary */
+ if (priv->pdev && dma_regs)
+ pci_set_master(priv->pdev);
+
+ dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
+ macio_ata_names[priv->kind], priv->aapl_bus_id);
+
+ /* Start it up */
+ priv->irq = irq;
+ rc = ata_host_activate(priv->host, irq, ata_sff_interrupt, 0,
+ &pata_macio_sht);
+ unlock_media_bay(priv->mdev->media_bay);
+ return rc;
+}
+
+static int __devinit pata_macio_attach(struct macio_dev *mdev,
+ const struct of_device_id *match)
+{
+ struct pata_macio_priv *priv;
+ resource_size_t tfregs, dmaregs = 0;
+ unsigned long irq;
+
+ /* Check for broken device-trees */
+ if (macio_resource_count(mdev) == 0) {
+ dev_err(&mdev->ofdev.dev,
+ "No addresses for controller\n");
+ return -ENXIO;
+ }
+
+ /* Enable managed resources */
+ macio_enable_devres(mdev);
+
+ /* Allocate and init private data structure */
+ priv = devm_kzalloc(&mdev->ofdev.dev,
+ sizeof(struct pata_macio_priv), GFP_KERNEL);
+ if (priv == NULL) {
+ dev_err(&mdev->ofdev.dev,
+ "Failed to allocate private memory\n");
+ return -ENOMEM;
+ }
+ priv->node = of_node_get(mdev->ofdev.node);
+ priv->mdev = mdev;
+ priv->dev = &mdev->ofdev.dev;
+
+ /* Request memory resource for taskfile registers */
+ if (macio_request_resource(mdev, 0, "pata-macio")) {
+ dev_err(&mdev->ofdev.dev,
+ "Cannot obtain taskfile resource\n");
+ return -EBUSY;
+ }
+ tfregs = macio_resource_start(mdev, 0);
+
+ /* Request resources for DMA registers if any */
+ if (macio_resource_count(mdev) >= 2) {
+ if (macio_request_resource(mdev, 1, "pata-macio-dma"))
+ dev_err(&mdev->ofdev.dev,
+ "Cannot obtain DMA resource\n");
+ else
+ dmaregs = macio_resource_start(mdev, 1);
+ }
+
+ /*
+ * Fixup missing IRQ for some old implementations with broken
+ * device-trees.
+ *
+ * This is a bit bogus, it should be fixed in the device-tree itself,
+ * via the existing macio fixups, based on the type of interrupt
+ * controller in the machine. However, I have no test HW for this case,
+ * and this trick works well enough on those old machines...
+ */
+ if (macio_irq_count(mdev) == 0) {
+ dev_warn(&mdev->ofdev.dev,
+ "No interrupts for controller, using 13\n");
+ irq = irq_create_mapping(NULL, 13);
+ } else
+ irq = macio_irq(mdev, 0);
+
+ /* Get register addresses and call common initialization */
+ if (pata_macio_common_init(priv,
+ tfregs, /* Taskfile regs */
+ dmaregs, /* DBDMA regs */
+ 0, /* Feature control */
+ irq))
+ return -ENXIO;
+
+ return 0;
+}
+
+static int __devexit pata_macio_detach(struct macio_dev *mdev)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+
+ ata_host_detach(host);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+
+ return pata_macio_do_suspend(host->private_data, mesg);
+}
+
+static int pata_macio_resume(struct macio_dev *mdev)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+
+ return pata_macio_do_resume(host->private_data);
+}
+
+#endif /* CONFIG_PM */
+
+#ifdef CONFIG_PMAC_MEDIABAY
+static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
+{
+ struct ata_host *host = macio_get_drvdata(mdev);
+ struct ata_port *ap;
+ struct ata_eh_info *ehi;
+ struct ata_device *dev;
+ unsigned long flags;
+
+ if (!host)
+ return;
+ ap = host->ports[0];
+ spin_lock_irqsave(ap->lock, flags);
+ ehi = &ap->link.eh_info;
+ if (mb_state == MB_CD) {
+ ata_ehi_push_desc(ehi, "mediabay plug");
+ ata_ehi_hotplugged(ehi);
+ ata_port_freeze(ap);
+ } else {
+ ata_ehi_push_desc(ehi, "mediabay unplug");
+ ata_for_each_dev(dev, &ap->link, ALL)
+ dev->flags |= ATA_DFLAG_DETACH;
+ ata_port_schedule_eh(ap);
+ }
+ spin_unlock_irqrestore(ap->lock, flags);
+
+}
+#endif /* CONFIG_PMAC_MEDIABAY */
+
+
+static int __devinit pata_macio_pci_attach(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct pata_macio_priv *priv;
+ struct device_node *np;
+ resource_size_t rbase;
+
+ /* We cannot use a MacIO controller without its OF device node */
+ np = pci_device_to_OF_node(pdev);
+ if (np == NULL) {
+ dev_err(&pdev->dev,
+ "Cannot find OF device node for controller\n");
+ return -ENODEV;
+ }
+
+ /* Check that it can be enabled */
+ if (pcim_enable_device(pdev)) {
+ dev_err(&pdev->dev,
+ "Cannot enable controller PCI device\n");
+ return -ENXIO;
+ }
+
+ /* Allocate and init private data structure */
+ priv = devm_kzalloc(&pdev->dev,
+ sizeof(struct pata_macio_priv), GFP_KERNEL);
+ if (priv == NULL) {
+ dev_err(&pdev->dev,
+ "Failed to allocate private memory\n");
+ return -ENOMEM;
+ }
+ priv->node = of_node_get(np);
+ priv->pdev = pdev;
+ priv->dev = &pdev->dev;
+
+ /* Get MMIO regions */
+ if (pci_request_regions(pdev, "pata-macio")) {
+ dev_err(&pdev->dev,
+ "Cannot obtain PCI resources\n");
+ return -EBUSY;
+ }
+
+ /* Get register addresses and call common initialization */
+ rbase = pci_resource_start(pdev, 0);
+ if (pata_macio_common_init(priv,
+ rbase + 0x2000, /* Taskfile regs */
+ rbase + 0x1000, /* DBDMA regs */
+ rbase, /* Feature control */
+ pdev->irq))
+ return -ENXIO;
+
+ return 0;
+}
+
+static void __devexit pata_macio_pci_detach(struct pci_dev *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ ata_host_detach(host);
+}
+
+#ifdef CONFIG_PM
+
+static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ return pata_macio_do_suspend(host->private_data, mesg);
+}
+
+static int pata_macio_pci_resume(struct pci_dev *pdev)
+{
+ struct ata_host *host = dev_get_drvdata(&pdev->dev);
+
+ return pata_macio_do_resume(host->private_data);
+}
+
+#endif /* CONFIG_PM */
+
+static struct of_device_id pata_macio_match[] =
+{
+ {
+ .name = "IDE",
+ },
+ {
+ .name = "ATA",
+ },
+ {
+ .type = "ide",
+ },
+ {
+ .type = "ata",
+ },
+ {},
+};
+
+static struct macio_driver pata_macio_driver =
+{
+ .name = "pata-macio",
+ .match_table = pata_macio_match,
+ .probe = pata_macio_attach,
+ .remove = pata_macio_detach,
+#ifdef CONFIG_PM
+ .suspend = pata_macio_suspend,
+ .resume = pata_macio_resume,
+#endif
+#ifdef CONFIG_PMAC_MEDIABAY
+ .mediabay_event = pata_macio_mb_event,
+#endif
+ .driver = {
+ .owner = THIS_MODULE,
+ },
+};
+
+static const struct pci_device_id pata_macio_pci_match[] = {
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
+ { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
+ {},
+};
+
+static struct pci_driver pata_macio_pci_driver = {
+ .name = "pata-pci-macio",
+ .id_table = pata_macio_pci_match,
+ .probe = pata_macio_pci_attach,
+ .remove = pata_macio_pci_detach,
+#ifdef CONFIG_PM
+ .suspend = pata_macio_pci_suspend,
+ .resume = pata_macio_pci_resume,
+#endif
+ .driver = {
+ .owner = THIS_MODULE,
+ },
+};
+MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
+
+
+static int __init pata_macio_init(void)
+{
+ int rc;
+
+ if (!machine_is(powermac))
+ return -ENODEV;
+
+ rc = pci_register_driver(&pata_macio_pci_driver);
+ if (rc)
+ return rc;
+ rc = macio_register_driver(&pata_macio_driver);
+ if (rc) {
+ pci_unregister_driver(&pata_macio_pci_driver);
+ return rc;
+ }
+ return 0;
+}
+
+static void __exit pata_macio_exit(void)
+{
+ macio_unregister_driver(&pata_macio_driver);
+ pci_unregister_driver(&pata_macio_pci_driver);
+}
+
+module_init(pata_macio_init);
+module_exit(pata_macio_exit);
+
+MODULE_AUTHOR("Benjamin Herrenschmidt");
+MODULE_DESCRIPTION("Apple MacIO PATA driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
Index: linux-work/drivers/ata/Kconfig
===================================================================
--- linux-work.orig/drivers/ata/Kconfig 2009-12-01 17:48:27.000000000 +1100
+++ linux-work/drivers/ata/Kconfig 2009-12-01 17:48:48.000000000 +1100
@@ -781,5 +781,15 @@ config PATA_BF54X
If unsure, say N.
+config PATA_MACIO
+ tristate "Apple PowerMac/PowerBook internal 'MacIO' IDE"
+ depends on PPC_PMAC
+ help
+ Most IDE capable PowerMacs have IDE busses driven by a variant
+ of this controller which is part of the Apple chipset used on
+ most PowerMac models. Some models have multiple busses using
+ different chipsets, though generally, MacIO is one of them.
+
+
endif # ATA_SFF
endif # ATA
Index: linux-work/drivers/ata/Makefile
===================================================================
--- linux-work.orig/drivers/ata/Makefile 2009-12-01 17:48:27.000000000 +1100
+++ linux-work/drivers/ata/Makefile 2009-12-01 17:48:48.000000000 +1100
@@ -18,6 +18,7 @@ obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
obj-$(CONFIG_SATA_FSL) += sata_fsl.o
+obj-$(CONFIG_PATA_MACIO) += pata_macio.o
obj-$(CONFIG_PATA_ALI) += pata_ali.o
obj-$(CONFIG_PATA_AMD) += pata_amd.o
^ permalink raw reply
* [PATCH 4/5] libata/sff: Use ops->bmdma_stop instead of ata_bmdma_stop()
From: Benjamin Herrenschmidt @ 2009-12-01 7:08 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
In libata-sff, ata_sff_post_internal_cmd() directly calls ata_bmdma_stop()
instead of ap->ops->bmdma_stop(). This can be a problem for controllers
that use their own bmdma_stop for which the generic sff one isn't suitable
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
drivers/ata/libata-sff.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-work.orig/drivers/ata/libata-sff.c 2009-12-01 17:48:27.000000000 +1100
+++ linux-work/drivers/ata/libata-sff.c 2009-12-01 17:48:48.000000000 +1100
@@ -2384,7 +2384,7 @@ void ata_sff_post_internal_cmd(struct at
ap->hsm_task_state = HSM_ST_IDLE;
if (ap->ioaddr.bmdma_addr)
- ata_bmdma_stop(qc);
+ ap->ops->bmdma_stop(qc);
spin_unlock_irqrestore(ap->lock, flags);
}
^ permalink raw reply
* [PATCH 3/5] powerpc/macio: Rework hotplug media bay support
From: Benjamin Herrenschmidt @ 2009-12-01 7:08 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
The hotplug mediabay has tendrils deep into drivers/ide code
which makes a libata port reather difficult. In addition it's
ugly and could be done better.
This reworks the interface between the mediabay and the rest
of the world so that:
- Any macio_driver can now have a mediabay_event callback
which will be called when that driver sits on a mediabay and
it's been either plugged or unplugged. The device type is
passed as an argument. We can now move all the IDE cruft
into the IDE driver itself
- A check_media_bay() function can be used to take a peek
at the type of device currently in the bay if any, a cleaner
variant of the previous function with the same name.
- A pair of lock/unlock functions are exposed to allow the
IDE driver to block the hotplug callbacks during the initial
setup and probing of the bay in order to avoid nasty race
conditions.
- The mediabay code no longer needs to spin on the status
register of the IDE interface when it detects an IDE device,
this is done just fine by the IDE code itself
Overall, less code, simpler, and allows for another driver
than our old drivers/ide based one.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/include/asm/macio.h | 3
arch/powerpc/include/asm/mediabay.h | 29 +--
drivers/block/swim3.c | 39 +---
drivers/ide/pmac.c | 87 ++++++---
drivers/macintosh/mediabay.c | 328 +++++++++++++-----------------------
5 files changed, 213 insertions(+), 273 deletions(-)
--- linux-work.orig/arch/powerpc/include/asm/macio.h 2009-12-01 16:51:50.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/macio.h 2009-12-01 16:51:51.000000000 +1100
@@ -134,6 +134,9 @@ struct macio_driver
int (*resume)(struct macio_dev* dev);
int (*shutdown)(struct macio_dev* dev);
+#ifdef CONFIG_PMAC_MEDIABAY
+ void (*mediabay_event)(struct macio_dev* dev, int mb_state);
+#endif
struct device_driver driver;
};
#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
Index: linux-work/arch/powerpc/include/asm/mediabay.h
===================================================================
--- linux-work.orig/arch/powerpc/include/asm/mediabay.h 2009-12-01 16:51:11.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/mediabay.h 2009-12-01 17:50:11.000000000 +1100
@@ -17,26 +17,31 @@
#define MB_POWER 6 /* media bay contains a Power device (???) */
#define MB_NO 7 /* media bay contains nothing */
-/* Number of bays in the machine or 0 */
-extern int media_bay_count;
+struct macio_dev;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-#include <linux/ide.h>
+#ifdef CONFIG_PMAC_MEDIABAY
-int check_media_bay_by_base(unsigned long base, int what);
-/* called by IDE PMAC host driver to register IDE controller for media bay */
-int media_bay_set_ide_infos(struct device_node *which_bay, unsigned long base,
- int irq, ide_hwif_t *hwif);
-
-int check_media_bay(struct device_node *which_bay, int what);
+/* Check the content type of the bay, returns MB_NO if the bay is still
+ * transitionning
+ */
+extern int check_media_bay(struct macio_dev *bay);
+
+/* The ATA driver uses the calls below to temporarily hold on the
+ * media bay callbacks while initializing the interface
+ */
+extern void lock_media_bay(struct macio_dev *bay);
+extern void unlock_media_bay(struct macio_dev *bay);
#else
-static inline int check_media_bay(struct device_node *which_bay, int what)
+static inline int check_media_bay(struct macio_dev *bay)
{
- return -ENODEV;
+ return MB_NO;
}
+static inline void lock_media_bay(struct macio_dev *bay) { }
+static inline void unlock_media_bay(struct macio_dev *bay) { }
+
#endif
#endif /* __KERNEL__ */
Index: linux-work/drivers/macintosh/mediabay.c
===================================================================
--- linux-work.orig/drivers/macintosh/mediabay.c 2009-12-01 16:51:11.000000000 +1100
+++ linux-work/drivers/macintosh/mediabay.c 2009-12-01 17:51:32.000000000 +1100
@@ -33,15 +33,6 @@
#include <linux/adb.h>
#include <linux/pmu.h>
-
-#define MB_DEBUG
-
-#ifdef MB_DEBUG
-#define MBDBG(fmt, arg...) printk(KERN_INFO fmt , ## arg)
-#else
-#define MBDBG(fmt, arg...) do { } while (0)
-#endif
-
#define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
#define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
@@ -76,28 +67,14 @@ struct media_bay_info {
int index;
int cached_gpio;
int sleeping;
+ int user_lock;
struct mutex lock;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- ide_hwif_t *cd_port;
- void __iomem *cd_base;
- int cd_irq;
- int cd_retry;
-#endif
-#if defined(CONFIG_BLK_DEV_IDE_PMAC)
- int cd_index;
-#endif
};
#define MAX_BAYS 2
static struct media_bay_info media_bays[MAX_BAYS];
-int media_bay_count = 0;
-
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-/* check the busy bit in the media-bay ide interface
- (assumes the media-bay contains an ide device) */
-#define MB_IDE_READY(i) ((readb(media_bays[i].cd_base + 0x70) & 0x80) == 0)
-#endif
+static int media_bay_count = 0;
/*
* Wait that number of ms between each step in normal polling mode
@@ -130,21 +107,11 @@ int media_bay_count = 0;
/*
* Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
- * (or until the device is ready) before waiting for busy bit to disappear
+ * (or until the device is ready) before calling into the driver
*/
#define MB_IDE_WAIT 1000
/*
- * Timeout waiting for busy bit of an IDE device to go down
- */
-#define MB_IDE_TIMEOUT 5000
-
-/*
- * Max retries of the full power up/down sequence for an IDE device
- */
-#define MAX_CD_RETRIES 3
-
-/*
* States of a media bay
*/
enum {
@@ -153,7 +120,6 @@ enum {
mb_enabling_bay, /* enable bits set, waiting MB_RESET_DELAY */
mb_resetting, /* reset bit unset, waiting MB_SETUP_DELAY */
mb_ide_resetting, /* IDE reset bit unser, waiting MB_IDE_WAIT */
- mb_ide_waiting, /* Waiting for BUSY bit to go away until MB_IDE_TIMEOUT */
mb_up, /* Media bay full */
mb_powering_down /* Powering down (avoid too fast down/up) */
};
@@ -373,12 +339,12 @@ static inline void set_mb_power(struct m
if (onoff) {
bay->ops->power(bay, 1);
bay->state = mb_powering_up;
- MBDBG("mediabay%d: powering up\n", bay->index);
+ pr_debug("mediabay%d: powering up\n", bay->index);
} else {
/* Make sure everything is powered down & disabled */
bay->ops->power(bay, 0);
bay->state = mb_powering_down;
- MBDBG("mediabay%d: powering down\n", bay->index);
+ pr_debug("mediabay%d: powering down\n", bay->index);
}
bay->timer = msecs_to_jiffies(MB_POWER_DELAY);
}
@@ -387,107 +353,118 @@ static void poll_media_bay(struct media_
{
int id = bay->ops->content(bay);
- if (id == bay->last_value) {
- if (id != bay->content_id) {
- bay->value_count += msecs_to_jiffies(MB_POLL_DELAY);
- if (bay->value_count >= msecs_to_jiffies(MB_STABLE_DELAY)) {
- /* If the device type changes without going thru
- * "MB_NO", we force a pass by "MB_NO" to make sure
- * things are properly reset
- */
- if ((id != MB_NO) && (bay->content_id != MB_NO)) {
- id = MB_NO;
- MBDBG("mediabay%d: forcing MB_NO\n", bay->index);
- }
- MBDBG("mediabay%d: switching to %d\n", bay->index, id);
- set_mb_power(bay, id != MB_NO);
- bay->content_id = id;
- if (id == MB_NO) {
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- bay->cd_retry = 0;
-#endif
- printk(KERN_INFO "media bay %d is empty\n", bay->index);
- }
- }
- }
- } else {
+ static char *mb_content_types[] = {
+ "a floppy drive",
+ "a floppy drive",
+ "an unsuported audio device",
+ "an ATA device",
+ "an unsupported PCI device",
+ "an unknown device",
+ };
+
+ if (id != bay->last_value) {
bay->last_value = id;
bay->value_count = 0;
+ return;
}
-}
+ if (id == bay->content_id)
+ return;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
-int check_media_bay(struct device_node *which_bay, int what)
-{
- int i;
-
- for (i=0; i<media_bay_count; i++)
- if (media_bays[i].mdev && which_bay == media_bays[i].mdev->ofdev.node) {
- if ((what == media_bays[i].content_id) && media_bays[i].state == mb_up)
- return 0;
- media_bays[i].cd_index = -1;
- return -EINVAL;
+ bay->value_count += msecs_to_jiffies(MB_POLL_DELAY);
+ if (bay->value_count >= msecs_to_jiffies(MB_STABLE_DELAY)) {
+ /* If the device type changes without going thru
+ * "MB_NO", we force a pass by "MB_NO" to make sure
+ * things are properly reset
+ */
+ if ((id != MB_NO) && (bay->content_id != MB_NO)) {
+ id = MB_NO;
+ pr_debug("mediabay%d: forcing MB_NO\n", bay->index);
}
- return -ENODEV;
+ pr_debug("mediabay%d: switching to %d\n", bay->index, id);
+ set_mb_power(bay, id != MB_NO);
+ bay->content_id = id;
+ if (id >= MB_NO || id < 0)
+ printk(KERN_INFO "mediabay%d: Bay is now empty\n", bay->index);
+ else
+ printk(KERN_INFO "mediabay%d: Bay contains %s\n",
+ bay->index, mb_content_types[id]);
+ }
}
-EXPORT_SYMBOL(check_media_bay);
-int check_media_bay_by_base(unsigned long base, int what)
+int check_media_bay(struct macio_dev *baydev)
{
- int i;
+ struct media_bay_info* bay;
+ int id;
- for (i=0; i<media_bay_count; i++)
- if (media_bays[i].mdev && base == (unsigned long) media_bays[i].cd_base) {
- if ((what == media_bays[i].content_id) && media_bays[i].state == mb_up)
- return 0;
- media_bays[i].cd_index = -1;
- return -EINVAL;
- }
+ if (baydev == NULL)
+ return MB_NO;
- return -ENODEV;
+ /* This returns an instant snapshot, not locking, sine
+ * we may be called with the bay lock held. The resulting
+ * fuzzyness of the result if called at the wrong time is
+ * not actually a huge deal
+ */
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return MB_NO;
+ id = bay->content_id;
+ if (bay->state != mb_up)
+ return MB_NO;
+ if (id == MB_FD1)
+ return MB_FD;
+ return id;
}
-EXPORT_SYMBOL_GPL(check_media_bay_by_base);
+EXPORT_SYMBOL_GPL(check_media_bay);
-int media_bay_set_ide_infos(struct device_node* which_bay, unsigned long base,
- int irq, ide_hwif_t *hwif)
+void lock_media_bay(struct macio_dev *baydev)
{
- int i;
+ struct media_bay_info* bay;
- for (i=0; i<media_bay_count; i++) {
- struct media_bay_info* bay = &media_bays[i];
+ if (baydev == NULL)
+ return;
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return;
+ mutex_lock(&bay->lock);
+ bay->user_lock = 1;
+}
+EXPORT_SYMBOL_GPL(lock_media_bay);
- if (bay->mdev && which_bay == bay->mdev->ofdev.node) {
- int timeout = 5000, index = hwif->index;
-
- mutex_lock(&bay->lock);
-
- bay->cd_port = hwif;
- bay->cd_base = (void __iomem *) base;
- bay->cd_irq = irq;
-
- if ((MB_CD != bay->content_id) || bay->state != mb_up) {
- mutex_unlock(&bay->lock);
- return 0;
- }
- printk(KERN_DEBUG "Registered ide%d for media bay %d\n", index, i);
- do {
- if (MB_IDE_READY(i)) {
- bay->cd_index = index;
- mutex_unlock(&bay->lock);
- return 0;
- }
- mdelay(1);
- } while(--timeout);
- printk(KERN_DEBUG "Timeount waiting IDE in bay %d\n", i);
- mutex_unlock(&bay->lock);
- return -ENODEV;
- }
+void unlock_media_bay(struct macio_dev *baydev)
+{
+ struct media_bay_info* bay;
+
+ if (baydev == NULL)
+ return;
+ bay = macio_get_drvdata(baydev);
+ if (bay == NULL)
+ return;
+ if (bay->user_lock) {
+ bay->user_lock = 0;
+ mutex_unlock(&bay->lock);
}
+}
+EXPORT_SYMBOL_GPL(unlock_media_bay);
- return -ENODEV;
+static int mb_broadcast_hotplug(struct device *dev, void *data)
+{
+ struct media_bay_info* bay = data;
+ struct macio_dev *mdev;
+ struct macio_driver *drv;
+ int state;
+
+ if (dev->bus != &macio_bus_type)
+ return 0;
+
+ state = bay->state == mb_up ? bay->content_id : MB_NO;
+ if (state == MB_FD1)
+ state = MB_FD;
+ mdev = to_macio_device(dev);
+ drv = to_macio_driver(dev->driver);
+ if (dev->driver && drv->mediabay_event)
+ drv->mediabay_event(mdev, state);
+ return 0;
}
-EXPORT_SYMBOL_GPL(media_bay_set_ide_infos);
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
static void media_bay_step(int i)
{
@@ -497,8 +474,8 @@ static void media_bay_step(int i)
if (bay->state != mb_powering_down)
poll_media_bay(bay);
- /* If timer expired or polling IDE busy, run state machine */
- if ((bay->state != mb_ide_waiting) && (bay->timer != 0)) {
+ /* If timer expired run state machine */
+ if (bay->timer != 0) {
bay->timer -= msecs_to_jiffies(MB_POLL_DELAY);
if (bay->timer > 0)
return;
@@ -508,100 +485,50 @@ static void media_bay_step(int i)
switch(bay->state) {
case mb_powering_up:
if (bay->ops->setup_bus(bay, bay->last_value) < 0) {
- MBDBG("mediabay%d: device not supported (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: device not supported (kind:%d)\n",
+ i, bay->content_id);
set_mb_power(bay, 0);
break;
}
bay->timer = msecs_to_jiffies(MB_RESET_DELAY);
bay->state = mb_enabling_bay;
- MBDBG("mediabay%d: enabling (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: enabling (kind:%d)\n", i, bay->content_id);
break;
case mb_enabling_bay:
bay->ops->un_reset(bay);
bay->timer = msecs_to_jiffies(MB_SETUP_DELAY);
bay->state = mb_resetting;
- MBDBG("mediabay%d: waiting reset (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: releasing bay reset (kind:%d)\n",
+ i, bay->content_id);
break;
case mb_resetting:
if (bay->content_id != MB_CD) {
- MBDBG("mediabay%d: bay is up (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: bay is up (kind:%d)\n", i,
+ bay->content_id);
bay->state = mb_up;
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
break;
}
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- MBDBG("mediabay%d: waiting IDE reset (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: releasing ATA reset (kind:%d)\n",
+ i, bay->content_id);
bay->ops->un_reset_ide(bay);
bay->timer = msecs_to_jiffies(MB_IDE_WAIT);
bay->state = mb_ide_resetting;
-#else
- printk(KERN_DEBUG "media-bay %d is ide (not compiled in kernel)\n", i);
- set_mb_power(bay, 0);
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
break;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
+
case mb_ide_resetting:
- bay->timer = msecs_to_jiffies(MB_IDE_TIMEOUT);
- bay->state = mb_ide_waiting;
- MBDBG("mediabay%d: waiting IDE ready (kind:%d)\n", i, bay->content_id);
+ pr_debug("mediabay%d: bay is up (kind:%d)\n", i, bay->content_id);
+ bay->state = mb_up;
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
break;
- case mb_ide_waiting:
- if (bay->cd_base == NULL) {
- bay->timer = 0;
- bay->state = mb_up;
- MBDBG("mediabay%d: up before IDE init\n", i);
- break;
- } else if (MB_IDE_READY(i)) {
- bay->timer = 0;
- bay->state = mb_up;
- if (bay->cd_index < 0) {
- printk("mediabay %d, registering IDE...\n", i);
- pmu_suspend();
- ide_port_scan(bay->cd_port);
- if (bay->cd_port->present)
- bay->cd_index = bay->cd_port->index;
- pmu_resume();
- }
- if (bay->cd_index == -1) {
- /* We eventually do a retry */
- bay->cd_retry++;
- printk("IDE register error\n");
- set_mb_power(bay, 0);
- } else {
- printk(KERN_DEBUG "media-bay %d is ide%d\n", i, bay->cd_index);
- MBDBG("mediabay %d IDE ready\n", i);
- }
- break;
- } else if (bay->timer > 0)
- bay->timer -= msecs_to_jiffies(MB_POLL_DELAY);
- if (bay->timer <= 0) {
- printk("\nIDE Timeout in bay %d !, IDE state is: 0x%02x\n",
- i, readb(bay->cd_base + 0x70));
- MBDBG("mediabay%d: nIDE Timeout !\n", i);
- set_mb_power(bay, 0);
- bay->timer = 0;
- }
- break;
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
+
case mb_powering_down:
bay->state = mb_empty;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- if (bay->cd_index >= 0) {
- printk(KERN_DEBUG "Unregistering mb %d ide, index:%d\n", i,
- bay->cd_index);
- ide_port_unregister_devices(bay->cd_port);
- bay->cd_index = -1;
- }
- if (bay->cd_retry) {
- if (bay->cd_retry > MAX_CD_RETRIES) {
- /* Should add an error sound (sort of beep in dmasound) */
- printk("\nmedia-bay %d, IDE device badly inserted or unrecognised\n", i);
- } else {
- /* Force a new power down/up sequence */
- bay->content_id = MB_NO;
- }
- }
-#endif /* CONFIG_BLK_DEV_IDE_PMAC */
- MBDBG("mediabay%d: end of power down\n", i);
+ device_for_each_child(&bay->mdev->ofdev.dev,
+ bay, mb_broadcast_hotplug);
+ pr_debug("mediabay%d: end of power down\n", i);
break;
}
}
@@ -676,11 +603,6 @@ static int __devinit media_bay_attach(st
bay->last_value = bay->ops->content(bay);
bay->value_count = msecs_to_jiffies(MB_STABLE_DELAY);
bay->state = mb_empty;
- do {
- msleep(MB_POLL_DELAY);
- media_bay_step(i);
- } while((bay->state != mb_empty) &&
- (bay->state != mb_up));
/* Mark us ready by filling our mdev data */
macio_set_drvdata(mdev, bay);
@@ -725,7 +647,7 @@ static int media_bay_resume(struct macio
set_mb_power(bay, 0);
msleep(MB_POWER_DELAY);
if (bay->ops->content(bay) != bay->content_id) {
- printk("mediabay%d: content changed during sleep...\n", bay->index);
+ printk("mediabay%d: Content changed during sleep...\n", bay->index);
mutex_unlock(&bay->lock);
return 0;
}
@@ -733,9 +655,6 @@ static int media_bay_resume(struct macio
bay->last_value = bay->content_id;
bay->value_count = msecs_to_jiffies(MB_STABLE_DELAY);
bay->timer = msecs_to_jiffies(MB_POWER_DELAY);
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- bay->cd_retry = 0;
-#endif
do {
msleep(MB_POLL_DELAY);
media_bay_step(bay->index);
@@ -823,9 +742,6 @@ static int __init media_bay_init(void)
for (i=0; i<MAX_BAYS; i++) {
memset((char *)&media_bays[i], 0, sizeof(struct media_bay_info));
media_bays[i].content_id = -1;
-#ifdef CONFIG_BLK_DEV_IDE_PMAC
- media_bays[i].cd_index = -1;
-#endif
}
if (!machine_is(powermac))
return 0;
Index: linux-work/drivers/ide/pmac.c
===================================================================
--- linux-work.orig/drivers/ide/pmac.c 2009-12-01 16:51:11.000000000 +1100
+++ linux-work/drivers/ide/pmac.c 2009-12-01 17:50:30.000000000 +1100
@@ -59,13 +59,14 @@ typedef struct pmac_ide_hwif {
int irq;
int kind;
int aapl_bus_id;
- unsigned mediabay : 1;
unsigned broken_dma : 1;
unsigned broken_dma_warn : 1;
struct device_node* node;
struct macio_dev *mdev;
u32 timings[4];
volatile u32 __iomem * *kauai_fcr;
+ ide_hwif_t *hwif;
+
/* Those fields are duplicating what is in hwif. We currently
* can't use the hwif ones because of some assumptions that are
* beeing done by the generic code about the kind of dma controller
@@ -854,6 +855,11 @@ sanitize_timings(pmac_ide_hwif_t *pmif)
pmif->timings[2] = pmif->timings[3] = value2;
}
+static int on_media_bay(pmac_ide_hwif_t *pmif)
+{
+ return pmif->mdev && pmif->mdev->media_bay != NULL;
+}
+
/* Suspend call back, should be called after the child devices
* have actually been suspended
*/
@@ -866,7 +872,7 @@ static int pmac_ide_do_suspend(pmac_ide_
disable_irq(pmif->irq);
/* The media bay will handle itself just fine */
- if (pmif->mediabay)
+ if (on_media_bay(pmif))
return 0;
/* Kauai has bus control FCRs directly here */
@@ -889,7 +895,7 @@ static int pmac_ide_do_suspend(pmac_ide_
static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
{
/* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
- if (!pmif->mediabay) {
+ if (!on_media_bay(pmif)) {
ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
msleep(10);
@@ -950,13 +956,11 @@ static void pmac_ide_init_dev(ide_drive_
pmac_ide_hwif_t *pmif =
(pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
- if (pmif->mediabay) {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (check_media_bay_by_base(pmif->regbase, MB_CD) == 0) {
+ if (on_media_bay(pmif)) {
+ if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
return;
}
-#endif
drive->dev_flags |= IDE_DFLAG_NOPROBE;
}
}
@@ -1072,26 +1076,22 @@ static int __devinit pmac_ide_setup_devi
writel(KAUAI_FCR_UATA_MAGIC |
KAUAI_FCR_UATA_RESET_N |
KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
-
- pmif->mediabay = 0;
/* Make sure we have sane timings */
sanitize_timings(pmif);
+ /* If we are on a media bay, wait for it to settle and lock it */
+ lock_media_bay(pmif->mdev->media_bay);
+
host = ide_host_alloc(&d, hws, 1);
- if (host == NULL)
- return -ENOMEM;
- hwif = host->ports[0];
+ if (host == NULL) {
+ rc = -ENOMEM;
+ goto bail;
+ }
+ hwif = pmif->hwif = host->ports[0];
-#ifndef CONFIG_PPC64
- /* XXX FIXME: Media bay stuff need re-organizing */
- if (np->parent && np->parent->name
- && strcasecmp(np->parent->name, "media-bay") == 0) {
-#ifdef CONFIG_PMAC_MEDIABAY
- media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq,
- hwif);
-#endif /* CONFIG_PMAC_MEDIABAY */
- pmif->mediabay = 1;
+ if (on_media_bay(pmif)) {
+ /* Fixup bus ID for media bay */
if (!bidp)
pmif->aapl_bus_id = 1;
} else if (pmif->kind == controller_ohare) {
@@ -1100,9 +1100,7 @@ static int __devinit pmac_ide_setup_devi
* units, I keep the old way
*/
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
- } else
-#endif
- {
+ } else {
/* This is necessary to enable IDE when net-booting */
ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
@@ -1112,17 +1110,20 @@ static int __devinit pmac_ide_setup_devi
}
printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
- "bus ID %d%s, irq %d\n", model_name[pmif->kind],
- pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
- pmif->mediabay ? " (mediabay)" : "", hw->irq);
+ "bus ID %d%s, irq %d\n", model_name[pmif->kind],
+ pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
+ on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
rc = ide_host_register(host, &d, hws);
- if (rc) {
- ide_host_free(host);
- return rc;
- }
+ if (rc)
+ pmif->hwif = NULL;
- return 0;
+ unlock_media_bay(pmif->mdev->media_bay);
+
+ bail:
+ if (rc && host)
+ ide_host_free(host);
+ return rc;
}
static void __devinit pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
@@ -1362,6 +1363,25 @@ pmac_ide_pci_resume(struct pci_dev *pdev
return rc;
}
+#ifdef CONFIG_PMAC_MEDIABAY
+static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
+{
+ pmac_ide_hwif_t *pmif =
+ (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
+
+ switch(mb_state) {
+ case MB_CD:
+ if (!pmif->hwif->present)
+ ide_port_scan(pmif->hwif);
+ break;
+ default:
+ if (pmif->hwif->present)
+ ide_port_unregister_devices(pmif->hwif);
+ }
+}
+#endif /* CONFIG_PMAC_MEDIABAY */
+
+
static struct of_device_id pmac_ide_macio_match[] =
{
{
@@ -1386,6 +1406,9 @@ static struct macio_driver pmac_ide_maci
.probe = pmac_ide_macio_attach,
.suspend = pmac_ide_macio_suspend,
.resume = pmac_ide_macio_resume,
+#ifdef CONFIG_PMAC_MEDIABAY
+ .mediabay_event = pmac_ide_macio_mb_event,
+#endif
};
static const struct pci_device_id pmac_ide_pci_match[] = {
Index: linux-work/drivers/block/swim3.c
===================================================================
--- linux-work.orig/drivers/block/swim3.c 2009-12-01 16:51:11.000000000 +1100
+++ linux-work/drivers/block/swim3.c 2009-12-01 16:51:51.000000000 +1100
@@ -200,7 +200,7 @@ struct floppy_state {
int ejected;
wait_queue_head_t wait;
int wanted;
- struct device_node* media_bay; /* NULL when not in bay */
+ struct macio_dev *mdev;
char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
};
@@ -303,14 +303,13 @@ static int swim3_readbit(struct floppy_s
static void do_fd_request(struct request_queue * q)
{
int i;
- for(i=0;i<floppy_count;i++)
- {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (floppy_states[i].media_bay &&
- check_media_bay(floppy_states[i].media_bay, MB_FD))
+
+ for(i=0; i<floppy_count; i++) {
+ struct floppy_state *fs = &floppy_states[i];
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
continue;
-#endif /* CONFIG_PMAC_MEDIABAY */
- start_request(&floppy_states[i]);
+ start_request(fs);
}
}
@@ -849,10 +848,9 @@ static int floppy_ioctl(struct block_dev
if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
return -EPERM;
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
switch (cmd) {
case FDEJECT:
@@ -876,10 +874,9 @@ static int floppy_open(struct block_devi
int n, err = 0;
if (fs->ref_count == 0) {
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
out_8(&sw->control_bic, 0xff);
out_8(&sw->mode, 0x95);
@@ -963,10 +960,9 @@ static int floppy_revalidate(struct gend
struct swim3 __iomem *sw;
int ret, n;
-#ifdef CONFIG_PMAC_MEDIABAY
- if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
+ if (fs->mdev->media_bay &&
+ check_media_bay(fs->mdev->media_bay) != MB_FD)
return -ENXIO;
-#endif
sw = fs->swim3;
grab_drive(fs, revalidating, 0);
@@ -1009,7 +1005,6 @@ static const struct block_device_operati
static int swim3_add_device(struct macio_dev *mdev, int index)
{
struct device_node *swim = mdev->ofdev.node;
- struct device_node *mediabay;
struct floppy_state *fs = &floppy_states[index];
int rc = -EBUSY;
@@ -1036,9 +1031,7 @@ static int swim3_add_device(struct macio
}
dev_set_drvdata(&mdev->ofdev.dev, fs);
- mediabay = (strcasecmp(swim->parent->type, "media-bay") == 0) ?
- swim->parent : NULL;
- if (mediabay == NULL)
+ if (mdev->media_bay == NULL)
pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
memset(fs, 0, sizeof(*fs));
@@ -1068,7 +1061,7 @@ static int swim3_add_device(struct macio
fs->secpercyl = 36;
fs->secpertrack = 18;
fs->total_secs = 2880;
- fs->media_bay = mediabay;
+ fs->mdev = mdev;
init_waitqueue_head(&fs->wait);
fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
@@ -1093,7 +1086,7 @@ static int swim3_add_device(struct macio
init_timer(&fs->timeout);
printk(KERN_INFO "fd%d: SWIM3 floppy controller %s\n", floppy_count,
- mediabay ? "in media bay" : "");
+ mdev->media_bay ? "in media bay" : "");
return 0;
^ permalink raw reply
* [PATCH 2/5] powerpc/macio: Add dma_parms support to macio
From: Benjamin Herrenschmidt @ 2009-12-01 7:08 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
This adds dma_parms to macio devices and initializes them with
default values. This will allow pata_macio to setup the appropriate
max segment size for the block layer.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/include/asm/macio.h | 1 +
drivers/macintosh/macio_asic.c | 5 +++++
2 files changed, 6 insertions(+)
--- linux-work.orig/arch/powerpc/include/asm/macio.h 2009-11-27 14:38:05.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/macio.h 2009-11-27 14:38:20.000000000 +1100
@@ -39,6 +39,7 @@ struct macio_dev
struct macio_bus *bus; /* macio bus this device is on */
struct macio_dev *media_bay; /* Device is part of a media bay */
struct of_device ofdev;
+ struct device_dma_parameters dma_parms; /* ide needs that */
int n_resources;
struct resource resource[MACIO_DEV_COUNT_RESOURCES];
int n_interrupts;
Index: linux-work/drivers/macintosh/macio_asic.c
===================================================================
--- linux-work.orig/drivers/macintosh/macio_asic.c 2009-11-27 14:39:24.000000000 +1100
+++ linux-work/drivers/macintosh/macio_asic.c 2009-11-27 16:37:39.000000000 +1100
@@ -379,6 +379,11 @@ static struct macio_dev * macio_add_one_
dev->ofdev.dev.parent = parent;
dev->ofdev.dev.bus = &macio_bus_type;
dev->ofdev.dev.release = macio_release_dev;
+ dev->ofdev.dev.dma_parms = &dev->dma_parms;
+
+ /* Standard DMA paremeters */
+ dma_set_max_seg_size(&dev->ofdev.dev, 65536);
+ dma_set_seg_boundary(&dev->ofdev.dev, 0xffffffff);
#ifdef CONFIG_PCI
/* Set the DMA ops to the ones from the PCI device, this could be
^ permalink raw reply
* [PATCH 1/5] powerpc/macio: Add devres support to macio_device
From: Benjamin Herrenschmidt @ 2009-12-01 7:08 UTC (permalink / raw)
To: linux-ide; +Cc: tj, linuxppc-dev, jeff
This adds some basic devres support. When enabled via macio_enable_devres()
resources requested by drivers will be automatically released.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/include/asm/macio.h | 2 +
drivers/macintosh/macio_asic.c | 47 +++++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
--- linux-work.orig/arch/powerpc/include/asm/macio.h 2009-11-30 12:48:33.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/macio.h 2009-11-30 14:16:55.000000000 +1100
@@ -78,6 +78,8 @@ static inline unsigned long macio_resour
return res->end - res->start + 1;
}
+extern int macio_enable_devres(struct macio_dev *dev);
+
extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
extern void macio_release_resource(struct macio_dev *dev, int resource_no);
extern int macio_request_resources(struct macio_dev *dev, const char *name);
Index: linux-work/drivers/macintosh/macio_asic.c
===================================================================
--- linux-work.orig/drivers/macintosh/macio_asic.c 2009-11-30 12:41:12.000000000 +1100
+++ linux-work/drivers/macintosh/macio_asic.c 2009-11-30 14:17:19.000000000 +1100
@@ -538,6 +538,42 @@ void macio_unregister_driver(struct maci
driver_unregister(&drv->driver);
}
+/* Managed MacIO resources */
+struct macio_devres {
+ u32 res_mask;
+};
+
+static void maciom_release(struct device *gendev, void *res)
+{
+ struct macio_dev *dev = to_macio_device(gendev);
+ struct macio_devres *dr = res;
+ int i, max;
+
+ max = min(dev->n_resources, 32);
+ for (i = 0; i < max; i++) {
+ if (dr->res_mask & (1 << i))
+ macio_release_resource(dev, i);
+ }
+}
+
+int macio_enable_devres(struct macio_dev *dev)
+{
+ struct macio_devres *dr;
+
+ dr = devres_find(&dev->ofdev.dev, maciom_release, NULL, NULL);
+ if (!dr) {
+ dr = devres_alloc(maciom_release, sizeof(*dr), GFP_KERNEL);
+ if (!dr)
+ return -ENOMEM;
+ }
+ return devres_get(&dev->ofdev.dev, dr, NULL, NULL) != NULL;
+}
+
+static struct macio_devres * find_macio_dr(struct macio_dev *dev)
+{
+ return devres_find(&dev->ofdev.dev, maciom_release, NULL, NULL);
+}
+
/**
* macio_request_resource - Request an MMIO resource
* @dev: pointer to the device holding the resource
@@ -555,6 +591,8 @@ void macio_unregister_driver(struct maci
int macio_request_resource(struct macio_dev *dev, int resource_no,
const char *name)
{
+ struct macio_devres *dr = find_macio_dr(dev);
+
if (macio_resource_len(dev, resource_no) == 0)
return 0;
@@ -562,6 +600,9 @@ int macio_request_resource(struct macio_
macio_resource_len(dev, resource_no),
name))
goto err_out;
+
+ if (dr && resource_no < 32)
+ dr->res_mask |= 1 << resource_no;
return 0;
@@ -582,10 +623,14 @@ err_out:
*/
void macio_release_resource(struct macio_dev *dev, int resource_no)
{
+ struct macio_devres *dr = find_macio_dr(dev);
+
if (macio_resource_len(dev, resource_no) == 0)
return;
release_mem_region(macio_resource_start(dev, resource_no),
macio_resource_len(dev, resource_no));
+ if (dr && resource_no < 32)
+ dr->res_mask &= ~(1 << resource_no);
}
/**
@@ -744,3 +789,5 @@ EXPORT_SYMBOL(macio_request_resource);
EXPORT_SYMBOL(macio_release_resource);
EXPORT_SYMBOL(macio_request_resources);
EXPORT_SYMBOL(macio_release_resources);
+EXPORT_SYMBOL(macio_enable_devres);
+
^ permalink raw reply
* RE: ep440xs board boot problem
From: Tirumala Reddy Marri @ 2009-12-01 5:49 UTC (permalink / raw)
To: Allan Wang, linuxppc-dev
In-Reply-To: <288168.33010.qm@web52902.mail.re2.yahoo.com>
SXQgY291bGQgYmUgcmFtZGlzayBzaXplIGlzc3VlLiAgaWYgaXQgaXMgYmlnZ2VyIHRoYW4gNE1C
IHlvdSBtaWdodCBoYXZlIHRvIHBhc3MgcmFtaWRpc2tfc2l6ZT0xMDAwMDAgKDEwME1CIG9yID4g
eW91ciByYW1kaXNrIHNpemUpLg0KDQotLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KRnJvbTog
bGludXhwcGMtZGV2LWJvdW5jZXMrdG1hcnJpPWFtY2MuY29tQGxpc3RzLm96bGFicy5vcmcgW21h
aWx0bzpsaW51eHBwYy1kZXYtYm91bmNlcyt0bWFycmk9YW1jYy5jb21AbGlzdHMub3psYWJzLm9y
Z10gT24gQmVoYWxmIE9mIEFsbGFuIFdhbmcNClNlbnQ6IE1vbmRheSwgTm92ZW1iZXIgMzAsIDIw
MDkgOTozNSBQTQ0KVG86IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnDQpTdWJqZWN0OiBl
cDQ0MHhzIGJvYXJkIGJvb3QgcHJvYmxlbQ0KDQpIZWxsbywgQWxsLA0KDQpJIGFtIG5ldyB0byB0
aGUgbGlzdC4gSSBhbSBzdGlsbCBuZXdiaWUgdG8gZW1iZWRkZWQgbGludXguIEkgaGF2ZSBib3Vn
aHQgYW4gZXA0NDB4cyBib2FyZCB3aGljaCBpcyBzaW1pbGFyIHRvIHNlcXVvaWEgYm9hcmQuIHUt
Ym9vdCBpcyB3b3JraW5nLiBJIGFtIHRyeWluZyB0byBtYWtlIGl0IHJ1biBsaW51eC4gIEkgaGF2
ZSB0aGUgZm9sbG93aW5nIHByb2JsZW1zIGFuZCBuZWVkIHlvdXIgaGVscC4gVGhhbmsgeW91IHZl
cnkgbXVjaDoNCg0KDQpJIGFtIHVzaW5nIGxpbnV4IGtlcm5lbCAyLjYuMzAuNC4gSSBlbmNvdW50
ZXIgMiBwcm9ibGVtczoNCjEuIEFmdGVyIGNvbnNvbGVfaW5pdCgpIGlzIGNhbGxlZCBpbnNpZGUg
c3RhcnRfa2VybmVsKCksIHRoZSBjb25zb2xlIHN0YXJ0cyBwcmludGluZyBnYXJiYWdlIGxpa2U6
DQpTZXJpYWw6IDgyNTAvMTY1NTAgZHJpdmVyLCA0IHBvcnRzLCBJUlEgc2hhcmluZyBlbmFibGVk
DQpzZXJpYWw4MjUwLjA6IHR0eVMwIGF0IE1NSU8gMHgxZWY2MDAzMDAgKGlycSA9IDE2KSBpcyBh
IDE2NTUwQQ0K77+977+977+977+977+977+977+977+977+977+977+977+977+977+977+977+9
77+977+977+977+977+977+977+977+977+977+977+977+977+977+9DQrvv73vv73vv73vv73v
v73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv73v
v73vv73vv73vv73vv70NCu+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/
ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/ve+/
vQ0K77+977+977+977+977+977+977+977+977+977+977+977+977+977+977+977+977+977+9
77+977+977+977+977+977+977+977+977+977+977+977+9DQrvv73vv73vv73vv73vv73vv73v
v73vv73vv73vv73vv73vv73vv73vv73vv73vv73vv70uDQoyLiBJdCBwYWtpY3Mgd2hlbiBtb3Vu
dGluZyB0aGUgcm9vdCBmaWxlIHN5c3RlbShORlMpOg0KKGdkYikgYnQNCiMwICBwYW5pYyAoZm10
PTB4YzAyOTBlOTQgIlZGUzogVW5hYmxlIHRvIG1vdW50IHJvb3QgZnMgb24gJXMiKQ0KYXQga2Vy
bmVsL3BhbmljLmM6NzANCiMxICAweGMwMmQ4Y2UwIGluIG1vdW50X2Jsb2NrX3Jvb3QgKG5hbWU9
MHhjMDI5MGRlNCAiL2Rldi9yb290IiwgZmxhZ3M9MHg4MDAxKQ0KYXQgaW5pdC9kb19tb3VudHMu
YzoyNzINCiMyICAweGMwMmQ5MDg0IGluIHByZXBhcmVfbmFtZXNwYWNlICgpIGF0IGluaXQvZG9f
bW91bnRzLmM6NDE1DQojMyAgMHhjMDJkODFlYyBpbiBrZXJuZWxfaW5pdCAodW51c2VkPTx2YWx1
ZSBvcHRpbWl6ZWQgb3V0PikgYXQgaW5pdC9tYWluLmM6ODg1DQojNCAgMHhjMDAwZGU2MCBpbiBr
ZXJuZWxfdGhyZWFkICgpDQpUaGVyZSBpcyBhIHBhdGNoIGZvciBTZXF1b2lhIGJvYXJkIHRvIGRl
bGV0ZSAvY2hvc2VuIHBhcnQgaW4gc2VxdW9pYS5kdHMsIGlzIC9jaG9zZW4gcmVxdWlyZWQ/DQoN
CkFsbGFuDQoNCg0KDQogICAgICANCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fDQpMaW51eHBwYy1kZXYgbWFpbGluZyBsaXN0DQpMaW51eHBwYy1kZXZAbGlz
dHMub3psYWJzLm9yZw0KaHR0cHM6Ly9saXN0cy5vemxhYnMub3JnL2xpc3RpbmZvL2xpbnV4cHBj
LWRldg0K
^ permalink raw reply
* Re: Ethernet issues with lite5200 board from linux-2.6.31
From: Yogesh Chaudhari @ 2009-12-01 5:48 UTC (permalink / raw)
To: Grant Likely
Cc: Robin Gareus, rt-users, Fernando Lopez-Lezcano, Peter Zijlstra,
Frank Rowand, Philippe Reynes, Mark Knecht, LKML, Steven Rostedt,
Sven-Thorsten Dietrich, linuxppc-dev, Clark Williams, Darren Hart,
Will Schmidt, Jon Masters, John Kacur, Ingo Molnar, Jan Blunck,
Gregory Haskins
In-Reply-To: <fa686aa40911300759h153b3300uc54b5d1871bfc839@mail.gmail.com>
Hello Grant,
2009/11/30 Grant Likely <grant.likely@secretlab.ca>:
> On Mon, Nov 30, 2009 at 2:50 AM, Yogesh Chaudhari <mr.yogesh@gmail.com> w=
rote:
>> Hello,
>> =A0 =A0 =A0 =A0 I am running linux kernel with rt patch on embedded boar=
d
>> based on lite5200 eval board. From linux-2.6.31 release, in which the
>> mdio patch has gone inside, =A0the fec ethernet does not come up on this
>> board. I get the following message at startup:
>> mpc52xx MII bus: probed
>> mdio_bus f0003000: error probing PHY at address 1
>>
>>
>> After the bootup if I try to do a ifconfig I get the message:
>> net eth2: of_phy_connect failed
>>
>>
>> If I change the value of reg in dts file (lite5200.dts) to 0 then this
>> ethernet comes up. However upto this kernel version, this was not
>> required.
>>
>> Ethernet does not come up on board with original lite5200.dts file
>
> Is your board based on the Lite5200 or the Lite5200B? =A0The phys are at
> different addresses on those two revisions of the board. =A0There is a
> different .dts file for each board.
>
>> phy0: ethernet-phy@1 {
>> =A0=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =
=3D <1>;
>> =A0=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>>
>> Ethernet comes up on board with this change
>> phy0: ethernet-phy@1 {
>> =A0=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =
=3D <0>;
>> =A0=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> Some PHYs treat address 0 as the 'broadcast' address. =A0You need to
> fill in this field (and modify the ethernet-phy@<address> node name)
> to reflect the address that your phy is actually at.
This change in reg value was not required till 2.6.31. It is only
after this version that the change is needed. Is there some change in
31 that makes this change mandatory?
>
> g.
>
--=20
DREAM IT, CODE IT
"CODITO, ERGO SUM"
"I CODE, THEREFORE I AM"
^ permalink raw reply
* Re: [RFC PATCH v3 3/3] powerpc: gamecube/wii: early debugging using usbgecko
From: Albert Herranz @ 2009-12-01 5:45 UTC (permalink / raw)
To: michael; +Cc: Richard Holden, linuxppc-dev
In-Reply-To: <1259646011.4502.4.camel@concordia>
Michael Ellerman wrote:
>>> you may want to rename the ug_ prefix, it took me a while looking back
>>> and forth through the patch to convince myself it wasn't a typo.
>>>
>> What's wrong with ug_ ? (ug = (u)sb(g)ecko)
>
> What's wrong with usb_gecko_early_remap() :)
>
Nothing, except that names end up been way long for my taste (like for example usb_gecko_early_grab_exi_io_base())
I prefer to use a shorter prefix consistently.
But that's my taste :)
Cheers,
Albert
^ permalink raw reply
* Re: [RFC PATCH v3 3/3] powerpc: gamecube/wii: early debugging using usbgecko
From: Michael Ellerman @ 2009-12-01 5:40 UTC (permalink / raw)
To: Albert Herranz; +Cc: Richard Holden, linuxppc-dev
In-Reply-To: <4B14A834.4070907@yahoo.es>
[-- Attachment #1: Type: text/plain, Size: 1020 bytes --]
On Tue, 2009-12-01 at 06:23 +0100, Albert Herranz wrote:
> Richard Holden wrote:
> >> diff --git a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
> >> index ba4c7cc..3f125b6 100644
> >> --- a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
> >> +++ b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
> >> @@ -17,6 +17,7 @@
> >> #include <asm/io.h>
> >> #include <asm/prom.h>
> >> #include <asm/udbg.h>
> >> +#include <asm/fixmap.h>
> >>
> >> #include "usbgecko_udbg.h"
> >>
> >> @@ -270,3 +271,61 @@ done:
> >> of_node_put(np);
> >> return;
> >> }
> >> +
> >> +#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
> >> +
> >> +static void __init ug_early_remap(void)
> >
> > you may want to rename the ug_ prefix, it took me a while looking back
> > and forth through the patch to convince myself it wasn't a typo.
> >
>
> What's wrong with ug_ ? (ug = (u)sb(g)ecko)
What's wrong with usb_gecko_early_remap() :)
cheers
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* RE: [PATCH v3 3/3] powerpc/fsl: 85xx: add cache-sram support
From: Mahajan Vivek-B08308 @ 2009-12-01 5:36 UTC (permalink / raw)
To: Wood Scott-B07421; +Cc: linuxppc-dev, Gala Kumar-B11780
In-Reply-To: <20091120173859.GC18967@loki.buserror.net>
> From: Wood Scott-B07421=20
> Sent: Friday, November 20, 2009 11:09 PM
> > Cache-sram does not have any device tree entry since it is not a=20
> > hardware as such. Putting it under chosen can be another option.
> > I think, Scott (cc'ed) was of the opinion that since 32b=20
> base address=20
> > support is missing; so there is no point in moving this=20
> address to the=20
> > command line and .config should be okay for now for it.
>=20
> I don't know what you mean by "32b base address support is=20
> missing". I have no objection to putting it on the command line.
It was a typo, it should be missing 36b address support. Since the
kernel=20
did not run under different environment (i.e 32b / 36b base address); so
it=20
was decided that .config may be okay for this.
>=20
> -Scott
>=20
Thanks,
Vivek
^ permalink raw reply
* ep440xs board boot problem
From: Allan Wang @ 2009-12-01 5:35 UTC (permalink / raw)
To: linuxppc-dev
Hello, All,=0A=0AI am new to the list. I am still newbie to embedded linux.=
I have bought an ep440xs board which is similar to sequoia board. u-boot i=
s working. I am trying to make it run linux. I have the following problems=
and need your help. Thank you very much:=0A=0A=0AI am using linux kernel 2=
.6.30.4. I encounter 2 problems:=0A1. After console_init() is called inside=
start_kernel(), the console starts printing garbage like:=0ASerial: 8250/1=
6550 driver, 4 ports, IRQ sharing enabled=0Aserial8250.0: ttyS0 at MMIO 0x1=
ef600300 (irq =3D 16) is a 16550A=0A=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=
=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=
=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=
=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=
=BF=BD=0A=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=
=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=
=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=
=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=0A=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=
=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=
=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=
=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=
=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=0A=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=
=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=
=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=
=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=
=EF=BF=BD=0A=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=
=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=
=BF=BD=EF=BF=BD.=0A2. It pakics when mounting the root file system(NFS):=0A=
(gdb) bt=0A#0 panic (fmt=3D0xc0290e94 "VFS: Unable to mount root fs on %s"=
)=0Aat kernel/panic.c:70=0A#1 0xc02d8ce0 in mount_block_root (name=3D0xc02=
90de4 "/dev/root", flags=3D0x8001)=0Aat init/do_mounts.c:272=0A#2 0xc02d90=
84 in prepare_namespace () at init/do_mounts.c:415=0A#3 0xc02d81ec in kern=
el_init (unused=3D<value optimized out>) at init/main.c:885=0A#4 0xc000de6=
0 in kernel_thread ()=0AThere is a patch for Sequoia board to delete /chose=
n part in sequoia.dts, is /chosen required?=0A=0AAllan=0A=0A=0A=0A
^ permalink raw reply
* Re: [RFC PATCH v3 3/3] powerpc: gamecube/wii: early debugging using usbgecko
From: Albert Herranz @ 2009-12-01 5:23 UTC (permalink / raw)
To: Richard Holden; +Cc: linuxppc-dev
In-Reply-To: <4B147086.6070602@gmail.com>
Richard Holden wrote:
> Albert Herranz wrote:
>> Add support for using the USB Gecko adapter as an early debugging
>> console on the Nintendo GameCube and Wii video game consoles.
>> The USB Gecko is a 3rd party memory card interface adapter that provides
>> a EXI (External Interface) to USB serial converter.
>>
>> Signed-off-by: Albert Herranz <albert_herranz@yahoo.es>
>> ---
>> arch/powerpc/Kconfig.debug | 8 +++
>> arch/powerpc/include/asm/udbg.h | 1 +
>> arch/powerpc/kernel/head_32.S | 21 +++++++
>> arch/powerpc/kernel/udbg.c | 2 +
>> arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c | 59 ++++++++++++++++++++
>> arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h | 2 +
>> 6 files changed, 93 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
>> index 3b10051..11e385b 100644
>> --- a/arch/powerpc/Kconfig.debug
>> +++ b/arch/powerpc/Kconfig.debug
>> @@ -254,6 +254,14 @@ config PPC_EARLY_DEBUG_CPM
>> using a CPM-based serial port. This assumes that the bootwrapper
>> has run, and set up the CPM in a particular way.
>>
>> +config PPC_EARLY_DEBUG_USBGECKO
>> + bool "Early debugging through the USB Gecko adapter"
>> + depends on GAMECUBE_COMMON
>> + select USBGECKO_UDBG
>> + help
>> + Select this to enable early debugging for Nintendo GameCube/Wii
>> + consoles via an external USB Gecko adapter.
>> +
>> endchoice
>>
>> config PPC_EARLY_DEBUG_44x_PHYSLOW
>
> Small nit, my preference would be for this to be in the patch 1 where it
> is first referenced.
>
The first patch is generic, and uses PPC_EARLY_DEBUG.
This is the first patch where PPC_EARLY_DEBUG_USBGECKO is referenced.
>> diff --git a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
>> index ba4c7cc..3f125b6 100644
>> --- a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
>> +++ b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
>> @@ -17,6 +17,7 @@
>> #include <asm/io.h>
>> #include <asm/prom.h>
>> #include <asm/udbg.h>
>> +#include <asm/fixmap.h>
>>
>> #include "usbgecko_udbg.h"
>>
>> @@ -270,3 +271,61 @@ done:
>> of_node_put(np);
>> return;
>> }
>> +
>> +#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
>> +
>> +static void __init ug_early_remap(void)
>
> you may want to rename the ug_ prefix, it took me a while looking back
> and forth through the patch to convince myself it wasn't a typo.
>
What's wrong with ug_ ? (ug = (u)sb(g)ecko)
> -Richard Holden
>
Thanks,
Albert
^ permalink raw reply
* Re: [PATCH] ppc64: re-enable kexec to allow module loads with CONFIG_MODVERSIONS and CONFIG_RELOCATABLE turned on
From: Rusty Russell @ 2009-12-01 2:58 UTC (permalink / raw)
To: Neil Horman; +Cc: linuxppc-dev, paulus, linux-kernel
In-Reply-To: <20091130181600.GA11583@hmsreliant.think-freely.org>
On Tue, 1 Dec 2009 04:46:00 am Neil Horman wrote:
> Paul, Ben, given that Rusty hasn't come back with any opinion on this patch, do you
> feel comfortable merging it via the ppc tree? Currently the earlyinit routine
> is only compiled in and used for your arch, so I think its fairly benign.
Sorry, I *did* track down the archives for linuxppc-dev, then find your post,
then read your patch. But I didn't actually reply.
Other than minor issues, there's one significant one: you shouldn't be trying
to change rodata. It might work on PPC today, but it's poor form at least.
How's this? Untested on ppc.
Other changes:
1) I also changed reloc_start to an array; this is a good idea for any
linker-defined symbols so the compiler can't make assumptions about size.
2) local.h? How about module.h?
3) I don't think the extra ". = 0" is necessary.
4) ARCH_USES_RELOC_ENTRIES isn't clear enough for me; I prefer
ARCH_RELOCATE_KCRCTAB.
module: handle ppc64 relocating kcrctabs when CONFIG_RELOCATABLE=y
http://lists.ozlabs.org/pipermail/linuxppc-dev/2009-November/077972.html
Inspired-by: Neil Horman <nhorman@tuxdriver.com>
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
diff --git a/arch/powerpc/include/asm/module.h b/arch/powerpc/include/asm/module.h
--- a/arch/powerpc/include/asm/module.h
+++ b/arch/powerpc/include/asm/module.h
@@ -87,5 +87,10 @@ struct exception_table_entry;
void sort_ex_table(struct exception_table_entry *start,
struct exception_table_entry *finish);
+#ifdef CONFIG_MODVERSIONS
+#define ARCH_RELOCATES_KCRCTAB
+
+extern const unsigned long reloc_start[];
+#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MODULE_H */
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -38,6 +38,9 @@ jiffies = jiffies_64 + 4;
#endif
SECTIONS
{
+ . = 0;
+ reloc_start = .;
+
. = KERNELBASE;
/*
diff --git a/kernel/module.c b/kernel/module.c
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -1030,11 +1030,23 @@ static int try_to_force_load(struct modu
}
#ifdef CONFIG_MODVERSIONS
+/* If the arch applies (non-zero) relocations to kernel kcrctab, unapply it. */
+static unsigned long maybe_relocated(unsigned long crc,
+ const struct module *crc_owner)
+{
+#ifdef ARCH_RELOCATES_KCRCTAB
+ if (crc_owner == NULL)
+ return crc - (unsigned long)reloc_start;
+#endif
+ return crc;
+}
+
static int check_version(Elf_Shdr *sechdrs,
unsigned int versindex,
const char *symname,
struct module *mod,
- const unsigned long *crc)
+ const unsigned long *crc,
+ const struct module *crc_owner)
{
unsigned int i, num_versions;
struct modversion_info *versions;
@@ -1055,10 +1067,10 @@ static int check_version(Elf_Shdr *sechd
if (strcmp(versions[i].name, symname) != 0)
continue;
- if (versions[i].crc == *crc)
+ if (versions[i].crc == maybe_relocated(*crc, crc_owner))
return 1;
DEBUGP("Found checksum %lX vs module %lX\n",
- *crc, versions[i].crc);
+ maybe_relocated(*crc, crc_owner), versions[i].crc);
goto bad_version;
}
@@ -1081,7 +1093,8 @@ static inline int check_modstruct_versio
if (!find_symbol(MODULE_SYMBOL_PREFIX "module_layout", NULL,
&crc, true, false))
BUG();
- return check_version(sechdrs, versindex, "module_layout", mod, crc);
+ return check_version(sechdrs, versindex, "module_layout", mod, crc,
+ NULL);
}
/* First part is kernel version, which we ignore if module has crcs. */
@@ -1099,7 +1112,8 @@ static inline int check_version(Elf_Shdr
unsigned int versindex,
const char *symname,
struct module *mod,
- const unsigned long *crc)
+ const unsigned long *crc,
+ const struct module *crc_owner)
{
return 1;
}
@@ -1134,8 +1148,8 @@ static const struct kernel_symbol *resol
/* use_module can fail due to OOM,
or module initialization or unloading */
if (sym) {
- if (!check_version(sechdrs, versindex, name, mod, crc) ||
- !use_module(mod, owner))
+ if (!check_version(sechdrs, versindex, name, mod, crc, owner)
+ || !use_module(mod, owner))
sym = NULL;
}
return sym;
^ permalink raw reply
* Re: [RFC PATCH v3 3/3] powerpc: gamecube/wii: early debugging using usbgecko
From: Richard Holden @ 2009-12-01 1:25 UTC (permalink / raw)
To: Albert Herranz; +Cc: linuxppc-dev
In-Reply-To: <86935119c483c2d6e4c810c0afd079e049443b18.1259609263.git.albert_herranz@yahoo.es>
Albert Herranz wrote:
> Add support for using the USB Gecko adapter as an early debugging
> console on the Nintendo GameCube and Wii video game consoles.
> The USB Gecko is a 3rd party memory card interface adapter that provides
> a EXI (External Interface) to USB serial converter.
>
> Signed-off-by: Albert Herranz <albert_herranz@yahoo.es>
> ---
> arch/powerpc/Kconfig.debug | 8 +++
> arch/powerpc/include/asm/udbg.h | 1 +
> arch/powerpc/kernel/head_32.S | 21 +++++++
> arch/powerpc/kernel/udbg.c | 2 +
> arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c | 59 ++++++++++++++++++++
> arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h | 2 +
> 6 files changed, 93 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
> index 3b10051..11e385b 100644
> --- a/arch/powerpc/Kconfig.debug
> +++ b/arch/powerpc/Kconfig.debug
> @@ -254,6 +254,14 @@ config PPC_EARLY_DEBUG_CPM
> using a CPM-based serial port. This assumes that the bootwrapper
> has run, and set up the CPM in a particular way.
>
> +config PPC_EARLY_DEBUG_USBGECKO
> + bool "Early debugging through the USB Gecko adapter"
> + depends on GAMECUBE_COMMON
> + select USBGECKO_UDBG
> + help
> + Select this to enable early debugging for Nintendo GameCube/Wii
> + consoles via an external USB Gecko adapter.
> +
> endchoice
>
> config PPC_EARLY_DEBUG_44x_PHYSLOW
Small nit, my preference would be for this to be in the patch 1 where it
is first referenced.
> diff --git a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
> index ba4c7cc..3f125b6 100644
> --- a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
> +++ b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
> @@ -17,6 +17,7 @@
> #include <asm/io.h>
> #include <asm/prom.h>
> #include <asm/udbg.h>
> +#include <asm/fixmap.h>
>
> #include "usbgecko_udbg.h"
>
> @@ -270,3 +271,61 @@ done:
> of_node_put(np);
> return;
> }
> +
> +#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
> +
> +static void __init ug_early_remap(void)
you may want to rename the ug_ prefix, it took me a while looking back
and forth through the patch to convince myself it wasn't a typo.
-Richard Holden
^ permalink raw reply
* Re: [PATCH v2] ppc440spe-adma: adds updated ppc440spe adma driver
From: Dan Williams @ 2009-12-01 0:39 UTC (permalink / raw)
To: Anatolij Gustschin
Cc: linux-raid@vger.kernel.org, linuxppc-dev@ozlabs.org,
Yuri Tikhonov, wd@denx.de, dzu@denx.de
In-Reply-To: <1259186722-15012-1-git-send-email-agust@denx.de>
Anatolij Gustschin wrote:
> This patch adds new version of the PPC440SPe ADMA driver.
>
> Signed-off-by: Anatolij Gustschin <agust@denx.de>
> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
[minor] Sign-offs are typically in delivery path order, so yours would
appear last.
[..]
> drivers/dma/ppc440spe/ppc440spe-adma.c | 5015 ++++++++++++++++++++
> drivers/dma/ppc440spe/ppc440spe_adma.h | 195 +
> drivers/dma/ppc440spe/ppc440spe_dma.h | 223 +
> drivers/dma/ppc440spe/ppc440spe_xor.h | 110 +
I belong to the school of thought that says something along the lines of
"don't duplicate the directory path in the filename". You seem to have
copied the iop-adma driver's inconsistent use of '-' and '_' let's not
carry that forward, i.e. looking for a changelog like:
drivers/dma/ppc440spe/adma.c | 5015 ++++++++++++++++++++
drivers/dma/ppc440spe/adma.h | 195 +
drivers/dma/ppc440spe/dma.h | 223 +
drivers/dma/ppc440spe/xor.h | 110 +
> +/**
> + * ppc440spe_adma_prep_dma_pqzero_sum - prepare CDB group for
> + * a PQ_ZERO_SUM operation
> + */
> +static struct dma_async_tx_descriptor *ppc440spe_adma_prep_dma_pqzero_sum(
> + struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
> + unsigned int src_cnt, const unsigned char *scf, size_t len,
> + enum sum_check_flags *pqres, unsigned long flags)
> +{
> + struct ppc440spe_adma_chan *ppc440spe_chan;
> + struct ppc440spe_adma_desc_slot *sw_desc, *iter;
> + dma_addr_t pdest, qdest;
> + int slot_cnt, slots_per_op, idst, dst_cnt;
> +
> + if (unlikely(!len))
> + return NULL;
> + if (len > PAGE_SIZE)
> + return NULL;
This won't work, as currently we'll end up in an infinite loop in
async_syndrome_val() because all descriptor allocation failures are
assumed to be time-limited. The code just issues any pending operations
and waits for descriptor resources to become available.
What this comes down to is that ppc440spe_adma is essentially fibbing
about its support for the pq_val operation. I think a more generic
solution would be to advertise to the async_tx api that the driver has
per channel temporary buffers that can be used to store intermediate pq
results and let the async_tx api handle the emulation using its
knowledge of ->max_pq. We would also need a mechanism for the async_tx
api to lock out other requesters of the temporary buffer until a
coherent set of descriptors referencing those temporary buffers has been
submitted to the driver. This would help other drivers like mv_xor
which has no val support and ioatdma which currently can only validate
up to 8 sources asynchronously.
Can you clarify what ppc440spe-adma supports in this area? It looks
like it has some hardware support for result checking but always needs
to write p and/or q somewhere? Some devices may be able to do the final
comparison against the original parity values asynchronously while
others may need to do it synchronously in software. These details can
be handled at the async_tx api level.
Until this is resolved I would prefer that ppe440spe-adma use the
existing pq_val emulation by not setting DMA_PQ_VAL in the capability mask.
--
Dan
^ permalink raw reply
* linux-next: powerpc tree build failure
From: Stephen Rothwell @ 2009-11-30 23:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, linuxppc-dev
Cc: linux-next, linux-kernel, David Gibson
[-- Attachment #1: Type: text/plain, Size: 672 bytes --]
Hi Ben,
Today's linux-next build (powerpc ppc64_defconfig) failed like this:
arch/powerpc/mm/mmu_context_hash64.c: In function 'destroy_context':
arch/powerpc/mm/mmu_context_hash64.c:96: error: passing argument 1 of 'subpage_prot_free' from incompatible pointer type
arch/powerpc/include/asm/mmu-hash64.h:404: note: expected 'pgd_t *' but argument is of type 'struct mm_struct *'
Casued by commit c045256d146800ea1d741a8e9e377dada6b7e195 ("powerpc/mm:
Fix bug in pagetable cache cleanup with CONFIG_PPC_SUBPAGE_PROT") which I
have reverted for today.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply
* [RFC PATCH v3 3/3] powerpc: gamecube/wii: early debugging using usbgecko
From: Albert Herranz @ 2009-11-30 23:09 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Albert Herranz
In-Reply-To: <cover.1259609263.git.albert_herranz@yahoo.es>
Add support for using the USB Gecko adapter as an early debugging
console on the Nintendo GameCube and Wii video game consoles.
The USB Gecko is a 3rd party memory card interface adapter that provides
a EXI (External Interface) to USB serial converter.
Signed-off-by: Albert Herranz <albert_herranz@yahoo.es>
---
arch/powerpc/Kconfig.debug | 8 +++
arch/powerpc/include/asm/udbg.h | 1 +
arch/powerpc/kernel/head_32.S | 21 +++++++
arch/powerpc/kernel/udbg.c | 2 +
arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c | 59 ++++++++++++++++++++
arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h | 2 +
6 files changed, 93 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 3b10051..11e385b 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -254,6 +254,14 @@ config PPC_EARLY_DEBUG_CPM
using a CPM-based serial port. This assumes that the bootwrapper
has run, and set up the CPM in a particular way.
+config PPC_EARLY_DEBUG_USBGECKO
+ bool "Early debugging through the USB Gecko adapter"
+ depends on GAMECUBE_COMMON
+ select USBGECKO_UDBG
+ help
+ Select this to enable early debugging for Nintendo GameCube/Wii
+ consoles via an external USB Gecko adapter.
+
endchoice
config PPC_EARLY_DEBUG_44x_PHYSLOW
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index 9dfedec..5abfd0f 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -54,6 +54,7 @@ extern void __init udbg_init_btext(void);
extern void __init udbg_init_44x_as1(void);
extern void __init udbg_init_40x_realmode(void);
extern void __init udbg_init_cpm(void);
+extern void __init udbg_init_usbgecko(void);
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_UDBG_H */
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 829c3fe..c3f3737 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -164,6 +164,9 @@ __after_mmu_off:
#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
bl setup_cpm_bat
#endif
+#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
+ bl setup_usbgecko_bat
+#endif
/*
* Call setup_cpu for CPU 0 and initialize 6xx Idle
@@ -1203,6 +1206,24 @@ setup_cpm_bat:
blr
#endif
+#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
+setup_usbgecko_bat:
+ /* prepare a BAT for early io */
+#if defined(CONFIG_GAMECUBE)
+ lis r8, 0x0c00
+#elif defined(CONFIG_WII)
+ lis r8, 0x0d00
+#else
+#error Invalid platform for USB Gecko based early debugging.
+#endif
+ mr r11, r8
+ ori r8, r8, 0x002a /* uncached, guarded ,rw */
+ ori r11, r11, 0x3 /* 128K */
+ mtspr SPRN_DBAT1L, r8
+ mtspr SPRN_DBAT1U, r11
+ blr
+#endif
+
#ifdef CONFIG_8260
/* Jump into the system reset for the rom.
* We first disable the MMU, and then jump to the ROM reset address.
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index 2711050..65a7926 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -63,6 +63,8 @@ void __init udbg_early_init(void)
udbg_init_40x_realmode();
#elif defined(CONFIG_PPC_EARLY_DEBUG_CPM)
udbg_init_cpm();
+#elif defined(CONFIG_PPC_EARLY_DEBUG_USBGECKO)
+ udbg_init_usbgecko();
#endif
#ifdef CONFIG_PPC_EARLY_DEBUG
diff --git a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
index ba4c7cc..3f125b6 100644
--- a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
+++ b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
@@ -17,6 +17,7 @@
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/udbg.h>
+#include <asm/fixmap.h>
#include "usbgecko_udbg.h"
@@ -270,3 +271,61 @@ done:
of_node_put(np);
return;
}
+
+#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
+
+static void __init ug_early_remap(void)
+{
+ unsigned long addr;
+ void __iomem *io;
+
+ if (ug_io_base) {
+ addr = (unsigned long)ug_io_base;
+ set_fixmap_nocache(FIX_EARLY_DEBUG_BASE, addr & PAGE_MASK);
+ io = (void __iomem *)__fix_to_virt(FIX_EARLY_DEBUG_BASE);
+ io += addr & ~PAGE_MASK;
+ udbg_printf("%s: %p -> %p\n", __func__, ug_io_base, io);
+ ug_io_base = io;
+ }
+}
+
+static void __iomem * __init ug_early_grab_exi_io_base(void)
+{
+#if defined(CONFIG_GAMECUBE)
+ return (void __iomem *)0x0c006800;
+#elif defined(CONFIG_WII)
+ return (void __iomem *)0x0d006800;
+#else
+#error Invalid platform for USB Gecko based early debugging.
+#endif
+}
+
+/*
+ * USB Gecko early debug support initialization for udbg.
+ */
+void __init udbg_init_usbgecko(void)
+{
+ void __iomem *exi_io_base;
+
+ /*
+ * At this point we have a BAT already setup that enables I/O
+ * to the EXI hardware.
+ */
+
+ exi_io_base = ug_early_grab_exi_io_base();
+ if (!exi_io_base)
+ return;
+
+ /* try to detect a USB Gecko */
+ if (!ug_udbg_probe(exi_io_base))
+ return;
+
+ /* we found a USB Gecko, load udbg hooks */
+ udbg_putc = ug_udbg_putc;
+ udbg_getc = ug_udbg_getc;
+ udbg_getc_poll = ug_udbg_getc_poll;
+ udbg_early_remap = ug_early_remap;
+}
+
+#endif /* CONFIG_PPC_EARLY_DEBUG_USBGECKO */
+
diff --git a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h
index 3929de3..bb6cde4 100644
--- a/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h
+++ b/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h
@@ -27,4 +27,6 @@ static inline void __init ug_udbg_init(void)
#endif /* CONFIG_USBGECKO_UDBG */
+void __init udbg_init_usbgecko(void);
+
#endif /* __USBGECKO_UDBG_H */
--
1.6.3.3
^ permalink raw reply related
* [RFC PATCH v3 2/3] powerpc: udbg: add fixmap entry for early debug
From: Albert Herranz @ 2009-11-30 23:09 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Albert Herranz
In-Reply-To: <cover.1259609263.git.albert_herranz@yahoo.es>
Add a new entry to the fixmap table to allow low level early udbg drivers
to safely reserve virtual address space and create their I/O mappings.
Signed-off-by: Albert Herranz <albert_herranz@yahoo.es>
---
arch/powerpc/include/asm/fixmap.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h
index f1f4e23..424e5a6 100644
--- a/arch/powerpc/include/asm/fixmap.h
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -48,6 +48,9 @@ enum fixed_addresses {
FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
#endif
+#ifdef CONFIG_PPC_EARLY_DEBUG
+ FIX_EARLY_DEBUG_BASE,
+#endif
/* FIX_PCIE_MCFG, */
__end_of_fixed_addresses
};
--
1.6.3.3
^ permalink raw reply related
* [RFC PATCH v3 1/3] powerpc: udbg: add early remap hook
From: Albert Herranz @ 2009-11-30 23:09 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Albert Herranz
In-Reply-To: <cover.1259609263.git.albert_herranz@yahoo.es>
The udbg facility provides an early debug extension that can be enabled
using CONFIG_PPC_EARLY_DEBUG.
In some cases, this early debugging facility cannot be used after
MMU_init runs (and the MMU is loaded and enabled with the definitive
mappings) because the early mappings are not valid anymore.
This patch provides a udbg hook called udbg_early_remap that gets called
at the end of MMU_init and can be used by a low level udbg driver
to accomplish several goals, like:
- extending the early debugging life by configuring and using a new
valid I/O mapping
- safely disabling the early debugging
Signed-off-by: Albert Herranz <albert_herranz@yahoo.es>
---
arch/powerpc/include/asm/udbg.h | 3 +++
arch/powerpc/kernel/udbg.c | 3 +++
arch/powerpc/mm/init_32.c | 10 ++++++++++
3 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index cd21e5e..9dfedec 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -18,6 +18,9 @@ extern void (*udbg_putc)(char c);
extern void (*udbg_flush)(void);
extern int (*udbg_getc)(void);
extern int (*udbg_getc_poll)(void);
+#ifdef CONFIG_PPC_EARLY_DEBUG
+extern void (*udbg_early_remap)(void);
+#endif
extern void udbg_puts(const char *s);
extern int udbg_write(const char *s, int n);
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index fc9af47..2711050 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -21,6 +21,9 @@ void (*udbg_putc)(char c);
void (*udbg_flush)(void);
int (*udbg_getc)(void);
int (*udbg_getc_poll)(void);
+#ifdef CONFIG_PPC_EARLY_DEBUG
+void (*udbg_early_remap)(void);
+#endif
/*
* Early debugging facilities. You can enable _one_ of these via .config,
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 9ddcfb4..066e4ff 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -43,6 +43,7 @@
#include <asm/tlb.h>
#include <asm/sections.h>
#include <asm/system.h>
+#include <asm/udbg.h>
#include "mmu_decl.h"
@@ -180,6 +181,15 @@ void __init MMU_init(void)
#ifdef CONFIG_BOOTX_TEXT
btext_unmap();
#endif
+#ifdef CONFIG_PPC_EARLY_DEBUG
+ /*
+ * This hook can be used by a low level early udbg driver to either
+ * provide a new valid I/O mapping to be used after MMU_init
+ * or just to safely disable actual udbg I/O from now on.
+ */
+ if (udbg_early_remap)
+ udbg_early_remap();
+#endif
}
/* This is only called until mem_init is done. */
--
1.6.3.3
^ permalink raw reply related
* [RFC PATCH v3 0/3] rework of usbgecko-based early debug
From: Albert Herranz @ 2009-11-30 23:09 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Albert Herranz
This series is a rework of the previously posted patch:
- [RFC PATCH v2 08/11] powerpc: gamecube/wii: early debugging using usbgecko
It tries to implement the ideas suggested by Benjamin Herrenschmidt
regarding the use of a fixmap entry to provide a valid I/O mapping
immediately after MMU_init runs and MMU is definitively enabled.
Albert Herranz (3):
powerpc: udbg: add early remap hook
powerpc: udbg: add fixmap entry for early debug
powerpc: gamecube/wii: early debugging using usbgecko
arch/powerpc/Kconfig.debug | 8 +++
arch/powerpc/include/asm/fixmap.h | 3 +
arch/powerpc/include/asm/udbg.h | 4 +
arch/powerpc/kernel/head_32.S | 21 +++++++
arch/powerpc/kernel/udbg.c | 5 ++
arch/powerpc/mm/init_32.c | 10 +++
arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c | 59 ++++++++++++++++++++
arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h | 2 +
8 files changed, 112 insertions(+), 0 deletions(-)
^ permalink raw reply
* [PATCH] Adding PCI-E support for 460SX based redwood board.
From: tmarri @ 2009-11-30 22:58 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev, writetomarri, Tirumala Marri
From: Tirumala Marri <tmarri@amcc.com>
This patch would add PCI-E support for AMCC 460SX processor based
redwood board.
Signed-off-by: Tirumala Marri <tmarri@amcc.com>
---
arch/powerpc/boot/dts/redwood.dts | 122 +++++++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/ppc4xx_pci.c | 119 ++++++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/ppc4xx_pci.h | 58 +++++++++++++++++
3 files changed, 299 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
index ad402c4..9eeec28 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -233,6 +233,128 @@
has-inverted-stacr-oc;
has-new-stacr-staopc;
};
+ PCIE0: pciex@d00000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
+ primary;
+ port = <0x0>; /* port number */
+ reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
+ 0x0000000c 0x10000000 0x00001000>; /* Registers */
+ dcr-reg = <0x100 0x020>;
+ sdr-base = <0x300>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 10 to 0x1f */
+ bus-range = <0x10 0x1f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0 0x0 0x0 0x1 &UIC3 0x0 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0x1 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0x2 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0x3 0x4 /* swizzled int D */>;
+ };
+
+ PCIE1: pciex@d20000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
+ primary;
+ port = <0x1>; /* port number */
+ reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
+ 0x0000000c 0x10001000 0x00001000>; /* Registers */
+ dcr-reg = <0x120 0x020>;
+ sdr-base = <0x340>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 10 to 0x1f */
+ bus-range = <0x20 0x2f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0 0x0 0x0 0x1 &UIC3 0x4 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0x5 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0x6 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0x7 0x4 /* swizzled int D */>;
+ };
+
+ PCIE2: pciex@d40000000 {
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-460sx", "ibm,plb-pciex";
+ primary;
+ port = <0x2>; /* port number */
+ reg = <0x0000000d 0x40000000 0x20000000 /* Config space access */
+ 0x0000000c 0x10002000 0x00001000>; /* Registers */
+ dcr-reg = <0x140 0x020>;
+ sdr-base = <0x370>;
+
+ /* Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000f 0x00000000 0x00000000 0x80000000
+ 0x01000000 0x00000000 0x00000000 0x0000000f 0x80020000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 10 to 0x1f */
+ bus-range = <0x30 0x3f>;
+
+ /* Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <
+ 0x0 0x0 0x0 0x1 &UIC3 0x8 0x4 /* swizzled int A */
+ 0x0 0x0 0x0 0x2 &UIC3 0x9 0x4 /* swizzled int B */
+ 0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
+ 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
+ };
};
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 6ff9d71..64cd020 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -972,6 +972,123 @@ static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
.setup_utl = ppc460ex_pciex_init_utl,
};
+static int __init ppc460sx_pciex_core_init(struct device_node *np)
+{
+ /* HSS drive amplitude */
+ mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
+
+ mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
+
+ mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
+ mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
+
+ /* HSS TX pre-emphasis */
+ mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
+
+ mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
+
+ mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
+ mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
+
+ /* HSS TX calibration control */
+ mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
+ mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
+ mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
+
+ /* HSS TX slew control */
+ mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
+ mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
+ mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
+
+ udelay(100);
+
+ /* De-assert PLLRESET */
+ dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
+
+ /* Reset DL, UTL, GPL before configuration */
+ mtdcri(SDR0, PESDR0_460SX_RCSSET,
+ PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
+ mtdcri(SDR0, PESDR1_460SX_RCSSET,
+ PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
+ mtdcri(SDR0, PESDR2_460SX_RCSSET,
+ PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
+
+ udelay(100);
+
+ /*
+ * If bifurcation is not enabled, u-boot would have disabled the
+ * third PCIe port
+ */
+ if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
+ 0x00000001)) {
+ printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
+ printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
+ return 3;
+ }
+
+ printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
+ return 2;
+}
+
+static int ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
+{
+
+ if (port->endpoint)
+ dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
+ 0x01000000, 0);
+ else
+ dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
+ 0, 0x01000000);
+
+ /*Gen-1*/
+ mtdcri(SDR0, port->sdr_base + PESDRn_460SX_RCEI, 0x08000000);
+
+ dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
+ (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
+ PESDRx_RCSSET_RSTPYN);
+
+ port->has_ibpre = 1;
+
+ return 0;
+}
+
+static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
+{
+ /* Max 128 Bytes */
+ out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
+ return 0;
+}
+
+static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
+ .core_init = ppc460sx_pciex_core_init,
+ .port_init_hw = ppc460sx_pciex_init_port_hw,
+ .setup_utl = ppc460sx_pciex_init_utl,
+};
+
#endif /* CONFIG_44x */
#ifdef CONFIG_40x
@@ -1087,6 +1204,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
}
if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
+ if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
+ ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
#endif /* CONFIG_44x */
#ifdef CONFIG_40x
if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index d04e40b..56d9e5d 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -324,6 +324,64 @@
#define PESDR0_460EX_IHS2 0x036D
/*
+ * 460SX addtional DCRs
+ */
+#define PESDRn_460SX_RCEI 0x02
+
+#define PESDR0_460SX_HSSL0DAMP 0x320
+#define PESDR0_460SX_HSSL1DAMP 0x321
+#define PESDR0_460SX_HSSL2DAMP 0x322
+#define PESDR0_460SX_HSSL3DAMP 0x323
+#define PESDR0_460SX_HSSL4DAMP 0x324
+#define PESDR0_460SX_HSSL5DAMP 0x325
+#define PESDR0_460SX_HSSL6DAMP 0x326
+#define PESDR0_460SX_HSSL7DAMP 0x327
+
+#define PESDR1_460SX_HSSL0DAMP 0x354
+#define PESDR1_460SX_HSSL1DAMP 0x355
+#define PESDR1_460SX_HSSL2DAMP 0x356
+#define PESDR1_460SX_HSSL3DAMP 0x357
+
+#define PESDR2_460SX_HSSL0DAMP 0x384
+#define PESDR2_460SX_HSSL1DAMP 0x385
+#define PESDR2_460SX_HSSL2DAMP 0x386
+#define PESDR2_460SX_HSSL3DAMP 0x387
+
+#define PESDR0_460SX_HSSL0COEFA 0x328
+#define PESDR0_460SX_HSSL1COEFA 0x329
+#define PESDR0_460SX_HSSL2COEFA 0x32A
+#define PESDR0_460SX_HSSL3COEFA 0x32B
+#define PESDR0_460SX_HSSL4COEFA 0x32C
+#define PESDR0_460SX_HSSL5COEFA 0x32D
+#define PESDR0_460SX_HSSL6COEFA 0x32E
+#define PESDR0_460SX_HSSL7COEFA 0x32F
+
+#define PESDR1_460SX_HSSL0COEFA 0x358
+#define PESDR1_460SX_HSSL1COEFA 0x359
+#define PESDR1_460SX_HSSL2COEFA 0x35A
+#define PESDR1_460SX_HSSL3COEFA 0x35B
+
+#define PESDR2_460SX_HSSL0COEFA 0x388
+#define PESDR2_460SX_HSSL1COEFA 0x389
+#define PESDR2_460SX_HSSL2COEFA 0x38A
+#define PESDR2_460SX_HSSL3COEFA 0x38B
+
+#define PESDR0_460SX_HSSL1CALDRV 0x339
+#define PESDR1_460SX_HSSL1CALDRV 0x361
+#define PESDR2_460SX_HSSL1CALDRV 0x391
+
+#define PESDR0_460SX_HSSSLEW 0x338
+#define PESDR1_460SX_HSSSLEW 0x360
+#define PESDR2_460SX_HSSSLEW 0x390
+
+#define PESDR0_460SX_HSSCTLSET 0x31E
+#define PESDR1_460SX_HSSCTLSET 0x352
+#define PESDR2_460SX_HSSCTLSET 0x382
+
+#define PESDR0_460SX_RCSSET 0x304
+#define PESDR1_460SX_RCSSET 0x344
+#define PESDR2_460SX_RCSSET 0x374
+/*
* Of the above, some are common offsets from the base
*/
#define PESDRn_UTLSET1 0x00
--
1.6.3.3
^ permalink raw reply related
* [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2009-11-30 22:46 UTC (permalink / raw)
To: Linus Torvalds; +Cc: Andrew Morton, linuxppc-dev list, Linux Kernel list
Hi Linus
Please pull one patch from Becky to fix a build breakage in 2.6.32 with
CONFIG_DEBUG_HIGHMEM. This is, I believe, the same patch that went
into ARM to fix the same issue.
Cheers,
Ben.
The following changes since commit a8a8a669ea13d792296737505adc43ccacf3a648:
Linus Torvalds (1):
Merge branch 'i2c-pnx-fixes' of git://git.fluff.org/bjdooks/linux
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
Becky Bruce (1):
powerpc: Fix DEBUG_HIGHMEM build break from d4515646699
arch/powerpc/include/asm/kmap_types.h | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
^ permalink raw reply
* Re: [PATCH 00/10 v6] Fix 8xx MMU/TLB
From: Joakim Tjernlund @ 2009-11-30 22:30 UTC (permalink / raw)
To: Scott Wood; +Cc: Rex Feany, linuxppc-dev@ozlabs.org
In-Reply-To: <4B14465A.3080804@freescale.com>
Scott Wood <scottwood@freescale.com> wrote on 30/11/2009 23:25:30:
>
> Benjamin Herrenschmidt wrote:
> > On Fri, 2009-11-27 at 11:57 +0100, Joakim Tjernlund wrote:
> >> Scott and Rex, I think we need you s-o-b to make it into the kernel proper.
> >>
> >> Marcelo and Vitaly, I noticed you guys are listed as 8xx maintainers.
> >> Have you seen this? What do you think?
> >
> > I think Marcelo isn't much involved with 8xx anymore. I'd say if Scott
> > and Vitaly are ok, then the patches are good. But I'll wait for at least
> > Scott to give an Ack as he can at least test which I can't :-)
>
> ACK
Yippie, lets see if I can work up the energy to do the
same for 2.4 once this is in 2.6 :)
^ permalink raw reply
* Re: [PATCH 00/10 v6] Fix 8xx MMU/TLB
From: Scott Wood @ 2009-11-30 22:25 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev@ozlabs.org, Rex Feany
In-Reply-To: <1259357845.2076.9.camel@pasglop>
Benjamin Herrenschmidt wrote:
> On Fri, 2009-11-27 at 11:57 +0100, Joakim Tjernlund wrote:
>> Scott and Rex, I think we need you s-o-b to make it into the kernel proper.
>>
>> Marcelo and Vitaly, I noticed you guys are listed as 8xx maintainers.
>> Have you seen this? What do you think?
>
> I think Marcelo isn't much involved with 8xx anymore. I'd say if Scott
> and Vitaly are ok, then the patches are good. But I'll wait for at least
> Scott to give an Ack as he can at least test which I can't :-)
ACK
-Scott
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox