* Re: [PATCHv2] [RFC] Xilinx Virtex 4 FX Soft FPU support
From: Josh Boyer @ 2010-05-26 11:50 UTC (permalink / raw)
To: Grant Likely; +Cc: Sergey Temerkhanov, linuxppc-dev, John Linn
In-Reply-To: <AANLkTimJUqD6n9LHGZcWEkHFKvSRJsHJ9gQYMNBsIBu1@mail.gmail.com>
On Tue, May 25, 2010 at 03:38:47PM -0600, Grant Likely wrote:
>Hmmm. There should be a nicer way of doing this, but this will do for now.
>
>Otherwise, this patch looks good to me. Josh, what do you think?
I don't have any additional comments. I agree with Grant on the points he
raised, and otherwise it also looks good to me.
josh
^ permalink raw reply
* [PATCH] powerpc/44x: icon: select SM502 and frame buffer console support
From: Anatolij Gustschin @ 2010-05-26 10:36 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Anatolij Gustschin, Wolfgang Denk
Enables SM502 frame buffer and framebuffer console
in the default config file
Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
arch/powerpc/configs/44x/icon_defconfig | 149 +++++++++++++++++++++++++++++--
1 files changed, 142 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/configs/44x/icon_defconfig b/arch/powerpc/configs/44x/icon_defconfig
index 40a755b..277f88c 100644
--- a/arch/powerpc/configs/44x/icon_defconfig
+++ b/arch/powerpc/configs/44x/icon_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.34-rc5
-# Mon Apr 26 16:44:40 2010
+# Linux kernel version: 2.6.34-rc7
+# Fri May 21 17:40:22 2010
#
# CONFIG_PPC64 is not set
@@ -691,18 +691,74 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
#
# Input device support
#
-# CONFIG_INPUT is not set
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
-# CONFIG_SERIO is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_XILINX_XPS_PS2 is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
-# CONFIG_VT is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
@@ -826,7 +882,7 @@ CONFIG_SSB_POSSIBLE=y
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_SM501 is not set
+CONFIG_MFD_SM501=y
# CONFIG_HTC_PASIC3 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
@@ -852,14 +908,93 @@ CONFIG_VGA_ARB_MAX_GPUS=16
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_FB is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_OF is not set
+# CONFIG_FB_CT65550 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_VIA is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_SM501=y
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+
+#
+# Special HID drivers
+#
# CONFIG_USB_SUPPORT is not set
# CONFIG_UWB is not set
# CONFIG_MMC is not set
--
1.6.2.5
^ permalink raw reply related
* Re: [Patch 1/4] Allow arch-specific cleanup before breakpoint unregistration
From: David Howells @ 2010-05-26 9:54 UTC (permalink / raw)
To: prasad
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, Linux Kernel Mailing List, Millton Miller,
David Gibson, linuxppc-dev@ozlabs.org, Alan Stern, Paul Mackerras,
Andrew Morton, Roland McGrath
In-Reply-To: <20100526065129.GA3746@in.ibm.com>
K.Prasad <prasad@linux.vnet.ibm.com> wrote:
> > My understanding is weak function definitions must appear in a different C
> > file than their call sites to work on some toolchains.
> >
>
> Atleast, there are quite a few precedents inside the Linux kernel for
> __weak functions being invoked from the file in which they are defined
> (arch_hwblk_init, arch_enable_nonboot_cpus_begin and hw_perf_disable to
> name a few).
> Moreover the online GCC docs haven't any such constraints mentioned.
I've seen problems in this area. gcc sometimes inlines a weak function that's
in the same file as the call point.
David
^ permalink raw reply
* Re: [Patch 1/4] Allow arch-specific cleanup before breakpoint unregistration
From: K.Prasad @ 2010-05-26 6:51 UTC (permalink / raw)
To: Millton Miller
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, Linux Kernel Mailing List, David Gibson,
linuxppc-dev@ozlabs.org, Alan Stern, Paul Mackerras,
Andrew Morton, Roland McGrath
In-Reply-To: <1274787559_8162@mail4.comsite.net>
On Tue, May 25, 2010 at 06:39:19AM -0500, Millton Miller wrote:
> On Tue, 25 May 2010 at 14:43:56 +0530, K.Prasad wrote:
> > Certain architectures (such as PowerPC Book III S) have a need to cleanup
> > data-structures before the breakpoint is unregistered. This patch introduces
> > an arch-specific hook in release_bp_slot() along with a weak definition in
> > the form of a stub funciton.
> >
> > Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
> > ---
> > kernel/hw_breakpoint.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
>
>
> My understanding is weak function definitions must appear in a different C
> file than their call sites to work on some toolchains.
>
Atleast, there are quite a few precedents inside the Linux kernel for
__weak functions being invoked from the file in which they are defined
(arch_hwblk_init, arch_enable_nonboot_cpus_begin and hw_perf_disable to
name a few).
Moreover the online GCC docs haven't any such constraints mentioned.
> Andrew, can you confirm the above statement?
>
> > Index: linux-2.6.ppc64_test/kernel/hw_breakpoint.c
> > ===================================================================
> > --- linux-2.6.ppc64_test.orig/kernel/hw_breakpoint.c
> > +++ linux-2.6.ppc64_test/kernel/hw_breakpoint.c
> > @@ -242,6 +242,17 @@ toggle_bp_slot(struct perf_event *bp, bo
> > }
> >
> > /*
> > + * Function to perform processor-specific cleanup during unregistration
> > + */
> > +__weak void arch_unregister_hw_breakpoint(struct perf_event *bp)
> > +{
> > + /*
> > + * A weak stub function here for those archs that don't define
> > + * it inside arch/.../kernel/hw_breakpoint.c
> > + */
> > +}
> > +
> > +/*
> > * Contraints to check before allowing this new breakpoint counter:
> > *
> > * == Non-pinned counter == (Considered as pinned for now)
> > @@ -339,6 +350,7 @@ void release_bp_slot(struct perf_event *
> > {
> > mutex_lock(&nr_bp_mutex);
> >
> > + arch_unregister_hw_breakpoint(bp);
> > __release_bp_slot(bp);
> >
> > mutex_unlock(&nr_bp_mutex);
> >
>
>
> Since the weak version is empty, should it just be delcared (in
> a header, put the comment there) and not defined?
>
The initial thinking behind defining it in the .c file was, for one,
the function need not be moved (from .h to .c) when other architectures
have a need to populate them. Secondly, given that powerpc (which has a
'strong' definition for arch_unregister_hw_breakpoint()) includes the
header file (in which this can be moved to) I wasn't sure about
possible conflicts.
> milton
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
Thanks,
K.Prasad
^ permalink raw reply
* Re: Spinlock lockup lockup in switch_mmu_context and task_rq_lock
From: Benjamin Herrenschmidt @ 2010-05-26 4:48 UTC (permalink / raw)
To: Li, Jianlin (Jianlin); +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <38A3C77CC1D12D4DB6632EFEE8128BFE1367A668FA@USNAVSXCHMBSA1.ndc.alcatel-lucent.com>
On Tue, 2010-05-25 at 09:15 -0500, Li, Jianlin (Jianlin) wrote:
> Hi,
>
> I am running 2.6.29.1 on MPC8572 dual core with SMP enabled on our customized board.
>
> I have two applications running. One is to access CPLD registers via PCI bus and then sleep in an endless loop, the other is to send (and of course receive data) via TSEC port in an endless loop.
>
> Sooner or later, I will encounter spinlock lockup in both cores.
>
> I examined the call traces and found out that it is always the case that one got stuck in switch_mmu_context and the other in task_rq_lock when switching from interrupt context to a waiting process.
This has been fixed since then. I suggest you look at the git changes to
mmu_context_nohash.c after 2.6.29 and you'll find the fix quickly.
Cheers,
Ben.
> BUG: spinlock lockup on CPU#0, diag/31023, c0478f64
> BUG: spinlock lockup on CPU#1, diag/31016, c18123c0
> Call Trace:
> [edb4d980] [c0007a78] show_stack+0x48/0x16c (unreliable)
> [edb4d9b0] [c01c1a48] _raw_spin_lock+0x1b0/0x1c4
> [edb4d9f0] [c0348e7c] _spin_lock+0x10/0x20
> [edb4da00] [c002f0c8] task_rq_lock+0x50/0x94
> [edb4da30] [c0035430] try_to_wake_up+0xb0/0x214
> [edb4da60] [c00b99ec] pollwake+0x64/0x74
> [edb4dab0] [c0037970] __wake_up_common+0x5c/0xa0
> [edb4dae0] [c0037a6c] __wake_up_sync+0x48/0x68
> [edb4db10] [c0272aa8] sock_def_write_space+0xac/0xbc
> [edb4db30] [c0271e48] sock_wfree+0x98/0x9c
> [edb4db50] [c0274bd0] skb_release_head_state+0x8c/0xa8
> [edb4db70] [c0274c04] skb_release_all+0x18/0x30
> [edb4db90] [c0274c34] __kfree_skb+0x18/0xec
> [edb4dbb0] [f106c6fc] csmencaps_rcv+0x474/0x57c [csmencaps]
> [edb4dbe0] [c027f2c0] netif_receive_skb+0x2ec/0x32c
> [edb4dc10] [c02167dc] gfar_clean_rx_ring+0x180/0x3dc
> [edb4dc60] [c0216aa0] gfar_poll+0x68/0x354
> [edb4dcc0] [c027fd34] net_rx_action+0x12c/0x1a8
> [edb4dcf0] [c00435b0] __do_softirq+0xa8/0x15c
> [edb4dd40] [c0004348] do_softirq+0x60/0x68
> [edb4dd60] [c0043768] irq_exit+0x8c/0x90
> [edb4dd80] [c00041e4] do_IRQ+0xd8/0x110
> [edb4ddb0] [c00102f4] ret_from_except+0x0/0x18
> [edb4de70] [c0014a84] destroy_context+0x3c/0xac
> [edb4de90] [c003b3fc] __mmdrop+0x3c/0x60
> [edb4deb0] [c0035880] finish_task_switch+0xd0/0xd4
> [edb4ded0] [c03467b0] __sched_text_start+0x200/0x6b4
> [edb4df40] [c00107a8] recheck+0x0/0x24
> Call Trace:
> [e92e9e10] [c0007a78] show_stack+0x48/0x16c (unreliable)
> [e92e9e40] [c01c1a48] _raw_spin_lock+0x1b0/0x1c4
> [e92e9e80] [c0348e7c] _spin_lock+0x10/0x20
> [e92e9e90] [c0014700] switch_mmu_context+0x2c/0x35c
> [e92e9ed0] [c0346778] __sched_text_start+0x1c8/0x6b4
> [e92e9f40] [c00107a8] recheck+0x0/0x24
>
> Does anyone have some clue on this?
>
> Thanks,
>
> Jane
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH v3] powerpc: Add i8042 keyboard and mouse irq parsing
From: Mitch Bradley @ 2010-05-25 23:19 UTC (permalink / raw)
To: Grant Likely
Cc: Martyn Welch, linuxppc-dev, devicetree-discuss, Dmitry Torokhov,
linux-input
In-Reply-To: <AANLkTikve-ZghgpVl3cyjjgWAch-oCJ0EiYK2127f5gS@mail.gmail.com>
Grant Likely wrote:
> On Tue, May 25, 2010 at 2:09 AM, Martyn Welch <martyn.welch@ge.com> wrote:
>
>> Currently the irqs for the i8042, which historically provides keyboard and
>> mouse (aux) support, is hardwired in the driver rather than parsing the
>> dts. This patch modifies the powerpc legacy IO code to attempt to parse
>> the device tree for this information, failing back to the hardcoded values
>> if it fails.
>>
>> Signed-off-by: Martyn Welch <martyn.welch@ge.com>
>> ---
>>
>> v2: This patch no longer requires the DTS files to be modified, reading the
>> interrupts from the current location as suggested by Grant.
>>
>> v3: Code compacted as suggested by Grant.
>>
>> arch/powerpc/kernel/setup-common.c | 13 +++++++++++++
>> drivers/input/serio/i8042-io.h | 5 +++++
>> 2 files changed, 18 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
>> index 48f0a00..3d169bb 100644
>> --- a/arch/powerpc/kernel/setup-common.c
>> +++ b/arch/powerpc/kernel/setup-common.c
>> @@ -94,6 +94,10 @@ struct screen_info screen_info = {
>> .orig_video_points = 16
>> };
>>
>> +/* Variables required to store legacy IO irq routing */
>> +int of_i8042_kbd_irq;
>> +int of_i8042_aux_irq;
>> +
>> #ifdef __DO_IRQ_CANON
>> /* XXX should go elsewhere eventually */
>> int ppc_do_canonicalize_irqs;
>> @@ -567,6 +571,15 @@ int check_legacy_ioport(unsigned long base_port)
>> np = of_find_compatible_node(NULL, NULL, "pnpPNP,f03");
>> if (np) {
>> parent = of_get_parent(np);
>> +
>> + of_i8042_kbd_irq = irq_of_parse_and_map(parent, 0);
>> + if (!of_i8042_kbd_irq)
>> + of_i8042_kbd_irq = 1;
>> +
>> + of_i8042_aux_irq = irq_of_parse_and_map(parent, 1);
>> + if (!of_i8042_aux_irq)
>> + of_i8042_aux_irq = 12;
>> +
>>
>
> The patch looks okay to me.
>
> BTW, where is the i8042 binding documented? Ben, is this location of
> the kbd/mouse irq historical,
i8042 is, of course, the legacy PC keyboard interrupt controller, and
the IRQs that it generates on behalf of its attached keyboard and mouse
have always been 1 and 12 on the PC platforms that drive the hardware
designs of junk I/O chips. By the time that PowerPC came on the market,
the i8042 functionality was always implemented as a subsystem within a
much larger "SuperIO" chip, which often included the (legacy PC)
interrupt controller functionality. Those SuperIO chips let you move
the IRQ numbers around for some of the included devices, but I don't
remember whether or not you could move the IRQs for the keyboard and
mouse. Even if you could, "nobody" ever did it, because people were so
accustomed to 1 and 12 being keyboard and mouse that changing them would
just cause too much confusion. There was also the issue of setting the
edge/level and polarity correctly for the various IRQs. Moving the
kbd/mouse IRQs would have a ripple effect on other old-and-dusty code
that nobody wanted to touch.
The design of PReP (PowerPC Reference Platform) was amusing to watch.
Apple was wanting to make it into a 68K Macintosh I/O system with a
PowerPC grafted in, while IBM wanted a conventional PC with a PowerPC
grafted in. IBM stacked the committee and basically got what they
wanted - a PC with a different CPU chip. At the Comdex show where they
rolled out the PReP spec, Apple had their own announcement to make -
Apple wasn't going to use PReP. So IBM's power play backfired.
The PReP committee (consisting of representatives from IBM, Apple,
Motorola, and a few other bit players like myself) then went into panic
mode, and came out with CHRP. CHRP was PReP with a legacy Macintosh I/O
system bolted onto the side. So you had the worst of both worlds. In
the PReP mode, you had PC-style I/O like IDE, i8042, 8259 interrupt
controller, etc. In the Mac mode, you had SCSI (using a horrible
ancient programming model that nobody else was using anymore), ADB, and
an OpenPIC interrupt controller. The chipsets had to support both sets.
The final shoe dropped 18 months later, when Steve Jobs re-took Apple
and announced that Apple was not in fact going to license MacOS for use
on third-party CHRP machines.
The original binding documents for the PC-style I/O system were driven
from the IBM side. I may have written some of the text (or maybe not; I
forget), but it was IBM who stipulated how it was going to work.
> or is it just something that we happened
> to get when the .dts files were first created? Having the irq
> specified directly in the kbd or aux nodes would make a lot more
> sense, and if this isn't something already nailed down, then it
> probably does make sense to move the irq specification, fall back to
> the parent node to still support older trees, and with the hard coded
> irq numbers as the last resort.
>
> Cheers,
> g.
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
>
>
^ permalink raw reply
* Re: [PATCHv2] [RFC] Xilinx Virtex 4 FX Soft FPU support
From: Grant Likely @ 2010-05-25 21:38 UTC (permalink / raw)
To: Sergey Temerkhanov; +Cc: linuxppc-dev, John Linn
In-Reply-To: <201005201401.09912.temerkhanov@cifronik.ru>
(cc'ing Josh Boyer and John Linn)
On Thu, May 20, 2010 at 4:01 AM, Sergey Temerkhanov
<temerkhanov@cifronik.ru> wrote:
> This patch enables support for Xilinx Virtex 4 FX singe-float FPU.
>
> Changelog v1->v2:
> =9A =9A =9A =9A-Added MSR_AP bit definition
> =9A =9A =9A =9A-Renamed CONFIG_XILINX_FPU to CONFIG_XILINX_SOFTFPU, moved=
it to
> =9A =9A =9A =9A'Platform support' and made it Virtex4-FX-only.
> =9A =9A =9A =9A-Changed SAVE_FPR/REST_FPR definition style.
>
> Caveats:
> =9A =9A =9A =9A- Hard-float binaries which rely on in-kernel math emulati=
on will give
> wrong results since they expect 64-bit double-precision instead of 32-bit
> single-precision numbers which Xilinx V4-FX Soft FPU produces.
>
> Regards, Sergey Temerkhanov
>
Hi Sergey. Comments below.
First off, see if you can use 'git mail' or some other way to inline
your patches. Patches as attachments are awkward to deal with and the
patch description is getting separated from the patch itself.
> Signed-off-by: Sergey Temerkhanov<temerkhanov@cifronik.ru>
>
> diff -r b59861a64e13 arch/powerpc/include/asm/ppc_asm.h
> --- a/arch/powerpc/include/asm/ppc_asm.h Thu May 20 13:24:53 2010 +0400
> +++ b/arch/powerpc/include/asm/ppc_asm.h Thu May 20 13:55:10 2010 +0400
> @@ -85,13 +85,21 @@
> #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
> #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
>
> -#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
> +
> +#ifdef CONFIG_XILINX_SOFTFPU
> +#define SAVE_FPR(n, base) stfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
> +#define REST_FPR(n, base) lfs n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
> +#else
> +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
> +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
> +#endif
> +
Hint: If you don't change the whitespace on the SAVE_FPR() line, then diff =
will
realize it is unchanged and reviewers will have more context queues as
to what you are doing.
Otherwise, this looks better.
> #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
> #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
> #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
> #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
> #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, bas=
e)
> -#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base)
> +
> #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
> #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
> #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
> diff -r b59861a64e13 arch/powerpc/include/asm/reg.h
> --- a/arch/powerpc/include/asm/reg.h Thu May 20 13:24:53 2010 +0400
> +++ b/arch/powerpc/include/asm/reg.h Thu May 20 13:55:10 2010 +0400
> @@ -30,6 +30,7 @@
> #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
> #define MSR_HV_LG 60 /* Hypervisor state */
> #define MSR_VEC_LG 25 /* Enable AltiVec */
> +#define MSR_AP_LG 25 /* Enable APU */
> #define MSR_VSX_LG 23 /* Enable VSX */
> #define MSR_POW_LG 18 /* Enable Power Management */
> #define MSR_WE_LG 18 /* Wait State Enable */
> @@ -71,6 +72,7 @@
> #define MSR_HV 0
> #endif
>
> +#define MSR_AP __MASK(MSR_AP_LG) /* Enable APU */
Need to be more specific: "Enable Xilinx Virtex 405 APU". Same goes
for MSR_AP_LG line above.
> #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
> #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
> #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
> diff -r b59861a64e13 arch/powerpc/kernel/fpu.S
> --- a/arch/powerpc/kernel/fpu.S Thu May 20 13:24:53 2010 +0400
> +++ b/arch/powerpc/kernel/fpu.S Thu May 20 13:55:10 2010 +0400
> @@ -57,6 +57,9 @@
> _GLOBAL(load_up_fpu)
> mfmsr r5
> ori r5,r5,MSR_FP
> +#ifdef CONFIG_XILINX_SOFTFPU
> + oris r5,r5,MSR_AP@h
> +#endif
> #ifdef CONFIG_VSX
> BEGIN_FTR_SECTION
> oris r5,r5,MSR_VSX@h
> @@ -85,6 +88,9 @@
> toreal(r5)
> PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
> li r10,MSR_FP|MSR_FE0|MSR_FE1
> +#ifdef CONFIG_XILINX_SOFTFPU
> + oris r10,r10,MSR_AP@h
> +#endif
> andc r4,r4,r10 /* disable FP for previous task */
> PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
> 1:
> @@ -94,6 +100,9 @@
> mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
> lwz r4,THREAD_FPEXC_MODE(r5)
> ori r9,r9,MSR_FP /* enable FP for current */
> +#ifdef CONFIG_XILINX_SOFTFPU
> + oris r9,r9,MSR_AP@h
> +#endif
> or r9,r9,r4
> #else
> ld r4,PACACURRENT(r13)
> @@ -124,6 +133,9 @@
> _GLOBAL(giveup_fpu)
> mfmsr r5
> ori r5,r5,MSR_FP
> +#ifdef CONFIG_XILINX_SOFTFPU
> + oris r5,r5,MSR_AP@h
> +#endif
> #ifdef CONFIG_VSX
> BEGIN_FTR_SECTION
> oris r5,r5,MSR_VSX@h
> @@ -145,6 +157,9 @@
> beq 1f
> PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
> li r3,MSR_FP|MSR_FE0|MSR_FE1
> +#ifdef CONFIG_XILINX_SOFTFPU
> + oris r3,r3,MSR_AP@h
> +#endif
> #ifdef CONFIG_VSX
> BEGIN_FTR_SECTION
> oris r3,r3,MSR_VSX@h
> diff -r b59861a64e13 arch/powerpc/kernel/head_40x.S
> --- a/arch/powerpc/kernel/head_40x.S Thu May 20 13:24:53 2010 +0400
> +++ b/arch/powerpc/kernel/head_40x.S Thu May 20 13:55:10 2010 +0400
> @@ -420,7 +420,19 @@
> addi r3,r1,STACK_FRAME_OVERHEAD
> EXC_XFER_STD(0x700, program_check_exception)
>
> +/* 0x0800 - FPU unavailable Exception */
> +#ifdef CONFIG_PPC_FPU
> + START_EXCEPTION(0x0800, FloatingPointUnavailable)
> + NORMAL_EXCEPTION_PROLOG
> + beq 1f; \
> + bl load_up_fpu; /* if from user, just load it up */ \
> + b fast_exception_return; \
> +1: addi r3,r1,STACK_FRAME_OVERHEAD; \
> + EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
> +#else
> EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE)
> +#endif
> +
> EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE)
> EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE)
> EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE)
> @@ -432,7 +444,7 @@
>
> EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE)
> EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE)
> - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE)
> + EXCEPTION(0x0F20, Trap_0F, unknown_exception, EXC_XFER_EE)
Is this change required to support the FPU? It looks like something
that belongs in a separate patch.
>
> /* 0x1000 - Programmable Interval Timer (PIT) Exception */
> START_EXCEPTION(0x1000, Decrementer)
> @@ -821,8 +833,10 @@
> * The PowerPC 4xx family of processors do not have an FPU, so this just
> * returns.
> */
> +#ifndef CONFIG_PPC_FPU
> _ENTRY(giveup_fpu)
> blr
> +#endif
>
> /* This is where the main kernel code starts.
> */
> diff -r b59861a64e13 arch/powerpc/platforms/Kconfig
> --- a/arch/powerpc/platforms/Kconfig Thu May 20 13:24:53 2010 +0400
> +++ b/arch/powerpc/platforms/Kconfig Thu May 20 13:55:10 2010 +0400
> @@ -333,4 +333,9 @@
> bool "Xilinx PCI host bridge support"
> depends on PCI && XILINX_VIRTEX
>
> +config XILINX_SOFTFPU
> + bool "Xilinx Soft FPU"
> + select PPC_FPU
> + depends on XILINX_VIRTEX_4_FX && !PPC40x_SIMPLE && !405GP && !405GPR
> +
Hmmm. There should be a nicer way of doing this, but this will do for now.
Otherwise, this patch looks good to me. Josh, what do you think?
Cheers,
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH v3] powerpc: Add i8042 keyboard and mouse irq parsing
From: Grant Likely @ 2010-05-25 20:21 UTC (permalink / raw)
To: Martyn Welch
Cc: devicetree-discuss, Dmitry Torokhov, linux-input, linuxppc-dev
In-Reply-To: <20100525080834.29149.70967.stgit@ES-J7S4D2J.amer.consind.ge.com>
On Tue, May 25, 2010 at 2:09 AM, Martyn Welch <martyn.welch@ge.com> wrote:
> Currently the irqs for the i8042, which historically provides keyboard an=
d
> mouse (aux) support, is hardwired in the driver rather than parsing the
> dts. =A0This patch modifies the powerpc legacy IO code to attempt to pars=
e
> the device tree for this information, failing back to the hardcoded value=
s
> if it fails.
>
> Signed-off-by: Martyn Welch <martyn.welch@ge.com>
> ---
>
> v2: This patch no longer requires the DTS files to be modified, reading t=
he
> interrupts from the current location as suggested by Grant.
>
> v3: Code compacted as suggested by Grant.
>
> =A0arch/powerpc/kernel/setup-common.c | =A0 13 +++++++++++++
> =A0drivers/input/serio/i8042-io.h =A0 =A0 | =A0 =A05 +++++
> =A02 files changed, 18 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/set=
up-common.c
> index 48f0a00..3d169bb 100644
> --- a/arch/powerpc/kernel/setup-common.c
> +++ b/arch/powerpc/kernel/setup-common.c
> @@ -94,6 +94,10 @@ struct screen_info screen_info =3D {
> =A0 =A0 =A0 =A0.orig_video_points =3D 16
> =A0};
>
> +/* Variables required to store legacy IO irq routing */
> +int of_i8042_kbd_irq;
> +int of_i8042_aux_irq;
> +
> =A0#ifdef __DO_IRQ_CANON
> =A0/* XXX should go elsewhere eventually */
> =A0int ppc_do_canonicalize_irqs;
> @@ -567,6 +571,15 @@ int check_legacy_ioport(unsigned long base_port)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0np =3D of_find_compatible_=
node(NULL, NULL, "pnpPNP,f03");
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (np) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0parent =3D of_get_parent(n=
p);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 of_i8042_kbd_irq =3D irq_of=
_parse_and_map(parent, 0);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!of_i8042_kbd_irq)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 of_i8042_kb=
d_irq =3D 1;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 of_i8042_aux_irq =3D irq_of=
_parse_and_map(parent, 1);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!of_i8042_aux_irq)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 of_i8042_au=
x_irq =3D 12;
> +
The patch looks okay to me.
BTW, where is the i8042 binding documented? Ben, is this location of
the kbd/mouse irq historical, or is it just something that we happened
to get when the .dts files were first created? Having the irq
specified directly in the kbd or aux nodes would make a lot more
sense, and if this isn't something already nailed down, then it
probably does make sense to move the irq specification, fall back to
the parent node to still support older trees, and with the hard coded
irq numbers as the last resort.
Cheers,
g.
^ permalink raw reply
* Spinlock lockup lockup in switch_mmu_context and task_rq_lock
From: Li, Jianlin (Jianlin) @ 2010-05-25 14:15 UTC (permalink / raw)
To: linuxppc-dev@lists.ozlabs.org
Hi,
I am running 2.6.29.1 on MPC8572 dual core with SMP enabled on our customiz=
ed board.
I have two applications running. One is to access CPLD registers via PCI bu=
s and then sleep in an endless loop, the other is to send (and of course re=
ceive data) via TSEC port in an endless loop.
Sooner or later, I will encounter spinlock lockup in both cores.
I examined the call traces and found out that it is always the case that on=
e got stuck in switch_mmu_context and the other in task_rq_lock when switch=
ing from interrupt context to a waiting process.
BUG: spinlock lockup on CPU#0, diag/31023, c0478f64
BUG: spinlock lockup on CPU#1, diag/31016, c18123c0
Call Trace:
[edb4d980] [c0007a78] show_stack+0x48/0x16c (unreliable)
[edb4d9b0] [c01c1a48] _raw_spin_lock+0x1b0/0x1c4
[edb4d9f0] [c0348e7c] _spin_lock+0x10/0x20
[edb4da00] [c002f0c8] task_rq_lock+0x50/0x94
[edb4da30] [c0035430] try_to_wake_up+0xb0/0x214
[edb4da60] [c00b99ec] pollwake+0x64/0x74
[edb4dab0] [c0037970] __wake_up_common+0x5c/0xa0
[edb4dae0] [c0037a6c] __wake_up_sync+0x48/0x68
[edb4db10] [c0272aa8] sock_def_write_space+0xac/0xbc
[edb4db30] [c0271e48] sock_wfree+0x98/0x9c
[edb4db50] [c0274bd0] skb_release_head_state+0x8c/0xa8
[edb4db70] [c0274c04] skb_release_all+0x18/0x30
[edb4db90] [c0274c34] __kfree_skb+0x18/0xec
[edb4dbb0] [f106c6fc] csmencaps_rcv+0x474/0x57c [csmencaps]
[edb4dbe0] [c027f2c0] netif_receive_skb+0x2ec/0x32c
[edb4dc10] [c02167dc] gfar_clean_rx_ring+0x180/0x3dc
[edb4dc60] [c0216aa0] gfar_poll+0x68/0x354
[edb4dcc0] [c027fd34] net_rx_action+0x12c/0x1a8
[edb4dcf0] [c00435b0] __do_softirq+0xa8/0x15c
[edb4dd40] [c0004348] do_softirq+0x60/0x68
[edb4dd60] [c0043768] irq_exit+0x8c/0x90
[edb4dd80] [c00041e4] do_IRQ+0xd8/0x110
[edb4ddb0] [c00102f4] ret_from_except+0x0/0x18
[edb4de70] [c0014a84] destroy_context+0x3c/0xac
[edb4de90] [c003b3fc] __mmdrop+0x3c/0x60
[edb4deb0] [c0035880] finish_task_switch+0xd0/0xd4
[edb4ded0] [c03467b0] __sched_text_start+0x200/0x6b4
[edb4df40] [c00107a8] recheck+0x0/0x24
Call Trace:
[e92e9e10] [c0007a78] show_stack+0x48/0x16c (unreliable)
[e92e9e40] [c01c1a48] _raw_spin_lock+0x1b0/0x1c4
[e92e9e80] [c0348e7c] _spin_lock+0x10/0x20
[e92e9e90] [c0014700] switch_mmu_context+0x2c/0x35c
[e92e9ed0] [c0346778] __sched_text_start+0x1c8/0x6b4
[e92e9f40] [c00107a8] recheck+0x0/0x24
Does anyone have some clue on this?
Thanks,
Jane=
^ permalink raw reply
* [Patch 1/4] Allow arch-specific cleanup before breakpoint unregistration
From: Millton Miller @ 2010-05-25 11:39 UTC (permalink / raw)
To: K.Prasad
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, Linux Kernel Mailing List, David Gibson,
linuxppc-dev@ozlabs.org, Alan Stern, Paul Mackerras,
Andrew Morton, K.Prasad, Roland McGrath
In-Reply-To: <20100525091356.GB29003@in.ibm.com>
On Tue, 25 May 2010 at 14:43:56 +0530, K.Prasad wrote:
> Certain architectures (such as PowerPC Book III S) have a need to cleanup
> data-structures before the breakpoint is unregistered. This patch introduces
> an arch-specific hook in release_bp_slot() along with a weak definition in
> the form of a stub funciton.
>
> Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
> ---
> kernel/hw_breakpoint.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
My understanding is weak function definitions must appear in a different C
file than their call sites to work on some toolchains.
Andrew, can you confirm the above statement?
> Index: linux-2.6.ppc64_test/kernel/hw_breakpoint.c
> ===================================================================
> --- linux-2.6.ppc64_test.orig/kernel/hw_breakpoint.c
> +++ linux-2.6.ppc64_test/kernel/hw_breakpoint.c
> @@ -242,6 +242,17 @@ toggle_bp_slot(struct perf_event *bp, bo
> }
>
> /*
> + * Function to perform processor-specific cleanup during unregistration
> + */
> +__weak void arch_unregister_hw_breakpoint(struct perf_event *bp)
> +{
> + /*
> + * A weak stub function here for those archs that don't define
> + * it inside arch/.../kernel/hw_breakpoint.c
> + */
> +}
> +
> +/*
> * Contraints to check before allowing this new breakpoint counter:
> *
> * == Non-pinned counter == (Considered as pinned for now)
> @@ -339,6 +350,7 @@ void release_bp_slot(struct perf_event *
> {
> mutex_lock(&nr_bp_mutex);
>
> + arch_unregister_hw_breakpoint(bp);
> __release_bp_slot(bp);
>
> mutex_unlock(&nr_bp_mutex);
>
Since the weak version is empty, should it just be delcared (in
a header, put the comment there) and not defined?
milton
^ permalink raw reply
* Re: mmio_nvram.c users ?
From: Josh Boyer @ 2010-05-25 11:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <1274773439.1931.238.camel@pasglop>
On Tue, May 25, 2010 at 05:43:59PM +1000, Benjamin Herrenschmidt wrote:
>Hi folks !
>
>Anybody aware of anything other than Cell using that driver ?
>
>I'd like to make it a platform driver instead of having something that
>pokes at anything that has a "device_type" set to "nvram" (which is
>gross and bogus). But I need to know what platforms to fixup...
Why bother? You could just use either drivers/mtd/devices/{phram.c or slram.c}
and get the same functionality at that point, couldn't you?
josh
^ permalink raw reply
* Re: [git pull] Please pull powerpc.git next branch
From: Josh Boyer @ 2010-05-25 10:58 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.1005242136240.18901@localhost.localdomain>
On Mon, May 24, 2010 at 09:38:14PM -0500, Kumar Gala wrote:
>The following changes since commit 99ec28f183daa450faa7bdad6f932364ae325648:
> FUJITA Tomonori (1):
> powerpc: Remove unused 'protect4gb' boot parameter
>
>are available in the git repository at:
Ben, don't forget I still have some stuff pending that you haven't picked up.
josh
^ permalink raw reply
* [Patch 4/4] PPC64-HWBKPT: Enable hw-breakpoints while handling intervening signals
From: K.Prasad @ 2010-05-25 9:15 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100525083055.342788418@linux.vnet.ibm.com>
A signal delivered between a hw_breakpoint_handler() and the
single_step_dabr_instruction() will not have the breakpoint active during
signal handling (since breakpoint will not be restored through single-stepping
due to absence of MSR_SE bit on the signal frame). Enable breakpoints before
signal delivery.
Restore hw-breakpoints if the user-context is altered in the signal handler.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/hw_breakpoint.h | 2 ++
arch/powerpc/kernel/hw_breakpoint.c | 16 ++++++++++++++++
arch/powerpc/kernel/signal.c | 3 +++
arch/powerpc/kernel/signal_32.c | 2 ++
arch/powerpc/kernel/signal_64.c | 2 ++
5 files changed, 25 insertions(+)
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/hw_breakpoint.h
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
@@ -65,9 +65,11 @@ static inline void hw_breakpoint_disable
{
set_dabr(0);
}
+extern void thread_change_pc(struct task_struct *tsk);
#else /* CONFIG_HAVE_HW_BREAKPOINT */
static inline void hw_breakpoint_disable(void) { }
+static inline void thread_change_pc(struct task_struct *tsk) { }
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif /* __KERNEL__ */
#endif /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/hw_breakpoint.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
@@ -176,6 +176,22 @@ int arch_validate_hwbkpt_settings(struct
}
/*
+ * Restores the breakpoint on the debug registers.
+ * Invoke this function if it is known that the execution context is about to
+ * change to cause loss of MSR_SE settings.
+ */
+void thread_change_pc(struct task_struct *tsk)
+{
+ struct arch_hw_breakpoint *info;
+
+ if (likely(!tsk->thread.last_hit_ubp))
+ return;
+
+ info = counter_arch_bp(tsk->thread.last_hit_ubp);
+ set_dabr(info->address | info->type | DABR_TRANSLATION);
+}
+
+/*
* Handle debug exception notifications.
*/
int __kprobes hw_breakpoint_handler(struct die_args *args)
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/signal.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/signal.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/signal.c
@@ -11,6 +11,7 @@
#include <linux/tracehook.h>
#include <linux/signal.h>
+#include <asm/hw_breakpoint.h>
#include <asm/uaccess.h>
#include <asm/unistd.h>
@@ -149,6 +150,8 @@ static int do_signal_pending(sigset_t *o
if (current->thread.dabr)
set_dabr(current->thread.dabr);
#endif
+ /* Re-enable the breakpoints for the signal stack */
+ thread_change_pc(current);
if (is32) {
if (ka.sa.sa_flags & SA_SIGINFO)
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/signal_64.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/signal_64.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/signal_64.c
@@ -33,6 +33,7 @@
#include <asm/cacheflush.h>
#include <asm/syscalls.h>
#include <asm/vdso.h>
+#include <asm/hw_breakpoint.h>
#include "signal.h"
@@ -312,6 +313,7 @@ int sys_swapcontext(struct ucontext __us
|| __copy_to_user(&old_ctx->uc_sigmask,
¤t->blocked, sizeof(sigset_t)))
return -EFAULT;
+ thread_change_pc(current);
}
if (new_ctx == NULL)
return 0;
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/signal_32.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/signal_32.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/signal_32.c
@@ -42,6 +42,7 @@
#include <asm/syscalls.h>
#include <asm/sigcontext.h>
#include <asm/vdso.h>
+#include <asm/hw_breakpoint.h>
#ifdef CONFIG_PPC64
#include "ppc32.h"
#include <asm/unistd.h>
@@ -996,6 +997,7 @@ long sys_swapcontext(struct ucontext __u
|| put_sigset_t(&old_ctx->uc_sigmask, ¤t->blocked)
|| __put_user(to_user_ptr(mctx), &old_ctx->uc_regs))
return -EFAULT;
+ thread_change_pc(current);
}
if (new_ctx == NULL)
return 0;
^ permalink raw reply
* [Patch 3/4] PPC64-HWBKPT: Handle concurrent alignment interrupts
From: K.Prasad @ 2010-05-25 9:14 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100525083055.342788418@linux.vnet.ibm.com>
An alignment interrupt may intervene between a DSI/hw-breakpoint exception
and the single-step exception. Enable the alignment interrupt (through
modifications to emulate_single_step()) to notify the single-step exception
handler for proper restoration of hw-breakpoints.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/kernel/traps.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/traps.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/traps.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/traps.c
@@ -602,7 +602,7 @@ void RunModeException(struct pt_regs *re
void __kprobes single_step_exception(struct pt_regs *regs)
{
- regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
+ clear_single_step(regs);
if (notify_die(DIE_SSTEP, "single_step", regs, 5,
5, SIGTRAP) == NOTIFY_STOP)
@@ -621,10 +621,7 @@ void __kprobes single_step_exception(str
*/
static void emulate_single_step(struct pt_regs *regs)
{
- if (single_stepping(regs)) {
- clear_single_step(regs);
- _exception(SIGTRAP, regs, TRAP_TRACE, 0);
- }
+ single_step_exception(regs);
}
static inline int __parse_fpscr(unsigned long fpscr)
^ permalink raw reply
* [Patch 2/4] PPC64-HWBKPT: Implement hw-breakpoints for PowerPC BookIII S
From: K.Prasad @ 2010-05-25 9:14 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100525083055.342788418@linux.vnet.ibm.com>
Implement perf-events based hw-breakpoint interfaces for PowerPC Book III S
processors. These interfaces help arbitrate requests from various users and
schedules them as appropriate.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/Kconfig | 1
arch/powerpc/include/asm/cputable.h | 4
arch/powerpc/include/asm/hw_breakpoint.h | 73 ++++++
arch/powerpc/include/asm/processor.h | 8
arch/powerpc/kernel/Makefile | 1
arch/powerpc/kernel/hw_breakpoint.c | 338 +++++++++++++++++++++++++++++++
arch/powerpc/kernel/machine_kexec_64.c | 3
arch/powerpc/kernel/process.c | 6
arch/powerpc/kernel/ptrace.c | 64 +++++
arch/powerpc/lib/Makefile | 1
10 files changed, 499 insertions(+)
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
===================================================================
--- /dev/null
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
@@ -0,0 +1,73 @@
+/*
+ * PowerPC BookIII S hardware breakpoint definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010, IBM Corporation.
+ * Author: K.Prasad <prasad@linux.vnet.ibm.com>
+ *
+ */
+
+#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
+#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
+
+#ifdef __KERNEL__
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+
+struct arch_hw_breakpoint {
+ u8 len; /* length of the target data symbol */
+ int type;
+ unsigned long address;
+};
+
+#include <linux/kdebug.h>
+#include <asm/reg.h>
+#include <asm/system.h>
+
+static inline int hw_breakpoint_slots(int type)
+{
+ return HBP_NUM;
+}
+struct perf_event;
+struct pmu;
+struct perf_sample_data;
+
+#define HW_BREAKPOINT_ALIGN 0x7
+/* Maximum permissible length of any HW Breakpoint */
+#define HW_BREAKPOINT_LEN 0x8
+
+extern int arch_bp_generic_fields(int type, int *gen_bp_type);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+ unsigned long val, void *data);
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
+
+extern struct pmu perf_ops_bp;
+extern void ptrace_triggered(struct perf_event *bp, int nmi,
+ struct perf_sample_data *data, struct pt_regs *regs);
+static inline void hw_breakpoint_disable(void)
+{
+ set_dabr(0);
+}
+
+#else /* CONFIG_HAVE_HW_BREAKPOINT */
+static inline void hw_breakpoint_disable(void) { }
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+#endif /* __KERNEL__ */
+#endif /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
===================================================================
--- /dev/null
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
@@ -0,0 +1,338 @@
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers. Derived from
+ * "arch/x86/kernel/hw_breakpoint.c"
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010 IBM Corporation
+ * Author: K.Prasad <prasad@linux.vnet.ibm.com>
+ *
+ */
+
+#include <linux/hw_breakpoint.h>
+#include <linux/notifier.h>
+#include <linux/kprobes.h>
+#include <linux/percpu.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm/hw_breakpoint.h>
+#include <asm/processor.h>
+#include <asm/sstep.h>
+
+/*
+ * Stores the breakpoints currently in use on each breakpoint address
+ * register for every cpu
+ */
+static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
+
+/*
+ * Install a perf counter breakpoint.
+ *
+ * We seek a free debug address register and use it for this
+ * breakpoint.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+ struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+ struct perf_event **slot = &__get_cpu_var(bp_per_reg);
+
+ *slot = bp;
+
+ /*
+ * Do not install DABR values if the instruction must be single-stepped.
+ * If so, DABR will be populated in single_step_dabr_instruction().
+ */
+ if (current->thread.last_hit_ubp != bp)
+ set_dabr(info->address | info->type | DABR_TRANSLATION);
+
+ return 0;
+}
+
+/*
+ * Uninstall the breakpoint contained in the given counter.
+ *
+ * First we search the debug address register it uses and then we disable
+ * it.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+ struct perf_event **slot = &__get_cpu_var(bp_per_reg);
+
+ if (*slot != bp) {
+ WARN_ONCE(1, "Can't find the breakpoint");
+ return;
+ }
+
+ *slot = NULL;
+ set_dabr(0);
+}
+
+/*
+ * Perform cleanup of arch-specific counters during unregistration
+ * of the perf-event
+ */
+void arch_unregister_hw_breakpoint(struct perf_event *bp)
+{
+ /*
+ * If the breakpoint is unregistered between a hw_breakpoint_handler()
+ * and the single_step_dabr_instruction(), then cleanup the breakpoint
+ * restoration variables to prevent dangling pointers.
+ */
+ if (bp->ctx->task)
+ bp->ctx->task->thread.last_hit_ubp = NULL;
+
+ put_cpu();
+}
+
+/*
+ * Check for virtual address in kernel space.
+ */
+int arch_check_bp_in_kernelspace(struct perf_event *bp)
+{
+ struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+ return is_kernel_addr(info->address);
+}
+
+int arch_bp_generic_fields(int type, int *gen_bp_type)
+{
+ switch (type) {
+ case DABR_DATA_READ:
+ *gen_bp_type = HW_BREAKPOINT_R;
+ break;
+ case DABR_DATA_WRITE:
+ *gen_bp_type = HW_BREAKPOINT_W;
+ break;
+ case (DABR_DATA_WRITE | DABR_DATA_READ):
+ *gen_bp_type = (HW_BREAKPOINT_W | HW_BREAKPOINT_R);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings
+ */
+int arch_validate_hwbkpt_settings(struct perf_event *bp)
+{
+ int ret = -EINVAL;
+ struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+ if (!bp)
+ return ret;
+
+ switch (bp->attr.bp_type) {
+ case HW_BREAKPOINT_R:
+ info->type = DABR_DATA_READ;
+ break;
+ case HW_BREAKPOINT_W:
+ info->type = DABR_DATA_WRITE;
+ break;
+ case HW_BREAKPOINT_R | HW_BREAKPOINT_W:
+ info->type = (DABR_DATA_READ | DABR_DATA_WRITE);
+ break;
+ default:
+ return ret;
+ }
+
+ info->address = bp->attr.bp_addr;
+ info->len = bp->attr.bp_len;
+
+ /*
+ * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
+ * and breakpoint addresses are aligned to nearest double-word
+ * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
+ * 'symbolsize' should satisfy the check below.
+ */
+ if (info->len >
+ (HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
+ return -EINVAL;
+ return 0;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_handler(struct die_args *args)
+{
+ bool is_ptrace_bp = false;
+ int rc = NOTIFY_STOP;
+ struct perf_event *bp;
+ struct pt_regs *regs = args->regs;
+ unsigned long dar = regs->dar;
+ int stepped = 1;
+ struct arch_hw_breakpoint *info;
+
+ /* Disable breakpoints during exception handling */
+ set_dabr(0);
+ /*
+ * The counter may be concurrently released but that can only
+ * occur from a call_rcu() path. We can then safely fetch
+ * the breakpoint, use its callback, touch its counter
+ * while we are in an rcu_read_lock() path.
+ */
+ rcu_read_lock();
+
+ bp = __get_cpu_var(bp_per_reg);
+ if (!bp)
+ goto out;
+ info = counter_arch_bp(bp);
+ is_ptrace_bp = (bp->overflow_handler == ptrace_triggered) ?
+ true : false;
+
+ /*
+ * Verify if dar lies within the address range occupied by the symbol
+ * being watched to filter extraneous exceptions.
+ */
+ if (!((bp->attr.bp_addr <= dar) &&
+ (dar <= (bp->attr.bp_addr + bp->attr.bp_len))) &&
+ (!is_ptrace_bp))
+ /*
+ * This exception is triggered not because of a memory access on
+ * the monitored variable but in the double-word address range
+ * in which it is contained. We will consume this exception,
+ * considering it as 'noise'.
+ */
+ goto restore_bp;
+
+ /*
+ * Return early after invoking user-callback function without restoring
+ * DABR if the breakpoint is from ptrace which always operates in
+ * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
+ * generated in do_dabr().
+ */
+ if (is_ptrace_bp) {
+ perf_bp_event(bp, regs);
+ rc = NOTIFY_DONE;
+ goto out;
+ }
+
+ /* Do not emulate user-space instructions, instead single-step them */
+ if (user_mode(regs)) {
+ bp->ctx->task->thread.last_hit_ubp = bp;
+ regs->msr |= MSR_SE;
+ goto out;
+ }
+
+ stepped = emulate_step(regs, regs->nip);
+ /*
+ * emulate_step() could not execute it. We've failed in reliably
+ * handling the hw-breakpoint. Unregister it and throw a warning
+ * message to let the user know about it.
+ */
+ if (!stepped) {
+ WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
+ "0x%lx will be uninstalled.", info->address);
+ unregister_hw_breakpoint(bp);
+ goto out;
+ }
+ /*
+ * As a policy, the callback is invoked in a 'trigger-after-execute'
+ * fashion
+ */
+ perf_bp_event(bp, regs);
+
+restore_bp:
+ set_dabr(info->address | info->type | DABR_TRANSLATION);
+out:
+ rcu_read_unlock();
+ return rc;
+}
+
+/*
+ * Handle single-step exceptions following a DABR hit.
+ */
+int __kprobes single_step_dabr_instruction(struct die_args *args)
+{
+ struct pt_regs *regs = args->regs;
+ struct perf_event *bp = NULL;
+ struct arch_hw_breakpoint *bp_info;
+
+ bp = current->thread.last_hit_ubp;
+ /*
+ * Check if we are single-stepping as a result of a
+ * previous HW Breakpoint exception
+ */
+ if (!bp)
+ return NOTIFY_DONE;
+
+ bp_info = counter_arch_bp(bp);
+
+ /*
+ * We shall invoke the user-defined callback function in the single
+ * stepping handler to confirm to 'trigger-after-execute' semantics
+ */
+ perf_bp_event(bp, regs);
+
+ /*
+ * Do not disable MSR_SE if the process was already in
+ * single-stepping mode.
+ */
+ if (!test_thread_flag(TIF_SINGLESTEP))
+ regs->msr &= ~MSR_SE;
+
+ set_dabr(bp_info->address | bp_info->type | DABR_TRANSLATION);
+ return NOTIFY_STOP;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_exceptions_notify(
+ struct notifier_block *unused, unsigned long val, void *data)
+{
+ int ret = NOTIFY_DONE;
+
+ switch (val) {
+ case DIE_DABR_MATCH:
+ ret = hw_breakpoint_handler(data);
+ break;
+ case DIE_SSTEP:
+ ret = single_step_dabr_instruction(data);
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * Release the user breakpoints used by ptrace
+ */
+void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+ struct thread_struct *t = &tsk->thread;
+
+ unregister_hw_breakpoint(t->ptrace_bps[0]);
+ t->ptrace_bps[0] = NULL;
+}
+
+void hw_breakpoint_pmu_read(struct perf_event *bp)
+{
+ /* TODO */
+}
+
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/Makefile
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/Makefile
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/Makefile
@@ -34,6 +34,7 @@ obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
signal_64.o ptrace32.o \
paca.o nvram_64.o firmware.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/processor.h
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/processor.h
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/processor.h
@@ -209,6 +209,14 @@ struct thread_struct {
#ifdef CONFIG_PPC64
unsigned long start_tb; /* Start purr when proc switched in */
unsigned long accum_tb; /* Total accumilated purr for process */
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ struct perf_event *ptrace_bps[HBP_NUM];
+ /*
+ * Helps identify source of single-step exception and subsequent
+ * hw-breakpoint enablement
+ */
+ struct perf_event *last_hit_ubp;
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
unsigned long dabr; /* Data address breakpoint register */
#ifdef CONFIG_ALTIVEC
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/ptrace.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/ptrace.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/ptrace.c
@@ -32,6 +32,8 @@
#ifdef CONFIG_PPC32
#include <linux/module.h>
#endif
+#include <linux/hw_breakpoint.h>
+#include <linux/perf_event.h>
#include <asm/uaccess.h>
#include <asm/page.h>
@@ -866,9 +868,34 @@ void user_disable_single_step(struct tas
clear_tsk_thread_flag(task, TIF_SINGLESTEP);
}
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+void ptrace_triggered(struct perf_event *bp, int nmi,
+ struct perf_sample_data *data, struct pt_regs *regs)
+{
+ struct perf_event_attr attr;
+
+ /*
+ * Disable the breakpoint request here since ptrace has defined a
+ * one-shot behaviour for breakpoint exceptions in PPC64.
+ * The SIGTRAP signal is generated automatically for us in do_dabr().
+ * We don't have to do anything about that here
+ */
+ attr = bp->attr;
+ attr.disabled = true;
+ modify_user_hw_breakpoint(bp, &attr);
+}
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
unsigned long data)
{
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ int ret;
+ struct thread_struct *thread = &(task->thread);
+ struct perf_event *bp;
+ struct perf_event_attr attr;
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
/* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
* For embedded processors we support one DAC and no IAC's at the
* moment.
@@ -896,6 +923,43 @@ int ptrace_set_debugreg(struct task_stru
/* Ensure breakpoint translation bit is set */
if (data && !(data & DABR_TRANSLATION))
return -EIO;
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ bp = thread->ptrace_bps[0];
+ if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
+ if (bp) {
+ unregister_hw_breakpoint(bp);
+ thread->ptrace_bps[0] = NULL;
+ }
+ return 0;
+ }
+ if (bp) {
+ attr = bp->attr;
+ attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
+ arch_bp_generic_fields(data &
+ (DABR_DATA_WRITE | DABR_DATA_READ),
+ &attr.bp_type);
+ ret = modify_user_hw_breakpoint(bp, &attr);
+ if (ret)
+ return ret;
+ thread->ptrace_bps[0] = bp;
+ thread->dabr = data;
+ return 0;
+ }
+
+ /* Create a new breakpoint request if one doesn't exist already */
+ hw_breakpoint_init(&attr);
+ attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
+ arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
+ &attr.bp_type);
+
+ thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
+ ptrace_triggered, task);
+ if (IS_ERR(bp)) {
+ thread->ptrace_bps[0] = NULL;
+ return PTR_ERR(bp);
+ }
+
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
/* Move contents to the DABR register */
task->thread.dabr = data;
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/process.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/process.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/process.c
@@ -462,8 +462,14 @@ struct task_struct *__switch_to(struct t
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
switch_booke_debug_regs(&new->thread);
#else
+/*
+ * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
+ * schedule DABR
+ */
+#ifndef CONFIG_HAVE_HW_BREAKPOINT
if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
set_dabr(new->thread.dabr);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/cputable.h
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/cputable.h
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/cputable.h
@@ -516,6 +516,10 @@ static inline int cpu_has_feature(unsign
& feature);
}
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+#define HBP_NUM 1
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/machine_kexec_64.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/machine_kexec_64.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/machine_kexec_64.c
@@ -25,6 +25,7 @@
#include <asm/sections.h> /* _end */
#include <asm/prom.h>
#include <asm/smp.h>
+#include <asm/hw_breakpoint.h>
int default_machine_kexec_prepare(struct kimage *image)
{
@@ -165,6 +166,7 @@ static void kexec_smp_down(void *arg)
while(kexec_all_irq_disabled == 0)
cpu_relax();
mb(); /* make sure all irqs are disabled before this */
+ hw_breakpoint_disable();
/*
* Now every CPU has IRQs off, we can clear out any pending
* IPIs and be sure that no more will come in after this.
@@ -180,6 +182,7 @@ static void kexec_prepare_cpus_wait(int
{
int my_cpu, i, notified=-1;
+ hw_breakpoint_disable();
my_cpu = get_cpu();
/* Make sure each CPU has atleast made it to the state we need */
for (i=0; i < NR_CPUS; i++) {
Index: linux-2.6.ppc64_test/arch/powerpc/lib/Makefile
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/lib/Makefile
+++ linux-2.6.ppc64_test/arch/powerpc/lib/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PPC64) += copypage_64.o cop
memcpy_64.o usercopy_64.o mem_64.o string.o
obj-$(CONFIG_XMON) += sstep.o
obj-$(CONFIG_KPROBES) += sstep.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o
ifeq ($(CONFIG_PPC64),y)
obj-$(CONFIG_SMP) += locks.o
Index: linux-2.6.ppc64_test/arch/powerpc/Kconfig
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/Kconfig
+++ linux-2.6.ppc64_test/arch/powerpc/Kconfig
@@ -141,6 +141,7 @@ config PPC
select GENERIC_ATOMIC64 if PPC32
select HAVE_PERF_EVENTS
select HAVE_REGS_AND_STACK_ACCESS_API
+ select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
config EARLY_PRINTK
bool
^ permalink raw reply
* [Patch 1/4] Allow arch-specific cleanup before breakpoint unregistration
From: K.Prasad @ 2010-05-25 9:13 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras,
Linux Kernel Mailing List
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100525083055.342788418@linux.vnet.ibm.com>
Certain architectures (such as PowerPC Book III S) have a need to cleanup
data-structures before the breakpoint is unregistered. This patch introduces
an arch-specific hook in release_bp_slot() along with a weak definition in
the form of a stub funciton.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
kernel/hw_breakpoint.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: linux-2.6.ppc64_test/kernel/hw_breakpoint.c
===================================================================
--- linux-2.6.ppc64_test.orig/kernel/hw_breakpoint.c
+++ linux-2.6.ppc64_test/kernel/hw_breakpoint.c
@@ -242,6 +242,17 @@ toggle_bp_slot(struct perf_event *bp, bo
}
/*
+ * Function to perform processor-specific cleanup during unregistration
+ */
+__weak void arch_unregister_hw_breakpoint(struct perf_event *bp)
+{
+ /*
+ * A weak stub function here for those archs that don't define
+ * it inside arch/.../kernel/hw_breakpoint.c
+ */
+}
+
+/*
* Contraints to check before allowing this new breakpoint counter:
*
* == Non-pinned counter == (Considered as pinned for now)
@@ -339,6 +350,7 @@ void release_bp_slot(struct perf_event *
{
mutex_lock(&nr_bp_mutex);
+ arch_unregister_hw_breakpoint(bp);
__release_bp_slot(bp);
mutex_unlock(&nr_bp_mutex);
^ permalink raw reply
* [Patch 0/4] PPC64-HWBKPT: Hardware Breakpoint interfaces - ver XXI
From: K.Prasad @ 2010-05-25 9:13 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, Roland McGrath
Hi All,
Please find a new version of the hw-breakpoint patchset with
changes as described below.
The patchset, passes when tested against breakpoints caused by user-space
instructions but fails against kernel-space instructions (as a result of
emulate_step() failure). They should begin to work fine with further
enhancements to emulate_step().
Changelog - ver XXI
--------------------
(Version XIX: linuxppc-dev ref:20100524103136.GA8131@in.ibm.com)
- Decision to emulate an instruction is now based on whether the causative
instruction is in user_mode() or not.
- Breakpoints don't have to be cleared during sigreturn. A 'double-hit' on
hw_breakpoint_handler() is harmless for non-ptrace instructions.
- Minor changes to enhance code brevity.
Kindly let me know your comments.
Thanks,
K.Prasad
Changelog - ver XX
--------------------
(Version XIX: linuxppc-dev ref: 20100524040137.GA20873@in.ibm.com)
- Non task-bound breakpoints will only be emulated. Breakpoint will be
unregistered with a warning if emulation fails.
Changelog - ver XIX
--------------------
(Version XVIII: linuxppc-dev ref: 20100512033055.GA6384@in.ibm.com)
- Increased coverage of breakpoints during concurrent alignment_exception
and signal handling (which previously had 'blind-spots').
- Support for kernel-thread breakpoints and kernel-space breakpoints inside the
context of a user-space process.
- Patches re-based to commit f4b87dee923342505e1ddba8d34ce9de33e75050, thereby
necessitating minor changes to arch_validate_hwbkpt_settings().
Changelog - ver XVIII
--------------------
(Version XVII: linuxppc-dev ref: 20100414034340.GA6571@in.ibm.com)
- Slight code restructuring for brevity and coding-style corrections.
- emulate_single_step() now notifies DIE_SSTEP to registered handlers;
causes single_step_dabr_instruction() to be invoked after alignment_exception.
- hw-breakpoint restoration variables are cleaned-up before unregistration
through arch_unregister_hw_breakpoint().
- SIGTRAP is no longer generated for non-ptrace user-space breakpoints.
Changelog - ver XVII
--------------------
(Version XVI: linuxppc-dev ref: 20100330095809.GA14403@in.ibm.com)
- CONFIG_HAVE_HW_BREAKPOINT is now used to define the scope of the new code
(in lieu of CONFIG_PPC_BOOK3S_64).
- CONFIG_HAVE_HW_BREAKPOINT is now dependant upon CONFIG_PERF_EVENTS and
CONFIG_PPC_BOOK3S_64 (to overcome build failures under certain configs).
- Included a target in arch/powerpc/lib/Makefile to build sstep.o when
HAVE_HW_BREAKPOINT.
- Added a dummy definition for hw_breakpoint_disable() when !HAVE_HW_BREAKPOINT.
- Tested builds under defconfigs for ppc64, cell and g5 (found no patch induced
failures).
Changelog - ver XVI
--------------------
(Version XV: linuxppc-dev ref: 20100323140639.GA21836@in.ibm.com)
- Used a new config option CONFIG_PPC_BOOK3S_64 (in lieu of
CONFIG_PPC64/CPU_FTR_HAS_DABR) to limit the scope of the new code.
- Disabled breakpoints before kexec of the machine using hw_breakpoint_disable().
- Minor optimisation in exception-64s.S to check for data breakpoint exceptions
in DSISR finally (after check for other causes) + changes in code comments and
representation of DSISR_DABRMATCH constant.
- Rebased to commit ae6be51ed01d6c4aaf249a207b4434bc7785853b of linux-2.6.
Changelog - ver XV
--------------------
(Version XIV: linuxppc-dev ref: 20100308181232.GA3406@in.ibm.com)
- Additional patch to disable interrupts during data breakpoint exception
handling.
- Moved HBP_NUM definition to cputable.h under a new CPU_FTR definition
(CPU_FTR_HAS_DABR).
- Filtering of extraneous exceptions (due to accesses outside symbol length) is
by-passed for ptrace requests.
- Removed flush_ptrace_hw_breakpoint() from __switch_to() due to incorrect
coding placement.
- Changes to code comments as per community reviews for previous version.
- Minor coding-style changes in hw_breakpoint.c as per review comments.
- Re-based to commit ae6be51ed01d6c4aaf249a207b4434bc7785853b of linux-2.6
Changelog - ver XIV
--------------------
(Version XIII: linuxppc-dev ref: 20100215055605.GB3670@in.ibm.com)
- Removed the 'name' field from 'struct arch_hw_breakpoint'.
- All callback invocations through bp->overflow_handler() are replaced with
perf_bp_event().
- Removed the check for pre-existing single-stepping mode in
hw_breakpoint_handler() as this check is unreliable while in kernel-space.
Side effect of this change is the non-triggering of hw-breakpoints while
single-stepping kernel through KGDB or Xmon.
- Minor code-cleanups and addition of comments in hw_breakpoint_handler() and
single_step_dabr_instruction().
- Re-based to commit 25cf84cf377c0aae5dbcf937ea89bc7893db5176 of linux-2.6
Changelog - ver XIII
--------------------
(Version XII: linuxppc-dev ref: 20100121084640.GA3252@in.ibm.com)
- Fixed a bug for user-space breakpoints (triggered following the failure of a
breakpoint request).
- Re-based on commit 724e6d3fe8003c3f60bf404bf22e4e331327c596 of linux-2.6
Changelog - ver XII
--------------------
(Version XI: linuxppc-dev ref: 20100119091234.GA9971@in.ibm.com)
- Unset MSR_SE only if kernel was not previously in single-step mode.
- Pre-emption is now enabled before returning from the hw-breakpoint exception
handler.
- Variables to track the source of single-step exception (breakpoint from kernel,
user-space vs single-stepping due to other requests) are added.
- Extraneous hw-breakpoint exceptions (due to memory accesses lying outside
monitored symbol length) is now done for both kernel and user-space
(previously only user-space).
- single_step_dabr_instruction() now returns NOTIFY_DONE if kernel was in
single-step mode even before the hw-breakpoint. This enables other users of
single-step mode to be notified of the exception.
- User-space instructions are not emulated from kernel-space, they are instead
single-stepped.
Changelog - ver XI
------------------
(Version X: linuxppc-dev ref: 20091211160144.GA23156@in.ibm.com)
- Conditionally unset MSR_SE in the single-step handler
- Added comments to explain the duration and need for pre-emption
disable following hw-breakpoint exception.
Changelog - ver X
------------------
- Re-write the PPC64 patches for the new implementation of hw-breakpoints that
uses the perf-layer.
- Rebased to commit 7622fc234190a37d4e9fe3ed944a2b61a63fca03 of -tip.
Changelog - ver IX
-------------------
- Invocation of user-defined callback will be 'trigger-after-execute' (except
for ptrace).
- Creation of a new global per-CPU breakpoint structure to help invocation of
user-defined callback from single-step handler.
(Changes made now)
- Validation before registration will fail only if the address does not match
the kernel symbol's (if specified) resolved address
(through kallsyms_lookup_name()).
- 'symbolsize' value is expected to within the range contained by the symbol's
starting address and the end of a double-word boundary (8 Bytes).
- PPC64's arch-dependant code is now aware of 'cpumask' in 'struct hw_breakpoint'
and can accomodate requests for a subset of CPUs in the system.
- Introduced arch_disable_hw_breakpoint() required for
<enable><disable>_hw_breakpoint() APIs.
Changelog - ver VIII
-------------------
- Reverting changes to allow one-shot breakpoints only for ptrace requests.
- Minor changes in sanity checking in arch_validate_hwbkpt_settings().
- put_cpu_no_resched() is no longer available. Converted to put_cpu().
Changelog - ver VII
-------------------
- Allow the one-shot behaviour for exception handlers to be defined by the user.
A new 'is_one_shot' flag is added to 'struct arch_hw_breakpoint'.
Changelog - ver VI
------------------
The task of identifying 'genuine' breakpoint exceptions from those caused by
'out-of-range' accesses turned out to be more tricky than originally thought.
Some changes to this effect were made in version IV of this patchset, but they
were not sufficient for user-space. Basically the breakpoint address received
through ptrace is always aligned to 8-bytes since ptrace receives an encoded
'data' (consisting of address | translation_enable | bkpt_type), and the size of
the symbol is not known. However for kernel-space addresses, the symbol-size can
be determined using kallsyms_lookup_size_offset() and this is used to check if
DAR (in the exception context) is
'bkpt_address <= DAR <= (bkpt_address + symbol_size)', failing which we conclude
it as a stray exception.
The following changes are made to enable check:
- Addition of a symbolsize field in 'struct arch_hw_breakpoint' field.
- Store the size of the 'watched' kernel symbol into 'symbolsize' field in
arch_store_info(0 routine.
- Verify if the above described condition is true when is_one_shot is FALSE in
hw_breakpoint_handler().
Changelog - ver V
------------------
- Breakpoint requests from ptrace (for user-space) are designed to be one-shot
in PPC64. The patch contains changes to retain this behaviour by returning early
in hw_breakpoint_handler() [without re-initialising DABR] and unregistering the
user-space request in ptrace_triggered(). It is safe to make a
unregister_user_hw_breakpoint() call from the breakpoint exception context
[through ptrace_triggered()] without giving rise to circular locking-dependancy.
This is because there can be no kernel code running on the CPU (which received
the exception) with the same spinlock held.
- Minor change in 'type' member of 'struct arch_hw_breakpoint' from u8 to 'int'.
Changelog - ver IV
------------------
- While DABR register requires double-word (8 bytes) aligned addresses, i.e.
the breakpoint is active over a range of 8 bytes, PPC64 allows byte-level
addressability. This may lead to stray exceptions which have to be ignored in
hw_breakpoint_handler(), when DAR != (Breakpoint request address). However DABR
will be populated with the requested breakpoint address aligned to the previous
double-word address. The code is now modified to store user-requested address
in 'bp->info.address' but update the DABR with a double-word aligned address.
- Please note that the Data Breakpoint facility in Xmon is broken as of 2.6.29
and the same has not been integrated into this facility as described in Ver I.
Changelog - ver III
------------------
- Patches are based on commit 08f16e060bf54bdc34f800ed8b5362cdeda75d8b of -tip
tree.
- The declarations in arch/powerpc/include/asm/hw_breakpoint.h are done only if
CONFIG_PPC64 is defined. This eliminates the need to conditionally include this
header file.
- load_debug_registers() is done in start_secondary() i.e. during CPU
initialisation.
- arch_check_va_<> routines in hw_breakpoint.c are now replaced with a much
simpler is_kernel_addr() check in arch_validate_hwbkpt_settings()
- Return code of hw_breakpoint_handler() when triggered due to Lazy debug
register switching is now changed to NOTIFY_STOP.
- The ptrace code no longer sets the TIF_DEBUG task flag as it is proposed to
be done in register_user_hw_breakpoint() routine.
- hw_breakpoint_handler() is now modified to use hbp_kernel_pos value to
determine if the trigger was a user/kernel space address. The DAR register
value is checked with the address stored in 'struct hw_breakpoint' to avoid
handling of exceptions that belong to kprobe/Xmon.
Changelog - ver II
------------------
- Split the monolithic patch into six logical patches
- Changed the signature of arch_check_va_in_<user><kernel>space functions. They
are now marked static.
- HB_NUM is now called as HBP_NUM (to preserve a consistent short-name
convention)
- Introduced hw_breakpoint_disable() and changes to kexec code to disable
breakpoints before a reboot.
- Minor changes in ptrace code to use macro-defined constants instead of
numbers.
- Introduced a new constant definition INSTRUCTION_LEN in reg.h
^ permalink raw reply
* Re: mmio_nvram.c users ?
From: Martyn Welch @ 2010-05-25 8:43 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <1274773439.1931.238.camel@pasglop>
One day I'll manage to hit "Reply" or "Reply All" correctly...
Benjamin Herrenschmidt wrote:
> Hi folks !
>
> Anybody aware of anything other than Cell using that driver ?
>
> I'd like to make it a platform driver instead of having something that
> pokes at anything that has a "device_type" set to "nvram" (which is
> gross and bogus). But I need to know what platforms to fixup...
>
>
We do on our boards, that would currently be the sbc310, sbc610 and
ppc9a (all FSL 86xx based boards). I also have 2 other boards I'm
currently working on that will also use that driver.
Martyn
> Cheers,
> Ben.
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748 | Barbirolli Square, Manchester,
E martyn.welch@ge.com | M2 3AB VAT:GB 927559189
^ permalink raw reply
* Re: mmio_nvram.c users ?
From: Adrian Reber @ 2010-05-25 8:41 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <1274773439.1931.238.camel@pasglop>
On Tue, May 25, 2010 at 05:43:59PM +1000, Benjamin Herrenschmidt wrote:
> Anybody aware of anything other than Cell using that driver ?
>
> I'd like to make it a platform driver instead of having something that
> pokes at anything that has a "device_type" set to "nvram" (which is
> gross and bogus). But I need to know what platforms to fixup...
The PowerStation is also using it.
Adrian
^ permalink raw reply
* [PATCH v3] powerpc: Add i8042 keyboard and mouse irq parsing
From: Martyn Welch @ 2010-05-25 8:09 UTC (permalink / raw)
To: Grant Likely, benh; +Cc: linuxppc-dev, Dmitry Torokhov, linux-input
Currently the irqs for the i8042, which historically provides keyboard and
mouse (aux) support, is hardwired in the driver rather than parsing the
dts. This patch modifies the powerpc legacy IO code to attempt to parse
the device tree for this information, failing back to the hardcoded values
if it fails.
Signed-off-by: Martyn Welch <martyn.welch@ge.com>
---
v2: This patch no longer requires the DTS files to be modified, reading the
interrupts from the current location as suggested by Grant.
v3: Code compacted as suggested by Grant.
arch/powerpc/kernel/setup-common.c | 13 +++++++++++++
drivers/input/serio/i8042-io.h | 5 +++++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 48f0a00..3d169bb 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -94,6 +94,10 @@ struct screen_info screen_info = {
.orig_video_points = 16
};
+/* Variables required to store legacy IO irq routing */
+int of_i8042_kbd_irq;
+int of_i8042_aux_irq;
+
#ifdef __DO_IRQ_CANON
/* XXX should go elsewhere eventually */
int ppc_do_canonicalize_irqs;
@@ -567,6 +571,15 @@ int check_legacy_ioport(unsigned long base_port)
np = of_find_compatible_node(NULL, NULL, "pnpPNP,f03");
if (np) {
parent = of_get_parent(np);
+
+ of_i8042_kbd_irq = irq_of_parse_and_map(parent, 0);
+ if (!of_i8042_kbd_irq)
+ of_i8042_kbd_irq = 1;
+
+ of_i8042_aux_irq = irq_of_parse_and_map(parent, 1);
+ if (!of_i8042_aux_irq)
+ of_i8042_aux_irq = 12;
+
of_node_put(np);
np = parent;
break;
diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
index 847f4aa..5d48bb6 100644
--- a/drivers/input/serio/i8042-io.h
+++ b/drivers/input/serio/i8042-io.h
@@ -27,6 +27,11 @@
#include <asm/irq.h>
#elif defined(CONFIG_SH_CAYMAN)
#include <asm/irq.h>
+#elif defined(CONFIG_PPC)
+extern int of_i8042_kbd_irq;
+extern int of_i8042_aux_irq;
+# define I8042_KBD_IRQ of_i8042_kbd_irq
+# define I8042_AUX_IRQ of_i8042_aux_irq
#else
# define I8042_KBD_IRQ 1
# define I8042_AUX_IRQ 12
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748 | Barbirolli Square, Manchester,
E martyn.welch@ge.com | M2 3AB VAT:GB 927559189
^ permalink raw reply related
* mmio_nvram.c users ?
From: Benjamin Herrenschmidt @ 2010-05-25 7:43 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: linuxppc-dev
Hi folks !
Anybody aware of anything other than Cell using that driver ?
I'd like to make it a platform driver instead of having something that
pokes at anything that has a "device_type" set to "nvram" (which is
gross and bogus). But I need to know what platforms to fixup...
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v2] powerpc: Add i8042 keyboard and mouse irq parsing
From: Martyn Welch @ 2010-05-25 7:52 UTC (permalink / raw)
To: Grant Likely; +Cc: Dmitry Torokhov, linux-input, linuxppc-dev
In-Reply-To: <AANLkTikrakCQhSn9y07sSKlc2QuLU1Mg52Ko_cSsx2lZ@mail.gmail.com>
Grant Likely wrote:
> On Mon, May 24, 2010 at 10:25 AM, Martyn Welch <martyn.welch@ge.com> wrote:
>
>> Currently the irqs for the i8042, which historically provides keyboard and
>> mouse (aux) support, is hardwired in the driver rather than parsing the
>> dts. This patch modifies the powerpc legacy IO code to attempt to parse
>> the device tree for this information, failing back to the hardcoded values
>> if it fails.
>>
>> Signed-off-by: Martyn Welch <martyn.welch@ge.com>
>> ---
>>
>> v2: This patch no longer requires the DTS files to be modified, reading the
>> interrupts from the current location as suggested by Grant.
>>
>> arch/powerpc/kernel/setup-common.c | 49 ++++++++++++++++++++++++++++++++++--
>> drivers/input/serio/i8042-io.h | 8 ++++++
>> 2 files changed, 54 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
>> index 48f0a00..7f1bb99 100644
>> --- a/arch/powerpc/kernel/setup-common.c
>> +++ b/arch/powerpc/kernel/setup-common.c
>> @@ -94,6 +94,10 @@ struct screen_info screen_info = {
>> .orig_video_points = 16
>> };
>>
>> +/* Variables required to store legacy IO irq routing */
>> +int of_i8042_kbd_irq;
>> +int of_i8042_aux_irq;
>> +
>> #ifdef __DO_IRQ_CANON
>> /* XXX should go elsewhere eventually */
>> int ppc_do_canonicalize_irqs;
>> @@ -558,13 +562,52 @@ void probe_machine(void)
>> /* Match a class of boards, not a specific device configuration. */
>> int check_legacy_ioport(unsigned long base_port)
>> {
>> - struct device_node *parent, *np = NULL;
>> + struct device_node *parent, *np = NULL, *np_aux = NULL;
>> int ret = -ENODEV;
>>
>> switch(base_port) {
>> case I8042_DATA_REG:
>> - if (!(np = of_find_compatible_node(NULL, NULL, "pnpPNP,303")))
>> - np = of_find_compatible_node(NULL, NULL, "pnpPNP,f03");
>> + np = of_find_compatible_node(NULL, NULL, "pnpPNP,303");
>> + if (np) {
>> + /* Interrupt routing in parent node */
>> + parent = of_get_parent(np);
>> + if (parent) {
>> + /*
>> + * Attempt to parse DTS for keyboard irq,
>> + * fallback to standard.
>> + */
>> + of_i8042_kbd_irq = irq_of_parse_and_map(parent,
>> + 0);
>> + if (!of_i8042_kbd_irq)
>> + of_i8042_kbd_irq = 1;
>> +
>> + of_node_put(parent);
>> + }
>> + }
>> +
>> + np_aux = of_find_compatible_node(NULL, NULL, "pnpPNP,f03");
>> + if (np_aux) {
>> + if (!np) {
>> + of_node_put(np);
>> + np = np_aux;
>> + }
>> +
>> + /* Interrupt routing in parent node */
>> + parent = of_get_parent(np_aux);
>> + if (parent) {
>> + /*
>> + * Attempt to parse DTS for mouse (aux) irq,
>> + * fallback to standard.
>> + */
>> + of_i8042_aux_irq = irq_of_parse_and_map(parent,
>> + 1);
>> + if (!of_i8042_aux_irq)
>> + of_i8042_aux_irq = 12;
>> +
>> + of_node_put(parent);
>> + }
>> + }
>> +
>>
>
> This seems to be a lot more code that you need. The existing code
> already obtains a pointer to the parent node for you. All you really
> should need to add is the two calls to irq_of_parse_and_map() for
> obtaining the kbd and aux irq numbers.
>
Your right - new patch on it's way.
>> if (np) {
>> parent = of_get_parent(np);
>> of_node_put(np);
>> diff --git a/drivers/input/serio/i8042-io.h b/drivers/input/serio/i8042-io.h
>> index 847f4aa..8fc8753 100644
>> --- a/drivers/input/serio/i8042-io.h
>> +++ b/drivers/input/serio/i8042-io.h
>> @@ -19,6 +19,11 @@
>> * IRQs.
>> */
>>
>> +#if defined(CONFIG_PPC)
>> +extern int of_i8042_kbd_irq;
>> +extern int of_i8042_aux_irq;
>> +#endif
>>
>
> Please fold these two extern definitions into the #elif
> defined(CONFIG_PPC) block below.
>
Will do.
>> +
>> #ifdef __alpha__
>> # define I8042_KBD_IRQ 1
>> # define I8042_AUX_IRQ (RTC_PORT(0) == 0x170 ? 9 : 12) /* Jensen is special */
>> @@ -27,6 +32,9 @@
>> #include <asm/irq.h>
>> #elif defined(CONFIG_SH_CAYMAN)
>> #include <asm/irq.h>
>> +#elif defined(CONFIG_PPC)
>> +#define I8042_KBD_IRQ of_i8042_kbd_irq
>> +#define I8042_AUX_IRQ of_i8042_aux_irq
>> #else
>> # define I8042_KBD_IRQ 1
>> # define I8042_AUX_IRQ 12
>>
>
> Cheers,
> g.
>
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748 | Barbirolli Square, Manchester,
E martyn.welch@ge.com | M2 3AB VAT:GB 927559189
^ permalink raw reply
* Re: [PATCH v2] powerpc/85xx: Add P1021MDS board support
From: Kumar Gala @ 2010-05-25 6:43 UTC (permalink / raw)
To: Haiying Wang; +Cc: linuxppc-dev
In-Reply-To: <1274451372.3003.7.camel@r54964-12.am.freescale.net>
On May 21, 2010, at 9:16 AM, Haiying Wang wrote:
> P1021 is a dual e500v2 core based SOC with:
> * 3 eTSECs (eTSEC1/3 RGMII, eTSEC2 SGMII on this board)
> * 2 PCIe Controller
> * 1 USB2.0 controller
> * eSDHC, eSPI, I2C, DUART
> * eLBC (NAND, BCSR, PMC0/1)
> * Security Engine (SEC 3.3.2)
> * Quicc Engine (QE)
>=20
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> Signed-off-by: Yu Liu <Yu.Liu@freescale.com>
> ---
> v2: address the comments from Kumar.
> arch/powerpc/boot/dts/p1021mds.dts | 698 =
+++++++++++++++++++++++++++++
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 102 ++++-
> 2 files changed, 797 insertions(+), 3 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/p1021mds.dts
applied to next
- k=
^ permalink raw reply
* [git pull] Please pull powerpc.git next branch
From: Kumar Gala @ 2010-05-25 2:38 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
The following changes since commit 99ec28f183daa450faa7bdad6f932364ae325648:
FUJITA Tomonori (1):
powerpc: Remove unused 'protect4gb' boot parameter
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Andy Fleming (1):
powerpc/85xx: Enable support for ports 3 and 4 on 8548 CDS
Anton Vorontsov (1):
powerpc/fsl-booke: Add hibernation support for FSL BookE processors
Haiying Wang (1):
powerpc/85xx: Add P1021MDS board support
Lan Chunhe-B25806 (1):
powerpc/fsl_msi: Add multiple MSI bank support
Li Yang (5):
powerpc/fsl_msi: fix the conflict of virt_msir's chip_data
powerpc/fsl_msi: enable msi allocation in all banks
powerpc/fsl_msi: enable msi sharing through AMP OSes
powerpc/fsl_msi: add removal path and probe failing path
powerpc/85xx: Change MPC8572DS camp dtses for MSI sharing
Scott Wood (1):
powerpc/e500mc: Implement machine check handler.
Sebastian Andrzej Siewior (3):
powerpc/fsl-booke: fix the case where we are not in the first page
powerpc/fsl-booke: Move the entry setup code into a seperate file
powerpc/kexec: Add support for FSL-BookE
arch/powerpc/Kconfig | 2 +-
arch/powerpc/boot/dts/mpc8548cds.dts | 4 -
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts | 15 +-
arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts | 7 +-
arch/powerpc/boot/dts/p1021mds.dts | 698 ++++++++++++++++++++++++
arch/powerpc/include/asm/cputable.h | 1 +
arch/powerpc/include/asm/kexec.h | 13 +
arch/powerpc/include/asm/reg_booke.h | 33 +-
arch/powerpc/kernel/Makefile | 8 +-
arch/powerpc/kernel/cputable.c | 2 +-
arch/powerpc/kernel/crash.c | 4 +
arch/powerpc/kernel/fsl_booke_entry_mapping.S | 237 ++++++++
arch/powerpc/kernel/head_fsl_booke.S | 200 +-------
arch/powerpc/kernel/misc_32.S | 17 +
arch/powerpc/kernel/swsusp_booke.S | 193 +++++++
arch/powerpc/kernel/traps.c | 88 +++-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 102 ++++-
arch/powerpc/sysdev/fsl_msi.c | 117 ++++-
arch/powerpc/sysdev/fsl_msi.h | 3 +
19 files changed, 1494 insertions(+), 250 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1021mds.dts
create mode 100644 arch/powerpc/kernel/fsl_booke_entry_mapping.S
create mode 100644 arch/powerpc/kernel/swsusp_booke.S
^ permalink raw reply
* Re: [PATCH 2/2] powerpc, kdump: Fix race in kdump shutdown
From: Michael Neuling @ 2010-05-24 23:53 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, kexec, jlarrew, Anton Blanchard
In-Reply-To: <04AC722A-97CD-4451-B6AB-F4AC37EFAB1D@kernel.crashing.org>
In message <04AC722A-97CD-4451-B6AB-F4AC37EFAB1D@kernel.crashing.org> you wrote
:
>
> On May 24, 2010, at 2:23 PM, Kumar Gala wrote:
>
> >=20
> > On May 14, 2010, at 12:40 AM, Michael Neuling wrote:
> >=20
> >> When we are crashing, the crashing/primary CPU IPIs the secondaries =
> to
> >> turn off IRQs, go into real mode and wait in kexec_wait. While this
> >> is happening, the primary tears down all the MMU maps. Unfortunately
> >> the primary doesn't check to make sure the secondaries have entered
> >> real mode before doing this.
> >>=20
> >> On PHYP machines, the secondaries can take a long time shutting down
> >> the IRQ controller as RTAS calls are need. These RTAS calls need to
> >> be serialised which resilts in the secondaries contending in
> >> lock_rtas() and hence taking a long time to shut down.
> >>=20
> >> We've hit this on large POWER7 machines, where some secondaries are
> >> still waiting in lock_rtas(), when the primary tears down the HPTEs.
> >>=20
> >> This patch makes sure all secondaries are in real mode before the
> >> primary tears down the MMU. It uses the new kexec_state entry in the
> >> paca. It times out if the secondaries don't reach real mode after
> >> 10sec.
> >>=20
> >> Signed-off-by: Michael Neuling <mikey@neuling.org>
> >> ---
> >>=20
> >> arch/powerpc/kernel/crash.c | 27 +++++++++++++++++++++++++++
> >> 1 file changed, 27 insertions(+)
> >>=20
> >> Index: linux-2.6-ozlabs/arch/powerpc/kernel/crash.c
> >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> >> --- linux-2.6-ozlabs.orig/arch/powerpc/kernel/crash.c
> >> +++ linux-2.6-ozlabs/arch/powerpc/kernel/crash.c
> >> @@ -162,6 +162,32 @@ static void crash_kexec_prepare_cpus(int
> >> /* Leave the IPI callback set */
> >> }
> >>=20
> >> +/* wait for all the CPUs to hit real mode but timeout if they don't =
> come in */
> >> +static void crash_kexec_wait_realmode(int cpu)
> >> +{
> >> + unsigned int msecs;
> >> + int i;
> >> +
> >> + msecs =3D 10000;
> >> + for (i=3D0; i < NR_CPUS && msecs > 0; i++) {
> >> + if (i =3D=3D cpu)
> >> + continue;
> >> +
> >> + while (paca[i].kexec_state < KEXEC_STATE_REAL_MODE) {
> >> + barrier();
> >> + if (!cpu_possible(i)) {
> >> + break;
> >> + }
> >> + if (!cpu_online(i)) {
> >> + break;
> >> + }
> >> + msecs--;
> >> + mdelay(1);
> >> + }
> >> + }
> >> + mb();
> >> +}
> >> +
> >> /*
> >> * This function will be called by secondary cpus or by kexec cpu
> >> * if soft-reset is activated to stop some CPUs.
> >> @@ -412,6 +438,7 @@ void default_machine_crash_shutdown(stru
> >> crash_kexec_prepare_cpus(crashing_cpu);
> >> cpu_set(crashing_cpu, cpus_in_crash);
> >> crash_kexec_stop_spus();
> >=20
> > should this be
> >=20
> > #ifdef CONFIG_PPC_STD_MMU
> >=20
> >> + crash_kexec_wait_realmode(crashing_cpu);
> >=20
> > #endif
>
> I'm going to make it CONFIG_PPC_STD_MMU_64 as part of a Kexec book-e =
> patch
Ok, thanks, I'll leave it up to you then
Mikey
^ permalink raw reply
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