* [PATCH] [SCSI] ipr: Fix stack overflow in ipr_format_resource_path
From: Anton Blanchard @ 2010-06-02 11:16 UTC (permalink / raw)
To: brking, wayneb, betabandido; +Cc: linuxppc-dev, linux-scsi
Victor reported an oops during boot with 2.6.34 on a POWER6 JS22:
https://bugzilla.kernel.org/show_bug.cgi?id=16089
Checking ipr microcode levels
Unable to handle kernel paging request for instruction fetch
Faulting instruction address: 0x322d30312d31302c
...
Oops: Kernel access of bad area, sig: 11 [#1]
SMP NR_CPUS=128 NUMA pSeries
last sysfs file:
/sys/devices/pci0000:00/0000:00:01.0/host0/target0:255:255/0:255:255:255/resource_path
Modules linked in:
NIP: 322d30312d31302c LR: 322d30312d31302d CTR: c000000000375bec
REGS: c0000003d360f8f0 TRAP: 0400 Not tainted (2.6.34-vjj)
MSR: 8000000040009432 <EE,ME,IR,DR> CR: 28002484 XER: 20000020
TASK = c0000003d587d010[5163] 'iprupdate' THREAD: c0000003d360c000 CPU: 7
GPR00: 322d30312d31302d c0000003d360fb70 c000000000ad07c0 00000000000185a0
GPR04: 0000000000000001 c0000003d360fb10 04000affffffffff c0000000006a6700
GPR08: c000000000823383 0000000000000000 0000000000000020 0000000000000000
GPR12: 000000000000f032 c00000000f622e00 00000000000000ed 0000000000000000
GPR16: 00000000100b8808 0000000010020000 0000000010020000 0000000010010000
GPR20: 0000000010010000 0000000000000001 0000000000001000 000000001045eef8
GPR24: c0000003d360fdf8 302d31342d31302d 43302d30302d3030 2d30332d44352d34
GPR28: 422d33382d30302d 30302d30302d3030 2d30302d30302d30 302d30302d30302d
NIP [322d30312d31302c] 0x322d30312d31302c
LR [322d30312d31302d] 0x322d30312d31302d
A stack overflow. It turns out ipr_format_resource_path writes to a
passed in buffer using sprintf which is dangerous and in this case looks
to be the cause of the overflow.
The following patch passes in the length of the buffer and uses snprintf,
which fixes the fail for me. It doesn't fix the other issue, which is
why the loop in ipr_format_resource_path didn't terminate in the first place.
That can be fixed in a follow up patch.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: linux.trees.git/drivers/scsi/ipr.c
===================================================================
--- linux.trees.git.orig/drivers/scsi/ipr.c 2010-05-31 08:51:20.000000000 +1000
+++ linux.trees.git/drivers/scsi/ipr.c 2010-06-02 21:15:41.000000000 +1000
@@ -1132,17 +1132,20 @@ static int ipr_is_same_device(struct ipr
* ipr_format_resource_path - Format the resource path for printing.
* @res_path: resource path
* @buf: buffer
+ * @len: length of the buffer
*
* Return value:
* pointer to buffer
**/
-static char *ipr_format_resource_path(u8 *res_path, char *buffer)
+static char *ipr_format_resource_path(u8 *res_path, char *buffer,
+ unsigned int len)
{
int i;
+ char *p = buffer;
- sprintf(buffer, "%02X", res_path[0]);
+ p += snprintf(p, buffer + len - p, "%02X", res_path[0]);
for (i=1; res_path[i] != 0xff; i++)
- sprintf(buffer, "%s-%02X", buffer, res_path[i]);
+ p += snprintf(p, buffer + len - p, "-%02X", res_path[i]);
return buffer;
}
@@ -1187,7 +1190,8 @@ static void ipr_update_res_entry(struct
if (res->sdev && new_path)
sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
- ipr_format_resource_path(&res->res_path[0], &buffer[0]));
+ ipr_format_resource_path(&res->res_path[0],
+ &buffer[0], sizeof(buffer)));
} else {
res->flags = cfgtew->u.cfgte->flags;
if (res->flags & IPR_IS_IOA_RESOURCE)
@@ -1573,7 +1577,8 @@ static void ipr_log_sis64_config_error(s
ipr_err_separator;
ipr_err("Device %d : %s", i + 1,
- ipr_format_resource_path(&dev_entry->res_path[0], &buffer[0]));
+ ipr_format_resource_path(&dev_entry->res_path[0],
+ &buffer[0], sizeof(buffer)));
ipr_log_ext_vpd(&dev_entry->vpd);
ipr_err("-----New Device Information-----\n");
@@ -1919,13 +1924,15 @@ static void ipr_log64_fabric_path(struct
ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
path_active_desc[i].desc, path_state_desc[j].desc,
- ipr_format_resource_path(&fabric->res_path[0], &buffer[0]));
+ ipr_format_resource_path(&fabric->res_path[0],
+ &buffer[0], sizeof(buffer)));
return;
}
}
ipr_err("Path state=%02X Resource Path=%s\n", path_state,
- ipr_format_resource_path(&fabric->res_path[0], &buffer[0]));
+ ipr_format_resource_path(&fabric->res_path[0], &buffer[0],
+ sizeof(buffer)));
}
static const struct {
@@ -2066,7 +2073,9 @@ static void ipr_log64_path_elem(struct i
ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
path_status_desc[j].desc, path_type_desc[i].desc,
- ipr_format_resource_path(&cfg->res_path[0], &buffer[0]),
+ ipr_format_resource_path(&cfg->res_path[0],
+ &buffer[0],
+ sizeof(buffer)),
link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
return;
@@ -2074,7 +2083,8 @@ static void ipr_log64_path_elem(struct i
}
ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
"WWN=%08X%08X\n", cfg->type_status,
- ipr_format_resource_path(&cfg->res_path[0], &buffer[0]),
+ ipr_format_resource_path(&cfg->res_path[0], &buffer[0],
+ sizeof(buffer)),
link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
}
@@ -2139,7 +2149,8 @@ static void ipr_log_sis64_array_error(st
ipr_err("RAID %s Array Configuration: %s\n",
error->protection_level,
- ipr_format_resource_path(&error->last_res_path[0], &buffer[0]));
+ ipr_format_resource_path(&error->last_res_path[0], &buffer[0],
+ sizeof(buffer)));
ipr_err_separator;
@@ -2160,9 +2171,12 @@ static void ipr_log_sis64_array_error(st
ipr_err("Array Member %d:\n", i);
ipr_log_ext_vpd(&array_entry->vpd);
ipr_err("Current Location: %s",
- ipr_format_resource_path(&array_entry->res_path[0], &buffer[0]));
+ ipr_format_resource_path(&array_entry->res_path[0],
+ &buffer[0],
+ sizeof(buffer)));
ipr_err("Expected Location: %s",
- ipr_format_resource_path(&array_entry->expected_res_path[0], &buffer[0]));
+ ipr_format_resource_path(&array_entry->expected_res_path[0],
+ &buffer[0], sizeof(buffer)));
ipr_err_separator;
}
@@ -4099,7 +4113,9 @@ static ssize_t ipr_show_resource_path(st
res = (struct ipr_resource_entry *)sdev->hostdata;
if (res)
len = snprintf(buf, PAGE_SIZE, "%s\n",
- ipr_format_resource_path(&res->res_path[0], &buffer[0]));
+ ipr_format_resource_path(&res->res_path[0],
+ &buffer[0],
+ sizeof(buffer)));
spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
return len;
}
@@ -4351,7 +4367,9 @@ static int ipr_slave_configure(struct sc
scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
if (ioa_cfg->sis64)
sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
- ipr_format_resource_path(&res->res_path[0], &buffer[0]));
+ ipr_format_resource_path(&res->res_path[0],
+ &buffer[0],
+ sizeof(buffer)));
return 0;
}
spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
Index: linux.trees.git/drivers/scsi/ipr.h
===================================================================
--- linux.trees.git.orig/drivers/scsi/ipr.h 2010-05-31 08:51:20.000000000 +1000
+++ linux.trees.git/drivers/scsi/ipr.h 2010-06-02 21:15:41.000000000 +1000
@@ -1685,7 +1685,8 @@ struct ipr_ucode_image_header {
if ((hostrcb)->ioa_cfg->sis64) { \
printk(KERN_ERR IPR_NAME ": %s: " fmt, \
ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
- &hostrcb->rp_buffer[0]), \
+ &hostrcb->rp_buffer[0], \
+ sizeof(hostrcb->rp_buffer)), \
__VA_ARGS__); \
} else { \
ipr_ra_err((hostrcb)->ioa_cfg, \
^ permalink raw reply
* [PATCH] powerpc: Emulate most Book I instructions in emulate_step()
From: Paul Mackerras @ 2010-06-02 11:29 UTC (permalink / raw)
To: linuxppc-dev; +Cc: K.Prasad
This extends the emulate_step() function to handle a large proportion
of the Book I instructions implemented on current 64-bit server
processors. The aim is to handle all the load and store instructions
used in the kernel, plus all of the instructions that appear between
l[wd]arx and st[wd]cx., so this handles the Altivec/VMX lvx and stvx
and the VSX lxv2dx and stxv2dx instructions (implemented in POWER7).
The new code can emulate user mode instructions, and checks the
effective address for a load or store if the saved state is for
user mode. It doesn't handle little-endian mode at present.
For floating-point, Altivec/VMX and VSX instructions, it checks
that the saved MSR has the enable bit for the relevant facility
set, and if so, assumes that the FP/VMX/VSX registers contain
valid state, and does loads or stores directly to/from the
FP/VMX/VSX registers, using assembly helpers in ldstfp.S.
Instructions supported now include:
* Loads and stores, including some but not all VMX and VSX instructions,
and lmw/stmw
* Atomic loads and stores (l[dw]arx, st[dw]cx.)
* Integer arithmetic instructions (add, subtract, multiply, divide, etc.)
* Compare instructions
* Rotate and mask instructions
* Shift instructions
* Logical instructions (and, or, xor, etc.)
* Condition register logical instructions
* mtcrf, cntlz[wd], exts[bhw]
* isync, sync, lwsync, ptesync, eieio
* Cache operations (dcbf, dcbst, dcbt, dcbtst)
The overflow-checking arithmetic instructions are not included, but
they appear not to be ever used in C code. None of the floating
point, VMX or VSX computational instructions are included.
This uses decimal values for the minor opcodes in the switch statements
because that is what appears in the Power ISA specification, thus it is
easier to check that they are correct if they are in decimal.
Signed-off-by: Paul Mackerras <paulus@samba.org>
---
arch/powerpc/lib/Makefile | 4 +-
arch/powerpc/lib/ldstfp.S | 207 ++++++
arch/powerpc/lib/sstep.c | 1513 +++++++++++++++++++++++++++++++++++++++++++--
3 files changed, 1677 insertions(+), 47 deletions(-)
create mode 100644 arch/powerpc/lib/ldstfp.S
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 3040dac..7581dbf 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -18,8 +18,8 @@ obj-$(CONFIG_HAS_IOMEM) += devres.o
obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
memcpy_64.o usercopy_64.o mem_64.o string.o
-obj-$(CONFIG_XMON) += sstep.o
-obj-$(CONFIG_KPROBES) += sstep.o
+obj-$(CONFIG_XMON) += sstep.o ldstfp.o
+obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o
ifeq ($(CONFIG_PPC64),y)
obj-$(CONFIG_SMP) += locks.o
diff --git a/arch/powerpc/lib/ldstfp.S b/arch/powerpc/lib/ldstfp.S
new file mode 100644
index 0000000..a462767
--- /dev/null
+++ b/arch/powerpc/lib/ldstfp.S
@@ -0,0 +1,207 @@
+/*
+ * Floating-point, VMX/Altivec and VSX loads and stores
+ * for use in instruction emulation.
+ *
+ * Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/processor.h>
+#include <asm/ppc_asm.h>
+#include <asm/reg.h>
+#include <asm/asm-offsets.h>
+#include <linux/errno.h>
+
+ .macro inst32 op
+ reg = 0
+ .rept 32
+20: \op reg,0,r4
+ b 3f
+ .section __ex_table,"a"
+ PPC_LONG 20b,99f
+ .previous
+ reg = reg + 1
+ .endr
+ .endm
+
+/* Load FP reg N from float at *p. N is in r3, p in r4. */
+_GLOBAL(do_lfs)
+ mflr r0
+ mfmsr r6
+ ori r7,r6,MSR_FP
+ rlwinm r3,r3,3,0xf8
+ bcl 20,31,2f
+1: inst32 lfsx
+2: mflr r5
+ mtlr r0
+ add r8,r3,r5
+ mtctr r8
+ li r3,0
+ mtmsrd r7
+ isync
+ bctr
+99: li r3,-EFAULT
+3: mtmsrd r6
+ blr
+
+/* Load FP reg N from double at *p. N is in r3, p in r4. */
+_GLOBAL(do_lfd)
+ mflr r0
+ mfmsr r6
+ ori r7,r6,MSR_FP
+ rlwinm r3,r3,3,0xf8
+ bcl 20,31,2f
+1: inst32 lfdx
+2: mflr r5
+ mtlr r0
+ add r8,r3,r5
+ mtctr r8
+ li r3,0
+ mtmsrd r7
+ isync
+ bctr
+99: li r3,-EFAULT
+3: mtmsrd r6
+ blr
+
+
+/* Store FP reg N to float at *p. N is in r3, p in r4. */
+_GLOBAL(do_stfs)
+ mflr r0
+ mfmsr r6
+ ori r7,r6,MSR_FP
+ rlwinm r3,r3,3,0xf8
+ bcl 20,31,2f
+1: inst32 stfsx
+2: mflr r5
+ mtlr r0
+ add r8,r3,r5
+ mtctr r8
+ li r3,0
+ mtmsrd r7
+ isync
+ bctr
+99: li r3,-EFAULT
+3: mtmsrd r6
+ blr
+
+/* Store FP reg N to double at *p. N is in r3, p in r4. */
+_GLOBAL(do_stfd)
+ mflr r0
+ mfmsr r6
+ ori r7,r6,MSR_FP
+ rlwinm r3,r3,3,0xf8
+ bcl 20,31,2f
+1: inst32 stfdx
+2: mflr r5
+ mtlr r0
+ add r8,r3,r5
+ mtctr r8
+ li r3,0
+ mtmsrd r7
+ isync
+ bctr
+99: li r3,-EFAULT
+3: mtmsrd r6
+ blr
+
+#ifdef CONFIG_ALTIVEC
+/* Load vector reg N from *p. N is in r3, p in r4. */
+_GLOBAL(do_lvx)
+ mflr r0
+ mfmsr r6
+ oris r7,r6,MSR_VEC@h
+ rlwinm r3,r3,3,0xf8
+ bcl 20,31,2f
+1: inst32 lvx
+2: mflr r5
+ mtlr r0
+ add r8,r3,r5
+ mtctr r8
+ li r3,0
+ mtmsrd r7
+ isync
+ bctr
+3: mtmsrd r6
+ blr
+
+/* Store vector reg N to *p. N is in r3, p in r4. */
+_GLOBAL(do_stvx)
+ mflr r0
+ mfmsr r6
+ oris r7,r6,MSR_VEC@h
+ rlwinm r3,r3,3,0xf8
+ bcl 20,31,2f
+1: inst32 stvx
+2: mflr r5
+ mtlr r0
+ add r8,r3,r5
+ mtctr r8
+ li r3,0
+ mtmsrd r7
+ isync
+ bctr
+99: li r3,-EFAULT
+3: mtmsrd r6
+ blr
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef CONFIG_VSX
+
+ .macro inst64 opcode
+ reg = 0
+ .rept 64
+20: .long \opcode + ((reg & 0x1f) << 21) + ((reg >> 5) & 1) + (4 << 11)
+ b 3f
+ .section __ex_table,"a"
+ PPC_LONG 20b,99f
+ .previous
+ reg = reg + 1
+ .endr
+ .endm
+
+/* Load VSX reg N from vector doubleword *p. N is in r3, p in r4. */
+_GLOBAL(do_lxvd2x)
+ mflr r0
+ mfmsr r6
+ oris r7,r6,MSR_VSX@h
+ rlwinm r3,r3,3,0xf8
+ bcl 20,31,2f
+1: inst64 PPC_INST_LXVD2X
+2: mflr r5
+ mtlr r0
+ add r8,r3,r5
+ mtctr r8
+ li r3,0
+ mtmsrd r7
+ isync
+ bctr
+99: li r3,-EFAULT
+3: mtmsrd r6
+ blr
+
+/* Store VSX reg N to vector doubleword *p. N is in r3, p in r4. */
+_GLOBAL(do_stxvd2x)
+ mflr r0
+ mfmsr r6
+ oris r7,r6,MSR_VSX@h
+ rlwinm r3,r3,3,0xf8
+ bcl 20,31,2f
+1: inst64 PPC_INST_STXVD2X
+2: mflr r5
+ mtlr r0
+ add r8,r3,r5
+ mtctr r8
+ li r3,0
+ mtmsrd r7
+ isync
+ bctr
+99: li r3,-EFAULT
+3: mtmsrd r6
+ blr
+
+#endif /* CONFIG_VSX */
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 13b7d54..a8eaff4 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -13,6 +13,8 @@
#include <linux/ptrace.h>
#include <asm/sstep.h>
#include <asm/processor.h>
+#include <asm/uaccess.h>
+#include <asm/cputable.h>
extern char system_call_common[];
@@ -23,6 +25,23 @@ extern char system_call_common[];
#define MSR_MASK 0x87c0ffff
#endif
+/* Bits in XER */
+#define XER_SO 0x80000000U
+#define XER_OV 0x40000000U
+#define XER_CA 0x20000000U
+
+/*
+ * Functions in ldstfp.S
+ */
+extern int do_lfs(int rn, unsigned long ea);
+extern int do_lfd(int rn, unsigned long ea);
+extern int do_stfs(int rn, unsigned long ea);
+extern int do_stfd(int rn, unsigned long ea);
+extern int do_lvx(int rn, unsigned long ea);
+extern int do_stvx(int rn, unsigned long ea);
+extern int do_lxvd2x(int rn, unsigned long ea);
+extern int do_stxvd2x(int rn, unsigned long ea);
+
/*
* Determine whether a conditional branch instruction would branch.
*/
@@ -46,16 +65,499 @@ static int __kprobes branch_taken(unsigned int instr, struct pt_regs *regs)
return 1;
}
+
+static inline long address_ok(struct pt_regs *regs, unsigned long ea, int nb)
+{
+ if (!user_mode(regs))
+ return 1;
+ return __access_ok(ea, nb, USER_DS);
+}
+
+/*
+ * Calculate effective address for a D-form instruction
+ */
+static inline unsigned long dform_ea(unsigned int instr, struct pt_regs *regs)
+{
+ int ra;
+ unsigned long ea;
+
+ ra = (instr >> 16) & 0x1f;
+ ea = (signed short) instr; /* sign-extend */
+ if (ra) {
+ ea += regs->gpr[ra];
+ if (instr & 0x04000000) /* update forms */
+ regs->gpr[ra] = ea;
+ }
+#ifdef __powerpc64__
+ if (!(regs->msr & MSR_SF))
+ ea &= 0xffffffffUL;
+#endif
+ return ea;
+}
+
+/*
+ * Calculate effective address for a DS-form instruction
+ */
+static inline unsigned long dsform_ea(unsigned int instr, struct pt_regs *regs)
+{
+ int ra;
+ unsigned long ea;
+
+ ra = (instr >> 16) & 0x1f;
+ ea = (signed short) (instr & ~3); /* sign-extend */
+ if (ra) {
+ ea += regs->gpr[ra];
+ if ((instr & 3) == 1) /* update forms */
+ regs->gpr[ra] = ea;
+ }
+#ifdef __powerpc64__
+ if (!(regs->msr & MSR_SF))
+ ea &= 0xffffffffUL;
+#endif
+ return ea;
+}
+
+/*
+ * Calculate effective address for an X-form instruction
+ */
+static inline unsigned long xform_ea(unsigned int instr, struct pt_regs *regs,
+ int do_update)
+{
+ int ra, rb;
+ unsigned long ea;
+
+ ra = (instr >> 16) & 0x1f;
+ rb = (instr >> 11) & 0x1f;
+ ea = regs->gpr[rb];
+ if (ra) {
+ ea += regs->gpr[ra];
+ if (do_update) /* update forms */
+ regs->gpr[ra] = ea;
+ }
+#ifdef __powerpc64__
+ if (!(regs->msr & MSR_SF))
+ ea &= 0xffffffffUL;
+#endif
+ return ea;
+}
+
+/*
+ * Return the largest power of 2, not greater than sizeof(unsigned long),
+ * such that x is a multiple of it.
+ */
+static inline unsigned long max_align(unsigned long x)
+{
+ x |= sizeof(unsigned long);
+ return x & -x; /* isolates rightmost one bit */
+}
+
+
+static inline unsigned long byterev_2(unsigned long x)
+{
+ return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
+}
+
+static inline unsigned long byterev_4(unsigned long x)
+{
+ return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
+ ((x & 0xff00) << 8) | ((x & 0xff) << 24);
+}
+
+#ifdef __powerpc64__
+static inline unsigned long byterev_8(unsigned long x)
+{
+ return (byterev_4(x) << 32) | byterev_4(x >> 32);
+}
+#endif
+
+static inline int read_mem_aligned(unsigned long *dest, unsigned long ea,
+ int nb)
+{
+ int err = 0;
+ unsigned long x = 0;
+
+ switch (nb) {
+ case 1:
+ err = __get_user(x, (unsigned char __user *) ea);
+ break;
+ case 2:
+ err = __get_user(x, (unsigned short __user *) ea);
+ break;
+ case 4:
+ err = __get_user(x, (unsigned int __user *) ea);
+ break;
+#ifdef __powerpc64__
+ case 8:
+ err = __get_user(x, (unsigned long __user *) ea);
+ break;
+#endif
+ }
+ if (!err)
+ *dest = x;
+ return err;
+}
+
+static int __kprobes read_mem_unaligned(unsigned long *dest, unsigned long ea,
+ int nb, struct pt_regs *regs)
+{
+ int err;
+ unsigned long x, b, c;
+
+ /* unaligned, do this in pieces */
+ x = 0;
+ for (; nb > 0; nb -= c) {
+ c = max_align(ea);
+ if (c > nb)
+ c = max_align(nb);
+ err = read_mem_aligned(&b, ea, c);
+ if (err)
+ return err;
+ x = (x << (8 * c)) + b;
+ ea += c;
+ }
+ *dest = x;
+ return 0;
+}
+
+/*
+ * Read memory at address ea for nb bytes, return 0 for success
+ * or -EFAULT if an error occurred.
+ */
+static inline int read_mem(unsigned long *dest, unsigned long ea, int nb,
+ struct pt_regs *regs)
+{
+ if (!address_ok(regs, ea, nb))
+ return -EFAULT;
+ if ((ea & (nb - 1)) == 0)
+ return read_mem_aligned(dest, ea, nb);
+ return read_mem_unaligned(dest, ea, nb, regs);
+}
+
+static inline int write_mem_aligned(unsigned long val, unsigned long ea,
+ int nb)
+{
+ int err = 0;
+
+ switch (nb) {
+ case 1:
+ err = __put_user(val, (unsigned char __user *) ea);
+ break;
+ case 2:
+ err = __put_user(val, (unsigned short __user *) ea);
+ break;
+ case 4:
+ err = __put_user(val, (unsigned int __user *) ea);
+ break;
+#ifdef __powerpc64__
+ case 8:
+ err = __put_user(val, (unsigned long __user *) ea);
+ break;
+#endif
+ }
+ return err;
+}
+
+static int __kprobes write_mem_unaligned(unsigned long val, unsigned long ea,
+ int nb, struct pt_regs *regs)
+{
+ int err;
+ unsigned long c;
+
+ /* unaligned or little-endian, do this in pieces */
+ for (; nb > 0; nb -= c) {
+ c = max_align(ea);
+ if (c > nb)
+ c = max_align(nb);
+ err = write_mem_aligned(val >> (nb - c) * 8, ea, c);
+ if (err)
+ return err;
+ ++ea;
+ }
+ return 0;
+}
+
+/*
+ * Write memory at address ea for nb bytes, return 0 for success
+ * or -EFAULT if an error occurred.
+ */
+static inline int write_mem(unsigned long val, unsigned long ea, int nb,
+ struct pt_regs *regs)
+{
+ if (!address_ok(regs, ea, nb))
+ return -EFAULT;
+ if ((ea & (nb - 1)) == 0)
+ return write_mem_aligned(val, ea, nb);
+ return write_mem_unaligned(val, ea, nb, regs);
+}
+
+/*
+ * Check the address and alignment, and call func to do the actual
+ * load or store.
+ */
+static int __kprobes do_fp_load(int rn, int (*func)(int, unsigned long),
+ unsigned long ea, int nb,
+ struct pt_regs *regs)
+{
+ int err;
+ unsigned long val[sizeof(double) / sizeof(long)];
+ unsigned long ptr;
+
+ if (!address_ok(regs, ea, nb))
+ return -EFAULT;
+ if ((ea & 3) == 0)
+ return (*func)(rn, ea);
+ ptr = (unsigned long) &val[0];
+ if (sizeof(unsigned long) == 8 || nb == 4) {
+ err = read_mem_unaligned(&val[0], ea, nb, regs);
+ ptr += sizeof(unsigned long) - nb;
+ } else {
+ /* reading a double on 32-bit */
+ err = read_mem_unaligned(&val[0], ea, 4, regs);
+ if (!err)
+ err = read_mem_unaligned(&val[1], ea + 4, 4, regs);
+ }
+ if (err)
+ return err;
+ return (*func)(rn, ptr);
+}
+
+static int __kprobes do_fp_store(int rn, int (*func)(int, unsigned long),
+ unsigned long ea, int nb,
+ struct pt_regs *regs)
+{
+ int err;
+ unsigned long val[sizeof(double) / sizeof(long)];
+ unsigned long ptr;
+
+ if (!address_ok(regs, ea, nb))
+ return -EFAULT;
+ if ((ea & 3) == 0)
+ return (*func)(rn, ea);
+ ptr = (unsigned long) &val[0];
+ if (sizeof(unsigned long) == 8 || nb == 4) {
+ ptr += sizeof(unsigned long) - nb;
+ err = (*func)(rn, ptr);
+ if (err)
+ return err;
+ err = write_mem_unaligned(val[0], ea, nb, regs);
+ } else {
+ /* writing a double on 32-bit */
+ err = (*func)(rn, ptr);
+ if (err)
+ return err;
+ err = write_mem_unaligned(val[0], ea, 4, regs);
+ if (!err)
+ err = write_mem_unaligned(val[1], ea + 4, 4, regs);
+ }
+ return err;
+}
+
+#ifdef CONFIG_ALTIVEC
+/* For Altivec/VMX, no need to worry about alignment */
+static inline int do_vec_load(int rn, int (*func)(int, unsigned long),
+ unsigned long ea, struct pt_regs *regs)
+{
+ if (!address_ok(regs, ea & ~0xfUL, 16))
+ return -EFAULT;
+ return (*func)(rn, ea);
+}
+
+static inline int do_vec_store(int rn, int (*func)(int, unsigned long),
+ unsigned long ea, struct pt_regs *regs)
+{
+ if (!address_ok(regs, ea & ~0xfUL, 16))
+ return -EFAULT;
+ return (*func)(rn, ea);
+}
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef CONFIG_VSX
+static int __kprobes do_vsx_load(int rn, int (*func)(int, unsigned long),
+ unsigned long ea, struct pt_regs *regs)
+{
+ int err;
+ unsigned long val[2];
+
+ if (!address_ok(regs, ea, 16))
+ return -EFAULT;
+ if ((ea & 3) == 0)
+ return (*func)(rn, ea);
+ err = read_mem_unaligned(&val[0], ea, 8, regs);
+ if (!err)
+ err = read_mem_unaligned(&val[1], ea + 8, 8, regs);
+ if (!err)
+ err = (*func)(rn, (unsigned long) &val[0]);
+ return err;
+}
+
+static int __kprobes do_vsx_store(int rn, int (*func)(int, unsigned long),
+ unsigned long ea, struct pt_regs *regs)
+{
+ int err;
+ unsigned long val[2];
+
+ if (!address_ok(regs, ea, 16))
+ return -EFAULT;
+ if ((ea & 3) == 0)
+ return (*func)(rn, ea);
+ err = (*func)(rn, (unsigned long) &val[0]);
+ if (err)
+ return err;
+ err = write_mem_unaligned(val[0], ea, 8, regs);
+ if (!err)
+ err = write_mem_unaligned(val[1], ea + 8, 8, regs);
+ return err;
+}
+#endif /* CONFIG_VSX */
+
+#define __put_user_asmx(x, addr, err, op, cr) \
+ __asm__ __volatile__( \
+ "1: " op " %2,0,%3\n" \
+ " mfcr %1\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: li %0,%4\n" \
+ " b 2b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ PPC_LONG_ALIGN "\n" \
+ PPC_LONG "1b,3b\n" \
+ ".previous" \
+ : "=r" (err), "=r" (cr) \
+ : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
+
+#define __get_user_asmx(x, addr, err, op) \
+ __asm__ __volatile__( \
+ "1: "op" %1,0,%2\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: li %0,%3\n" \
+ " b 2b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ PPC_LONG_ALIGN "\n" \
+ PPC_LONG "1b,3b\n" \
+ ".previous" \
+ : "=r" (err), "=r" (x) \
+ : "r" (addr), "i" (-EFAULT), "0" (err))
+
+#define __cacheop_user_asmx(addr, err, op) \
+ __asm__ __volatile__( \
+ "1: "op" 0,%1\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: li %0,%3\n" \
+ " b 2b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ PPC_LONG_ALIGN "\n" \
+ PPC_LONG "1b,3b\n" \
+ ".previous" \
+ : "=r" (err) \
+ : "r" (addr), "i" (-EFAULT), "0" (err))
+
+static void __kprobes set_cr0(struct pt_regs *regs, int rd)
+{
+ long val = regs->gpr[rd];
+
+ regs->ccr = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
+#ifdef __powerpc64__
+ if (!(regs->msr & MSR_SF))
+ val = (int) val;
+#endif
+ if (val < 0)
+ regs->ccr |= 0x80000000;
+ else if (val > 0)
+ regs->ccr |= 0x40000000;
+ else
+ regs->ccr |= 0x20000000;
+}
+
+static void __kprobes add_with_carry(struct pt_regs *regs, int rd,
+ unsigned long val1, unsigned long val2,
+ unsigned long carry_in)
+{
+ unsigned long val = val1 + val2;
+
+ if (carry_in)
+ ++val;
+ regs->gpr[rd] = val;
+#ifdef __powerpc64__
+ if (!(regs->msr & MSR_SF)) {
+ val = (unsigned int) val;
+ val1 = (unsigned int) val1;
+ }
+#endif
+ if (val < val1 || (carry_in && val == val1))
+ regs->xer |= XER_CA;
+ else
+ regs->xer &= ~XER_CA;
+}
+
+static void __kprobes do_cmp_signed(struct pt_regs *regs, long v1, long v2,
+ int crfld)
+{
+ unsigned int crval, shift;
+
+ crval = (regs->xer >> 31) & 1; /* get SO bit */
+ if (v1 < v2)
+ crval |= 8;
+ else if (v1 > v2)
+ crval |= 4;
+ else
+ crval |= 2;
+ shift = (7 - crfld) * 4;
+ regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
+}
+
+static void __kprobes do_cmp_unsigned(struct pt_regs *regs, unsigned long v1,
+ unsigned long v2, int crfld)
+{
+ unsigned int crval, shift;
+
+ crval = (regs->xer >> 31) & 1; /* get SO bit */
+ if (v1 < v2)
+ crval |= 8;
+ else if (v1 > v2)
+ crval |= 4;
+ else
+ crval |= 2;
+ shift = (7 - crfld) * 4;
+ regs->ccr = (regs->ccr & ~(0xf << shift)) | (crval << shift);
+}
+
/*
- * Emulate instructions that cause a transfer of control.
+ * Elements of 32-bit rotate and mask instructions.
+ */
+#define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
+ ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
+#ifdef __powerpc64__
+#define MASK64_L(mb) (~0UL >> (mb))
+#define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
+#define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
+#define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
+#else
+#define DATA32(x) (x)
+#endif
+#define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
+
+/*
+ * Emulate instructions that cause a transfer of control,
+ * loads and stores, and a few other instructions.
* Returns 1 if the step was emulated, 0 if not,
* or -1 if the instruction is one that should not be stepped,
* such as an rfid, or a mtmsrd that would clear MSR_RI.
*/
int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
{
- unsigned int opcode, rs, rb, rd, spr;
+ unsigned int opcode, ra, rb, rd, spr, u;
unsigned long int imm;
+ unsigned long int val, val2;
+ unsigned long int ea;
+ unsigned int cr, mb, me, sh;
+ int err;
+ unsigned long old_ra;
+ long ival;
opcode = instr >> 26;
switch (opcode) {
@@ -78,7 +580,13 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
* entry code works. If that is changed, this will
* need to be changed also.
*/
+ if (regs->gpr[0] == 0x1ebe &&
+ cpu_has_feature(CPU_FTR_REAL_LE)) {
+ regs->msr ^= MSR_LE;
+ goto instr_done;
+ }
regs->gpr[9] = regs->gpr[13];
+ regs->gpr[10] = MSR_KERNEL;
regs->gpr[11] = regs->nip + 4;
regs->gpr[12] = regs->msr & MSR_MASK;
regs->gpr[13] = (unsigned long) get_paca();
@@ -102,9 +610,9 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
regs->nip = imm;
return 1;
case 19:
- switch (instr & 0x7fe) {
- case 0x20: /* bclr */
- case 0x420: /* bcctr */
+ switch ((instr >> 1) & 0x3ff) {
+ case 16: /* bclr */
+ case 528: /* bcctr */
imm = (instr & 0x400)? regs->ctr: regs->link;
regs->nip += 4;
if ((regs->msr & MSR_SF) == 0) {
@@ -116,30 +624,233 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
if (branch_taken(instr, regs))
regs->nip = imm;
return 1;
- case 0x24: /* rfid, scary */
+
+ case 18: /* rfid, scary */
return -1;
+
+ case 150: /* isync */
+ isync();
+ goto instr_done;
+
+ case 33: /* crnor */
+ case 129: /* crandc */
+ case 193: /* crxor */
+ case 225: /* crnand */
+ case 257: /* crand */
+ case 289: /* creqv */
+ case 417: /* crorc */
+ case 449: /* cror */
+ ra = (instr >> 16) & 0x1f;
+ rb = (instr >> 11) & 0x1f;
+ rd = (instr >> 21) & 0x1f;
+ ra = (regs->ccr >> (31 - ra)) & 1;
+ rb = (regs->ccr >> (31 - rb)) & 1;
+ val = (instr >> (6 + ra * 2 + rb)) & 1;
+ regs->ccr = (regs->ccr & ~(1UL << (31 - rd))) |
+ (val << (31 - rd));
+ goto instr_done;
}
+ break;
case 31:
- rd = (instr >> 21) & 0x1f;
- switch (instr & 0x7fe) {
- case 0xa6: /* mfmsr */
+ switch ((instr >> 1) & 0x3ff) {
+ case 598: /* sync */
+#ifdef __powerpc64__
+ switch ((instr >> 21) & 3) {
+ case 1: /* lwsync */
+ asm volatile("lwsync" : : : "memory");
+ goto instr_done;
+ case 2: /* ptesync */
+ asm volatile("ptesync" : : : "memory");
+ goto instr_done;
+ }
+#endif
+ mb();
+ goto instr_done;
+
+ case 854: /* eieio */
+ eieio();
+ goto instr_done;
+ }
+ break;
+ }
+
+ /* Following cases refer to regs->gpr[], so we need all regs */
+ if (!FULL_REGS(regs))
+ return 0;
+
+ rd = (instr >> 21) & 0x1f;
+ ra = (instr >> 16) & 0x1f;
+ rb = (instr >> 11) & 0x1f;
+
+ switch (opcode) {
+ case 7: /* mulli */
+ regs->gpr[rd] = regs->gpr[ra] * (short) instr;
+ goto instr_done;
+
+ case 8: /* subfic */
+ imm = (short) instr;
+ add_with_carry(regs, rd, ~regs->gpr[ra], imm, 1);
+ goto instr_done;
+
+ case 10: /* cmpli */
+ imm = (unsigned short) instr;
+ val = regs->gpr[ra];
+#ifdef __powerpc64__
+ if ((rd & 1) == 0)
+ val = (unsigned int) val;
+#endif
+ do_cmp_unsigned(regs, val, imm, rd >> 2);
+ goto instr_done;
+
+ case 11: /* cmpi */
+ imm = (short) instr;
+ val = regs->gpr[ra];
+#ifdef __powerpc64__
+ if ((rd & 1) == 0)
+ val = (int) val;
+#endif
+ do_cmp_signed(regs, val, imm, rd >> 2);
+ goto instr_done;
+
+ case 12: /* addic */
+ imm = (short) instr;
+ add_with_carry(regs, rd, regs->gpr[ra], imm, 0);
+ goto instr_done;
+
+ case 13: /* addic. */
+ imm = (short) instr;
+ add_with_carry(regs, rd, regs->gpr[ra], imm, 0);
+ set_cr0(regs, rd);
+ goto instr_done;
+
+ case 14: /* addi */
+ imm = (short) instr;
+ if (ra)
+ imm += regs->gpr[ra];
+ regs->gpr[rd] = imm;
+ goto instr_done;
+
+ case 15: /* addis */
+ imm = ((short) instr) << 16;
+ if (ra)
+ imm += regs->gpr[ra];
+ regs->gpr[rd] = imm;
+ goto instr_done;
+
+ case 20: /* rlwimi */
+ mb = (instr >> 6) & 0x1f;
+ me = (instr >> 1) & 0x1f;
+ val = DATA32(regs->gpr[rd]);
+ imm = MASK32(mb, me);
+ regs->gpr[ra] = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
+ goto logical_done;
+
+ case 21: /* rlwinm */
+ mb = (instr >> 6) & 0x1f;
+ me = (instr >> 1) & 0x1f;
+ val = DATA32(regs->gpr[rd]);
+ regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me);
+ goto logical_done;
+
+ case 23: /* rlwnm */
+ mb = (instr >> 6) & 0x1f;
+ me = (instr >> 1) & 0x1f;
+ rb = regs->gpr[rb] & 0x1f;
+ val = DATA32(regs->gpr[rd]);
+ regs->gpr[ra] = ROTATE(val, rb) & MASK32(mb, me);
+ goto logical_done;
+
+ case 24: /* ori */
+ imm = (unsigned short) instr;
+ regs->gpr[ra] = regs->gpr[rd] | imm;
+ goto instr_done;
+
+ case 25: /* oris */
+ imm = (unsigned short) instr;
+ regs->gpr[ra] = regs->gpr[rd] | (imm << 16);
+ goto instr_done;
+
+ case 26: /* xori */
+ imm = (unsigned short) instr;
+ regs->gpr[ra] = regs->gpr[rd] ^ imm;
+ goto instr_done;
+
+ case 27: /* xoris */
+ imm = (unsigned short) instr;
+ regs->gpr[ra] = regs->gpr[rd] ^ (imm << 16);
+ goto instr_done;
+
+ case 28: /* andi. */
+ imm = (unsigned short) instr;
+ regs->gpr[ra] = regs->gpr[rd] & imm;
+ set_cr0(regs, ra);
+ goto instr_done;
+
+ case 29: /* andis. */
+ imm = (unsigned short) instr;
+ regs->gpr[ra] = regs->gpr[rd] & (imm << 16);
+ set_cr0(regs, ra);
+ goto instr_done;
+
+#ifdef __powerpc64__
+ case 30: /* rld* */
+ mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
+ val = regs->gpr[rd];
+ if ((instr & 0x10) == 0) {
+ sh = rb | ((instr & 2) << 4);
+ val = ROTATE(val, sh);
+ switch ((instr >> 2) & 3) {
+ case 0: /* rldicl */
+ regs->gpr[ra] = val & MASK64_L(mb);
+ goto logical_done;
+ case 1: /* rldicr */
+ regs->gpr[ra] = val & MASK64_R(mb);
+ goto logical_done;
+ case 2: /* rldic */
+ regs->gpr[ra] = val & MASK64(mb, 63 - sh);
+ goto logical_done;
+ case 3: /* rldimi */
+ imm = MASK64(mb, 63 - sh);
+ regs->gpr[ra] = (regs->gpr[ra] & ~imm) |
+ (val & imm);
+ goto logical_done;
+ }
+ } else {
+ sh = regs->gpr[rb] & 0x3f;
+ val = ROTATE(val, sh);
+ switch ((instr >> 1) & 7) {
+ case 0: /* rldcl */
+ regs->gpr[ra] = val & MASK64_L(mb);
+ goto logical_done;
+ case 1: /* rldcr */
+ regs->gpr[ra] = val & MASK64_R(mb);
+ goto logical_done;
+ }
+ }
+#endif
+
+ case 31:
+ switch ((instr >> 1) & 0x3ff) {
+ case 83: /* mfmsr */
+ if (regs->msr & MSR_PR)
+ break;
regs->gpr[rd] = regs->msr & MSR_MASK;
- regs->nip += 4;
- if ((regs->msr & MSR_SF) == 0)
- regs->nip &= 0xffffffffUL;
- return 1;
- case 0x124: /* mtmsr */
+ goto instr_done;
+ case 146: /* mtmsr */
+ if (regs->msr & MSR_PR)
+ break;
imm = regs->gpr[rd];
if ((imm & MSR_RI) == 0)
/* can't step mtmsr that would clear MSR_RI */
return -1;
regs->msr = imm;
- regs->nip += 4;
- return 1;
+ goto instr_done;
#ifdef CONFIG_PPC64
- case 0x164: /* mtmsrd */
+ case 178: /* mtmsrd */
/* only MSR_EE and MSR_RI get changed if bit 15 set */
/* mtmsrd doesn't change MSR_HV and MSR_ME */
+ if (regs->msr & MSR_PR)
+ break;
imm = (instr & 0x10000)? 0x8002: 0xefffffffffffefffUL;
imm = (regs->msr & MSR_MASK & ~imm)
| (regs->gpr[rd] & imm);
@@ -147,57 +858,769 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
/* can't step mtmsrd that would clear MSR_RI */
return -1;
regs->msr = imm;
- regs->nip += 4;
- if ((imm & MSR_SF) == 0)
- regs->nip &= 0xffffffffUL;
- return 1;
+ goto instr_done;
#endif
- case 0x26: /* mfcr */
+ case 19: /* mfcr */
regs->gpr[rd] = regs->ccr;
regs->gpr[rd] &= 0xffffffffUL;
- goto mtspr_out;
- case 0x2a6: /* mfspr */
+ goto instr_done;
+
+ case 144: /* mtcrf */
+ imm = 0xf0000000UL;
+ val = regs->gpr[rd];
+ for (sh = 0; sh < 8; ++sh) {
+ if (instr & (0x80000 >> sh))
+ regs->ccr = (regs->ccr & ~imm) |
+ (val & imm);
+ imm >>= 4;
+ }
+ goto instr_done;
+
+ case 339: /* mfspr */
spr = (instr >> 11) & 0x3ff;
switch (spr) {
case 0x20: /* mfxer */
regs->gpr[rd] = regs->xer;
regs->gpr[rd] &= 0xffffffffUL;
- goto mtspr_out;
+ goto instr_done;
case 0x100: /* mflr */
regs->gpr[rd] = regs->link;
- goto mtspr_out;
+ goto instr_done;
case 0x120: /* mfctr */
regs->gpr[rd] = regs->ctr;
- goto mtspr_out;
- }
- break;
- case 0x378: /* orx */
- if (instr & 1)
- break;
- rs = (instr >> 21) & 0x1f;
- rb = (instr >> 11) & 0x1f;
- if (rs == rb) { /* mr */
- rd = (instr >> 16) & 0x1f;
- regs->gpr[rd] = regs->gpr[rs];
- goto mtspr_out;
+ goto instr_done;
}
break;
- case 0x3a6: /* mtspr */
+
+ case 467: /* mtspr */
spr = (instr >> 11) & 0x3ff;
switch (spr) {
case 0x20: /* mtxer */
regs->xer = (regs->gpr[rd] & 0xffffffffUL);
- goto mtspr_out;
+ goto instr_done;
case 0x100: /* mtlr */
regs->link = regs->gpr[rd];
- goto mtspr_out;
+ goto instr_done;
case 0x120: /* mtctr */
regs->ctr = regs->gpr[rd];
-mtspr_out:
- regs->nip += 4;
- return 1;
+ goto instr_done;
}
+ break;
+
+/*
+ * Compare instructions
+ */
+ case 0: /* cmp */
+ val = regs->gpr[ra];
+ val2 = regs->gpr[rb];
+#ifdef __powerpc64__
+ if ((rd & 1) == 0) {
+ /* word (32-bit) compare */
+ val = (int) val;
+ val2 = (int) val2;
+ }
+#endif
+ do_cmp_signed(regs, val, val2, rd >> 2);
+ goto instr_done;
+
+ case 32: /* cmpl */
+ val = regs->gpr[ra];
+ val2 = regs->gpr[rb];
+#ifdef __powerpc64__
+ if ((rd & 1) == 0) {
+ /* word (32-bit) compare */
+ val = (unsigned int) val;
+ val2 = (unsigned int) val2;
+ }
+#endif
+ do_cmp_unsigned(regs, val, val2, rd >> 2);
+ goto instr_done;
+
+/*
+ * Arithmetic instructions
+ */
+ case 8: /* subfc */
+ add_with_carry(regs, rd, ~regs->gpr[ra],
+ regs->gpr[rb], 1);
+ goto arith_done;
+#ifdef __powerpc64__
+ case 9: /* mulhdu */
+ asm("mulhdu %0,%1,%2" : "=r" (regs->gpr[rd]) :
+ "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+ goto arith_done;
+#endif
+ case 10: /* addc */
+ add_with_carry(regs, rd, regs->gpr[ra],
+ regs->gpr[rb], 0);
+ goto arith_done;
+
+ case 11: /* mulhwu */
+ asm("mulhwu %0,%1,%2" : "=r" (regs->gpr[rd]) :
+ "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+ goto arith_done;
+
+ case 40: /* subf */
+ regs->gpr[rd] = regs->gpr[rb] - regs->gpr[ra];
+ goto arith_done;
+#ifdef __powerpc64__
+ case 73: /* mulhd */
+ asm("mulhd %0,%1,%2" : "=r" (regs->gpr[rd]) :
+ "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+ goto arith_done;
+#endif
+ case 75: /* mulhw */
+ asm("mulhw %0,%1,%2" : "=r" (regs->gpr[rd]) :
+ "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
+ goto arith_done;
+
+ case 104: /* neg */
+ regs->gpr[rd] = -regs->gpr[ra];
+ goto arith_done;
+
+ case 136: /* subfe */
+ add_with_carry(regs, rd, ~regs->gpr[ra], regs->gpr[rb],
+ regs->xer & XER_CA);
+ goto arith_done;
+
+ case 138: /* adde */
+ add_with_carry(regs, rd, regs->gpr[ra], regs->gpr[rb],
+ regs->xer & XER_CA);
+ goto arith_done;
+
+ case 200: /* subfze */
+ add_with_carry(regs, rd, ~regs->gpr[ra], 0L,
+ regs->xer & XER_CA);
+ goto arith_done;
+
+ case 202: /* addze */
+ add_with_carry(regs, rd, regs->gpr[ra], 0L,
+ regs->xer & XER_CA);
+ goto arith_done;
+
+ case 232: /* subfme */
+ add_with_carry(regs, rd, ~regs->gpr[ra], -1L,
+ regs->xer & XER_CA);
+ goto arith_done;
+#ifdef __powerpc64__
+ case 233: /* mulld */
+ regs->gpr[rd] = regs->gpr[ra] * regs->gpr[rb];
+ goto arith_done;
+#endif
+ case 234: /* addme */
+ add_with_carry(regs, rd, regs->gpr[ra], -1L,
+ regs->xer & XER_CA);
+ goto arith_done;
+
+ case 235: /* mullw */
+ regs->gpr[rd] = (unsigned int) regs->gpr[ra] *
+ (unsigned int) regs->gpr[rb];
+ goto arith_done;
+
+ case 266: /* add */
+ regs->gpr[rd] = regs->gpr[ra] + regs->gpr[rb];
+ goto arith_done;
+#ifdef __powerpc64__
+ case 457: /* divdu */
+ regs->gpr[rd] = regs->gpr[ra] / regs->gpr[rb];
+ goto arith_done;
+#endif
+ case 459: /* divwu */
+ regs->gpr[rd] = (unsigned int) regs->gpr[ra] /
+ (unsigned int) regs->gpr[rb];
+ goto arith_done;
+#ifdef __powerpc64__
+ case 489: /* divd */
+ regs->gpr[rd] = (long int) regs->gpr[ra] /
+ (long int) regs->gpr[rb];
+ goto arith_done;
+#endif
+ case 491: /* divw */
+ regs->gpr[rd] = (int) regs->gpr[ra] /
+ (int) regs->gpr[rb];
+ goto arith_done;
+
+
+/*
+ * Logical instructions
+ */
+ case 26: /* cntlzw */
+ asm("cntlzw %0,%1" : "=r" (regs->gpr[ra]) :
+ "r" (regs->gpr[rd]));
+ goto logical_done;
+#ifdef __powerpc64__
+ case 58: /* cntlzd */
+ asm("cntlzd %0,%1" : "=r" (regs->gpr[ra]) :
+ "r" (regs->gpr[rd]));
+ goto logical_done;
+#endif
+ case 28: /* and */
+ regs->gpr[ra] = regs->gpr[rd] & regs->gpr[rb];
+ goto logical_done;
+
+ case 60: /* andc */
+ regs->gpr[ra] = regs->gpr[rd] & ~regs->gpr[rb];
+ goto logical_done;
+
+ case 124: /* nor */
+ regs->gpr[ra] = ~(regs->gpr[rd] | regs->gpr[rb]);
+ goto logical_done;
+
+ case 284: /* xor */
+ regs->gpr[ra] = ~(regs->gpr[rd] ^ regs->gpr[rb]);
+ goto logical_done;
+
+ case 316: /* xor */
+ regs->gpr[ra] = regs->gpr[rd] ^ regs->gpr[rb];
+ goto logical_done;
+
+ case 412: /* orc */
+ regs->gpr[ra] = regs->gpr[rd] | ~regs->gpr[rb];
+ goto logical_done;
+
+ case 444: /* or */
+ regs->gpr[ra] = regs->gpr[rd] | regs->gpr[rb];
+ goto logical_done;
+
+ case 476: /* nand */
+ regs->gpr[ra] = ~(regs->gpr[rd] & regs->gpr[rb]);
+ goto logical_done;
+
+ case 922: /* extsh */
+ regs->gpr[ra] = (signed short) regs->gpr[rd];
+ goto logical_done;
+
+ case 954: /* extsb */
+ regs->gpr[ra] = (signed char) regs->gpr[rd];
+ goto logical_done;
+#ifdef __powerpc64__
+ case 986: /* extsw */
+ regs->gpr[ra] = (signed int) regs->gpr[rd];
+ goto logical_done;
+#endif
+
+/*
+ * Shift instructions
+ */
+ case 24: /* slw */
+ sh = regs->gpr[rb] & 0x3f;
+ if (sh < 32)
+ regs->gpr[ra] = (regs->gpr[rd] << sh) & 0xffffffffUL;
+ else
+ regs->gpr[ra] = 0;
+ goto logical_done;
+
+ case 536: /* srw */
+ sh = regs->gpr[rb] & 0x3f;
+ if (sh < 32)
+ regs->gpr[ra] = (regs->gpr[rd] & 0xffffffffUL) >> sh;
+ else
+ regs->gpr[ra] = 0;
+ goto logical_done;
+
+ case 792: /* sraw */
+ sh = regs->gpr[rb] & 0x3f;
+ ival = (signed int) regs->gpr[rd];
+ regs->gpr[ra] = ival >> (sh < 32 ? sh : 31);
+ if (ival < 0 && (sh >= 32 || (ival & ((1 << sh) - 1)) != 0))
+ regs->xer |= XER_CA;
+ else
+ regs->xer &= ~XER_CA;
+ goto logical_done;
+
+ case 824: /* srawi */
+ sh = rb;
+ ival = (signed int) regs->gpr[rd];
+ regs->gpr[ra] = ival >> sh;
+ if (ival < 0 && (ival & ((1 << sh) - 1)) != 0)
+ regs->xer |= XER_CA;
+ else
+ regs->xer &= ~XER_CA;
+ goto logical_done;
+
+#ifdef __powerpc64__
+ case 27: /* sld */
+ sh = regs->gpr[rd] & 0x7f;
+ if (sh < 64)
+ regs->gpr[ra] = regs->gpr[rd] << sh;
+ else
+ regs->gpr[ra] = 0;
+ goto logical_done;
+
+ case 539: /* srd */
+ sh = regs->gpr[rb] & 0x7f;
+ if (sh < 64)
+ regs->gpr[ra] = regs->gpr[rd] >> sh;
+ else
+ regs->gpr[ra] = 0;
+ goto logical_done;
+
+ case 794: /* srad */
+ sh = regs->gpr[rb] & 0x7f;
+ ival = (signed long int) regs->gpr[rd];
+ regs->gpr[ra] = ival >> (sh < 64 ? sh : 63);
+ if (ival < 0 && (sh >= 64 || (ival & ((1 << sh) - 1)) != 0))
+ regs->xer |= XER_CA;
+ else
+ regs->xer &= ~XER_CA;
+ goto logical_done;
+
+ case 826: /* sradi with sh_5 = 0 */
+ case 827: /* sradi with sh_5 = 1 */
+ sh = rb | ((instr & 2) << 4);
+ ival = (signed long int) regs->gpr[rd];
+ regs->gpr[ra] = ival >> sh;
+ if (ival < 0 && (ival & ((1 << sh) - 1)) != 0)
+ regs->xer |= XER_CA;
+ else
+ regs->xer &= ~XER_CA;
+ goto logical_done;
+#endif /* __powerpc64__ */
+
+/*
+ * Cache instructions
+ */
+ case 54: /* dcbst */
+ ea = xform_ea(instr, regs, 0);
+ if (!address_ok(regs, ea, 8))
+ return 0;
+ err = 0;
+ __cacheop_user_asmx(ea, err, "dcbst");
+ if (err)
+ return 0;
+ goto instr_done;
+
+ case 86: /* dcbf */
+ ea = xform_ea(instr, regs, 0);
+ if (!address_ok(regs, ea, 8))
+ return 0;
+ err = 0;
+ __cacheop_user_asmx(ea, err, "dcbf");
+ if (err)
+ return 0;
+ goto instr_done;
+
+ case 246: /* dcbtst */
+ if (rd == 0) {
+ ea = xform_ea(instr, regs, 0);
+ prefetchw((void *) ea);
+ }
+ goto instr_done;
+
+ case 278: /* dcbt */
+ if (rd == 0) {
+ ea = xform_ea(instr, regs, 0);
+ prefetch((void *) ea);
+ }
+ goto instr_done;
+
}
+ break;
}
- return 0;
+
+ /*
+ * Following cases are for loads and stores, so bail out
+ * if we're in little-endian mode.
+ */
+ if (regs->msr & MSR_LE)
+ return 0;
+
+ /*
+ * Save register RA in case it's an update form load or store
+ * and the access faults.
+ */
+ old_ra = regs->gpr[ra];
+
+ switch (opcode) {
+ case 31:
+ u = instr & 0x40;
+ switch ((instr >> 1) & 0x3ff) {
+ case 20: /* lwarx */
+ ea = xform_ea(instr, regs, 0);
+ if (ea & 3)
+ break; /* can't handle misaligned */
+ err = -EFAULT;
+ if (!address_ok(regs, ea, 4))
+ goto ldst_done;
+ err = 0;
+ __get_user_asmx(val, ea, err, "lwarx");
+ if (!err)
+ regs->gpr[rd] = val;
+ goto ldst_done;
+
+ case 150: /* stwcx. */
+ ea = xform_ea(instr, regs, 0);
+ if (ea & 3)
+ break; /* can't handle misaligned */
+ err = -EFAULT;
+ if (!address_ok(regs, ea, 4))
+ goto ldst_done;
+ err = 0;
+ __put_user_asmx(regs->gpr[rd], ea, err, "stwcx.", cr);
+ if (!err)
+ regs->ccr = (regs->ccr & 0x0fffffff) |
+ (cr & 0xe0000000) |
+ ((regs->xer >> 3) & 0x10000000);
+ goto ldst_done;
+
+#ifdef __powerpc64__
+ case 84: /* ldarx */
+ ea = xform_ea(instr, regs, 0);
+ if (ea & 7)
+ break; /* can't handle misaligned */
+ err = -EFAULT;
+ if (!address_ok(regs, ea, 8))
+ goto ldst_done;
+ err = 0;
+ __get_user_asmx(val, ea, err, "ldarx");
+ if (!err)
+ regs->gpr[rd] = val;
+ goto ldst_done;
+
+ case 214: /* stdcx. */
+ ea = xform_ea(instr, regs, 0);
+ if (ea & 7)
+ break; /* can't handle misaligned */
+ err = -EFAULT;
+ if (!address_ok(regs, ea, 8))
+ goto ldst_done;
+ err = 0;
+ __put_user_asmx(regs->gpr[rd], ea, err, "stdcx.", cr);
+ if (!err)
+ regs->ccr = (regs->ccr & 0x0fffffff) |
+ (cr & 0xe0000000) |
+ ((regs->xer >> 3) & 0x10000000);
+ goto ldst_done;
+
+ case 21: /* ldx */
+ case 53: /* ldux */
+ err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
+ 8, regs);
+ goto ldst_done;
+#endif
+
+ case 23: /* lwzx */
+ case 55: /* lwzux */
+ err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
+ 4, regs);
+ goto ldst_done;
+
+ case 87: /* lbzx */
+ case 119: /* lbzux */
+ err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
+ 1, regs);
+ goto ldst_done;
+
+#ifdef CONFIG_ALTIVEC
+ case 103: /* lvx */
+ case 359: /* lvxl */
+ if (!(regs->msr & MSR_VEC))
+ break;
+ ea = xform_ea(instr, regs, 0);
+ err = do_vec_load(rd, do_lvx, ea, regs);
+ goto ldst_done;
+
+ case 231: /* stvx */
+ case 487: /* stvxl */
+ if (!(regs->msr & MSR_VEC))
+ break;
+ ea = xform_ea(instr, regs, 0);
+ err = do_vec_store(rd, do_stvx, ea, regs);
+ goto ldst_done;
+#endif /* CONFIG_ALTIVEC */
+
+#ifdef __powerpc64__
+ case 149: /* stdx */
+ case 181: /* stdux */
+ val = regs->gpr[rd];
+ err = write_mem(val, xform_ea(instr, regs, u), 8, regs);
+ goto ldst_done;
+#endif
+
+ case 151: /* stwx */
+ case 183: /* stwux */
+ val = regs->gpr[rd];
+ err = write_mem(val, xform_ea(instr, regs, u), 4, regs);
+ goto ldst_done;
+
+ case 215: /* stbx */
+ case 247: /* stbux */
+ val = regs->gpr[rd];
+ err = write_mem(val, xform_ea(instr, regs, u), 1, regs);
+ goto ldst_done;
+
+ case 279: /* lhzx */
+ case 311: /* lhzux */
+ err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
+ 2, regs);
+ goto ldst_done;
+
+#ifdef __powerpc64__
+ case 341: /* lwax */
+ case 373: /* lwaux */
+ err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
+ 4, regs);
+ if (!err)
+ regs->gpr[rd] = (signed int) regs->gpr[rd];
+ goto ldst_done;
+#endif
+
+ case 343: /* lhax */
+ case 375: /* lhaux */
+ err = read_mem(®s->gpr[rd], xform_ea(instr, regs, u),
+ 2, regs);
+ if (!err)
+ regs->gpr[rd] = (signed short) regs->gpr[rd];
+ goto ldst_done;
+
+ case 407: /* sthx */
+ case 439: /* sthux */
+ val = regs->gpr[rd];
+ err = write_mem(val, xform_ea(instr, regs, u), 2, regs);
+ goto ldst_done;
+
+#ifdef __powerpc64__
+ case 532: /* ldbrx */
+ err = read_mem(&val, xform_ea(instr, regs, 0), 8, regs);
+ if (!err)
+ regs->gpr[rd] = byterev_8(val);
+ goto ldst_done;
+
+#endif
+
+ case 534: /* lwbrx */
+ err = read_mem(&val, xform_ea(instr, regs, 0), 4, regs);
+ if (!err)
+ regs->gpr[rd] = byterev_4(val);
+ goto ldst_done;
+
+ case 535: /* lfsx */
+ case 567: /* lfsux */
+ if (!(regs->msr & MSR_FP))
+ break;
+ ea = xform_ea(instr, regs, u);
+ err = do_fp_load(rd, do_lfs, ea, 4, regs);
+ goto ldst_done;
+
+ case 599: /* lfdx */
+ case 631: /* lfdux */
+ if (!(regs->msr & MSR_FP))
+ break;
+ ea = xform_ea(instr, regs, u);
+ err = do_fp_load(rd, do_lfd, ea, 8, regs);
+ goto ldst_done;
+
+ case 663: /* stfsx */
+ case 695: /* stfsux */
+ if (!(regs->msr & MSR_FP))
+ break;
+ ea = xform_ea(instr, regs, u);
+ err = do_fp_store(rd, do_stfs, ea, 4, regs);
+ goto ldst_done;
+
+ case 727: /* stfdx */
+ case 759: /* stfdux */
+ if (!(regs->msr & MSR_FP))
+ break;
+ ea = xform_ea(instr, regs, u);
+ err = do_fp_store(rd, do_stfd, ea, 8, regs);
+ goto ldst_done;
+
+#ifdef __powerpc64__
+ case 660: /* stdbrx */
+ val = byterev_8(regs->gpr[rd]);
+ err = write_mem(val, xform_ea(instr, regs, 0), 8, regs);
+ goto ldst_done;
+
+#endif
+ case 662: /* stwbrx */
+ val = byterev_4(regs->gpr[rd]);
+ err = write_mem(val, xform_ea(instr, regs, 0), 4, regs);
+ goto ldst_done;
+
+ case 790: /* lhbrx */
+ err = read_mem(&val, xform_ea(instr, regs, 0), 2, regs);
+ if (!err)
+ regs->gpr[rd] = byterev_2(val);
+ goto ldst_done;
+
+ case 918: /* sthbrx */
+ val = byterev_2(regs->gpr[rd]);
+ err = write_mem(val, xform_ea(instr, regs, 0), 2, regs);
+ goto ldst_done;
+
+#ifdef CONFIG_VSX
+ case 844: /* lxvd2x */
+ case 876: /* lxvd2ux */
+ if (!(regs->msr & MSR_VSX))
+ break;
+ rd |= (instr & 1) << 5;
+ ea = xform_ea(instr, regs, u);
+ err = do_vsx_load(rd, do_lxvd2x, ea, regs);
+ goto ldst_done;
+
+ case 972: /* stxvd2x */
+ case 1004: /* stxvd2ux */
+ if (!(regs->msr & MSR_VSX))
+ break;
+ rd |= (instr & 1) << 5;
+ ea = xform_ea(instr, regs, u);
+ err = do_vsx_store(rd, do_stxvd2x, ea, regs);
+ goto ldst_done;
+
+#endif /* CONFIG_VSX */
+ }
+ break;
+
+ case 32: /* lwz */
+ case 33: /* lwzu */
+ err = read_mem(®s->gpr[rd], dform_ea(instr, regs), 4, regs);
+ goto ldst_done;
+
+ case 34: /* lbz */
+ case 35: /* lbzu */
+ err = read_mem(®s->gpr[rd], dform_ea(instr, regs), 1, regs);
+ goto ldst_done;
+
+ case 36: /* stw */
+ case 37: /* stwu */
+ val = regs->gpr[rd];
+ err = write_mem(val, dform_ea(instr, regs), 4, regs);
+ goto ldst_done;
+
+ case 38: /* stb */
+ case 39: /* stbu */
+ val = regs->gpr[rd];
+ err = write_mem(val, dform_ea(instr, regs), 1, regs);
+ goto ldst_done;
+
+ case 40: /* lhz */
+ case 41: /* lhzu */
+ err = read_mem(®s->gpr[rd], dform_ea(instr, regs), 2, regs);
+ goto ldst_done;
+
+ case 42: /* lha */
+ case 43: /* lhau */
+ err = read_mem(®s->gpr[rd], dform_ea(instr, regs), 2, regs);
+ if (!err)
+ regs->gpr[rd] = (signed short) regs->gpr[rd];
+ goto ldst_done;
+
+ case 44: /* sth */
+ case 45: /* sthu */
+ err = write_mem(val, dform_ea(instr, regs), 2, regs);
+ goto ldst_done;
+
+ case 46: /* lmw */
+ ra = (instr >> 16) & 0x1f;
+ if (ra >= rd)
+ break; /* invalid form, ra in range to load */
+ ea = dform_ea(instr, regs);
+ do {
+ err = read_mem(®s->gpr[rd], ea, 4, regs);
+ if (err)
+ return 0;
+ ea += 4;
+ } while (++rd < 32);
+ goto instr_done;
+
+ case 47: /* stmw */
+ ea = dform_ea(instr, regs);
+ do {
+ err = write_mem(regs->gpr[rd], ea, 4, regs);
+ if (err)
+ return 0;
+ ea += 4;
+ } while (++rd < 32);
+ goto instr_done;
+
+ case 48: /* lfs */
+ case 49: /* lfsu */
+ if (!(regs->msr & MSR_FP))
+ break;
+ ea = dform_ea(instr, regs);
+ err = do_fp_load(rd, do_lfs, ea, 4, regs);
+ goto ldst_done;
+
+ case 50: /* lfd */
+ case 51: /* lfdu */
+ if (!(regs->msr & MSR_FP))
+ break;
+ ea = dform_ea(instr, regs);
+ err = do_fp_load(rd, do_lfd, ea, 8, regs);
+ goto ldst_done;
+
+ case 52: /* stfs */
+ case 53: /* stfsu */
+ if (!(regs->msr & MSR_FP))
+ break;
+ ea = dform_ea(instr, regs);
+ err = do_fp_store(rd, do_stfs, ea, 4, regs);
+ goto ldst_done;
+
+ case 54: /* stfd */
+ case 55: /* stfdu */
+ if (!(regs->msr & MSR_FP))
+ break;
+ ea = dform_ea(instr, regs);
+ err = do_fp_store(rd, do_stfd, ea, 8, regs);
+ goto ldst_done;
+
+#ifdef __powerpc64__
+ case 58: /* ld[u], lwa */
+ switch (instr & 3) {
+ case 0: /* ld */
+ err = read_mem(®s->gpr[rd], dsform_ea(instr, regs),
+ 8, regs);
+ goto ldst_done;
+ case 1: /* ldu */
+ err = read_mem(®s->gpr[rd], dsform_ea(instr, regs),
+ 8, regs);
+ goto ldst_done;
+ case 2: /* lwa */
+ err = read_mem(®s->gpr[rd], dsform_ea(instr, regs),
+ 4, regs);
+ if (!err)
+ regs->gpr[rd] = (signed int) regs->gpr[rd];
+ goto ldst_done;
+ }
+ break;
+
+ case 62: /* std[u] */
+ val = regs->gpr[rd];
+ switch (instr & 3) {
+ case 0: /* std */
+ err = write_mem(val, dsform_ea(instr, regs), 8, regs);
+ goto ldst_done;
+ case 1: /* stdu */
+ err = write_mem(val, dsform_ea(instr, regs), 8, regs);
+ goto ldst_done;
+ }
+ break;
+#endif /* __powerpc64__ */
+
+ }
+ err = -EINVAL;
+
+ ldst_done:
+ if (err) {
+ regs->gpr[ra] = old_ra;
+ return 0; /* invoke DSI if -EFAULT? */
+ }
+ instr_done:
+ regs->nip += 4;
+#ifdef __powerpc64__
+ if ((regs->msr & MSR_SF) == 0)
+ regs->nip &= 0xffffffffUL;
+#endif
+ return 1;
+
+ logical_done:
+ if (instr & 1)
+ set_cr0(regs, ra);
+ goto instr_done;
+
+ arith_done:
+ if (instr & 1)
+ set_cr0(regs, rd);
+ goto instr_done;
}
--
1.7.1
^ permalink raw reply related
* Re: [Patch 0/5] PPC64-HWBKPT: Hardware Breakpoint interfaces - ver XXII
From: Paul Mackerras @ 2010-06-02 11:33 UTC (permalink / raw)
To: K.Prasad; +Cc: linuxppc-dev@ozlabs.org, Benjamin Herrenschmidt
In-Reply-To: <20100528063924.GA8679@in.ibm.com>
On Fri, May 28, 2010 at 12:09:24PM +0530, K.Prasad wrote:
> Please find a new set of patches that have the following changes.
Thanks. There are a couple of minor things still remaining (dangling
put_cpu in arch_unregister_hw_breakpoint, plus I don't think reusing
current->thread.ptrace_bps the way you did in patch 5/5 is a good
idea), but I think at this stage I'll put them in a tree together
with my latest emulate_step version and then push them to Ben H and/or
Ingo Molnar once I've done some testing.
Paul.
^ permalink raw reply
* Re: [PATCH] powerpc: Emulate most Book I instructions in emulate_step()
From: Kumar Gala @ 2010-06-02 12:45 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, K.Prasad
In-Reply-To: <20100602112903.GB30149@brick.ozlabs.ibm.com>
On Jun 2, 2010, at 6:29 AM, Paul Mackerras wrote:
> This extends the emulate_step() function to handle a large proportion
> of the Book I instructions implemented on current 64-bit server
> processors. The aim is to handle all the load and store instructions
> used in the kernel, plus all of the instructions that appear between
> l[wd]arx and st[wd]cx., so this handles the Altivec/VMX lvx and stvx
> and the VSX lxv2dx and stxv2dx instructions (implemented in POWER7).
>=20
> The new code can emulate user mode instructions, and checks the
> effective address for a load or store if the saved state is for
> user mode. It doesn't handle little-endian mode at present.
>=20
> For floating-point, Altivec/VMX and VSX instructions, it checks
> that the saved MSR has the enable bit for the relevant facility
> set, and if so, assumes that the FP/VMX/VSX registers contain
> valid state, and does loads or stores directly to/from the
> FP/VMX/VSX registers, using assembly helpers in ldstfp.S.
>=20
> Instructions supported now include:
> * Loads and stores, including some but not all VMX and VSX =
instructions,
> and lmw/stmw
> * Atomic loads and stores (l[dw]arx, st[dw]cx.)
> * Integer arithmetic instructions (add, subtract, multiply, divide, =
etc.)
> * Compare instructions
> * Rotate and mask instructions
> * Shift instructions
> * Logical instructions (and, or, xor, etc.)
> * Condition register logical instructions
> * mtcrf, cntlz[wd], exts[bhw]
> * isync, sync, lwsync, ptesync, eieio
> * Cache operations (dcbf, dcbst, dcbt, dcbtst)
>=20
> The overflow-checking arithmetic instructions are not included, but
> they appear not to be ever used in C code. None of the floating
> point, VMX or VSX computational instructions are included.
>=20
> This uses decimal values for the minor opcodes in the switch =
statements
> because that is what appears in the Power ISA specification, thus it =
is
> easier to check that they are correct if they are in decimal.
>=20
> Signed-off-by: Paul Mackerras <paulus@samba.org>
> ---
> arch/powerpc/lib/Makefile | 4 +-
> arch/powerpc/lib/ldstfp.S | 207 ++++++
> arch/powerpc/lib/sstep.c | 1513 =
+++++++++++++++++++++++++++++++++++++++++++--
> 3 files changed, 1677 insertions(+), 47 deletions(-)
> create mode 100644 arch/powerpc/lib/ldstfp.S
Why do we need to have emu support for all of these instructions?
- k=
^ permalink raw reply
* [PATCH] powerpc: fix a compile error in fsl_msi.c
From: Kevin Hao @ 2010-06-02 12:07 UTC (permalink / raw)
To: Li Yang, Kumar Gala, Benjamin Herrenschmidt; +Cc: linuxppc-dev list
The commit 061ca4ad still use the old style to refer to device
node, and cause the following compile error.
arch/powerpc/sysdev/fsl_msi.c: In function 'fsl_of_msi_probe':
arch/powerpc/sysdev/fsl_msi.c:350: error: 'struct of_device' has no member named 'node'
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/sysdev/fsl_msi.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 0f5bee9..962c2d8 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -347,7 +347,7 @@ static int __devinit fsl_of_msi_probe(struct of_device *dev,
goto error_out;
}
offset = 0;
- p = of_get_property(dev->node, "msi-available-ranges", &len);
+ p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
if (p)
offset = *p / IRQS_PER_MSI_REG;
--
1.6.3.1
^ permalink raw reply related
* Re: [PATCH] KVM: PPC: elide struct thread_struct instances from stack
From: Marcelo Tosatti @ 2010-06-02 16:00 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev, kvm, kvm-ppc, Alexander Graf
In-Reply-To: <m26323onam.fsf@igel.home>
On Mon, May 31, 2010 at 09:59:13PM +0200, Andreas Schwab wrote:
> Instead of instantiating a whole thread_struct on the stack use only the
> required parts of it.
>
> Signed-off-by: Andreas Schwab <schwab@linux-m68k.org>
> Tested-by: Alexander Graf <agraf@suse.de>
> ---
> arch/powerpc/include/asm/kvm_fpu.h | 27 +++++----
> arch/powerpc/kernel/ppc_ksyms.c | 4 -
> arch/powerpc/kvm/book3s.c | 49 +++++++++-------
> arch/powerpc/kvm/book3s_paired_singles.c | 94 ++++++++++++------------------
> arch/powerpc/kvm/fpu.S | 18 ++++++
> 5 files changed, 97 insertions(+), 95 deletions(-)
Applied, thanks.
^ permalink raw reply
* Re: [PATCH] PowerPC: Remove hardcoded BAT configuration of IMMR in CPM early debug console
From: Scott Wood @ 2010-06-02 16:28 UTC (permalink / raw)
To: Martyn Welch; +Cc: linuxppc-dev
In-Reply-To: <4C0610F8.6020801@ge.com>
On 06/02/2010 03:06 AM, Martyn Welch wrote:
>>>> I think that's a more fundamental change to CPM early debug than I can
>>>> handle right now.
>>
>> Is IMMRBASE on your board at some address that has a low likelihood of
>> conflicting when treated as a kernel effective address?
>
> It's at 0x0f000000, is seems ok, but then I'm not sure I fully
> understand kernel effective addresses.
That overlaps userspace -- is the BAT cleared before userspace starts?
If you don't want to do the fixmap stuff, might want to at least just
leave it at the current arbitrary effective address, which hasn't seemed
to cause much trouble so far.
But fixmap is the right way to do it.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/oprofile: fix potential buffer overrun in op_model_cell.c
From: Carl Love @ 2010-06-02 20:12 UTC (permalink / raw)
To: Denis Kirjanov; +Cc: arnd, linuxppc-dev, paulus, jkosina, oprofile-list
In-Reply-To: <20100601194334.GA4549@hera.kernel.org>
[-- Attachment #1.1: Type: text/plain, Size: 2614 bytes --]
Denis:
I have reviewed the change and agree to it. Thanks for catching that.
Carl Love
Denis Kirjanov
<dkirjanov@hera.k
ernel.org> To
arnd@arndb.de,
06/01/2010 12:43 benh@kernel.crashing.org,
PM paulus@samba.org, jkosina@suse.cz
cc
linuxppc-dev@ozlabs.org,
oprofile-list@lists.sf.net
Subject
[PATCH] powerpc/oprofile: fix
potential buffer overrun in
op_model_cell.c
Fix potential initial_lfsr buffer overrun.
Writing past the end of the buffer could happen when index == ENTRIES
Signed-off-by: Denis Kirjanov <dkirjanov@kernel.org>
---
arch/powerpc/oprofile/op_model_cell.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/oprofile/op_model_cell.c
b/arch/powerpc/oprofile/op_model_cell.c
index 2c9e522..7fd90d0 100644
--- a/arch/powerpc/oprofile/op_model_cell.c
+++ b/arch/powerpc/oprofile/op_model_cell.c
@@ -1077,7 +1077,7 @@ static int calculate_lfsr(int n)
index = ENTRIES-1;
/* make sure index is valid */
- if ((index > ENTRIES) || (index < 0))
+ if ((index >= ENTRIES) || (index < 0))
index = ENTRIES-1;
return initial_lfsr[index];
------------------------------------------------------------------------------
_______________________________________________
oprofile-list mailing list
oprofile-list@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/oprofile-list
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^ permalink raw reply related
* Re: [PATCH] powerpc: Fix ioremap_flags() with book3e pte definition
From: Kumar Gala @ 2010-06-02 21:59 UTC (permalink / raw)
To: Greg KH; +Cc: linuxppc-dev, stable
In-Reply-To: <1274726319-4673-1-git-send-email-galak@kernel.crashing.org>
On May 24, 2010, at 1:38 PM, Kumar Gala wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>=20
> We can't just clear the user read permission in book3e pte, because
> that will also clear supervisor read permission. This surely isn't
> desired. Fix the problem by adding the supervisor read back.
>=20
> BenH: Slightly simplified the ifdef and applied to ppc64 too
>=20
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> For 2.6.34 stable commit 55052eeca6d71d76f7c3f156c0501814d8e5e6d3
>=20
> arch/powerpc/mm/pgtable_32.c | 8 ++++++++
> arch/powerpc/mm/pgtable_64.c | 8 ++++++++
> 2 files changed, 16 insertions(+), 0 deletions(-)
Wondering what happened to this patch (and 2 other) getting into stable =
queue for .34.x
- k=
^ permalink raw reply
* Re: [PATCH] powerpc: Fix ioremap_flags() with book3e pte definition
From: Greg KH @ 2010-06-02 22:02 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, stable
In-Reply-To: <81DFFD59-BF21-4754-B006-805CFDC09576@kernel.crashing.org>
On Wed, Jun 02, 2010 at 04:59:16PM -0500, Kumar Gala wrote:
>
> On May 24, 2010, at 1:38 PM, Kumar Gala wrote:
>
> > From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >
> > We can't just clear the user read permission in book3e pte, because
> > that will also clear supervisor read permission. This surely isn't
> > desired. Fix the problem by adding the supervisor read back.
> >
> > BenH: Slightly simplified the ifdef and applied to ppc64 too
> >
> > Signed-off-by: Li Yang <leoli@freescale.com>
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > ---
> > For 2.6.34 stable commit 55052eeca6d71d76f7c3f156c0501814d8e5e6d3
> >
> > arch/powerpc/mm/pgtable_32.c | 8 ++++++++
> > arch/powerpc/mm/pgtable_64.c | 8 ++++++++
> > 2 files changed, 16 insertions(+), 0 deletions(-)
>
> Wondering what happened to this patch (and 2 other) getting into stable queue for .34.x
They are still in the "to-apply" queue. Please be patient, I was busy
with the .35-rc1 merge window and now am catching up on the stable
trees. There's over 130 patches that people seem to want in the first
.34 stable release, so it's taking some time to get them all in and
tested.
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH] powerpc: Emulate most Book I instructions in emulate_step()
From: Paul Mackerras @ 2010-06-03 0:47 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, K.Prasad
In-Reply-To: <09904F7B-6319-45FA-ADC4-757A2AD239AB@kernel.crashing.org>
On Wed, Jun 02, 2010 at 07:45:27AM -0500, Kumar Gala wrote:
> Why do we need to have emu support for all of these instructions?
Fair question. This arose in the context of the support for data
breakpoint events in perf_events. Since the data breakpoint facility
on our processors (DABR on server, DAC/DVC on Book 3E) interrupts
before doing the access, we have to execute the instruction that
caused the breakpoint without the data breakpoint set, then put the
data breakpoint back and carry on.
The interesting case comes when the interrupt occurs on a
lwarx/ldarx. If we just single-step it, we'll lose the reservation
and most likely get into an infinite loop, making no progress. So we
have two alternatives: either try to arrange that we can single-step
the lwarx and get to the stwcx without losing the reservation, or
emulate the lwarx and all the instructions up to and including the
stwcx.
The first alternative seemed pretty fragile to me since it means that
we have to arrange that we can single-step and take data breakpoints
without using any spinlocks, mutexes or atomic ops (including
bitops). Also, the architecture says that some embedded
implementations might clear the reservation on taking an interrupt
(which presumably could include debug interrupts).
The second alternative -- emulating the lwarx/stwcx and all the
instructions in between -- sounds complicated but turns out to be
pretty straightforward in fact, since the code for each instruction is
pretty small, easy to verify that it's correct, and has little
interaction with other code.
Note that we have to do this emulation both for the kernel and for
user code, since a data breakpoint event could occur in the kernel or
in usermode. While we can constrain what occurs between lwarx/stwcx
in the kernel pretty tightly, userspace is not so well constrained, so
I though it best to do all the integer ops that can be done reasonably
easily and can occur in C code.
The other thing I want to do is use this to replace the alignment
fixup code, since they're doing very similar things now. That will
need little-endian support plus implementing the rest of the Altivec
and VSX loads and stores, along with dcbz, l/stswi, l/stswx, etc.
Finally, emulating should be faster than single-stepping, and so
extending the set of emulated instructions should improve the
performance of kprobes and uprobes.
Paul.
^ permalink raw reply
* Re: [PATCH] powerpc: Emulate most Book I instructions in emulate_step()
From: Matt Evans @ 2010-06-03 1:10 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, K.Prasad
In-Reply-To: <20100603004758.GA19618@brick.ozlabs.ibm.com>
Paul Mackerras wrote:
> [snip]
> The second alternative -- emulating the lwarx/stwcx and all the
> instructions in between -- sounds complicated but turns out to be
> pretty straightforward in fact, since the code for each instruction is
> pretty small, easy to verify that it's correct, and has little
> interaction with other code.
Easy to verify -- visually or logically?
Having had a little experience with interpreters 'invisibly' operating behind the scenes I am all for very rigorous testing of these things. I have lost at least four of my nine lives to incorrect flag values, odd data problems and hideous heisenbugs etc. of such interpreters. Looked at another way, you'd be surprised how much one can break in an interpreter and still successfully run various programs.
Presumably your first pass is completely correct already, but I'm thinking that if any future changes are made to it
it would be good to include test code/modes alongside the interpreter so others can check alterations. E.g. include the "run user program interpreted" test switch patch, or even better compare the interpreted state to real hardware execution. There are other more directed test strategies (e.g. handwritten tests, random code) but these would be a good start.
Cheers,
Matt
^ permalink raw reply
* Re: [PATCH] powerpc: Emulate most Book I instructions in emulate_step()
From: Michael Ellerman @ 2010-06-03 1:43 UTC (permalink / raw)
To: Matt Evans; +Cc: linuxppc-dev, Paul Mackerras, K.Prasad
In-Reply-To: <4C0700FD.6060303@ozlabs.org>
[-- Attachment #1: Type: text/plain, Size: 1580 bytes --]
On Thu, 2010-06-03 at 11:10 +1000, Matt Evans wrote:
> Paul Mackerras wrote:
> > [snip]
> > The second alternative -- emulating the lwarx/stwcx and all the
> > instructions in between -- sounds complicated but turns out to be
> > pretty straightforward in fact, since the code for each instruction is
> > pretty small, easy to verify that it's correct, and has little
> > interaction with other code.
>
> Easy to verify -- visually or logically?
>
> Having had a little experience with interpreters 'invisibly' operating
> behind the scenes I am all for very rigorous testing of these things.
> I have lost at least four of my nine lives to incorrect flag values,
> odd data problems and hideous heisenbugs etc. of such interpreters.
> Looked at another way, you'd be surprised how much one can break in an
> interpreter and still successfully run various programs.
>
> Presumably your first pass is completely correct already, but I'm
> thinking that if any future changes are made to it
> it would be good to include test code/modes alongside the interpreter
> so others can check alterations. E.g. include the "run user program
> interpreted" test switch patch, or even better compare the interpreted
> state to real hardware execution. There are other more directed test
> strategies (e.g. handwritten tests, random code) but these would be a
> good start.
Emphatic nod. We all trust Paulus to get this right, but I for one would
not be game to touch it without a test suite.
It's ripe territory for a boot time selftest IMHO.
cheers
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^ permalink raw reply
* Re: [PATCH] [SCSI] ipr: Fix stack overflow in ipr_format_resource_path
From: Wayne Boyer @ 2010-06-03 4:14 UTC (permalink / raw)
To: Anton Blanchard; +Cc: betabandido, linux-scsi, linuxppc-dev
In-Reply-To: <20100602111658.GH28295@kryten>
Hi Anton,
We also saw a variation of this problem last week and I have an alternative
patch that I'd prefer over this one. I'll post the patch in a separate
email.
Thanks,
--
Wayne Boyer
IBM - Beaverton, Oregon
LTC S/W Development - eServerIO
(503) 578-5236, T/L 775-5236
On 06/02/2010 04:16 AM, Anton Blanchard wrote:
>
> Victor reported an oops during boot with 2.6.34 on a POWER6 JS22:
>
> https://bugzilla.kernel.org/show_bug.cgi?id=16089
>
> Checking ipr microcode levels
> Unable to handle kernel paging request for instruction fetch
> Faulting instruction address: 0x322d30312d31302c
> ...
> Oops: Kernel access of bad area, sig: 11 [#1]
> SMP NR_CPUS=128 NUMA pSeries
> last sysfs file:
> /sys/devices/pci0000:00/0000:00:01.0/host0/target0:255:255/0:255:255:255/resource_path
> Modules linked in:
> NIP: 322d30312d31302c LR: 322d30312d31302d CTR: c000000000375bec
> REGS: c0000003d360f8f0 TRAP: 0400 Not tainted (2.6.34-vjj)
> MSR: 8000000040009432 <EE,ME,IR,DR> CR: 28002484 XER: 20000020
> TASK = c0000003d587d010[5163] 'iprupdate' THREAD: c0000003d360c000 CPU: 7
> GPR00: 322d30312d31302d c0000003d360fb70 c000000000ad07c0 00000000000185a0
> GPR04: 0000000000000001 c0000003d360fb10 04000affffffffff c0000000006a6700
> GPR08: c000000000823383 0000000000000000 0000000000000020 0000000000000000
> GPR12: 000000000000f032 c00000000f622e00 00000000000000ed 0000000000000000
> GPR16: 00000000100b8808 0000000010020000 0000000010020000 0000000010010000
> GPR20: 0000000010010000 0000000000000001 0000000000001000 000000001045eef8
> GPR24: c0000003d360fdf8 302d31342d31302d 43302d30302d3030 2d30332d44352d34
> GPR28: 422d33382d30302d 30302d30302d3030 2d30302d30302d30 302d30302d30302d
> NIP [322d30312d31302c] 0x322d30312d31302c
> LR [322d30312d31302d] 0x322d30312d31302d
>
> A stack overflow. It turns out ipr_format_resource_path writes to a
> passed in buffer using sprintf which is dangerous and in this case looks
> to be the cause of the overflow.
>
> The following patch passes in the length of the buffer and uses snprintf,
> which fixes the fail for me. It doesn't fix the other issue, which is
> why the loop in ipr_format_resource_path didn't terminate in the first place.
> That can be fixed in a follow up patch.
>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
>
> Index: linux.trees.git/drivers/scsi/ipr.c
> ===================================================================
> --- linux.trees.git.orig/drivers/scsi/ipr.c 2010-05-31 08:51:20.000000000 +1000
> +++ linux.trees.git/drivers/scsi/ipr.c 2010-06-02 21:15:41.000000000 +1000
> @@ -1132,17 +1132,20 @@ static int ipr_is_same_device(struct ipr
> * ipr_format_resource_path - Format the resource path for printing.
> * @res_path: resource path
> * @buf: buffer
> + * @len: length of the buffer
> *
> * Return value:
> * pointer to buffer
> **/
> -static char *ipr_format_resource_path(u8 *res_path, char *buffer)
> +static char *ipr_format_resource_path(u8 *res_path, char *buffer,
> + unsigned int len)
> {
> int i;
> + char *p = buffer;
>
> - sprintf(buffer, "%02X", res_path[0]);
> + p += snprintf(p, buffer + len - p, "%02X", res_path[0]);
> for (i=1; res_path[i] != 0xff; i++)
> - sprintf(buffer, "%s-%02X", buffer, res_path[i]);
> + p += snprintf(p, buffer + len - p, "-%02X", res_path[i]);
>
> return buffer;
> }
> @@ -1187,7 +1190,8 @@ static void ipr_update_res_entry(struct
>
> if (res->sdev && new_path)
> sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
> - ipr_format_resource_path(&res->res_path[0], &buffer[0]));
> + ipr_format_resource_path(&res->res_path[0],
> + &buffer[0], sizeof(buffer)));
> } else {
> res->flags = cfgtew->u.cfgte->flags;
> if (res->flags & IPR_IS_IOA_RESOURCE)
> @@ -1573,7 +1577,8 @@ static void ipr_log_sis64_config_error(s
> ipr_err_separator;
>
> ipr_err("Device %d : %s", i + 1,
> - ipr_format_resource_path(&dev_entry->res_path[0], &buffer[0]));
> + ipr_format_resource_path(&dev_entry->res_path[0],
> + &buffer[0], sizeof(buffer)));
> ipr_log_ext_vpd(&dev_entry->vpd);
>
> ipr_err("-----New Device Information-----\n");
> @@ -1919,13 +1924,15 @@ static void ipr_log64_fabric_path(struct
>
> ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
> path_active_desc[i].desc, path_state_desc[j].desc,
> - ipr_format_resource_path(&fabric->res_path[0], &buffer[0]));
> + ipr_format_resource_path(&fabric->res_path[0],
> + &buffer[0], sizeof(buffer)));
> return;
> }
> }
>
> ipr_err("Path state=%02X Resource Path=%s\n", path_state,
> - ipr_format_resource_path(&fabric->res_path[0], &buffer[0]));
> + ipr_format_resource_path(&fabric->res_path[0], &buffer[0],
> + sizeof(buffer)));
> }
>
> static const struct {
> @@ -2066,7 +2073,9 @@ static void ipr_log64_path_elem(struct i
>
> ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
> path_status_desc[j].desc, path_type_desc[i].desc,
> - ipr_format_resource_path(&cfg->res_path[0], &buffer[0]),
> + ipr_format_resource_path(&cfg->res_path[0],
> + &buffer[0],
> + sizeof(buffer)),
> link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
> be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
> return;
> @@ -2074,7 +2083,8 @@ static void ipr_log64_path_elem(struct i
> }
> ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
> "WWN=%08X%08X\n", cfg->type_status,
> - ipr_format_resource_path(&cfg->res_path[0], &buffer[0]),
> + ipr_format_resource_path(&cfg->res_path[0], &buffer[0],
> + sizeof(buffer)),
> link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
> be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
> }
> @@ -2139,7 +2149,8 @@ static void ipr_log_sis64_array_error(st
>
> ipr_err("RAID %s Array Configuration: %s\n",
> error->protection_level,
> - ipr_format_resource_path(&error->last_res_path[0], &buffer[0]));
> + ipr_format_resource_path(&error->last_res_path[0], &buffer[0],
> + sizeof(buffer)));
>
> ipr_err_separator;
>
> @@ -2160,9 +2171,12 @@ static void ipr_log_sis64_array_error(st
> ipr_err("Array Member %d:\n", i);
> ipr_log_ext_vpd(&array_entry->vpd);
> ipr_err("Current Location: %s",
> - ipr_format_resource_path(&array_entry->res_path[0], &buffer[0]));
> + ipr_format_resource_path(&array_entry->res_path[0],
> + &buffer[0],
> + sizeof(buffer)));
> ipr_err("Expected Location: %s",
> - ipr_format_resource_path(&array_entry->expected_res_path[0], &buffer[0]));
> + ipr_format_resource_path(&array_entry->expected_res_path[0],
> + &buffer[0], sizeof(buffer)));
>
> ipr_err_separator;
> }
> @@ -4099,7 +4113,9 @@ static ssize_t ipr_show_resource_path(st
> res = (struct ipr_resource_entry *)sdev->hostdata;
> if (res)
> len = snprintf(buf, PAGE_SIZE, "%s\n",
> - ipr_format_resource_path(&res->res_path[0], &buffer[0]));
> + ipr_format_resource_path(&res->res_path[0],
> + &buffer[0],
> + sizeof(buffer)));
> spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
> return len;
> }
> @@ -4351,7 +4367,9 @@ static int ipr_slave_configure(struct sc
> scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
> if (ioa_cfg->sis64)
> sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
> - ipr_format_resource_path(&res->res_path[0], &buffer[0]));
> + ipr_format_resource_path(&res->res_path[0],
> + &buffer[0],
> + sizeof(buffer)));
> return 0;
> }
> spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
> Index: linux.trees.git/drivers/scsi/ipr.h
> ===================================================================
> --- linux.trees.git.orig/drivers/scsi/ipr.h 2010-05-31 08:51:20.000000000 +1000
> +++ linux.trees.git/drivers/scsi/ipr.h 2010-06-02 21:15:41.000000000 +1000
> @@ -1685,7 +1685,8 @@ struct ipr_ucode_image_header {
> if ((hostrcb)->ioa_cfg->sis64) { \
> printk(KERN_ERR IPR_NAME ": %s: " fmt, \
> ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
> - &hostrcb->rp_buffer[0]), \
> + &hostrcb->rp_buffer[0], \
> + sizeof(hostrcb->rp_buffer)), \
> __VA_ARGS__); \
> } else { \
> ipr_ra_err((hostrcb)->ioa_cfg, \
> --
> To unsubscribe from this list: send the line "unsubscribe linux-scsi" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] [SCSI] ipr: Fix stack overflow in ipr_format_resource_path
From: Anton Blanchard @ 2010-06-03 4:20 UTC (permalink / raw)
To: Wayne Boyer; +Cc: betabandido, linux-scsi, linuxppc-dev
In-Reply-To: <4C072C18.4030005@linux.vnet.ibm.com>
Hi Wayne,
> We also saw a variation of this problem last week and I have an alternative
> patch that I'd prefer over this one. I'll post the patch in a separate
> email.
Thanks. Can you get it into -stable too? As you can see users are hitting it.
Anton
^ permalink raw reply
* [PATCH] kvm/powerpc: fix a build error in e500_tlb.c
From: Kevin Hao @ 2010-06-03 5:52 UTC (permalink / raw)
To: Marcelo Tosatti, Kumar Gala, Avi Kivity, Alexander Graf; +Cc: linuxppc-dev, kvm
We use the wrong number arguments when invoking trace_kvm_stlb_inval,
and cause the following build error.
arch/powerpc/kvm/e500_tlb.c: In function 'kvmppc_e500_stlbe_invalidate':
arch/powerpc/kvm/e500_tlb.c:230: error: too many arguments to function 'trace_kvm_stlb_inval'
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/kvm/e500_tlb.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index 21011e1..1261a21 100644
--- a/arch/powerpc/kvm/e500_tlb.c
+++ b/arch/powerpc/kvm/e500_tlb.c
@@ -226,8 +226,7 @@ static void kvmppc_e500_stlbe_invalidate(struct kvmppc_vcpu_e500 *vcpu_e500,
kvmppc_e500_shadow_release(vcpu_e500, tlbsel, esel);
stlbe->mas1 = 0;
- trace_kvm_stlb_inval(index_of(tlbsel, esel), stlbe->mas1, stlbe->mas2,
- stlbe->mas3, stlbe->mas7);
+ trace_kvm_stlb_inval(index_of(tlbsel, esel));
}
static void kvmppc_e500_tlb1_invalidate(struct kvmppc_vcpu_e500 *vcpu_e500,
--
1.6.3.1
^ permalink raw reply related
* Re: [PATCH] powerpc: Emulate most Book I instructions in emulate_step()
From: Kumar Gala @ 2010-06-03 6:25 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, K.Prasad
In-Reply-To: <20100603004758.GA19618@brick.ozlabs.ibm.com>
On Jun 2, 2010, at 7:47 PM, Paul Mackerras wrote:
> On Wed, Jun 02, 2010 at 07:45:27AM -0500, Kumar Gala wrote:
>=20
>> Why do we need to have emu support for all of these instructions?
>=20
> Fair question. This arose in the context of the support for data
> breakpoint events in perf_events. Since the data breakpoint facility
> on our processors (DABR on server, DAC/DVC on Book 3E) interrupts
> before doing the access, we have to execute the instruction that
> caused the breakpoint without the data breakpoint set, then put the
> data breakpoint back and carry on.
>=20
> The interesting case comes when the interrupt occurs on a
> lwarx/ldarx. If we just single-step it, we'll lose the reservation
> and most likely get into an infinite loop, making no progress. So we
> have two alternatives: either try to arrange that we can single-step
> the lwarx and get to the stwcx without losing the reservation, or
> emulate the lwarx and all the instructions up to and including the
> stwcx.
>=20
> The first alternative seemed pretty fragile to me since it means that
> we have to arrange that we can single-step and take data breakpoints
> without using any spinlocks, mutexes or atomic ops (including
> bitops). Also, the architecture says that some embedded
> implementations might clear the reservation on taking an interrupt
> (which presumably could include debug interrupts).
>=20
> The second alternative -- emulating the lwarx/stwcx and all the
> instructions in between -- sounds complicated but turns out to be
> pretty straightforward in fact, since the code for each instruction is
> pretty small, easy to verify that it's correct, and has little
> interaction with other code.
>=20
> Note that we have to do this emulation both for the kernel and for
> user code, since a data breakpoint event could occur in the kernel or
> in usermode. While we can constrain what occurs between lwarx/stwcx
> in the kernel pretty tightly, userspace is not so well constrained, so
> I though it best to do all the integer ops that can be done reasonably
> easily and can occur in C code.
>=20
> The other thing I want to do is use this to replace the alignment
> fixup code, since they're doing very similar things now. That will
> need little-endian support plus implementing the rest of the Altivec
> and VSX loads and stores, along with dcbz, l/stswi, l/stswx, etc.
>=20
> Finally, emulating should be faster than single-stepping, and so
> extending the set of emulated instructions should improve the
> performance of kprobes and uprobes.
Thanks, mind appending the commit message w/some of this so 20 kernel =
versions from now we'll remember why this was added :)
- k=
^ permalink raw reply
* [PATCH] powerpc: unconditionally enabled irq stacks
From: Christoph Hellwig @ 2010-06-03 8:24 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
Irq stacks provide an essential protection from stack overflows through
external interrupts, at the cost of two additionals stacks per CPU.
Enable them unconditionally to simplify the kernel build and prevent
people from accidentally disabling them.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Index: linux-2.6/arch/powerpc/Kconfig.debug
===================================================================
--- linux-2.6.orig/arch/powerpc/Kconfig.debug 2010-05-26 13:38:58.839003980 +0200
+++ linux-2.6/arch/powerpc/Kconfig.debug 2010-06-03 10:20:08.965273921 +0200
@@ -135,13 +135,6 @@ config DEBUGGER
depends on KGDB || XMON
default y
-config IRQSTACKS
- bool "Use separate kernel stacks when processing interrupts"
- help
- If you say Y here the kernel will use separate kernel stacks
- for handling hard and soft interrupts. This can help avoid
- overflowing the process kernel stacks.
-
config VIRQ_DEBUG
bool "Expose hardware/virtual IRQ mapping via debugfs"
depends on DEBUG_FS
Index: linux-2.6/arch/powerpc/include/asm/irq.h
===================================================================
--- linux-2.6.orig/arch/powerpc/include/asm/irq.h 2010-05-25 19:27:32.731003980 +0200
+++ linux-2.6/arch/powerpc/include/asm/irq.h 2010-06-03 10:20:08.965273921 +0200
@@ -358,7 +358,6 @@ extern void exc_lvl_ctx_init(void);
#define exc_lvl_ctx_init()
#endif
-#ifdef CONFIG_IRQSTACKS
/*
* Per-cpu stacks for handling hard and soft interrupts.
*/
@@ -369,11 +368,6 @@ extern void irq_ctx_init(void);
extern void call_do_softirq(struct thread_info *tp);
extern int call_handle_irq(int irq, void *p1,
struct thread_info *tp, void *func);
-#else
-#define irq_ctx_init()
-
-#endif /* CONFIG_IRQSTACKS */
-
extern void do_IRQ(struct pt_regs *regs);
#endif /* _ASM_IRQ_H */
Index: linux-2.6/arch/powerpc/kernel/irq.c
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/irq.c 2010-05-26 13:38:58.958005865 +0200
+++ linux-2.6/arch/powerpc/kernel/irq.c 2010-06-03 10:20:08.971003841 +0200
@@ -317,7 +317,6 @@ void fixup_irqs(const struct cpumask *ma
}
#endif
-#ifdef CONFIG_IRQSTACKS
static inline void handle_one_irq(unsigned int irq)
{
struct thread_info *curtp, *irqtp;
@@ -358,12 +357,6 @@ static inline void handle_one_irq(unsign
if (irqtp->flags)
set_bits(irqtp->flags, &curtp->flags);
}
-#else
-static inline void handle_one_irq(unsigned int irq)
-{
- generic_handle_irq(irq);
-}
-#endif
static inline void check_stack_overflow(void)
{
@@ -455,7 +448,6 @@ void exc_lvl_ctx_init(void)
}
#endif
-#ifdef CONFIG_IRQSTACKS
struct thread_info *softirq_ctx[NR_CPUS] __read_mostly;
struct thread_info *hardirq_ctx[NR_CPUS] __read_mostly;
@@ -492,10 +484,6 @@ static inline void do_softirq_onstack(vo
irqtp->task = NULL;
}
-#else
-#define do_softirq_onstack() __do_softirq()
-#endif /* CONFIG_IRQSTACKS */
-
void do_softirq(void)
{
unsigned long flags;
Index: linux-2.6/arch/powerpc/kernel/misc_32.S
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/misc_32.S 2010-06-02 09:26:40.048004190 +0200
+++ linux-2.6/arch/powerpc/kernel/misc_32.S 2010-06-03 10:20:08.977033804 +0200
@@ -33,7 +33,6 @@
.text
-#ifdef CONFIG_IRQSTACKS
_GLOBAL(call_do_softirq)
mflr r0
stw r0,4(r1)
@@ -56,7 +55,6 @@ _GLOBAL(call_handle_irq)
lwz r0,4(r1)
mtlr r0
blr
-#endif /* CONFIG_IRQSTACKS */
/*
* This returns the high 64 bits of the product of two 64-bit numbers.
Index: linux-2.6/arch/powerpc/kernel/misc_64.S
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/misc_64.S 2010-05-26 13:38:58.963008170 +0200
+++ linux-2.6/arch/powerpc/kernel/misc_64.S 2010-06-03 10:20:08.985033594 +0200
@@ -28,7 +28,6 @@
.text
-#ifdef CONFIG_IRQSTACKS
_GLOBAL(call_do_softirq)
mflr r0
std r0,16(r1)
@@ -52,7 +51,6 @@ _GLOBAL(call_handle_irq)
ld r0,16(r1)
mtlr r0
blr
-#endif /* CONFIG_IRQSTACKS */
.section ".toc","aw"
PPC64_CACHES:
Index: linux-2.6/arch/powerpc/kernel/process.c
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/process.c 2010-05-26 13:38:58.969003561 +0200
+++ linux-2.6/arch/powerpc/kernel/process.c 2010-06-03 10:20:08.992032756 +0200
@@ -1005,7 +1005,6 @@ out:
return error;
}
-#ifdef CONFIG_IRQSTACKS
static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
unsigned long nbytes)
{
@@ -1030,10 +1029,6 @@ static inline int valid_irq_stack(unsign
return 0;
}
-#else
-#define valid_irq_stack(sp, p, nb) 0
-#endif /* CONFIG_IRQSTACKS */
-
int validate_sp(unsigned long sp, struct task_struct *p,
unsigned long nbytes)
{
Index: linux-2.6/arch/powerpc/kernel/setup_32.c
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/setup_32.c 2010-05-25 19:27:32.767003492 +0200
+++ linux-2.6/arch/powerpc/kernel/setup_32.c 2010-06-03 10:20:08.998034153 +0200
@@ -241,7 +241,6 @@ int __init ppc_init(void)
arch_initcall(ppc_init);
-#ifdef CONFIG_IRQSTACKS
static void __init irqstack_early_init(void)
{
unsigned int i;
@@ -255,9 +254,6 @@ static void __init irqstack_early_init(v
__va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
}
}
-#else
-#define irqstack_early_init()
-#endif
#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
static void __init exc_lvl_early_init(void)
Index: linux-2.6/arch/powerpc/kernel/setup_64.c
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/setup_64.c 2010-05-26 13:38:58.987005796 +0200
+++ linux-2.6/arch/powerpc/kernel/setup_64.c 2010-06-03 10:20:09.003255762 +0200
@@ -432,7 +432,6 @@ static u64 slb0_limit(void)
return 1UL << SID_SHIFT;
}
-#ifdef CONFIG_IRQSTACKS
static void __init irqstack_early_init(void)
{
u64 limit = slb0_limit();
@@ -451,9 +450,6 @@ static void __init irqstack_early_init(v
THREAD_SIZE, limit));
}
}
-#else
-#define irqstack_early_init()
-#endif
#ifdef CONFIG_PPC_BOOK3E
static void __init exc_lvl_early_init(void)
^ permalink raw reply
* Re: [PATCH 1/5] sched: fix capacity calculations for SMT4
From: Peter Zijlstra @ 2010-06-03 8:56 UTC (permalink / raw)
To: svaidy
Cc: Michael Neuling, Suresh Siddha, Gautham R Shenoy, linux-kernel,
linuxppc-dev, Ingo Molnar
In-Reply-To: <20100601225250.GA7764@dirshya.in.ibm.com>
On Wed, 2010-06-02 at 04:22 +0530, Vaidyanathan Srinivasan wrote:
> > If the group were a core group, the total would be much higher and we'd
> > likely end up assigning 1 to each before we'd run out of capacity.
>=20
> This is a tricky case because we are depending upon the
> DIV_ROUND_CLOSEST to decide whether to flag capacity to 0 or 1. We
> will not have any task movement until capacity is depleted to quite
> low value due to RT task. Having a threshold to flag 0/1 instead of
> DIV_ROUND_CLOSEST just like you have suggested in the power savings
> case may help here as well to move tasks to other idle cores.
Right, well we could put the threshold higher than the 50%, say 90% or
so.
> > For power savings, we can lower the threshold and maybe use the maximal
> > individual cpu_power in the group to base 1 capacity from.
> >=20
> > So, suppose the second example, where sibling0 has 50 and the others
> > have 294, you'd end up with a capacity distribution of: {0,1,1,1}.
>=20
> One challenge here is that if RT tasks run on more that one thread in
> this group, we will have slightly different cpu powers. Arranging
> them from max to min and having a cutoff threshold should work.
Right, like the 90% above.
> Should we keep the RT scaling as a separate entity along with
> cpu_power to simplify these thresholds. Whenever we need to scale
> group load with cpu power can take the product of cpu_power and
> scale_rt_power but in these cases where we compute capacity, we can
> mark a 0 or 1 just based on whether scale_rt_power was less than
> SCHED_LOAD_SCALE or not. Alternatively we can keep cpu_power as
> a product of all scaling factors as it is today but save the component
> scale factors also like scale_rt_power() and arch_scale_freq_power()
> so that it can be used in load balance decisions.
Right, so the question is, do we only care about RT or should capacity
reflect the full asymmetric MP case.
I don't quite see why RT is special from any of the other scale factors,
if someone pegged one core at half the frequency of the others you'd
still want it to get 0 capacity so that we only try to populate it on
overload.
> Basically in power save balance we would give all threads a capacity
> '1' unless the cpu_power was reduced due to RT task. Similarly in
> the non-power save case, we can have flag 1,0,0,0 unless first thread
> had a RT scaling during the last interval.
>=20
> I am suggesting to distinguish the reduction is cpu_power due to
> architectural (hardware DVFS) reasons from RT tasks so that it is easy
> to decide if moving tasks to sibling thread or core can help or not.
For power savings such a special heuristic _might_ make sense.
^ permalink raw reply
* Re: [PATCH] PowerPC: Remove hardcoded BAT configuration of IMMR in CPM early debug console
From: Martyn Welch @ 2010-06-03 9:12 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <4C068691.6040501@freescale.com>
Scott Wood wrote:
> On 06/02/2010 03:06 AM, Martyn Welch wrote:
>>>>> I think that's a more fundamental change to CPM early debug than I
>>>>> can
>>>>> handle right now.
>>>
>>> Is IMMRBASE on your board at some address that has a low likelihood of
>>> conflicting when treated as a kernel effective address?
>>
>> It's at 0x0f000000, is seems ok, but then I'm not sure I fully
>> understand kernel effective addresses.
>
> That overlaps userspace -- is the BAT cleared before userspace starts?
>
To be honest, once I'd got the device booting past the early debug
stage, I rebuilt the kernel without udbg in it...
> If you don't want to do the fixmap stuff, might want to at least just
> leave it at the current arbitrary effective address, which hasn't
> seemed to cause much trouble so far.
>
Given that I've now switched udbg off in the kernel config, I really
can't substantiate spending much more time on this. This patch was
mainly to help others that maybe struggling to bring up Linux on a
device with CPM serial.
I'll try and get a revised patch out soon which keeps the current
arbitrary effective address.
Martyn
> But fixmap is the right way to do it.
>
> -Scott
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748 | Barbirolli Square, Manchester,
E martyn.welch@ge.com | M2 3AB VAT:GB 927559189
^ permalink raw reply
* Adding a section to linux kernel
From: Azhar Shaikh @ 2010-06-03 11:41 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 683 bytes --]
Hi,
I am building a kernel module on linux-2.6.31 on a PowerPC architecture.
While buildng the module i am including a static library given by the
client.
I am getting the below warning while building the module with the library:
WARNING: /home/drivers/modules/module.o (.ghsinfo): unexpected
non-allocatable section.
Did you forget to use "ax"/"aw" in a .S file?
Note that for example <linux/init.h> contains
section definitions for use in .S files.
The .ghsinfo section i havent used in my code. It is being used in the
Library given by the client.
Does anyone know how do i include a section (namely .ghsinfo) into the
kernel to get rid of the above warning?
Regards,
Azhar
[-- Attachment #2: Type: text/html, Size: 812 bytes --]
^ permalink raw reply
* Anyone using "PowerPC" little-endian mode?
From: Paul Mackerras @ 2010-06-03 12:20 UTC (permalink / raw)
To: linuxppc-dev
Currently the kernel supports processes running in little-endian mode
on machines that have a little-endian mode (as opposed to an endian
bit in the TLB entry like most embedded PowerPC processors do, which
is a much better idea). Little-endian mode comes in two flavours:
so-called "PowerPC" little-endian mode, which works by swizzling the
bottom 3 bits of the address, and "true" little-endian mode, which
actually swaps the order of the bytes read from or written to memory.
The classic 32-bit processors (603, 604, 750, 74xx, and derivatives)
implemented PowerPC little-endian mode, and I think some early 64-bit
processors did also. POWER6 and POWER7 implement true little-endian
mode. POWER4, PPC970 and POWER5 don't implement any little-endian
mode.
Is anyone actually using little-endian mode processes on processors
that implement PowerPC little-endian mode? One of the ways that we
could make the alignment interrupt handler go faster is by removing
the code for address swizzling that we have in order to handle PowerPC
little-endian mode. If nobody is actually using it, we should
remove it and make the code simpler and faster.
Paul.
^ permalink raw reply
* Re: Anyone using "PowerPC" little-endian mode?
From: Gary Thomas @ 2010-06-03 12:25 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20100603122012.GA22799@brick.ozlabs.ibm.com>
On 06/03/2010 06:20 AM, Paul Mackerras wrote:
> Currently the kernel supports processes running in little-endian mode
> on machines that have a little-endian mode (as opposed to an endian
> bit in the TLB entry like most embedded PowerPC processors do, which
> is a much better idea). Little-endian mode comes in two flavours:
> so-called "PowerPC" little-endian mode, which works by swizzling the
> bottom 3 bits of the address, and "true" little-endian mode, which
> actually swaps the order of the bytes read from or written to memory.
> The classic 32-bit processors (603, 604, 750, 74xx, and derivatives)
> implemented PowerPC little-endian mode, and I think some early 64-bit
> processors did also. POWER6 and POWER7 implement true little-endian
> mode. POWER4, PPC970 and POWER5 don't implement any little-endian
> mode.
>
> Is anyone actually using little-endian mode processes on processors
> that implement PowerPC little-endian mode? One of the ways that we
> could make the alignment interrupt handler go faster is by removing
> the code for address swizzling that we have in order to handle PowerPC
> little-endian mode. If nobody is actually using it, we should
> remove it and make the code simpler and faster.
I don't know about today, but my recollection is that the only
use of little-endian mode on PowerPC was during the early days
attempt to run Windows-NT.
--
------------------------------------------------------------
Gary Thomas | Consulting for the
MLB Associates | Embedded world
------------------------------------------------------------
^ permalink raw reply
* Re: [PATCH] powerpc: unconditionally enabled irq stacks
From: Michael Ellerman @ 2010-06-03 13:39 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc-dev
In-Reply-To: <20100603082426.GA6110@lst.de>
[-- Attachment #1: Type: text/plain, Size: 617 bytes --]
On Thu, 2010-06-03 at 10:24 +0200, Christoph Hellwig wrote:
> Irq stacks provide an essential protection from stack overflows through
> external interrupts, at the cost of two additionals stacks per CPU.
>
> Enable them unconditionally to simplify the kernel build and prevent
> people from accidentally disabling them.
Since when did we worry about simplifying the kernel build? :)
I'm thinking embedded folks might prefer the reduction in stack space,
though I guess we'll let them speak for themselves. Perhaps it could
depend on EMBEDDED?
It's not like it's a lot of extra code.
cheers
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^ permalink raw reply
* Compilation error: KVM support for PowerPC book3s_64 processors
From: Linux User #330250 @ 2010-06-03 14:10 UTC (permalink / raw)
To: linuxppc-dev
Hello!
My hardware: Apple Power Mac G5 "Late 2005"
I've just compiled kernel 2.6.34 for Gentoo Linux.
# ACCEPT_KEYWORDS=3D"~ppc64" emerge -1 sys-kernel/gentoo-sources-2.6.34
I tried the "KVM support for PowerPC book3s_64 processors" just to see if w=
hat=20
I could do with KVM on my Apple Power Mac G5 with IBM PowerPC 970MP process=
or.=20
Apperently it isn't supported by this CPU. Or am I wrong?
Anyway, I get errors that indicate this option requires some VSX support,=20
which isn't supported by IBM POWER4+/PowerPC G5. I cannot post the complete=
=20
error message right now, but maybe some of you can try it.
Processor support --->
[*] AltiVec Support
[ ] VSX Support
[*] Virtualization --->
<*> KVM support for PowerPC book3s_64 processors
Some maybe relevant .config options:
CONFIG_PPC_BOOK3S_64=3Dy
CONFIG_PPC_BOOK3S=3Dy
CONFIG_POWER4_ONLY=3Dy
CONFIG_POWER4=3Dy
CONFIG_PPC_FPU=3Dy
CONFIG_ALTIVEC=3Dy
=E2=80=A6
CONFIG_PPC_PMAC=3Dy
CONFIG_PPC_PMAC64=3Dy
=E2=80=A6
CONFIG_KVM_MMIO=3Dy
CONFIG_VIRTUALIZATION=3Dy
CONFIG_KVM=3Dy
CONFIG_KVM_BOOK3S_64_HANDLER=3Dy
CONFIG_KVM_BOOK3S_64=3Dy
Maybe I've got something wrong though=E2=80=A6 Or there are other dependenc=
ies, like=20
CONFIG_VSX that are not met.
Let me know if I can help to test something.
Cheers,
Andreas.
^ permalink raw reply
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