* [PATCH v4 00/12] ptp: IEEE 1588 clock support
From: Richard Cochran @ 2010-06-15 16:06 UTC (permalink / raw)
To: netdev; +Cc: devicetree-discuss, linuxppc-dev, linux-arm-kernel,
Krzysztof Halasa
Now and again there has been talk on the netdev list of adding PTP
support into Linux. One part of the picture is already in place, the
SO_TIMESTAMPING API for hardware time stamping. This patch set offers
the missing second part needed for complete IEEE 1588 support.
The only feature still to be implemented is the hook into the PPS
subsystem, to synchronize the Linux clock to the PTP clock.
The first seven patches concern phylib. A new generation of PHYs with
timestamping capabilities is appearing on the market. In order to
support hardware timestamping on these devices in Linux, a number of
adjustments will have to be made in the PHY subsystem. The reasons for
the changes are explained inline at the top of the patches.
The last five patches provide the PTP subsystem itself.
* Why all the CCs?
1. The patches probably should go through netdev.
2. One driver is for PowerPC, and adds device tree stuff.
3. One driver is for the ARM Xscale IXP465
* Open Issues:
** DP83640
In order to make this work, three lines must be added into the MAC
driver. Since this PHY can be connected to almost any MAC, I did
not do anything about that. If you have the DP83640 and want to try
the driver, you need to add three lines to your MAC driver.
1. Before mdio_register, add
bus->locktype = MDIOBUS_ATOMIC_RW;
2. In the .ndo_start_xmit function, add
skb_tx_timestamp()
3. In the NAPI poll function, add
skb_rx_timestamp()
** IXP465
I do not know how to correctly choose the timestamp "channel" based
on the port identifier:
#define PORT2CHANNEL(p) 1
/*
* PHYSICAL_ID(p->id) ?
* TODO - Figure out correct mapping.
*/
* Patch ChangeLog
** v4
*** general
- Added a clock driver for the National Semiconductor PHYTER.
- Added a clock driver for the Intel IXP465.
- Made more stylish according to checkstyle.pl.
*** gianfar
- Replace device_type and model with compatible string ("fsl,etsec-ptp")
- Register only one interrupt, since others are superfluous.
- Combine ptp clock instance with private variable structure.
- ISR now returns NONE or HANDLED properly.
- Print error message if something is missing from the device nodes.
** v3
*** general
- Added documentation on writing clock drivers.
- Added the ioctls for the ancillary clock features.
- Changed wrong subsys_initcall() to module_init() in clock drivers.
- Removed the (too coarse) character device mutex.
- Setting the clock now requires CAP_SYS_TIME.
*** gianfar
- Added alarm feature.
- Added device tree node binding description.
- Added fine grain locking of the clock registers.
- Added the external time stamp feature.
- Added white space for better style.
- Coverted base+offset to structure pointers for register access.
- When removing the driver, we now disable all PTP functions.
** v2
- Changed clock list from a static array into a dynamic list. Also,
use a bitmap to manage the clock's minor numbers.
- Replaced character device semaphore with a mutex.
- Drop .ko from module names in Kbuild help.
- Replace deprecated unifdef-y with header-y for user space header file.
- Added links to both of the ptpd patches on sourceforge.
- Gianfar driver now gets parameters from device tree.
- Added API documentation to Documentation/ptp/ptp.txt
Looking forward to your feedback,
Richard
Richard Cochran (12):
phylib: preserve ifreq parameter when calling generic phy_mii_ioctl()
phylib: do not filter phy_mii_ioctl()
phylib: add a driver method for the SIOCSHWTSTAMP ioctl.
phylib: add a way to make PHY time stamps possible.
phylib: Allow reading and writing a mii bus from atomic context.
ptp: add a BPF to help drivers detect PTP packets.
phylib: support the National Semiconductor DP83640 PHY.
ptp: Added a brand new class driver for ptp clocks.
ptp: Added a clock that uses the Linux system time.
ptp: Added a clock that uses the eTSEC found on the MPC85xx.
ptp: Added a clock driver for the IXP46x.
ptp: Added a clock driver for the National Semiconductor PHYTER.
Documentation/powerpc/dts-bindings/fsl/tsec.txt | 54 ++
Documentation/ptp/ptp.txt | 95 ++++
Documentation/ptp/testptp.c | 269 ++++++++++
Documentation/ptp/testptp.mk | 33 ++
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 67 +++
arch/powerpc/boot/dts/mpc8313erdb.dts | 13 +
arch/powerpc/boot/dts/p2020ds.dts | 13 +
arch/powerpc/boot/dts/p2020rdb.dts | 13 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/net/Makefile | 1 +
drivers/net/arm/ixp4xx_eth.c | 197 ++++++++-
drivers/net/au1000_eth.c | 2 +-
drivers/net/bcm63xx_enet.c | 2 +-
drivers/net/cpmac.c | 5 +-
drivers/net/dnet.c | 2 +-
drivers/net/ethoc.c | 2 +-
drivers/net/fec.c | 2 +-
drivers/net/fec_mpc52xx.c | 2 +-
drivers/net/fs_enet/fs_enet-main.c | 3 +-
drivers/net/gianfar.c | 2 +-
drivers/net/gianfar_ptp.c | 518 ++++++++++++++++++++
drivers/net/gianfar_ptp_reg.h | 113 +++++
drivers/net/macb.c | 2 +-
drivers/net/mv643xx_eth.c | 2 +-
drivers/net/octeon/octeon_mgmt.c | 2 +-
drivers/net/phy/Kconfig | 16 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/dp83640.c | 595 +++++++++++++++++++++++
drivers/net/phy/dp83640_reg.h | 237 +++++++++
drivers/net/phy/mdio_bus.c | 35 ++-
drivers/net/phy/phy.c | 8 +-
drivers/net/sb1250-mac.c | 2 +-
drivers/net/sh_eth.c | 2 +-
drivers/net/smsc911x.c | 2 +-
drivers/net/smsc9420.c | 2 +-
drivers/net/stmmac/stmmac_main.c | 22 +-
drivers/net/tc35815.c | 2 +-
drivers/net/tg3.c | 2 +-
drivers/ptp/Kconfig | 64 +++
drivers/ptp/Makefile | 7 +
drivers/ptp/ptp_clock.c | 514 ++++++++++++++++++++
drivers/ptp/ptp_ixp46x.c | 231 +++++++++
drivers/ptp/ptp_linux.c | 136 ++++++
drivers/staging/octeon/ethernet-mdio.c | 2 +-
include/linux/Kbuild | 1 +
include/linux/phy.h | 22 +-
include/linux/ptp_classify.h | 118 +++++
include/linux/ptp_clock.h | 79 +++
include/linux/ptp_clock_kernel.h | 137 ++++++
include/linux/skbuff.h | 32 ++
kernel/time/ntp.c | 2 +
net/Kconfig | 11 +
net/dsa/slave.c | 3 +-
54 files changed, 3651 insertions(+), 51 deletions(-)
create mode 100644 Documentation/ptp/ptp.txt
create mode 100644 Documentation/ptp/testptp.c
create mode 100644 Documentation/ptp/testptp.mk
create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
create mode 100644 drivers/net/gianfar_ptp.c
create mode 100644 drivers/net/gianfar_ptp_reg.h
create mode 100644 drivers/net/phy/dp83640.c
create mode 100644 drivers/net/phy/dp83640_reg.h
create mode 100644 drivers/ptp/Kconfig
create mode 100644 drivers/ptp/Makefile
create mode 100644 drivers/ptp/ptp_clock.c
create mode 100644 drivers/ptp/ptp_ixp46x.c
create mode 100644 drivers/ptp/ptp_linux.c
create mode 100644 include/linux/ptp_classify.h
create mode 100644 include/linux/ptp_clock.h
create mode 100644 include/linux/ptp_clock_kernel.h
^ permalink raw reply
* [PATCH 2/2 v4] sound/soc: mpc5200_psc_ac97: Use gpio pins for cold reset
From: Eric Millbrandt @ 2010-06-15 16:05 UTC (permalink / raw)
To: Grant Likely; +Cc: Mark Brown, linuxppc-dev, Eric Millbrandt
In-Reply-To: <1276617907-10862-2-git-send-email-emillbrandt@dekaresearch.com>
Call the gpio reset platform function instead of using the flawed
ac97 functionality of the MPC5200(b)
>From MPC5200B User's Manual:
"Some AC97 devices goes to a test mode, if the Sync line is high
during the Res line is low (reset phase). To avoid this behavior the
Sync line must be also forced to zero during the reset phase. To do
that, the pin muxing should switch to GPIO mode and the GPIO control
register should be used to control the output lines."
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
---
changes since v1
- Amended with comments from Mark Brown
- Fall back to the original reset implementation if no gpio pins are define=
d
in the device tree
changes since v2
- Refactored to move the port_config manipulation to platform code.
- Remove the gpio pins from the device-tree
changes since v3
- Remove redundant checks around call to mpc5200_psc_ac97_gpio_reset()
sound/soc/fsl/mpc5200_psc_ac97.c | 22 ++++++++++++++++++----
1 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/sound/soc/fsl/mpc5200_psc_ac97.c b/sound/soc/fsl/mpc5200_psc_a=
c97.c
index e2ee220..e7f5d50 100644
--- a/sound/soc/fsl/mpc5200_psc_ac97.c
+++ b/sound/soc/fsl/mpc5200_psc_ac97.c
@@ -20,6 +20,7 @@
#include <asm/time.h>
#include <asm/delay.h>
+#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>
#include "mpc5200_dma.h"
@@ -100,19 +101,32 @@ static void psc_ac97_warm_reset(struct snd_ac97 *ac97=
)
{
struct mpc52xx_psc __iomem *regs =3D psc_dma->psc_regs;
+ mutex_lock(&psc_dma->mutex);
+
out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR);
udelay(3);
out_be32(®s->sicr, psc_dma->sicr);
+
+ mutex_unlock(&psc_dma->mutex);
}
static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
{
struct mpc52xx_psc __iomem *regs =3D psc_dma->psc_regs;
- /* Do a cold reset */
- out_8(®s->op1, MPC52xx_PSC_OP_RES);
- udelay(10);
- out_8(®s->op0, MPC52xx_PSC_OP_RES);
+ mutex_lock(&psc_dma->mutex);
+ dev_dbg(psc_dma->dev, "cold reset\n");
+
+ mpc5200_psc_ac97_gpio_reset(psc_dma->id);
+
+ /* Notify the PSC that a reset has occurred */
+ out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_ACRB);
+
+ /* Re-enable RX and TX */
+ out_8(®s->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE=
);
+
+ mutex_unlock(&psc_dma->mutex);
+
msleep(1);
psc_ac97_warm_reset(ac97);
}
--
-DISCLAIMER: an automatically appended disclaimer may follow. By posting-
-to a public e-mail mailing list I hereby grant permission to distribute-
-and copy this message.-
1.6.3.1
This e-mail and the information, including any attachments, it contains are=
intended to be a confidential communication only to the person or entity t=
o whom it is addressed and may contain information that is privileged. If t=
he reader of this message is not the intended recipient, you are hereby not=
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* [PATCH 1/2 v3] powerpc/5200: add mpc5200_psc_ac97_gpio_reset
From: Eric Millbrandt @ 2010-06-15 16:05 UTC (permalink / raw)
To: Grant Likely; +Cc: Mark Brown, linuxppc-dev, Eric Millbrandt
In-Reply-To: <1276617907-10862-1-git-send-email-emillbrandt@dekaresearch.com>
Work around a silicon bug in the ac97 reset functionality of the
mpc5200(b). The implementation of the ac97 "cold" reset is flawed.
If the sync and output lines are high when reset is asserted the
attached ac97 device may go into test mode. Avoid this by
reconfiguring the psc to gpio mode and generating the reset manually.
>From MPC5200B User's Manual:
"Some AC97 devices goes to a test mode, if the Sync line is high
during the Res line is low (reset phase). To avoid this behavior the
Sync line must be also forced to zero during the reset phase. To do
that, the pin muxing should switch to GPIO mode and the GPIO control
register should be used to control the output lines."
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
---
changes since v1
- Refactored to manipulate port_config and gpio pins internally instead of
exporting an API.
changes since v2
- Factored out gpiolib calls, write to the gpio registers directly
arch/powerpc/include/asm/mpc52xx.h | 1 +
arch/powerpc/include/asm/mpc52xx_psc.h | 1 +
arch/powerpc/platforms/52xx/mpc52xx_common.c | 113 ++++++++++++++++++++++=
++++
3 files changed, 115 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/=
mpc52xx.h
index b664ce7..1f41382 100644
--- a/arch/powerpc/include/asm/mpc52xx.h
+++ b/arch/powerpc/include/asm/mpc52xx.h
@@ -271,6 +271,7 @@ struct mpc52xx_intr {
/* mpc52xx_common.c */
extern void mpc5200_setup_xlb_arbiter(void);
extern void mpc52xx_declare_of_platform_devices(void);
+extern int mpc5200_psc_ac97_gpio_reset(int psc_number);
extern void mpc52xx_map_common_devices(void);
extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/=
asm/mpc52xx_psc.h
index ecc4fc6..2966df6 100644
--- a/arch/powerpc/include/asm/mpc52xx_psc.h
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -131,6 +131,7 @@
#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
+#define MPC52xx_PSC_SICR_ACRB (0x8 << 24)
#define MPC52xx_PSC_SICR_AWR (1 << 30)
#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
#define MPC52xx_PSC_SICR_I2S (1 << 22)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/pl=
atforms/52xx/mpc52xx_common.c
index a46bad0..116d461 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -12,9 +12,11 @@
#undef DEBUG
+#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/mpc52xx.h>
@@ -82,6 +84,14 @@ mpc5200_setup_xlb_arbiter(void)
iounmap(xlb);
}
+/*
+ * This variable is mapped in mpc52xx_map_common_devices and
+ * used in mpc5200_psc_ac97_gpio_reset().
+ */
+static DEFINE_SPINLOCK(gpio_lock);
+struct mpc52xx_gpio __iomem *simple_gpio;
+struct mpc52xx_gpio_wkup __iomem *wkup_gpio;
+
/**
* mpc52xx_declare_of_platform_devices: register internal devices and chil=
dren
* of the localplus bus to the of_plat=
form
@@ -109,6 +119,19 @@ static struct of_device_id mpc52xx_cdm_ids[] __initdat=
a =3D {
{ .compatible =3D "mpc5200-cdm", }, /* old */
{}
};
+static const struct of_device_id mpc52xx_gpio_simple[] =3D {
+ {
+ .compatible =3D "fsl,mpc5200-gpio",
+ },
+ {}
+};
+static const struct of_device_id mpc52xx_gpio_wkup[] =3D {
+ {
+ .compatible =3D "fsl,mpc5200-gpio-wkup",
+ },
+ {}
+};
+
/**
* mpc52xx_map_common_devices: iomap devices required by common code
@@ -135,6 +158,16 @@ mpc52xx_map_common_devices(void)
np =3D of_find_matching_node(NULL, mpc52xx_cdm_ids);
mpc52xx_cdm =3D of_iomap(np, 0);
of_node_put(np);
+
+ /* simple_gpio registers */
+ np =3D of_find_matching_node(NULL, mpc52xx_gpio_simple);
+ simple_gpio =3D of_iomap(np, 0);
+ of_node_put(np);
+
+ /* wkup_gpio registers */
+ np =3D of_find_matching_node(NULL, mpc52xx_gpio_wkup);
+ wkup_gpio =3D of_iomap(np, 0);
+ of_node_put(np);
}
/**
@@ -233,3 +266,83 @@ mpc52xx_restart(char *cmd)
while (1);
}
+
+#define PSC1_RESET 0x1
+#define PSC1_SYNC 0x4
+#define PSC1_SDATA_OUT 0x1
+#define PSC2_RESET 0x2
+#define PSC2_SYNC (0x4<<4)
+#define PSC2_SDATA_OUT (0x1<<4)
+#define MPC52xx_GPIO_PSC1_MASK 0x7
+#define MPC52xx_GPIO_PSC2_MASK (0x7<<4)
+
+/**
+ * mpc5200_psc_ac97_gpio_reset: Use gpio pins to reset the ac97 bus
+ *
+ * @psc: psc number to reset (only psc 1 and 2 support ac97)
+ */
+int mpc5200_psc_ac97_gpio_reset(int psc_number)
+{
+ unsigned long flags;
+ u32 gpio;
+ u32 mux;
+ int out;
+ int reset;
+ int sync;
+
+ if ((!simple_gpio) || (!wkup_gpio))
+ return -ENODEV;
+
+ switch (psc_number) {
+ case 0:
+ reset =3D PSC1_RESET; /* AC97_1_RES */
+ sync =3D PSC1_SYNC; /* AC97_1_SYNC */
+ out =3D PSC1_SDATA_OUT; /* AC97_1_SDATA_OUT */
+ gpio =3D MPC52xx_GPIO_PSC1_MASK;
+ break;
+ case 1:
+ reset =3D PSC2_RESET; /* AC97_2_RES */
+ sync =3D PSC2_SYNC; /* AC97_2_SYNC */
+ out =3D PSC2_SDATA_OUT; /* AC97_2_SDATA_OUT */
+ gpio =3D MPC52xx_GPIO_PSC2_MASK;
+ break;
+ default:
+ printk(KERN_ERR __FILE__ ": "
+ "Unable to determine PSC, no ac97 cold-reset will be =
"
+ "performed\n");
+ return -ENODEV;
+ }
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
+ mux =3D in_be32(&simple_gpio->port_config);
+
+ /* Reconfiure pin-muxing to gpio */
+ out_be32(&simple_gpio->port_config, mux & (~gpio));
+
+ /* enable gpio pins for output */
+ setbits8(&wkup_gpio->wkup_gpioe, reset);
+ setbits32(&simple_gpio->simple_gpioe, sync | out);
+
+ setbits8(&wkup_gpio->wkup_ddr, reset);
+ setbits32(&simple_gpio->simple_ddr, sync | out);
+
+ /* Assert cold reset */
+ setbits32(&simple_gpio->simple_dvo, sync | out);
+ setbits8(&wkup_gpio->wkup_dvo, reset);
+
+ /* wait at lease 1 us */
+ udelay(2);
+
+ /* Deassert reset */
+ clrbits8(&wkup_gpio->wkup_dvo, reset);
+ clrbits32(&simple_gpio->simple_dvo, sync | out);
+
+ /* Restore pin-muxing */
+ out_be32(&simple_gpio->port_config, mux);
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL(mpc5200_psc_ac97_gpio_reset);
--
-DISCLAIMER: an automatically appended disclaimer may follow. By posting-
-to a public e-mail mailing list I hereby grant permission to distribute-
-and copy this message.-
1.6.3.1
This e-mail and the information, including any attachments, it contains are=
intended to be a confidential communication only to the person or entity t=
o whom it is addressed and may contain information that is privileged. If t=
he reader of this message is not the intended recipient, you are hereby not=
ified that any dissemination, distribution or copying of this communication=
is strictly prohibited. If you have received this communication in error, =
please immediately notify the sender and destroy the original message.
Thank you.
Please consider the environment before printing this email.
^ permalink raw reply related
* [PATCH 0/2 v3] mpc5200 ac97 gpio reset
From: Eric Millbrandt @ 2010-06-15 16:05 UTC (permalink / raw)
To: Grant Likely; +Cc: Mark Brown, linuxppc-dev
These patches reimplement the reset fuction in the ac97 to use gpio pins
instead of using the mpc5200 ac97 reset functionality in the psc. This
avoids a problem in which attached ac97 devices go into "test" mode appear
unresponsive.
These patches were tested on a pcm030 baseboard and on custom hardware with
a wm9715 audio codec/touchscreen controller.
Eric Millbrandt
---
changes since v1
- Refactored to manipulate port_config and gpio pins internally instead of
exporting an API.
- Amended commit message with comments from Mark Brown
- Refactored to move the port_config manipulation to platform code.
- Remove the gpio pins from the device-tree
changes since v2
- Factored out gpiolib calls, write to the gpio registers directly
- Remove redundant checks around call to mpc5200_psc_ac97_gpio_reset()
Eric Millbrandt (2):
powerpc/5200: add mpc5200_psc_ac97_gpio_reset
sound/soc: mpc5200_psc_ac97: Use gpio pins for cold reset
arch/powerpc/include/asm/mpc52xx.h | 1 +
arch/powerpc/include/asm/mpc52xx_psc.h | 1 +
arch/powerpc/platforms/52xx/mpc52xx_common.c | 113 ++++++++++++++++++++++=
++++
sound/soc/fsl/mpc5200_psc_ac97.c | 22 ++++-
4 files changed, 133 insertions(+), 4 deletions(-)
-DISCLAIMER: an automatically appended disclaimer may follow. By posting-
-to a public e-mail mailing list I hereby grant permission to distribute-
-and copy this message.-
This e-mail and the information, including any attachments, it contains are=
intended to be a confidential communication only to the person or entity t=
o whom it is addressed and may contain information that is privileged. If t=
he reader of this message is not the intended recipient, you are hereby not=
ified that any dissemination, distribution or copying of this communication=
is strictly prohibited. If you have received this communication in error, =
please immediately notify the sender and destroy the original message.
Thank you.
Please consider the environment before printing this email.
^ permalink raw reply
* [PATCH 2/2] ehea: Fix kernel deadlock in DLPAR-mem processing
From: Jan-Bernd Themann @ 2010-06-15 15:35 UTC (permalink / raw)
To: David Miller
Cc: themann, netdev, linux-kernel, linuxppc-dev, tklein, Andre Detsch
Port reset operations and memory add/remove operations need to
be serialized to avoid a kernel deadlock. The deadlock is caused
by calling the napi_disable() function twice.
Therefore we have to employ the dlpar_mem_lock in the ehea_reset_port
function as well
Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com>
---
created against kernel-2.6.35-rc3
drivers/net/ehea/ehea.h | 2 +-
drivers/net/ehea/ehea_main.c | 8 +++-----
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ehea/ehea.h b/drivers/net/ehea/ehea.h
index 0630980..0060e42 100644
--- a/drivers/net/ehea/ehea.h
+++ b/drivers/net/ehea/ehea.h
@@ -40,7 +40,7 @@
#include <asm/io.h>
#define DRV_NAME "ehea"
-#define DRV_VERSION "EHEA_0103"
+#define DRV_VERSION "EHEA_0105"
/* eHEA capability flags */
#define DLPAR_PORT_ADD_REM 1
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index fd890fa..8b92acb 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -2860,6 +2860,7 @@ static void ehea_reset_port(struct work_struct *work)
container_of(work, struct ehea_port, reset_task);
struct net_device *dev = port->netdev;
+ mutex_lock(&dlpar_mem_lock);
port->resets++;
mutex_lock(&port->port_lock);
netif_stop_queue(dev);
@@ -2882,6 +2883,7 @@ static void ehea_reset_port(struct work_struct *work)
netif_wake_queue(dev);
out:
mutex_unlock(&port->port_lock);
+ mutex_unlock(&dlpar_mem_lock);
}
static void ehea_rereg_mrs(struct work_struct *work)
@@ -3543,10 +3545,7 @@ static int ehea_mem_notifier(struct notifier_block *nb,
int ret = NOTIFY_BAD;
struct memory_notify *arg = data;
- if (!mutex_trylock(&dlpar_mem_lock)) {
- ehea_info("ehea_mem_notifier must not be called parallelized");
- goto out;
- }
+ mutex_lock(&dlpar_mem_lock);
switch (action) {
case MEM_CANCEL_OFFLINE:
@@ -3575,7 +3574,6 @@ static int ehea_mem_notifier(struct notifier_block *nb,
out_unlock:
mutex_unlock(&dlpar_mem_lock);
-out:
return ret;
}
--
1.7.0
^ permalink raw reply related
* [PATCH 1/2] ehea: fix delayed packet processing
From: Jan-Bernd Themann @ 2010-06-15 15:35 UTC (permalink / raw)
To: David Miller
Cc: themann, netdev, linux-kernel, linuxppc-dev, tklein, Andre Detsch
In the eHEA poll function an rmb() is required. Without that some packets
on the receive queue are not seen and thus delayed until the next interrupt
is handled for the same receive queue.
Signed-off-by: Jan-Bernd Themann <themann@de.ibm.com>
---
Patch created against 2.6.35-rc3
drivers/net/ehea/ehea_main.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index f547894..fd890fa 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -867,6 +867,7 @@ static int ehea_poll(struct napi_struct *napi, int budget)
ehea_reset_cq_ep(pr->send_cq);
ehea_reset_cq_n1(pr->recv_cq);
ehea_reset_cq_n1(pr->send_cq);
+ rmb();
cqe = ehea_poll_rq1(pr->qp, &wqe_index);
cqe_skb = ehea_poll_cq(pr->send_cq);
--
1.7.0
^ permalink raw reply related
* Re:Re: PCIe bus seems work while 'dma' can't under linux
From: jxnuxdy @ 2010-06-15 7:05 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Michal Simek, Stephen Rothwell, devicetree-discuss,
microblaze-uclinux
In-Reply-To: <1276240884.1962.132.camel@pasglop>
[-- Attachment #1: Type: text/plain, Size: 6349 bytes --]
Thanks Benjamin, the regions don't display as what we expect, that's why we suspect if there any configuration probelms in CPU host bridge, but we changed the uboot/linux a lot, seems take no effect on that problems.
We use CPU MPC8544, and connect two PCIE devices to CPU PCIE1 and PCIE2 directly without a extended PCIE bridge, so we disabled PCIE3 and PCI controlers in uboot level.
More settings pls take a look at the attach file log.txt.
Many thanks,
Denny
----------------------------------------------------------------------------------------------------------------------------
在2010-06-11 15:21:24，"Benjamin Herrenschmidt" <benh@kernel.crashing.org> 写道：
>On Fri, 2010-06-11 at 09:30 +0800, jxnuxdy wrote:
>> Hi guys,
>>
>> I encountered a PCIe problem under linux, the two PCIe bus on my board seems work,
>> at least I can access the registers through the PCIe bus, however the dma for the
>> PCIe bus can't work, so I just dumped the pci device, but I am curiously to find
>> there is no regions displayed on PCIe controlers, why? is it relate with my 'dma' issue then?
>
>It would help if you told us a bit more what the HW is, what you are
>doing with it, etc...
>
>IE. What is your host, what is your device, what platform, etc...
>
>DMA should work provided that your platform code sets it up properly.
>The DMA regions don't appear in /proc/pci or lspci.
>
>Cheers,
>Ben.
>
>>
>> bash-2.04# cat /proc/pci
>> PCI devices found:
>> Bus 0, device 0, function 0:
>> Class 0b20 Header Type 01: PCI device 1957:0032 (rev 17).
>> Bus 1, device 0, function 0:
>> Class 0580 Header Type 00: PCI device 11ab:db90 (rev 1).
>> Prefetchable 64 bit memory at 0x80000000 [0x800fffff].
>> Prefetchable 64 bit memory at 0x84000000 [0x87ffffff].
>> Bus 9, device 0, function 0:
>> Class 0b20 Header Type 01: PCI device 1957:0032 (rev 17).
>> Bus 10, device 0, function 0:
>> Class 0580 Header Type 00: PCI device 11ab:db90 (rev 1).
>> Prefetchable 64 bit memory at 0xa0000000 [0xa00fffff].
>> Prefetchable 64 bit memory at 0xa4000000 [0xa7ffffff].
>> bash-2.04# lspci -vv
>> 00:00.0 Power PC: Unknown device 1957:0032 (rev 11)
>> !!! Invalid class 0b20 for header type 01
>> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
>> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
>> Latency: 0, cache line size 08
>> Bus: primary=00, secondary=01, subordinate=06, sec-latency=0
>> I/O behind bridge: 00000000-00000fff
>> Memory behind bridge: 80000000-9fffffff
>> BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
>> Capabilities: [44] Power Management version 2
>> Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
>> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
>> Capabilities: [4c] #10 [0041]
>>
>> 01:00.0 Memory controller: Galileo Technology Ltd.: Unknown device db90 (rev 01)
>> Subsystem: Galileo Technology Ltd.: Unknown device 11ab
>> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
>> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
>> Latency: 0, cache line size 08
>> Interrupt: pin A routed to IRQ 0
>> Region 0: Memory at 80000000 (64-bit, prefetchable) [size=1M]
>> Region 2: Memory at 84000000 (64-bit, prefetchable) [size=64M]
>> Capabilities: [40] Power Management version 2
>> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
>> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
>> Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
>> Address: 0000000000000000 Data: 0000
>> Capabilities: [60] #10 [0011]
>>
>> 09:00.0 Power PC: Unknown device 1957:0032 (rev 11)
>> !!! Invalid class 0b20 for header type 01
>> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
>> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
>> Latency: 0, cache line size 08
>> Bus: primary=00, secondary=0a, subordinate=0f, sec-latency=0
>> I/O behind bridge: 00000000-00000fff
>> Memory behind bridge: a0000000-bfffffff
>> BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
>> Capabilities: [44] Power Management version 2
>> Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
>> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
>> Capabilities: [4c] #10 [0041]
>>
>> 0a:00.0 Memory controller: Galileo Technology Ltd.: Unknown device db90 (rev 01)
>> Subsystem: Galileo Technology Ltd.: Unknown device 11ab
>> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
>> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
>> Latency: 0, cache line size 08
>> Interrupt: pin A routed to IRQ 0
>> Region 0: Memory at a0000000 (64-bit, prefetchable) [size=1M]
>> Region 2: Memory at a4000000 (64-bit, prefetchable) [size=64M]
>> Capabilities: [40] Power Management version 2
>> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
>> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
>> Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
>> Address: 0000000000000000 Data: 0000
>> Capabilities: [60] #10 [0011]
>>
>> bash-2.04#
>>
>> Thanks
>> Denny
>>
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@lists.ozlabs.org
>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
>
>_______________________________________________
>Linuxppc-dev mailing list
>Linuxppc-dev@lists.ozlabs.org
>https://lists.ozlabs.org/listinfo/linuxppc-dev
[-- Attachment #2: log.txt --]
[-- Type: text/plain, Size: 63314 bytes --]
U-Boot 1.1.3 (Jun 14 2010 - 19:26:53)
CPU: 8544_E, Version: 1.1, (0x803c0111)
Core: E500, Version: 2.2, (0x80210022)
Clock Configuration:
CPU: 800 MHz, CCB: 400 MHz,
DDR: 200 MHz, LBC: 50 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: C48
CPU Board Revision 0.0 (0x0000)
PCI2: disabled
I2C: ready
DRAM: Initializing DDRSDRAM
memsize = 200
DDR: 512 MB
POST RAM test disabled.
Now running in RAM - U-Boot at: 1fb7c000
trap_init : 0x0
system inventory subsystem initialized
FLASH: 64 MB
L2 cache 256KB: enabled
PCI:
Scanning PCI bus 00
01 00 11ab db90 0580 00
Scanning PCI bus 02
03 00 11ab db90 0580 00
In: serial
Out: serial
Err: serial
Net:
ENET0: PHY is Marvell 88E1112 (1410c97)
set_bootstatus: BS_LOAD_OS, platform_idx = 11
Hit ESC to stop autoboot: 0
## Booting image at fb400000 ...
Image Name: Linux-2.6.14.2
Image Type: PowerPC Linux Multi-File Image (gzip compressed)
Data Size: 2506379 Bytes = 2.4 MB
Load Address: 00000000
Entry Point: 00000000
Contents:
Image 0: 1429862 Bytes = 1.4 MB
Image 1: 1076503 Bytes = 1 MB
Uncompressing Multi-File Image ... ## Current stack ends at 0x1FB5ABD0 => set upper limit to 0x00800000
## initrd at 0xFB55D1B4 ... 0xFB663ECA (len=1076503=0x106D17)
Loading Ramdisk to 1fa53000, end 1fb59d17 ... OK
initrd_start = 1fa53000, initrd_end = 1fb59d17
## Transferring control to Linux (at address 00000000) ...
Memory CAM mapping: CAM0=256Mb, CAM1=256Mb, CAM2=0Mb residual: 0Mb
tlbcam_index=2
Linux version 2.6.14.2 (dxiao@blc-10-6) (gcc version 3.4.6) #25 Fri Jun 11 17:59:39 PDT 2010
silkworm85xx_setup_arch
mpc85xx_setup: Doing Pcie bridge setup
Scanning PcieBus...
cpld_init: platform (101) not supported
Brocade Silkworm port (C) 2006 Brocade Communications Systems, Inc.
DMA zone: 131072 pages, LIFO batch:31
Normal zone: 0 pages, LIFO batch:1
HighMem zone: 0 pages, LIFO batch:1
Built 1 zonelists
Kernel command line: ip=off console=ttyS1,9600 noinitrd rootfstype=jffs2 root=/dev/mtdblock1 rw
OpenPIC Version 1.2 (1 CPUs and 60 IRQ sources) at fafb9000
PID hash table entries: 4096 (order: 12, 65536 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 514944k available (2280k kernel code, 668k data, 144k init, 0k highmem)
Mount-cache hash table entries: 512
checking if image is initramfs...it isn't (no cpio magic); looks like an initrd
Freeing initrd memory: 1051k freed
softlockup thread 0 started up.
NET: Registered protocol family 16
PCI:: Probing PCI hardware
PCI: 0000:00:00.0: class b20 doesn't match header type 01. Ignoring class.
PCI: 0001:02:00.0: class b20 doesn't match header type 01. Ignoring class.
Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc.
Initializing Cryptographic API
Generic RTC Driver v1.07
SWBD Platform Driver v1.0: [type 101, rev 2].
Config Silkworm
PowerPC Book-E Watchdog Timer Loaded
Serial: 8250/16550 driver $Revision: 1.90 $ 2 ports, IRQ sharing disabled
ttyS0 at MMIO 0xe0004600 (irq = 26) is a 16550A
ttyS1 at MMIO 0xe0004500 (irq = 26) is a 16550A
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
loop: loaded (max 8 devices)
eth0: Gianfar Ethernet Controller Version 1.1, 00:e0:0c:00:00:fd
eth0: Running with NAPI enabled
eth0: 256/256 RX/TX BD ring size
mtdchar: write-caching enabled
silkworm: Using SWBD101 flash configuration
Boot flash: Found 1 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
Boot flash: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
Creating 6 MTD partitions on "Boot flash":
0x00000000-0x00800000 : "unused (mtd0)"
0x00800000-0x03400000 : "filesys: kernel and initrd (mtd1)"
0x03400000-0x03c00000 : "kernel: kernel and initrd (mtd2)"
0x03c00000-0x03c40000 : "bootenv0: boot environment (mtd3)"
0x03c40000-0x03c80000 : "bootenv1: boot environment (mtd4)"
0x03c80000-0x04000000 : "bootimage (mtd5)"
i2c /dev entries driver
MPC adapter: Platform type [101], Did not register I2C multiplexor callback.
MPC adapter: Platform type [101], Did not register I2C multiplexor callback.
NET: Registered protocol family 2
IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
TCP established hash table entries: 131072 (order: 7, 524288 bytes)
TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
TCP: Hash tables configured (established 131072 bind 65536)
TCP reno registered
ip_conntrack version 2.3 (4096 buckets, 32768 max) - 216 bytes per conntrack
ip_tables: (C) 2000-2002 Netfilter core team
arp_tables: (C) 2002 David S. Miller
TCP bic registered
Initializing IPsec netlink socket
NET: Registered protocol family 1
NET: Registered protocol family 10
IPv6 over IPv4 tunneling driver
ip6_tables: (C) 2000-2002 Netfilter core team
NET: Registered protocol family 17
NET: Registered protocol family 15
VFS: Mounted root (jffs2 filesystem).
Freeing unused kernel memory: 144k init
INIT: version 2.78 booting
INIT: Entering runlevel: 2
Installing dpci dpci_switch_module: module license 'unspecified' taints kernel.
switch module
Installing dgen module
eth0: PHY is Generic MII (ffffffff)
/etc/rc.d/rc2.d/S30diags: /nfabos/bin/diagburnin.sh: No such file or directory
bash-2.04# eth0: Full Duplex
eth0: Speed 100BT
eth0: Link is up
bash-2.04# nfdiag
SWBD: modelId 0x0 extId 0x4e
CHOW48 platform.
slot: 0, bus: 1, dev: 0, size: 4194304, vAddr = 0x0, dmaAddr = 0x0 pciFd 0x4
DMA CPU Address 0xdf000000 PCI Address 0x9f000000 for slot 0 cheetah3 0
slot: 0, bus: 3, dev: 0, size: 4194304, vAddr = 0x0, dmaAddr = 0x0 pciFd 0x4
DMA CPU Address 0xdec00000 PCI Address 0x9ec00000 for slot 0 cheetah3 1
main (lc0)> pci -o read -s 0 -b 0 -u 0 -a 0 -l 0x128
00 BusNo 0 DevNo 0
00000000 1957 0032 0006 0010 0011 0b20 0008 0001 .W.2............
00000010 0000 0000 0000 0000 0100 0006 0000 0000 ................
00000020 8000 9ff0 1001 0001 0000 0000 0000 0000 ................
00000030 0000 0000 0044 0000 0000 0000 0000 0000 .....D..........
00000040 0000 0000 4c01 fe02 0000 0000 0010 0041 ....L..........A
00000050 0001 0000 2810 0000 d481 0003 0008 0011 ....(...........
00000060 07c0 0000 03c0 0040 0000 0000 0000 0000 .......@........
00000070 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000080 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000090 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000100 0001 0001 0000 0000 0000 0000 2010 0006 ................
00000110 0000 0000 0000 0000 00a0 0000 0000 0000 ................
00000120 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000130 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000140 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000150 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000160 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000170 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000180 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000190 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000200 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000210 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000220 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000230 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000240 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000250 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000260 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000270 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000280 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000290 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000300 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000310 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000320 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000330 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000340 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000350 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000360 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000370 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000380 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000390 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000400 0000 0000 0016 0000 04e2 0000 0000 0000 ................
00000410 0004 0000 0001 0000 0000 0000 4040 0000 ............@@..
00000420 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000430 0000 0000 0000 0000 8121 009e b04c 0004 .........!...L..
00000440 0010 0000 0000 0000 0000 0000 0000 0000 ................
00000450 d7ce 0014 1e20 01fc 0000 0000 0c5c 0000 .............\..
00000460 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000470 1957 0032 0011 0b20 0000 0000 0001 0000 .W.2............
00000480 3d48 0000 0000 0000 07f0 0000 0000 0000 =H..............
00000490 07c0 0000 0000 0000 0000 0000 0000 0000 ................
main (lc0)> pci -o read -u 0 -s 0 -b 1 -a 0x0 -l 0xff
00 BusNo 1 DevNo 0
00000000 11ab db90 0006 0010 0001 0580 0008 0000 ................
00000010 000c 8000 0000 0000 000c 8400 0000 0000 ................
00000020 0000 0000 0000 0000 0000 0000 11ab 11ab ................
00000030 0000 0000 0040 0000 0000 0000 0100 0000 .....@..........
00000040 5001 0002 0000 0000 0000 0000 0000 0000 P...............
00000050 6005 0080 0000 0000 0000 0000 0000 0000 `...............
00000060 0010 0011 0080 003c 2000 0000 a411 0003 .......<........
00000070 0008 1011 0000 0000 0000 0000 0000 0000 ................
00000080 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000090 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000100 0001 0001 0000 0000 0000 0000 0010 0006 ................
00000110 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000120 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000130 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000140 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000150 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000160 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000170 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000180 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000190 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000001F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000200 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000210 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000220 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000230 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000240 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000250 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000260 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000270 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000280 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000290 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000002F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000300 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000310 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000320 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000330 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000340 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000350 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000360 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000370 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000380 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000390 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000003F0 0000 0000 0000 0000 0000 0000
main (lc0)> pci -o read -s 0 -u 0 -a 0x0 -b 2 -l 0x40
00 BusNo 2 DevNo 0
00000000 1957 0032 0006 0010 0011 0b20 0008 0001 .W.2............
00000010 0000 0000 0000 0000 0300 000f 0000 0000 ................
00000020 a000 bff0 1001 0001 0000 0000 0000 0000 ................
00000030 0000 0000 0044 0000 0000 0000 0000 0000 .....D..........
00000040 0000 0000 4c01 fe02 0000 0000 0010 0041 ....L..........A
00000050 0001 0000 2810 0000 d481 0003 0008 0011 ....(...........
00000060 07c0 0000 03c0 0040 0000 0000 0000 0000 .......@........
00000070 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000080 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000090 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
main (lc0)> pci -o read -s 0 -u 0 -a 0x0 -b 3 -l 0x40
00 BusNo 3 DevNo 0
00000000 11ab db90 0006 0010 0001 0580 0008 0000 ................
00000010 000c a000 0000 0000 000c a400 0000 0000 ................
00000020 0000 0000 0000 0000 0000 0000 11ab 11ab ................
00000030 0000 0000 0040 0000 0000 0000 0100 0000 .....@..........
00000040 5001 0002 0000 0000 0000 0000 0000 0000 P...............
00000050 6005 0080 0000 0000 0000 0000 0000 0000 `...............
00000060 0010 0011 0080 003c 2000 0000 a411 0003 .......<........
00000070 0008 1011 0000 0000 0000 0000 0000 0000 ................
00000080 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000090 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000A0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000B0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000C0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000D0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000E0 0000 0000 0000 0000 0000 0000 0000 0000 ................
000000F0 0000 0000 0000 0000 0000 0000 0000 0000 ................
main (lc0)> mem -o read -a 0xe000a000 -l 0x400
E000A000 $830100f8 $00000000 $00000000 $0010ffff ................
E000A010 $0400ffff $00000028 $00000000 $00000000 .......(........
E000A020 $00000000 $00000000 $00000000 $00000000 ................
E000A030 $00000000 $00000000 $00000000 $00000000 ................
E000A040 $00000000 $00000000 $00000000 $00000000 ................
E000A050 $00000000 $00000000 $00000000 $00000000 ................
E000A060 $00000000 $00000000 $00000000 $00000000 ................
E000A070 $00000000 $00000000 $00000000 $00000000 ................
E000A080 $00000000 $00000000 $00000000 $00000000 ................
E000A090 $00000000 $00000000 $00000000 $00000000 ................
E000A0A0 $00000000 $00000000 $00000000 $00000000 ................
E000A0B0 $00000000 $00000000 $00000000 $00000000 ................
E000A0C0 $00000000 $00000000 $00000000 $00000000 ................
E000A0D0 $00000000 $00000000 $00000000 $00000000 ................
E000A0E0 $00000000 $00000000 $00000000 $00000000 ................
E000A0F0 $00000000 $00000000 $00000000 $00000000 ................
E000A100 $00000000 $00000000 $00000000 $00000000 ................
E000A110 $00000000 $00000000 $00000000 $00000000 ................
E000A120 $00000000 $00000000 $00000000 $00000000 ................
E000A130 $00000000 $00000000 $00000000 $00000000 ................
E000A140 $00000000 $00000000 $00000000 $00000000 ................
E000A150 $00000000 $00000000 $00000000 $00000000 ................
E000A160 $00000000 $00000000 $00000000 $00000000 ................
E000A170 $00000000 $00000000 $00000000 $00000000 ................
E000A180 $00000000 $00000000 $00000000 $00000000 ................
E000A190 $00000000 $00000000 $00000000 $00000000 ................
E000A1A0 $00000000 $00000000 $00000000 $00000000 ................
E000A1B0 $00000000 $00000000 $00000000 $00000000 ................
E000A1C0 $00000000 $00000000 $00000000 $00000000 ................
E000A1D0 $00000000 $00000000 $00000000 $00000000 ................
E000A1E0 $00000000 $00000000 $00000000 $00000000 ................
E000A1F0 $00000000 $00000000 $00000000 $00000000 ................
E000A200 $00000000 $00000000 $00000000 $00000000 ................
E000A210 $00000000 $00000000 $00000000 $00000000 ................
E000A220 $00000000 $00000000 $00000000 $00000000 ................
E000A230 $00000000 $00000000 $00000000 $00000000 ................
E000A240 $00000000 $00000000 $00000000 $00000000 ................
E000A250 $00000000 $00000000 $00000000 $00000000 ................
E000A260 $00000000 $00000000 $00000000 $00000000 ................
E000A270 $00000000 $00000000 $00000000 $00000000 ................
E000A280 $00000000 $00000000 $00000000 $00000000 ................
E000A290 $00000000 $00000000 $00000000 $00000000 ................
E000A2A0 $00000000 $00000000 $00000000 $00000000 ................
E000A2B0 $00000000 $00000000 $00000000 $00000000 ................
E000A2C0 $00000000 $00000000 $00000000 $00000000 ................
E000A2D0 $00000000 $00000000 $00000000 $00000000 ................
E000A2E0 $00000000 $00000000 $00000000 $00000000 ................
E000A2F0 $00000000 $00000000 $00000000 $00000000 ................
E000A300 $00000000 $00000000 $00000000 $00000000 ................
E000A310 $00000000 $00000000 $00000000 $00000000 ................
E000A320 $00000000 $00000000 $00000000 $00000000 ................
E000A330 $00000000 $00000000 $00000000 $00000000 ................
E000A340 $00000000 $00000000 $00000000 $00000000 ................
E000A350 $00000000 $00000000 $00000000 $00000000 ................
E000A360 $00000000 $00000000 $00000000 $00000000 ................
E000A370 $00000000 $00000000 $00000000 $00000000 ................
E000A380 $00000000 $00000000 $00000000 $00000000 ................
E000A390 $00000000 $00000000 $00000000 $00000000 ................
E000A3A0 $00000000 $00000000 $00000000 $00000000 ................
E000A3B0 $00000000 $00000000 $00000000 $00000000 ................
E000A3C0 $00000000 $00000000 $00000000 $00000000 ................
E000A3D0 $00000000 $00000000 $00000000 $00000000 ................
E000A3E0 $00000000 $00000000 $00000000 $00000000 ................
E000A3F0 $00000000 $00000000 $00000000 $00000000 ................
E000A400 $00000000 $00000000 $00000000 $00000000 ................
E000A410 $00000000 $00000000 $00000000 $00000000 ................
E000A420 $00000000 $00000000 $00000000 $00000000 ................
E000A430 $00000000 $00000000 $00000000 $00000000 ................
E000A440 $00000000 $00000000 $00000000 $00000000 ................
E000A450 $00000000 $00000000 $00000000 $00000000 ................
E000A460 $00000000 $00000000 $00000000 $00000000 ................
E000A470 $00000000 $00000000 $00000000 $00000000 ................
E000A480 $00000000 $00000000 $00000000 $00000000 ................
E000A490 $00000000 $00000000 $00000000 $00000000 ................
E000A4A0 $00000000 $00000000 $00000000 $00000000 ................
E000A4B0 $00000000 $00000000 $00000000 $00000000 ................
E000A4C0 $00000000 $00000000 $00000000 $00000000 ................
E000A4D0 $00000000 $00000000 $00000000 $00000000 ................
E000A4E0 $00000000 $00000000 $00000000 $00000000 ................
E000A4F0 $00000000 $00000000 $00000000 $00000000 ................
E000A500 $00000000 $00000000 $00000000 $00000000 ................
E000A510 $00000000 $00000000 $00000000 $00000000 ................
E000A520 $00000000 $00000000 $00000000 $00000000 ................
E000A530 $00000000 $00000000 $00000000 $00000000 ................
E000A540 $00000000 $00000000 $00000000 $00000000 ................
E000A550 $00000000 $00000000 $00000000 $00000000 ................
E000A560 $00000000 $00000000 $00000000 $00000000 ................
E000A570 $00000000 $00000000 $00000000 $00000000 ................
E000A580 $00000000 $00000000 $00000000 $00000000 ................
E000A590 $00000000 $00000000 $00000000 $00000000 ................
E000A5A0 $00000000 $00000000 $00000000 $00000000 ................
E000A5B0 $00000000 $00000000 $00000000 $00000000 ................
E000A5C0 $00000000 $00000000 $00000000 $00000000 ................
E000A5D0 $00000000 $00000000 $00000000 $00000000 ................
E000A5E0 $00000000 $00000000 $00000000 $00000000 ................
E000A5F0 $00000000 $00000000 $00000000 $00000000 ................
E000A600 $00000000 $00000000 $00000000 $00000000 ................
E000A610 $00000000 $00000000 $00000000 $00000000 ................
E000A620 $00000000 $00000000 $00000000 $00000000 ................
E000A630 $00000000 $00000000 $00000000 $00000000 ................
E000A640 $00000000 $00000000 $00000000 $00000000 ................
E000A650 $00000000 $00000000 $00000000 $00000000 ................
E000A660 $00000000 $00000000 $00000000 $00000000 ................
E000A670 $00000000 $00000000 $00000000 $00000000 ................
E000A680 $00000000 $00000000 $00000000 $00000000 ................
E000A690 $00000000 $00000000 $00000000 $00000000 ................
E000A6A0 $00000000 $00000000 $00000000 $00000000 ................
E000A6B0 $00000000 $00000000 $00000000 $00000000 ................
E000A6C0 $00000000 $00000000 $00000000 $00000000 ................
E000A6D0 $00000000 $00000000 $00000000 $00000000 ................
E000A6E0 $00000000 $00000000 $00000000 $00000000 ................
E000A6F0 $00000000 $00000000 $00000000 $00000000 ................
E000A700 $00000000 $00000000 $00000000 $00000000 ................
E000A710 $00000000 $00000000 $00000000 $00000000 ................
E000A720 $00000000 $00000000 $00000000 $00000000 ................
E000A730 $00000000 $00000000 $00000000 $00000000 ................
E000A740 $00000000 $00000000 $00000000 $00000000 ................
E000A750 $00000000 $00000000 $00000000 $00000000 ................
E000A760 $00000000 $00000000 $00000000 $00000000 ................
E000A770 $00000000 $00000000 $00000000 $00000000 ................
E000A780 $00000000 $00000000 $00000000 $00000000 ................
E000A790 $00000000 $00000000 $00000000 $00000000 ................
E000A7A0 $00000000 $00000000 $00000000 $00000000 ................
E000A7B0 $00000000 $00000000 $00000000 $00000000 ................
E000A7C0 $00000000 $00000000 $00000000 $00000000 ................
E000A7D0 $00000000 $00000000 $00000000 $00000000 ................
E000A7E0 $00000000 $00000000 $00000000 $00000000 ................
E000A7F0 $00000000 $00000000 $00000000 $00000000 ................
E000A800 $00000000 $00000000 $00000000 $00000000 ................
E000A810 $00000000 $00000000 $00000000 $00000000 ................
E000A820 $00000000 $00000000 $00000000 $00000000 ................
E000A830 $00000000 $00000000 $00000000 $00000000 ................
E000A840 $00000000 $00000000 $00000000 $00000000 ................
E000A850 $00000000 $00000000 $00000000 $00000000 ................
E000A860 $00000000 $00000000 $00000000 $00000000 ................
E000A870 $00000000 $00000000 $00000000 $00000000 ................
E000A880 $00000000 $00000000 $00000000 $00000000 ................
E000A890 $00000000 $00000000 $00000000 $00000000 ................
E000A8A0 $00000000 $00000000 $00000000 $00000000 ................
E000A8B0 $00000000 $00000000 $00000000 $00000000 ................
E000A8C0 $00000000 $00000000 $00000000 $00000000 ................
E000A8D0 $00000000 $00000000 $00000000 $00000000 ................
E000A8E0 $00000000 $00000000 $00000000 $00000000 ................
E000A8F0 $00000000 $00000000 $00000000 $00000000 ................
E000A900 $00000000 $00000000 $00000000 $00000000 ................
E000A910 $00000000 $00000000 $00000000 $00000000 ................
E000A920 $00000000 $00000000 $00000000 $00000000 ................
E000A930 $00000000 $00000000 $00000000 $00000000 ................
E000A940 $00000000 $00000000 $00000000 $00000000 ................
E000A950 $00000000 $00000000 $00000000 $00000000 ................
E000A960 $00000000 $00000000 $00000000 $00000000 ................
E000A970 $00000000 $00000000 $00000000 $00000000 ................
E000A980 $00000000 $00000000 $00000000 $00000000 ................
E000A990 $00000000 $00000000 $00000000 $00000000 ................
E000A9A0 $00000000 $00000000 $00000000 $00000000 ................
E000A9B0 $00000000 $00000000 $00000000 $00000000 ................
E000A9C0 $00000000 $00000000 $00000000 $00000000 ................
E000A9D0 $00000000 $00000000 $00000000 $00000000 ................
E000A9E0 $00000000 $00000000 $00000000 $00000000 ................
E000A9F0 $00000000 $00000000 $00000000 $00000000 ................
E000AA00 $00000000 $00000000 $00000000 $00000000 ................
E000AA10 $00000000 $00000000 $00000000 $00000000 ................
E000AA20 $00000000 $00000000 $00000000 $00000000 ................
E000AA30 $00000000 $00000000 $00000000 $00000000 ................
E000AA40 $00000000 $00000000 $00000000 $00000000 ................
E000AA50 $00000000 $00000000 $00000000 $00000000 ................
E000AA60 $00000000 $00000000 $00000000 $00000000 ................
E000AA70 $00000000 $00000000 $00000000 $00000000 ................
E000AA80 $00000000 $00000000 $00000000 $00000000 ................
E000AA90 $00000000 $00000000 $00000000 $00000000 ................
E000AAA0 $00000000 $00000000 $00000000 $00000000 ................
E000AAB0 $00000000 $00000000 $00000000 $00000000 ................
E000AAC0 $00000000 $00000000 $00000000 $00000000 ................
E000AAD0 $00000000 $00000000 $00000000 $00000000 ................
E000AAE0 $00000000 $00000000 $00000000 $00000000 ................
E000AAF0 $00000000 $00000000 $00000000 $00000000 ................
E000AB00 $00000000 $00000000 $00000000 $00000000 ................
E000AB10 $00000000 $00000000 $00000000 $00000000 ................
E000AB20 $00000000 $00000000 $00000000 $00000000 ................
E000AB30 $00000000 $00000000 $00000000 $00000000 ................
E000AB40 $00000000 $00000000 $00000000 $00000000 ................
E000AB50 $00000000 $00000000 $00000000 $00000000 ................
E000AB60 $00000000 $00000000 $00000000 $00000000 ................
E000AB70 $00000000 $00000000 $00000000 $00000000 ................
E000AB80 $00000000 $00000000 $00000000 $00000000 ................
E000AB90 $00000000 $00000000 $00000000 $00000000 ................
E000ABA0 $00000000 $00000000 $00000000 $00000000 ................
E000ABB0 $00000000 $00000000 $00000000 $00000000 ................
E000ABC0 $00000000 $00000000 $00000000 $00000000 ................
E000ABD0 $00000000 $00000000 $00000000 $00000000 ................
E000ABE0 $00000000 $00000000 $00000000 $00000000 ................
E000ABF0 $00000000 $00000000 $02080100 $00000000 ................
E000AC00 $00000000 $00000000 $00000000 $00000000 ................
E000AC10 $80044023 $00000000 $00000000 $00000000 ..@#............
E000AC20 $00080000 $00000000 $00080000 $00000000 ................
E000AC30 $8004401c $00000000 $00000000 $00000000 ..@.............
E000AC40 $00000000 $00000000 $000e3000 $00000000 ..........0.....
E000AC50 $80088016 $00000000 $00000000 $00000000 ................
E000AC60 $00000000 $00000000 $00000000 $00000000 ................
E000AC70 $00044023 $00000000 $00000000 $00000000 ..@#............
E000AC80 $00000000 $00000000 $00000000 $00000000 ................
E000AC90 $00044023 $00000000 $00000000 $00000000 ..@#............
E000ACA0 $00000000 $00000000 $00000000 $00000000 ................
E000ACB0 $00000000 $00000000 $00000000 $00000000 ................
E000ACC0 $00000000 $00000000 $00000000 $00000000 ................
E000ACD0 $00000000 $00000000 $00000000 $00000000 ................
E000ACE0 $00000000 $00000000 $00000000 $00000000 ................
E000ACF0 $00000000 $00000000 $00000000 $00000000 ................
E000AD00 $00000000 $00000000 $00000000 $00000000 ................
E000AD10 $00000000 $00000000 $00000000 $00000000 ................
E000AD20 $00000000 $00000000 $00000000 $00000000 ................
E000AD30 $00000000 $00000000 $00000000 $00000000 ................
E000AD40 $00000000 $00000000 $00000000 $00000000 ................
E000AD50 $00000000 $00000000 $00000000 $00000000 ................
E000AD60 $00000000 $00000000 $00000000 $00000000 ................
E000AD70 $00000000 $00000000 $00000000 $00000000 ................
E000AD80 $00000000 $00000000 $00000000 $00000000 ................
E000AD90 $00000000 $00000000 $00000000 $00000000 ................
E000ADA0 $00000000 $00000000 $00000000 $00000000 ................
E000ADB0 $a0f5501e $00000000 $00000000 $00000000 ..P.............
E000ADC0 $00000000 $00000000 $00000000 $00000000 ................
E000ADD0 $20f44023 $00000000 $00000000 $00000000 ..@#............
E000ADE0 $00000000 $00000000 $00000000 $00000000 ................
E000ADF0 $20f44023 $00000000 $00000000 $00000000 ..@#............
E000AE00 $80020000 $00000000 $00bdfe00 $00000000 ................
E000AE10 $00000000 $00000000 $00000000 $00000000 ................
E000AE20 $00000041 $00000000 $00000800 $00000000 ...A............
E000AE30 $00000000 $00000000 $00000000 $00000000 ................
E000AE40 $00000000 $00000000 $00000000 $00000000 ................
E000AE50 $00000000 $00000000 $00000000 $00000000 ................
E000AE60 $00000000 $00000000 $00000000 $00000000 ................
E000AE70 $00000000 $00000000 $00000000 $00000000 ................
E000AE80 $00000000 $00000000 $00000000 $00000000 ................
E000AE90 $00000000 $00000000 $00000000 $00000000 ................
E000AEA0 $00000000 $00000000 $00000000 $00000000 ................
E000AEB0 $00000000 $00000000 $00000000 $00000000 ................
E000AEC0 $00000000 $00000000 $00000000 $00000000 ................
E000AED0 $00000000 $00000000 $00000000 $00000000 ................
E000AEE0 $00000000 $00000000 $00000000 $00000000 ................
E000AEF0 $00000000 $00000000 $00000000 $00000000 ................
E000AF00 $80400080 $00000000 $00000000 $00000000 .@..............
E000AF10 $c8800000 $a0000000 $00000000 $00000000 ................
E000AF20 $00008000 $00000000 $00000000 $00000000 ................
E000AF30 $00000000 $00000000 $00000000 $00000000 ................
E000AF40 $00000000 $00000000 $00000000 $00000000 ................
E000AF50 $00000000 $00000000 $00000000 $00000000 ................
E000AF60 $00000000 $00000000 $00000000 $00000000 ................
E000AF70 $00000000 $00000000 $00000000 $00000000 ................
E000AF80 $00000000 $00000000 $00000000 $00000000 ................
E000AF90 $00000000 $00000000 $00000000 $00000000 ................
E000AFA0 $00000000 $00000000 $00000000 $00000000 ................
E000AFB0 $00000000 $00000000 $00000000 $00000000 ................
E000AFC0 $00000000 $00000000 $00000000 $00000000 ................
E000AFD0 $00000000 $00000000 $00000000 $00000000 ................
E000AFE0 $00000000 $00000000 $00000000 $00000000 ................
E000AFF0 $00000000 $00000000 $00000000 $00000000 ................
main (lc0)> mem -o read -a 0xe0009000 0x400
Invalid usage
main (lc0)> mem -o read -a 0xe0009000 -l 0x400
E0009000 $800300fc $00000000 $00000000 $0010ffff ................
E0009010 $0400ffff $00000028 $00000000 $00000000 .......(........
E0009020 $00000000 $00000000 $00000000 $00000000 ................
E0009030 $00000000 $00000000 $00000000 $00000000 ................
E0009040 $00000000 $00000000 $00000000 $00000000 ................
E0009050 $00000000 $00000000 $00000000 $00000000 ................
E0009060 $00000000 $00000000 $00000000 $00000000 ................
E0009070 $00000000 $00000000 $00000000 $00000000 ................
E0009080 $00000000 $00000000 $00000000 $00000000 ................
E0009090 $00000000 $00000000 $00000000 $00000000 ................
E00090A0 $00000000 $00000000 $00000000 $00000000 ................
E00090B0 $00000000 $00000000 $00000000 $00000000 ................
E00090C0 $00000000 $00000000 $00000000 $00000000 ................
E00090D0 $00000000 $00000000 $00000000 $00000000 ................
E00090E0 $00000000 $00000000 $00000000 $00000000 ................
E00090F0 $00000000 $00000000 $00000000 $00000000 ................
E0009100 $00000000 $00000000 $00000000 $00000000 ................
E0009110 $00000000 $00000000 $00000000 $00000000 ................
E0009120 $00000000 $00000000 $00000000 $00000000 ................
E0009130 $00000000 $00000000 $00000000 $00000000 ................
E0009140 $00000000 $00000000 $00000000 $00000000 ................
E0009150 $00000000 $00000000 $00000000 $00000000 ................
E0009160 $00000000 $00000000 $00000000 $00000000 ................
E0009170 $00000000 $00000000 $00000000 $00000000 ................
E0009180 $00000000 $00000000 $00000000 $00000000 ................
E0009190 $00000000 $00000000 $00000000 $00000000 ................
E00091A0 $00000000 $00000000 $00000000 $00000000 ................
E00091B0 $00000000 $00000000 $00000000 $00000000 ................
E00091C0 $00000000 $00000000 $00000000 $00000000 ................
E00091D0 $00000000 $00000000 $00000000 $00000000 ................
E00091E0 $00000000 $00000000 $00000000 $00000000 ................
E00091F0 $00000000 $00000000 $00000000 $00000000 ................
E0009200 $00000000 $00000000 $00000000 $00000000 ................
E0009210 $00000000 $00000000 $00000000 $00000000 ................
E0009220 $00000000 $00000000 $00000000 $00000000 ................
E0009230 $00000000 $00000000 $00000000 $00000000 ................
E0009240 $00000000 $00000000 $00000000 $00000000 ................
E0009250 $00000000 $00000000 $00000000 $00000000 ................
E0009260 $00000000 $00000000 $00000000 $00000000 ................
E0009270 $00000000 $00000000 $00000000 $00000000 ................
E0009280 $00000000 $00000000 $00000000 $00000000 ................
E0009290 $00000000 $00000000 $00000000 $00000000 ................
E00092A0 $00000000 $00000000 $00000000 $00000000 ................
E00092B0 $00000000 $00000000 $00000000 $00000000 ................
E00092C0 $00000000 $00000000 $00000000 $00000000 ................
E00092D0 $00000000 $00000000 $00000000 $00000000 ................
E00092E0 $00000000 $00000000 $00000000 $00000000 ................
E00092F0 $00000000 $00000000 $00000000 $00000000 ................
E0009300 $00000000 $00000000 $00000000 $00000000 ................
E0009310 $00000000 $00000000 $00000000 $00000000 ................
E0009320 $00000000 $00000000 $00000000 $00000000 ................
E0009330 $00000000 $00000000 $00000000 $00000000 ................
E0009340 $00000000 $00000000 $00000000 $00000000 ................
E0009350 $00000000 $00000000 $00000000 $00000000 ................
E0009360 $00000000 $00000000 $00000000 $00000000 ................
E0009370 $00000000 $00000000 $00000000 $00000000 ................
E0009380 $00000000 $00000000 $00000000 $00000000 ................
E0009390 $00000000 $00000000 $00000000 $00000000 ................
E00093A0 $00000000 $00000000 $00000000 $00000000 ................
E00093B0 $00000000 $00000000 $00000000 $00000000 ................
E00093C0 $00000000 $00000000 $00000000 $00000000 ................
E00093D0 $00000000 $00000000 $00000000 $00000000 ................
E00093E0 $00000000 $00000000 $00000000 $00000000 ................
E00093F0 $00000000 $00000000 $00000000 $00000000 ................
E0009400 $00000000 $00000000 $00000000 $00000000 ................
E0009410 $00000000 $00000000 $00000000 $00000000 ................
E0009420 $00000000 $00000000 $00000000 $00000000 ................
E0009430 $00000000 $00000000 $00000000 $00000000 ................
E0009440 $00000000 $00000000 $00000000 $00000000 ................
E0009450 $00000000 $00000000 $00000000 $00000000 ................
E0009460 $00000000 $00000000 $00000000 $00000000 ................
E0009470 $00000000 $00000000 $00000000 $00000000 ................
E0009480 $00000000 $00000000 $00000000 $00000000 ................
E0009490 $00000000 $00000000 $00000000 $00000000 ................
E00094A0 $00000000 $00000000 $00000000 $00000000 ................
E00094B0 $00000000 $00000000 $00000000 $00000000 ................
E00094C0 $00000000 $00000000 $00000000 $00000000 ................
E00094D0 $00000000 $00000000 $00000000 $00000000 ................
E00094E0 $00000000 $00000000 $00000000 $00000000 ................
E00094F0 $00000000 $00000000 $00000000 $00000000 ................
E0009500 $00000000 $00000000 $00000000 $00000000 ................
E0009510 $00000000 $00000000 $00000000 $00000000 ................
E0009520 $00000000 $00000000 $00000000 $00000000 ................
E0009530 $00000000 $00000000 $00000000 $00000000 ................
E0009540 $00000000 $00000000 $00000000 $00000000 ................
E0009550 $00000000 $00000000 $00000000 $00000000 ................
E0009560 $00000000 $00000000 $00000000 $00000000 ................
E0009570 $00000000 $00000000 $00000000 $00000000 ................
E0009580 $00000000 $00000000 $00000000 $00000000 ................
E0009590 $00000000 $00000000 $00000000 $00000000 ................
E00095A0 $00000000 $00000000 $00000000 $00000000 ................
E00095B0 $00000000 $00000000 $00000000 $00000000 ................
E00095C0 $00000000 $00000000 $00000000 $00000000 ................
E00095D0 $00000000 $00000000 $00000000 $00000000 ................
E00095E0 $00000000 $00000000 $00000000 $00000000 ................
E00095F0 $00000000 $00000000 $00000000 $00000000 ................
E0009600 $00000000 $00000000 $00000000 $00000000 ................
E0009610 $00000000 $00000000 $00000000 $00000000 ................
E0009620 $00000000 $00000000 $00000000 $00000000 ................
E0009630 $00000000 $00000000 $00000000 $00000000 ................
E0009640 $00000000 $00000000 $00000000 $00000000 ................
E0009650 $00000000 $00000000 $00000000 $00000000 ................
E0009660 $00000000 $00000000 $00000000 $00000000 ................
E0009670 $00000000 $00000000 $00000000 $00000000 ................
E0009680 $00000000 $00000000 $00000000 $00000000 ................
E0009690 $00000000 $00000000 $00000000 $00000000 ................
E00096A0 $00000000 $00000000 $00000000 $00000000 ................
E00096B0 $00000000 $00000000 $00000000 $00000000 ................
E00096C0 $00000000 $00000000 $00000000 $00000000 ................
E00096D0 $00000000 $00000000 $00000000 $00000000 ................
E00096E0 $00000000 $00000000 $00000000 $00000000 ................
E00096F0 $00000000 $00000000 $00000000 $00000000 ................
E0009700 $00000000 $00000000 $00000000 $00000000 ................
E0009710 $00000000 $00000000 $00000000 $00000000 ................
E0009720 $00000000 $00000000 $00000000 $00000000 ................
E0009730 $00000000 $00000000 $00000000 $00000000 ................
E0009740 $00000000 $00000000 $00000000 $00000000 ................
E0009750 $00000000 $00000000 $00000000 $00000000 ................
E0009760 $00000000 $00000000 $00000000 $00000000 ................
E0009770 $00000000 $00000000 $00000000 $00000000 ................
E0009780 $00000000 $00000000 $00000000 $00000000 ................
E0009790 $00000000 $00000000 $00000000 $00000000 ................
E00097A0 $00000000 $00000000 $00000000 $00000000 ................
E00097B0 $00000000 $00000000 $00000000 $00000000 ................
E00097C0 $00000000 $00000000 $00000000 $00000000 ................
E00097D0 $00000000 $00000000 $00000000 $00000000 ................
E00097E0 $00000000 $00000000 $00000000 $00000000 ................
E00097F0 $00000000 $00000000 $00000000 $00000000 ................
E0009800 $00000000 $00000000 $00000000 $00000000 ................
E0009810 $00000000 $00000000 $00000000 $00000000 ................
E0009820 $00000000 $00000000 $00000000 $00000000 ................
E0009830 $00000000 $00000000 $00000000 $00000000 ................
E0009840 $00000000 $00000000 $00000000 $00000000 ................
E0009850 $00000000 $00000000 $00000000 $00000000 ................
E0009860 $00000000 $00000000 $00000000 $00000000 ................
E0009870 $00000000 $00000000 $00000000 $00000000 ................
E0009880 $00000000 $00000000 $00000000 $00000000 ................
E0009890 $00000000 $00000000 $00000000 $00000000 ................
E00098A0 $00000000 $00000000 $00000000 $00000000 ................
E00098B0 $00000000 $00000000 $00000000 $00000000 ................
E00098C0 $00000000 $00000000 $00000000 $00000000 ................
E00098D0 $00000000 $00000000 $00000000 $00000000 ................
E00098E0 $00000000 $00000000 $00000000 $00000000 ................
E00098F0 $00000000 $00000000 $00000000 $00000000 ................
E0009900 $00000000 $00000000 $00000000 $00000000 ................
E0009910 $00000000 $00000000 $00000000 $00000000 ................
E0009920 $00000000 $00000000 $00000000 $00000000 ................
E0009930 $00000000 $00000000 $00000000 $00000000 ................
E0009940 $00000000 $00000000 $00000000 $00000000 ................
E0009950 $00000000 $00000000 $00000000 $00000000 ................
E0009960 $00000000 $00000000 $00000000 $00000000 ................
E0009970 $00000000 $00000000 $00000000 $00000000 ................
E0009980 $00000000 $00000000 $00000000 $00000000 ................
E0009990 $00000000 $00000000 $00000000 $00000000 ................
E00099A0 $00000000 $00000000 $00000000 $00000000 ................
E00099B0 $00000000 $00000000 $00000000 $00000000 ................
E00099C0 $00000000 $00000000 $00000000 $00000000 ................
E00099D0 $00000000 $00000000 $00000000 $00000000 ................
E00099E0 $00000000 $00000000 $00000000 $00000000 ................
E00099F0 $00000000 $00000000 $00000000 $00000000 ................
E0009A00 $00000000 $00000000 $00000000 $00000000 ................
E0009A10 $00000000 $00000000 $00000000 $00000000 ................
E0009A20 $00000000 $00000000 $00000000 $00000000 ................
E0009A30 $00000000 $00000000 $00000000 $00000000 ................
E0009A40 $00000000 $00000000 $00000000 $00000000 ................
E0009A50 $00000000 $00000000 $00000000 $00000000 ................
E0009A60 $00000000 $00000000 $00000000 $00000000 ................
E0009A70 $00000000 $00000000 $00000000 $00000000 ................
E0009A80 $00000000 $00000000 $00000000 $00000000 ................
E0009A90 $00000000 $00000000 $00000000 $00000000 ................
E0009AA0 $00000000 $00000000 $00000000 $00000000 ................
E0009AB0 $00000000 $00000000 $00000000 $00000000 ................
E0009AC0 $00000000 $00000000 $00000000 $00000000 ................
E0009AD0 $00000000 $00000000 $00000000 $00000000 ................
E0009AE0 $00000000 $00000000 $00000000 $00000000 ................
E0009AF0 $00000000 $00000000 $00000000 $00000000 ................
E0009B00 $00000000 $00000000 $00000000 $00000000 ................
E0009B10 $00000000 $00000000 $00000000 $00000000 ................
E0009B20 $00000000 $00000000 $00000000 $00000000 ................
E0009B30 $00000000 $00000000 $00000000 $00000000 ................
E0009B40 $00000000 $00000000 $00000000 $00000000 ................
E0009B50 $00000000 $00000000 $00000000 $00000000 ................
E0009B60 $00000000 $00000000 $00000000 $00000000 ................
E0009B70 $00000000 $00000000 $00000000 $00000000 ................
E0009B80 $00000000 $00000000 $00000000 $00000000 ................
E0009B90 $00000000 $00000000 $00000000 $00000000 ................
E0009BA0 $00000000 $00000000 $00000000 $00000000 ................
E0009BB0 $00000000 $00000000 $00000000 $00000000 ................
E0009BC0 $00000000 $00000000 $00000000 $00000000 ................
E0009BD0 $00000000 $00000000 $00000000 $00000000 ................
E0009BE0 $00000000 $00000000 $00000000 $00000000 ................
E0009BF0 $00000000 $00000000 $02080100 $00000000 ................
E0009C00 $00000000 $00000000 $00000000 $00000000 ................
E0009C10 $80044023 $00000000 $00000000 $00000000 ..@#............
E0009C20 $000a0000 $00000000 $000a0000 $00000000 ................
E0009C30 $8004401c $00000000 $00000000 $00000000 ..@.............
E0009C40 $00000000 $00000000 $000e3800 $00000000 ..........8.....
E0009C50 $80088016 $00000000 $00000000 $00000000 ................
E0009C60 $00000000 $00000000 $00000000 $00000000 ................
E0009C70 $00044023 $00000000 $00000000 $00000000 ..@#............
E0009C80 $00000000 $00000000 $00000000 $00000000 ................
E0009C90 $00044023 $00000000 $00000000 $00000000 ..@#............
E0009CA0 $00000000 $00000000 $00000000 $00000000 ................
E0009CB0 $00000000 $00000000 $00000000 $00000000 ................
E0009CC0 $00000000 $00000000 $00000000 $00000000 ................
E0009CD0 $00000000 $00000000 $00000000 $00000000 ................
E0009CE0 $00000000 $00000000 $00000000 $00000000 ................
E0009CF0 $00000000 $00000000 $00000000 $00000000 ................
E0009D00 $00000000 $00000000 $00000000 $00000000 ................
E0009D10 $00000000 $00000000 $00000000 $00000000 ................
E0009D20 $00000000 $00000000 $00000000 $00000000 ................
E0009D30 $00000000 $00000000 $00000000 $00000000 ................
E0009D40 $00000000 $00000000 $00000000 $00000000 ................
E0009D50 $00000000 $00000000 $00000000 $00000000 ................
E0009D60 $00000000 $00000000 $00000000 $00000000 ................
E0009D70 $00000000 $00000000 $00000000 $00000000 ................
E0009D80 $00000000 $00000000 $00000000 $00000000 ................
E0009D90 $00000000 $00000000 $00000000 $00000000 ................
E0009DA0 $00000000 $00000000 $00000000 $00000000 ................
E0009DB0 $a0f5501e $00000000 $00000000 $00000000 ..P.............
E0009DC0 $00000000 $00000000 $00000000 $00000000 ................
E0009DD0 $20f44023 $00000000 $00000000 $00000000 ..@#............
E0009DE0 $00000000 $00000000 $00000000 $00000000 ................
E0009DF0 $20f44023 $00000000 $00000000 $00000000 ..@#............
E0009E00 $80020000 $00000000 $00bdfe00 $00000000 ................
E0009E10 $00000000 $00000000 $00000000 $00000000 ................
E0009E20 $00000041 $00000000 $00000800 $00000000 ...A............
E0009E30 $00000000 $00000000 $00000000 $00000000 ................
E0009E40 $00000000 $00000000 $00000000 $00000000 ................
E0009E50 $00000000 $00000000 $00000000 $00000000 ................
E0009E60 $00000000 $00000000 $00000000 $00000000 ................
E0009E70 $00000000 $00000000 $00000000 $00000000 ................
E0009E80 $00000000 $00000000 $00000000 $00000000 ................
E0009E90 $00000000 $00000000 $00000000 $00000000 ................
E0009EA0 $00000000 $00000000 $00000000 $00000000 ................
E0009EB0 $00000000 $00000000 $00000000 $00000000 ................
E0009EC0 $00000000 $00000000 $00000000 $00000000 ................
E0009ED0 $00000000 $00000000 $00000000 $00000000 ................
E0009EE0 $00000000 $00000000 $00000000 $00000000 ................
E0009EF0 $00000000 $00000000 $00000000 $00000000 ................
E0009F00 $80400080 $00000000 $00000000 $00000000 .@..............
E0009F10 $c8800000 $a0000000 $00000000 $00000000 ................
E0009F20 $00008000 $00000000 $00000000 $00000000 ................
E0009F30 $00000000 $00000000 $00000000 $00000000 ................
E0009F40 $00000000 $00000000 $00000000 $00000000 ................
E0009F50 $00000000 $00000000 $00000000 $00000000 ................
E0009F60 $00000000 $00000000 $00000000 $00000000 ................
E0009F70 $00000000 $00000000 $00000000 $00000000 ................
E0009F80 $00000000 $00000000 $00000000 $00000000 ................
E0009F90 $00000000 $00000000 $00000000 $00000000 ................
E0009FA0 $00000000 $00000000 $00000000 $00000000 ................
E0009FB0 $00000000 $00000000 $00000000 $00000000 ................
E0009FC0 $00000000 $00000000 $00000000 $00000000 ................
E0009FD0 $00000000 $00000000 $00000000 $00000000 ................
E0009FE0 $00000000 $00000000 $00000000 $00000000 ................
E0009FF0 $00000000 $00000000 $00000000 $00000000 ................
main (lc0)>
^ permalink raw reply
* Re: Re:Re: PCIe bus seems work while 'dma' can't under linux
From: Benjamin Herrenschmidt @ 2010-06-15 7:12 UTC (permalink / raw)
To: jxnuxdy
Cc: linuxppc-dev, Michal Simek, Stephen Rothwell, devicetree-discuss,
microblaze-uclinux
In-Reply-To: <1a6d876.2342.1293a6db848.Coremail.jxnuxdy@163.com>
On Tue, 2010-06-15 at 15:05 +0800, jxnuxdy wrote:
> Thanks Benjamin, the regions don't display as what we expect, that's why we suspect if there any configuration probelms in CPU host bridge, but we changed the uboot/linux a lot, seems take no effect on that problems.
>
> We use CPU MPC8544, and connect two PCIE devices to CPU PCIE1 and PCIE2 directly without a extended PCIE bridge, so we disabled PCIE3 and PCI controlers in uboot level.
>
> More settings pls take a look at the attach file log.txt.
I'm not familiar with those freescale parts, so I'll let others comment
on your settings since it's most likely to be where the problem is.
Cheers,
Ben.
>
> Many thanks,
> Denny
> ----------------------------------------------------------------------------------------------------------------------------
> 在2010-06-11 15:21:24，"Benjamin Herrenschmidt" <benh@kernel.crashing.org> 写道：
> >On Fri, 2010-06-11 at 09:30 +0800, jxnuxdy wrote:
> >> Hi guys,
> >>
> >> I encountered a PCIe problem under linux, the two PCIe bus on my board seems work,
> >> at least I can access the registers through the PCIe bus, however the dma for the
> >> PCIe bus can't work, so I just dumped the pci device, but I am curiously to find
> >> there is no regions displayed on PCIe controlers, why? is it relate with my 'dma' issue then?
> >
> >It would help if you told us a bit more what the HW is, what you are
> >doing with it, etc...
> >
> >IE. What is your host, what is your device, what platform, etc...
> >
> >DMA should work provided that your platform code sets it up properly.
> >The DMA regions don't appear in /proc/pci or lspci.
> >
> >Cheers,
> >Ben.
> >
> >>
> >> bash-2.04# cat /proc/pci
> >> PCI devices found:
> >> Bus 0, device 0, function 0:
> >> Class 0b20 Header Type 01: PCI device 1957:0032 (rev 17).
> >> Bus 1, device 0, function 0:
> >> Class 0580 Header Type 00: PCI device 11ab:db90 (rev 1).
> >> Prefetchable 64 bit memory at 0x80000000 [0x800fffff].
> >> Prefetchable 64 bit memory at 0x84000000 [0x87ffffff].
> >> Bus 9, device 0, function 0:
> >> Class 0b20 Header Type 01: PCI device 1957:0032 (rev 17).
> >> Bus 10, device 0, function 0:
> >> Class 0580 Header Type 00: PCI device 11ab:db90 (rev 1).
> >> Prefetchable 64 bit memory at 0xa0000000 [0xa00fffff].
> >> Prefetchable 64 bit memory at 0xa4000000 [0xa7ffffff].
> >> bash-2.04# lspci -vv
> >> 00:00.0 Power PC: Unknown device 1957:0032 (rev 11)
> >> !!! Invalid class 0b20 for header type 01
> >> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
> >> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
> >> Latency: 0, cache line size 08
> >> Bus: primary=00, secondary=01, subordinate=06, sec-latency=0
> >> I/O behind bridge: 00000000-00000fff
> >> Memory behind bridge: 80000000-9fffffff
> >> BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
> >> Capabilities: [44] Power Management version 2
> >> Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
> >> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> >> Capabilities: [4c] #10 [0041]
> >>
> >> 01:00.0 Memory controller: Galileo Technology Ltd.: Unknown device db90 (rev 01)
> >> Subsystem: Galileo Technology Ltd.: Unknown device 11ab
> >> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
> >> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
> >> Latency: 0, cache line size 08
> >> Interrupt: pin A routed to IRQ 0
> >> Region 0: Memory at 80000000 (64-bit, prefetchable) [size=1M]
> >> Region 2: Memory at 84000000 (64-bit, prefetchable) [size=64M]
> >> Capabilities: [40] Power Management version 2
> >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
> >> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> >> Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
> >> Address: 0000000000000000 Data: 0000
> >> Capabilities: [60] #10 [0011]
> >>
> >> 09:00.0 Power PC: Unknown device 1957:0032 (rev 11)
> >> !!! Invalid class 0b20 for header type 01
> >> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
> >> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
> >> Latency: 0, cache line size 08
> >> Bus: primary=00, secondary=0a, subordinate=0f, sec-latency=0
> >> I/O behind bridge: 00000000-00000fff
> >> Memory behind bridge: a0000000-bfffffff
> >> BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
> >> Capabilities: [44] Power Management version 2
> >> Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
> >> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> >> Capabilities: [4c] #10 [0041]
> >>
> >> 0a:00.0 Memory controller: Galileo Technology Ltd.: Unknown device db90 (rev 01)
> >> Subsystem: Galileo Technology Ltd.: Unknown device 11ab
> >> Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
> >> Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
> >> Latency: 0, cache line size 08
> >> Interrupt: pin A routed to IRQ 0
> >> Region 0: Memory at a0000000 (64-bit, prefetchable) [size=1M]
> >> Region 2: Memory at a4000000 (64-bit, prefetchable) [size=64M]
> >> Capabilities: [40] Power Management version 2
> >> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
> >> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> >> Capabilities: [50] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable-
> >> Address: 0000000000000000 Data: 0000
> >> Capabilities: [60] #10 [0011]
> >>
> >> bash-2.04#
> >>
> >> Thanks
> >> Denny
> >>
> >> _______________________________________________
> >> Linuxppc-dev mailing list
> >> Linuxppc-dev@lists.ozlabs.org
> >> https://lists.ozlabs.org/listinfo/linuxppc-dev
> >
> >
> >_______________________________________________
> >Linuxppc-dev mailing list
> >Linuxppc-dev@lists.ozlabs.org
> >https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* [git pull] Please pull powerpc.git next branch
From: Benjamin Herrenschmidt @ 2010-06-15 6:29 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, Andrew Morton, Linux Kernel list
Hi Linus !
Here's a few powerpc fixes for 2.6.35. The diffstat is sadly bloated by
a small defconfig change, I hate that too :-) We'll switch to some
better mechanism as soon as the dust as settled on what that mechanism
should be, hopefully real soon.
Cheers,
Ben.
The following changes since commit 7e27d6e778cd87b6f2415515d7127eba53fe5d02:
Linus Torvalds (1):
Linux 2.6.35-rc3
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
Alastair Bridgewater (1):
powerpc: Fix mpic_resume on early G5 macs
Anton Blanchard (1):
powerpc: Move kdump default base address to 64MB on 64bit
Benjamin Herrenschmidt (1):
Merge commit 'kumar/merge' into merge
Christoph Egger (1):
powerpc: Remove dead CONFIG_HIGHPTE
Christoph Hellwig (1):
powerpc: Unconditionally enabled irq stacks
Grant Likely (1):
powerpc: Disable CONFIG_SYSFS_DEPRECATED
Kumar Gala (1):
powerpc/fsl-booke: Move loadcam_entry back to asm code to fix SMP ftrace
Li Yang (1):
powerpc/fsl-booke: Fix InstructionTLBError execute permission check
Matt Evans (1):
powerpc/kexec: Wait for online/possible CPUs only.
Milton Miller (1):
powerpc: rtas_flash needs to use rtas_data_buf
Paul Mackerras (1):
powerpc/boot: Remove addRamdisk.c since it is now unused
arch/powerpc/Kconfig.debug | 7 -
arch/powerpc/boot/Makefile | 2 +-
arch/powerpc/boot/addRamDisk.c | 311 ----------------------
arch/powerpc/configs/40x/acadia_defconfig | 3 +-
arch/powerpc/configs/40x/ep405_defconfig | 3 +-
arch/powerpc/configs/40x/hcu4_defconfig | 3 +-
arch/powerpc/configs/40x/kilauea_defconfig | 3 +-
arch/powerpc/configs/40x/makalu_defconfig | 3 +-
arch/powerpc/configs/40x/virtex_defconfig | 3 +-
arch/powerpc/configs/40x/walnut_defconfig | 3 +-
arch/powerpc/configs/44x/arches_defconfig | 3 +-
arch/powerpc/configs/44x/bamboo_defconfig | 3 +-
arch/powerpc/configs/44x/canyonlands_defconfig | 3 +-
arch/powerpc/configs/44x/ebony_defconfig | 3 +-
arch/powerpc/configs/44x/eiger_defconfig | 3 +-
arch/powerpc/configs/44x/katmai_defconfig | 3 +-
arch/powerpc/configs/44x/rainier_defconfig | 3 +-
arch/powerpc/configs/44x/redwood_defconfig | 3 +-
arch/powerpc/configs/44x/sam440ep_defconfig | 3 +-
arch/powerpc/configs/44x/sequoia_defconfig | 3 +-
arch/powerpc/configs/44x/taishan_defconfig | 3 +-
arch/powerpc/configs/44x/virtex5_defconfig | 3 +-
arch/powerpc/configs/52xx/cm5200_defconfig | 3 +-
arch/powerpc/configs/52xx/lite5200b_defconfig | 3 +-
arch/powerpc/configs/52xx/motionpro_defconfig | 3 +-
arch/powerpc/configs/52xx/pcm030_defconfig | 3 +-
arch/powerpc/configs/52xx/tqm5200_defconfig | 3 +-
arch/powerpc/configs/86xx/gef_ppc9a_defconfig | 3 +-
arch/powerpc/configs/86xx/gef_sbc310_defconfig | 3 +-
arch/powerpc/configs/86xx/gef_sbc610_defconfig | 3 +-
arch/powerpc/configs/86xx/mpc8610_hpcd_defconfig | 3 +-
arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig | 3 +-
arch/powerpc/configs/86xx/sbc8641d_defconfig | 3 +-
arch/powerpc/configs/adder875_defconfig | 3 +-
arch/powerpc/configs/amigaone_defconfig | 3 +-
arch/powerpc/configs/c2k_defconfig | 3 +-
arch/powerpc/configs/cell_defconfig | 3 +-
arch/powerpc/configs/celleb_defconfig | 3 +-
arch/powerpc/configs/chrp32_defconfig | 3 +-
arch/powerpc/configs/ep8248e_defconfig | 3 +-
arch/powerpc/configs/ep88xc_defconfig | 3 +-
arch/powerpc/configs/g5_defconfig | 3 +-
arch/powerpc/configs/gamecube_defconfig | 3 +-
arch/powerpc/configs/holly_defconfig | 1 -
arch/powerpc/configs/iseries_defconfig | 3 +-
arch/powerpc/configs/linkstation_defconfig | 3 +-
arch/powerpc/configs/maple_defconfig | 3 +-
arch/powerpc/configs/mgcoge_defconfig | 3 +-
arch/powerpc/configs/mgsuvd_defconfig | 3 +-
arch/powerpc/configs/mpc512x_defconfig | 3 +-
arch/powerpc/configs/mpc5200_defconfig | 3 +-
arch/powerpc/configs/mpc7448_hpc2_defconfig | 3 +-
arch/powerpc/configs/pasemi_defconfig | 3 +-
arch/powerpc/configs/pmac32_defconfig | 3 +-
arch/powerpc/configs/ppc40x_defconfig | 3 +-
arch/powerpc/configs/ppc44x_defconfig | 3 +-
arch/powerpc/configs/ppc64_defconfig | 3 +-
arch/powerpc/configs/ppc64e_defconfig | 3 +-
arch/powerpc/configs/pq2fads_defconfig | 3 +-
arch/powerpc/configs/prpmc2800_defconfig | 3 +-
arch/powerpc/configs/pseries_defconfig | 3 +-
arch/powerpc/configs/storcenter_defconfig | 3 +-
arch/powerpc/configs/wii_defconfig | 3 +-
arch/powerpc/include/asm/irq.h | 6 -
arch/powerpc/include/asm/kdump.h | 11 +-
arch/powerpc/kernel/irq.c | 12 -
arch/powerpc/kernel/machine_kexec_64.c | 18 +--
arch/powerpc/kernel/misc_32.S | 2 -
arch/powerpc/kernel/misc_64.S | 2 -
arch/powerpc/kernel/process.c | 5 -
arch/powerpc/kernel/rtas_flash.c | 39 ++--
arch/powerpc/kernel/setup_32.c | 4 -
arch/powerpc/kernel/setup_64.c | 4 -
arch/powerpc/mm/pgtable_32.c | 4 -
arch/powerpc/sysdev/mpic.c | 2 +-
75 files changed, 93 insertions(+), 514 deletions(-)
delete mode 100644 arch/powerpc/boot/addRamDisk.c
^ permalink raw reply
* Re: [Patch 0/5] PPC64-HWBKPT: Hardware Breakpoint interfaces - ver XXII
From: K.Prasad @ 2010-06-15 6:09 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev@ozlabs.org, Benjamin Herrenschmidt
In-Reply-To: <20100615015459.GA30479@drongo>
On Tue, Jun 15, 2010 at 11:54:59AM +1000, Paul Mackerras wrote:
> On Fri, Jun 04, 2010 at 12:21:45PM +0530, K.Prasad wrote:
>
> > Meanwhile I tested the per-cpu breakpoints with the new emulate_step
> > patch (refer linuxppc-dev message-id:
> > 20100602112903.GB30149@brick.ozlabs.ibm.com) and they continue to fail
> > due to emulate_step() failure, in my case, on a "lwz r0,0(r28)"
> > instruction.
>
> You need to pass the instruction word to emulate_step(), not the
> instruction address. Also you need to have the full GPR set
> available. The patch below fixes these problems. I'll fold these
> changes into your patch 2/5.
>
> Paul.
The breakpoints that used to fail before (due to emulate_step() failure)
are now working fine upon applying this patch.
Please include this patch along with my 2/5 as indicated by you.
Thanks,
K.Prasad
^ permalink raw reply
* Re: [Patch 5/5] PPC64-HWBKPT: Discard extraneous interrupt due to accesses outside symbol length
From: K.Prasad @ 2010-06-15 6:07 UTC (permalink / raw)
To: Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, linuxppc-dev@ozlabs.org,
Alan Stern, Roland McGrath
In-Reply-To: <20100610124024.GA28613@brick.ozlabs.ibm.com>
On Thu, Jun 10, 2010 at 10:40:24PM +1000, Paul Mackerras wrote:
> On Wed, Jun 09, 2010 at 03:55:59PM +0530, K.Prasad wrote:
>
> > + if (!((bp->attr.bp_addr <= dar) &&
> > + (dar <= (bp->attr.bp_addr + bp->attr.bp_len)))) {
> > + /*
> > + * This exception is triggered not because of a memory access
> > + * on the monitored variable but in the double-word address
> > + * range in which it is contained. We will consume this
> > + * exception, considering it as 'noise'.
> > + */
> > + info->extraneous_interrupt = true;
> > + }
>
> Ummm, don't you need to add "else info->extraneous_interrupt = false;"
> here? I don't see anywhere that you ever clear it otherwise.
>
> Also, I think you need to do the "if (!info->extraneous_interrupt)"
> check around the call to perf_bp_event() later on in
> hw_breakpoint_handler() as well as around the call in
> single_step_dabr_instruction().
>
> Paul.
True, I've added the check before perf_bp_event() (wherever it was
missing before) in the patchset ver XXIV.
Thanks,
K.Prasad
^ permalink raw reply
* [Patch 5/5] PPC64-HWBKPT: Discard extraneous interrupt due to accesses outside symbol length
From: K.Prasad @ 2010-06-15 6:06 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100615055010.108795721@linux.vnet.ibm.com>
Many a times, the requested breakpoint length can be less than the fixed
breakpoint length i.e. 8 bytes supported by PowerPC BookIII S. This could lead
to extraneous interrupts resulting in false breakpoint notifications. The patch
below detects and discards such interrupts for non-ptrace requests (we don't
want to change ptrace behaviour for fear of breaking compatability).
[Suggestions from Paul Mackerras <paulus@samba.org> to add a new flag in
'struct arch_hw_breakpoint' to identify extraneous interrupts]
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/hw_breakpoint.h | 1 +
arch/powerpc/kernel/hw_breakpoint.c | 23 +++++++++++++++++++++--
2 files changed, 22 insertions(+), 2 deletions(-)
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/hw_breakpoint.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
@@ -202,6 +202,7 @@ int __kprobes hw_breakpoint_handler(stru
struct pt_regs *regs = args->regs;
int stepped = 1;
struct arch_hw_breakpoint *info;
+ unsigned long dar = regs->dar;
/* Disable breakpoints during exception handling */
set_dabr(0);
@@ -232,6 +233,22 @@ int __kprobes hw_breakpoint_handler(stru
goto out;
}
+ /*
+ * Verify if dar lies within the address range occupied by the symbol
+ * being watched to filter extraneous exceptions.
+ */
+ if (!((bp->attr.bp_addr <= dar) &&
+ (dar <= (bp->attr.bp_addr + bp->attr.bp_len)))) {
+ /*
+ * This exception is triggered not because of a memory access
+ * on the monitored variable but in the double-word address
+ * range in which it is contained. We will consume this
+ * exception, considering it as 'noise'.
+ */
+ info->extraneous_interrupt = true;
+ } else
+ info->extraneous_interrupt = false;
+
/* Do not emulate user-space instructions, instead single-step them */
if (user_mode(regs)) {
bp->ctx->task->thread.last_hit_ubp = bp;
@@ -255,7 +272,8 @@ int __kprobes hw_breakpoint_handler(stru
* As a policy, the callback is invoked in a 'trigger-after-execute'
* fashion
*/
- perf_bp_event(bp, regs);
+ if (!info->extraneous_interrupt)
+ perf_bp_event(bp, regs);
set_dabr(info->address | info->type | DABR_TRANSLATION);
out:
@@ -286,7 +304,8 @@ int __kprobes single_step_dabr_instructi
* We shall invoke the user-defined callback function in the single
* stepping handler to confirm to 'trigger-after-execute' semantics
*/
- perf_bp_event(bp, regs);
+ if (!bp_info->extraneous_interrupt)
+ perf_bp_event(bp, regs);
/*
* Do not disable MSR_SE if the process was already in
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/hw_breakpoint.h
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
@@ -27,6 +27,7 @@
#ifdef CONFIG_HAVE_HW_BREAKPOINT
struct arch_hw_breakpoint {
+ bool extraneous_interrupt;
u8 len; /* length of the target data symbol */
int type;
unsigned long address;
^ permalink raw reply
* [Patch 4/5] PPC64-HWBKPT: Enable hw-breakpoints while handling intervening signals
From: K.Prasad @ 2010-06-15 6:05 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100615055010.108795721@linux.vnet.ibm.com>
A signal delivered between a hw_breakpoint_handler() and the
single_step_dabr_instruction() will not have the breakpoint active during
signal handling (since breakpoint will not be restored through single-stepping
due to absence of MSR_SE bit on the signal frame). Enable breakpoints before
signal delivery.
Restore hw-breakpoints if the user-context is altered in the signal handler.
[With inputs from Paul Mackerras <paulus@samba.org> which helped identify a
need to restore breakpoints before handling a signal delivered in certain
cases]
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/hw_breakpoint.h | 3 +++
arch/powerpc/kernel/hw_breakpoint.c | 18 ++++++++++++++++++
arch/powerpc/kernel/signal.c | 3 +++
3 files changed, 24 insertions(+)
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/hw_breakpoint.h
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
@@ -65,9 +65,12 @@ static inline void hw_breakpoint_disable
{
set_dabr(0);
}
+extern void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs);
#else /* CONFIG_HAVE_HW_BREAKPOINT */
static inline void hw_breakpoint_disable(void) { }
+static inline void thread_change_pc(struct task_struct *tsk,
+ struct pt_regs *regs) { }
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif /* __KERNEL__ */
#endif /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/hw_breakpoint.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
@@ -174,6 +174,24 @@ int arch_validate_hwbkpt_settings(struct
}
/*
+ * Restores the breakpoint on the debug registers.
+ * Invoke this function if it is known that the execution context is about to
+ * change to cause loss of MSR_SE settings.
+ */
+void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
+{
+ struct arch_hw_breakpoint *info;
+
+ if (likely(!tsk->thread.last_hit_ubp))
+ return;
+
+ info = counter_arch_bp(tsk->thread.last_hit_ubp);
+ regs->msr &= ~MSR_SE;
+ set_dabr(info->address | info->type | DABR_TRANSLATION);
+ tsk->thread.last_hit_ubp = NULL;
+}
+
+/*
* Handle debug exception notifications.
*/
int __kprobes hw_breakpoint_handler(struct die_args *args)
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/signal.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/signal.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/signal.c
@@ -11,6 +11,7 @@
#include <linux/tracehook.h>
#include <linux/signal.h>
+#include <asm/hw_breakpoint.h>
#include <asm/uaccess.h>
#include <asm/unistd.h>
@@ -149,6 +150,8 @@ static int do_signal_pending(sigset_t *o
if (current->thread.dabr)
set_dabr(current->thread.dabr);
#endif
+ /* Re-enable the breakpoints for the signal stack */
+ thread_change_pc(current, regs);
if (is32) {
if (ka.sa.sa_flags & SA_SIGINFO)
^ permalink raw reply
* [Patch 3/5] PPC64-HWBKPT: Handle concurrent alignment interrupts
From: K.Prasad @ 2010-06-15 6:05 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100615055010.108795721@linux.vnet.ibm.com>
An alignment interrupt may intervene between a DSI/hw-breakpoint exception
and the single-step exception. Enable the alignment interrupt (through
modifications to emulate_single_step()) to notify the single-step exception
handler for proper restoration of hw-breakpoints.
[The need to invoke single-step handler after alignment interrupt pointed out
by Paul Mackerras <paulus@samba.org>]
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/kernel/traps.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/traps.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/traps.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/traps.c
@@ -602,7 +602,7 @@ void RunModeException(struct pt_regs *re
void __kprobes single_step_exception(struct pt_regs *regs)
{
- regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */
+ clear_single_step(regs);
if (notify_die(DIE_SSTEP, "single_step", regs, 5,
5, SIGTRAP) == NOTIFY_STOP)
@@ -621,10 +621,8 @@ void __kprobes single_step_exception(str
*/
static void emulate_single_step(struct pt_regs *regs)
{
- if (single_stepping(regs)) {
- clear_single_step(regs);
- _exception(SIGTRAP, regs, TRAP_TRACE, 0);
- }
+ if (single_stepping(regs))
+ single_step_exception(regs);
}
static inline int __parse_fpscr(unsigned long fpscr)
^ permalink raw reply
* [Patch 2/5] PPC64-HWBKPT: Implement hw-breakpoints for PowerPC BookIII S
From: K.Prasad @ 2010-06-15 6:05 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100615055010.108795721@linux.vnet.ibm.com>
Implement perf-events based hw-breakpoint interfaces for PowerPC Book III S
processors. These interfaces help arbitrate requests from various users and
schedules them as appropriate.
[Suggestions from Paul Mackerras <paulus@samba.org> to
- emulate_step() all non-task bound breakpoints and single-step only the
per-task breakpoints
- perform arch-specific cleanup before unregistration through
arch_unregister_hw_breakpoint()
]
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
---
arch/powerpc/Kconfig | 1
arch/powerpc/include/asm/cputable.h | 4
arch/powerpc/include/asm/hw_breakpoint.h | 73 +++++++
arch/powerpc/include/asm/processor.h | 8
arch/powerpc/kernel/Makefile | 1
arch/powerpc/kernel/hw_breakpoint.c | 320 +++++++++++++++++++++++++++++++
arch/powerpc/kernel/machine_kexec_64.c | 3
arch/powerpc/kernel/process.c | 14 +
arch/powerpc/kernel/ptrace.c | 64 ++++++
arch/powerpc/lib/Makefile | 1
10 files changed, 489 insertions(+)
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
===================================================================
--- /dev/null
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/hw_breakpoint.h
@@ -0,0 +1,73 @@
+/*
+ * PowerPC BookIII S hardware breakpoint definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010, IBM Corporation.
+ * Author: K.Prasad <prasad@linux.vnet.ibm.com>
+ *
+ */
+
+#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
+#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
+
+#ifdef __KERNEL__
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+
+struct arch_hw_breakpoint {
+ u8 len; /* length of the target data symbol */
+ int type;
+ unsigned long address;
+};
+
+#include <linux/kdebug.h>
+#include <asm/reg.h>
+#include <asm/system.h>
+
+static inline int hw_breakpoint_slots(int type)
+{
+ return HBP_NUM;
+}
+struct perf_event;
+struct pmu;
+struct perf_sample_data;
+
+#define HW_BREAKPOINT_ALIGN 0x7
+/* Maximum permissible length of any HW Breakpoint */
+#define HW_BREAKPOINT_LEN 0x8
+
+extern int arch_bp_generic_fields(int type, int *gen_bp_type);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+ unsigned long val, void *data);
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
+
+extern struct pmu perf_ops_bp;
+extern void ptrace_triggered(struct perf_event *bp, int nmi,
+ struct perf_sample_data *data, struct pt_regs *regs);
+static inline void hw_breakpoint_disable(void)
+{
+ set_dabr(0);
+}
+
+#else /* CONFIG_HAVE_HW_BREAKPOINT */
+static inline void hw_breakpoint_disable(void) { }
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+#endif /* __KERNEL__ */
+#endif /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
===================================================================
--- /dev/null
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/hw_breakpoint.c
@@ -0,0 +1,320 @@
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers. Derived from
+ * "arch/x86/kernel/hw_breakpoint.c"
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright 2010 IBM Corporation
+ * Author: K.Prasad <prasad@linux.vnet.ibm.com>
+ *
+ */
+
+#include <linux/hw_breakpoint.h>
+#include <linux/notifier.h>
+#include <linux/kprobes.h>
+#include <linux/percpu.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm/hw_breakpoint.h>
+#include <asm/processor.h>
+#include <asm/sstep.h>
+
+/*
+ * Stores the breakpoints currently in use on each breakpoint address
+ * register for every cpu
+ */
+static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
+
+/*
+ * Install a perf counter breakpoint.
+ *
+ * We seek a free debug address register and use it for this
+ * breakpoint.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+ struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+ struct perf_event **slot = &__get_cpu_var(bp_per_reg);
+
+ *slot = bp;
+
+ /*
+ * Do not install DABR values if the instruction must be single-stepped.
+ * If so, DABR will be populated in single_step_dabr_instruction().
+ */
+ if (current->thread.last_hit_ubp != bp)
+ set_dabr(info->address | info->type | DABR_TRANSLATION);
+
+ return 0;
+}
+
+/*
+ * Uninstall the breakpoint contained in the given counter.
+ *
+ * First we search the debug address register it uses and then we disable
+ * it.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+ struct perf_event **slot = &__get_cpu_var(bp_per_reg);
+
+ if (*slot != bp) {
+ WARN_ONCE(1, "Can't find the breakpoint");
+ return;
+ }
+
+ *slot = NULL;
+ set_dabr(0);
+}
+
+/*
+ * Perform cleanup of arch-specific counters during unregistration
+ * of the perf-event
+ */
+void arch_unregister_hw_breakpoint(struct perf_event *bp)
+{
+ /*
+ * If the breakpoint is unregistered between a hw_breakpoint_handler()
+ * and the single_step_dabr_instruction(), then cleanup the breakpoint
+ * restoration variables to prevent dangling pointers.
+ */
+ if (bp->ctx->task)
+ bp->ctx->task->thread.last_hit_ubp = NULL;
+}
+
+/*
+ * Check for virtual address in kernel space.
+ */
+int arch_check_bp_in_kernelspace(struct perf_event *bp)
+{
+ struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+ return is_kernel_addr(info->address);
+}
+
+int arch_bp_generic_fields(int type, int *gen_bp_type)
+{
+ switch (type) {
+ case DABR_DATA_READ:
+ *gen_bp_type = HW_BREAKPOINT_R;
+ break;
+ case DABR_DATA_WRITE:
+ *gen_bp_type = HW_BREAKPOINT_W;
+ break;
+ case (DABR_DATA_WRITE | DABR_DATA_READ):
+ *gen_bp_type = (HW_BREAKPOINT_W | HW_BREAKPOINT_R);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings
+ */
+int arch_validate_hwbkpt_settings(struct perf_event *bp)
+{
+ int ret = -EINVAL;
+ struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+ if (!bp)
+ return ret;
+
+ switch (bp->attr.bp_type) {
+ case HW_BREAKPOINT_R:
+ info->type = DABR_DATA_READ;
+ break;
+ case HW_BREAKPOINT_W:
+ info->type = DABR_DATA_WRITE;
+ break;
+ case HW_BREAKPOINT_R | HW_BREAKPOINT_W:
+ info->type = (DABR_DATA_READ | DABR_DATA_WRITE);
+ break;
+ default:
+ return ret;
+ }
+
+ info->address = bp->attr.bp_addr;
+ info->len = bp->attr.bp_len;
+
+ /*
+ * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
+ * and breakpoint addresses are aligned to nearest double-word
+ * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
+ * 'symbolsize' should satisfy the check below.
+ */
+ if (info->len >
+ (HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
+ return -EINVAL;
+ return 0;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_handler(struct die_args *args)
+{
+ bool is_ptrace_bp = false;
+ int rc = NOTIFY_STOP;
+ struct perf_event *bp;
+ struct pt_regs *regs = args->regs;
+ int stepped = 1;
+ struct arch_hw_breakpoint *info;
+
+ /* Disable breakpoints during exception handling */
+ set_dabr(0);
+ /*
+ * The counter may be concurrently released but that can only
+ * occur from a call_rcu() path. We can then safely fetch
+ * the breakpoint, use its callback, touch its counter
+ * while we are in an rcu_read_lock() path.
+ */
+ rcu_read_lock();
+
+ bp = __get_cpu_var(bp_per_reg);
+ if (!bp)
+ goto out;
+ info = counter_arch_bp(bp);
+ is_ptrace_bp = (bp->overflow_handler == ptrace_triggered) ?
+ true : false;
+
+ /*
+ * Return early after invoking user-callback function without restoring
+ * DABR if the breakpoint is from ptrace which always operates in
+ * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
+ * generated in do_dabr().
+ */
+ if (is_ptrace_bp) {
+ perf_bp_event(bp, regs);
+ rc = NOTIFY_DONE;
+ goto out;
+ }
+
+ /* Do not emulate user-space instructions, instead single-step them */
+ if (user_mode(regs)) {
+ bp->ctx->task->thread.last_hit_ubp = bp;
+ regs->msr |= MSR_SE;
+ goto out;
+ }
+
+ stepped = emulate_step(regs, regs->nip);
+ /*
+ * emulate_step() could not execute it. We've failed in reliably
+ * handling the hw-breakpoint. Unregister it and throw a warning
+ * message to let the user know about it.
+ */
+ if (!stepped) {
+ WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
+ "0x%lx will be disabled.", info->address);
+ perf_event_disable(bp);
+ goto out;
+ }
+ /*
+ * As a policy, the callback is invoked in a 'trigger-after-execute'
+ * fashion
+ */
+ perf_bp_event(bp, regs);
+
+ set_dabr(info->address | info->type | DABR_TRANSLATION);
+out:
+ rcu_read_unlock();
+ return rc;
+}
+
+/*
+ * Handle single-step exceptions following a DABR hit.
+ */
+int __kprobes single_step_dabr_instruction(struct die_args *args)
+{
+ struct pt_regs *regs = args->regs;
+ struct perf_event *bp = NULL;
+ struct arch_hw_breakpoint *bp_info;
+
+ bp = current->thread.last_hit_ubp;
+ /*
+ * Check if we are single-stepping as a result of a
+ * previous HW Breakpoint exception
+ */
+ if (!bp)
+ return NOTIFY_DONE;
+
+ bp_info = counter_arch_bp(bp);
+
+ /*
+ * We shall invoke the user-defined callback function in the single
+ * stepping handler to confirm to 'trigger-after-execute' semantics
+ */
+ perf_bp_event(bp, regs);
+
+ /*
+ * Do not disable MSR_SE if the process was already in
+ * single-stepping mode.
+ */
+ if (!test_thread_flag(TIF_SINGLESTEP))
+ regs->msr &= ~MSR_SE;
+
+ set_dabr(bp_info->address | bp_info->type | DABR_TRANSLATION);
+ current->thread.last_hit_ubp = NULL;
+ return NOTIFY_STOP;
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_exceptions_notify(
+ struct notifier_block *unused, unsigned long val, void *data)
+{
+ int ret = NOTIFY_DONE;
+
+ switch (val) {
+ case DIE_DABR_MATCH:
+ ret = hw_breakpoint_handler(data);
+ break;
+ case DIE_SSTEP:
+ ret = single_step_dabr_instruction(data);
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * Release the user breakpoints used by ptrace
+ */
+void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+ struct thread_struct *t = &tsk->thread;
+
+ unregister_hw_breakpoint(t->ptrace_bps[0]);
+ t->ptrace_bps[0] = NULL;
+}
+
+void hw_breakpoint_pmu_read(struct perf_event *bp)
+{
+ /* TODO */
+}
+
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/Makefile
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/Makefile
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/Makefile
@@ -34,6 +34,7 @@ obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
signal_64.o ptrace32.o \
paca.o nvram_64.o firmware.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/processor.h
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/processor.h
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/processor.h
@@ -209,6 +209,14 @@ struct thread_struct {
#ifdef CONFIG_PPC64
unsigned long start_tb; /* Start purr when proc switched in */
unsigned long accum_tb; /* Total accumilated purr for process */
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ struct perf_event *ptrace_bps[HBP_NUM];
+ /*
+ * Helps identify source of single-step exception and subsequent
+ * hw-breakpoint enablement
+ */
+ struct perf_event *last_hit_ubp;
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
unsigned long dabr; /* Data address breakpoint register */
#ifdef CONFIG_ALTIVEC
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/ptrace.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/ptrace.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/ptrace.c
@@ -32,6 +32,8 @@
#ifdef CONFIG_PPC32
#include <linux/module.h>
#endif
+#include <linux/hw_breakpoint.h>
+#include <linux/perf_event.h>
#include <asm/uaccess.h>
#include <asm/page.h>
@@ -866,9 +868,34 @@ void user_disable_single_step(struct tas
clear_tsk_thread_flag(task, TIF_SINGLESTEP);
}
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+void ptrace_triggered(struct perf_event *bp, int nmi,
+ struct perf_sample_data *data, struct pt_regs *regs)
+{
+ struct perf_event_attr attr;
+
+ /*
+ * Disable the breakpoint request here since ptrace has defined a
+ * one-shot behaviour for breakpoint exceptions in PPC64.
+ * The SIGTRAP signal is generated automatically for us in do_dabr().
+ * We don't have to do anything about that here
+ */
+ attr = bp->attr;
+ attr.disabled = true;
+ modify_user_hw_breakpoint(bp, &attr);
+}
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
unsigned long data)
{
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ int ret;
+ struct thread_struct *thread = &(task->thread);
+ struct perf_event *bp;
+ struct perf_event_attr attr;
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
/* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
* For embedded processors we support one DAC and no IAC's at the
* moment.
@@ -896,6 +923,43 @@ int ptrace_set_debugreg(struct task_stru
/* Ensure breakpoint translation bit is set */
if (data && !(data & DABR_TRANSLATION))
return -EIO;
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ bp = thread->ptrace_bps[0];
+ if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
+ if (bp) {
+ unregister_hw_breakpoint(bp);
+ thread->ptrace_bps[0] = NULL;
+ }
+ return 0;
+ }
+ if (bp) {
+ attr = bp->attr;
+ attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
+ arch_bp_generic_fields(data &
+ (DABR_DATA_WRITE | DABR_DATA_READ),
+ &attr.bp_type);
+ ret = modify_user_hw_breakpoint(bp, &attr);
+ if (ret)
+ return ret;
+ thread->ptrace_bps[0] = bp;
+ thread->dabr = data;
+ return 0;
+ }
+
+ /* Create a new breakpoint request if one doesn't exist already */
+ hw_breakpoint_init(&attr);
+ attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
+ arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
+ &attr.bp_type);
+
+ thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
+ ptrace_triggered, task);
+ if (IS_ERR(bp)) {
+ thread->ptrace_bps[0] = NULL;
+ return PTR_ERR(bp);
+ }
+
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
/* Move contents to the DABR register */
task->thread.dabr = data;
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/process.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/process.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/process.c
@@ -37,6 +37,7 @@
#include <linux/kernel_stat.h>
#include <linux/personality.h>
#include <linux/random.h>
+#include <linux/hw_breakpoint.h>
#include <asm/pgtable.h>
#include <asm/uaccess.h>
@@ -462,8 +463,14 @@ struct task_struct *__switch_to(struct t
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
switch_booke_debug_regs(&new->thread);
#else
+/*
+ * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
+ * schedule DABR
+ */
+#ifndef CONFIG_HAVE_HW_BREAKPOINT
if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
set_dabr(new->thread.dabr);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
#endif
@@ -642,7 +649,11 @@ void flush_thread(void)
{
discard_lazy_cpu_state();
+#ifdef CONFIG_HAVE_HW_BREAKPOINTS
+ flush_ptrace_hw_breakpoint(current);
+#else /* CONFIG_HAVE_HW_BREAKPOINTS */
set_debug_reg_defaults(¤t->thread);
+#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
}
void
@@ -660,6 +671,9 @@ void prepare_to_copy(struct task_struct
flush_altivec_to_thread(current);
flush_vsx_to_thread(current);
flush_spe_to_thread(current);
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ flush_ptrace_hw_breakpoint(tsk);
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
}
/*
Index: linux-2.6.ppc64_test/arch/powerpc/include/asm/cputable.h
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/include/asm/cputable.h
+++ linux-2.6.ppc64_test/arch/powerpc/include/asm/cputable.h
@@ -516,6 +516,10 @@ static inline int cpu_has_feature(unsign
& feature);
}
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+#define HBP_NUM 1
+#endif /* CONFIG_HAVE_HW_BREAKPOINT */
+
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */
Index: linux-2.6.ppc64_test/arch/powerpc/kernel/machine_kexec_64.c
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/kernel/machine_kexec_64.c
+++ linux-2.6.ppc64_test/arch/powerpc/kernel/machine_kexec_64.c
@@ -25,6 +25,7 @@
#include <asm/sections.h> /* _end */
#include <asm/prom.h>
#include <asm/smp.h>
+#include <asm/hw_breakpoint.h>
int default_machine_kexec_prepare(struct kimage *image)
{
@@ -165,6 +166,7 @@ static void kexec_smp_down(void *arg)
while(kexec_all_irq_disabled == 0)
cpu_relax();
mb(); /* make sure all irqs are disabled before this */
+ hw_breakpoint_disable();
/*
* Now every CPU has IRQs off, we can clear out any pending
* IPIs and be sure that no more will come in after this.
@@ -180,6 +182,7 @@ static void kexec_prepare_cpus_wait(int
{
int my_cpu, i, notified=-1;
+ hw_breakpoint_disable();
my_cpu = get_cpu();
/* Make sure each CPU has atleast made it to the state we need */
for (i=0; i < NR_CPUS; i++) {
Index: linux-2.6.ppc64_test/arch/powerpc/lib/Makefile
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/lib/Makefile
+++ linux-2.6.ppc64_test/arch/powerpc/lib/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PPC64) += copypage_64.o cop
memcpy_64.o usercopy_64.o mem_64.o string.o
obj-$(CONFIG_XMON) += sstep.o
obj-$(CONFIG_KPROBES) += sstep.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o
ifeq ($(CONFIG_PPC64),y)
obj-$(CONFIG_SMP) += locks.o
Index: linux-2.6.ppc64_test/arch/powerpc/Kconfig
===================================================================
--- linux-2.6.ppc64_test.orig/arch/powerpc/Kconfig
+++ linux-2.6.ppc64_test/arch/powerpc/Kconfig
@@ -141,6 +141,7 @@ config PPC
select GENERIC_ATOMIC64 if PPC32
select HAVE_PERF_EVENTS
select HAVE_REGS_AND_STACK_ACCESS_API
+ select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
config EARLY_PRINTK
bool
^ permalink raw reply
* [Patch 1/5] Allow arch-specific cleanup before breakpoint unregistration
From: K.Prasad @ 2010-06-15 6:04 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, K.Prasad,
Roland McGrath
In-Reply-To: <20100615055010.108795721@linux.vnet.ibm.com>
Certain architectures (such as PowerPC Book III S) have a need to cleanup
data-structures before the breakpoint is unregistered. This patch introduces
an arch-specific hook in release_bp_slot() along with a weak definition in
the form of a stub funciton.
Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com>
Acked-by: Frederic Weisbecker <fweisbec@gmail.com>
---
kernel/hw_breakpoint.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: linux-2.6.ppc64_test/kernel/hw_breakpoint.c
===================================================================
--- linux-2.6.ppc64_test.orig/kernel/hw_breakpoint.c
+++ linux-2.6.ppc64_test/kernel/hw_breakpoint.c
@@ -242,6 +242,17 @@ toggle_bp_slot(struct perf_event *bp, bo
}
/*
+ * Function to perform processor-specific cleanup during unregistration
+ */
+__weak void arch_unregister_hw_breakpoint(struct perf_event *bp)
+{
+ /*
+ * A weak stub function here for those archs that don't define
+ * it inside arch/.../kernel/hw_breakpoint.c
+ */
+}
+
+/*
* Contraints to check before allowing this new breakpoint counter:
*
* == Non-pinned counter == (Considered as pinned for now)
@@ -339,6 +350,7 @@ void release_bp_slot(struct perf_event *
{
mutex_lock(&nr_bp_mutex);
+ arch_unregister_hw_breakpoint(bp);
__release_bp_slot(bp);
mutex_unlock(&nr_bp_mutex);
^ permalink raw reply
* [Patch 0/5] PPC64-HWBKPT: Hardware Breakpoint interfaces - ver XXIV
From: K.Prasad @ 2010-06-15 6:04 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, Paul Mackerras
Cc: Michael Neuling, Benjamin Herrenschmidt, shaggy,
Frederic Weisbecker, David Gibson, Alan Stern, Roland McGrath
Hi Paul,
Please find a new set of patches with changes as described below.
The patches have been tested for kernel- and user-mode breakpoints (after
applying the two patches you sent, refer message-id:
20100603004758.GA19618@brick.ozlabs.ibm.com and message-id:
20100615015459.GA30479@drongo) and are found to work fine!
Changelog - ver XXIV
--------------------
(Version XXII: 20100609102446.GA20332@in.ibm.com)
- A lockdep issue seen due to invocation of unregister_hw_breakpoint() in
exception context is now fixed (perf_event_disable() is used instead).
- Fixed improper handling of extraneous exceptions (through clearing of
extraneous exception flag and preventing the invocation of callback).
Kindly let me know if you have any further comments.
Thanks,
K.Prasad
Changelog - ver XXIII
--------------------
(Version XXII: 20100528063924.GA8679@in.ibm.com)
- Detection of extraneous breakpoint exceptions is now done using a boolean flag
in 'struct arch_hw_breakpoint'.
- A dangling put_cpu() (remnant from previous patch versions) in
arch_unregister_hw_breakpoint() is now removed.
Changelog - ver XXII
--------------------
(Version XXI: linuxppc-dev ref:20100525091314.GA29003@in.ibm.com)
- Extraneous breakpoint exceptions are now properly handled; causative
instruction will be single-stepped and debug register values restored.
- Restoration of breakpoints during signal handling through thread_change_pc()
had defects which are now fixed.
- Breakpoints are flushed through flush_ptrace_hw_breakpoint() call in both
flush_thread() and prepare_to_copy() functions. 'ptrace_bps[]' and
'last_hit_ubp' members are now promptly cleaned-up.
- Single-step exception is now conditionally emulated upon hitting
alignment_exception.
- Rebased to commit 31f46717997a83bdf6db0dd04810c0a329eb3148 of linux-2.6 tree.
Changelog - ver XXI
--------------------
(Version XX: linuxppc-dev ref:20100524103136.GA8131@in.ibm.com)
- Decision to emulate an instruction is now based on whether the causative
instruction is in user_mode() or not.
- Breakpoints don't have to be cleared during sigreturn. A 'double-hit' on
hw_breakpoint_handler() is harmless for non-ptrace instructions.
- Minor changes to aid code brevity.
Changelog - ver XX
--------------------
(Version XIX: linuxppc-dev ref: 20100524040137.GA20873@in.ibm.com)
- Non task-bound breakpoints will only be emulated. Breakpoint will be
unregistered with a warning if emulation fails.
Changelog - ver XIX
--------------------
(Version XVIII: linuxppc-dev ref: 20100512033055.GA6384@in.ibm.com)
- Increased coverage of breakpoints during concurrent alignment_exception
and signal handling (which previously had 'blind-spots').
- Support for kernel-thread breakpoints and kernel-space breakpoints inside the
context of a user-space process.
- Patches re-based to commit f4b87dee923342505e1ddba8d34ce9de33e75050, thereby
necessitating minor changes to arch_validate_hwbkpt_settings().
Changelog - ver XVIII
--------------------
(Version XVII: linuxppc-dev ref: 20100414034340.GA6571@in.ibm.com)
- Slight code restructuring for brevity and coding-style corrections.
- emulate_single_step() now notifies DIE_SSTEP to registered handlers;
causes single_step_dabr_instruction() to be invoked after alignment_exception.
- hw-breakpoint restoration variables are cleaned-up before unregistration
through arch_unregister_hw_breakpoint().
- SIGTRAP is no longer generated for non-ptrace user-space breakpoints.
Changelog - ver XVII
--------------------
(Version XVI: linuxppc-dev ref: 20100330095809.GA14403@in.ibm.com)
- CONFIG_HAVE_HW_BREAKPOINT is now used to define the scope of the new code
(in lieu of CONFIG_PPC_BOOK3S_64).
- CONFIG_HAVE_HW_BREAKPOINT is now dependant upon CONFIG_PERF_EVENTS and
CONFIG_PPC_BOOK3S_64 (to overcome build failures under certain configs).
- Included a target in arch/powerpc/lib/Makefile to build sstep.o when
HAVE_HW_BREAKPOINT.
- Added a dummy definition for hw_breakpoint_disable() when !HAVE_HW_BREAKPOINT.
- Tested builds under defconfigs for ppc64, cell and g5 (found no patch induced
failures).
Changelog - ver XVI
--------------------
(Version XV: linuxppc-dev ref: 20100323140639.GA21836@in.ibm.com)
- Used a new config option CONFIG_PPC_BOOK3S_64 (in lieu of
CONFIG_PPC64/CPU_FTR_HAS_DABR) to limit the scope of the new code.
- Disabled breakpoints before kexec of the machine using hw_breakpoint_disable().
- Minor optimisation in exception-64s.S to check for data breakpoint exceptions
in DSISR finally (after check for other causes) + changes in code comments and
representation of DSISR_DABRMATCH constant.
- Rebased to commit ae6be51ed01d6c4aaf249a207b4434bc7785853b of linux-2.6.
Changelog - ver XV
--------------------
(Version XIV: linuxppc-dev ref: 20100308181232.GA3406@in.ibm.com)
- Additional patch to disable interrupts during data breakpoint exception
handling.
- Moved HBP_NUM definition to cputable.h under a new CPU_FTR definition
(CPU_FTR_HAS_DABR).
- Filtering of extraneous exceptions (due to accesses outside symbol length) is
by-passed for ptrace requests.
- Removed flush_ptrace_hw_breakpoint() from __switch_to() due to incorrect
coding placement.
- Changes to code comments as per community reviews for previous version.
- Minor coding-style changes in hw_breakpoint.c as per review comments.
- Re-based to commit ae6be51ed01d6c4aaf249a207b4434bc7785853b of linux-2.6
Changelog - ver XIV
--------------------
(Version XIII: linuxppc-dev ref: 20100215055605.GB3670@in.ibm.com)
- Removed the 'name' field from 'struct arch_hw_breakpoint'.
- All callback invocations through bp->overflow_handler() are replaced with
perf_bp_event().
- Removed the check for pre-existing single-stepping mode in
hw_breakpoint_handler() as this check is unreliable while in kernel-space.
Side effect of this change is the non-triggering of hw-breakpoints while
single-stepping kernel through KGDB or Xmon.
- Minor code-cleanups and addition of comments in hw_breakpoint_handler() and
single_step_dabr_instruction().
- Re-based to commit 25cf84cf377c0aae5dbcf937ea89bc7893db5176 of linux-2.6
Changelog - ver XIII
--------------------
(Version XII: linuxppc-dev ref: 20100121084640.GA3252@in.ibm.com)
- Fixed a bug for user-space breakpoints (triggered following the failure of a
breakpoint request).
- Re-based on commit 724e6d3fe8003c3f60bf404bf22e4e331327c596 of linux-2.6
Changelog - ver XII
--------------------
(Version XI: linuxppc-dev ref: 20100119091234.GA9971@in.ibm.com)
- Unset MSR_SE only if kernel was not previously in single-step mode.
- Pre-emption is now enabled before returning from the hw-breakpoint exception
handler.
- Variables to track the source of single-step exception (breakpoint from kernel,
user-space vs single-stepping due to other requests) are added.
- Extraneous hw-breakpoint exceptions (due to memory accesses lying outside
monitored symbol length) is now done for both kernel and user-space
(previously only user-space).
- single_step_dabr_instruction() now returns NOTIFY_DONE if kernel was in
single-step mode even before the hw-breakpoint. This enables other users of
single-step mode to be notified of the exception.
- User-space instructions are not emulated from kernel-space, they are instead
single-stepped.
Changelog - ver XI
------------------
(Version X: linuxppc-dev ref: 20091211160144.GA23156@in.ibm.com)
- Conditionally unset MSR_SE in the single-step handler
- Added comments to explain the duration and need for pre-emption
disable following hw-breakpoint exception.
Changelog - ver X
------------------
- Re-write the PPC64 patches for the new implementation of hw-breakpoints that
uses the perf-layer.
- Rebased to commit 7622fc234190a37d4e9fe3ed944a2b61a63fca03 of -tip.
Changelog - ver IX
-------------------
- Invocation of user-defined callback will be 'trigger-after-execute' (except
for ptrace).
- Creation of a new global per-CPU breakpoint structure to help invocation of
user-defined callback from single-step handler.
(Changes made now)
- Validation before registration will fail only if the address does not match
the kernel symbol's (if specified) resolved address
(through kallsyms_lookup_name()).
- 'symbolsize' value is expected to within the range contained by the symbol's
starting address and the end of a double-word boundary (8 Bytes).
- PPC64's arch-dependant code is now aware of 'cpumask' in 'struct hw_breakpoint'
and can accomodate requests for a subset of CPUs in the system.
- Introduced arch_disable_hw_breakpoint() required for
<enable><disable>_hw_breakpoint() APIs.
Changelog - ver VIII
-------------------
- Reverting changes to allow one-shot breakpoints only for ptrace requests.
- Minor changes in sanity checking in arch_validate_hwbkpt_settings().
- put_cpu_no_resched() is no longer available. Converted to put_cpu().
Changelog - ver VII
-------------------
- Allow the one-shot behaviour for exception handlers to be defined by the user.
A new 'is_one_shot' flag is added to 'struct arch_hw_breakpoint'.
Changelog - ver VI
------------------
The task of identifying 'genuine' breakpoint exceptions from those caused by
'out-of-range' accesses turned out to be more tricky than originally thought.
Some changes to this effect were made in version IV of this patchset, but they
were not sufficient for user-space. Basically the breakpoint address received
through ptrace is always aligned to 8-bytes since ptrace receives an encoded
'data' (consisting of address | translation_enable | bkpt_type), and the size of
the symbol is not known. However for kernel-space addresses, the symbol-size can
be determined using kallsyms_lookup_size_offset() and this is used to check if
DAR (in the exception context) is
'bkpt_address <= DAR <= (bkpt_address + symbol_size)', failing which we conclude
it as a stray exception.
The following changes are made to enable check:
- Addition of a symbolsize field in 'struct arch_hw_breakpoint' field.
- Store the size of the 'watched' kernel symbol into 'symbolsize' field in
arch_store_info(0 routine.
- Verify if the above described condition is true when is_one_shot is FALSE in
hw_breakpoint_handler().
Changelog - ver V
------------------
- Breakpoint requests from ptrace (for user-space) are designed to be one-shot
in PPC64. The patch contains changes to retain this behaviour by returning early
in hw_breakpoint_handler() [without re-initialising DABR] and unregistering the
user-space request in ptrace_triggered(). It is safe to make a
unregister_user_hw_breakpoint() call from the breakpoint exception context
[through ptrace_triggered()] without giving rise to circular locking-dependancy.
This is because there can be no kernel code running on the CPU (which received
the exception) with the same spinlock held.
- Minor change in 'type' member of 'struct arch_hw_breakpoint' from u8 to 'int'.
Changelog - ver IV
------------------
- While DABR register requires double-word (8 bytes) aligned addresses, i.e.
the breakpoint is active over a range of 8 bytes, PPC64 allows byte-level
addressability. This may lead to stray exceptions which have to be ignored in
hw_breakpoint_handler(), when DAR != (Breakpoint request address). However DABR
will be populated with the requested breakpoint address aligned to the previous
double-word address. The code is now modified to store user-requested address
in 'bp->info.address' but update the DABR with a double-word aligned address.
- Please note that the Data Breakpoint facility in Xmon is broken as of 2.6.29
and the same has not been integrated into this facility as described in Ver I.
Changelog - ver III
------------------
- Patches are based on commit 08f16e060bf54bdc34f800ed8b5362cdeda75d8b of -tip
tree.
- The declarations in arch/powerpc/include/asm/hw_breakpoint.h are done only if
CONFIG_PPC64 is defined. This eliminates the need to conditionally include this
header file.
- load_debug_registers() is done in start_secondary() i.e. during CPU
initialisation.
- arch_check_va_<> routines in hw_breakpoint.c are now replaced with a much
simpler is_kernel_addr() check in arch_validate_hwbkpt_settings()
- Return code of hw_breakpoint_handler() when triggered due to Lazy debug
register switching is now changed to NOTIFY_STOP.
- The ptrace code no longer sets the TIF_DEBUG task flag as it is proposed to
be done in register_user_hw_breakpoint() routine.
- hw_breakpoint_handler() is now modified to use hbp_kernel_pos value to
determine if the trigger was a user/kernel space address. The DAR register
value is checked with the address stored in 'struct hw_breakpoint' to avoid
handling of exceptions that belong to kprobe/Xmon.
Changelog - ver II
------------------
- Split the monolithic patch into six logical patches
- Changed the signature of arch_check_va_in_<user><kernel>space functions. They
are now marked static.
- HB_NUM is now called as HBP_NUM (to preserve a consistent short-name
convention)
- Introduced hw_breakpoint_disable() and changes to kexec code to disable
breakpoints before a reboot.
- Minor changes in ptrace code to use macro-defined constants instead of
numbers.
- Introduced a new constant definition INSTRUCTION_LEN in reg.h
^ permalink raw reply
* Re: [PATCH] powerpc: Fix mpic_resume on early G5 macs
From: Benjamin Herrenschmidt @ 2010-06-15 5:04 UTC (permalink / raw)
To: Alastair Bridgewater; +Cc: linuxppc-dev
In-Reply-To: <AANLkTimrq40Pd-ulPkfb8T2LJ0NSybd5InviirU7fK5D@mail.gmail.com>
On Sat, 2010-06-12 at 21:36 -0400, Alastair Bridgewater wrote:
> mpic_resume() on G5 macs blindly dereferences mpic->fixups, but
> it may legitimately be NULL (as on PowerMac7,2). Add an explicit
> check.
>
> This fixes susend-to-disk with one processor (maxcpus=1) for me.
Thanks. Patch is terribly mangled tho (word wrapped and tabs have been
replaced with spaces). I fixed it up manually but check your email setup
next time.
Cheers,
Ben.
> Signed-off-by: Alastair Bridgewater <alastair.bridgewater@gmail.com>
> ---
> diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
> index 4fd57ab..28668ba 100644
> --- a/arch/powerpc/sysdev/mpic.c
> +++ b/arch/powerpc/sysdev/mpic.c
> @@ -1666,7 +1666,7 @@ static int mpic_resume(struct sys_device *dev)
> mpic->save_data[i].dest);
>
> #ifdef CONFIG_MPIC_U3_HT_IRQS
> - {
> + if (mpic->fixups) {
> struct mpic_irq_fixup *fixup = &mpic->fixups[i];
>
> if (fixup->base) {
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: Request review of device tree documentation
From: David Gibson @ 2010-06-15 2:02 UTC (permalink / raw)
To: Nicolas Pitre
Cc: microblaze-uclinux, devicetree-discuss, linuxppc-dev,
Mitch Bradley, Dan Malek, Jeremy Kerr, linux-arm-kernel
In-Reply-To: <alpine.LFD.2.00.1006141044510.13427@xanadu.home>
On Mon, Jun 14, 2010 at 10:59:20AM -0400, Nicolas Pitre wrote:
> On Mon, 14 Jun 2010, David Gibson wrote:
>
> > On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
> > [sni]
> > > > That's sort of a self-fulfilling prophecy. If the OS doesn't trust the
> > > > firmware, there is no pressure for the firmware to "get it right".
> > >
> > > Firmware will not get it right. Period. There will always be
> > > something wrong. It is never right on PCs. It will never be right on
> > > the other architectures.
> >
> > Yes, yes, yes. And there is a great deal of empirical evidence to
> > back that assertion.
> >
> > > That goes for OSes too, but upgrading an OS
> > > isn't as risky as upgrading firmware. That isn't to say that it can't
> > > be close, but every firmware feature that the OS depends on is a
> > > feature that could force a risky firmware upgrade when the bug in it
> > > is discovered.
> >
> > Indeed. In fact, the general rule of thumb is really "put as much as
> > possible into the most easily replaced layer of the stack". This is,
> > incidentally, why I've always been dubious about simple firmwares
> > supplying a flattened device tree rather than including the device
> > tree template in the kernel, cuboot style.
>
> The biggest advantage, IMHO, for adding DT to ARM, is actually to
> decouple the hardware config information and the kernel. If in the end
> the DT has to be shipped in the kernel then we're losing all this
> advantage over the current state of things on ARM which still works
> pretty well otherwise.
Right, which is why I'm just dubious, not dead against it. If
firmware supplies a device tree that's so awful you have to replace
most of it, then you haven't won much over having a kernel wrapper
which uses ad-hoc logic to detect the board type from whatever random
clues the firmware leaves and selects a device tree from it's library
of them based on that. On ARM this sort of approach is probably more
effective than powerpc, even, since you could use the machine number
to select from a bag of canned device trees and still have a
multi-board kernel.
> In the best case, the simple firmware simply has to retrieve the
> flattened device tree from flash, and pass it to the kernel just like
> some anonymous blob. And the simple firmware only needs to provide a
> way for that DT blob to be updatable, like through an upload of a
> replacement blob that was prepared offline. Just like a ramdisk image
> or the like.
Yes, having the firmware DT independently updateable makes most of my
concerns about it go away.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [Patch 0/5] PPC64-HWBKPT: Hardware Breakpoint interfaces - ver XXII
From: Paul Mackerras @ 2010-06-15 1:54 UTC (permalink / raw)
To: K.Prasad; +Cc: linuxppc-dev@ozlabs.org, Benjamin Herrenschmidt
In-Reply-To: <20100604065145.GA2408@in.ibm.com>
On Fri, Jun 04, 2010 at 12:21:45PM +0530, K.Prasad wrote:
> Meanwhile I tested the per-cpu breakpoints with the new emulate_step
> patch (refer linuxppc-dev message-id:
> 20100602112903.GB30149@brick.ozlabs.ibm.com) and they continue to fail
> due to emulate_step() failure, in my case, on a "lwz r0,0(r28)"
> instruction.
You need to pass the instruction word to emulate_step(), not the
instruction address. Also you need to have the full GPR set
available. The patch below fixes these problems. I'll fold these
changes into your patch 2/5.
Paul.
---
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 3e423fb..f53029a 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -828,6 +828,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
/* We have a data breakpoint exception - handle it */
handle_dabr_fault:
+ bl .save_nvgprs
ld r4,_DAR(r1)
ld r5,_DSISR(r1)
addi r3,r1,STACK_FRAME_OVERHEAD
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index ef70cf0..489049c 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -35,6 +35,7 @@
#include <asm/hw_breakpoint.h>
#include <asm/processor.h>
#include <asm/sstep.h>
+#include <asm/uaccess.h>
/*
* Stores the breakpoints currently in use on each breakpoint address
@@ -203,6 +204,7 @@ int __kprobes hw_breakpoint_handler(struct die_args *args)
int stepped = 1;
struct arch_hw_breakpoint *info;
unsigned long dar = regs->dar;
+ unsigned int instr;
/* Disable breakpoints during exception handling */
set_dabr(0);
@@ -255,7 +257,11 @@ int __kprobes hw_breakpoint_handler(struct die_args *args)
goto out;
}
- stepped = emulate_step(regs, regs->nip);
+ stepped = 0;
+ instr = 0;
+ if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
+ stepped = emulate_step(regs, instr);
+
/*
* emulate_step() could not execute it. We've failed in reliably
* handling the hw-breakpoint. Unregister it and throw a warning
^ permalink raw reply related
* Re: [PATCH 1/2 v2] powerpc/5200: add mpc5200_psc_ac97_gpio_reset
From: Grant Likely @ 2010-06-14 23:39 UTC (permalink / raw)
To: Eric Millbrandt; +Cc: Mark Brown, linuxppc-dev
In-Reply-To: <1276552518-11441-2-git-send-email-emillbrandt@dekaresearch.com>
On Mon, Jun 14, 2010 at 3:55 PM, Eric Millbrandt
<emillbrandt@dekaresearch.com> wrote:
> Work around a silicon bug in the ac97 reset functionality of the
> mpc5200(b). =A0The implementation of the ac97 "cold" reset is flawed.
> If the sync and output lines are high when reset is asserted the
> attached ac97 device may go into test mode. =A0Avoid this by
> reconfiguring the psc to gpio mode and generating the reset manually.
>
> From MPC5200B User's Manual:
> "Some AC97 devices goes to a test mode, if the Sync line is high
> during the Res line is low (reset phase). To avoid this behavior the
> Sync line must be also forced to zero during the reset phase. To do
> that, the pin muxing should switch to GPIO mode and the GPIO control
> register should be used to control the output lines."
>
> Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
> ---
>
> changes since v1
> - Refactored to manipulate port_config and gpio pins internally instead o=
f
> =A0exporting an API.
>
> =A0arch/powerpc/include/asm/mpc52xx.h =A0 =A0 =A0 =A0 =A0 | =A0 =A01 +
> =A0arch/powerpc/platforms/52xx/mpc52xx_common.c | =A0103 ++++++++++++++++=
++++++++++
> =A02 files changed, 104 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/as=
m/mpc52xx.h
> index b664ce7..1f41382 100644
> --- a/arch/powerpc/include/asm/mpc52xx.h
> +++ b/arch/powerpc/include/asm/mpc52xx.h
> @@ -271,6 +271,7 @@ struct mpc52xx_intr {
> =A0/* mpc52xx_common.c */
> =A0extern void mpc5200_setup_xlb_arbiter(void);
> =A0extern void mpc52xx_declare_of_platform_devices(void);
> +extern int mpc5200_psc_ac97_gpio_reset(int psc_number);
> =A0extern void mpc52xx_map_common_devices(void);
> =A0extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
> =A0extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
> diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/=
platforms/52xx/mpc52xx_common.c
> index a46bad0..a9866fa 100644
> --- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
> +++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
> @@ -12,9 +12,11 @@
>
> =A0#undef DEBUG
>
> +#include <linux/gpio.h>
> =A0#include <linux/kernel.h>
> =A0#include <linux/spinlock.h>
> =A0#include <linux/of_platform.h>
> +#include <linux/of_gpio.h>
> =A0#include <asm/io.h>
> =A0#include <asm/prom.h>
> =A0#include <asm/mpc52xx.h>
> @@ -37,6 +39,11 @@ static struct of_device_id mpc52xx_bus_ids[] __initdat=
a =3D {
> =A0 =A0 =A0 =A0{}
> =A0};
>
> +static struct of_device_id mpc52xx_gpio_simple[] =3D {
> + =A0 =A0 =A0 { .compatible =3D "fsl,mpc5200-gpio", },
> + =A0 =A0 =A0 {}
> +};
> +
> =A0/*
> =A0* This variable is mapped in mpc52xx_map_wdt() and used in mpc52xx_res=
tart().
> =A0* Permanent mapping is required because mpc52xx_restart() can be calle=
d
> @@ -82,6 +89,13 @@ mpc5200_setup_xlb_arbiter(void)
> =A0 =A0 =A0 =A0iounmap(xlb);
> =A0}
>
> +/*
> + * This variable is mapped in mpc52xx_write_port_config() and
> + * mpc52xx_read_port_config().
> + */
> +DEFINE_SPINLOCK(mpc52xx_gpio_lock);
You don't need to define a new spin lock. Hold the spin lock already
defined in mpc52xx_gpio.c (see below)
> +static u32 __iomem *port_config;
> +
> =A0/**
> =A0* mpc52xx_declare_of_platform_devices: register internal devices and c=
hildren
> =A0* =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 of the localplus bus to the of_platform
> @@ -117,6 +131,7 @@ void __init
> =A0mpc52xx_map_common_devices(void)
> =A0{
> =A0 =A0 =A0 =A0struct device_node *np;
> + =A0 =A0 =A0 const u32 *regaddr;
>
> =A0 =A0 =A0 =A0/* mpc52xx_wdt is mapped here and used in mpc52xx_restart,
> =A0 =A0 =A0 =A0 * possibly from a interrupt context. wdt is only implemen=
t
> @@ -135,6 +150,13 @@ mpc52xx_map_common_devices(void)
> =A0 =A0 =A0 =A0np =3D of_find_matching_node(NULL, mpc52xx_cdm_ids);
> =A0 =A0 =A0 =A0mpc52xx_cdm =3D of_iomap(np, 0);
> =A0 =A0 =A0 =A0of_node_put(np);
> +
> + =A0 =A0 =A0 /* port_config register */
> + =A0 =A0 =A0 np =3D of_find_matching_node(NULL, mpc52xx_gpio_simple);
> + =A0 =A0 =A0 regaddr =3D of_get_address(np, 0, NULL, NULL);
> + =A0 =A0 =A0 port_config =3D ioremap((u32) of_translate_address(np, rega=
ddr), 0x4);
> +
> + =A0 =A0 =A0 of_node_put(np);
> =A0}
>
> =A0/**
> @@ -233,3 +255,84 @@ mpc52xx_restart(char *cmd)
>
> =A0 =A0 =A0 =A0while (1);
> =A0}
> +
> +#define PSC1_RESET =A0 =A0 254
> +#define PSC1_SYNC =A0 =A0 =A0244
> +#define PSC1_SDATA_OUT 246
> +#define PSC2_RESET =A0 =A0 253
> +#define PSC2_SYNC =A0 =A0 =A0240
> +#define PSC2_SDATA_OUT 242
These numbers are dynamically assigned. You cannot rely on them being
fixed. You'll need to use the hardware GPIO numbers.
However, as long as you're holding the existing gpio_lock, I've got no
problem with you sidestepping the GPIO api and accessing the registers
directly. It doesn't need to integrate with the gpio api because the
value of those GPIO signals is irrelevant after port_config is
switched back to PSC ac97 mode. (Just make sure you use
setbits32()/clrbits32() so you don't disturb the other GPIO line
settings.)
Cheers,
g.
> +#define MPC52xx_GPIO_PSC1_MASK 0x7
> +#define MPC52xx_GPIO_PSC2_MASK (0x7<<4)
> +
> +/**
> + * mpc5200_psc_ac97_gpio_reset: Use gpio pins to reset the ac97 bus
> + *
> + * @psc: psc number to reset (only psc 1 and 2 support ac97)
> + */
> +int mpc5200_psc_ac97_gpio_reset(int psc_number)
> +{
> + =A0 =A0 =A0 unsigned long flags;
> + =A0 =A0 =A0 u32 gpio;
> + =A0 =A0 =A0 u32 mux;
> + =A0 =A0 =A0 int out;
> + =A0 =A0 =A0 int reset;
> + =A0 =A0 =A0 int sync;
> +
> + =A0 =A0 =A0 if (!port_config)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return -ENODEV;
> +
> + =A0 =A0 =A0 switch (psc_number) {
> + =A0 =A0 =A0 case 0:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reset =A0 =3D PSC1_RESET; =A0 =A0 =A0 =A0 =
=A0 /* AC97_1_RES */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 sync =A0 =A0=3D PSC1_SYNC; =A0 =A0 =A0 =A0 =
=A0 =A0/* AC97_1_SYNC */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out =A0 =A0 =3D PSC1_SDATA_OUT; =A0 =A0 =A0=
/* AC97_1_SDATA_OUT */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 gpio =A0 =A0=3D MPC52xx_GPIO_PSC1_MASK;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> + =A0 =A0 =A0 case 1:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reset =A0 =3D PSC2_RESET; =A0 =A0 =A0 =A0 =
=A0 /* AC97_2_RES */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 sync =A0 =A0=3D PSC2_SYNC; =A0 =A0 =A0 =A0 =
=A0 =A0/* AC97_2_SYNC */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out =A0 =A0 =3D PSC2_SDATA_OUT; =A0 =A0 =A0=
/* AC97_2_SDATA_OUT */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 gpio =A0 =A0=3D MPC52xx_GPIO_PSC2_MASK;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> + =A0 =A0 =A0 default:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_ERR __FILE__ ": "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "Unable to determine PSC, no ac=
97 cold-reset will be "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "performed\n");
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return -ENODEV;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 gpio_request(reset, "reset");
> + =A0 =A0 =A0 gpio_request(sync, "sync");
> + =A0 =A0 =A0 gpio_request(out, "out");
> +
> + =A0 =A0 =A0 spin_lock_irqsave(&mpc52xx_gpio_lock, flags);
> +
> + =A0 =A0 =A0 mux =3D in_be32(port_config);
> +
> + =A0 =A0 =A0 /* Reconfiure pin-muxing to gpio */
> + =A0 =A0 =A0 out_be32(port_config, mux & (~gpio));
> +
> + =A0 =A0 =A0 /* Assert cold reset */
> + =A0 =A0 =A0 gpio_direction_output(sync, 0);
> + =A0 =A0 =A0 gpio_direction_output(out, 0);
> + =A0 =A0 =A0 gpio_direction_output(reset, 0);
> +
> + =A0 =A0 =A0 /* wait at lease 1 us */
> + =A0 =A0 =A0 udelay(2);
> +
> + =A0 =A0 =A0 /* Deassert reset */
> + =A0 =A0 =A0 gpio_direction_output(reset, 1);
> +
> + =A0 =A0 =A0 /* Restore pin-muxing */
> + =A0 =A0 =A0 out_be32(port_config, mux);
> +
> + =A0 =A0 =A0 spin_unlock_irqrestore(&mpc52xx_gpio_lock, flags);
> +
> + =A0 =A0 =A0 gpio_free(out);
> + =A0 =A0 =A0 gpio_free(sync);
> + =A0 =A0 =A0 gpio_free(reset);
> +
> + =A0 =A0 =A0 return 0;
> +}
> +EXPORT_SYMBOL(mpc5200_psc_ac97_gpio_reset);
> --
> -DISCLAIMER: an automatically appended disclaimer may follow. By posting-
> -to a public e-mail mailing list I hereby grant permission to distribute-
> -and copy this message.-
>
> 1.6.3.1
>
>
> This e-mail and the information, including any attachments, it contains a=
re intended to be a confidential communication only to the person or entity=
to whom it is addressed and may contain information that is privileged. If=
the reader of this message is not the intended recipient, you are hereby n=
otified that any dissemination, distribution or copying of this communicati=
on is strictly prohibited. If you have received this communication in error=
, please immediately notify the sender and destroy the original message.
>
> Thank you.
>
> Please consider the environment before printing this email.
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH 2/2 v3] sound/soc: mpc5200_psc_ac97: Use gpio pins for cold reset
From: Grant Likely @ 2010-06-14 23:09 UTC (permalink / raw)
To: Eric Millbrandt; +Cc: Mark Brown, linuxppc-dev
In-Reply-To: <1276552518-11441-3-git-send-email-emillbrandt@dekaresearch.com>
On Mon, Jun 14, 2010 at 3:55 PM, Eric Millbrandt
<emillbrandt@dekaresearch.com> wrote:
> Call the gpio reset platform function instead of using the flawed
> ac97 functionality of the MPC5200(b)
>
> From MPC5200B User's Manual:
> "Some AC97 devices goes to a test mode, if the Sync line is high
> during the Res line is low (reset phase). To avoid this behavior the
> Sync line must be also forced to zero during the reset phase. To do
> that, the pin muxing should switch to GPIO mode and the GPIO control
> register should be used to control the output lines."
>
> Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
> ---
>
> changes since v1
> - Amended with comments from Mark Brown
> - Fall back to the original reset implementation if no gpio pins are defi=
ned
> =A0in the device tree
>
> changes since v2
> - Refactored to move the port_config manipulation to platform code.
> - Remove the gpio pins from the device-tree
>
> =A0sound/soc/fsl/mpc5200_psc_ac97.c | =A0 33 ++++++++++++++++++++++++++++=
+----
> =A01 files changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/sound/soc/fsl/mpc5200_psc_ac97.c b/sound/soc/fsl/mpc5200_psc=
_ac97.c
> index e2ee220..380a127 100644
> --- a/sound/soc/fsl/mpc5200_psc_ac97.c
> +++ b/sound/soc/fsl/mpc5200_psc_ac97.c
> @@ -20,6 +20,7 @@
>
> =A0#include <asm/time.h>
> =A0#include <asm/delay.h>
> +#include <asm/mpc52xx.h>
> =A0#include <asm/mpc52xx_psc.h>
>
> =A0#include "mpc5200_dma.h"
> @@ -100,19 +101,43 @@ static void psc_ac97_warm_reset(struct snd_ac97 *ac=
97)
> =A0{
> =A0 =A0 =A0 =A0struct mpc52xx_psc __iomem *regs =3D psc_dma->psc_regs;
>
> + =A0 =A0 =A0 mutex_lock(&psc_dma->mutex);
> +
> =A0 =A0 =A0 =A0out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR=
);
> =A0 =A0 =A0 =A0udelay(3);
> =A0 =A0 =A0 =A0out_be32(®s->sicr, psc_dma->sicr);
> +
> + =A0 =A0 =A0 mutex_unlock(&psc_dma->mutex);
> =A0}
>
> +#define =A0MPC52xx_PSC_SICR_ACRB (0x8 << 24)
Put this #define with the rest of the MPC52xx_PSC_SICR_* #defines.
> =A0static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
> =A0{
> =A0 =A0 =A0 =A0struct mpc52xx_psc __iomem *regs =3D psc_dma->psc_regs;
>
> - =A0 =A0 =A0 /* Do a cold reset */
> - =A0 =A0 =A0 out_8(®s->op1, MPC52xx_PSC_OP_RES);
> - =A0 =A0 =A0 udelay(10);
> - =A0 =A0 =A0 out_8(®s->op0, MPC52xx_PSC_OP_RES);
> + =A0 =A0 =A0 mutex_lock(&psc_dma->mutex);
> +
> + =A0 =A0 =A0 switch (psc_dma->id) {
> + =A0 =A0 =A0 case 0:
> + =A0 =A0 =A0 case 1:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 mpc5200_psc_ac97_gpio_reset(psc_dma->id);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 dev_info(psc_dma->dev, "cold reset\n");
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Notify the PSC that a reset has occurred=
*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_be32(®s->sicr, psc_dma->sicr | MPC52=
xx_PSC_SICR_ACRB);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Re-enable RX and TX */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_8(®s->command, MPC52xx_PSC_TX_ENABLE=
| MPC52xx_PSC_RX_ENABLE);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> + =A0 =A0 =A0 default:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 dev_err(psc_dma->dev,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "Unable to determine PSC, n=
o cold-reset will be "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "performed\n");
> + =A0 =A0 =A0 }
You can drop the switch block and the error message. You do exactly
the same thing in the common code. Just call
mpc5200_psc_ac97_gpio_reset() unconditionally.
Otherwise, this version looks pretty good. After you've respun both
patches (I've got comments to make on the other too), and if it's okay
by Mark, then I can merge both patches through my tree.
Cheers,
g.
^ permalink raw reply
* Re: [PATCH 0/2 v2] mpc5200 ac97 gpio reset
From: Grant Likely @ 2010-06-14 22:08 UTC (permalink / raw)
To: Eric Millbrandt; +Cc: Mark Brown, linuxppc-dev
In-Reply-To: <1276552518-11441-1-git-send-email-emillbrandt@dekaresearch.com>
On Mon, Jun 14, 2010 at 3:55 PM, Eric Millbrandt
<emillbrandt@dekaresearch.com> wrote:
> These patches reimplement the reset fuction in the ac97 to use gpio pins
> instead of using the mpc5200 ac97 reset functionality in the psc. =A0This
> avoids a problem in which attached ac97 devices go into "test" mode appea=
r
> unresponsive.
>
> These patches were tested on a pcm030 baseboard and on custom hardware wi=
th
> a wm9715 audio codec/touchscreen controller.
>
> Eric Millbrandt
>
> ---
>
> changes since v1
> - Refactored to manipulate port_config and gpio pins internally instead o=
f
> =A0exporting an API.
> - Amended commit message with comments from Mark Brown
> - Refactored to move the port_config manipulation to platform code.
> - Remove the gpio pins from the device-tree
>
> Eric Millbrandt (2):
> =A0 =A0powerpc/5200: add mpc5200_psc_ac97_gpio_reset
> =A0 =A0sound/soc: mpc5200_psc_ac97: Use gpio pins for cold reset
>
> =A0arch/powerpc/include/asm/mpc52xx.h =A0 =A0 =A0 =A0 =A0 | =A0 =A01 +
> =A0arch/powerpc/platforms/52xx/mpc52xx_common.c | =A0103 ++++++++++++++++=
++++++++++
> =A0sound/soc/fsl/mpc5200_psc_ac97.c =A0 =A0 =A0 =A0 =A0 =A0 | =A0 33 ++++=
+++-
> =A03 files changed, 133 insertions(+), 4 deletions(-)
>
> -DISCLAIMER: an automatically appended disclaimer may follow. By posting-
> -to a public e-mail mailing list I hereby grant permission to distribute-
> -and copy this message.-
Hahahahaha! You're disclaimer to the disclaimer is awesome.
g.
>
>
>
> This e-mail and the information, including any attachments, it contains a=
re intended to be a confidential communication only to the person or entity=
to whom it is addressed and may contain information that is privileged. If=
the reader of this message is not the intended recipient, you are hereby n=
otified that any dissemination, distribution or copying of this communicati=
on is strictly prohibited. If you have received this communication in error=
, please immediately notify the sender and destroy the original message.
>
> Thank you.
>
> Please consider the environment before printing this email.
>
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* [PATCH 2/2 v3] sound/soc: mpc5200_psc_ac97: Use gpio pins for cold reset
From: Eric Millbrandt @ 2010-06-14 21:55 UTC (permalink / raw)
To: Grant Likely; +Cc: Mark Brown, linuxppc-dev, Eric Millbrandt
In-Reply-To: <1276552518-11441-2-git-send-email-emillbrandt@dekaresearch.com>
Call the gpio reset platform function instead of using the flawed
ac97 functionality of the MPC5200(b)
>From MPC5200B User's Manual:
"Some AC97 devices goes to a test mode, if the Sync line is high
during the Res line is low (reset phase). To avoid this behavior the
Sync line must be also forced to zero during the reset phase. To do
that, the pin muxing should switch to GPIO mode and the GPIO control
register should be used to control the output lines."
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
---
changes since v1
- Amended with comments from Mark Brown
- Fall back to the original reset implementation if no gpio pins are define=
d
in the device tree
changes since v2
- Refactored to move the port_config manipulation to platform code.
- Remove the gpio pins from the device-tree
sound/soc/fsl/mpc5200_psc_ac97.c | 33 +++++++++++++++++++++++++++++----
1 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/sound/soc/fsl/mpc5200_psc_ac97.c b/sound/soc/fsl/mpc5200_psc_a=
c97.c
index e2ee220..380a127 100644
--- a/sound/soc/fsl/mpc5200_psc_ac97.c
+++ b/sound/soc/fsl/mpc5200_psc_ac97.c
@@ -20,6 +20,7 @@
#include <asm/time.h>
#include <asm/delay.h>
+#include <asm/mpc52xx.h>
#include <asm/mpc52xx_psc.h>
#include "mpc5200_dma.h"
@@ -100,19 +101,43 @@ static void psc_ac97_warm_reset(struct snd_ac97 *ac97=
)
{
struct mpc52xx_psc __iomem *regs =3D psc_dma->psc_regs;
+ mutex_lock(&psc_dma->mutex);
+
out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR);
udelay(3);
out_be32(®s->sicr, psc_dma->sicr);
+
+ mutex_unlock(&psc_dma->mutex);
}
+#define MPC52xx_PSC_SICR_ACRB (0x8 << 24)
static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
{
struct mpc52xx_psc __iomem *regs =3D psc_dma->psc_regs;
- /* Do a cold reset */
- out_8(®s->op1, MPC52xx_PSC_OP_RES);
- udelay(10);
- out_8(®s->op0, MPC52xx_PSC_OP_RES);
+ mutex_lock(&psc_dma->mutex);
+
+ switch (psc_dma->id) {
+ case 0:
+ case 1:
+ mpc5200_psc_ac97_gpio_reset(psc_dma->id);
+ dev_info(psc_dma->dev, "cold reset\n");
+
+ /* Notify the PSC that a reset has occurred */
+ out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_ACRB=
);
+
+ /* Re-enable RX and TX */
+ out_8(®s->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_R=
X_ENABLE);
+
+ break;
+ default:
+ dev_err(psc_dma->dev,
+ "Unable to determine PSC, no cold-reset will be "
+ "performed\n");
+ }
+
+ mutex_unlock(&psc_dma->mutex);
+
msleep(1);
psc_ac97_warm_reset(ac97);
}
--
-DISCLAIMER: an automatically appended disclaimer may follow. By posting-
-to a public e-mail mailing list I hereby grant permission to distribute-
-and copy this message.-
1.6.3.1
This e-mail and the information, including any attachments, it contains are=
intended to be a confidential communication only to the person or entity t=
o whom it is addressed and may contain information that is privileged. If t=
he reader of this message is not the intended recipient, you are hereby not=
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* [PATCH 1/2 v2] powerpc/5200: add mpc5200_psc_ac97_gpio_reset
From: Eric Millbrandt @ 2010-06-14 21:55 UTC (permalink / raw)
To: Grant Likely; +Cc: Mark Brown, linuxppc-dev, Eric Millbrandt
In-Reply-To: <1276552518-11441-1-git-send-email-emillbrandt@dekaresearch.com>
Work around a silicon bug in the ac97 reset functionality of the
mpc5200(b). The implementation of the ac97 "cold" reset is flawed.
If the sync and output lines are high when reset is asserted the
attached ac97 device may go into test mode. Avoid this by
reconfiguring the psc to gpio mode and generating the reset manually.
>From MPC5200B User's Manual:
"Some AC97 devices goes to a test mode, if the Sync line is high
during the Res line is low (reset phase). To avoid this behavior the
Sync line must be also forced to zero during the reset phase. To do
that, the pin muxing should switch to GPIO mode and the GPIO control
register should be used to control the output lines."
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
---
changes since v1
- Refactored to manipulate port_config and gpio pins internally instead of
exporting an API.
arch/powerpc/include/asm/mpc52xx.h | 1 +
arch/powerpc/platforms/52xx/mpc52xx_common.c | 103 ++++++++++++++++++++++=
++++
2 files changed, 104 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/=
mpc52xx.h
index b664ce7..1f41382 100644
--- a/arch/powerpc/include/asm/mpc52xx.h
+++ b/arch/powerpc/include/asm/mpc52xx.h
@@ -271,6 +271,7 @@ struct mpc52xx_intr {
/* mpc52xx_common.c */
extern void mpc5200_setup_xlb_arbiter(void);
extern void mpc52xx_declare_of_platform_devices(void);
+extern int mpc5200_psc_ac97_gpio_reset(int psc_number);
extern void mpc52xx_map_common_devices(void);
extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/pl=
atforms/52xx/mpc52xx_common.c
index a46bad0..a9866fa 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -12,9 +12,11 @@
#undef DEBUG
+#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/mpc52xx.h>
@@ -37,6 +39,11 @@ static struct of_device_id mpc52xx_bus_ids[] __initdata =
=3D {
{}
};
+static struct of_device_id mpc52xx_gpio_simple[] =3D {
+ { .compatible =3D "fsl,mpc5200-gpio", },
+ {}
+};
+
/*
* This variable is mapped in mpc52xx_map_wdt() and used in mpc52xx_restar=
t().
* Permanent mapping is required because mpc52xx_restart() can be called
@@ -82,6 +89,13 @@ mpc5200_setup_xlb_arbiter(void)
iounmap(xlb);
}
+/*
+ * This variable is mapped in mpc52xx_write_port_config() and
+ * mpc52xx_read_port_config().
+ */
+DEFINE_SPINLOCK(mpc52xx_gpio_lock);
+static u32 __iomem *port_config;
+
/**
* mpc52xx_declare_of_platform_devices: register internal devices and chil=
dren
* of the localplus bus to the of_plat=
form
@@ -117,6 +131,7 @@ void __init
mpc52xx_map_common_devices(void)
{
struct device_node *np;
+ const u32 *regaddr;
/* mpc52xx_wdt is mapped here and used in mpc52xx_restart,
* possibly from a interrupt context. wdt is only implement
@@ -135,6 +150,13 @@ mpc52xx_map_common_devices(void)
np =3D of_find_matching_node(NULL, mpc52xx_cdm_ids);
mpc52xx_cdm =3D of_iomap(np, 0);
of_node_put(np);
+
+ /* port_config register */
+ np =3D of_find_matching_node(NULL, mpc52xx_gpio_simple);
+ regaddr =3D of_get_address(np, 0, NULL, NULL);
+ port_config =3D ioremap((u32) of_translate_address(np, regaddr), 0x=
4);
+
+ of_node_put(np);
}
/**
@@ -233,3 +255,84 @@ mpc52xx_restart(char *cmd)
while (1);
}
+
+#define PSC1_RESET 254
+#define PSC1_SYNC 244
+#define PSC1_SDATA_OUT 246
+#define PSC2_RESET 253
+#define PSC2_SYNC 240
+#define PSC2_SDATA_OUT 242
+#define MPC52xx_GPIO_PSC1_MASK 0x7
+#define MPC52xx_GPIO_PSC2_MASK (0x7<<4)
+
+/**
+ * mpc5200_psc_ac97_gpio_reset: Use gpio pins to reset the ac97 bus
+ *
+ * @psc: psc number to reset (only psc 1 and 2 support ac97)
+ */
+int mpc5200_psc_ac97_gpio_reset(int psc_number)
+{
+ unsigned long flags;
+ u32 gpio;
+ u32 mux;
+ int out;
+ int reset;
+ int sync;
+
+ if (!port_config)
+ return -ENODEV;
+
+ switch (psc_number) {
+ case 0:
+ reset =3D PSC1_RESET; /* AC97_1_RES */
+ sync =3D PSC1_SYNC; /* AC97_1_SYNC */
+ out =3D PSC1_SDATA_OUT; /* AC97_1_SDATA_OUT */
+ gpio =3D MPC52xx_GPIO_PSC1_MASK;
+ break;
+ case 1:
+ reset =3D PSC2_RESET; /* AC97_2_RES */
+ sync =3D PSC2_SYNC; /* AC97_2_SYNC */
+ out =3D PSC2_SDATA_OUT; /* AC97_2_SDATA_OUT */
+ gpio =3D MPC52xx_GPIO_PSC2_MASK;
+ break;
+ default:
+ printk(KERN_ERR __FILE__ ": "
+ "Unable to determine PSC, no ac97 cold-reset will be =
"
+ "performed\n");
+ return -ENODEV;
+ }
+
+ gpio_request(reset, "reset");
+ gpio_request(sync, "sync");
+ gpio_request(out, "out");
+
+ spin_lock_irqsave(&mpc52xx_gpio_lock, flags);
+
+ mux =3D in_be32(port_config);
+
+ /* Reconfiure pin-muxing to gpio */
+ out_be32(port_config, mux & (~gpio));
+
+ /* Assert cold reset */
+ gpio_direction_output(sync, 0);
+ gpio_direction_output(out, 0);
+ gpio_direction_output(reset, 0);
+
+ /* wait at lease 1 us */
+ udelay(2);
+
+ /* Deassert reset */
+ gpio_direction_output(reset, 1);
+
+ /* Restore pin-muxing */
+ out_be32(port_config, mux);
+
+ spin_unlock_irqrestore(&mpc52xx_gpio_lock, flags);
+
+ gpio_free(out);
+ gpio_free(sync);
+ gpio_free(reset);
+
+ return 0;
+}
+EXPORT_SYMBOL(mpc5200_psc_ac97_gpio_reset);
--
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