* Re: [v2 PATCH] ucc_geth: fix ethtool set ring param bug
From: Liang Li @ 2010-09-03 1:20 UTC (permalink / raw)
To: Ben Hutchings; +Cc: netdev, avorontsov, davem, linuxppc-dev
In-Reply-To: <1283450699.2272.18.camel@achroite.uk.solarflarecom.com>
On Thu, Sep 02, 2010 at 07:04:59PM +0100, Ben Hutchings wrote:
> On Fri, 2010-09-03 at 00:02 +0800, Liang Li wrote:
> > It's common sense that when we should do change to driver ring
> > desc/buffer etc only after 'stop/shutdown' the device. When we
> > do change while devices/driver is running, kernel oops occur:
> [...]
> > + printk(KERN_INFO "Reactivating interface %s.\n", netdev->name);
> > + ret = ucc_geth_open(netdev);
> > + if (ret) {
> > + printk(KERN_WARNING "uec_set_ringparam: set ring param for running"
> > + " interface %s failed. Please try again.\n", netdev->name);
> > + dev_close(netdev);
> [...]
>
> If ucc_geth_open() failed you MUST NOT call ucc_geth_close(), but that
> is what dev_close() is going to do. But the device is still flagged as
> running so 'ifconfig down' is going to call dev_close() as well. There
> is no way out.
dev_close is safe enough IMHO. Call dev_close repeatly won't cause
problem though.
>
> This is why I said you must call dev_close() and then dev_open()
> instead. Then if dev_open() fails, just print the error, e.g.:
>
> dev_close(netdev);
> ret = dev_open(netdev);
> if (ret)
> netdev_err(netdev,
> "uec_set_ringparam: failed to restart"
> " interface with new ring parameters\n");
>
> (And I think this really is a serious error, hence the 'err' rather than
> 'warning' severity.)
I checked NIC drivers in drivers/net, there is no such:
dev_close(netdev);
ret = dev_open(netdev)
if (ret)
netdev_err(...);
Instead, there are:
nic_driver_close/down(netdev);
ret = nic_driver_open/restart(netdev);
if (ret) {
waring;
dev_close(netdev);
}
>
> (By the way, I noticed there are other places where ucc_geth_close() and
> ucc_geth_open() are called, without error checking. These are also
> bugs, but that doesn't justify adding new bugs.)
I think I did not invite new bugs, as I mentioned before, can you show
scenario that the reopen fail and perfect cleanup way?
Thanks,
-Liang Li
>
> Ben.
>
> --
> Ben Hutchings, Senior Software Engineer, Solarflare Communications
> Not speaking for my employer; that's the marketing department's job.
> They asked us to note that Solarflare product names are trademarked.
^ permalink raw reply
* Re: [PATCH] APM821xx: Add support for new SoC APM821xx
From: Josh Boyer @ 2010-09-03 2:08 UTC (permalink / raw)
To: tmarri; +Cc: linuxppc-dev
In-Reply-To: <1283464653-18492-1-git-send-email-tmarri@apm.com>
On Thu, Sep 02, 2010 at 02:57:33PM -0700, tmarri@apm.com wrote:
>From: Tirumala Marri <tmarri@apm.com>
>
>This patch adds CPU, device tree, defconfig and bluestone board
>support for APM821xx SoC.
>
>Signed-off-by: Tirumala R Marri <tmarri@apm.com>
>---
>APM821xx is Applied Micro Circuits Corporations naming convention for
>new line of SoCs.
So is it a 440x6 core then? Or what core is inside the SoC?
josh
^ permalink raw reply
* linux-next: build failure after merge of the final tree (powerpc related)
From: Stephen Rothwell @ 2010-09-03 3:24 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, linuxppc-dev
Cc: linux-next, linux-kernel, Ian Munsie
Hi all,
After merging the final tree, today's linux-next build
(powerpc64 allnoconfig) failed like this:
arch/powerpc/kernel/built-in.o: In function `.sys_call_table':
(.text+0x8d48): undefined reference to `.compat_sys_recv'
Caused by commit 86250b9d12caa1a3dee12a7cf638b7dd70eaadb6 ("powerpc: Wire
up direct socket system calls").
I have applied this patch for today:
From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Fri, 3 Sep 2010 13:19:04 +1000
Subject: [PATCH] powerpc: define a compat_sys_recv cond_syscall
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
kernel/sys_ni.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c
index bad369e..c782fe9 100644
--- a/kernel/sys_ni.c
+++ b/kernel/sys_ni.c
@@ -50,6 +50,7 @@ cond_syscall(compat_sys_sendmsg);
cond_syscall(sys_recvmsg);
cond_syscall(sys_recvmmsg);
cond_syscall(compat_sys_recvmsg);
+cond_syscall(compat_sys_recv);
cond_syscall(compat_sys_recvfrom);
cond_syscall(compat_sys_recvmmsg);
cond_syscall(sys_socketcall);
--
1.7.1
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
^ permalink raw reply related
* RE: P1021MDS QE Ethernet Ports
From: Ioannis Kokkoris @ 2010-09-03 7:05 UTC (permalink / raw)
To: haiying.wang; +Cc: linuxppc-dev
In-Reply-To: <1283434368.2904.2.camel@udp120119uds.am.freescale.net>
> Subject: RE: P1021MDS QE Ethernet Ports
> From: Haiying.Wang@freescale.com
> To: johnkokko@hotmail.com
> CC: linuxppc-dev@lists.ozlabs.org
> Date: Thu=2C 2 Sep 2010 09:32:48 -0400
>
> On Thu=2C 2010-02-09 at 11:26 +0300=2C Ioannis Kokkoris wrote:
>>> From: johnkokko@hotmail.com
>>> To: linuxppc-dev@lists.ozlabs.org
>>> Subject: P1021MDS QE Ethernet Ports
>>> Date: Wed=2C 1 Sep 2010 15:11:56 +0300
>>>
>>>
>>> Hello=2C
>>>
>>> we are seeing a strange behavior when trying to use the QE Ethernet int=
erfaces.
>>> ENET5 (UCC5 - RMII) interface on P1021MDS boards does not come up if th=
ere is no physical link on the ENET1 (UCC1 - MII) Port.
>>> It seems that interrupts from ENET5 are normally received but the link =
comes up and works properly only if we have physical connection on ENET1.
>>>
>> So far I found the following:
>>
>> After adding traces=2C it seems that genphy_update_link() polls the corr=
ect device=2C with the correct address (0x03)=2C but although a physical li=
nk is present in ENET5=2C the polling is not successful until there is a li=
nk in ENET1 (address 0x02)!
>>
>> genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x7849 (withou=
t ENET1 Link)
>> genphy_update_link: Dev: Micrel KS8041 ADD: 3 Status read 0x786D (with E=
NET1 Link)
>>
>> How does the MDIO of ENET1 affect the management of the physical interfa=
ce in a different HW address?
> Which board version are you using? this problem is now fixed in the new b=
oard version but not available right now.=20
We are using a board revision 2 (pilot version). Our main concern is whethe=
r this issue affects the working UCC1 eth interface performance.
Do you think that removing or pulling-down R79 (pin 21@U11) will fix the pr=
oblem with ENET1?
> You can connect two UECs for your current development.
Do you mean that changing the ENET1 interface from UCC1 to UCC3 in dts may =
solve the problem?
thank you for your reply=2C
John
=
^ permalink raw reply
* How to define an I2C-to-SPI bridge device ?
From: André Schwarz @ 2010-09-03 8:36 UTC (permalink / raw)
To: DevTreeDiscuss, LinuxPPC List
Hi,
we're about to get new MPC8377 based hardware with various peripherals.
There are two I2C-to-SPI bridge devices (NXP SC18IS602) and I'm not sure
how to define a proper dts...
Of course it's an easy thing creating 2 child nodes on the CPU's I2C
device - but how can I represent the created SPI bus ?
Is the (possibly) required driver (of_sc18is60x_spi ?) supposed to be an
I2C slave or an SPI host driver ?
Any help is welcome.
--
Mit freundlichen Grüßen / Best regards
André Schwarz
___________________________________________
MATRIX VISION GmbH
- Entwicklung / Development -
Talstraße 16
D-71570 Oppenweiler
Fon: ++49-07191-9432-420
Fax: ++49-07191-9432-288
eMail: andre.schwarz@matrix-vision.de
web: www.matrix-vision.de
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich
^ permalink raw reply
* RE: [PATCH 1/3][MTD] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Zang Roy-R61911 @ 2010-09-03 10:33 UTC (permalink / raw)
To: Zang Roy-R61911, linux-mtd, Gala Kumar-B11780
Cc: Lan Chunhe-B25806, linuxppc-dev, akpm
In-Reply-To: <1281063096-26598-1-git-send-email-tie-fei.zang@freescale.com>
> -----Original Message-----
> From: Zang Roy-R61911
> Sent: Friday, August 06, 2010 10:52 AM
> To: linux-mtd@lists.infradead.org
> Cc: linuxppc-dev@ozlabs.org; akpm@linux-foundation.org; Gala
Kumar-B11780; Lan
> Chunhe-B25806
> Subject: [PATCH 1/3][MTD] P4080/eLBC: Make Freescale elbc interrupt
common to
> elbc devices
>=20
> From: Lan Chunhe-B25806 <b25806@freescale.com>
>=20
> Move Freescale elbc interrupt from nand dirver to elbc driver.
> Then all elbc devices can use the interrupt instead of ONLY nand.
>=20
> Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> send the patch to linux-mtd@lists.infradead.org
> it has been posted to linuxppc-dev@ozlabs.org and do not get any
comment.
Hi, Kumar
I can see that this patch delegates to you in the mail list.
Do you have any comment?
Today, I rebase the patch to Linux 2.6.26-rc3.
1/3, 3/3 are still OK for the latest tree.
For patch 2/3, some minor fix needs to change for of_dev to
platform_device.
Should I resend the patch?
Thanks.
Roy
^ permalink raw reply
* Re: [PATCH 1/3][MTD] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Anton Vorontsov @ 2010-09-03 11:27 UTC (permalink / raw)
To: Roy Zang; +Cc: B25806, linuxppc-dev, akpm, linux-mtd, B11780
In-Reply-To: <1281063096-26598-1-git-send-email-tie-fei.zang@freescale.com>
On Fri, Aug 06, 2010 at 10:51:34AM +0800, Roy Zang wrote:
> From: Lan Chunhe-B25806 <b25806@freescale.com>
>
> Move Freescale elbc interrupt from nand dirver to elbc driver.
> Then all elbc devices can use the interrupt instead of ONLY nand.
>
> Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
> send the patch to linux-mtd@lists.infradead.org
> it has been posted to linuxppc-dev@ozlabs.org and do not get any comment.
>
> arch/powerpc/Kconfig | 7 +-
> arch/powerpc/include/asm/fsl_lbc.h | 34 +++++-
> arch/powerpc/sysdev/fsl_lbc.c | 254 ++++++++++++++++++++++++++++++------
> 3 files changed, 253 insertions(+), 42 deletions(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 2031a28..5155b53 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -703,9 +703,12 @@ config 4xx_SOC
> bool
>
> config FSL_LBC
> - bool
> + bool "Freescale Local Bus support"
> + depends on FSL_SOC
> help
> - Freescale Localbus support
> + Enables reporting of errors from the Freescale local bus
> + controller. Also contains some common code used by
> + drivers for specific local bus peripherals.
>
> config FSL_GTM
> bool
[...]
> diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
> index dceb8d1..9c9e44f 100644
> --- a/arch/powerpc/sysdev/fsl_lbc.c
> +++ b/arch/powerpc/sysdev/fsl_lbc.c
> @@ -5,6 +5,10 @@
> *
> * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
> *
> + * Copyright (c) 2010 Freescale Semiconductor
> + *
> + * Authors: Jack Lan <Jack.Lan@freescale.com>
Would be prettier if you'd group copyright and authorship notices.
I.e.
Copyright 2008 MV
Copyright 2010 FSL
Authors: Anton
Jack
> + *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> * the Free Software Foundation; either version 2 of the License, or
> @@ -23,35 +27,8 @@
> #include <asm/fsl_lbc.h>
>
> static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
> -static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
> -
> -static char __initdata *compat_lbc[] = {
> - "fsl,pq2-localbus",
> - "fsl,pq2pro-localbus",
> - "fsl,pq3-localbus",
> - "fsl,elbc",
> -};
> -
> -static int __init fsl_lbc_init(void)
> -{
> - struct device_node *lbus;
> - int i;
> -
> - for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
> - lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
> - if (lbus)
> - goto found;
> - }
> - return -ENODEV;
> -
> -found:
> - fsl_lbc_regs = of_iomap(lbus, 0);
> - of_node_put(lbus);
> - if (!fsl_lbc_regs)
> - return -ENOMEM;
> - return 0;
> -}
> -arch_initcall(fsl_lbc_init);
> +struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
> +EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
>
> /**
> * fsl_lbc_find - find Localbus bank
> @@ -66,12 +43,12 @@ int fsl_lbc_find(phys_addr_t addr_base)
> {
> int i;
>
> - if (!fsl_lbc_regs)
> + if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
> return -ENODEV;
>
> - for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
> - __be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
> - __be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
> + for (i = 0; i < ARRAY_SIZE(fsl_lbc_ctrl_dev->regs->bank); i++) {
> + __be32 br = in_be32(&fsl_lbc_ctrl_dev->regs->bank[i].br);
> + __be32 or = in_be32(&fsl_lbc_ctrl_dev->regs->bank[i].or);
A dedicated variable for regs would make this much more readable?
>
> if (br & BR_V && (br & or & BR_BA) == addr_base)
> return i;
> @@ -99,17 +76,20 @@ int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
> if (bank < 0)
> return bank;
>
> - br = in_be32(&fsl_lbc_regs->bank[bank].br);
> + if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
> + return -ENODEV;
> +
> + br = in_be32(&fsl_lbc_ctrl_dev->regs->bank[bank].br);
>
> switch (br & BR_MSEL) {
> case BR_MS_UPMA:
> - upm->mxmr = &fsl_lbc_regs->mamr;
> + upm->mxmr = &fsl_lbc_ctrl_dev->regs->mamr;
Ditto, a very repetitive stuff, desires a variable for regs?
> break;
> case BR_MS_UPMB:
> - upm->mxmr = &fsl_lbc_regs->mbmr;
> + upm->mxmr = &fsl_lbc_ctrl_dev->regs->mbmr;
> break;
> case BR_MS_UPMC:
> - upm->mxmr = &fsl_lbc_regs->mcmr;
> + upm->mxmr = &fsl_lbc_ctrl_dev->regs->mcmr;
> break;
> default:
> return -EINVAL;
> @@ -143,14 +123,18 @@ EXPORT_SYMBOL(fsl_upm_find);
> * thus UPM pattern actually executed. Note that mar usage depends on the
> * pre-programmed AMX bits in the UPM RAM.
> */
> +
> int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
> {
> int ret = 0;
> unsigned long flags;
>
> + if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
> + return -ENODEV;
> +
> spin_lock_irqsave(&fsl_lbc_lock, flags);
>
> - out_be32(&fsl_lbc_regs->mar, mar);
> + out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
>
> switch (upm->width) {
> case 8:
> @@ -172,3 +156,197 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
> return ret;
> }
> EXPORT_SYMBOL(fsl_upm_run_pattern);
> +
> +static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
> +{
> + struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
Yep, something like this for the functions above.
> +
> + /* clear event registers */
> + setbits32(&lbc->ltesr, LTESR_CLEAR);
> + out_be32(&lbc->lteatr, 0);
> + out_be32(&lbc->ltear, 0);
> + out_be32(&lbc->lteccr, LTECCR_CLEAR);
> + out_be32(&lbc->ltedr, LTEDR_ENABLE);
> +
> + /* Enable interrupts for any detected events */
> + out_be32(&lbc->lteir, LTEIR_ENABLE);
> +
> + return 0;
> +}
> +
> +static int __devexit fsl_lbc_ctrl_remove(struct of_device *ofdev)
> +{
> + struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&ofdev->dev);
> +
> + if (ctrl->irq)
> + free_irq(ctrl->irq, ctrl);
> +
> + if (ctrl->regs)
> + iounmap(ctrl->regs);
> +
> + dev_set_drvdata(&ofdev->dev, NULL);
> + kfree(ctrl);
> +
> + return 0;
> +}
> +
> +/* NOTE: This interrupt is used to report localbus events of various kinds,
> + * such as transaction errors on the chipselects.
> + */
/*
* multi line comments
* should be like this
*/
[...]
> +/* fsl_lbc_ctrl_probe
> + *
> + * called by device layer when it finds a device matching
> + * one our driver can handled. This code allocates all of
> + * the resources needed for the controller only. The
> + * resources for the NAND banks themselves are allocated
> + * in the chip probe function.
> +*/
ditto.
> +static int __devinit fsl_lbc_ctrl_probe(struct of_device *ofdev,
> + const struct of_device_id *match)
> +{
> + int ret = 0;
no need for the initial value here.
> +
> + fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
> + if (!fsl_lbc_ctrl_dev)
> + return -ENOMEM;
> +
> + dev_set_drvdata(&ofdev->dev, fsl_lbc_ctrl_dev);
> +
> + spin_lock_init(&fsl_lbc_ctrl_dev->lock);
> + init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
> +
> + fsl_lbc_ctrl_dev->regs = of_iomap(ofdev->dev.of_node, 0);
> + if (!fsl_lbc_ctrl_dev->regs) {
> + dev_err(&ofdev->dev, "failed to get memory region\n");
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + fsl_lbc_ctrl_dev->irq = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
> + if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
> + dev_err(&ofdev->dev, "failed to get irq resource\n");
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + fsl_lbc_ctrl_dev->dev = &ofdev->dev;
> +
> + ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
> + if (ret < 0)
> + goto err;
> +
> + ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
> + "fsl-lbc", fsl_lbc_ctrl_dev);
> + if (ret != 0) {
> + dev_err(&ofdev->dev, "failed to install irq (%d)\n",
> + fsl_lbc_ctrl_dev->irq);
> + ret = fsl_lbc_ctrl_dev->irq;
> + goto err;
> + }
> +
> + return 0;
> +
> +err:
fsl_lbc_ctrl_dev leaked. Plus, after freeing it, you should
NULLify it as well, as other functions checks it for !NULL.
fsl_lbc_ctrl_dev->regs leaks too.
> + return ret;
> +}
> +
> +static const struct of_device_id fsl_lbc_match[] = {
> + {
> + .compatible = "fsl,elbc",
> + },
> + {
> + .compatible = "fsl,pq3-localbus",
> + },
> + {
> + .compatible = "fsl,pq2-localbus",
> + },
> + {
> + .compatible = "fsl,pq2pro-localbus",
> + },
> + {},
Could save 8 lines by writing "{ .compatible = "...", },".
> +};
> +
> +static struct of_platform_driver fsl_lbc_ctrl_driver = {
I think you shouldn't use of_platform for new code. just platform
will work (there's platform_driver.driver.of_match_table nowadays).
> + .driver = {
> + .name = "fsl-lbc",
> + .of_match_table = fsl_lbc_match,
> + },
> + .probe = fsl_lbc_ctrl_probe,
> + .remove = __devexit_p(fsl_lbc_ctrl_remove),
The device is not removable, I think you don't need this.
> +};
> +
> +static int __init fsl_lbc_init(void)
> +{
> + return of_register_platform_driver(&fsl_lbc_ctrl_driver);
> +}
> +
> +static void __exit fsl_lbc_exit(void)
> +{
> + of_unregister_platform_driver(&fsl_lbc_ctrl_driver);
> +}
> +
> +module_init(fsl_lbc_init);
> +module_exit(fsl_lbc_exit);
fsl_lbc is not a module, so you don't need _exit().
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Freescale Semiconductor");
> +MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller driver");
ditto, no need for this.
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* Re: [PATCH 3/3][MTD] P4080/nand: Fix the freescale lbc issue with 36bit mode
From: Anton Vorontsov @ 2010-09-03 11:36 UTC (permalink / raw)
To: Roy Zang; +Cc: B25806, linuxppc-dev, akpm, linux-mtd, B11780
In-Reply-To: <1281063096-26598-3-git-send-email-tie-fei.zang@freescale.com>
On Fri, Aug 06, 2010 at 10:51:36AM +0800, Roy Zang wrote:
[...]
> /**
> + * convert_lbc_address - convert the base address
> + * @addr_base: base address of the memory bank
> + *
> + * This function converts a base address of lbc into the right format for the BR
> + * registers. If the SOC has eLBC then it returns 32bit physical address else
> + * it returns 34bit physical address for local bus(Example: MPC8641).
> + */
> +unsigned int convert_lbc_address(phys_addr_t addr_base)
> +{
> + void *dev;
> + int compatible;
> +
> + dev = of_find_node_by_name(NULL, "localbus");
Nope, you shouldn't do this. Never search by name.
Also, aren't there already a global dev, which was found by the
_probe() stuff?
> + if (!dev) {
> + printk(KERN_INFO "fsl-lbc: can't find localbus node\n");
> + of_node_put(dev);
> + return 0;
> + }
> +
> + compatible = of_device_is_compatible(dev, "fsl,elbc");
> + of_node_put(dev);
> + if (compatible)
> + return addr_base & 0xffff8000;
> + else
> + return (addr_base & 0x0ffff8000ull) \
> + | ((addr_base & 0x300000000ull) >> 19);
> +}
> +EXPORT_SYMBOL(convert_lbc_address);
> +
> +/**
> * fsl_lbc_find - find Localbus bank
> * @addr_base: base address of the memory bank
> *
> @@ -50,7 +80,8 @@ int fsl_lbc_find(phys_addr_t addr_base)
> __be32 br = in_be32(&fsl_lbc_ctrl_dev->regs->bank[i].br);
> __be32 or = in_be32(&fsl_lbc_ctrl_dev->regs->bank[i].or);
>
> - if (br & BR_V && (br & or & BR_BA) == addr_base)
> + if (br & BR_V && (br & or & BR_BA) \
No need for "\" at the end of the line, keep == on the same line.
> + == convert_lbc_address(addr_base))
Would be prettier if you name it fsl_lbc_addr(). Keeps prefix
the same for the rest of the file, plus makes it shorter (so
there probably won't be any need for breaking the line).
> return i;
> }
>
> diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
> index 7bbcb3f..0e8dc40 100644
> --- a/drivers/mtd/nand/fsl_elbc_nand.c
> +++ b/drivers/mtd/nand/fsl_elbc_nand.c
> @@ -838,7 +838,7 @@ static int __devinit fsl_elbc_nand_probe(struct of_device *dev,
> (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM &&
> (in_be32(&lbc->bank[bank].br) &
> in_be32(&lbc->bank[bank].or) & BR_BA)
> - == res.start)
> + == convert_lbc_address(res.start))
> break;
>
> if (bank >= MAX_BANKS) {
> --
> 1.5.6.5
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* Re: [PATCH 2/3][MTD] P4080/nand: Only make elbc nand driver detect nand flash partitions
From: Anton Vorontsov @ 2010-09-03 11:43 UTC (permalink / raw)
To: Roy Zang; +Cc: B25806, linuxppc-dev, linux-mtd, Scott Wood, akpm, B11780
In-Reply-To: <1281063096-26598-2-git-send-email-tie-fei.zang@freescale.com>
On Fri, Aug 06, 2010 at 10:51:35AM +0800, Roy Zang wrote:
[...]
>
> +static struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
> +
Are you sure that you want it as a global var? A bit scary change.
Oh, you probably don't need it, as you can get it from
fsl_lbc_ctrl_dev->nand?
I wonder if Scott saw these patches? Cc'ed.
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* Dual ethernet attachment with single FEC
From: LEROY Christophe @ 2010-09-03 11:49 UTC (permalink / raw)
To: LinuxPPC-dev
Hello,
I have a board with 2 PHYs attached to one FEC.
I want to implement some kind of main-standby attachment to LAN by
setting the ISOLATE bit on one on the two PHYs then monitoring the link
status and switch to the other PHY when the link status goes down.
What would be the most proper way to implement this functionality ?
* Modify FEC driver to manage that ?
* Implement a virtual PHY driver that would manage that ?
* Other solution ?
Best regards
C. Leroy
^ permalink raw reply
* Re: How to define an I2C-to-SPI bridge device ?
From: Anton Vorontsov @ 2010-09-03 12:08 UTC (permalink / raw)
To: André Schwarz; +Cc: LinuxPPC List, DevTreeDiscuss
In-Reply-To: <1283502979.17812.22.camel@swa-m460>
On Fri, Sep 03, 2010 at 10:36:19AM +0200, André Schwarz wrote:
> Hi,
>
> we're about to get new MPC8377 based hardware with various peripherals.
> There are two I2C-to-SPI bridge devices (NXP SC18IS602) and I'm not sure
> how to define a proper dts...
>
> Of course it's an easy thing creating 2 child nodes on the CPU's I2C
> device - but how can I represent the created SPI bus ?
Um.. the same as the other SPI buses? I.e.
i2c-controller { /* SOC I2C controller */
spi-controller { /* The I2C-to-SPI bridge */
spi-device@0 {
};
spi-device@1 {
};
};
};
> Is the (possibly) required driver (of_sc18is60x_spi ?) supposed to be an
> I2C slave or an SPI host driver ?
It should be an I2C driver that registers an SPI master (i.e.
calls spi_alloc_master() and spi_register_master()).
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* RE: P1021MDS QE Ethernet Ports
From: Haiying Wang @ 2010-09-03 14:39 UTC (permalink / raw)
To: Ioannis Kokkoris; +Cc: linuxppc-dev
In-Reply-To: <COL120-W1B541E7CCFDA55F070E79A78D0@phx.gbl>
On Fri, 2010-03-09 at 10:05 +0300, Ioannis Kokkoris wrote:
> We are using a board revision 2 (pilot version). Our main concern is whether this issue affects the working UCC1 eth interface performance.
No, it won't affect the performance. We got line rate for performance
for UECs on this board.
> Do you think that removing or pulling-down R79 (pin 21@U11) will fix the problem with ENET1?
I don't know.
> > You can connect two UECs for your current development.
>
> Do you mean that changing the ENET1 interface from UCC1 to UCC3 in dts may solve the problem?
No, I did not mean that. Only UCC1 and UCC5 are wired out for Ethernet
mode on this board, you can not change the UCC#. I meant, you should
have both UCC1/UCC5(ENET1/ENET5) connected with Ethernet cable.
Haiying
^ permalink raw reply
* [PATCH] powerpc/5200: tighten up ac97 reset timing
From: Eric Millbrandt @ 2010-09-03 15:45 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, Eric Millbrandt
Tighten up time timing around the gpio reset functionality. Add a 200ns
delay before remuxing the pins back to ac97 to comply with the ac97 spec.
This delay ensures that sync and sdata_out are held low while reset
transitions to high.
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
---
Scope shots are availible upon request.
arch/powerpc/platforms/52xx/mpc52xx_common.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/pl=
atforms/52xx/mpc52xx_common.c
index 6e90531..79adfe7 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -326,11 +326,14 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number)
clrbits8(&wkup_gpio->wkup_dvo, reset);
/* wait at lease 1 us */
- udelay(2);
+ udelay(1);
/* Deassert reset */
setbits8(&wkup_gpio->wkup_dvo, reset);
+ /* wait at least 200ns */
+ __delay(7);
+
/* Restore pin-muxing */
out_be32(&simple_gpio->port_config, mux);
--
1.6.3.1
-DISCLAIMER: an automatically appended disclaimer may follow. By posting-
-to a public e-mail mailing list I hereby grant permission to distribute-
-and copy this message.-
This e-mail and the information, including any attachments, it contains are=
intended to be a confidential communication only to the person or entity t=
o whom it is addressed and may contain information that is privileged. If t=
he reader of this message is not the intended recipient, you are hereby not=
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^ permalink raw reply related
* Re: [PATCH] powerpc/5200: tighten up ac97 reset timing
From: Wolfram Sang @ 2010-09-03 16:02 UTC (permalink / raw)
To: Eric Millbrandt; +Cc: linuxppc-dev
In-Reply-To: <1283528722-15644-1-git-send-email-emillbrandt@dekaresearch.com>
[-- Attachment #1: Type: text/plain, Size: 2483 bytes --]
On Fri, Sep 03, 2010 at 11:45:22AM -0400, Eric Millbrandt wrote:
> Tighten up time timing around the gpio reset functionality. Add a 200ns
> delay before remuxing the pins back to ac97 to comply with the ac97 spec.
> This delay ensures that sync and sdata_out are held low while reset
> transitions to high.
>
> Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
> ---
>
> Scope shots are availible upon request.
>
> arch/powerpc/platforms/52xx/mpc52xx_common.c | 5 ++++-
> 1 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
> index 6e90531..79adfe7 100644
> --- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
> +++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
> @@ -326,11 +326,14 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number)
> clrbits8(&wkup_gpio->wkup_dvo, reset);
>
> /* wait at lease 1 us */
Maybe you could fix this typo as well while you are here?
> - udelay(2);
> + udelay(1);
>
> /* Deassert reset */
> setbits8(&wkup_gpio->wkup_dvo, reset);
>
> + /* wait at least 200ns */
> + __delay(7);
ndelay(200)?
> +
> /* Restore pin-muxing */
> out_be32(&simple_gpio->port_config, mux);
>
> --
> 1.6.3.1
>
> -DISCLAIMER: an automatically appended disclaimer may follow. By posting-
> -to a public e-mail mailing list I hereby grant permission to distribute-
> -and copy this message.-
>
> This e-mail and the information, including any attachments, it contains are intended to be a confidential communication only to the person or entity to whom it is addressed and may contain information that is privileged. If the reader of this message is not the intended recipient, you are hereby notified that any dissemination, distribution or copying of this communication is strictly prohibited. If you have received this communication in error, please immediately notify the sender and destroy the original message.
>
> Thank you.
>
> Please consider the environment before printing this email.
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply
* RE: [PATCH] powerpc/5200: tighten up ac97 reset timing
From: Eric Millbrandt @ 2010-09-03 16:17 UTC (permalink / raw)
To: 'Wolfram Sang'; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20100903160209.GE4813@pengutronix.de>
On Fri, 3 Sep 2010 at 12:02:09 Wolfram Sang wrote:
> On Fri, Sep 03, 2010 at 11:45:22AM -0400, Eric Millbrandt wrote:
>> Tighten up time timing around the gpio reset functionality. Add a 200ns
>> delay before remuxing the pins back to ac97 to comply with the ac97
>> spec. This delay ensures that sync and sdata_out are held low while
>> reset transitions to high.
>>
>> Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
>> ---
>>
>> Scope shots are availible upon request.
>>
>> arch/powerpc/platforms/52xx/mpc52xx_common.c | 5 ++++-
>> 1 files changed, 4 insertions(+), 1 deletions(-)
>> diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c
>> b/arch/powerpc/platforms/52xx/mpc52xx_common.c index 6e90531..79adfe7
>> 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_common.c +++
>> b/arch/powerpc/platforms/52xx/mpc52xx_common.c @@ -326,11 +326,14 @@
>> int mpc5200_psc_ac97_gpio_reset(int
> psc_number)
>> clrbits8(&wkup_gpio->wkup_dvo, reset);
>>
>> /* wait at lease 1 us */
>
> Maybe you could fix this typo as well while you are here?
Can do.
>
>> - udelay(2);
>> + udelay(1);
>>
>> /* Deassert reset */
>> setbits8(&wkup_gpio->wkup_dvo, reset);
>>
>> + /* wait at least 200ns */
>> + __delay(7);
>
> ndelay(200)?
Is ndelay defined for powerpc? I was under the impression that it was
being redefined to udelay in linux/delay.h.
#ifndef ndelay
static inline void ndelay(unsigned long x)
{
udelay(DIV_ROUND_UP(x, 1000));
}
#define ndelay(x) ndelay(x)
#endif
-DISCLAIMER: an automatically appended disclaimer may follow. By posting-
-to a public e-mail mailing list I hereby grant permission to distribute-
-and copy this message.-
This e-mail and the information, including any attachments, it contains are=
intended to be a confidential communication only to the person or entity t=
o whom it is addressed and may contain information that is privileged. If t=
he reader of this message is not the intended recipient, you are hereby not=
ified that any dissemination, distribution or copying of this communication=
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please immediately notify the sender and destroy the original message.
Thank you.
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^ permalink raw reply
* Re: [PATCH] powerpc/5200: tighten up ac97 reset timing
From: Wolfram Sang @ 2010-09-03 16:22 UTC (permalink / raw)
To: Eric Millbrandt; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <0A40042D85E7C84DB443060EC44B3FD3254AA09E8E@dekaexchange07.deka.local>
[-- Attachment #1: Type: text/plain, Size: 845 bytes --]
> >> - udelay(2);
> >> + udelay(1);
> >>
> >> /* Deassert reset */
> >> setbits8(&wkup_gpio->wkup_dvo, reset);
> >>
> >> + /* wait at least 200ns */
> >> + __delay(7);
> >
> > ndelay(200)?
>
> Is ndelay defined for powerpc? I was under the impression that it was
> being redefined to udelay in linux/delay.h.
>
> #ifndef ndelay
> static inline void ndelay(unsigned long x)
> {
> udelay(DIV_ROUND_UP(x, 1000));
> }
> #define ndelay(x) ndelay(x)
> #endif
Yes, but it is way more readable. Does the extra delay hurt? The value
of 7 looks a bit magic to me. Are you sure it will do for various clock
frequencies?
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply
* RE: [PATCH] powerpc/5200: tighten up ac97 reset timing
From: Eric Millbrandt @ 2010-09-03 16:40 UTC (permalink / raw)
To: 'Wolfram Sang'; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20100903162224.GF4813@pengutronix.de>
On Fri, 3 Sep 2010 at 12:22:24 Wolfram Sang wrote:
>>>> - udelay(2);
>>>> + udelay(1);
>>>>
>>>> /* Deassert reset */
>>>> setbits8(&wkup_gpio->wkup_dvo, reset);
>>>>
>>>> + /* wait at least 200ns */
>>>> + __delay(7);
>>>
>>> ndelay(200)?
>> Is ndelay defined for powerpc? I was under the impression that it was
>> being redefined to udelay in linux/delay.h.
>>
>> #ifndef ndelay
>> static inline void ndelay(unsigned long x)
>> {
>> udelay(DIV_ROUND_UP(x, 1000));
>> }
>> #define ndelay(x) ndelay(x)
>> #endif
>
> Yes, but it is way more readable. Does the extra delay hurt? The value
> of 7 looks a bit magic to me. Are you sure it will do for various
> clock frequencies?
>
The reset is happening in the gpio spinlock, so I am trying to keep busy
waiting to a minimum. The magic value of 7 calculates to *roughly* 200ns
with a system timebase of 33mhz. This timebase drives the mpc5200(b) at
its max clock speed of 400mhz, so slower frequencies should just extend the
delay, which is acceptable. If you strongly object to the use of __delay
I can change it to ndelay.
-DISCLAIMER: an automatically appended disclaimer may follow. By posting-
-to a public e-mail mailing list I hereby grant permission to distribute-
-and copy this message.-
This e-mail and the information, including any attachments, it contains are=
intended to be a confidential communication only to the person or entity t=
o whom it is addressed and may contain information that is privileged. If t=
he reader of this message is not the intended recipient, you are hereby not=
ified that any dissemination, distribution or copying of this communication=
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please immediately notify the sender and destroy the original message.
Thank you.
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^ permalink raw reply
* Re: [PATCH] powerpc/5200: tighten up ac97 reset timing
From: Wolfram Sang @ 2010-09-03 16:49 UTC (permalink / raw)
To: Eric Millbrandt; +Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <0A40042D85E7C84DB443060EC44B3FD3254AA09E8F@dekaexchange07.deka.local>
[-- Attachment #1: Type: text/plain, Size: 953 bytes --]
> > Yes, but it is way more readable. Does the extra delay hurt? The value
> > of 7 looks a bit magic to me. Are you sure it will do for various
> > clock frequencies?
> >
>
> The reset is happening in the gpio spinlock, so I am trying to keep busy
> waiting to a minimum. The magic value of 7 calculates to *roughly* 200ns
> with a system timebase of 33mhz. This timebase drives the mpc5200(b) at
> its max clock speed of 400mhz, so slower frequencies should just extend the
> delay, which is acceptable. If you strongly object to the use of __delay
> I can change it to ndelay.
That might be a valid reason, dunno the details here. I'll leave the
final decision for Grant. If the use of __delay is acceptable, the
calculation that led to 7 should be explained, I think.
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply
* [PATCH v2] powerpc/5200: tighten up ac97 reset timing
From: Eric Millbrandt @ 2010-09-03 17:27 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, Eric Millbrandt
Tighten up time timing around the gpio reset functionality. Add a 200ns
delay before remuxing the pins back to ac97 to comply with the ac97 spec.
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
---
Scope shots availible upon request
changes since v1
- amended with comments from Wolfram Sang
arch/powerpc/platforms/52xx/mpc52xx_common.c | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/pl=
atforms/52xx/mpc52xx_common.c
index 6e90531..41f3a7e 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -325,12 +325,16 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number)
clrbits32(&simple_gpio->simple_dvo, sync | out);
clrbits8(&wkup_gpio->wkup_dvo, reset);
- /* wait at lease 1 us */
- udelay(2);
+ /* wait for 1 us */
+ udelay(1);
/* Deassert reset */
setbits8(&wkup_gpio->wkup_dvo, reset);
+ /* wait at least 200ns */
+ /* 7 ~=3D (200ns * timebase) / ns2sec */
+ __delay(7);
+
/* Restore pin-muxing */
out_be32(&simple_gpio->port_config, mux);
--
1.6.3.1
-DISCLAIMER: an automatically appended disclaimer may follow. By posting-
-to a public e-mail mailing list I hereby grant permission to distribute-
-and copy this message.-
This e-mail and the information, including any attachments, it contains are=
intended to be a confidential communication only to the person or entity t=
o whom it is addressed and may contain information that is privileged. If t=
he reader of this message is not the intended recipient, you are hereby not=
ified that any dissemination, distribution or copying of this communication=
is strictly prohibited. If you have received this communication in error, =
please immediately notify the sender and destroy the original message.
Thank you.
Please consider the environment before printing this email.
^ permalink raw reply related
* Re: [PATCH 2/3][MTD] P4080/nand: Only make elbc nand driver detect nand flash partitions
From: Scott Wood @ 2010-09-03 17:33 UTC (permalink / raw)
To: Anton Vorontsov; +Cc: B25806, linuxppc-dev, linux-mtd, akpm, B11780
In-Reply-To: <20100903114357.GC11847@oksana.dev.rtsoft.ru>
On Fri, 3 Sep 2010 15:43:57 +0400
Anton Vorontsov <cbouatmailru@gmail.com> wrote:
> On Fri, Aug 06, 2010 at 10:51:35AM +0800, Roy Zang wrote:
> [...]
> >
> > +static struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
> > +
>
> Are you sure that you want it as a global var? A bit scary change.
>
> Oh, you probably don't need it, as you can get it from
> fsl_lbc_ctrl_dev->nand?
>
> I wonder if Scott saw these patches? Cc'ed.
I saw many iterations of these patches. :-)
I had the same reaction to this, but during internal review it did not
seem to be the most pressing concern to focus on.
In practice, there will only be one eLBC, and properly handling multiple
devices and binding the right one across this new boundary would have
been unnecessary complexity.
-Scott
^ permalink raw reply
* Re: [PATCH][RFC] preempt_count corruption across H_CEDE call with CONFIG_PREEMPT on pseries
From: Will Schmidt @ 2010-09-03 20:10 UTC (permalink / raw)
To: Darren Hart
Cc: Stephen Rothwell, Michael Neuling, Gautham R Shenoy,
Josh Triplett, Steven Rostedt, linuxppc-dev, Paul Mackerras,
Ankita Garg, Thomas Gleixner
In-Reply-To: <4C7F3E6C.3010905@us.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 938 bytes --]
dvhltc@linux.vnet.ibm.com wrote on 09/02/2010 01:04:28 AM:
> Subject
>
> Re: [PATCH][RFC] preempt_count corruption across H_CEDE call with
> CONFIG_PREEMPT on pseries
> With this in place, we no longer see the preempt_count dropping below
> zero. However, if I offline/online a CPU about 246 times I hit the
> opposite problem, a preempt_count() overflow. There appears to be a
> missing preempt_enable() somewhere in the offline/online paths.
This (preempt_count overflow) also occurred in mainline (with
CONFIG_PREEMPT=y) in 2.6.35, but not in 2.6.36-rc3. A
bisect seems to indicate it was fixed with
a7c2bb8279d20d853e43c34584eaf2b039de8026 "powerpc: Re-enable preemption
before cpu_die()".
Which may look familiar. :-)
It looks like this patch went to mainline (likely via the powerpc tree),
but may
have not gotten back into the -rt branch.
-Will
>
> --
> Darren Hart
> IBM Linux Technology Center
> Real-Time Linux Team
[-- Attachment #2: Type: text/html, Size: 1282 bytes --]
^ permalink raw reply
* RE: [PATCH] APM821xx: Add support for new SoC APM821xx
From: Tirumala Marri @ 2010-09-03 20:38 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20100903020851.GC29732@hansolo.jdub.homelinux.org>
> >APM821xx is Applied Micro Circuits Corporations naming convention for
> >new line of SoCs.
>
> So is it a 440x6 core then? Or what core is inside the SoC?
[Marri] It is 464 core.
^ permalink raw reply
* [PATCH RFCv1 0/3] CARMA Board Support
From: Ira W. Snyder @ 2010-09-03 22:30 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel, Ira W. Snyder
Hello everyone,
Yesterday I asked where board specific drivers should be located in the
source tree. Several people suggested I just post the drivers for review
right away, and let the reviewers comment on where to put the drivers.
Here they are. I've created a new drivers/fpga/carma/ directory for the
drivers. I expect that this will not be their final resting place.
The CARMA board is essentially an MPC8349EA MDS reference design with a
1GHz ADC and 4 high powered data processing FPGAs connected to the local
bus. It is all packed into a compact PCI form factor. It is used at the
Owens Valley Radio Observatory as the main component in the correlator
system.
For more information, see this webpage, maintained by the board's hardware
engineer: http://www.mmarray.org/~dwh/carma_board/index.html
These drivers are the necessary pieces to get the data processing FPGAs
working and producing data. Despite the fact that the hardware is custom
and we are the only users, I'd still like to get the drivers upstream.
Several people have suggested that this is possible.
Some further patches will be forthcoming. I have a driver for the LED
subsystem and the PPS subsystem. The LED register layout is expected to
change soon, so I won't post the driver until that is finished. The PPS
driver will be posted seperately from this patch series; it is very
generic.
Thanks for any review and comments you can offer!
Ira
Ira W. Snyder (3):
fpga: add basic CARMA board support
fpga: add CARMA DATA-FPGA Access Driver
fpga: add CARMA DATA-FPGA Programmer support
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/fpga/Kconfig | 1 +
drivers/fpga/Makefile | 1 +
drivers/fpga/carma/Kconfig | 38 +
drivers/fpga/carma/Makefile | 3 +
drivers/fpga/carma/carma-fpga-program.c | 1136 ++++++++++++++++++++++++
drivers/fpga/carma/carma-fpga.c | 1447 +++++++++++++++++++++++++++++++
drivers/fpga/carma/carma.c | 73 ++
drivers/fpga/carma/carma.h | 22 +
10 files changed, 2724 insertions(+), 0 deletions(-)
create mode 100644 drivers/fpga/Kconfig
create mode 100644 drivers/fpga/Makefile
create mode 100644 drivers/fpga/carma/Kconfig
create mode 100644 drivers/fpga/carma/Makefile
create mode 100644 drivers/fpga/carma/carma-fpga-program.c
create mode 100644 drivers/fpga/carma/carma-fpga.c
create mode 100644 drivers/fpga/carma/carma.c
create mode 100644 drivers/fpga/carma/carma.h
^ permalink raw reply
* [PATCH RFCv1 1/3] fpga: add basic CARMA board support
From: Ira W. Snyder @ 2010-09-03 22:30 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel, Ira W. Snyder
In-Reply-To: <1283553052-23576-1-git-send-email-iws@ovro.caltech.edu>
This adds basic support for the system controller FPGA on the OVRO CARMA
board. This patch only adds infrastructure that will be used by later
drivers.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
---
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/fpga/Kconfig | 1 +
drivers/fpga/Makefile | 1 +
drivers/fpga/carma/Kconfig | 21 ++++++++++++
drivers/fpga/carma/Makefile | 1 +
drivers/fpga/carma/carma.c | 73 +++++++++++++++++++++++++++++++++++++++++++
drivers/fpga/carma/carma.h | 22 +++++++++++++
8 files changed, 122 insertions(+), 0 deletions(-)
create mode 100644 drivers/fpga/Kconfig
create mode 100644 drivers/fpga/Makefile
create mode 100644 drivers/fpga/carma/Kconfig
create mode 100644 drivers/fpga/carma/Makefile
create mode 100644 drivers/fpga/carma/carma.c
create mode 100644 drivers/fpga/carma/carma.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index a2b902f..8945ae6 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -111,4 +111,6 @@ source "drivers/xen/Kconfig"
source "drivers/staging/Kconfig"
source "drivers/platform/Kconfig"
+
+source "drivers/fpga/Kconfig"
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index ae47344..c0b05de 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -115,3 +115,4 @@ obj-$(CONFIG_VLYNQ) += vlynq/
obj-$(CONFIG_STAGING) += staging/
obj-y += platform/
obj-y += ieee802154/
+obj-$(CONFIG_FPGA_DRIVERS) += fpga/
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
new file mode 100644
index 0000000..c85c2cc
--- /dev/null
+++ b/drivers/fpga/Kconfig
@@ -0,0 +1 @@
+source "drivers/fpga/carma/Kconfig"
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
new file mode 100644
index 0000000..409a5f9
--- /dev/null
+++ b/drivers/fpga/Makefile
@@ -0,0 +1 @@
+obj-y += carma/
diff --git a/drivers/fpga/carma/Kconfig b/drivers/fpga/carma/Kconfig
new file mode 100644
index 0000000..448885e
--- /dev/null
+++ b/drivers/fpga/carma/Kconfig
@@ -0,0 +1,21 @@
+
+menuconfig FPGA_DRIVERS
+ bool "FPGA Drivers"
+ default n
+ help
+ Say Y here to see options for devices used with custom FPGAs.
+ This option alone does not add any kernel code.
+
+ If you say N, all options in this submenu will be skipped and disabled.
+
+if FPGA_DRIVERS
+
+config CARMA
+ tristate "CARMA System Controller FPGA support"
+ depends on FSL_SOC && PPC_83xx
+ default n
+ help
+ Say Y here to include basic support for the CARMA System Controller
+ FPGA. This option allows the other more advanced drivers to be built.
+
+endif # FPGA_DRIVERS
diff --git a/drivers/fpga/carma/Makefile b/drivers/fpga/carma/Makefile
new file mode 100644
index 0000000..90d0594
--- /dev/null
+++ b/drivers/fpga/carma/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CARMA) += carma.o
diff --git a/drivers/fpga/carma/carma.c b/drivers/fpga/carma/carma.c
new file mode 100644
index 0000000..97549d2
--- /dev/null
+++ b/drivers/fpga/carma/carma.c
@@ -0,0 +1,73 @@
+/*
+ * CARMA Board Utility Driver
+ *
+ * Copyright (c) 2009-2010 Ira W. Snyder <iws@ovro.caltech.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/err.h>
+
+#include "carma.h"
+
+static struct class *carma_class;
+static const char drv_name[] = "carma";
+
+/*
+ * CARMA Device Class Functions
+ */
+
+struct device *carma_device_create(struct device *parent, dev_t devno,
+ const char *fmt, ...)
+{
+ struct device *dev;
+ va_list vargs;
+
+ va_start(vargs, fmt);
+ dev = device_create_vargs(carma_class, parent, devno, NULL, fmt, vargs);
+ va_end(vargs);
+
+ return dev;
+}
+EXPORT_SYMBOL_GPL(carma_device_create);
+
+void carma_device_destroy(dev_t devno)
+{
+ device_destroy(carma_class, devno);
+}
+EXPORT_SYMBOL_GPL(carma_device_destroy);
+
+/*
+ * Module Init / Exit
+ */
+
+static int __init carma_init(void)
+{
+ /* Register the CARMA device class */
+ carma_class = class_create(THIS_MODULE, "carma");
+ if (IS_ERR(carma_class)) {
+ pr_err("%s: unable to create CARMA class\n", drv_name);
+ return PTR_ERR(carma_class);
+ }
+
+ return 0;
+}
+
+static void __exit carma_exit(void)
+{
+ class_destroy(carma_class);
+}
+
+MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
+MODULE_DESCRIPTION("CARMA Device Class Driver");
+MODULE_LICENSE("GPL");
+
+module_init(carma_init);
+module_exit(carma_exit);
diff --git a/drivers/fpga/carma/carma.h b/drivers/fpga/carma/carma.h
new file mode 100644
index 0000000..f556dc8
--- /dev/null
+++ b/drivers/fpga/carma/carma.h
@@ -0,0 +1,22 @@
+/*
+ * CARMA Board Utilities
+ *
+ * Copyright (c) 2009-2010 Ira W. Snyder <iws@ovro.caltech.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef CARMA_DEVICE_H
+#define CARMA_DEVICE_H
+
+#include <linux/device.h>
+
+struct device *carma_device_create(struct device *parent, dev_t devno,
+ const char *fmt, ...)
+ __attribute__((format(printf, 3, 4)));
+void carma_device_destroy(dev_t devno);
+
+#endif /* CARMA_DEVICE_H */
--
1.7.1
^ permalink raw reply related
* [PATCH RFCv1 2/3] fpga: add CARMA DATA-FPGA Access Driver
From: Ira W. Snyder @ 2010-09-03 22:30 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel, Ira W. Snyder
In-Reply-To: <1283553052-23576-1-git-send-email-iws@ovro.caltech.edu>
This driver allows userspace to access the data processing FPGAs on the
OVRO CARMA board. It has two modes of operation:
1) random access
This allows users to poke any DATA-FPGA registers by using mmap to map
the address region directly into their memory map.
2) correlation dumping
When correlating, the DATA-FPGA's have special requirements for getting
the data out of their memory before the next correlation. This nominally
happens at 64Hz (every 15.625ms). If the data is not dumped before the
next correlation, data is lost.
The data dumping driver handles buffering up to 1 second worth of
correlation data from the FPGAs. This lowers the realtime scheduling
requirements for the userspace process reading the device.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
---
drivers/fpga/carma/Kconfig | 9 +
drivers/fpga/carma/Makefile | 1 +
drivers/fpga/carma/carma-fpga.c | 1447 +++++++++++++++++++++++++++++++++++++++
3 files changed, 1457 insertions(+), 0 deletions(-)
create mode 100644 drivers/fpga/carma/carma-fpga.c
diff --git a/drivers/fpga/carma/Kconfig b/drivers/fpga/carma/Kconfig
index 448885e..5592f73 100644
--- a/drivers/fpga/carma/Kconfig
+++ b/drivers/fpga/carma/Kconfig
@@ -18,4 +18,13 @@ config CARMA
Say Y here to include basic support for the CARMA System Controller
FPGA. This option allows the other more advanced drivers to be built.
+config CARMA_FPGA
+ tristate "CARMA DATA-FPGA Access Driver"
+ depends on CARMA
+ select VIDEOBUF_DMA_SG
+ default n
+ help
+ Say Y here to include support for communicating with the data
+ processing FPGAs on the CARMA board.
+
endif # FPGA_DRIVERS
diff --git a/drivers/fpga/carma/Makefile b/drivers/fpga/carma/Makefile
index 90d0594..c175d34 100644
--- a/drivers/fpga/carma/Makefile
+++ b/drivers/fpga/carma/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_CARMA) += carma.o
+obj-$(CONFIG_CARMA_FPGA) += carma-fpga.o
diff --git a/drivers/fpga/carma/carma-fpga.c b/drivers/fpga/carma/carma-fpga.c
new file mode 100644
index 0000000..ab1b536
--- /dev/null
+++ b/drivers/fpga/carma/carma-fpga.c
@@ -0,0 +1,1447 @@
+/*
+ * CARMA DATA-FPGA Access Driver
+ *
+ * Copyright (c) 2009-2010 Ira W. Snyder <iws@ovro.caltech.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/*
+ * FPGA Memory Dump Format
+ *
+ * FPGA #0 control registers (32 x 32-bit words)
+ * FPGA #1 control registers (32 x 32-bit words)
+ * FPGA #2 control registers (32 x 32-bit words)
+ * FPGA #3 control registers (32 x 32-bit words)
+ * SYSFPGA control registers (32 x 32-bit words)
+ * FPGA #0 correlation array (NUM_CORL0 correlation blocks)
+ * FPGA #1 correlation array (NUM_CORL1 correlation blocks)
+ * FPGA #2 correlation array (NUM_CORL2 correlation blocks)
+ * FPGA #3 correlation array (NUM_CORL3 correlation blocks)
+ *
+ * Each correlation array consists of:
+ *
+ * Correlation Data (2 x NUM_LAGSn x 32-bit words)
+ * Pipeline Metadata (2 x NUM_METAn x 32-bit words)
+ * Quantization Counters (2 x NUM_QCNTn x 32-bit words)
+ *
+ * The NUM_CORLn, NUM_LAGSn, NUM_METAn, and NUM_QCNTn values come from
+ * the FPGA configuration registers. They do not change once the FPGA's
+ * have been programmed, they only change on re-programming.
+ */
+
+/*
+ * Basic Description:
+ *
+ * This driver is used to capture correlation spectra off of the four data
+ * processing FPGAs. The FPGAs are often reprogrammed at runtime, therefore
+ * this driver supports dynamic enable/disable of capture while the device
+ * remains open.
+ *
+ * The nominal capture rate is 64Hz (every 15.625ms). To facilitate this fast
+ * capture rate, all buffers are pre-allocated to avoid any potentially long
+ * running memory allocations while capturing.
+ *
+ * There are three lists which are used to keep track of the different states
+ * of data buffers.
+ *
+ * 1) free list
+ * This list holds all empty data buffers which are ready to receive data.
+ *
+ * 2) inflight list
+ * This list holds data buffers which are currently waiting for a DMA operation
+ * to complete.
+ *
+ * 3) used list
+ * This list holds data buffers which have been filled, and are waiting to be
+ * read by userspace.
+ *
+ * All buffers start life on the free list, then move successively to the
+ * inflight list, and then to the used list. After they have been read by
+ * userspace, they are moved back to the free list. The cycle repeats as long
+ * as necessary.
+ */
+
+/*
+ * Notes on the IRQ masking scheme:
+ *
+ * The IRQ masking scheme here is different than most other hardware. The only
+ * way for the DATA-FPGAs to detect if the kernel has taken too long to copy
+ * the data is if the status registers are not cleared before the next
+ * correlation data dump is ready.
+ *
+ * The interrupt line is connected to the status registers, such that when they
+ * are cleared, the interrupt is de-asserted. Therein lies our problem. We need
+ * to schedule a long-running DMA operation and return from the interrupt
+ * handler quickly, but we cannot clear the status registers.
+ *
+ * To handle this, the system controller FPGA has the capability to connect the
+ * interrupt line to a user-controlled GPIO pin. This pin is driven high
+ * (unasserted) and left that way. To mask the interrupt, we change the
+ * interrupt source to the GPIO pin. Tada, we hid the interrupt. :)
+ */
+
+#include <linux/of_platform.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/dmaengine.h>
+#include <linux/highmem.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/cdev.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <media/videobuf-dma-sg.h>
+#include <asm/fsldma.h>
+
+#include "carma.h"
+
+/* system controller registers */
+#define SYS_IRQ_SOURCE_CTL 0x24
+#define SYS_IRQ_OUTPUT_EN 0x28
+#define SYS_IRQ_OUTPUT_DATA 0x2C
+#define SYS_IRQ_INPUT_DATA 0x30
+
+/* GPIO IRQ line assignment */
+#define IRQ_CORL_DONE 0x10
+
+/* FPGA registers */
+#define MMAP_REG_CORL_CONF1 0x08
+#define MMAP_REG_CORL_CONF2 0x0C
+#define MMAP_REG_STATUS 0x48
+
+#define SYS_FPGA_BLOCK 0xF0000000
+
+static const char drv_name[] = "carma-fpga";
+
+#define NUM_FPGA 4
+
+#define MIN_DATA_BUFS 8
+#define MAX_DATA_BUFS 64
+
+struct fpga_info {
+ unsigned int num_corl;
+ unsigned int blk_size;
+};
+
+struct data_buf {
+ struct list_head entry;
+ struct videobuf_dmabuf vb;
+ bool mapped;
+ size_t size;
+};
+
+struct fpga_device {
+ struct cdev cdev;
+ dev_t devno;
+
+ struct device *dev;
+ struct mutex mutex;
+
+ /* FPGA registers and information */
+ struct fpga_info info[NUM_FPGA];
+ void __iomem *regs;
+ int irq;
+
+ /* FPGA Physical Address/Size Information */
+ resource_size_t phys_addr;
+ size_t phys_size;
+
+ /* DMA structures */
+ struct fsl_dma_slave *slave;
+ struct dma_chan *chan;
+ struct device *dmadev;
+
+ /* Protection for all members below */
+ spinlock_t lock;
+
+ /* Device enable/disable flag */
+ bool enabled;
+
+ /* Correlation data buffers */
+ wait_queue_head_t wait;
+ struct list_head free;
+ struct list_head used;
+ struct list_head inflight;
+
+ /* Information about data buffers */
+ unsigned int num_dropped;
+ unsigned int num_buffers;
+ size_t bufsize;
+};
+
+struct fpga_reader {
+ struct fpga_device *priv;
+ struct data_buf *buf;
+ off_t buf_start;
+};
+
+#define inode_to_dev(inode) container_of(inode->i_cdev, struct fpga_device, cdev)
+
+/*
+ * Data Buffer Allocation Helpers
+ */
+
+static int data_map_buffer(struct device *dev, struct data_buf *buf)
+{
+ int ret;
+
+ /* if the buffer is already mapped, we're done */
+ if (buf->mapped)
+ return 0;
+
+ ret = videobuf_dma_map(dev, &buf->vb);
+ if (ret)
+ return ret;
+
+ buf->mapped = true;
+ return 0;
+}
+
+static void data_unmap_buffer(struct device *dev, struct data_buf *buf)
+{
+ /* the buffer is already unmapped, we're done */
+ if (!buf->mapped)
+ return;
+
+ videobuf_dma_unmap(dev, &buf->vb);
+ buf->mapped = false;
+}
+
+/*
+ * Free a single data buffer and all allocated pages
+ *
+ * This will free all of the pages allocated to the given data buffer, and
+ * then free the structure itself
+ *
+ * @dev: the DMA device to map for
+ * @buf: the buffer to free
+ */
+static void data_free_buffer(struct device *dev, struct data_buf *buf)
+{
+ /* It is ok to free a NULL buffer */
+ if (!buf)
+ return;
+
+ /* Make sure the buffer is not on any list */
+ list_del_init(&buf->entry);
+
+ /* unmap it for DMA */
+ data_unmap_buffer(dev, buf);
+
+ /* free all memory */
+ videobuf_dma_free(&buf->vb);
+ kfree(buf);
+}
+
+/*
+ * Allocate and fill a data buffer
+ *
+ * This allocates all space needed for a data buffer, and gets it ready to be
+ * used in a DMA transaction. It only needs to be used, never mapped before
+ * use. This avoids calling vmalloc in hardirq context.
+ *
+ * @dev: the DMA device to map for
+ * @bytes: the number of bytes required
+ * @return: a new buffer or NULL on failure
+ */
+static struct data_buf *data_alloc_buffer(struct device *dev, const size_t bytes)
+{
+ unsigned int nr_pages;
+ struct data_buf *buf;
+ int ret;
+
+ /* calculate the number of pages necessary */
+ nr_pages = DIV_ROUND_UP(bytes, PAGE_SIZE);
+
+ /* allocate the buffer structure */
+ buf = kzalloc(sizeof(*buf), GFP_KERNEL);
+ if (!buf)
+ goto out_return;
+
+ /* initialize internal fields */
+ INIT_LIST_HEAD(&buf->entry);
+ buf->size = bytes;
+
+ /* allocate the videobuf */
+ videobuf_dma_init(&buf->vb);
+ ret = videobuf_dma_init_kernel(&buf->vb, DMA_FROM_DEVICE, nr_pages);
+ if (ret)
+ goto out_free_buf;
+
+ /* map it for DMA */
+ ret = data_map_buffer(dev, buf);
+ if (ret)
+ goto out_free_videobuf;
+
+ return buf;
+
+out_free_videobuf:
+ videobuf_dma_free(&buf->vb);
+out_free_buf:
+ kfree(buf);
+out_return:
+ return NULL;
+}
+
+/*
+ * Free all of the buffers allocated for correlation data
+ *
+ * This routine will free all data buffers that are being used by the driver.
+ *
+ * REQUIREMENTS: all list manipulation must have ceased
+ * REQUIREMENTS: all DMA must be complete, and the engine stopped
+ *
+ * CONTEXT: user
+ *
+ * @param priv the driver's private data structure
+ */
+static void data_free_buffers(struct fpga_device *priv)
+{
+ struct device *dev = priv->dmadev;
+ struct data_buf *buf, *tmp;
+
+ spin_lock_irq(&priv->lock);
+ BUG_ON(!list_empty(&priv->inflight));
+
+ list_for_each_entry_safe(buf, tmp, &priv->free, entry) {
+ list_del_init(&buf->entry);
+ spin_unlock_irq(&priv->lock);
+ data_free_buffer(dev, buf);
+ spin_lock_irq(&priv->lock);
+ }
+
+ list_for_each_entry_safe(buf, tmp, &priv->used, entry) {
+ list_del_init(&buf->entry);
+ spin_unlock_irq(&priv->lock);
+ data_free_buffer(dev, buf);
+ spin_lock_irq(&priv->lock);
+ }
+
+ priv->num_buffers = 0;
+ priv->bufsize = 0;
+
+ spin_unlock_irq(&priv->lock);
+}
+
+/*
+ * Allocate enough buffers for a whole second worth of data
+ *
+ * This routine will attempt to degrade nicely by succeeding even if a full
+ * second worth of data buffers could not be allocated, as long as a minimum
+ * number were allocated. In this case, it will print a message to the kernel
+ * log.
+ *
+ * CONTEXT: user
+ *
+ * @param priv the driver's private data structure
+ * @return 0 on success, -ERRNO otherwise
+ */
+static int data_alloc_buffers(struct fpga_device *priv)
+{
+ struct device *dev = priv->dmadev;
+ struct data_buf *buf;
+ int i;
+
+ for (i = 0; i < MAX_DATA_BUFS; i++) {
+ buf = data_alloc_buffer(dev, priv->bufsize);
+ if (!buf)
+ break;
+
+ spin_lock_irq(&priv->lock);
+ list_add_tail(&buf->entry, &priv->free);
+ spin_unlock_irq(&priv->lock);
+ }
+
+ /* Make sure we allocated the minimum required number of buffers */
+ if (i < MIN_DATA_BUFS) {
+ dev_err(priv->dev, "Unable to allocate enough data buffers\n");
+ data_free_buffers(priv);
+ return -ENOMEM;
+ }
+
+ /* Warn if we are running in a degraded state, but do not fail */
+ if (i < MAX_DATA_BUFS) {
+ dev_warn(priv->dev, "Unable to allocate one second worth of "
+ "buffers, using %d buffers instead\n", i);
+ }
+
+ priv->num_buffers = i;
+ return 0;
+}
+
+/*
+ * DMA Operations Helpers
+ */
+
+/*
+ * Calculate the physical address of the start of FPGA memory
+ *
+ * @param priv the driver's private data structure
+ * @param fpga the FPGA number
+ * @return the physical address of the correlation data block
+ */
+static dma_addr_t fpga_start_addr(struct fpga_device *priv, unsigned int fpga)
+{
+ return priv->phys_addr + 0x400000 + (0x80000 * fpga);
+}
+
+/*
+ * Calculate the physical address of an FPGA correlation data block
+ *
+ * @param priv the driver's private data structure
+ * @param fpga the FPGA number
+ * @param blknum the correlation data block number
+ * @return the physical address of the correlation data block
+ */
+static dma_addr_t fpga_block_addr(struct fpga_device *priv, unsigned int fpga,
+ unsigned int blknum)
+{
+ return fpga_start_addr(priv, fpga) + (0x10000 * (1 + blknum));
+}
+
+/*
+ * Add the correlation data for a single DATA FPGA to the DMA_SLAVE structure
+ *
+ * @param priv the driver's private data structure
+ * @param slave the Freescale DMA_SLAVE structure
+ * @param fpga the FPGA number
+ * @return 0 on success, -ERRNO otherwise
+ */
+static int fpga_append_correlation_data(struct fpga_device *priv,
+ struct fsl_dma_slave *slave,
+ unsigned int fpga)
+{
+ struct fpga_info *info = &priv->info[fpga];
+ dma_addr_t addr;
+ size_t len;
+ int i, ret;
+
+ for (i = 0; i < info->num_corl; i++) {
+ addr = fpga_block_addr(priv, fpga, i);
+ len = info->blk_size;
+ ret = fsl_dma_slave_append(slave, addr, len);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/*
+ * Create the DMA_SLAVE structure for transferring data from the DATA FPGA's
+ *
+ * This structure will be reused for each buffer that needs to be filled
+ * with correlation data from the DATA FPGA's
+ *
+ * @param priv the driver's private data structure
+ * @return 0 on success, -ERRNO otherwise
+ */
+static int data_setup_dma_slave(struct fpga_device *priv)
+{
+ static const char prefix[] = "DMA_SLAVE: unable to";
+ struct fsl_dma_slave *slave;
+ dma_addr_t addr;
+ size_t len;
+ int i, ret;
+
+ /* Create the Freescale DMA_SLAVE structure */
+ slave = fsl_dma_slave_alloc(GFP_KERNEL);
+ if (!slave) {
+ dev_err(priv->dev, "%s allocate structure\n", prefix);
+ ret = -ENOMEM;
+ goto out_return;
+ }
+
+ /* Add the FPGA registers to the slave list */
+ for (i = 0; i < NUM_FPGA; i++) {
+ addr = fpga_start_addr(priv, i);
+ len = 32 * 4;
+ ret = fsl_dma_slave_append(slave, addr, len);
+ if (ret) {
+ dev_err(priv->dev, "%s add FPGA registers\n", prefix);
+ goto out_free_slave;
+ }
+ }
+
+ /* Add the SYS-FPGA registers to the slave list */
+ addr = SYS_FPGA_BLOCK;
+ len = 32 * 4;
+ ret = fsl_dma_slave_append(slave, addr, len);
+ if (ret) {
+ dev_err(priv->dev, "%s add SYS-FPGA registers\n", prefix);
+ goto out_free_slave;
+ }
+
+ /* Add the FPGA correlation data blocks to the slave list */
+ for (i = 0; i < NUM_FPGA; i++) {
+ ret = fpga_append_correlation_data(priv, slave, i);
+ if (ret) {
+ dev_err(priv->dev, "%s add correlation data\n", prefix);
+ goto out_free_slave;
+ }
+ }
+
+ /*
+ * That's everything, this slave structure can be re-used for
+ * every FPGA DATA interrupt
+ */
+ priv->slave = slave;
+ return 0;
+
+out_free_slave:
+ fsl_dma_slave_free(slave);
+out_return:
+ return ret;
+}
+
+/*
+ * FPGA Register Access Helpers
+ */
+
+static void fpga_write_reg(struct fpga_device *priv, unsigned int fpga,
+ unsigned int reg, u32 val)
+{
+ iowrite32be(val, priv->regs + 0x400000 + (fpga * 0x80000) + reg);
+}
+
+static u32 fpga_read_reg(struct fpga_device *priv, unsigned int fpga,
+ unsigned int reg)
+{
+ return ioread32be(priv->regs + 0x400000 + (fpga * 0x80000) + reg);
+}
+
+/*
+ * Calculate the total buffer size needed to hold a single block
+ * of correlation data
+ *
+ * CONTEXT: user
+ *
+ * @param priv the driver's private data structure
+ * @return 0 on success, -ERRNO otherwise
+ */
+static int data_calculate_bufsize(struct fpga_device *priv)
+{
+ u32 num_corl, num_lags, num_meta, num_qcnt, blk_size;
+ u32 conf1, conf2;
+ int i;
+
+ /* Zero the total buffer size */
+ priv->bufsize = 0;
+
+ /* Read and store the configuration data for each FPGA */
+ for (i = 0; i < NUM_FPGA; i++) {
+ conf1 = fpga_read_reg(priv, i, MMAP_REG_CORL_CONF1);
+ conf2 = fpga_read_reg(priv, i, MMAP_REG_CORL_CONF2);
+
+ num_corl = (conf1 & 0x000000F0) >> 4;
+ num_lags = (conf1 & 0x000FFF00) >> 8;
+ num_meta = (conf1 & 0x7FF00000) >> 20;
+ num_qcnt = (conf2 & 0x00000FFF) >> 0;
+ blk_size = (num_lags + num_meta + num_qcnt) * 8;
+
+ priv->info[i].num_corl = num_corl;
+ priv->info[i].blk_size = blk_size;
+ priv->bufsize += num_corl * blk_size;
+
+ dev_dbg(priv->dev, "FPGA %d NUM_CORL: %d\n", i, num_corl);
+ dev_dbg(priv->dev, "FPGA %d NUM_LAGS: %d\n", i, num_lags);
+ dev_dbg(priv->dev, "FPGA %d NUM_META: %d\n", i, num_meta);
+ dev_dbg(priv->dev, "FPGA %d NUM_QCNT: %d\n", i, num_qcnt);
+ dev_dbg(priv->dev, "FPGA %d BLK_SIZE: %d\n", i, blk_size);
+ }
+
+ /* Add in the 5 FPGA register areas */
+ priv->bufsize += 5 * (32 * 4);
+ dev_dbg(priv->dev, "TOTAL BUFFER SIZE: %zu bytes\n", priv->bufsize);
+
+ return 0;
+}
+
+/*
+ * Interrupt Handling
+ */
+
+/*
+ * Hide interrupts by switching to GPIO interrupt source
+ *
+ * LOCKING: must hold dev->lock
+ */
+static void data_disable_interrupts(struct fpga_device *priv)
+{
+ /* hide the interrupt by switching the IRQ driver to GPIO */
+ iowrite32be(0x2F, priv->regs + SYS_IRQ_SOURCE_CTL);
+}
+
+/*
+ * Unhide interrupts by switching to the FPGA interrupt source
+ *
+ * LOCKING: must hold dev->lock
+ */
+static void data_enable_interrupts(struct fpga_device *priv)
+{
+ /* clear the actual FPGA corl_done interrupt */
+ fpga_write_reg(priv, 0, MMAP_REG_STATUS, 0x0);
+ fpga_write_reg(priv, 1, MMAP_REG_STATUS, 0x0);
+ fpga_write_reg(priv, 2, MMAP_REG_STATUS, 0x0);
+ fpga_write_reg(priv, 3, MMAP_REG_STATUS, 0x0);
+
+ /* flush the writes */
+ fpga_read_reg(priv, 0, MMAP_REG_STATUS);
+
+ /* switch back to the external interrupt source */
+ iowrite32be(0x3F, priv->regs + SYS_IRQ_SOURCE_CTL);
+}
+
+/*
+ * Complete a DMA transfer from the FPGA's
+ *
+ * This is called via the DMA callback mechanism, and will handle moving the
+ * completed DMA transaction to the used list, and then wake any processes
+ * waiting for new data
+ *
+ * CONTEXT: any, softirq expected
+ *
+ * @param data the driver's private data structure
+ */
+static void data_dma_cb(void *data)
+{
+ struct fpga_device *priv = data;
+ struct data_buf *buf;
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->lock, flags);
+
+ /* clear the FPGA status and re-enable interrupts */
+ data_enable_interrupts(priv);
+
+ /* If the inflight list is empty, we've got a bug */
+ BUG_ON(list_empty(&priv->inflight));
+
+ /* Grab the first buffer from the inflight list */
+ buf = list_first_entry(&priv->inflight, struct data_buf, entry);
+ list_del_init(&buf->entry);
+
+ /* Add it to the used list */
+ list_add_tail(&buf->entry, &priv->used);
+
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ /* We've changed both the inflight and used lists, so we need
+ * to wake up any processes that are blocking for those events */
+ wake_up(&priv->wait);
+}
+
+/*
+ * Prepare and submit a DMA_SLAVE transaction for a correlation data buffer
+ *
+ * LOCKING: must hold dev->lock
+ * CONTEXT: hardirq only
+ *
+ * @param priv the driver's private data structure
+ * @param buf the data buffer to DMA into
+ * @return 0 on success, -ERRNO otherwise
+ */
+static int data_submit_dma(struct fpga_device *priv, struct data_buf *buf)
+{
+ struct scatterlist *sg = buf->vb.sglist;
+ unsigned int nents = buf->vb.sglen;
+ struct dma_chan *chan = priv->chan;
+ struct dma_async_tx_descriptor *tx;
+ dma_cookie_t cookie;
+ dma_addr_t dst, src;
+
+ /*
+ * All buffers passed to this function should be ready and mapped
+ * for DMA already. Therefore, we don't need to do anything except
+ * submit it to the Freescale DMA Engine for processing
+ */
+
+ /* setup the DMA_SLAVE transaction */
+ chan->private = priv->slave;
+ tx = chan->device->device_prep_slave_sg(chan, sg, nents,
+ DMA_FROM_DEVICE, 0);
+ if (!tx) {
+ dev_err(priv->dev, "unable to prep slave DMA 1\n");
+ return -ENOMEM;
+ }
+
+ /* submit the transaction to the DMA controller */
+ cookie = tx->tx_submit(tx);
+ if (dma_submit_error(cookie)) {
+ dev_err(priv->dev, "unable to submit slave DMA 1\n");
+ return -ENOMEM;
+ }
+
+ /* Prepare the re-read of the SYS-FPGA block */
+ dst = sg_dma_address(sg) + (NUM_FPGA * 32 * 4);
+ src = SYS_FPGA_BLOCK;
+ tx = chan->device->device_prep_dma_memcpy(chan, dst, src, 32 * 4,
+ DMA_PREP_INTERRUPT);
+ if (!tx) {
+ dev_err(priv->dev, "unable to prep slave DMA 2\n");
+ return -ENOMEM;
+ }
+
+ /* Setup the callback */
+ tx->callback = data_dma_cb;
+ tx->callback_param = priv;
+
+ /* submit the transaction to the DMA controller */
+ cookie = tx->tx_submit(tx);
+ if (dma_submit_error(cookie)) {
+ dev_err(priv->dev, "unable to submit slave DMA 2\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+#define CORL_DONE 0x1
+#define CORL_ERR 0x2
+
+static irqreturn_t data_irq(int irq, void *dev_id)
+{
+ struct fpga_device *priv = dev_id;
+ struct data_buf *buf;
+ u32 status;
+ int i;
+
+ /* detect spurious interrupts via FPGA status */
+ for (i = 0; i < 4; i++) {
+ status = fpga_read_reg(priv, i, MMAP_REG_STATUS);
+ if (!(status & (CORL_DONE | CORL_ERR))) {
+ dev_err(priv->dev, "spurious irq detected (FPGA)\n");
+ return IRQ_NONE;
+ }
+ }
+
+ /* detect spurious interrupts via raw IRQ pin readback */
+ status = ioread32be(priv->regs + SYS_IRQ_INPUT_DATA);
+ if (status & IRQ_CORL_DONE) {
+ dev_err(priv->dev, "spurious irq detected (IRQ)\n");
+ return IRQ_NONE;
+ }
+
+ spin_lock(&priv->lock);
+
+ /* hide the interrupt by switching the IRQ driver to GPIO */
+ data_disable_interrupts(priv);
+
+ /* Check that we actually have a free buffer */
+ if (list_empty(&priv->free)) {
+ priv->num_dropped++;
+ data_enable_interrupts(priv);
+ goto out_unlock;
+ }
+
+ buf = list_first_entry(&priv->free, struct data_buf, entry);
+ list_del_init(&buf->entry);
+
+ /* Check the buffer size */
+ BUG_ON(buf->size != priv->bufsize);
+
+ /* Submit a DMA transfer to get the correlation data */
+ if (data_submit_dma(priv, buf)) {
+ dev_err(priv->dev, "Unable to setup DMA transfer\n");
+ list_add_tail(&buf->entry, &priv->free);
+ data_enable_interrupts(priv);
+ goto out_unlock;
+ }
+
+ /* DMA setup succeeded, GO!!! */
+ list_add_tail(&buf->entry, &priv->inflight);
+ dma_async_memcpy_issue_pending(priv->chan);
+
+out_unlock:
+ spin_unlock(&priv->lock);
+ return IRQ_HANDLED;
+}
+
+/*
+ * Realtime Device Enable Helpers
+ */
+
+/*
+ * Enable the device for buffered dumping
+ *
+ * ASSUMES: the FPGA's are powered on and reads will succeed
+ * LOCKING: dev->mutex held
+ * CONTEXT: user context only
+ */
+static int data_device_enable(struct fpga_device *priv)
+{
+ u32 val;
+ int ret;
+
+ /* multiple enables are safe: they do nothing */
+ if (priv->enabled)
+ return 0;
+
+ /* check that the FPGAs are programmed */
+ val = ioread32be(priv->regs + 0x44);
+ if (!(val & (1 << 18))) {
+ dev_err(priv->dev, "DATA-FPGAs are not enabled\n");
+ return -ENODATA;
+ }
+
+ /* read the FPGAs to calculate the buffer size */
+ ret = data_calculate_bufsize(priv);
+ if (ret) {
+ dev_err(priv->dev, "unable to calculate buffer size\n");
+ goto out_error;
+ }
+
+ /* allocate the correlation data buffers */
+ ret = data_alloc_buffers(priv);
+ if (ret) {
+ dev_err(priv->dev, "unable to allocate buffers\n");
+ goto out_error;
+ }
+
+ /* allocate the DMA_SLAVE structure for correlation data */
+ ret = data_setup_dma_slave(priv);
+ if (ret) {
+ dev_err(priv->dev, "unable to setup DMA list\n");
+ goto out_error;
+ }
+
+ /* switch to the external FPGA IRQ line */
+ data_enable_interrupts(priv);
+
+ /* hookup the irq handler */
+ ret = request_irq(priv->irq, data_irq, IRQF_SHARED, drv_name, priv);
+ if (ret) {
+ dev_err(priv->dev, "unable to request IRQ handler\n");
+ goto out_free_slave;
+ }
+
+ /* success, we're enabled */
+ priv->enabled = true;
+ return 0;
+
+out_free_slave:
+ fsl_dma_slave_free(priv->slave);
+ priv->slave = NULL;
+out_error:
+ data_free_buffers(priv);
+ return ret;
+}
+
+/*
+ * Disable the device for buffered dumping
+ *
+ * LOCKING: must hold dev->mutex
+ * CONTEXT: user only
+ */
+static int data_device_disable(struct fpga_device *priv)
+{
+ struct list_head *list;
+ int ret;
+
+ /* allow multiple disable */
+ if (!priv->enabled)
+ return 0;
+
+ /* switch to the internal GPIO IRQ line */
+ data_disable_interrupts(priv);
+
+ /* unhook the irq handler */
+ free_irq(priv->irq, priv);
+
+ /* wait for all outstanding DMA to complete */
+ list = &priv->inflight;
+
+ spin_lock_irq(&priv->lock);
+ while (!list_empty(list)) {
+ spin_unlock_irq(&priv->lock);
+
+ ret = wait_event_interruptible(priv->wait, list_empty(list));
+ if (ret)
+ return -ERESTARTSYS;
+
+ spin_lock_irq(&priv->lock);
+ }
+ spin_unlock_irq(&priv->lock);
+
+ /* free the DMA_SLAVE structure */
+ fsl_dma_slave_free(priv->slave);
+ priv->slave = NULL;
+
+ /* free all of the buffers */
+ data_free_buffers(priv);
+ priv->enabled = false;
+ return 0;
+}
+
+/*
+ * SYSFS Attributes
+ */
+
+/*
+ * Count the number of entries in the given list
+ */
+static unsigned int list_num_entries(struct list_head *list)
+{
+ struct list_head *entry;
+ unsigned int ret = 0;
+
+ list_for_each(entry, list)
+ ret++;
+
+ return ret;
+}
+
+static ssize_t data_num_buffers_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fpga_device *priv = dev_get_drvdata(dev);
+ unsigned int num;
+
+ spin_lock_irq(&priv->lock);
+ num = priv->num_buffers;
+ spin_unlock_irq(&priv->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", num);
+}
+
+static ssize_t data_bufsize_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fpga_device *priv = dev_get_drvdata(dev);
+ size_t num;
+
+ spin_lock_irq(&priv->lock);
+ num = priv->bufsize;
+ spin_unlock_irq(&priv->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%zu\n", num);
+}
+
+static ssize_t data_inflight_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fpga_device *priv = dev_get_drvdata(dev);
+ unsigned int num;
+
+ spin_lock_irq(&priv->lock);
+ num = list_num_entries(&priv->inflight);
+ spin_unlock_irq(&priv->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", num);
+}
+
+static ssize_t data_free_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fpga_device *priv = dev_get_drvdata(dev);
+ unsigned int num;
+
+ spin_lock_irq(&priv->lock);
+ num = list_num_entries(&priv->free);
+ spin_unlock_irq(&priv->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", num);
+}
+
+static ssize_t data_used_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fpga_device *priv = dev_get_drvdata(dev);
+ unsigned int num;
+
+ spin_lock_irq(&priv->lock);
+ num = list_num_entries(&priv->used);
+ spin_unlock_irq(&priv->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", num);
+}
+
+static ssize_t data_num_dropped_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fpga_device *priv = dev_get_drvdata(dev);
+ unsigned int num;
+
+ spin_lock_irq(&priv->lock);
+ num = priv->num_dropped;
+ spin_unlock_irq(&priv->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", num);
+}
+
+static ssize_t data_en_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct fpga_device *priv = dev_get_drvdata(dev);
+ ssize_t count;
+
+ if (mutex_lock_interruptible(&priv->mutex))
+ return -ERESTARTSYS;
+
+ count = snprintf(buf, PAGE_SIZE, "%u\n", priv->enabled);
+ mutex_unlock(&priv->mutex);
+ return count;
+}
+
+static ssize_t data_en_set(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct fpga_device *priv = dev_get_drvdata(dev);
+ unsigned long enable;
+ int ret;
+
+ ret = strict_strtoul(buf, 0, &enable);
+ if (ret) {
+ dev_err(priv->dev, "unable to parse enable input\n");
+ return -EINVAL;
+ }
+
+ if (mutex_lock_interruptible(&priv->mutex))
+ return -ERESTARTSYS;
+
+ if (enable)
+ ret = data_device_enable(priv);
+ else
+ ret = data_device_disable(priv);
+
+ if (ret) {
+ dev_err(priv->dev, "device %s failed\n",
+ enable ? "enable" : "disable");
+ count = ret;
+ goto out_unlock;
+ }
+
+out_unlock:
+ mutex_unlock(&priv->mutex);
+ return count;
+}
+
+static DEVICE_ATTR(num_buffers, S_IRUGO, data_num_buffers_show, NULL);
+static DEVICE_ATTR(buffer_size, S_IRUGO, data_bufsize_show, NULL);
+static DEVICE_ATTR(num_inflight, S_IRUGO, data_inflight_show, NULL);
+static DEVICE_ATTR(num_free, S_IRUGO, data_free_show, NULL);
+static DEVICE_ATTR(num_used, S_IRUGO, data_used_show, NULL);
+static DEVICE_ATTR(num_dropped, S_IRUGO, data_num_dropped_show, NULL);
+static DEVICE_ATTR(enable, S_IWUGO | S_IRUGO, data_en_show, data_en_set);
+
+static struct attribute *data_sysfs_attrs[] = {
+ &dev_attr_num_buffers.attr,
+ &dev_attr_buffer_size.attr,
+ &dev_attr_num_inflight.attr,
+ &dev_attr_num_free.attr,
+ &dev_attr_num_used.attr,
+ &dev_attr_num_dropped.attr,
+ &dev_attr_enable.attr,
+ NULL,
+};
+
+static const struct attribute_group rt_sysfs_attr_group = {
+ .attrs = data_sysfs_attrs,
+};
+
+/*
+ * FPGA Realtime Data Character Device
+ */
+
+static int data_open(struct inode *inode, struct file *filp)
+{
+ struct fpga_device *priv = inode_to_dev(inode);
+ struct fpga_reader *reader;
+ int ret;
+
+ /* allocate private data */
+ reader = kzalloc(sizeof(*reader), GFP_KERNEL);
+ if (!reader)
+ return -ENOMEM;
+
+ reader->priv = priv;
+ reader->buf = NULL;
+
+ filp->private_data = reader;
+ ret = nonseekable_open(inode, filp);
+ if (ret) {
+ dev_err(priv->dev, "nonseekable-open failed\n");
+ kfree(reader);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int data_release(struct inode *inode, struct file *filp)
+{
+ struct fpga_reader *reader = filp->private_data;
+ struct fpga_device *priv = reader->priv;
+
+ /* free the per-reader structure */
+ data_free_buffer(priv->dmadev, reader->buf);
+ kfree(reader);
+ return 0;
+}
+
+static ssize_t data_read(struct file *filp, char __user *ubuf, size_t count,
+ loff_t *f_pos)
+{
+ struct fpga_reader *reader = filp->private_data;
+ struct fpga_device *priv = reader->priv;
+ struct list_head *used = &priv->used;
+ struct data_buf *dbuf;
+ size_t avail;
+ void *data;
+ int ret;
+
+ /* check if we already have a partial buffer */
+ if (reader->buf) {
+ dbuf = reader->buf;
+ goto have_buffer;
+ }
+
+ spin_lock_irq(&priv->lock);
+
+ /* Block until there is at least one buffer on the used list */
+ while (list_empty(used)) {
+ spin_unlock_irq(&priv->lock);
+
+ if (filp->f_flags & O_NONBLOCK)
+ return -EAGAIN;
+
+ if (wait_event_interruptible(priv->wait, !list_empty(used)))
+ return -ERESTARTSYS;
+
+ spin_lock_irq(&priv->lock);
+ }
+
+ /* Grab the first buffer off of the used list */
+ dbuf = list_first_entry(used, struct data_buf, entry);
+ list_del_init(&dbuf->entry);
+
+ spin_unlock_irq(&priv->lock);
+
+ /* Buffers are always mapped: unmap it */
+ data_unmap_buffer(priv->dmadev, dbuf);
+
+ /* save the buffer for later */
+ reader->buf = dbuf;
+ reader->buf_start = 0;
+
+ /* we removed a buffer from the used list: wake any waiters */
+ wake_up(&priv->wait);
+
+have_buffer:
+ /* Get the number of bytes available */
+ avail = dbuf->size - reader->buf_start;
+ data = dbuf->vb.vaddr + reader->buf_start;
+
+ /* Get the number of bytes we can transfer */
+ count = min(count, avail);
+
+ /* Copy the data to the userspace buffer */
+ if (copy_to_user(ubuf, data, count))
+ return -EFAULT;
+
+ /* Update the amount of available space */
+ avail -= count;
+
+ /* Lock against concurrent enable/disable */
+ if (mutex_lock_interruptible(&priv->mutex))
+ return -ERESTARTSYS;
+
+ /* Still some space available: save the buffer for later */
+ if (avail != 0) {
+ reader->buf_start += count;
+ reader->buf = dbuf;
+ goto out_unlock;
+ }
+
+ /*
+ * No space is available in this buffer
+ *
+ * This is a complicated decision:
+ * - if the device is not enabled: free the buffer
+ * - if the buffer is too small: free the buffer
+ */
+ if (!priv->enabled || dbuf->size != priv->bufsize) {
+ data_free_buffer(priv->dmadev, dbuf);
+ reader->buf = NULL;
+ goto out_unlock;
+ }
+
+ /*
+ * The buffer is safe to recycle: remap it and finish
+ *
+ * If this fails, we pretend that the read never happened, and return
+ * -EFAULT to userspace. They'll retry the read again.
+ */
+ ret = data_map_buffer(priv->dmadev, dbuf);
+ if (ret) {
+ dev_err(priv->dev, "unable to remap buffer for DMA\n");
+ count = -EFAULT;
+ goto out_unlock;
+ }
+
+ /* Add the buffer back to the free list */
+ reader->buf = NULL;
+ spin_lock_irq(&priv->lock);
+ list_add_tail(&dbuf->entry, &priv->free);
+ spin_unlock_irq(&priv->lock);
+
+out_unlock:
+ mutex_unlock(&priv->mutex);
+ return count;
+}
+
+static unsigned int data_poll(struct file *filp, struct poll_table_struct *tbl)
+{
+ struct fpga_reader *reader = filp->private_data;
+ struct fpga_device *priv = reader->priv;
+ unsigned int mask = 0;
+
+ poll_wait(filp, &priv->wait, tbl);
+
+ spin_lock_irq(&priv->lock);
+
+ if (!list_empty(&priv->used))
+ mask |= POLLIN | POLLRDNORM;
+
+ spin_unlock_irq(&priv->lock);
+ return mask;
+}
+
+static int data_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ struct fpga_reader *reader = filp->private_data;
+ struct fpga_device *priv = reader->priv;
+ unsigned long offset, vsize, psize, addr;
+
+ /* VMA properties */
+ offset = vma->vm_pgoff << PAGE_SHIFT;
+ vsize = vma->vm_end - vma->vm_start;
+ psize = priv->phys_size - offset;
+ addr = (priv->phys_addr + offset) >> PAGE_SHIFT;
+
+ /* Check against the FPGA region's physical memory size */
+ if (vsize > psize) {
+ dev_err(priv->dev, "requested mmap mapping too large\n");
+ return -EINVAL;
+ }
+
+ /* IO memory (stop cacheing) */
+ vma->vm_flags |= VM_IO | VM_RESERVED;
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ return io_remap_pfn_range(vma, vma->vm_start, addr, vsize,
+ vma->vm_page_prot);
+}
+
+static const struct file_operations data_fops = {
+ .owner = THIS_MODULE,
+ .open = data_open,
+ .release = data_release,
+ .read = data_read,
+ .poll = data_poll,
+ .mmap = data_mmap,
+ .llseek = no_llseek,
+};
+
+/*
+ * OpenFirmware Device Subsystem
+ */
+
+static bool dma_filter(struct dma_chan *chan, void *data)
+{
+ /*
+ * DMA Channel #0 is used for the FPGA Programmer, so ignore it
+ *
+ * This probably won't survive an unload/load cycle of the Freescale
+ * DMAEngine driver, but that won't be a problem
+ */
+ if (chan->chan_id == 0 && chan->device->dev_id == 0)
+ return false;
+
+ return true;
+}
+
+static int data_of_probe(struct platform_device *op,
+ const struct of_device_id *match)
+{
+ struct device_node *of_node = op->dev.of_node;
+ struct fpga_device *priv;
+ struct resource res;
+ dma_cap_mask_t mask;
+ int ret;
+
+ /* Allocate private data */
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(&op->dev, "Unable to allocate device private data\n");
+ ret = -ENOMEM;
+ goto out_return;
+ }
+
+ dev_set_drvdata(&op->dev, priv);
+ priv->dmadev = &op->dev;
+
+ /* Allocate the character device */
+ ret = alloc_chrdev_region(&priv->devno, 0, 1, drv_name);
+ if (ret) {
+ dev_err(&op->dev, "Unable to allocate chardev region\n");
+ goto out_free_priv;
+ }
+
+ /* Get the physical address of the FPGA registers */
+ ret = of_address_to_resource(of_node, 0, &res);
+ if (ret) {
+ dev_err(&op->dev, "Unable to find FPGA physical address\n");
+ ret = -ENODEV;
+ goto out_unregister_chrdev_region;
+ }
+
+ priv->phys_addr = res.start;
+ priv->phys_size = resource_size(&res);
+
+ /* ioremap the registers for use */
+ priv->regs = of_iomap(of_node, 0);
+ if (!priv->regs) {
+ dev_err(&op->dev, "Unable to ioremap registers\n");
+ ret = -ENOMEM;
+ goto out_unregister_chrdev_region;
+ }
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_MEMCPY, mask);
+ dma_cap_set(DMA_INTERRUPT, mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ /* Request a DMA channel */
+ priv->chan = dma_request_channel(mask, dma_filter, NULL);
+ if (!priv->chan) {
+ dev_err(&op->dev, "Unable to request DMA channel\n");
+ ret = -ENODEV;
+ goto out_unmap_regs;
+ }
+
+ /* Find the correct IRQ number */
+ priv->irq = irq_of_parse_and_map(of_node, 0);
+ if (priv->irq == NO_IRQ) {
+ dev_err(&op->dev, "Unable to find IRQ line\n");
+ ret = -ENODEV;
+ goto out_release_dma;
+ }
+
+ priv->dev = carma_device_create(&op->dev, priv->devno, drv_name);
+ if (IS_ERR(priv->dev)) {
+ dev_err(&op->dev, "Unable to create CARMA device\n");
+ ret = PTR_ERR(priv->dev);
+ goto out_irq_dispose_mapping;
+ }
+
+ dev_set_drvdata(priv->dev, priv);
+ cdev_init(&priv->cdev, &data_fops);
+ mutex_init(&priv->mutex);
+ spin_lock_init(&priv->lock);
+ INIT_LIST_HEAD(&priv->free);
+ INIT_LIST_HEAD(&priv->used);
+ INIT_LIST_HEAD(&priv->inflight);
+ init_waitqueue_head(&priv->wait);
+
+ /* Drive the GPIO for FPGA IRQ high (no interrupt) */
+ iowrite32be(IRQ_CORL_DONE, priv->regs + SYS_IRQ_OUTPUT_DATA);
+
+ /* Register the character device */
+ ret = cdev_add(&priv->cdev, priv->devno, 1);
+ if (ret) {
+ dev_err(&op->dev, "Unable to add character device\n");
+ goto out_destroy_carma_device;
+ }
+
+ /* Create the sysfs files */
+ ret = sysfs_create_group(&priv->dev->kobj, &rt_sysfs_attr_group);
+ if (ret) {
+ dev_err(&op->dev, "Unable to create sysfs files\n");
+ goto out_cdev_del;
+ }
+
+ dev_info(&op->dev, "CARMA FPGA Realtime Data Driver Loaded\n");
+ return 0;
+
+out_cdev_del:
+ cdev_del(&priv->cdev);
+out_destroy_carma_device:
+ carma_device_destroy(priv->devno);
+out_irq_dispose_mapping:
+ irq_dispose_mapping(priv->irq);
+out_release_dma:
+ dma_release_channel(priv->chan);
+out_unmap_regs:
+ iounmap(priv->regs);
+out_unregister_chrdev_region:
+ unregister_chrdev_region(priv->devno, 1);
+out_free_priv:
+ kfree(priv);
+out_return:
+ return ret;
+}
+
+static int data_of_remove(struct platform_device *op)
+{
+ struct fpga_device *priv = dev_get_drvdata(&op->dev);
+
+ /* make sure the IRQ line is disabled */
+ mutex_lock(&priv->mutex);
+ data_device_disable(priv);
+ mutex_unlock(&priv->mutex);
+
+ sysfs_remove_group(&priv->dev->kobj, &rt_sysfs_attr_group);
+ cdev_del(&priv->cdev);
+ carma_device_destroy(priv->devno);
+
+ irq_dispose_mapping(priv->irq);
+ dma_release_channel(priv->chan);
+ iounmap(priv->regs);
+ unregister_chrdev_region(priv->devno, 1);
+ kfree(priv);
+
+ return 0;
+}
+
+static struct of_device_id data_of_match[] = {
+ { .compatible = "carma,carma-fpga", },
+ {},
+};
+
+static struct of_platform_driver data_of_driver = {
+ .probe = data_of_probe,
+ .remove = data_of_remove,
+ .driver = {
+ .name = drv_name,
+ .of_match_table = data_of_match,
+ .owner = THIS_MODULE,
+ },
+};
+
+/*
+ * Module Init / Exit
+ */
+
+static int __init data_init(void)
+{
+ return of_register_platform_driver(&data_of_driver);
+}
+
+static void __exit data_exit(void)
+{
+ of_unregister_platform_driver(&data_of_driver);
+}
+
+MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
+MODULE_DESCRIPTION("CARMA DATA-FPGA Access Driver");
+MODULE_LICENSE("GPL");
+
+module_init(data_init);
+module_exit(data_exit);
--
1.7.1
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