* [PATCH V5 5/9] Add Synopsys DesignWare HS USB OTG HCD interrupt function.
From: Fushen Chen @ 2010-10-21 0:42 UTC (permalink / raw)
To: linux-usb; +Cc: linuxppc-dev, gregkh, Mark Miesfeld, Fushen Chen
In-Reply-To: <1287621774191-git-send-email-fchen@apm.com>
Implements DWC OTG USB HCD interrupt service routine.
Signed-off-by: Fushen Chen <fchen@apm.com>
Signed-off-by: Mark Miesfeld <mmiesfeld@apm.com>
---
drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1465 ++++++++++++++++++++++++++++++++
1 files changed, 1465 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
new file mode 100644
index 0000000..c4c8e10
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
@@ -0,0 +1,1465 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld <mmiesfeld@apm.com>
+ * Modified by Stefan Roese <sr@denx.de>, DENX Software Engineering
+ * Modified by Chuck Meade <chuck@theptrgroup.com>
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "dwc_otg_hcd.h"
+
+/* This file contains the implementation of the HCD Interrupt handlers. */
+static const int erratum_usb09_patched;
+static const int deferral_on = 1;
+static const int nak_deferral_delay = 8;
+static const int nyet_deferral_delay = 1;
+
+/**
+ * Handles the start-of-frame interrupt in host mode. Non-periodic
+ * transactions may be queued to the DWC_otg controller for the current
+ * (micro)frame. Periodic transactions may be queued to the controller for the
+ * next (micro)frame.
+ */
+static int dwc_otg_hcd_handle_sof_intr(struct dwc_hcd *hcd)
+{
+ union hfnum_data hfnum;
+ struct list_head *qh_entry;
+ struct dwc_qh *qh;
+ enum dwc_transaction_type tr_type;
+ union gintsts_data gintsts = {.d32 = 0};
+
+ hfnum.d32 =
+ dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
+
+ hcd->frame_number = hfnum.b.frnum;
+
+ /* Determine whether any periodic QHs should be executed. */
+ qh_entry = hcd->periodic_sched_inactive.next;
+ while (qh_entry != &hcd->periodic_sched_inactive) {
+ qh = list_entry(qh_entry, struct dwc_qh, qh_list_entry);
+ qh_entry = qh_entry->next;
+
+ /*
+ * If needed, move QH to the ready list to be executed next
+ * (micro)frame.
+ */
+ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number))
+ list_move(&qh->qh_list_entry,
+ &hcd->periodic_sched_ready);
+ }
+
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+
+ /* Clear interrupt */
+ gintsts.b.sofintr = 1;
+ dwc_write_reg32(gintsts_reg(hcd), gintsts.d32);
+ return 1;
+}
+
+/**
+ * Handles the Rx Status Queue Level Interrupt, which indicates that there is at
+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to
+ * memory if the DWC_otg controller is operating in Slave mode.
+ */
+static int dwc_otg_hcd_handle_rx_status_q_level_intr(struct dwc_hcd *hcd)
+{
+ union host_grxsts_data grxsts;
+ struct dwc_hc *hc = NULL;
+
+ grxsts.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->grxstsp);
+ hc = hcd->hc_ptr_array[grxsts.b.chnum];
+
+ /* Packet Status */
+ switch (grxsts.b.pktsts) {
+ case DWC_GRXSTS_PKTSTS_IN:
+ /* Read the data into the host buffer. */
+ if (grxsts.b.bcnt > 0) {
+ dwc_otg_read_packet(hcd->core_if, hc->xfer_buff,
+ grxsts.b.bcnt);
+ /* Update the HC fields for the next packet received. */
+ hc->xfer_count += grxsts.b.bcnt;
+ hc->xfer_buff += grxsts.b.bcnt;
+ }
+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
+ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+ case DWC_GRXSTS_PKTSTS_CH_HALTED:
+ /* Handled in interrupt, just ignore data */
+ break;
+ default:
+ printk(KERN_ERR "RX_STS_Q Interrupt: Unknown status %d\n",
+ grxsts.b.pktsts);
+ break;
+ }
+ return 1;
+}
+
+/**
+ * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
+ * data packets may be written to the FIFO for OUT transfers. More requests
+ * may be written to the non-periodic request queue for IN transfers. This
+ * interrupt is enabled only in Slave mode.
+ */
+static int dwc_otg_hcd_handle_np_tx_fifo_empty_intr(struct dwc_hcd *hcd)
+{
+ dwc_otg_hcd_queue_transactions(hcd, DWC_OTG_TRANSACTION_NON_PERIODIC);
+ return 1;
+}
+
+/**
+ * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
+ * packets may be written to the FIFO for OUT transfers. More requests may be
+ * written to the periodic request queue for IN transfers. This interrupt is
+ * enabled only in Slave mode.
+ */
+static int dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(struct dwc_hcd *hcd)
+{
+ dwc_otg_hcd_queue_transactions(hcd, DWC_OTG_TRANSACTION_PERIODIC);
+ return 1;
+}
+
+/**
+ * When the port changes to enabled it may be necessary to adjust the phy clock
+ * speed.
+ */
+static int adjusted_phy_clock_speed(struct dwc_hcd *hcd, union hprt0_data hprt0)
+{
+ int adjusted = 0;
+ union gusbcfg_data usbcfg;
+ struct core_params *params = hcd->core_if->core_params;
+ struct core_global_regs *g_regs = hcd->core_if->core_global_regs;
+ struct host_global_regs *h_regs =
+ hcd->core_if->host_if->host_global_regs;
+
+ usbcfg.d32 = dwc_read_reg32(&g_regs->gusbcfg);
+
+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ||
+ hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
+ /* Low power */
+ union hcfg_data hcfg;
+
+ if (usbcfg.b.phylpwrclksel == 0) {
+ /* Set PHY low power clock select for FS/LS devices */
+ usbcfg.b.phylpwrclksel = 1;
+ dwc_write_reg32(&g_regs->gusbcfg, usbcfg.d32);
+ adjusted = 1;
+ }
+
+ hcfg.d32 = dwc_read_reg32(&h_regs->hcfg);
+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED &&
+ params->host_ls_low_power_phy_clk ==
+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
+ /* 6 MHZ, check for 6 MHZ clock select */
+ if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
+ hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
+ dwc_write_reg32(&h_regs->hcfg, hcfg.d32);
+ adjusted = 1;
+ }
+ } else if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
+ /* 48 MHZ and clock select is not 48 MHZ */
+ hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
+ dwc_write_reg32(&h_regs->hcfg, hcfg.d32);
+ adjusted = 1;
+ }
+ } else if (usbcfg.b.phylpwrclksel == 1) {
+ usbcfg.b.phylpwrclksel = 0;
+ dwc_write_reg32(&g_regs->gusbcfg, usbcfg.d32);
+ adjusted = 1;
+ }
+ if (adjusted)
+ schedule_work(&hcd->usb_port_reset);
+
+ return adjusted;
+}
+
+/**
+ * Helper function to handle the port enable changed interrupt when the port
+ * becomes enabled. Checks if we need to adjust the PHY clock speed for low
+ * power and adjusts it if needed.
+ */
+static void port_enabled(struct dwc_hcd *hcd, union hprt0_data hprt0)
+{
+ if (hcd->core_if->core_params->host_support_fs_ls_low_power)
+ if (!adjusted_phy_clock_speed(hcd, hprt0))
+ hcd->flags.b.port_reset_change = 1;
+}
+
+/**
+ * There are multiple conditions that can cause a port interrupt. This function
+ * determines which interrupt conditions have occurred and handles them
+ * appropriately.
+ */
+static int dwc_otg_hcd_handle_port_intr(struct dwc_hcd *hcd)
+{
+ int retval = 0;
+ union hprt0_data hprt0;
+ union hprt0_data hprt0_modify;
+
+ hprt0.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
+ hprt0_modify.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
+
+ /*
+ * Clear appropriate bits in HPRT0 to clear the interrupt bit in
+ * GINTSTS
+ */
+ hprt0_modify.b.prtena = 0;
+ hprt0_modify.b.prtconndet = 0;
+ hprt0_modify.b.prtenchng = 0;
+ hprt0_modify.b.prtovrcurrchng = 0;
+
+ /* Port connect detected interrupt */
+ if (hprt0.b.prtconndet) {
+ /* Set the status flags and clear interrupt*/
+ hcd->flags.b.port_connect_status_change = 1;
+ hcd->flags.b.port_connect_status = 1;
+ hprt0_modify.b.prtconndet = 1;
+
+ /* B-Device has connected, Delete the connection timer. */
+ del_timer_sync(&hcd->conn_timer);
+
+ /*
+ * The Hub driver asserts a reset when it sees port connect
+ * status change flag
+ */
+ retval |= 1;
+ }
+
+ /* Port enable changed interrupt */
+ if (hprt0.b.prtenchng) {
+ /* Set the internal flag if the port was disabled */
+ if (hprt0.b.prtena)
+ port_enabled(hcd, hprt0);
+ else
+ hcd->flags.b.port_enable_change = 1;
+
+ /* Clear the interrupt */
+ hprt0_modify.b.prtenchng = 1;
+ retval |= 1;
+ }
+
+ /* Overcurrent change interrupt */
+ if (hprt0.b.prtovrcurrchng) {
+ hcd->flags.b.port_over_current_change = 1;
+ hprt0_modify.b.prtovrcurrchng = 1;
+ retval |= 1;
+ }
+
+ /* Clear the port interrupts */
+ dwc_write_reg32(hcd->core_if->host_if->hprt0, hprt0_modify.d32);
+ return retval;
+}
+
+/**
+ * Gets the actual length of a transfer after the transfer halts. halt_status
+ * holds the reason for the halt.
+ *
+ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, _short_read
+ * is set to 1 upon return if less than the requested number of bytes were
+ * transferred. Otherwise, _short_read is set to 0 upon return. _short_read may
+ * also be NULL on entry, in which case it remains unchanged.
+ */
+static u32 get_actual_xfer_length(struct dwc_hc *hc, struct dwc_hc_regs *regs,
+ struct dwc_qtd *qtd, enum dwc_halt_status halt_status,
+ int *_short_read)
+{
+ union hctsiz_data hctsiz;
+ u32 length;
+
+ if (_short_read)
+ *_short_read = 0;
+
+ hctsiz.d32 = dwc_read_reg32(®s->hctsiz);
+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+ if (hc->ep_is_in) {
+ length = hc->xfer_len - hctsiz.b.xfersize;
+ if (_short_read)
+ *_short_read = (hctsiz.b.xfersize != 0);
+ } else if (hc->qh->do_split) {
+ length = qtd->ssplit_out_xfer_count;
+ } else {
+ length = hc->xfer_len;
+ }
+ } else {
+ /*
+ * Must use the hctsiz.pktcnt field to determine how much data
+ * has been transferred. This field reflects the number of
+ * packets that have been transferred via the USB. This is
+ * always an integral number of packets if the transfer was
+ * halted before its normal completion. (Can't use the
+ * hctsiz.xfersize field because that reflects the number of
+ * bytes transferred via the AHB, not the USB).
+ */
+ length = (hc->start_pkt_count - hctsiz.b.pktcnt) *
+ hc->max_packet;
+ }
+ return length;
+}
+
+/**
+ * Updates the state of the URB after a Transfer Complete interrupt on the
+ * host channel. Updates the actual_length field of the URB based on the
+ * number of bytes transferred via the host channel. Sets the URB status
+ * if the data transfer is finished.
+ */
+static int update_urb_state_xfer_comp(struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct urb *urb,
+ struct dwc_qtd *qtd, int *status)
+{
+ int xfer_done = 0;
+ int short_read = 0;
+
+ urb->actual_length += get_actual_xfer_length(hc, regs, qtd,
+ DWC_OTG_HC_XFER_COMPLETE, &short_read);
+
+ if (short_read || urb->actual_length == urb->transfer_buffer_length) {
+ xfer_done = 1;
+ if (short_read && (urb->transfer_flags & URB_SHORT_NOT_OK))
+ *status = -EREMOTEIO;
+ else
+ *status = 0;
+ }
+ return xfer_done;
+}
+
+/*
+ * Save the starting data toggle for the next transfer. The data toggle is
+ * saved in the QH for non-control transfers and it's saved in the QTD for
+ * control transfers.
+ */
+static void save_data_toggle(struct dwc_hc *hc, struct dwc_hc_regs *regs,
+ struct dwc_qtd *qtd)
+{
+ union hctsiz_data hctsiz;
+ hctsiz.d32 = dwc_read_reg32(®s->hctsiz);
+
+ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
+ struct dwc_qh *qh = hc->qh;
+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0)
+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+ else
+ qh->data_toggle = DWC_OTG_HC_PID_DATA1;
+ } else {
+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0)
+ qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
+ else
+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
+ }
+}
+
+/**
+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
+ * still linked to the QH, the QH is added to the end of the inactive
+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic
+ * schedule if no more QTDs are linked to the QH.
+ */
+static void deactivate_qh(struct dwc_hcd *hcd, struct dwc_qh *qh, int free_qtd)
+{
+ int continue_split = 0;
+ struct dwc_qtd *qtd;
+
+ qtd = list_entry(qh->qtd_list.next, struct dwc_qtd, qtd_list_entry);
+ if (qtd->complete_split)
+ continue_split = 1;
+ else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
+ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END)
+ continue_split = 1;
+
+ if (free_qtd) {
+ dwc_otg_hcd_qtd_remove(qtd);
+ continue_split = 0;
+ }
+
+ qh->channel = NULL;
+ qh->qtd_in_process = NULL;
+ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
+}
+
+/**
+ * Updates the state of an Isochronous URB when the transfer is stopped for
+ * any reason. The fields of the current entry in the frame descriptor array
+ * are set based on the transfer state and the input status. Completes the
+ * Isochronous URB if all the URB frames have been completed.
+ */
+static enum dwc_halt_status update_isoc_urb_state(struct dwc_hcd *hcd,
+ struct dwc_hc *hc, struct dwc_hc_regs *regs,
+ struct dwc_qtd *qtd, enum dwc_halt_status status)
+{
+ struct urb *urb = qtd->urb;
+ enum dwc_halt_status ret_val = status;
+ struct usb_iso_packet_descriptor *frame_desc;
+ frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
+
+ switch (status) {
+ case DWC_OTG_HC_XFER_COMPLETE:
+ frame_desc->status = 0;
+ frame_desc->actual_length =
+ get_actual_xfer_length(hc, regs, qtd, status, NULL);
+ break;
+ case DWC_OTG_HC_XFER_FRAME_OVERRUN:
+ urb->error_count++;
+ if (hc->ep_is_in)
+ frame_desc->status = -ENOSR;
+ else
+ frame_desc->status = -ECOMM;
+
+ frame_desc->actual_length = 0;
+ break;
+ case DWC_OTG_HC_XFER_BABBLE_ERR:
+ /* Don't need to update actual_length in this case. */
+ urb->error_count++;
+ frame_desc->status = -EOVERFLOW;
+ break;
+ case DWC_OTG_HC_XFER_XACT_ERR:
+ urb->error_count++;
+ frame_desc->status = -EPROTO;
+ frame_desc->actual_length =
+ get_actual_xfer_length(hc, regs, qtd, status, NULL);
+ default:
+ printk(KERN_ERR "%s: Unhandled halt_status (%d)\n", __func__,
+ status);
+ BUG();
+ break;
+ }
+
+ if (++qtd->isoc_frame_index == urb->number_of_packets) {
+ /*
+ * urb->status is not used for isoc transfers.
+ * The individual frame_desc statuses are used instead.
+ */
+ dwc_otg_hcd_complete_urb(hcd, urb, 0);
+ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
+ } else {
+ ret_val = DWC_OTG_HC_XFER_COMPLETE;
+ }
+ return ret_val;
+}
+
+/**
+ * Releases a host channel for use by other transfers. Attempts to select and
+ * queue more transactions since at least one host channel is available.
+ */
+static void release_channel(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_qtd *qtd, enum dwc_halt_status halt_status,
+ int *must_free)
+{
+ enum dwc_transaction_type tr_type;
+ int free_qtd;
+ int deact = 1;
+ struct dwc_qh *qh;
+ int retry_delay = 1;
+
+ switch (halt_status) {
+ case DWC_OTG_HC_XFER_NYET:
+ case DWC_OTG_HC_XFER_NAK:
+ if (halt_status == DWC_OTG_HC_XFER_NYET)
+ retry_delay = nyet_deferral_delay;
+ else
+ retry_delay = nak_deferral_delay;
+ free_qtd = 0;
+ if (deferral_on && hc->do_split) {
+ qh = hc->qh;
+ if (qh)
+ deact = dwc_otg_hcd_qh_deferr(hcd, qh,
+ retry_delay);
+ }
+ break;
+ case DWC_OTG_HC_XFER_URB_COMPLETE:
+ free_qtd = 1;
+ break;
+ case DWC_OTG_HC_XFER_AHB_ERR:
+ case DWC_OTG_HC_XFER_STALL:
+ case DWC_OTG_HC_XFER_BABBLE_ERR:
+ free_qtd = 1;
+ break;
+ case DWC_OTG_HC_XFER_XACT_ERR:
+ if (qtd->error_count >= 3) {
+ free_qtd = 1;
+ dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPROTO);
+ } else {
+ free_qtd = 0;
+ }
+ break;
+ case DWC_OTG_HC_XFER_URB_DEQUEUE:
+ /*
+ * The QTD has already been removed and the QH has been
+ * deactivated. Don't want to do anything except release the
+ * host channel and try to queue more transfers.
+ */
+ goto cleanup;
+ case DWC_OTG_HC_XFER_NO_HALT_STATUS:
+ printk(KERN_ERR "%s: No halt_status, channel %d\n", __func__,
+ hc->hc_num);
+ free_qtd = 0;
+ break;
+ default:
+ free_qtd = 0;
+ break;
+ }
+ if (free_qtd)
+ /* must_free pre-initialized to zero */
+ *must_free = 1;
+ if (deact)
+ deactivate_qh(hcd, hc->qh, free_qtd);
+
+cleanup:
+ /*
+ * Release the host channel for use by other transfers. The cleanup
+ * function clears the channel interrupt enables and conditions, so
+ * there's no need to clear the Channel Halted interrupt separately.
+ */
+ dwc_otg_hc_cleanup(hcd->core_if, hc);
+ list_add_tail(&hc->hc_list_entry, &hcd->free_hc_list);
+ hcd->available_host_channels++;
+ /* Try to queue more transfers now that there's a free channel. */
+ if (!erratum_usb09_patched) {
+ tr_type = dwc_otg_hcd_select_transactions(hcd);
+ if (tr_type != DWC_OTG_TRANSACTION_NONE)
+ dwc_otg_hcd_queue_transactions(hcd, tr_type);
+ }
+}
+
+/**
+ * Halts a host channel. If the channel cannot be halted immediately because
+ * the request queue is full, this function ensures that the FIFO empty
+ * interrupt for the appropriate queue is enabled so that the halt request can
+ * be queued when there is space in the request queue.
+ *
+ * This function may also be called in DMA mode. In that case, the channel is
+ * simply released since the core always halts the channel automatically in
+ * DMA mode.
+ */
+static void halt_channel(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_qtd *qtd, enum dwc_halt_status halt_status, int *must_free)
+{
+ if (hcd->core_if->dma_enable) {
+ release_channel(hcd, hc, qtd, halt_status, must_free);
+ return;
+ }
+
+ /* Slave mode processing... */
+ dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
+ if (hc->halt_on_queue) {
+ union gintmsk_data gintmsk = {.d32 = 0};
+
+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
+ /*
+ * Make sure the Non-periodic Tx FIFO empty interrupt
+ * is enabled so that the non-periodic schedule will
+ * be processed.
+ */
+ gintmsk.b.nptxfempty = 1;
+ dwc_modify_reg32(gintmsk_reg(hcd), 0, gintmsk.d32);
+ } else {
+ /*
+ * Move the QH from the periodic queued schedule to
+ * the periodic assigned schedule. This allows the
+ * halt to be queued when the periodic schedule is
+ * processed.
+ */
+ list_move(&hc->qh->qh_list_entry,
+ &hcd->periodic_sched_assigned);
+
+ /*
+ * Make sure the Periodic Tx FIFO Empty interrupt is
+ * enabled so that the periodic schedule will be
+ * processed.
+ */
+ gintmsk.b.ptxfempty = 1;
+ dwc_modify_reg32(gintmsk_reg(hcd), 0, gintmsk.d32);
+ }
+ }
+}
+
+/**
+ * Performs common cleanup for non-periodic transfers after a Transfer
+ * Complete interrupt. This function should be called after any endpoint type
+ * specific handling is finished to release the host channel.
+ */
+static void complete_non_periodic_xfer(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd,
+ enum dwc_halt_status halt_status, int *must_free)
+{
+ union hcint_data hcint;
+
+ qtd->error_count = 0;
+ hcint.d32 = dwc_read_reg32(®s->hcint);
+ if (hcint.b.nyet) {
+ union hcint_data hcint_clear = { .d32 = 0};
+
+ hcint_clear.b.nyet = 1;
+ /*
+ * Got a NYET on the last transaction of the transfer. This
+ * means that the endpoint should be in the PING state at the
+ * beginning of the next transfer.
+ */
+ hc->qh->ping_state = 1;
+ dwc_write_reg32(&(regs->hcint), hcint_clear.d32);
+ }
+
+ /*
+ * Always halt and release the host channel to make it available for
+ * more transfers. There may still be more phases for a control
+ * transfer or more data packets for a bulk transfer at this point,
+ * but the host channel is still halted. A channel will be reassigned
+ * to the transfer when the non-periodic schedule is processed after
+ * the channel is released. This allows transactions to be queued
+ * properly via dwc_otg_hcd_queue_transactions, which also enables the
+ * Tx FIFO Empty interrupt if necessary.
+ *
+ * IN transfers in Slave mode require an explicit disable to
+ * halt the channel. (In DMA mode, this call simply releases
+ * the channel.)
+ *
+ * The channel is automatically disabled by the core for OUT
+ * transfers in Slave mode.
+ */
+ if (hc->ep_is_in)
+ halt_channel(hcd, hc, qtd, halt_status, must_free);
+ else
+ release_channel(hcd, hc, qtd, halt_status, must_free);
+}
+
+/**
+ * Performs common cleanup for periodic transfers after a Transfer Complete
+ * interrupt. This function should be called after any endpoint type specific
+ * handling is finished to release the host channel.
+ */
+static void complete_periodic_xfer(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd,
+ enum dwc_halt_status halt_status, int *must_free)
+{
+ union hctsiz_data hctsiz;
+
+ hctsiz.d32 = dwc_read_reg32(®s->hctsiz);
+ qtd->error_count = 0;
+
+ /*
+ * For OUT transfers and 0 packet count, the Core halts the channel,
+ * otherwise, Flush any outstanding requests from the Tx queue.
+ */
+ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0)
+ release_channel(hcd, hc, qtd, halt_status, must_free);
+ else
+ halt_channel(hcd, hc, qtd, halt_status, must_free);
+}
+
+/**
+ * Handles a host channel Transfer Complete interrupt. This handler may be
+ * called in either DMA mode or Slave mode.
+ */
+static int handle_hc_xfercomp_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ int urb_xfer_done;
+ enum dwc_halt_status halt_status = DWC_OTG_HC_XFER_COMPLETE;
+ struct urb *urb = qtd->urb;
+ int pipe_type = usb_pipetype(urb->pipe);
+ int status = -EINPROGRESS;
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ /* Handle xfer complete on CSPLIT. */
+ if (hc->qh->do_split)
+ qtd->complete_split = 0;
+
+ /* Update the QTD and URB states. */
+ switch (pipe_type) {
+ case PIPE_CONTROL:
+ switch (qtd->control_phase) {
+ case DWC_OTG_CONTROL_SETUP:
+ if (urb->transfer_buffer_length > 0)
+ qtd->control_phase = DWC_OTG_CONTROL_DATA;
+ else
+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
+ break;
+ case DWC_OTG_CONTROL_DATA:
+ urb_xfer_done = update_urb_state_xfer_comp(hc, regs,
+ urb, qtd, &status);
+ if (urb_xfer_done)
+ qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+ else
+ save_data_toggle(hc, regs, qtd);
+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
+ break;
+ case DWC_OTG_CONTROL_STATUS:
+ if (status == -EINPROGRESS)
+ status = 0;
+ dwc_otg_hcd_complete_urb(hcd, urb, status);
+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+ break;
+ }
+ complete_non_periodic_xfer(hcd, hc, regs, qtd,
+ halt_status, must_free);
+ break;
+ case PIPE_BULK:
+ urb_xfer_done = update_urb_state_xfer_comp(hc, regs, urb, qtd,
+ &status);
+ if (urb_xfer_done) {
+ dwc_otg_hcd_complete_urb(hcd, urb, status);
+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+ } else {
+ halt_status = DWC_OTG_HC_XFER_COMPLETE;
+ }
+
+ save_data_toggle(hc, regs, qtd);
+ complete_non_periodic_xfer(hcd, hc, regs, qtd,
+ halt_status, must_free);
+ break;
+ case PIPE_INTERRUPT:
+ update_urb_state_xfer_comp(hc, regs, urb, qtd, &status);
+ /*
+ * Interrupt URB is done on the first transfer complete
+ * interrupt.
+ */
+ dwc_otg_hcd_complete_urb(hcd, urb, status);
+ save_data_toggle(hc, regs, qtd);
+ complete_periodic_xfer(hcd, hc, regs, qtd,
+ DWC_OTG_HC_XFER_URB_COMPLETE, must_free);
+ break;
+ case PIPE_ISOCHRONOUS:
+ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
+ halt_status = update_isoc_urb_state(hcd, hc, regs, qtd,
+ DWC_OTG_HC_XFER_COMPLETE);
+ }
+ complete_periodic_xfer(hcd, hc, regs, qtd,
+ halt_status, must_free);
+ break;
+ }
+
+ /* disable xfercompl */
+ hcintmsk.b.xfercompl = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+
+ return 1;
+}
+
+/**
+ * Handles a host channel STALL interrupt. This handler may be called in
+ * either DMA mode or Slave mode.
+ */
+static int handle_hc_stall_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ struct urb *urb = qtd->urb;
+ int pipe_type = usb_pipetype(urb->pipe);
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ if (pipe_type == PIPE_CONTROL)
+ dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPIPE);
+
+ if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
+ dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPIPE);
+ /*
+ * USB protocol requires resetting the data toggle for bulk
+ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
+ * setup command is issued to the endpoint. Anticipate the
+ * CLEAR_FEATURE command since a STALL has occurred and reset
+ * the data toggle now.
+ */
+ hc->qh->data_toggle = 0;
+ }
+
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL, must_free);
+ /* disable stall */
+ hcintmsk.b.stall = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+
+ return 1;
+}
+
+/**
+ * Updates the state of the URB when a transfer has been stopped due to an
+ * abnormal condition before the transfer completes. Modifies the
+ * actual_length field of the URB to reflect the number of bytes that have
+ * actually been transferred via the host channel.
+ */
+static void update_urb_state_xfer_intr(struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct urb *urb, struct dwc_qtd *qtd,
+ enum dwc_halt_status sts)
+{
+ u32 xfr_len = get_actual_xfer_length(hc, regs, qtd, sts, NULL);
+ urb->actual_length += xfr_len;
+}
+
+/**
+ * Handles a host channel NAK interrupt. This handler may be called in either
+ * DMA mode or Slave mode.
+ */
+static int handle_hc_nak_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ /*
+ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
+ * interrupt. Re-start the SSPLIT transfer.
+ */
+ if (hc->do_split) {
+ if (hc->complete_split)
+ qtd->error_count = 0;
+
+ qtd->complete_split = 0;
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK, must_free);
+ goto handle_nak_done;
+ }
+ switch (usb_pipetype(qtd->urb->pipe)) {
+ case PIPE_CONTROL:
+ case PIPE_BULK:
+ if (hcd->core_if->dma_enable && hc->ep_is_in) {
+ /*
+ * NAK interrupts are enabled on bulk/control IN
+ * transfers in DMA mode for the sole purpose of
+ * resetting the error count after a transaction error
+ * occurs. The core will continue transferring data.
+ */
+ qtd->error_count = 0;
+ goto handle_nak_done;
+ }
+
+ /*
+ * NAK interrupts normally occur during OUT transfers in DMA
+ * or Slave mode. For IN transfers, more requests will be
+ * queued as request queue space is available.
+ */
+ qtd->error_count = 0;
+ if (!hc->qh->ping_state) {
+ update_urb_state_xfer_intr(hc, regs, qtd->urb, qtd,
+ DWC_OTG_HC_XFER_NAK);
+
+ save_data_toggle(hc, regs, qtd);
+ if (qtd->urb->dev->speed == USB_SPEED_HIGH)
+ hc->qh->ping_state = 1;
+ }
+
+ /*
+ * Halt the channel so the transfer can be re-started from
+ * the appropriate point or the PING protocol will
+ * start/continue.
+ */
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK, must_free);
+ break;
+ case PIPE_INTERRUPT:
+ qtd->error_count = 0;
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK, must_free);
+ break;
+ case PIPE_ISOCHRONOUS:
+ /* Should never get called for isochronous transfers. */
+ BUG();
+ break;
+ }
+
+handle_nak_done:
+ /* disable nak */
+ hcintmsk.b.nak = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+
+ return 1;
+}
+
+/**
+ * Helper function for handle_hc_ack_intr(). Sets the split values for an ACK
+ * on SSPLIT for ISOC OUT.
+ */
+static void set_isoc_out_vals(struct dwc_hc *hc, struct dwc_qtd *qtd)
+{
+ struct usb_iso_packet_descriptor *frame_desc;
+
+ switch (hc->xact_pos) {
+ case DWC_HCSPLIT_XACTPOS_ALL:
+ break;
+ case DWC_HCSPLIT_XACTPOS_END:
+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
+ qtd->isoc_split_offset = 0;
+ break;
+ case DWC_HCSPLIT_XACTPOS_BEGIN:
+ case DWC_HCSPLIT_XACTPOS_MID:
+ /*
+ * For BEGIN or MID, calculate the length for the next
+ * microframe to determine the correct SSPLIT token, either MID
+ * or END.
+ */
+ frame_desc = &qtd->urb->iso_frame_desc[qtd->isoc_frame_index];
+ qtd->isoc_split_offset += 188;
+
+ if ((frame_desc->length - qtd->isoc_split_offset) <= 188)
+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
+ else
+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
+
+ break;
+ }
+}
+
+/**
+ * Handles a host channel ACK interrupt. This interrupt is enabled when
+ * performing the PING protocol in Slave mode, when errors occur during
+ * either Slave mode or DMA mode, and during Start Split transactions.
+ */
+static int handle_hc_ack_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd,
+ int *must_free)
+{
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ if (hc->do_split) {
+ /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
+ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP)
+ qtd->ssplit_out_xfer_count = hc->xfer_len;
+
+ /* Don't need complete for isochronous out transfers. */
+ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in))
+ qtd->complete_split = 1;
+
+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)
+ set_isoc_out_vals(hc, qtd);
+ else
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK,
+ must_free);
+ } else {
+ qtd->error_count = 0;
+ if (hc->qh->ping_state) {
+ hc->qh->ping_state = 0;
+
+ /*
+ * Halt the channel so the transfer can be re-started
+ * from the appropriate point. This only happens in
+ * Slave mode. In DMA mode, the ping_state is cleared
+ * when the transfer is started because the core
+ * automatically executes the PING, then the transfer.
+ */
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK,
+ must_free);
+ }
+ }
+
+ /*
+ * If the ACK occurred when _not_ in the PING state, let the channel
+ * continue transferring data after clearing the error count.
+ */
+ /* disable ack */
+ hcintmsk.b.ack = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+
+ return 1;
+}
+
+/**
+ * Handles a host channel NYET interrupt. This interrupt should only occur on
+ * Bulk and Control OUT endpoints and for complete split transactions. If a
+ * NYET occurs at the same time as a Transfer Complete interrupt, it is
+ * handled in the xfercomp interrupt handler, not here. This handler may be
+ * called in either DMA mode or Slave mode.
+ */
+static int handle_hc_nyet_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+ union hcint_data hcint_clear = {.d32 = 0};
+
+ /*
+ * NYET on CSPLIT
+ * re-do the CSPLIT immediately on non-periodic
+ */
+ if (hc->do_split && hc->complete_split) {
+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+ int frnum = dwc_otg_hcd_get_frame_number(
+ dwc_otg_hcd_to_hcd(hcd));
+ if (dwc_full_frame_num(frnum) !=
+ dwc_full_frame_num(hc->qh->sched_frame)) {
+ qtd->complete_split = 0;
+ halt_channel(hcd, hc, qtd,
+ DWC_OTG_HC_XFER_XACT_ERR, must_free);
+ goto handle_nyet_done;
+ }
+ }
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET, must_free);
+ goto handle_nyet_done;
+ }
+ hc->qh->ping_state = 1;
+ qtd->error_count = 0;
+ update_urb_state_xfer_intr(hc, regs, qtd->urb, qtd,
+ DWC_OTG_HC_XFER_NYET);
+ save_data_toggle(hc, regs, qtd);
+ /*
+ * Halt the channel and re-start the transfer so the PING
+ * protocol will start.
+ */
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET, must_free);
+
+handle_nyet_done:
+ /* disable nyet */
+ hcintmsk.b.nyet = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+ /* clear nyet */
+ hcint_clear.b.nyet = 1;
+ dwc_write_reg32(&(regs->hcint), hcint_clear.d32);
+ return 1;
+}
+
+/**
+ * Handles a host channel babble interrupt. This handler may be called in
+ * either DMA mode or Slave mode.
+ */
+static int handle_hc_babble_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+ dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EOVERFLOW);
+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR,
+ must_free);
+ } else {
+ enum dwc_halt_status halt_status;
+ halt_status = update_isoc_urb_state(hcd, hc, regs, qtd,
+ DWC_OTG_HC_XFER_BABBLE_ERR);
+ halt_channel(hcd, hc, qtd, halt_status, must_free);
+ }
+ /* disable bblerr */
+ hcintmsk.b.bblerr = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+ return 1;
+}
+
+/**
+ * Handles a host channel AHB error interrupt. This handler is only called in
+ * DMA mode.
+ */
+static int handle_hc_ahberr_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd)
+{
+ union hcchar_data hcchar;
+ union hcsplt_data hcsplt;
+ union hctsiz_data hctsiz;
+ u32 hcdma;
+ struct urb *urb = qtd->urb;
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ hcchar.d32 = dwc_read_reg32(®s->hcchar);
+ hcsplt.d32 = dwc_read_reg32(®s->hcsplt);
+ hctsiz.d32 = dwc_read_reg32(®s->hctsiz);
+ hcdma = dwc_read_reg32(®s->hcdma);
+
+ printk(KERN_ERR "AHB ERROR, Channel %d\n", hc->hc_num);
+ printk(KERN_ERR " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
+ hcsplt.d32);
+ printk(KERN_ERR " hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
+
+ printk(KERN_ERR " Device address: %d\n", usb_pipedevice(urb->pipe));
+ printk(KERN_ERR " Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
+ (usb_pipein(urb->pipe) ? "IN" : "OUT"));
+
+ printk(KERN_ERR " Endpoint type: %s\n", pipetype_str(urb->pipe));
+ printk(KERN_ERR " Speed: %s\n", dev_speed_str(urb->dev->speed));
+ printk(KERN_ERR " Max packet size: %d\n",
+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
+ printk(KERN_ERR " Data buffer length: %d\n",
+ urb->transfer_buffer_length);
+ printk(KERN_ERR " Transfer buffer: %p, Transfer DMA: %p\n",
+ urb->transfer_buffer, (void *) (u32) urb->transfer_dma);
+ printk(KERN_ERR " Setup buffer: %p, Setup DMA: %p\n",
+ urb->setup_packet, (void *) (u32) urb->setup_dma);
+ printk(KERN_ERR " Interval: %d\n", urb->interval);
+
+ dwc_otg_hcd_complete_urb(hcd, urb, -EIO);
+
+ /*
+ * Force a channel halt. Don't call halt_channel because that won't
+ * write to the HCCHARn register in DMA mode to force the halt.
+ */
+ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
+ /* disable ahberr */
+ hcintmsk.b.ahberr = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+
+ return 1;
+}
+
+/**
+ * Handles a host channel transaction error interrupt. This handler may be
+ * called in either DMA mode or Slave mode.
+ */
+static int handle_hc_xacterr_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ enum dwc_halt_status status = DWC_OTG_HC_XFER_XACT_ERR;
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ switch (usb_pipetype(qtd->urb->pipe)) {
+ case PIPE_CONTROL:
+ case PIPE_BULK:
+ qtd->error_count++;
+ if (!hc->qh->ping_state) {
+ update_urb_state_xfer_intr(hc, regs, qtd->urb, qtd,
+ status);
+ save_data_toggle(hc, regs, qtd);
+
+ if (!hc->ep_is_in && qtd->urb->dev->speed ==
+ USB_SPEED_HIGH)
+ hc->qh->ping_state = 1;
+ }
+ /*
+ * Halt the channel so the transfer can be re-started from
+ * the appropriate point or the PING protocol will start.
+ */
+ halt_channel(hcd, hc, qtd, status, must_free);
+ break;
+ case PIPE_INTERRUPT:
+ qtd->error_count++;
+ if (hc->do_split && hc->complete_split)
+ qtd->complete_split = 0;
+
+ halt_channel(hcd, hc, qtd, status, must_free);
+ break;
+ case PIPE_ISOCHRONOUS:
+ status = update_isoc_urb_state(hcd, hc, regs, qtd, status);
+ halt_channel(hcd, hc, qtd, status, must_free);
+ break;
+ }
+ /* Disable xacterr */
+ hcintmsk.b.xacterr = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+
+ return 1;
+}
+
+/**
+ * Handles a host channel frame overrun interrupt. This handler may be called
+ * in either DMA mode or Slave mode.
+ */
+static int handle_hc_frmovrun_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ enum dwc_halt_status status = DWC_OTG_HC_XFER_FRAME_OVERRUN;
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ switch (usb_pipetype(qtd->urb->pipe)) {
+ case PIPE_CONTROL:
+ case PIPE_BULK:
+ break;
+ case PIPE_INTERRUPT:
+ halt_channel(hcd, hc, qtd, status, must_free);
+ break;
+ case PIPE_ISOCHRONOUS:
+ status = update_isoc_urb_state(hcd, hc, regs, qtd, status);
+ halt_channel(hcd, hc, qtd, status, must_free);
+ break;
+ }
+ /* Disable frmovrun */
+ hcintmsk.b.frmovrun = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+
+ return 1;
+}
+
+/**
+ * Handles a host channel data toggle error interrupt. This handler may be
+ * called in either DMA mode or Slave mode.
+ */
+static int handle_hc_datatglerr_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd)
+{
+ union hcintmsk_data hcintmsk = {.d32 = 0};
+
+ if (hc->ep_is_in)
+ qtd->error_count = 0;
+ else
+ printk(KERN_ERR "Data Toggle Error on OUT transfer, channel "
+ "%d\n", hc->hc_num);
+
+ /* disable datatglerr */
+ hcintmsk.b.datatglerr = 1;
+ dwc_modify_reg32(®s->hcintmsk, hcintmsk.d32, 0);
+
+ return 1;
+}
+
+/**
+ * Handles a host Channel Halted interrupt in DMA mode. This handler
+ * determines the reason the channel halted and proceeds accordingly.
+ */
+static void handle_hc_chhltd_intr_dma(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ union hcint_data hcint;
+ union hcintmsk_data hcintmsk;
+
+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+ hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+ /*
+ * Just release the channel. A dequeue can happen on a
+ * transfer timeout. In the case of an AHB Error, the channel
+ * was forced to halt because there's no way to gracefully
+ * recover.
+ */
+ release_channel(hcd, hc, qtd, hc->halt_status, must_free);
+ return;
+ }
+
+ /* Read the HCINTn register to determine the cause for the halt. */
+ hcint.d32 = dwc_read_reg32(®s->hcint);
+ hcintmsk.d32 = dwc_read_reg32(®s->hcintmsk);
+ if (hcint.b.xfercomp) {
+ /*
+ * This is here because of a possible hardware bug. Spec
+ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
+ * interrupt w/ACK bit set should occur, but I only see the
+ * XFERCOMP bit, even with it masked out. This is a workaround
+ * for that behavior. Should fix this when hardware is fixed.
+ */
+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)
+ handle_hc_ack_intr(hcd, hc, regs, qtd, must_free);
+
+ handle_hc_xfercomp_intr(hcd, hc, regs, qtd, must_free);
+ } else if (hcint.b.stall) {
+ handle_hc_stall_intr(hcd, hc, regs, qtd, must_free);
+ } else if (hcint.b.xacterr) {
+ /*
+ * Must handle xacterr before nak or ack. Could get a xacterr
+ * at the same time as either of these on a BULK/CONTROL OUT
+ * that started with a PING. The xacterr takes precedence.
+ */
+ handle_hc_xacterr_intr(hcd, hc, regs, qtd, must_free);
+ } else if (hcint.b.nyet) {
+ /*
+ * Must handle nyet before nak or ack. Could get a nyet at the
+ * same time as either of those on a BULK/CONTROL OUT that
+ * started with a PING. The nyet takes precedence.
+ */
+ handle_hc_nyet_intr(hcd, hc, regs, qtd, must_free);
+ } else if (hcint.b.bblerr) {
+ handle_hc_babble_intr(hcd, hc, regs, qtd, must_free);
+ } else if (hcint.b.frmovrun) {
+ handle_hc_frmovrun_intr(hcd, hc, regs, qtd, must_free);
+ } else if (hcint.b.datatglerr) {
+ handle_hc_datatglerr_intr(hcd, hc, regs, qtd);
+ hc->qh->data_toggle = 0;
+ halt_channel(hcd, hc, qtd, hc->halt_status, must_free);
+ } else if (hcint.b.nak && !hcintmsk.b.nak) {
+ /*
+ * If nak is not masked, it's because a non-split IN transfer
+ * is in an error state. In that case, the nak is handled by
+ * the nak interrupt handler, not here. Handle nak here for
+ * BULK/CONTROL OUT transfers, which halt on a NAK to allow
+ * rewinding the buffer pointer.
+ */
+ handle_hc_nak_intr(hcd, hc, regs, qtd, must_free);
+ } else if (hcint.b.ack && !hcintmsk.b.ack) {
+ /*
+ * If ack is not masked, it's because a non-split IN transfer
+ * is in an error state. In that case, the ack is handled by
+ * the ack interrupt handler, not here. Handle ack here for
+ * split transfers. Start splits halt on ACK.
+ */
+ handle_hc_ack_intr(hcd, hc, regs, qtd, must_free);
+ } else {
+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+ /*
+ * A periodic transfer halted with no other channel
+ * interrupts set. Assume it was halted by the core
+ * because it could not be completed in its scheduled
+ * (micro)frame.
+ */
+ halt_channel(hcd, hc, qtd,
+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
+ must_free);
+ } else {
+ printk(KERN_ERR "%s: Channel %d, DMA Mode -- ChHltd "
+ "set, but reason for halting is unknown, "
+ "hcint 0x%08x, intsts 0x%08x\n",
+ __func__, hc->hc_num, hcint.d32,
+ dwc_read_reg32(gintsts_reg(hcd)));
+ }
+ }
+}
+
+/**
+ * Handles a host channel Channel Halted interrupt.
+ *
+ * In slave mode, this handler is called only when the driver specifically
+ * requests a halt. This occurs during handling other host channel interrupts
+ * (e.g. nak, xacterr, stall, nyet, etc.).
+ *
+ * In DMA mode, this is the interrupt that occurs when the core has finished
+ * processing a transfer on a channel. Other host channel interrupts (except
+ * ahberr) are disabled in DMA mode.
+ */
+static int handle_hc_chhltd_intr(struct dwc_hcd *hcd, struct dwc_hc *hc,
+ struct dwc_hc_regs *regs, struct dwc_qtd *qtd, int *must_free)
+{
+ if (hcd->core_if->dma_enable)
+ handle_hc_chhltd_intr_dma(hcd, hc, regs, qtd, must_free);
+ else
+ release_channel(hcd, hc, qtd, hc->halt_status, must_free);
+
+ return 1;
+}
+
+/* Handles interrupt for a specific Host Channel */
+static int dwc_otg_hcd_handle_hc_n_intr(struct dwc_hcd *hcd, u32 num)
+{
+ int must_free = 0;
+ int retval = 0;
+ union hcint_data hcint;
+ union hcintmsk_data hcintmsk;
+ struct dwc_hc *hc;
+ struct dwc_hc_regs *hc_regs;
+ struct dwc_qtd *qtd;
+
+ hc = hcd->hc_ptr_array[num];
+ hc_regs = hcd->core_if->host_if->hc_regs[num];
+ qtd = list_entry(hc->qh->qtd_list.next, struct dwc_qtd, qtd_list_entry);
+
+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
+
+ hcint.d32 = hcint.d32 & hcintmsk.d32;
+ if (!hcd->core_if->dma_enable && hcint.b.chhltd && hcint.d32 != 0x2)
+ hcint.b.chhltd = 0;
+
+ if (hcint.b.xfercomp) {
+ retval |= handle_hc_xfercomp_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ /*
+ * If NYET occurred at same time as Xfer Complete, the NYET is
+ * handled by the Xfer Complete interrupt handler. Don't want
+ * to call the NYET interrupt handler in this case.
+ */
+ hcint.b.nyet = 0;
+ }
+
+ if (hcint.b.chhltd)
+ retval |= handle_hc_chhltd_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ if (hcint.b.ahberr)
+ retval |= handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
+ if (hcint.b.stall)
+ retval |= handle_hc_stall_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ if (hcint.b.nak)
+ retval |= handle_hc_nak_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ if (hcint.b.ack)
+ retval |= handle_hc_ack_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ if (hcint.b.nyet)
+ retval |= handle_hc_nyet_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ if (hcint.b.xacterr)
+ retval |= handle_hc_xacterr_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ if (hcint.b.bblerr)
+ retval |= handle_hc_babble_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ if (hcint.b.frmovrun)
+ retval |= handle_hc_frmovrun_intr(hcd, hc, hc_regs,
+ qtd, &must_free);
+ if (hcint.b.datatglerr)
+ retval |= handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
+
+ if (must_free)
+ /* Free the qtd here now that we are done using it. */
+ dwc_otg_hcd_qtd_free(qtd);
+ return retval;
+}
+
+/**
+ * This function returns the Host All Channel Interrupt register
+ */
+static inline u32 dwc_otg_read_host_all_channels_intr(struct core_if
+ *core_if)
+{
+ return dwc_read_reg32(&core_if->host_if->host_global_regs->haint);
+}
+
+/**
+ * This interrupt indicates that one or more host channels has a pending
+ * interrupt. There are multiple conditions that can cause each host channel
+ * interrupt. This function determines which conditions have occurred for each
+ * host channel interrupt and handles them appropriately.
+ */
+static int dwc_otg_hcd_handle_hc_intr(struct dwc_hcd *hcd)
+{
+ u32 i;
+ int retval = 0;
+ union haint_data haint;
+
+ /*
+ * Clear appropriate bits in HCINTn to clear the interrupt bit in
+ * GINTSTS
+ */
+ haint.d32 = dwc_otg_read_host_all_channels_intr(hcd->core_if);
+ for (i = 0; i < hcd->core_if->core_params->host_channels; i++)
+ if (haint.b2.chint & (1 << i))
+ retval |= dwc_otg_hcd_handle_hc_n_intr(hcd, i);
+
+ return retval;
+}
+
+/* This function handles interrupts for the HCD.*/
+int dwc_otg_hcd_handle_intr(struct dwc_hcd *hcd)
+{
+ int ret = 0;
+ struct core_if *core_if = hcd->core_if;
+ union gintsts_data gintsts;
+
+ /* Check if HOST Mode */
+ if (dwc_otg_is_host_mode(core_if)) {
+ spin_lock(&hcd->lock);
+ gintsts.d32 = dwc_otg_read_core_intr(core_if);
+ if (!gintsts.d32) {
+ spin_unlock(&hcd->lock);
+ return IRQ_NONE;
+ }
+
+ if (gintsts.b.sofintr)
+ ret |= dwc_otg_hcd_handle_sof_intr(hcd);
+ if (gintsts.b.rxstsqlvl)
+ ret |= dwc_otg_hcd_handle_rx_status_q_level_intr(hcd);
+ if (gintsts.b.nptxfempty)
+ ret |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(hcd);
+ if (gintsts.b.portintr)
+ ret |= dwc_otg_hcd_handle_port_intr(hcd);
+ if (gintsts.b.hcintr)
+ ret |= dwc_otg_hcd_handle_hc_intr(hcd);
+ if (gintsts.b.ptxfempty)
+ ret |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(hcd);
+
+ spin_unlock(&hcd->lock);
+ }
+ return ret;
+}
--
1.7.3
^ permalink raw reply related
* [PATCH V5 2/9] Add Synopsys DesignWare HS USB OTG driver framework.
From: Fushen Chen @ 2010-10-21 0:42 UTC (permalink / raw)
To: linux-usb; +Cc: linuxppc-dev, gregkh, Mark Miesfeld, Fushen Chen
In-Reply-To: <1287621773567-git-send-email-fchen@apm.com>
Platform probing is in dwc_otg_apmppc.c.
Driver parameter and parameter checking are in dwc_otg_param.c.
Signed-off-by: Fushen Chen <fchen@apm.com>
Signed-off-by: Mark Miesfeld <mmiesfeld@apm.com>
---
drivers/usb/dwc_otg/dwc_otg_apmppc.c | 394 ++++++++++++++++++
drivers/usb/dwc_otg/dwc_otg_driver.h | 78 ++++
drivers/usb/dwc_otg/dwc_otg_param.c | 730 ++++++++++++++++++++++++++++++++++
3 files changed, 1202 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/dwc_otg_apmppc.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h
create mode 100644 drivers/usb/dwc_otg/dwc_otg_param.c
diff --git a/drivers/usb/dwc_otg/dwc_otg_apmppc.c b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
new file mode 100644
index 0000000..a5c75c4
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_apmppc.c
@@ -0,0 +1,394 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld <mmiesfeld@apm.com>
+ * Modified by Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * The dwc_otg module provides the initialization and cleanup entry
+ * points for the dwcotg driver. This module will be dynamically installed
+ * after Linux is booted using the insmod command. When the module is
+ * installed, the dwc_otg_driver_init function is called. When the module is
+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
+ *
+ * This module also defines a data structure for the dwc_otg driver, which is
+ * used in conjunction with the standard device structure. These
+ * structures allow the OTG driver to comply with the standard Linux driver
+ * model in which devices and drivers are registered with a bus driver. This
+ * has the benefit that Linux can expose attributes of the driver and device
+ * in its special sysfs file system. Users can then read or write files in
+ * this file system to perform diagnostics on the driver components or the
+ * device.
+ */
+
+#include <linux/of_platform.h>
+
+#include "dwc_otg_driver.h"
+
+#define DWC_DRIVER_VERSION "1.05"
+#define DWC_DRIVER_DESC "HS OTG USB Controller driver"
+static const char dwc_driver_name[] = "dwc_otg";
+
+/**
+ * This function is the top level interrupt handler for the Common
+ * (Device and host modes) interrupts.
+ */
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval = IRQ_NONE;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev->core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the interrupt handler for the OverCurrent condition
+ * from the external charge pump (if enabled)
+ */
+static irqreturn_t dwc_otg_externalchgpump_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+
+ if (dwc_otg_is_host_mode(dwc_dev->core_if)) {
+ struct dwc_hcd *dwc_hcd;
+ union hprt0_data hprt0 = {.d32 = 0};
+
+ dwc_hcd = dwc_dev->hcd;
+ spin_lock(&dwc_hcd->lock);
+ dwc_hcd->flags.b.port_over_current_change = 1;
+
+ hprt0.b.prtpwr = 0;
+ dwc_write_reg32(dwc_dev->core_if->host_if->hprt0,
+ hprt0.d32);
+ spin_unlock(&dwc_hcd->lock);
+ } else {
+ /* Device mode - This int is n/a for device mode */
+ printk(KERN_ERR "DeviceMode: OTG OverCurrent Detected\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * This function is called when a device is unregistered with the
+ * dwc_otg_driver. This happens, for example, when the rmmod command is
+ * executed. The device may or may not be electrically present. If it is
+ * present, the driver stops device processing. Any resources used on behalf
+ * of this device are freed.
+ */
+static int __devexit dwc_otg_driver_remove(struct platform_device *ofdev)
+{
+ struct device *dev = &ofdev->dev;
+ struct dwc_otg_device *dwc_dev = dev_get_drvdata(dev);
+
+ /* Memory allocation for dwc_otg_device may have failed. */
+ if (!dwc_dev)
+ return 0;
+
+ usb_nop_xceiv_unregister();
+
+ /* Free the IRQ */
+ if (dwc_dev->common_irq_installed)
+ free_irq(dwc_dev->irq, dwc_dev);
+
+ if (!dwc_has_feature(dwc_dev->core_if, DWC_DEVICE_ONLY))
+ if (dwc_dev->hcd)
+ dwc_otg_hcd_remove(dev);
+
+ if (!dwc_has_feature(dwc_dev->core_if, DWC_HOST_ONLY))
+ if (dwc_dev->pcd)
+ dwc_otg_pcd_remove(dev);
+
+ if (dwc_dev->core_if)
+ dwc_otg_cil_remove(dwc_dev->core_if);
+
+ /* Return the memory. */
+ if (dwc_dev->base)
+ iounmap(dwc_dev->base);
+ if (dwc_dev->phys_addr)
+ release_mem_region(dwc_dev->phys_addr, dwc_dev->base_len);
+ kfree(dwc_dev);
+
+ /* Clear the drvdata pointer. */
+ dev_set_drvdata(dev, 0);
+ return 0;
+}
+
+/**
+ * This function is called when an device is bound to a
+ * dwc_otg_driver. It creates the driver components required to
+ * control the device (CIL, HCD, and PCD) and it initializes the
+ * device. The driver components are stored in a dwc_otg_device
+ * structure. A reference to the dwc_otg_device is saved in the
+ * device. This allows the driver to access the dwc_otg_device
+ * structure on subsequent calls to driver methods for this device.
+ */
+static int __devinit dwc_otg_driver_probe(struct platform_device *ofdev,
+ const struct of_device_id *match)
+{
+ int retval = 0;
+ struct dwc_otg_device *dwc_dev;
+ struct device *dev = &ofdev->dev;
+ struct resource res;
+ u32 *gusbcfg_addr;
+ union gusbcfg_data usbcfg = {.d32 = 0};
+ u32 cp_irq;
+
+ dev_dbg(dev, "dwc_otg_driver_probe(%p)\n", dev);
+
+ dwc_dev = kzalloc(sizeof(*dwc_dev), GFP_KERNEL);
+ if (!dwc_dev) {
+ dev_err(dev, "kmalloc of dwc_otg_device failed\n");
+ retval = -ENOMEM;
+ goto fail;
+ }
+
+ /* Retrieve the memory and IRQ resources. */
+ dwc_dev->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
+ if (dwc_dev->irq == NO_IRQ) {
+ dev_err(dev, "no device irq\n");
+ retval = -ENODEV;
+ goto fail;
+ }
+ dev_dbg(dev, "OTG - device irq: %d\n", dwc_dev->irq);
+
+ if (of_address_to_resource(ofdev->dev.of_node, 0, &res)) {
+ printk(KERN_ERR "%s: Can't get USB-OTG register address\n",
+ __func__);
+ retval = -ENOMEM;
+ goto fail;
+ }
+ dev_dbg(dev, "OTG - ioresource_mem start0x%08x: end:0x%08x\n",
+ (u32)res.start, (u32)res.end);
+
+ dwc_dev->phys_addr = res.start;
+ dwc_dev->base_len = res.end - res.start + 1;
+ if (!request_mem_region(dwc_dev->phys_addr,
+ dwc_dev->base_len,
+ dwc_driver_name)) {
+ dev_err(dev, "request_mem_region failed\n");
+ retval = -EBUSY;
+ goto fail;
+ }
+
+ /* Map the DWC_otg Core memory into virtual address space. */
+ dwc_dev->base = ioremap(dwc_dev->phys_addr,
+ dwc_dev->base_len);
+ if (!dwc_dev->base) {
+ dev_err(dev, "ioremap() failed\n");
+ retval = -ENOMEM;
+ goto fail;
+ }
+ dev_dbg(dev, "mapped base=0x%08x\n", (unsigned)dwc_dev->base);
+
+ /*
+ * Initialize driver data to point to the global DWC_otg
+ * Device structure.
+ */
+ dev_set_drvdata(dev, dwc_dev);
+
+ dev_dbg(dev, "dwc_dev=0x%p\n", dwc_dev);
+ dwc_dev->core_if =
+ dwc_otg_cil_init(dwc_dev->base, &dwc_otg_module_params);
+ if (!dwc_dev->core_if) {
+ dev_err(dev, "CIL initialization failed!\n");
+ retval = -ENOMEM;
+ goto fail;
+ }
+ usb_nop_xceiv_register();
+ dwc_dev->core_if->xceiv = otg_get_transceiver();
+ if (!dwc_dev->core_if->xceiv) {
+ retval = -ENODEV;
+ goto fail;
+ }
+ dwc_set_feature(dwc_dev->core_if);
+
+ gusbcfg_addr = &dwc_dev->core_if->core_global_regs->gusbcfg;
+
+ /*
+ * Validate parameter values.
+ */
+ if (check_parameters(dwc_dev->core_if)) {
+ retval = -EINVAL;
+ goto fail;
+ }
+
+ /* Added for PLB DMA phys virt mapping */
+ dwc_dev->core_if->phys_addr = dwc_dev->phys_addr;
+
+ /*
+ * Disable the global interrupt until all the interrupt
+ * handlers are installed.
+ */
+ dwc_otg_disable_global_interrupts(dwc_dev->core_if);
+
+ /*
+ * Install the interrupt handler for the common interrupts before
+ * enabling common interrupts in core_init below.
+ */
+ retval = request_irq(dwc_dev->irq, dwc_otg_common_irq,
+ IRQF_SHARED, "dwc_otg", dwc_dev);
+ if (retval) {
+ printk(KERN_ERR "request of irq%d failed retval: %d\n",
+ dwc_dev->irq, retval);
+ retval = -EBUSY;
+ goto fail;
+ } else {
+ dwc_dev->common_irq_installed = 1;
+ }
+
+ /* Initialize the DWC_otg core. */
+ dwc_otg_core_init(dwc_dev->core_if);
+
+ /* configure chargepump interrupt */
+ cp_irq = irq_of_parse_and_map(ofdev->dev.of_node, 3);
+ if (cp_irq) {
+ retval = request_irq(cp_irq, dwc_otg_externalchgpump_irq,
+ IRQF_SHARED, "dwc_otg_ext_chg_pump", dwc_dev);
+ if (retval) {
+ printk(KERN_ERR "request of irq failed retval: %d\n",
+ retval);
+ retval = -EBUSY;
+ goto fail;
+ } else {
+ printk(KERN_INFO "%s: ExtChgPump Detection "
+ "IRQ registered\n", dwc_driver_name);
+ }
+ }
+
+ if (!dwc_has_feature(dwc_dev->core_if, DWC_HOST_ONLY)) {
+ /* Initialize the PCD */
+ retval = dwc_otg_pcd_init(dev);
+ if (retval) {
+ printk(KERN_ERR "dwc_otg_pcd_init failed\n");
+ dwc_dev->pcd = NULL;
+ goto fail;
+ }
+ }
+
+ if (!dwc_has_feature(dwc_dev->core_if, DWC_DEVICE_ONLY)) {
+ /* Initialize the HCD and force_host_mode */
+ usbcfg.d32 = dwc_read_reg32(gusbcfg_addr);
+ usbcfg.b.force_host_mode = 1;
+ dwc_write_reg32(gusbcfg_addr, usbcfg.d32);
+
+ retval = dwc_otg_hcd_init(dev, dwc_dev);
+ if (retval) {
+ printk(KERN_ERR "dwc_otg_hcd_init failed\n");
+ dwc_dev->hcd = NULL;
+ goto fail;
+ }
+ }
+ /*
+ * Enable the global interrupt after all the interrupt
+ * handlers are installed.
+ */
+ dwc_otg_enable_global_interrupts(dwc_dev->core_if);
+
+ usbcfg.d32 = dwc_read_reg32(gusbcfg_addr);
+ usbcfg.b.force_host_mode = 0;
+ dwc_write_reg32(gusbcfg_addr, usbcfg.d32);
+
+ return 0;
+
+fail:
+ dwc_otg_driver_remove(ofdev);
+ return retval;
+}
+
+/*
+ * This structure defines the methods to be called by a bus driver
+ * during the lifecycle of a device on that bus. Both drivers and
+ * devices are registered with a bus driver. The bus driver matches
+ * devices to drivers based on information in the device and driver
+ * structures.
+ *
+ * The probe function is called when the bus driver matches a device
+ * to this driver. The remove function is called when a device is
+ * unregistered with the bus driver.
+ */
+static const struct of_device_id dwc_otg_match[] = {
+ { .compatible = "amcc,dwc-otg", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, dwc_otg_match);
+
+static struct of_platform_driver dwc_otg_driver = {
+ .probe = dwc_otg_driver_probe,
+ .remove = __devexit_p(dwc_otg_driver_remove),
+ .driver = {
+ .name = "dwc_otg",
+ .owner = THIS_MODULE,
+ .of_match_table = dwc_otg_match,
+ },
+};
+
+/**
+ * This function is called when the dwc_otg_driver is installed with the
+ * insmod command. It registers the dwc_otg_driver structure with the
+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function
+ * to be called. In addition, the bus driver will automatically expose
+ * attributes defined for the device and driver in the special sysfs file
+ * system.
+ */
+static int __init dwc_otg_driver_init(void)
+{
+ int retval = 0;
+
+ printk(KERN_INFO "%s: version %s\n", dwc_driver_name,
+ DWC_DRIVER_VERSION);
+ retval = of_register_platform_driver(&dwc_otg_driver);
+ if (retval < 0)
+ printk(KERN_ERR "%s registration failed. retval=%d\n",
+ dwc_driver_name, retval);
+ return retval;
+}
+module_init(dwc_otg_driver_init);
+
+/**
+ * This function is called when the driver is removed from the kernel
+ * with the rmmod command. The driver unregisters itself with its bus
+ * driver.
+ *
+ */
+static void __exit dwc_otg_driver_cleanup(void)
+{
+ of_unregister_platform_driver(&dwc_otg_driver);
+ printk(KERN_INFO "%s module removed\n", dwc_driver_name);
+}
+module_exit(dwc_otg_driver_cleanup);
+
+MODULE_DESCRIPTION(DWC_DRIVER_DESC);
+MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@apm.com");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.h b/drivers/usb/dwc_otg/dwc_otg_driver.h
new file mode 100644
index 0000000..b38f613
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_driver.h
@@ -0,0 +1,78 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld <mmiesfeld@apm.com>
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if !defined(__DWC_OTG_DRIVER_H__)
+#define __DWC_OTG_DRIVER_H__
+
+/*
+ * This file contains the interface to the Linux driver.
+ */
+#include "dwc_otg_cil.h"
+
+/*
+ * This structure is a wrapper that encapsulates the driver components used to
+ * manage a single DWC_otg controller.
+ */
+struct dwc_otg_device {
+ /* Base address returned from ioremap() */
+ void *base;
+
+ /* Pointer to the core interface structure. */
+ struct core_if *core_if;
+
+ /* Pointer to the PCD structure. */
+ struct dwc_pcd *pcd;
+
+ /* Pointer to the HCD structure. */
+ struct dwc_hcd *hcd;
+
+ /* Flag to indicate whether the common IRQ handler is installed. */
+ u8 common_irq_installed;
+
+ /* Interrupt request number. */
+ unsigned int irq;
+
+ /*
+ * Physical address of Control and Status registers, used by
+ * release_mem_region().
+ */
+ resource_size_t phys_addr;
+
+ /* Length of memory region, used by release_mem_region(). */
+ unsigned long base_len;
+};
+extern struct core_params dwc_otg_module_params;
+extern int __devinit check_parameters(struct core_if *core_if);
+#endif
diff --git a/drivers/usb/dwc_otg/dwc_otg_param.c b/drivers/usb/dwc_otg/dwc_otg_param.c
new file mode 100644
index 0000000..ee67d87a
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_param.c
@@ -0,0 +1,730 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld <mmiesfeld@apm.com>
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file provides dwc_otg driver parameter and parameter checking.
+ */
+
+#include "dwc_otg_cil.h"
+
+/* Global Debug Level Mask. */
+static u32 g_dbg_lvl = 0x0; /* OFF */
+
+/*
+ * Encapsulate the module parameter settings
+ */
+struct core_params dwc_otg_module_params = {
+ .opt = -1,
+ .otg_cap = -1,
+ .dma_enable = -1,
+ .dma_burst_size = -1,
+ .speed = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1,
+ .enable_dynamic_fifo = -1,
+ .data_fifo_size = -1,
+ .dev_rx_fifo_size = -1,
+ .dev_nperio_tx_fifo_size = -1,
+ .dev_perio_tx_fifo_size = {
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+ }, /* 15 */
+ .host_rx_fifo_size = -1,
+ .host_nperio_tx_fifo_size = -1,
+ .host_perio_tx_fifo_size = -1,
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
+ .host_channels = -1,
+ .dev_endpoints = -1,
+ .phy_type = -1,
+ .phy_utmi_width = -1,
+ .phy_ulpi_ddr = -1,
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .ts_dline = -1,
+ .en_multiple_tx_fifo = -1,
+ .dev_tx_fifo_size = {
+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
+ }, /* 15 */
+ .thr_ctl = -1,
+ .tx_thr_length = -1,
+ .rx_thr_length = -1,
+};
+
+/**
+ * Determines if the OTG capability parameter is valid under the current
+ * hardware configuration.
+ */
+static int is_valid_otg_cap(struct core_if *core_if)
+{
+ int valid = 1;
+
+ switch (dwc_otg_module_params.otg_cap) {
+ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
+ if (core_if->hwcfg2.b.op_mode !=
+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+ valid = 0;
+ break;
+ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
+ if (core_if->hwcfg2.b.op_mode !=
+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG &&
+ core_if->hwcfg2.b.op_mode !=
+ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG &&
+ core_if->hwcfg2.b.op_mode !=
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE &&
+ core_if->hwcfg2.b.op_mode !=
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
+ valid = 0;
+ break;
+ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
+ /* always valid */
+ break;
+ }
+ return valid;
+}
+
+/**
+ * Returns a valid OTG capability setting for the current hardware
+ * configuration.
+ */
+static int get_valid_otg_cap(struct core_if *core_if)
+{
+ if (core_if->hwcfg2.b.op_mode ==
+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG ||
+ core_if->hwcfg2.b.op_mode ==
+ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG ||
+ core_if->hwcfg2.b.op_mode ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
+ core_if->hwcfg2.b.op_mode ==
+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
+ return DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE;
+ else
+ return DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+}
+
+/**
+ * Checks that, if the user set a periodic Tx FIFO size parameter, the size is
+ * within the valid range. If not, the parameter is set to the default.
+ */
+static int chk_param_perio_tx_fifo_sizes(int retval)
+{
+ u32 *s = &dwc_otg_module_params.dev_perio_tx_fifo_size[0];
+ u32 i;
+
+ for (i = 0; i < MAX_PERIO_FIFOS; i++, s++) {
+ if (*s != -1 && (*s < 4 || *s > 768)) {
+ printk(KERN_ERR "`%d' invalid for parameter "
+ "`dev_perio_tx_fifo_size_%d'\n", *s, i);
+
+ *s = dwc_param_dev_perio_tx_fifo_size_default;
+ retval++;
+ }
+ }
+ return retval;
+}
+
+/**
+ * Checks that, if the user set a Tx FIFO size parameter, the size is within the
+ * valid range. If not, the parameter is set to the default.
+ */
+static int chk_param_tx_fifo_sizes(int retval)
+{
+ u32 *s = &dwc_otg_module_params.dev_tx_fifo_size[0];
+ u32 i;
+
+ for (i = 0; i < MAX_TX_FIFOS; i++, s++) {
+ if (*s != -1 && (*s < 4 || *s > 768)) {
+ printk(KERN_ERR "`%d' invalid for parameter "
+ "`dev_perio_tx_fifo_size_%d'\n", *s, i);
+
+ *s = dwc_param_dev_tx_fifo_size_default;
+ retval++;
+ }
+ }
+ return retval;
+}
+
+/**
+ * Checks that parameter settings for the periodic Tx FIFO sizes are correct
+ * according to the hardware configuration. Sets the size to the hardware
+ * configuration if an incorrect size is detected.
+ */
+static int chk_valid_perio_tx_fifo_sizes(struct core_if *core_if, int retval)
+{
+ struct core_global_regs *regs = core_if->core_global_regs;
+ u32 *param_size = &dwc_otg_module_params.dev_perio_tx_fifo_size[0];
+ u32 i;
+
+ for (i = 0; i < MAX_PERIO_FIFOS; i++, param_size++) {
+ int changed = 1;
+ int error = 0;
+ u32 size;
+
+ if (*param_size == -1) {
+ changed = 0;
+ *param_size = dwc_param_dev_perio_tx_fifo_size_default;
+ }
+
+ size = dwc_read_reg32(®s->dptxfsiz_dieptxf[i]);
+ if (*param_size > size) {
+ if (changed) {
+ printk(KERN_ERR "%d' invalid for parameter "
+ "`dev_perio_tx_fifo_size_%d'. Check HW "
+ "configuration.\n", *param_size, i);
+ error = 1;
+ }
+ *param_size = size;
+ }
+ retval += error;
+ }
+ return retval;
+}
+
+/**
+ * Checks that parameter settings for the Tx FIFO sizes are correct according to
+ * the hardware configuration. Sets the size to the hardware configuration if
+ * an incorrect size is detected.
+ */
+static int chk_valid_tx_fifo_sizes(struct core_if *core_if, int retval)
+{
+ struct core_global_regs *regs = core_if->core_global_regs;
+ u32 *param_size = &dwc_otg_module_params.dev_tx_fifo_size[0];
+ u32 i;
+
+ for (i = 0; i < MAX_TX_FIFOS; i++, param_size) {
+ int changed = 1;
+ int error = 0;
+ u32 size;
+
+ if (*param_size == -1) {
+ changed = 0;
+ *param_size = dwc_param_dev_tx_fifo_size_default;
+ }
+
+ size = dwc_read_reg32(®s->dptxfsiz_dieptxf[i]);
+ if (*param_size > size) {
+ if (changed) {
+ printk(KERN_ERR "%d' invalid for parameter "
+ "`dev_tx_fifo_size_%d'. Check HW "
+ "configuration.\n", *param_size, i);
+ error = 1;
+ }
+ *param_size = size;
+ }
+ retval += error;
+ }
+ return retval;
+}
+
+/**
+ * This function is called during module intialization to verify that
+ * the module parameters are in a valid state.
+ */
+int __devinit check_parameters(struct core_if *core_if)
+{
+ int retval = 0;
+
+ /* Checks if the parameter is outside of its valid range of values */
+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
+ ((dwc_otg_module_params._param_ < (_low_)) || \
+ (dwc_otg_module_params._param_ > (_high_)))
+
+ /*
+ * If the parameter has been set by the user, check that the parameter
+ * value is within the value range of values. If not, report a module
+ * error.
+ */
+#define DWC_OTG_PARAM_ERR(_param_, _low_, _high_, _string_) \
+ do { \
+ if (dwc_otg_module_params._param_ != -1) { \
+ if (DWC_OTG_PARAM_TEST(_param_, (_low_), (_high_))) { \
+ printk(KERN_ERR "`%d' invalid for parameter " \
+ "`%s'\n", \
+ dwc_otg_module_params._param_, \
+ _string_); \
+ dwc_otg_module_params._param_ = \
+ dwc_param_##_param_##_default; \
+ retval++; \
+ } \
+ } \
+ } while (0)
+
+ DWC_OTG_PARAM_ERR(opt, 0, 1, "opt");
+ DWC_OTG_PARAM_ERR(otg_cap, 0, 2, "otg_cap");
+ DWC_OTG_PARAM_ERR(dma_enable, 0, 1, "dma_enable");
+ DWC_OTG_PARAM_ERR(speed, 0, 1, "speed");
+
+ DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power, 0, 1,
+ "host_support_fs_ls_low_power");
+ DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk, 0, 1,
+ "host_ls_low_power_phy_clk");
+
+ DWC_OTG_PARAM_ERR(enable_dynamic_fifo, 0, 1, "enable_dynamic_fifo");
+ DWC_OTG_PARAM_ERR(data_fifo_size, 32, 32768, "data_fifo_size");
+ DWC_OTG_PARAM_ERR(dev_rx_fifo_size, 16, 32768, "dev_rx_fifo_size");
+ DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size, 16, 32768,
+ "dev_nperio_tx_fifo_size");
+ DWC_OTG_PARAM_ERR(host_rx_fifo_size, 16, 32768, "host_rx_fifo_size");
+ DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size, 16, 32768,
+ "host_nperio_tx_fifo_size");
+ DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size, 16, 32768,
+ "host_perio_tx_fifo_size");
+
+ DWC_OTG_PARAM_ERR(max_transfer_size, 2047, 524288,
+ "max_transfer_size");
+ DWC_OTG_PARAM_ERR(max_packet_count, 15, 511, "max_packet_count");
+
+ DWC_OTG_PARAM_ERR(host_channels, 1, 16, "host_channels");
+ DWC_OTG_PARAM_ERR(dev_endpoints, 1, 15, "dev_endpoints");
+
+ DWC_OTG_PARAM_ERR(phy_type, 0, 2, "phy_type");
+ DWC_OTG_PARAM_ERR(phy_ulpi_ddr, 0, 1, "phy_ulpi_ddr");
+ DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus, 0, 1, "phy_ulpi_ext_vbus");
+ DWC_OTG_PARAM_ERR(i2c_enable, 0, 1, "i2c_enable");
+ DWC_OTG_PARAM_ERR(ulpi_fs_ls, 0, 1, "ulpi_fs_ls");
+ DWC_OTG_PARAM_ERR(ts_dline, 0, 1, "ts_dline");
+
+ if (dwc_otg_module_params.dma_burst_size != -1) {
+ if (DWC_OTG_PARAM_TEST(dma_burst_size, 1, 1) &&
+ DWC_OTG_PARAM_TEST(dma_burst_size, 4, 4) &&
+ DWC_OTG_PARAM_TEST(dma_burst_size, 8, 8) &&
+ DWC_OTG_PARAM_TEST(dma_burst_size, 16, 16) &&
+ DWC_OTG_PARAM_TEST(dma_burst_size, 32, 32) &&
+ DWC_OTG_PARAM_TEST(dma_burst_size, 64, 64) &&
+ DWC_OTG_PARAM_TEST(dma_burst_size, 128, 128) &&
+ DWC_OTG_PARAM_TEST(dma_burst_size, 256, 256)) {
+ printk(KERN_ERR "`%d' invalid for parameter "
+ "`dma_burst_size'\n",
+ dwc_otg_module_params.dma_burst_size);
+ dwc_otg_module_params.dma_burst_size = 32;
+ retval++;
+ }
+ }
+
+ if (dwc_otg_module_params.phy_utmi_width != -1) {
+ if (DWC_OTG_PARAM_TEST(phy_utmi_width, 8, 8) &&
+ DWC_OTG_PARAM_TEST(phy_utmi_width, 16, 16)) {
+ printk(KERN_ERR "`%d'invalid for parameter "
+ "`phy_utmi_width'\n",
+ dwc_otg_module_params.phy_utmi_width);
+ dwc_otg_module_params.phy_utmi_width = 8;
+ retval++;
+ }
+ }
+
+ DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo");
+ retval += chk_param_perio_tx_fifo_sizes(retval);
+ retval += chk_param_tx_fifo_sizes(retval);
+
+ DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
+ DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
+ DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
+
+ /*
+ * At this point, all module parameters that have been set by the user
+ * are valid, and those that have not are left unset. Now set their
+ * default values and/or check the parameters against the hardware
+ * configurations of the OTG core.
+ */
+
+ /*
+ * This sets the parameter to the default value if it has not been set
+ * by the user
+ */
+#define DWC_OTG_PARAM_SET_DEFAULT(_param_) ({ \
+ int changed = 1; \
+ if (dwc_otg_module_params._param_ == -1) { \
+ changed = 0; \
+ dwc_otg_module_params._param_ = \
+ dwc_param_##_param_##_default; \
+ } \
+ changed; \
+ })
+
+ /*
+ * This checks the macro against the hardware configuration to see if it
+ * is valid. It is possible that the default value could be invalid.
+ * In this case, it will report a module error if the user touched the
+ * parameter. Otherwise it will adjust the value without any error.
+ */
+#define DWC_OTG_PARAM_CHECK_VALID(_param_, _str_, _is_valid_ , _set_valid_) ({ \
+ int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
+ int error = 0; \
+ if (!(_is_valid_)) { \
+ if (changed) { \
+ printk(KERN_ERR "`%d' invalid for parameter " \
+ "`%s' Check HW configuration.\n", \
+ dwc_otg_module_params._param_, \
+ _str_); \
+ error = 1; \
+ } \
+ dwc_otg_module_params._param_ = (_set_valid_); \
+ } \
+ error; \
+ })
+
+ /* OTG Cap */
+ retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap, "otg_cap",
+ is_valid_otg_cap(core_if), get_valid_otg_cap(core_if));
+
+ retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable, "dma_enable",
+ ((dwc_otg_module_params.dma_enable == 1) &&
+ (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1, 0);
+ retval += DWC_OTG_PARAM_CHECK_VALID(opt, "opt", 1, 0);
+ DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
+ retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
+ "host_support_fs_ls_low_power", 1, 0);
+ retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
+ "enable_dynamic_fifo",
+ ((dwc_otg_module_params.enable_dynamic_fifo == 0) ||
+ (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
+ retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size, "data_fifo_size",
+ (dwc_otg_module_params.data_fifo_size <=
+ core_if->hwcfg3.b.dfifo_depth),
+ core_if->hwcfg3.b.dfifo_depth);
+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
+ "dev_rx_fifo_size",
+ (dwc_otg_module_params.dev_rx_fifo_size <=
+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
+ "dev_nperio_tx_fifo_size",
+ (dwc_otg_module_params.dev_nperio_tx_fifo_size <=
+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz)
+ >> 16)),
+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz)
+ >> 16));
+ retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
+ "host_rx_fifo_size",
+ (dwc_otg_module_params.host_rx_fifo_size <=
+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
+ retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
+ "host_nperio_tx_fifo_size",
+ (dwc_otg_module_params.host_nperio_tx_fifo_size <=
+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz)
+ >> 16)),
+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz)
+ >> 16));
+ retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
+ "host_perio_tx_fifo_size",
+ (dwc_otg_module_params.host_perio_tx_fifo_size <=
+ ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz)
+ >> 16))),
+ ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz)
+ >> 16)));
+ retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
+ "max_transfer_size",
+ (dwc_otg_module_params.max_transfer_size <
+ (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
+ ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))
+ - 1));
+ retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
+ "max_packet_count",
+ (dwc_otg_module_params.max_packet_count <
+ (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))
+ - 1));
+ retval += DWC_OTG_PARAM_CHECK_VALID(host_channels, "host_channels",
+ (dwc_otg_module_params.host_channels <=
+ (core_if->hwcfg2.b.num_host_chan + 1)),
+ (core_if->hwcfg2.b.num_host_chan + 1));
+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints, "dev_endpoints",
+ (dwc_otg_module_params.dev_endpoints <=
+ (core_if->hwcfg2.b.num_dev_ep)),
+ core_if->hwcfg2.b.num_dev_ep);
+
+ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, "phy_type", 1, 0);
+ retval += DWC_OTG_PARAM_CHECK_VALID(speed, "speed",
+ (dwc_otg_module_params.speed == 0) &&
+ (dwc_otg_module_params.phy_type ==
+ DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
+ dwc_otg_module_params.phy_type ==
+ DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
+ retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
+ "host_ls_low_power_phy_clk",
+ ((dwc_otg_module_params.host_ls_low_power_phy_clk ==
+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) &&
+ (dwc_otg_module_params.phy_type ==
+ DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
+ ((dwc_otg_module_params.phy_type ==
+ DWC_PHY_TYPE_PARAM_FS) ?
+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
+
+ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
+ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
+ DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
+ DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
+ DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
+
+ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, "i2c_enable", 1, 0);
+
+ retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo,
+ "en_multiple_tx_fifo",
+ ((dwc_otg_module_params.en_multiple_tx_fifo == 1) &&
+ (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, 0);
+
+ retval += chk_valid_perio_tx_fifo_sizes(core_if, retval);
+ retval += chk_valid_tx_fifo_sizes(core_if, retval);
+
+ DWC_OTG_PARAM_SET_DEFAULT(thr_ctl);
+ DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
+ DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
+
+ return retval;
+}
+
+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
+module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
+MODULE_PARM_DESC(opt, "OPT Mode");
+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size,
+ int, 0444);
+MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, "
+ "128, 256");
+module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
+module_param_named(host_support_fs_ls_low_power,
+ dwc_otg_module_params.host_support_fs_ls_low_power,
+ int, 0444);
+MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS "
+ "0=Support 1=Don't Support");
+module_param_named(host_ls_low_power_phy_clk,
+ dwc_otg_module_params.host_ls_low_power_phy_clk,
+ int, 0444);
+MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock "
+ "0=48Mhz 1=6Mhz");
+module_param_named(enable_dynamic_fifo,
+ dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
+module_param_named(data_fifo_size,
+ dwc_otg_module_params.data_fifo_size, int, 0444);
+MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO "
+ "memory 32-32768");
+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
+ int, 0444);
+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
+module_param_named(dev_nperio_tx_fifo_size,
+ dwc_otg_module_params.dev_nperio_tx_fifo_size,
+ int, 0444);
+MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic "
+ "Tx FIFO 16-32768");
+module_param_named(dev_perio_tx_fifo_size_1,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[0],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_2,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[1],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_3,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[2],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_4,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[3],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_5,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[4],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_6,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[5],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_7,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[6],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_8,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[7],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_9,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[8],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_10,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[9],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_11,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[10],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_12,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[11],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_13,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[12],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_14,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[13],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(dev_perio_tx_fifo_size_15,
+ dwc_otg_module_params.dev_perio_tx_fifo_size[14],
+ int, 0444);
+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic "
+ "Tx FIFO 4-768");
+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
+ int, 0444);
+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
+module_param_named(host_nperio_tx_fifo_size,
+ dwc_otg_module_params.host_nperio_tx_fifo_size,
+ int, 0444);
+MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the "
+ "non-periodic Tx FIFO 16-32768");
+module_param_named(host_perio_tx_fifo_size,
+ dwc_otg_module_params.host_perio_tx_fifo_size,
+ int, 0444);
+MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host "
+ "periodic Tx FIFO 16-32768");
+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
+ int, 0444);
+
+MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in "
+ "bytes 2047-65535");
+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
+ int, 0444);
+MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a "
+ "transfer 15-511");
+module_param_named(host_channels, dwc_otg_module_params.host_channels,
+ int, 0444);
+MODULE_PARM_DESC(host_channels, "The number of host channel registers to "
+ "use 1-16");
+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints,
+ int, 0444);
+MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 "
+ "available for device mode 1-15");
+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width,
+ int, 0444);
+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr,
+ int, 0444);
+MODULE_PARM_DESC(phy_ulpi_ddr, "0");
+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
+ int, 0444);
+MODULE_PARM_DESC(phy_ulpi_ext_vbus,
+ "ULPI PHY using internal or external vbus 0=Internal");
+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
+module_param_named(debug, g_dbg_lvl, int, 0444);
+MODULE_PARM_DESC(debug, "0");
+module_param_named(en_multiple_tx_fifo,
+ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
+MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs "
+ "0=disabled 1=enabled");
+module_param_named(dev_tx_fifo_size_1,
+ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_2,
+ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_3,
+ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_4,
+ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_5,
+ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_6,
+ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_7,
+ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_8,
+ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_9,
+ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_10,
+ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_11,
+ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_12,
+ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_13,
+ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_14,
+ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
+module_param_named(dev_tx_fifo_size_15,
+ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
+MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., "
+ "1 - ISO Tx thr., 2 - Rx thr.- bit "
+ "0=disabled 1=enabled");
+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length,
+ int, 0444);
+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length,
+ int, 0444);
+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
--
1.7.3
^ permalink raw reply related
* [PATCH V5 6/9] Add Synopsys DesignWare HS USB OTG HCD queue function.
From: Fushen Chen @ 2010-10-21 0:42 UTC (permalink / raw)
To: linux-usb; +Cc: linuxppc-dev, gregkh, Mark Miesfeld, Fushen Chen
In-Reply-To: <12876217753881-git-send-email-fchen@apm.com>
Implements functions to manage Queue Heads and Queue
Transfer Descriptors of DWC USB OTG Controller.
Signed-off-by: Fushen Chen <fchen@apm.com>
Signed-off-by: Mark Miesfeld <mmiesfeld@apm.com>
---
drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 697 +++++++++++++++++++++++++++++++
1 files changed, 697 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
new file mode 100644
index 0000000..b1d67fe
--- /dev/null
+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
@@ -0,0 +1,697 @@
+/*
+ * DesignWare HS OTG controller driver
+ * Copyright (C) 2006 Synopsys, Inc.
+ * Portions Copyright (C) 2010 Applied Micro Circuits Corporation.
+ *
+ * This program is free software: you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License version 2 for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see http://www.gnu.org/licenses
+ * or write to the Free Software Foundation, Inc., 51 Franklin Street,
+ * Suite 500, Boston, MA 02110-1335 USA.
+ *
+ * Based on Synopsys driver version 2.60a
+ * Modified by Mark Miesfeld <mmiesfeld@apm.com>
+ * Modified by Stefan Roese <sr@denx.de>, DENX Software Engineering
+ * Modified by Chuck Meade <chuck@theptrgroup.com>
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL SYNOPSYS, INC. BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file contains the functions to manage Queue Heads and Queue
+ * Transfer Descriptors.
+ */
+
+#include "dwc_otg_hcd.h"
+
+static inline int is_fs_ls(enum usb_device_speed speed)
+{
+ return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
+}
+
+/* Allocates memory for a QH structure. */
+static inline struct dwc_qh *dwc_otg_hcd_qh_alloc(void)
+{
+ return kmalloc(sizeof(struct dwc_qh), GFP_ATOMIC);
+}
+
+/**
+ * Initializes a QH structure to initialize the QH.
+ */
+#define SCHEDULE_SLOP 10
+static void dwc_otg_hcd_qh_init(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ struct urb *urb)
+{
+ memset(qh, 0, sizeof(struct dwc_qh));
+
+ /* Initialize QH */
+ switch (usb_pipetype(urb->pipe)) {
+ case PIPE_CONTROL:
+ qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
+ break;
+ case PIPE_BULK:
+ qh->ep_type = USB_ENDPOINT_XFER_BULK;
+ break;
+ case PIPE_ISOCHRONOUS:
+ qh->ep_type = USB_ENDPOINT_XFER_ISOC;
+ break;
+ case PIPE_INTERRUPT:
+ qh->ep_type = USB_ENDPOINT_XFER_INT;
+ break;
+ }
+
+ qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
+ qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+ qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
+
+ INIT_LIST_HEAD(&qh->qtd_list);
+ INIT_LIST_HEAD(&qh->qh_list_entry);
+
+ qh->channel = NULL;
+ qh->speed = urb->dev->speed;
+
+ /*
+ * FS/LS Enpoint on HS Hub NOT virtual root hub
+ */
+ qh->do_split = 0;
+ if (is_fs_ls(urb->dev->speed) && urb->dev->tt && urb->dev->tt->hub &&
+ urb->dev->tt->hub->devnum != 1)
+ qh->do_split = 1;
+
+ if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
+ qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
+ /* Compute scheduling parameters once and save them. */
+ union hprt0_data hprt;
+ int bytecount = dwc_hb_mult(qh->maxp) *
+ dwc_max_packet(qh->maxp);
+
+ qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
+ usb_pipein(urb->pipe),
+ (qh->ep_type == USB_ENDPOINT_XFER_ISOC),
+ bytecount));
+
+ /* Start in a slightly future (micro)frame. */
+ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
+ SCHEDULE_SLOP);
+ qh->interval = urb->interval;
+
+ hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
+ if (hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED &&
+ is_fs_ls(urb->dev->speed)) {
+ qh->interval *= 8;
+ qh->sched_frame |= 0x7;
+ qh->start_split_frame = qh->sched_frame;
+ }
+ }
+}
+
+/**
+ * This function allocates and initializes a QH.
+ */
+static struct dwc_qh *dwc_otg_hcd_qh_create(struct dwc_hcd *hcd,
+ struct urb *urb)
+{
+ struct dwc_qh *qh;
+
+ /* Allocate memory */
+ qh = dwc_otg_hcd_qh_alloc();
+ if (qh == NULL)
+ return NULL;
+
+ dwc_otg_hcd_qh_init(hcd, qh, urb);
+ return qh;
+}
+
+/**
+ * Free each QTD in the QH's QTD-list then free the QH. QH should already be
+ * removed from a list. QTD list should already be empty if called from URB
+ * Dequeue.
+ */
+void dwc_otg_hcd_qh_free(struct dwc_qh *qh)
+{
+ struct dwc_qtd *qtd;
+ struct list_head *pos, *temp;
+
+ /* Free each QTD in the QTD list */
+ list_for_each_safe(pos, temp, &qh->qtd_list) {
+ list_del(pos);
+ qtd = dwc_list_to_qtd(pos);
+ dwc_otg_hcd_qtd_free(qtd);
+ }
+ kfree(qh);
+}
+
+/**
+ * Microframe scheduler
+ * track the total use in hcd->frame_usecs
+ * keep each qh use in qh->frame_usecs
+ * when surrendering the qh then donate the time back
+ */
+static const u16 max_uframe_usecs[] = {100, 100, 100, 100, 100, 100, 30, 0};
+
+/*
+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init
+ */
+int init_hcd_usecs(struct dwc_hcd *hcd)
+{
+ int i;
+
+ for (i = 0; i < 8; i++)
+ hcd->frame_usecs[i] = max_uframe_usecs[i];
+
+ return 0;
+}
+
+static int find_single_uframe(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ int i;
+ u16 utime;
+ int t_left;
+ int ret;
+ int done;
+
+ ret = -1;
+ utime = qh->usecs;
+ t_left = utime;
+ i = 0;
+ done = 0;
+ while (done == 0) {
+ /* At the start hcd->frame_usecs[i] = max_uframe_usecs[i]; */
+ if (utime <= hcd->frame_usecs[i]) {
+ hcd->frame_usecs[i] -= utime;
+ qh->frame_usecs[i] += utime;
+ t_left -= utime;
+ ret = i;
+ done = 1;
+ return ret;
+ } else {
+ i++;
+ if (i == 8) {
+ done = 1;
+ ret = -1;
+ }
+ }
+ }
+ return ret;
+}
+
+/*
+ * use this for FS apps that can span multiple uframes
+ */
+static int find_multi_uframe(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ int i;
+ int j;
+ u16 utime;
+ int t_left;
+ int ret;
+ int done;
+ u16 xtime;
+
+ ret = -1;
+ utime = qh->usecs;
+ t_left = utime;
+ i = 0;
+ done = 0;
+loop:
+ while (done == 0) {
+ if (hcd->frame_usecs[i] <= 0) {
+ i++;
+ if (i == 8) {
+ done = 1;
+ ret = -1;
+ }
+ goto loop;
+ }
+
+ /*
+ * We need n consequtive slots so use j as a start slot.
+ * j plus j+1 must be enough time (for now)
+ */
+ xtime = hcd->frame_usecs[i];
+ for (j = i + 1; j < 8; j++) {
+ /*
+ * if we add this frame remaining time to xtime we may
+ * be OK, if not we need to test j for a complete frame.
+ */
+ if ((xtime+hcd->frame_usecs[j]) < utime) {
+ if (hcd->frame_usecs[j] < max_uframe_usecs[j]) {
+ j = 8;
+ ret = -1;
+ continue;
+ }
+ }
+ if (xtime >= utime) {
+ ret = i;
+ j = 8; /* stop loop with a good value ret */
+ continue;
+ }
+ /* add the frame time to x time */
+ xtime += hcd->frame_usecs[j];
+ /* we must have a fully available next frame or break */
+ if ((xtime < utime) &&
+ (hcd->frame_usecs[j] == max_uframe_usecs[j])) {
+ ret = -1;
+ j = 8; /* stop loop with a bad value ret */
+ continue;
+ }
+ }
+ if (ret >= 0) {
+ t_left = utime;
+ for (j = i; (t_left > 0) && (j < 8); j++) {
+ t_left -= hcd->frame_usecs[j];
+ if (t_left <= 0) {
+ qh->frame_usecs[j] +=
+ hcd->frame_usecs[j] + t_left;
+ hcd->frame_usecs[j] = -t_left;
+ ret = i;
+ done = 1;
+ } else {
+ qh->frame_usecs[j] +=
+ hcd->frame_usecs[j];
+ hcd->frame_usecs[j] = 0;
+ }
+ }
+ } else {
+ i++;
+ if (i == 8) {
+ done = 1;
+ ret = -1;
+ }
+ }
+ }
+ return ret;
+}
+
+static int find_uframe(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ int ret = -1;
+
+ if (qh->speed == USB_SPEED_HIGH)
+ /* if this is a hs transaction we need a full frame */
+ ret = find_single_uframe(hcd, qh);
+ else
+ /* FS transaction may need a sequence of frames */
+ ret = find_multi_uframe(hcd, qh);
+
+ return ret;
+}
+
+/**
+ * Checks that the max transfer size allowed in a host channel is large enough
+ * to handle the maximum data transfer in a single (micro)frame for a periodic
+ * transfer.
+ */
+static int check_max_xfer_size(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ int status = 0;
+ u32 max_xfer_size;
+ u32 max_channel_xfer_size;
+
+ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
+ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
+
+ if (max_xfer_size > max_channel_xfer_size) {
+ printk(KERN_NOTICE "%s: Periodic xfer length %d > max xfer "
+ "length for channel %d\n", __func__, max_xfer_size,
+ max_channel_xfer_size);
+ status = -ENOSPC;
+ }
+
+ return status;
+}
+
+/**
+ * Schedules an interrupt or isochronous transfer in the periodic schedule.
+ */
+static int schedule_periodic(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ int status;
+ struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
+ int frame;
+
+ status = find_uframe(hcd, qh);
+ frame = -1;
+ if (status == 0) {
+ frame = 7;
+ } else {
+ if (status > 0)
+ frame = status-1;
+ }
+ /* Set the new frame up */
+ if (frame > -1) {
+ qh->sched_frame &= ~0x7;
+ qh->sched_frame |= (frame & 7);
+ }
+ if (status != -1)
+ status = 0;
+ if (status) {
+ printk(KERN_NOTICE "%s: Insufficient periodic bandwidth for "
+ "periodic transfer.\n", __func__);
+ return status;
+ }
+ status = check_max_xfer_size(hcd, qh);
+ if (status) {
+ printk(KERN_NOTICE "%s: Channel max transfer size too small "
+ "for periodic transfer.\n", __func__);
+ return status;
+ }
+ /* Always start in the inactive schedule. */
+ list_add_tail(&qh->qh_list_entry, &hcd->periodic_sched_inactive);
+
+ /* Update claimed usecs per (micro)frame. */
+ hcd->periodic_usecs += qh->usecs;
+
+ /*
+ * Update average periodic bandwidth claimed and # periodic reqs for
+ * usbfs.
+ */
+ bus->bandwidth_allocated += qh->usecs / qh->interval;
+
+ if (qh->ep_type == USB_ENDPOINT_XFER_INT)
+ bus->bandwidth_int_reqs++;
+ else
+ bus->bandwidth_isoc_reqs++;
+
+ return status;
+}
+
+/**
+ * This function adds a QH to either the non periodic or periodic schedule if
+ * it is not already in the schedule. If the QH is already in the schedule, no
+ * action is taken.
+ */
+static int dwc_otg_hcd_qh_add(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ int status = 0;
+
+ /* QH may already be in a schedule. */
+ if (!list_empty(&qh->qh_list_entry))
+ goto done;
+ /*
+ * Add the new QH to the appropriate schedule. For non-periodic, always
+ * start in the inactive schedule.
+ */
+ if (dwc_qh_is_non_per(qh))
+ list_add_tail(&qh->qh_list_entry,
+ &hcd->non_periodic_sched_inactive);
+ else
+ status = schedule_periodic(hcd, qh);
+
+done:
+ return status;
+}
+
+/**
+ * This function adds a QH to the non periodic deferred schedule.
+ *
+ * @return 0 if successful, negative error code otherwise.
+ */
+int dwc_otg_hcd_qh_add_deferred(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ if (!list_empty(&qh->qh_list_entry))
+ /* QH already in a schedule. */
+ goto done;
+
+ /* Add the new QH to the non periodic deferred schedule */
+ if (dwc_qh_is_non_per(qh))
+ list_add_tail(&qh->qh_list_entry,
+ &hcd->non_periodic_sched_deferred);
+done:
+ return 0;
+}
+
+
+/**
+ * Removes an interrupt or isochronous transfer from the periodic schedule.
+ */
+static void deschedule_periodic(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ struct usb_bus *bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
+ int i;
+
+ list_del_init(&qh->qh_list_entry);
+ /* Update claimed usecs per (micro)frame. */
+ hcd->periodic_usecs -= qh->usecs;
+ for (i = 0; i < 8; i++) {
+ hcd->frame_usecs[i] += qh->frame_usecs[i];
+ qh->frame_usecs[i] = 0;
+ }
+ /*
+ * Update average periodic bandwidth claimed and # periodic reqs for
+ * usbfs.
+ */
+ bus->bandwidth_allocated -= qh->usecs / qh->interval;
+
+ if (qh->ep_type == USB_ENDPOINT_XFER_INT)
+ bus->bandwidth_int_reqs--;
+ else
+ bus->bandwidth_isoc_reqs--;
+}
+
+/**
+ * Removes a QH from either the non-periodic or periodic schedule. Memory is
+ * not freed.
+ */
+void dwc_otg_hcd_qh_remove(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ /* Do nothing if QH is not in a schedule */
+ if (list_empty(&qh->qh_list_entry))
+ return;
+
+ if (dwc_qh_is_non_per(qh)) {
+ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry)
+ hcd->non_periodic_qh_ptr =
+ hcd->non_periodic_qh_ptr->next;
+ list_del_init(&qh->qh_list_entry);
+ } else {
+ deschedule_periodic(hcd, qh);
+ }
+}
+
+/**
+ * Defers a QH. For non-periodic QHs, removes the QH from the active
+ * non-periodic schedule. The QH is added to the deferred non-periodic
+ * schedule if any QTDs are still attached to the QH.
+ */
+int dwc_otg_hcd_qh_deferr(struct dwc_hcd *hcd, struct dwc_qh *qh, int delay)
+{
+ int deact = 1;
+
+ if (dwc_qh_is_non_per(qh)) {
+ qh->sched_frame =
+ dwc_frame_num_inc(hcd->frame_number,
+ delay);
+ qh->channel = NULL;
+ qh->qtd_in_process = NULL;
+ deact = 0;
+ dwc_otg_hcd_qh_remove(hcd, qh);
+ if (!list_empty(&qh->qtd_list))
+ /* Add back to deferred non-periodic schedule. */
+ dwc_otg_hcd_qh_add_deferred(hcd, qh);
+ }
+ return deact;
+}
+
+/**
+ * Schedule the next continuing periodic split transfer
+ */
+static void sched_next_per_split_xfr(struct dwc_qh *qh, u16 fr_num,
+ int sched_split)
+{
+ if (sched_split) {
+ qh->sched_frame = fr_num;
+ if (dwc_frame_num_le(fr_num,
+ dwc_frame_num_inc(qh->start_split_frame, 1))) {
+ /*
+ * Allow one frame to elapse after start split
+ * microframe before scheduling complete split, but DONT
+ * if we are doing the next start split in the
+ * same frame for an ISOC out.
+ */
+ if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
+ qh->ep_is_in)
+ qh->sched_frame = dwc_frame_num_inc(
+ qh->sched_frame, 1);
+ }
+ } else {
+ qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
+ qh->interval);
+
+ if (dwc_frame_num_le(qh->sched_frame, fr_num))
+ qh->sched_frame = fr_num;
+ qh->sched_frame |= 0x7;
+ qh->start_split_frame = qh->sched_frame;
+ }
+}
+
+/**
+ * Deactivates a periodic QH. The QH is removed from the periodic queued
+ * schedule. If there are any QTDs still attached to the QH, the QH is added to
+ * either the periodic inactive schedule or the periodic ready schedule and its
+ * next scheduled frame is calculated. The QH is placed in the ready schedule if
+ * the scheduled frame has been reached already. Otherwise it's placed in the
+ * inactive schedule. If there are no QTDs attached to the QH, the QH is
+ * completely removed from the periodic schedule.
+ */
+static void deactivate_periodic_qh(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ int sched_next_split)
+{
+ /* unsigned long flags; */
+ u16 fr_num = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
+
+ if (qh->do_split) {
+ sched_next_per_split_xfr(qh, fr_num, sched_next_split);
+ } else {
+ qh->sched_frame = dwc_frame_num_inc(qh->sched_frame,
+ qh->interval);
+ if (dwc_frame_num_le(qh->sched_frame, fr_num))
+ qh->sched_frame = fr_num;
+ }
+
+ if (list_empty(&qh->qtd_list)) {
+ dwc_otg_hcd_qh_remove(hcd, qh);
+ } else {
+ /*
+ * Remove from periodic_sched_queued and move to appropriate
+ * queue.
+ */
+ if (qh->sched_frame == fr_num)
+ list_move(&qh->qh_list_entry,
+ &hcd->periodic_sched_ready);
+ else
+ list_move(&qh->qh_list_entry,
+ &hcd->periodic_sched_inactive);
+ }
+}
+
+/**
+ * Deactivates a non-periodic QH. Removes the QH from the active non-periodic
+ * schedule. The QH is added to the inactive non-periodic schedule if any QTDs
+ * are still attached to the QH.
+ */
+static void deactivate_non_periodic_qh(struct dwc_hcd *hcd, struct dwc_qh *qh)
+{
+ dwc_otg_hcd_qh_remove(hcd, qh);
+ if (!list_empty(&qh->qtd_list))
+ dwc_otg_hcd_qh_add(hcd, qh);
+}
+
+/**
+ * Deactivates a QH. Determines if the QH is periodic or non-periodic and takes
+ * the appropriate action.
+ */
+void dwc_otg_hcd_qh_deactivate(struct dwc_hcd *hcd, struct dwc_qh *qh,
+ int sched_next_periodic_split)
+{
+ if (dwc_qh_is_non_per(qh))
+ deactivate_non_periodic_qh(hcd, qh);
+ else
+ deactivate_periodic_qh(hcd, qh, sched_next_periodic_split);
+}
+
+/**
+ * Initializes a QTD structure.
+ */
+static void dwc_otg_hcd_qtd_init(struct dwc_qtd *qtd, struct urb *urb)
+{
+ memset(qtd, 0, sizeof(struct dwc_qtd));
+ qtd->urb = urb;
+
+ if (usb_pipecontrol(urb->pipe)) {
+ /*
+ * The only time the QTD data toggle is used is on the data
+ * phase of control transfers. This phase always starts with
+ * DATA1.
+ */
+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
+ qtd->control_phase = DWC_OTG_CONTROL_SETUP;
+ }
+
+ /* start split */
+ qtd->complete_split = 0;
+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
+ qtd->isoc_split_offset = 0;
+
+ /* Store the qtd ptr in the urb to reference what QTD. */
+ urb->hcpriv = qtd;
+
+ INIT_LIST_HEAD(&qtd->qtd_list_entry);
+ return;
+}
+
+/* Allocates memory for a QTD structure. */
+static inline struct dwc_qtd *dwc_otg_hcd_qtd_alloc(gfp_t _mem_flags)
+{
+ return kmalloc(sizeof(struct dwc_qtd), _mem_flags);
+}
+
+/**
+ * This function allocates and initializes a QTD.
+ */
+struct dwc_qtd *dwc_otg_hcd_qtd_create(struct urb *urb, gfp_t _mem_flags)
+{
+ struct dwc_qtd *qtd = dwc_otg_hcd_qtd_alloc(_mem_flags);
+
+ if (!qtd)
+ return NULL;
+
+ dwc_otg_hcd_qtd_init(qtd, urb);
+ return qtd;
+}
+
+/**
+ * This function adds a QTD to the QTD-list of a QH. It will find the correct
+ * QH to place the QTD into. If it does not find a QH, then it will create a
+ * new QH. If the QH to which the QTD is added is not currently scheduled, it
+ * is placed into the proper schedule based on its EP type.
+ *
+ */
+int dwc_otg_hcd_qtd_add(struct dwc_qtd *qtd, struct dwc_hcd *hcd)
+{
+ struct usb_host_endpoint *ep;
+ struct dwc_qh *qh;
+ int retval = 0;
+ struct urb *urb = qtd->urb;
+
+ /*
+ * Get the QH which holds the QTD-list to insert to. Create QH if it
+ * doesn't exist.
+ */
+ ep = dwc_urb_to_endpoint(urb);
+
+ qh = (struct dwc_qh *) ep->hcpriv;
+ if (!qh) {
+ qh = dwc_otg_hcd_qh_create(hcd, urb);
+ if (!qh) {
+ retval = -1;
+ goto done;
+ }
+ ep->hcpriv = qh;
+ }
+ qtd->qtd_qh_ptr = qh;
+ retval = dwc_otg_hcd_qh_add(hcd, qh);
+ if (!retval)
+ list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
+
+done:
+ return retval;
+}
--
1.7.3
^ permalink raw reply related
* [PATCH V5 9/9] Add Synopsys DesignWare HS USB OTG driver kernel configuration and Makefile.
From: Fushen Chen @ 2010-10-21 0:42 UTC (permalink / raw)
To: linux-usb; +Cc: linuxppc-dev, gregkh, Mark Miesfeld, Fushen Chen
In-Reply-To: <1287621776919-git-send-email-fchen@apm.com>
Signed-off-by: Fushen Chen <fchen@apm.com>
Signed-off-by: Mark Miesfeld <mmiesfeld@apm.com>
---
drivers/Makefile | 1 +
drivers/usb/Kconfig | 2 +
drivers/usb/dwc_otg/Kconfig | 99 ++++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc_otg/Makefile | 19 ++++++++
4 files changed, 121 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/Kconfig
create mode 100644 drivers/usb/dwc_otg/Makefile
diff --git a/drivers/Makefile b/drivers/Makefile
index a2aea53..36cb201 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -67,6 +67,7 @@ obj-$(CONFIG_UWB) += uwb/
obj-$(CONFIG_USB_OTG_UTILS) += usb/otg/
obj-$(CONFIG_USB) += usb/
obj-$(CONFIG_USB_MUSB_HDRC) += usb/musb/
+obj-$(CONFIG_USB_DWC_OTG) += usb/dwc_otg/
obj-$(CONFIG_PCI) += usb/
obj-$(CONFIG_USB_GADGET) += usb/gadget/
obj-$(CONFIG_SERIO) += input/serio/
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 4aa00e6..bbb8b2c 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -114,6 +114,8 @@ source "drivers/usb/host/Kconfig"
source "drivers/usb/musb/Kconfig"
+source "drivers/usb/dwc_otg/Kconfig"
+
source "drivers/usb/class/Kconfig"
source "drivers/usb/storage/Kconfig"
diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig
new file mode 100644
index 0000000..174141d
--- /dev/null
+++ b/drivers/usb/dwc_otg/Kconfig
@@ -0,0 +1,99 @@
+#
+# USB Dual Role (OTG-ready) Controller Drivers
+# for silicon based on Synopsys DesignWare IP
+#
+
+comment "Enable Host or Gadget support for DesignWare OTG controller"
+ depends on !USB && USB_GADGET=n
+
+config USB_DWC_OTG
+ depends on (USB || USB_GADGET)
+ depends on 405EZ || 405EX || 460EX
+ select NOP_USB_XCEIV
+ select USB_OTG_UTILS
+ tristate "Synopsys DWC OTG Controller"
+ default USB_GADGET
+ help
+ This driver provides USB Device Controller support for the
+ Synopsys DesignWare USB OTG Core used on the AppliedMicro PowerPC SoC.
+
+config DWC_DEBUG
+ bool "Enable DWC Debugging"
+ depends on USB_DWC_OTG
+ default n
+ help
+ Enable DWC driver debugging
+
+choice
+ prompt "DWC Mode Selection"
+ depends on USB_DWC_OTG
+ default DWC_HOST_ONLY
+ help
+ Select the DWC Core in OTG, Host only, or Device only mode.
+
+config DWC_HOST_ONLY
+ bool "DWC Host Only Mode" if 405EX || 460EX
+
+config DWC_OTG_MODE
+ bool "DWC OTG Mode" if 405EX || 460EX
+ select USB_GADGET_SELECTED
+
+config DWC_DEVICE_ONLY
+ bool "DWC Device Only Mode"
+ select USB_GADGET_SELECTED
+
+endchoice
+
+# enable peripheral support (including with OTG)
+config USB_GADGET_DWC_HDRC
+ bool
+ depends on USB_DWC_OTG && (DWC_DEVICE_ONLY || USB_DWC_OTG)
+
+choice
+ prompt "DWC DMA/SlaveMode Selection"
+ depends on USB_DWC_OTG
+ default DWC_DMA_MODE
+ help
+ Select the DWC DMA or Slave Mode.
+ DMA mode uses the DWC core internal DMA engines.
+ Slave mode uses the processor PIO to tranfer data.
+ In Slave mode, processor's DMA channels can be used if available.
+
+config DWC_SLAVE
+ bool "DWC Slave Mode" if 405EX || 460EX
+
+config DWC_DMA_MODE
+ bool "DWC DMA Mode" if 405EX || (460EX && \
+ (!USB_EHCI_HCD || !USB_OHCI_HCD))
+
+endchoice
+
+config USB_OTG_WHITELIST
+ bool "Rely on OTG Targeted Peripherals List"
+ depends on !USB_SUSPEND && USB_DWC_OTG
+ default n
+ help
+ This is the same flag as in ../core/Kconfig.
+ It is here for easy deselect.
+
+config DWC_OTG_REG_LE
+ depends on USB_DWC_OTG
+ bool "DWC Little Endian Register" if 405EX || 460EX
+ default y
+ help
+ OTG core register access is Little-Endian.
+
+config DWC_OTG_FIFO_LE
+ depends on USB_DWC_OTG
+ bool "DWC FIFO Little Endian" if 405EZ
+ default n
+ help
+ OTG core FIFO access is Little-Endian.
+
+config DWC_LIMITED_XFER_SIZE
+ depends on USB_GADGET_DWC_HDRC
+ bool "DWC Endpoint Limited Xfer Size" if 405EZ || 405EX || 460EX
+ default n if 460EX || 405EX
+ default y if 405EZ
+ help
+ Bit fields in the Device EP Transfer Size Register is 11 bits.
diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile
new file mode 100644
index 0000000..31dd5e8
--- /dev/null
+++ b/drivers/usb/dwc_otg/Makefile
@@ -0,0 +1,19 @@
+#
+# OTG infrastructure and transceiver drivers
+#
+obj-$(CONFIG_USB_DWC_OTG) += dwc_otg.o
+
+dwc_otg-objs := dwc_otg_cil.o dwc_otg_cil_intr.o dwc_otg_param.o
+
+ifeq ($(CONFIG_4xx_SOC),y)
+dwc_otg-objs += dwc_otg_apmppc.o
+endif
+
+ifneq ($(CONFIG_DWC_DEVICE_ONLY),y)
+dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_intr.o \
+ dwc_otg_hcd_queue.o
+endif
+
+ifneq ($(CONFIG_DWC_HOST_ONLY),y)
+dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o
+endif
--
1.7.3
^ permalink raw reply related
* [PATCH V5 0/9] *** Add Synopsys DesignWare HS USB OTG driver ***
From: Fushen Chen @ 2010-10-21 0:42 UTC (permalink / raw)
To: linux-usb; +Cc: linuxppc-dev, gregkh, Fushen Chen
This patch series add Synopsys DesignWare HS USB OTG driver support.
"PATCH V5" has a new license header from Synopsys and APM
Previous versions:
1. Addressed comment from Wolfgang Denk to sync with
git://git.denx.de/linux-2.6-denx.git.
2. Added bug fixes and features from Stefan Roese and Chuck Meade.
3. Removed dts file from this pathch per Sergei Shtylyov suggestion.
We'll submit a separate patch to PowerPC tree.
4. Modified driver to use generic USB OTG enumeration state.
5. Move Makefiles to the last patch per David Daney suggestion.
Fushen Chen (9):
Add Synopsys DesignWare HS USB OTG Control and Status Register (CSR).
Add Synopsys DesignWare HS USB OTG driver framework.
Add Synopsys DesignWare HS USB OTG Core Interface Layer (CIL).
Add Synopsys DesignWare HS USB OTG HCD function.
Add Synopsys DesignWare HS USB OTG HCD interrupt function.
Add Synopsys DesignWare HS USB OTG HCD queue function.
Add Synopsys DesignWare HS USB OTG PCD function.
Add Synopsys DesignWare HS USB OTG PCD interrupt function.
Add Synopsys DesignWare HS USB OTG driver kernel configuration and
Makefile.
drivers/Makefile | 1 +
drivers/usb/Kconfig | 2 +
drivers/usb/dwc_otg/Kconfig | 99 +
drivers/usb/dwc_otg/Makefile | 19 +
drivers/usb/dwc_otg/dwc_otg_apmppc.c | 394 ++++
drivers/usb/dwc_otg/dwc_otg_cil.c | 892 +++++++++
drivers/usb/dwc_otg/dwc_otg_cil.h | 1181 +++++++++++
drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 618 ++++++
drivers/usb/dwc_otg/dwc_otg_driver.h | 78 +
drivers/usb/dwc_otg/dwc_otg_hcd.c | 2400 +++++++++++++++++++++++
drivers/usb/dwc_otg/dwc_otg_hcd.h | 413 ++++
drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1465 ++++++++++++++
drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 697 +++++++
drivers/usb/dwc_otg/dwc_otg_param.c | 730 +++++++
drivers/usb/dwc_otg/dwc_otg_pcd.c | 1733 ++++++++++++++++
drivers/usb/dwc_otg/dwc_otg_pcd.h | 137 ++
drivers/usb/dwc_otg/dwc_otg_pcd_intr.c | 2262 +++++++++++++++++++++
drivers/usb/dwc_otg/dwc_otg_regs.h | 3269 +++++++++++++++++++++++++++++++
18 files changed, 16390 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc_otg/Kconfig
create mode 100644 drivers/usb/dwc_otg/Makefile
create mode 100644 drivers/usb/dwc_otg/dwc_otg_apmppc.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h
create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h
create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h
create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_param.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd.h
create mode 100644 drivers/usb/dwc_otg/dwc_otg_pcd_intr.c
create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h
--
1.7.3
^ permalink raw reply
* [patch 1/1] powerpc: enable ARCH_DMA_ADDR_T_64BIT with ARCH_PHYS_ADDR_T_64BIT
From: akpm @ 2010-10-20 22:56 UTC (permalink / raw)
To: benh; +Cc: fujita.tomonori, linuxppc-dev, akpm
From: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
arch/powerpc/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff -puN arch/powerpc/Kconfig~powerpc-enable-arch_dma_addr_t_64bit-with-arch_phys_addr_t_64bit arch/powerpc/Kconfig
--- a/arch/powerpc/Kconfig~powerpc-enable-arch_dma_addr_t_64bit-with-arch_phys_addr_t_64bit
+++ a/arch/powerpc/Kconfig
@@ -16,6 +16,9 @@ config WORD_SIZE
config ARCH_PHYS_ADDR_T_64BIT
def_bool PPC64 || PHYS_64BIT
+config ARCH_DMA_ADDR_T_64BIT
+ def_bool ARCH_PHYS_ADDR_T_64BIT
+
config MMU
bool
default y
_
^ permalink raw reply
* Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
From: Benjamin Herrenschmidt @ 2010-10-20 20:56 UTC (permalink / raw)
To: pacman; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <20101020183336.1714.qmail@kosh.dhis.org>
On Wed, 2010-10-20 at 13:33 -0500, pacman@kosh.dhis.org wrote:
> > Just try :-) "quiesce" is something that afaik only apple ever
> > implemented anyways. It uses hooks inside their OF to shut down all
> > drivers that do bus master (among other HW sanitization tasks).
>
> I booted a version with a prom_close_stdout after the last prom_debug. It
> didn't have any effect. That 1000Hz clock was still ticking.
Ok so you'll have to make up a "workaround" in prom_init that looks for
OHCI's in the device-tree and disable them.
Check if the OHCI node has some existing f-code words you can use for
that with "dev /path-to-ohci words" in OF for example. If not, you may
need to use the low level register accessors. Use OF client interface
"interpret" to run forth code from C.
Cheers,
Ben.
^ permalink raw reply
* Re: [QUESTION] MPC8343 'internal only' DMA support
From: Timur Tabi @ 2010-10-20 19:45 UTC (permalink / raw)
To: KRONSTORFER Horst; +Cc: linuxppc-dev
In-Reply-To: <2E0C184B35151B4690232FF6CFE53FE501569473@VIECLEX02.frequentis.frq>
On Tue, Oct 19, 2010 at 3:15 AM, KRONSTORFER Horst
<Horst.KRONSTORFER@frequentis.com> wrote:
> i assume the mpc8343 dma controllers ability to do internally controlled
> operations (csb/csb)
> is _not_ affected by deactivating externally controlled operations via
> pinmultiplexing in sicrl.
>
> am I correct?
Hmmm... maybe. In general, if you want an external master for the DMA
controller, I think you need to enable that via various registers. So
if you don't enable external master, you won't have one.
Does that answer your question?
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
From: pacman @ 2010-10-20 18:33 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1287570736.2198.19.camel@pasglop>
Benjamin Herrenschmidt writes:
>
> On Tue, 2010-10-19 at 22:23 -0500, pacman@kosh.dhis.org wrote:
> > The diff fragment above applied inside prom_close_stdin, but there are
> > some
> > prom_printf calls after prom_close_stdin. Calling prom_printf after
> > closing
> > stdout sounds like it could be bad. If I moved it down below all the
> > prom_printf's, it would be after the "quiesce" call. Would that be
> > acceptable
> > (or even interesting as an experiment)? Does a close need a quiesce
> > after it?
>
> Just try :-) "quiesce" is something that afaik only apple ever
> implemented anyways. It uses hooks inside their OF to shut down all
> drivers that do bus master (among other HW sanitization tasks).
I booted a version with a prom_close_stdout after the last prom_debug. It
didn't have any effect. That 1000Hz clock was still ticking.
--
Alan Curry
^ permalink raw reply
* RE: Freescale P2020/ 85xx PCIe: DMA low throughtput
From: Jenkins, Clive @ 2010-10-20 12:49 UTC (permalink / raw)
To: Natalie Shapira, galak, linuxppc-dev, leoli, zw
In-Reply-To: <4CBEC62E.30900@extricom.com>
> Hi,=20
>=20
> I'm working on bring up for a new board based on Freescales p2020.
> I have a programmable FPGA as a PCIe device with a buffer I can
> write to and from.
> I want to test performence for the PCIe bus.=20
> I encountered a problem while doing a DMA between the FPGA & DDR.=20
> The whole buffer moves to and from the device with out
> mismatches but with low throughtput.=20
> The thing is that the buffer divided to many transactions of byte
> size instead of transferring it in a burst.=20
> I must mention that even a buffer of word size, divided in to byte
> transactions by the DMA (the core can read a word so it seems like
> the DMA fault.
> I tried to change the latency timer, max latency, min latency and
> cache line in the configuration space of both sides of the pcie
> bus. It didn't help.
> Do you have an idea what can it be?=20
>=20
> Thanks,
> Natalie.=20
Assuming the P2020 has the usual 85xx-style DMA engine, you may have
the Band Width Control cleared to 0. This 4-bit field (BWC) restricts
the transfer size to 2^BWC bytes, for BWC=3D0,1,..0xa. 0xb-0xe are
reserved. 0xf disables bandwidth sharing to allow uninterrupted
transfers from each channel, so if you are using several channels
one channel can completely lock out other channels. BWC=3D0x8 at reset
(2^8 =3D 256 bytes). See the P2020 manual for more details.
BWC is the field with mask 0x0f000000 in the MR (Master Reset)
register for the channel (0, 1, 2, 3), at offset 0x100, 0x180, 0x200,
0x280 relative to the base of the DMA controller.
Clive
^ permalink raw reply
* Freescale P2020/ 85xx PCIe: DMA low throughtput
From: Natalie Shapira @ 2010-10-20 10:36 UTC (permalink / raw)
To: galak, linuxppc-dev, leoli, zw
[-- Attachment #1: Type: text/plain, Size: 835 bytes --]
Hi,
I'm working on bring up for a new board based on Freescales p2020. I
have a programmable FPGA as a PCIe device with a buffer I can write to
and from.
I want to test performence for the PCIe bus.
I encountered a problem while doing a DMA between the FPGA & DDR.
The whole buffer moves to and from the device with out mismatches
but with low throughtput.
The thing is that the buffer divided to many transactions of byte size
instead of transferring it in a burst.
I must mention that even a buffer of word size, divided in to byte
transactions by the DMA (the core can read a word so it seems like the
DMA fault.
I tried to change the latency timer, max latency, min latency and cache
line in the configuration space of both sides of the pcie bus. It didn't
help.
Do you have an idea what can it be?
Thanks,
Natalie.
[-- Attachment #2: Type: text/html, Size: 1081 bytes --]
^ permalink raw reply
* Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
From: Benjamin Herrenschmidt @ 2010-10-20 10:32 UTC (permalink / raw)
To: pacman; +Cc: Mel Gorman, linux-kernel, linux-mm, Andrew Morton, linuxppc-dev
In-Reply-To: <20101020032345.5240.qmail@kosh.dhis.org>
On Tue, 2010-10-19 at 22:23 -0500, pacman@kosh.dhis.org wrote:
> The diff fragment above applied inside prom_close_stdin, but there are
> some
> prom_printf calls after prom_close_stdin. Calling prom_printf after
> closing
> stdout sounds like it could be bad. If I moved it down below all the
> prom_printf's, it would be after the "quiesce" call. Would that be
> acceptable
> (or even interesting as an experiment)? Does a close need a quiesce
> after it?
Just try :-) "quiesce" is something that afaik only apple ever
implemented anyways. It uses hooks inside their OF to shut down all
drivers that do bus master (among other HW sanitization tasks).
Cheers,
Ben.
^ permalink raw reply
* Re: CONFIG_FEC is not good for mpc8xx ethernet?
From: Shawn Jin @ 2010-10-20 9:19 UTC (permalink / raw)
To: tiejun.chen; +Cc: Scott Wood, ppcdev
In-Reply-To: <AANLkTinN-xOecVynPYxmLoT9HJKFs0iPo3pLXF05Tudv@mail.gmail.com>
> The problem for me is that the PHY failed to be probed. The related
> error messages are shown below. I even tried the patch Tiejun pointed
> out. But that doesn't help. The phy ID read from the bus was all Fs.
>
> FEC MII Bus: probed
> mdio_bus fa200e00: error probing PHY at address 0
I think I figured out the probing failure. My board uses PortD bit8 as
an input pin from phy's MDC. I didn't set up this pin assignment.
When probing the PHY the fs_enet_fec_mii_read() is called to get phy
id. The correct phy id was returned. However when I tried to set up
the ip address using the command "ifconfig eth0 192.168.0.4". The same
function was called again. But this time the fecp->fec_r_cntrl
mysteriously became 0 so the kernel reported bug for that.
# ifconfig eth0 192.168.0.4
------------[ cut here ]------------
kernel BUG at drivers/net/fs_enet/mii-fec.c:58!
Oops: Exception in kernel mode, sig: 5 [#1]
MyMPC870
NIP: c012b79c LR: c012963c CTR: c012b77c
REGS: c7457c60 TRAP: 0700 Not tainted (2.6.33.5)
MSR: 00029032 <EE,ME,CE,IR,DR> CR: 24020042 XER: 20000000
TASK = c7840000[236] 'ifconfig' THREAD: c7456000
GPR00: 00000001 c7457d10 c7840000 c7845400 00000000 00000001 ffffffff 00000000
GPR08: c77c44fc c906ce00 c784806c 00000b9f 84020042 100b986c 10096042 1009604f
GPR16: 1009603b 10096030 10096001 100b188e c7457e18 ffff8914 c742430c c740b000
GPR24: c7424300 c78443c0 00000001 00000000 c7845428 c7845400 c7845600 c7845600
NIP [c012b79c] fs_enet_fec_mii_read+0x20/0x90
LR [c012963c] mdiobus_read+0x50/0x74
Call Trace:
[c7457d10] [c0115744] driver_bound+0x60/0xa0 (unreliable)
[c7457d30] [c0129094] genphy_config_init+0x24/0xd4
[c7457d40] [c0128920] phy_init_hw+0x4c/0x78
[c7457d50] [c0128a40] phy_connect_direct+0x24/0x88
[c7457d70] [c0133e50] of_phy_connect+0x48/0x6c
[c7457d90] [c012ae10] fs_enet_open+0xf0/0x2cc
[c7457db0] [c0148a54] dev_open+0x100/0x138
[c7457dd0] [c0146ca0] dev_change_flags+0x80/0x1a8
[c7457df0] [c018e104] devinet_ioctl+0x630/0x750
[c7457e60] [c018eb5c] inet_ioctl+0xcc/0xf8
[c7457e70] [c01370d8] sock_ioctl+0x60/0x28c
[c7457e90] [c007dbcc] vfs_ioctl+0x38/0x9c
[c7457ea0] [c007ddf0] do_vfs_ioctl+0x84/0x708
[c7457f10] [c007e4b4] sys_ioctl+0x40/0x74
[c7457f40] [c000de60] ret_from_syscall+0x0/0x38
Instruction dump:
80010014 7c0803a6 38210010 4e800020 81230018 81290000 7c0004ac 80090144
0c000000 4c00012c 68000004 5400f7fe <0f000000> 5484b810 64846002 54a5925a
---[ end trace 41bf95259a68372e ]---
Trace/breakpoint trap
I cannot find where the fec_r_cntrl would be reset to 0 after
fs_enet_mdio_probe() sets it to FEC_RCNTRL_MII_MODE. Odd?
Thanks,
-Shawn.
^ permalink raw reply
* RE: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Zang Roy-R61911 @ 2010-10-20 8:33 UTC (permalink / raw)
To: Kumar Gala
Cc: Wood Scott-B07421, dedekind1, Lan Chunhe-B25806, linuxppc-dev,
linux-mtd, akpm, dwmw2, Gala Kumar-B11780
In-Reply-To: <707F7370-D01B-462F-B896-D7F677AED8EB@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Wednesday, October 20, 2010 14:55 PM
> To: Zang Roy-R61911
> Cc: linux-mtd@lists.infradead.org; Wood Scott-B07421;
dedekind1@gmail.com; Lan
> Chunhe-B25806; linuxppc-dev@ozlabs.org; akpm@linux-foundation.org;
> dwmw2@infradead.org; Gala Kumar-B11780
> Subject: Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt
common to
> elbc devices
>=20
>=20
> On Oct 20, 2010, at 12:12 AM, Zang Roy-R61911 wrote:
>=20
> >
> >
> >> -----Original Message-----
> >> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> >> Sent: Tuesday, October 19, 2010 21:19 PM
> >> To: Zang Roy-R61911
> >> Cc: linux-mtd@lists.infradead.org; Wood Scott-B07421;
> > dedekind1@gmail.com; Lan
> >> Chunhe-B25806; linuxppc-dev@ozlabs.org; akpm@linux-foundation.org;
> >> dwmw2@infradead.org; Gala Kumar-B11780
> >> Subject: Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt
> > common to
> >> elbc devices
> >>
> >>
> >> On Oct 18, 2010, at 2:22 AM, Roy Zang wrote:
> >>
> >>> Move Freescale elbc interrupt from nand dirver to elbc driver.
> >>> Then all elbc devices can use the interrupt instead of ONLY nand.
> >>>
> >>> For former nand driver, it had the two functions:
> >>>
> >>> 1. detecting nand flash partitions;
> >>> 2. registering elbc interrupt.
> >>>
> >>> Now, second function is removed to fsl_lbc.c.
> >>>
> >>> Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com>
> >>> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> >>> Reviewed-by: Anton Vorontsov <cbouatmailru@gmail.com>
> >>> Cc: Wood Scott-B07421 <B07421@freescale.com>
> >>> ---
> >>
> >> Roy, this is a nit, but are these really p4080 specific? just
> > wondering why
> >> the subject is P4080/eLBC:...
> > We start these code in P4080 project. Some customer want to track
eLBC
> > error on P4080, but some of the code is limited in nand driver only
...
> > That is why P4080/eLBC ...
> > Roy
>=20
> sure, but is anything about these patches p4080 specific?
No.
Should I update the subject by a new version.
Thanks.
Roy
^ permalink raw reply
* Re: CONFIG_FEC is not good for mpc8xx ethernet?
From: tiejun.chen @ 2010-10-20 7:46 UTC (permalink / raw)
To: Shawn Jin; +Cc: Scott Wood, ppcdev
In-Reply-To: <AANLkTinN-xOecVynPYxmLoT9HJKFs0iPo3pLXF05Tudv@mail.gmail.com>
Shawn Jin wrote:
>>> On MPC8xx you want drivers/net/fs_enet/mii-fec.c. �This is just the
>>> MDIO driver; it doesn't handle any particular PHY. �I don't know if
>>> there is a driver specifically for AM79C874, though the generic PHY
>>> support may be good enough.
>> Maybe.
>>
>> I can found one related patch for supporting PHY AM79C874 on 2.6.15,
>> ------
>> http://lists.ozlabs.org/pipermail/linuxppc-embedded/2005-November/021043.html
>>
>> But I don't see that on the latest kernel, and also I don't know the history
>> completely for that. Maybe its already merged into one generic PHY driver but
>> I'm not sure.
>
> Thank Scott & Tiejun for valuable information.
>
> The problem for me is that the PHY failed to be probed. The related
> error messages are shown below. I even tried the patch Tiejun pointed
> out. But that doesn't help. The phy ID read from the bus was all Fs.
>
> FEC MII Bus: probed
> mdio_bus fa200e00: error probing PHY at address 0
Is this is all log related to PHY? And are you sure your PHY Address is zero?
Often there are at most 32 PHY devices resided one MDIO bus. So you can dump PHY
ID to check if there is a PHY firstly. A ID value of 0xffff indicates that the
address is invalid if I recalled properly.
But I think PHY driver already do the above process on Linux.
So looks MDIO driver cannot compatible for your platform. I recommend you try
debug mdio driver to access valid PHY ID firstly. Especially where/why this stop
at address '0'? When you can get a valid PHY ID you can go phy driver.
>
> I don't know if AM79C874 requires any special handling. But from the
> comment in mdiobb_cmd() there seems to be something special.
> /*
> * Send a 32 bit preamble ('1's) with an extra '1' bit for good
> * measure. The IEEE spec says this is a PHY optional
> * requirement. The AMD 79C874 requires one after power up and
> * one after a MII communications error. This means that we are
> * doing more preambles than we need, but it is safer and will be
> * much more robust.
> */
>
> If there is any network action in u-boot, e.g., tftp or ping, the PHY
> can be successfully probed after that. Any hints what went wrong with
On bootstrap the driver should reset MDIO bus/PHY before probing PHY again.
Tiejun
> the PHY?
>
> Thanks,
> -Shawn.
>
^ permalink raw reply
* Re: CONFIG_FEC is not good for mpc8xx ethernet?
From: Shawn Jin @ 2010-10-20 7:03 UTC (permalink / raw)
To: tiejun.chen; +Cc: Scott Wood, ppcdev
In-Reply-To: <4CBCFC5D.3010403@windriver.com>
>> On MPC8xx you want drivers/net/fs_enet/mii-fec.c. =A0This is just the
>> MDIO driver; it doesn't handle any particular PHY. =A0I don't know if
>> there is a driver specifically for AM79C874, though the generic PHY
>> support may be good enough.
>
> Maybe.
>
> I can found one related patch for supporting PHY AM79C874 on 2.6.15,
> ------
> http://lists.ozlabs.org/pipermail/linuxppc-embedded/2005-November/021043.=
html
>
> But I don't see that on the latest kernel, and also I don't know the hist=
ory
> completely for that. Maybe its already merged into one generic PHY driver=
but
> I'm not sure.
Thank Scott & Tiejun for valuable information.
The problem for me is that the PHY failed to be probed. The related
error messages are shown below. I even tried the patch Tiejun pointed
out. But that doesn't help. The phy ID read from the bus was all Fs.
FEC MII Bus: probed
mdio_bus fa200e00: error probing PHY at address 0
I don't know if AM79C874 requires any special handling. But from the
comment in mdiobb_cmd() there seems to be something special.
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good
* measure. The IEEE spec says this is a PHY optional
* requirement. The AMD 79C874 requires one after power up and
* one after a MII communications error. This means that we are
* doing more preambles than we need, but it is safer and will be
* much more robust.
*/
If there is any network action in u-boot, e.g., tftp or ping, the PHY
can be successfully probed after that. Any hints what went wrong with
the PHY?
Thanks,
-Shawn.
^ permalink raw reply
* Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Kumar Gala @ 2010-10-20 6:54 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Wood Scott-B07421, dedekind1, Lan Chunhe-B25806, linuxppc-dev,
linux-mtd, akpm, dwmw2, Gala Kumar-B11780
In-Reply-To: <3850A844E6A3854C827AC5C0BEC7B60A2B08A5@zch01exm23.fsl.freescale.net>
On Oct 20, 2010, at 12:12 AM, Zang Roy-R61911 wrote:
>
>
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Tuesday, October 19, 2010 21:19 PM
>> To: Zang Roy-R61911
>> Cc: linux-mtd@lists.infradead.org; Wood Scott-B07421;
> dedekind1@gmail.com; Lan
>> Chunhe-B25806; linuxppc-dev@ozlabs.org; akpm@linux-foundation.org;
>> dwmw2@infradead.org; Gala Kumar-B11780
>> Subject: Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt
> common to
>> elbc devices
>>
>>
>> On Oct 18, 2010, at 2:22 AM, Roy Zang wrote:
>>
>>> Move Freescale elbc interrupt from nand dirver to elbc driver.
>>> Then all elbc devices can use the interrupt instead of ONLY nand.
>>>
>>> For former nand driver, it had the two functions:
>>>
>>> 1. detecting nand flash partitions;
>>> 2. registering elbc interrupt.
>>>
>>> Now, second function is removed to fsl_lbc.c.
>>>
>>> Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com>
>>> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
>>> Reviewed-by: Anton Vorontsov <cbouatmailru@gmail.com>
>>> Cc: Wood Scott-B07421 <B07421@freescale.com>
>>> ---
>>
>> Roy, this is a nit, but are these really p4080 specific? just
> wondering why
>> the subject is P4080/eLBC:...
> We start these code in P4080 project. Some customer want to track eLBC
> error on P4080, but some of the code is limited in nand driver only ...
> That is why P4080/eLBC ...
> Roy
sure, but is anything about these patches p4080 specific?
- k
^ permalink raw reply
* Re:
From: Michal Simek @ 2010-10-20 5:31 UTC (permalink / raw)
To: microblaze-uclinux; +Cc: nacc, linuxppc-dev, miltonm
In-Reply-To: <1287422825-14999-2-git-send-email-nacc@us.ibm.com>
Nishanth Aravamudan wrote:
> Use set_dma_ops and remove now used-once oddly named temp pointer sd.
>
> Signed-off-by: Milton Miller <miltonm@bga.com>
> Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
> Cc: benh@kernel.crashing.org
> Cc: linuxppc-dev@lists.ozlabs.org
> ---
Maybe I forget to write you that this patch is already applied.
http://git.monstr.eu/git/gitweb.cgi?p=linux-2.6-microblaze.git;a=commit;h=9a6df6cbfd903b6d9b4b1021f46d78601adfac77
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
^ permalink raw reply
* RE: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt common to elbc devices
From: Zang Roy-R61911 @ 2010-10-20 5:12 UTC (permalink / raw)
To: Kumar Gala
Cc: Wood Scott-B07421, dedekind1, Lan Chunhe-B25806, linuxppc-dev,
linux-mtd, akpm, dwmw2, Gala Kumar-B11780
In-Reply-To: <2D2A6B88-DA17-467D-BB43-919C1CAAB894@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Tuesday, October 19, 2010 21:19 PM
> To: Zang Roy-R61911
> Cc: linux-mtd@lists.infradead.org; Wood Scott-B07421;
dedekind1@gmail.com; Lan
> Chunhe-B25806; linuxppc-dev@ozlabs.org; akpm@linux-foundation.org;
> dwmw2@infradead.org; Gala Kumar-B11780
> Subject: Re: [PATCH 1/2] P4080/eLBC: Make Freescale elbc interrupt
common to
> elbc devices
>=20
>=20
> On Oct 18, 2010, at 2:22 AM, Roy Zang wrote:
>=20
> > Move Freescale elbc interrupt from nand dirver to elbc driver.
> > Then all elbc devices can use the interrupt instead of ONLY nand.
> >
> > For former nand driver, it had the two functions:
> >
> > 1. detecting nand flash partitions;
> > 2. registering elbc interrupt.
> >
> > Now, second function is removed to fsl_lbc.c.
> >
> > Signed-off-by: Lan Chunhe-B25806 <b25806@freescale.com>
> > Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> > Reviewed-by: Anton Vorontsov <cbouatmailru@gmail.com>
> > Cc: Wood Scott-B07421 <B07421@freescale.com>
> > ---
>=20
> Roy, this is a nit, but are these really p4080 specific? just
wondering why
> the subject is P4080/eLBC:...
We start these code in P4080 project. Some customer want to track eLBC
error on P4080, but some of the code is limited in nand driver only ...
That is why P4080/eLBC ...
Roy
^ permalink raw reply
* [PATCH v3] add icswx support
From: Tseng-Hui (Frank) Lin @ 2010-10-20 4:02 UTC (permalink / raw)
To: linuxppc-dev; +Cc: tsenglin
icswx is a PowerPC co-processor instruction to send data to a
co-processor. On Book-S processors the LPAR_ID and process ID (PID) of
the owning process are registered in the window context of the
co-processor at initial time. When the icswx instruction is executed,
the L2 generates a cop-reg transaction on PowerBus. The transaction has
no address and the processor does not perform an MMU access to
authenticate the transaction. The coprocessor compares the LPAR_ID and
the PID included in the transaction and the LPAR_ID and PID held in the
window context to determine if the process is authorized to generate the
transaction.
The OS needs to assign a 16-bit PID for the process. This cop-PID needs
to be updated during context switch. The cop-PID needs to be destroyed
when the context is destroyed.
Change log from v2:
- Make the code a CPU feature and return -NODEV if CPU doesn't have
icswx co-processor instruction.
- Change the goto loop in use_cop() into a do-while loop.
- Change context destroy code into a new destroy_context_acop() function
and #define it based on CONFIG_ICSWX.
- Remove mmput() from drop_cop().
- Fix some TAB/space problems.
Signed-off-by: Sonny Rao <sonnyrao@linux.vnet.ibm.com>
Signed-off-by: Tseng-Hui (Frank) Lin <thlin@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/cputable.h | 4 +-
arch/powerpc/include/asm/mmu-hash64.h | 5 ++
arch/powerpc/include/asm/mmu_context.h | 6 ++
arch/powerpc/include/asm/reg.h | 11 +++
arch/powerpc/include/asm/reg_booke.h | 3 -
arch/powerpc/mm/mmu_context_hash64.c | 109
++++++++++++++++++++++++++++++++
arch/powerpc/platforms/Kconfig.cputype | 17 +++++
7 files changed, 151 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h
b/arch/powerpc/include/asm/cputable.h
index 3a40a99..bbb4e2c 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -198,6 +198,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)
+#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0200000000000000)
#ifndef __ASSEMBLY__
@@ -413,7 +414,8 @@ extern const char *powerpc_base_platform;
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
- CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT)
+ CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
+ CPU_FTR_ICSWX)
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index acac35d..6c1ab90 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -423,6 +423,11 @@ typedef struct {
#ifdef CONFIG_PPC_SUBPAGE_PROT
struct subpage_prot_table spt;
#endif /* CONFIG_PPC_SUBPAGE_PROT */
+#ifdef CONFIG_ICSWX
+ unsigned long acop; /* mask of enabled coprocessor types */
+#define HASH64_MAX_PID (0xFFFF)
+ unsigned int acop_pid; /* pid value used with coprocessors */
+#endif /* CONFIG_ICSWX */
} mm_context_t;
diff --git a/arch/powerpc/include/asm/mmu_context.h
b/arch/powerpc/include/asm/mmu_context.h
index 81fb412..88118de 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -80,6 +80,12 @@ static inline void switch_mm(struct mm_struct *prev,
struct mm_struct *next,
#define deactivate_mm(tsk,mm) do { } while (0)
+#ifdef CONFIG_ICSWX
+extern void switch_cop(struct mm_struct *next);
+extern int use_cop(unsigned long acop, struct mm_struct *mm);
+extern void drop_cop(unsigned long acop, struct mm_struct *mm);
+#endif /* CONFIG_ICSWX */
+
/*
* After we have set current->mm to a new value, this activates
* the context for the new mm so we see the new mappings.
diff --git a/arch/powerpc/include/asm/reg.h
b/arch/powerpc/include/asm/reg.h
index ff0005eec..b86d876 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -170,8 +170,19 @@
#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control
*/
/* Special Purpose Registers (SPRNs)*/
+
+#ifdef CONFIG_40x
+#define SPRN_PID 0x3B1 /* Process ID */
+#else
+#define SPRN_PID 0x030 /* Process ID */
+#ifdef CONFIG_BOOKE
+#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
+#endif
+#endif
+
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DSCR 0x11
+#define SPRN_ACOP 0x1F /* Available Coprocessor Register */
#define SPRN_CTRLF 0x088
#define SPRN_CTRLT 0x098
#define CTRL_CT 0xc0000000 /* current thread */
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 667a498..5b0c781 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -150,8 +150,6 @@
* or IBM 40x.
*/
#ifdef CONFIG_BOOKE
-#define SPRN_PID 0x030 /* Process ID */
-#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
#define SPRN_DEAR 0x03D /* Data Error Address Register */
@@ -168,7 +166,6 @@
#define SPRN_TCR 0x154 /* Timer Control Register */
#endif /* Book E */
#ifdef CONFIG_40x
-#define SPRN_PID 0x3B1 /* Process ID */
#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
diff --git a/arch/powerpc/mm/mmu_context_hash64.c
b/arch/powerpc/mm/mmu_context_hash64.c
index 2535828..6ef6ce2 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -18,6 +18,7 @@
#include <linux/mm.h>
#include <linux/spinlock.h>
#include <linux/idr.h>
+#include <linux/percpu.h>
#include <linux/module.h>
#include <linux/gfp.h>
@@ -26,6 +27,113 @@
static DEFINE_SPINLOCK(mmu_context_lock);
static DEFINE_IDA(mmu_context_ida);
+#ifdef CONFIG_ICSWX
+static DEFINE_SPINLOCK(mmu_context_acop_lock);
+static DEFINE_IDA(cop_ida);
+
+/* Lazy switch the ACOP register */
+static DEFINE_PER_CPU(unsigned long, acop_reg);
+
+void switch_cop(struct mm_struct *next)
+{
+ if (!cpu_has_feature(CPU_FTR_ICSWX))
+ return;
+
+ mtspr(SPRN_PID, next->context.acop_pid);
+ if (next->context.acop_pid &&
+ __get_cpu_var(acop_reg) != next->context.acop) {
+ mtspr(SPRN_ACOP, next->context.acop);
+ __get_cpu_var(acop_reg) = next->context.acop;
+ }
+}
+EXPORT_SYMBOL(switch_cop);
+
+int use_cop(unsigned long acop, struct mm_struct *mm)
+{
+ int acop_pid;
+ int err;
+
+ if (!cpu_has_feature(CPU_FTR_ICSWX))
+ return -ENODEV;
+
+ if (!mm)
+ return -EINVAL;
+
+ if (!mm->context.acop_pid) {
+ if (!ida_pre_get(&cop_ida, GFP_KERNEL))
+ return -ENOMEM;
+ do {
+ spin_lock(&mmu_context_acop_lock);
+ err = ida_get_new_above(&cop_ida, 1, &acop_pid);
+ spin_unlock(&mmu_context_acop_lock);
+ } while (err == -EAGAIN);
+
+ if (err)
+ return err;
+
+ if (acop_pid > HASH64_MAX_PID) {
+ spin_lock(&mmu_context_acop_lock);
+ ida_remove(&cop_ida, acop_pid);
+ spin_unlock(&mmu_context_acop_lock);
+ return -EBUSY;
+ }
+ mm->context.acop_pid = acop_pid;
+ if (mm == current->active_mm)
+ mtspr(SPRN_PID, mm->context.acop_pid);
+ }
+ spin_lock(&mmu_context_acop_lock);
+ mm->context.acop |= acop;
+ spin_unlock(&mmu_context_acop_lock);
+
+ get_cpu_var(acop_reg) = mm->context.acop;
+ if (mm == current->active_mm)
+ mtspr(SPRN_ACOP, mm->context.acop);
+ put_cpu_var(acop_reg);
+
+ return mm->context.acop_pid;
+}
+EXPORT_SYMBOL(use_cop);
+
+void drop_cop(unsigned long acop, struct mm_struct *mm)
+{
+ if (!cpu_has_feature(CPU_FTR_ICSWX))
+ return;
+
+ if (WARN_ON(!mm))
+ return;
+
+ spin_lock(&mmu_context_acop_lock);
+ mm->context.acop &= ~acop;
+ spin_unlock(&mmu_context_acop_lock);
+ if (!mm->context.acop) {
+ spin_lock(&mmu_context_acop_lock);
+ ida_remove(&cop_ida, mm->context.acop_pid);
+ spin_unlock(&mmu_context_acop_lock);
+ mm->context.acop_pid = 0;
+ if (mm == current->active_mm)
+ mtspr(SPRN_PID, mm->context.acop_pid);
+ } else {
+ get_cpu_var(acop_reg) = mm->context.acop;
+ if (mm == current->active_mm)
+ mtspr(SPRN_ACOP, mm->context.acop);
+ put_cpu_var(acop_reg);
+ }
+}
+EXPORT_SYMBOL(drop_cop);
+
+static void destroy_context_acop(struct mm_struct *mm)
+{
+ if (mm->context.acop_pid) {
+ spin_lock(&mmu_context_acop_lock);
+ ida_remove(&cop_ida, mm->context.acop_pid);
+ spin_unlock(&mmu_context_acop_lock);
+ }
+}
+
+#else
+#define destroy_context_acop(mm)
+#endif /* CONFIG_ICSWX */
+
/*
* The proto-VSID space has 2^35 - 1 segments available for user
mappings.
* Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
@@ -93,6 +201,7 @@ EXPORT_SYMBOL_GPL(__destroy_context);
void destroy_context(struct mm_struct *mm)
{
+ destroy_context_acop(mm);
__destroy_context(mm->context.id);
subpage_prot_free(mm);
mm->context.id = NO_CONTEXT;
diff --git a/arch/powerpc/platforms/Kconfig.cputype
b/arch/powerpc/platforms/Kconfig.cputype
index d361f81..7678e29 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -220,6 +220,23 @@ config VSX
If in doubt, say Y here.
+config ICSWX
+ bool "Support for PowerPC icswx co-processor instruction"
+ depends on POWER4
+ default n
+ ---help---
+
+ Enabling this option to turn on the PowerPC icswx co-processor
+ instruction support for POWER7 or newer processors.
+ This option is only useful if you have a processor that supports
+ icswx co-processor instruction. It does not have any effect on
+ processors without icswx co-processor instruction.
+
+ This support slightly increases kernel memory usage.
+
+ Say N if you do not have a PowerPC processor supporting icswx
+ instruction and a PowerPC co-processor.
+
config SPE
bool "SPE Support"
depends on E200 || (E500 && !PPC_E500MC)
^ permalink raw reply related
* Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
From: pacman @ 2010-10-20 3:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Mel Gorman, linux-kernel, linux-mm, Andrew Morton, linuxppc-dev
In-Reply-To: <1287522168.2198.5.camel@pasglop>
Benjamin Herrenschmidt writes:
>
> On Tue, 2010-10-19 at 22:47 +0200, Segher Boessenkool wrote:
> >
> > It looks like it is the frame counter in an USB OHCI HCCA.
> > 16-bit, 1kHz update, offset x'80 in a page.
> >
> > So either the kernel forgot to call quiesce on it, or the firmware
> > doesn't implement that, or the firmware messed up some other way.
>
> I vote for the FW being on crack. Wouldn't be the first time with
> Pegasos.
>
> It's an OHCI or an UHCI in there ?
There's one of each... UHCI on the motherboard, OHCI on a card in a PCI
expansion slot. They shipped the ODW with the extra controller on an
expansion card since the on-board UHCI doesn't do USB2.0.
And that OHCI controller does appear to be the culprit. The 2 affected
addresses tick at 1000Hz until ohci-hcd is modprobe'd, then they stop.
I think the mm people can consider this closed. 6dda9d55 didn't do anything
but expose a problem which has been here all along. Will drop them from Cc
list in any further messages.
>
> Can you try in prom_init.c changing the prom_close_stdin() function to
> also close "stdout" ?
>
> if (prom_getprop(_prom->chosen, "stdin", &val, sizeof(val)) > 0)
> call_prom("close", 1, 0, val);
> + if (prom_getprop(_prom->chosen, "stdout", &val, sizeof(val)) > 0)
> + call_prom("close", 1, 0, val);
>
> See if that makes a difference ?
Huge difference. With no stdout to print to, the kernel seems to freeze up.
Or at least it loses the console. The last message it prints is "Device tree
struct 0x00933000 -> 0x00957000" then there's just nothing. I waited a while
for the console to come on but it didn't.
The diff fragment above applied inside prom_close_stdin, but there are some
prom_printf calls after prom_close_stdin. Calling prom_printf after closing
stdout sounds like it could be bad. If I moved it down below all the
prom_printf's, it would be after the "quiesce" call. Would that be acceptable
(or even interesting as an experiment)? Does a close need a quiesce after it?
--
Alan Curry
^ permalink raw reply
* Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
From: Benjamin Herrenschmidt @ 2010-10-19 21:02 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Mel Gorman, linux-kernel, linux-mm, pacman, Andrew Morton,
linuxppc-dev
In-Reply-To: <56111.84.105.60.153.1287521237.squirrel@gate.crashing.org>
On Tue, 2010-10-19 at 22:47 +0200, Segher Boessenkool wrote:
>
> It looks like it is the frame counter in an USB OHCI HCCA.
> 16-bit, 1kHz update, offset x'80 in a page.
>
> So either the kernel forgot to call quiesce on it, or the firmware
> doesn't implement that, or the firmware messed up some other way.
I vote for the FW being on crack. Wouldn't be the first time with
Pegasos.
It's an OHCI or an UHCI in there ?
Can you try in prom_init.c changing the prom_close_stdin() function to
also close "stdout" ?
if (prom_getprop(_prom->chosen, "stdin", &val, sizeof(val)) > 0)
call_prom("close", 1, 0, val);
+ if (prom_getprop(_prom->chosen, "stdout", &val, sizeof(val)) > 0)
+ call_prom("close", 1, 0, val);
See if that makes a difference ?
Last option would be to manually turn the thing off with MMIO in yet-another
pegasos workaround in prom_init.c.
Cheers,
Ben.
^ permalink raw reply
* Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
From: Benjamin Herrenschmidt @ 2010-10-19 20:58 UTC (permalink / raw)
To: pacman; +Cc: Mel Gorman, linux-mm, Andrew Morton, linuxppc-dev, linux-kernel
In-Reply-To: <20101019181021.22456.qmail@kosh.dhis.org>
On Tue, 2010-10-19 at 13:10 -0500, pacman@kosh.dhis.org wrote:
>
> So what type of driver, firmware, or hardware bug puts a 16-bit 1000Hz
> timer
> in memory, and does it in little-endian instead of the CPU's native
> byte
> order? And why does it stop doing it some time during the early init
> scripts,
> shortly after the root filesystem fsck?
>
> I have not yet attempted to repeat the experiment. If it is
> repeatable, I'll
> probe more deeply into those init scripts later. I'm looking hard at
> /etc/rcS.d/S11hwclock.sh
Stinks of USB...
Ben.
^ permalink raw reply
* Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
From: Segher Boessenkool @ 2010-10-19 20:47 UTC (permalink / raw)
To: pacman; +Cc: Mel Gorman, linux-kernel, linux-mm, Andrew Morton, linuxppc-dev
In-Reply-To: <20101019181021.22456.qmail@kosh.dhis.org>
> I made a new discovery.
And this nails it :-)
> So then I ran
> dd if=/dev/mem bs=4 count=1 skip=$((0xfc5c080/4)) | od -t x4
> a few times very fast, plucking the first affected word directly out of
> memory by its physical address. The result:
>
> The low 16 bits are always zero as before. The high 16 bits are a counter,
> being incremented at about 1000Hz (as close as I could measure with a
> crude
> shell script. 1024Hz would also be within the margin of error). And it's
> little-endian.
> So what type of driver, firmware, or hardware bug puts a 16-bit 1000Hz
> timer
> in memory, and does it in little-endian instead of the CPU's native byte
> order? And why does it stop doing it some time during the early init
> scripts,
> shortly after the root filesystem fsck?
It looks like it is the frame counter in an USB OHCI HCCA.
16-bit, 1kHz update, offset x'80 in a page.
So either the kernel forgot to call quiesce on it, or the firmware
doesn't implement that, or the firmware messed up some other way.
Segher
^ permalink raw reply
* Re: PROBLEM: memory corrupting bug, bisected to 6dda9d55
From: pacman @ 2010-10-19 18:10 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Mel Gorman, linux-mm, Andrew Morton, linuxppc-dev, linux-kernel
In-Reply-To: <1287483410.2341.66.camel@pasglop>
Benjamin Herrenschmidt writes:
> >
> > I thought of that, but as far as I can tell, this CPU doesn't have DABR.
>
> AFAIK, the 7447 is just a derivative of the 7450 design which -does-
> have a DABR ... Unless it's broken :-)
Hmm. gdb resorts to single-stepping when I set a watchpoint while debugging
some userspace program, which I assumed was caused by lack of hardware
watchpoint support. But that's not important right now.
I made a new discovery. During a test boot while looking at the usual symptom
of a corrupted page cache, I run md5sum /sbin/e2fsck twice and got 2
different results, neither one of them correct. The third time, yet another
different result. A few dozen more times, a few dozen more unique results. I
had somehow managed to get a usable interactive shell while corruption was
ongoing.
So then I ran
dd if=/dev/mem bs=4 count=1 skip=$((0xfc5c080/4)) | od -t x4
a few times very fast, plucking the first affected word directly out of
memory by its physical address. The result:
The low 16 bits are always zero as before. The high 16 bits are a counter,
being incremented at about 1000Hz (as close as I could measure with a crude
shell script. 1024Hz would also be within the margin of error). And it's
little-endian.
While I was watching this happen, there were only 5 or 6 userspace processes
running, and 3 of them were shells. So I doubt that anything in userspace was
doing it. It went on for a few minutes before I exited the interactive shell
and allowed the boot to continue, while keeping an extra shell running on
tty2 to continue making observations. It stopped incrementing almost
immediately.
So what type of driver, firmware, or hardware bug puts a 16-bit 1000Hz timer
in memory, and does it in little-endian instead of the CPU's native byte
order? And why does it stop doing it some time during the early init scripts,
shortly after the root filesystem fsck?
I have not yet attempted to repeat the experiment. If it is repeatable, I'll
probe more deeply into those init scripts later. I'm looking hard at
/etc/rcS.d/S11hwclock.sh
--
Alan Curry
^ permalink raw reply
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