* [PATCH 4/5] powerpc/5200: dts: Change combatible strings on localbus
From: John Bonesio @ 2010-11-17 23:28 UTC (permalink / raw)
To: linux-kernel; +Cc: glikely, jdl, linuxppc-dev, devicetree-discuss, david
In-Reply-To: <20101117232520.25947.37475.stgit@riker>
This patch changes some incorrect compatible strings on the local plus bus node
in dts files for MPC5200b based systems.
Signed-off-by: John Bonesio <bones@secretlab.ca>
---
arch/powerpc/boot/dts/cm5200.dts | 2 +-
arch/powerpc/boot/dts/digsy_mtc.dts | 2 +-
arch/powerpc/boot/dts/media5200.dts | 2 +-
arch/powerpc/boot/dts/motionpro.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index d549897..22f7233 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -219,7 +219,7 @@
};
localbus {
- compatible = "fsl,mpc5200b-lpb","simple-bus";
+ compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xfc000000 0x2000000>;
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index f0592de..3147b98 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -218,7 +218,7 @@
};
localbus {
- compatible = "fsl,mpc5200b-lpb","simple-bus";
+ compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xff000000 0x1000000>;
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index e027f45..861f09f 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -270,7 +270,7 @@
};
localbus {
- compatible = "fsl,mpc5200b-lpb","simple-bus";
+ compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 3ab4666..97cb085 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -236,7 +236,7 @@
};
localbus {
- compatible = "fsl,mpc5200b-lpb","simple-bus";
+ compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xff000000 0x01000000
^ permalink raw reply related
* [PATCH 5/5] powerpc/5200: dts: refactor dts files
From: John Bonesio @ 2010-11-17 23:28 UTC (permalink / raw)
To: linux-kernel; +Cc: glikely, jdl, linuxppc-dev, devicetree-discuss, david
In-Reply-To: <20101117232520.25947.37475.stgit@riker>
This patch creates mpc5200b.dtsi containing the information for the MPC5200b
SoC then modifies all of the dts files for MPC5200b based systems to use
mpc5200b.dtsi.
Signed-off-by: John Bonesio <bones@secretlab.ca>
---
arch/powerpc/boot/dts/cm5200.dts | 196 +++----------------------
arch/powerpc/boot/dts/digsy_mtc.dts | 173 +++-------------------
arch/powerpc/boot/dts/lite5200b.dts | 229 ++---------------------------
arch/powerpc/boot/dts/media5200.dts | 212 +++------------------------
arch/powerpc/boot/dts/motionpro.dts | 190 +++---------------------
arch/powerpc/boot/dts/mpc5200b.dtsi | 276 +++++++++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mucmc52.dts | 176 ++++++----------------
arch/powerpc/boot/dts/pcm030.dts | 193 ++----------------------
arch/powerpc/boot/dts/pcm032.dts | 197 +------------------------
arch/powerpc/boot/dts/uc101.dts | 162 ++++-----------------
10 files changed, 486 insertions(+), 1518 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mpc5200b.dtsi
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 22f7233..c6d5d46 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -10,226 +10,78 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "schindler,cm5200";
compatible = "schindler,cm5200";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x04000000>; // 64MB
- };
soc5200@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- reg = <0xf0000000 0x00000100>;
- bus-frequency = <0>; // from bootloader
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
-
timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
fsl,has-wdt;
};
- timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
- };
-
- timer@620 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
- };
-
- timer@630 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x630 0x10>;
- interrupts = <1 12 0>;
- };
-
- timer@640 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x640 0x10>;
- interrupts = <1 13 0>;
- };
-
- timer@650 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x650 0x10>;
- interrupts = <1 14 0>;
- };
-
- timer@660 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x660 0x10>;
- interrupts = <1 15 0>;
- };
-
- timer@670 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x670 0x10>;
- interrupts = <1 16 0>;
- };
-
- rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
- reg = <0x800 0x100>;
- interrupts = <1 5 0 1 6 0>;
- };
-
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <0xf00 0x20>;
- interrupts = <2 13 0 2 14 0>;
- };
-
- usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <0x1000 0xff>;
- interrupts = <2 6 0>;
- };
-
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
+ can@900 {
+ status = "disabled";
};
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
+ can@980 {
+ status = "disabled";
};
psc@2000 { // PSC1
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2000 0x100>;
- interrupts = <2 1 0>;
};
psc@2200 { // PSC2
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2200 0x100>;
- interrupts = <2 2 0>;
};
psc@2400 { // PSC3
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2400 0x100>;
- interrupts = <2 3 0>;
};
- psc@2c00 { // PSC6
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2c00 0x100>;
- interrupts = <2 4 0>;
+ psc@2600 { // PSC4
+ status = "disabled";
};
- ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
+ psc@2800 { // PSC5
+ status = "disabled";
};
- mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
+ psc@2c00 { // PSC6
+ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ };
+ mdio@3000 {
phy0: ethernet-phy@0 {
reg = <0>;
};
};
- i2c@3d40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d40 0x40>;
- interrupts = <2 16 0>;
+ ata@3a00 {
+ status = "disabled";
};
- sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
- reg = <0x8000 0x4000>;
+ i2c@3d00 {
+ status = "disabled";
};
+
};
- localbus {
- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0xfc000000 0x2000000>;
+ pci@f0000d00 {
+ status = "disabled";
+ };
+ localbus {
// 16-bit flash device at LocalPlus Bus CS0
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x2000000>;
bank-width = <2>;
device-width = <2>;
+ #size-cells = <1>;
+ #address-cells = <1>;
};
};
};
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index 3147b98..a12b587 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -11,195 +11,64 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "intercontrol,digsy-mtc";
compatible = "intercontrol,digsy-mtc";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
memory {
- device_type = "memory";
reg = <0x00000000 0x02000000>; // 32MB
};
soc5200@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- reg = <0xf0000000 0x00000100>;
- bus-frequency = <0>; // from bootloader
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
-
timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
fsl,has-wdt;
};
- timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
- };
-
- timer@620 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
- };
-
- timer@630 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x630 0x10>;
- interrupts = <1 12 0>;
- };
-
- timer@640 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x640 0x10>;
- interrupts = <1 13 0>;
- };
-
- timer@650 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x650 0x10>;
- interrupts = <1 14 0>;
+ rtc@800 {
+ status = "disabled";
};
- timer@660 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x660 0x10>;
- interrupts = <1 15 0>;
+ can@900 {
+ status = "disabled";
};
- timer@670 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x670 0x10>;
- interrupts = <1 16 0>;
+ can@980 {
+ status = "disabled";
};
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
+ psc@2000 { // PSC1
+ status = "disabled";
};
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
- gpio-controller;
- #gpio-cells = <2>;
+ psc@2200 { // PSC2
+ status = "disabled";
};
- spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <0xf00 0x20>;
- interrupts = <2 13 0 2 14 0>;
- };
-
- usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <0x1000 0xff>;
- interrupts = <2 6 0>;
- };
-
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
- };
-
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
+ psc@2400 { // PSC3
+ status = "disabled";
};
psc@2600 { // PSC4
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2600 0x100>;
- interrupts = <2 11 0>;
};
psc@2800 { // PSC5
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2800 0x100>;
- interrupts = <2 12 0>;
};
- ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
+ psc@2c00 { // PSC6
+ status = "disabled";
};
mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
-
phy0: ethernet-phy@0 {
reg = <0>;
};
};
- ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <0x3a00 0x100>;
- interrupts = <2 7 0>;
- };
-
i2c@3d00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d00 0x40>;
- interrupts = <2 15 0>;
-
rtc@50 {
compatible = "at,24c08";
reg = <0x50>;
@@ -211,16 +80,16 @@
};
};
- sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
- reg = <0x8000 0x4000>;
+ i2c@3d40 {
+ status = "disabled";
};
};
+ pci@f0000d00 {
+ status = "disabled";
+ };
+
localbus {
- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
ranges = <0 0 0xff000000 0x1000000>;
// 16-bit flash device at LocalPlus Bus CS0
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index c0a4e45..8d15dfd 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -10,253 +10,71 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "fsl,lite5200b";
compatible = "fsl,lite5200b";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
memory {
- device_type = "memory";
reg = <0x00000000 0x10000000>; // 256MB
};
soc5200@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- reg = <0xf0000000 0x00000100>;
- bus-frequency = <0>; // from bootloader
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
-
timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
fsl,has-wdt;
};
- timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
- };
-
- timer@620 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
- };
-
- timer@630 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x630 0x10>;
- interrupts = <1 12 0>;
- };
-
- timer@640 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x640 0x10>;
- interrupts = <1 13 0>;
- };
-
- timer@650 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x650 0x10>;
- interrupts = <1 14 0>;
- };
-
- timer@660 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x660 0x10>;
- interrupts = <1 15 0>;
- };
-
- timer@670 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x670 0x10>;
- interrupts = <1 16 0>;
- };
-
- rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
- reg = <0x800 0x100>;
- interrupts = <1 5 0 1 6 0>;
- };
-
- can@900 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 17 0>;
- reg = <0x900 0x80>;
- };
-
- can@980 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 18 0>;
- reg = <0x980 0x80>;
- };
-
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
- gpio-controller;
- #gpio-cells = <2>;
+ psc@2000 { // PSC1
+ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ cell-index = <0>;
};
- spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <0xf00 0x20>;
- interrupts = <2 13 0 2 14 0>;
+ psc@2200 { // PSC2
+ status = "disabled";
};
- usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <0x1000 0xff>;
- interrupts = <2 6 0>;
+ psc@2400 { // PSC3
+ status = "disabled";
};
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
+ psc@2600 { // PSC4
+ status = "disabled";
};
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
+ psc@2800 { // PSC5
+ status = "disabled";
};
- psc@2000 { // PSC1
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2000 0x100>;
- interrupts = <2 1 0>;
+ psc@2c00 { // PSC6
+ status = "disabled";
};
// PSC2 in ac97 mode example
//ac97@2200 { // PSC2
// compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
// cell-index = <1>;
- // reg = <0x2200 0x100>;
- // interrupts = <2 2 0>;
//};
// PSC3 in CODEC mode example
//i2s@2400 { // PSC3
// compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
// cell-index = <2>;
- // reg = <0x2400 0x100>;
- // interrupts = <2 3 0>;
- //};
-
- // PSC4 in uart mode example
- //serial@2600 { // PSC4
- // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- // reg = <0x2600 0x100>;
- // interrupts = <2 11 0>;
- //};
-
- // PSC5 in uart mode example
- //serial@2800 { // PSC5
- // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- // reg = <0x2800 0x100>;
- // interrupts = <2 12 0>;
//};
// PSC6 in spi mode example
//spi@2c00 { // PSC6
// compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
// cell-index = <5>;
- // reg = <0x2c00 0x100>;
- // interrupts = <2 4 0>;
//};
- ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
- };
-
mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
-
phy0: ethernet-phy@0 {
reg = <0>;
};
};
- ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <0x3a00 0x100>;
- interrupts = <2 7 0>;
- };
-
- i2c@3d00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d00 0x40>;
- interrupts = <2 15 0>;
- };
-
i2c@3d40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d40 0x40>;
- interrupts = <2 16 0>;
-
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
@@ -270,12 +88,6 @@
};
pci@f0000d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
- reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -295,19 +107,14 @@
};
localbus {
- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
-
- #address-cells = <2>;
- #size-cells = <1>;
-
ranges = <0 0 0xfe000000 0x02000000>;
flash@0,0 {
compatible = "cfi-flash";
- reg = <0 0 0x02000000>;
- bank-width = <1>;
- #size-cells = <1>;
- #address-cells = <1>;
+ reg = <0 0 0x02000000>;
+ bank-width = <1>;
+ #size-cells = <1>;
+ #address-cells = <1>;
partition@0 {
label = "kernel";
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index 861f09f..84558f8 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -11,14 +11,11 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "fsl,media5200";
compatible = "fsl,media5200";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
aliases {
console = &console;
@@ -30,16 +27,7 @@
};
cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
bus-frequency = <132000000>; // 132 MHz
clock-frequency = <396000000>; // 396 MHz
@@ -47,203 +35,53 @@
};
memory {
- device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB RAM
};
- soc@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- reg = <0xf0000000 0x00000100>;
+ soc5200@f0000000 {
bus-frequency = <132000000>;// 132 MHz
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
fsl,has-wdt;
};
- timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
- };
-
- timer@620 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
- };
-
- timer@630 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x630 0x10>;
- interrupts = <1 12 0>;
- };
-
- timer@640 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x640 0x10>;
- interrupts = <1 13 0>;
+ psc@2000 { // PSC1
+ status = "disabled";
};
- timer@650 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x650 0x10>;
- interrupts = <1 14 0>;
+ psc@2200 { // PSC2
+ status = "disabled";
};
- timer@660 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x660 0x10>;
- interrupts = <1 15 0>;
+ psc@2400 { // PSC3
+ status = "disabled";
};
- timer@670 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x670 0x10>;
- interrupts = <1 16 0>;
+ psc@2600 { // PSC4
+ status = "disabled";
};
- rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
- reg = <0x800 0x100>;
- interrupts = <1 5 0 1 6 0>;
- };
-
- can@900 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 17 0>;
- reg = <0x900 0x80>;
- };
-
- can@980 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 18 0>;
- reg = <0x980 0x80>;
- };
-
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <0xf00 0x20>;
- interrupts = <2 13 0 2 14 0>;
- };
-
- usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <0x1000 0x100>;
- interrupts = <2 6 0>;
- };
-
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
- };
-
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
+ psc@2800 { // PSC5
+ status = "disabled";
};
// PSC6 in uart mode
console: psc@2c00 { // PSC6
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2c00 0x100>;
- interrupts = <2 4 0>;
- };
-
- eth0: ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
};
mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
-
phy0: ethernet-phy@0 {
reg = <0>;
};
};
- ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <0x3a00 0x100>;
- interrupts = <2 7 0>;
- };
-
- i2c@3d00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d00 0x40>;
- interrupts = <2 15 0>;
- };
-
- i2c@3d40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d40 0x40>;
- interrupts = <2 16 0>;
- };
-
- sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
- reg = <0x8000 0x4000>;
+ usb@1000 {
+ reg = <0x1000 0x100>;
};
};
pci@f0000d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
- reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
0xc000 0 0 2 &media5200_fpga 0 3
@@ -260,37 +98,29 @@
0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 10 0>;
- interrupt-parent = <&mpc5200_pic>;
- bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
+ interrupt-parent = <&mpc5200_pic>;
};
localbus {
- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
-
ranges = < 0 0 0xfc000000 0x02000000
1 0 0xfe000000 0x02000000
2 0 0xf0010000 0x00010000
3 0 0xf0020000 0x00010000 >;
-
flash@0,0 {
compatible = "amd,am29lv28ml", "cfi-flash";
- reg = <0 0x0 0x2000000>; // 32 MB
- bank-width = <4>; // Width in bytes of the flash bank
- device-width = <2>; // Two devices on each bank
+ reg = <0 0x0 0x2000000>; // 32 MB
+ bank-width = <4>; // Width in bytes of the flash bank
+ device-width = <2>; // Two devices on each bank
};
flash@1,0 {
compatible = "amd,am29lv28ml", "cfi-flash";
- reg = <1 0 0x2000000>; // 32 MB
- bank-width = <4>; // Width in bytes of the flash bank
- device-width = <2>; // Two devices on each bank
+ reg = <1 0 0x2000000>; // 32 MB
+ bank-width = <4>; // Width in bytes of the flash bank
+ device-width = <2>; // Two devices on each bank
};
media5200_fpga: fpga@2,0 {
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 97cb085..2276ccd 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -10,219 +10,69 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "promess,motionpro";
compatible = "promess,motionpro";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x04000000>; // 64MB
- };
soc5200@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- reg = <0xf0000000 0x00000100>;
- bus-frequency = <0>; // from bootloader
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
-
timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
fsl,has-wdt;
};
- timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
- };
-
- timer@620 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
- };
-
- timer@630 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x630 0x10>;
- interrupts = <1 12 0>;
- };
-
- timer@640 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x640 0x10>;
- interrupts = <1 13 0>;
- };
-
- timer@650 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x650 0x10>;
- interrupts = <1 14 0>;
- };
-
timer@660 { // Motion-PRO status LED
compatible = "promess,motionpro-led";
label = "motionpro-statusled";
- reg = <0x660 0x10>;
- interrupts = <1 15 0>;
blink-delay = <100>; // 100 msec
};
timer@670 { // Motion-PRO ready LED
compatible = "promess,motionpro-led";
label = "motionpro-readyled";
- reg = <0x670 0x10>;
- interrupts = <1 16 0>;
};
- rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
- reg = <0x800 0x100>;
- interrupts = <1 5 0 1 6 0>;
- };
-
- can@980 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 18 0>;
- reg = <0x980 0x80>;
- };
-
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <0xf00 0x20>;
- interrupts = <2 13 0 2 14 0>;
- };
-
- usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <0x1000 0xff>;
- interrupts = <2 6 0>;
- };
-
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
- };
-
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
+ can@900 {
+ status = "disabled";
};
psc@2000 { // PSC1
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2000 0x100>;
- interrupts = <2 1 0>;
};
// PSC2 in spi master mode
psc@2200 { // PSC2
compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
cell-index = <1>;
- reg = <0x2200 0x100>;
- interrupts = <2 2 0>;
};
- // PSC5 in uart mode
+ psc@2400 { // PSC3
+ status = "disabled";
+ };
+
+ psc@2600 { // PSC4
+ status = "disabled";
+ };
+
psc@2800 { // PSC5
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2800 0x100>;
- interrupts = <2 12 0>;
};
- ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
+ psc@2c00 { // PSC6
+ status = "disabled";
};
mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
-
phy0: ethernet-phy@2 {
reg = <2>;
};
};
- ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <0x3a00 0x100>;
- interrupts = <2 7 0>;
+ i2c@3d00 {
+ status = "disabled";
};
i2c@3d40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d40 0x40>;
- interrupts = <2 16 0>;
-
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
@@ -235,10 +85,11 @@
};
};
+ pci@f0000d00 {
+ status = "disabled";
+ };
+
localbus {
- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
ranges = <0 0 0xff000000 0x01000000
1 0 0x50000000 0x00010000
2 0 0x50010000 0x00010000
@@ -277,6 +128,9 @@
reg = <0 0 0x01000000>;
bank-width = <2>;
device-width = <2>;
+ #size-cells = <1>;
+ #address-cells = <1>;
};
+
};
};
diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi
new file mode 100644
index 0000000..62cb4c9
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5200b.dtsi
@@ -0,0 +1,276 @@
+/*
+ * base MPC5200b Device Tree Source
+ *
+ * Copyright (C) 2010 SecretLab
+ * Grant Likely <grant@secretlab.ca>
+ * John Bonesio <bones@secretlab.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "fsl,mpc5200b";
+ compatible = "fsl,mpc5200b";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&mpc5200_pic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ powerpc: PowerPC,5200@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>; // from bootloader
+ bus-frequency = <0>; // from bootloader
+ clock-frequency = <0>; // from bootloader
+ };
+ };
+
+ memory: memory {
+ device_type = "memory";
+ reg = <0x00000000 0x04000000>; // 64MB
+ };
+
+ soc: soc5200@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc5200b-immr";
+ ranges = <0 0xf0000000 0x0000c000>;
+ reg = <0xf0000000 0x00000100>;
+ bus-frequency = <0>; // from bootloader
+ system-frequency = <0>; // from bootloader
+
+ cdm@200 {
+ compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+ reg = <0x200 0x38>;
+ };
+
+ mpc5200_pic: interrupt-controller@500 {
+ // 5200 interrupts are encoded into two levels;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+ reg = <0x500 0x80>;
+ };
+
+ timer@600 { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x600 0x10>;
+ interrupts = <1 9 0>;
+ };
+
+ timer@610 { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x610 0x10>;
+ interrupts = <1 10 0>;
+ };
+
+ timer@620 { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x620 0x10>;
+ interrupts = <1 11 0>;
+ };
+
+ timer@630 { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x630 0x10>;
+ interrupts = <1 12 0>;
+ };
+
+ timer@640 { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x640 0x10>;
+ interrupts = <1 13 0>;
+ };
+
+ timer@650 { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x650 0x10>;
+ interrupts = <1 14 0>;
+ };
+
+ timer@660 { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x660 0x10>;
+ interrupts = <1 15 0>;
+ };
+
+ timer@670 { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <0x670 0x10>;
+ interrupts = <1 16 0>;
+ };
+
+ rtc@800 { // Real time clock
+ compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
+ reg = <0x800 0x100>;
+ interrupts = <1 5 0 1 6 0>;
+ };
+
+ can@900 {
+ compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
+ interrupts = <2 17 0>;
+ reg = <0x900 0x80>;
+ };
+
+ can@980 {
+ compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
+ interrupts = <2 18 0>;
+ reg = <0x980 0x80>;
+ };
+
+ gpio_simple: gpio@b00 {
+ compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+ reg = <0xb00 0x40>;
+ interrupts = <1 7 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio_wkup: gpio@c00 {
+ compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
+ reg = <0xc00 0x40>;
+ interrupts = <1 8 0 0 3 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ spi@f00 {
+ compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
+ reg = <0xf00 0x20>;
+ interrupts = <2 13 0 2 14 0>;
+ };
+
+ usb: usb@1000 {
+ compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
+ reg = <0x1000 0xff>;
+ interrupts = <2 6 0>;
+ };
+
+ dma-controller@1200 {
+ compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
+ reg = <0x1200 0x80>;
+ interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
+ 3 4 0 3 5 0 3 6 0 3 7 0
+ 3 8 0 3 9 0 3 10 0 3 11 0
+ 3 12 0 3 13 0 3 14 0 3 15 0>;
+ };
+
+ xlb@1f00 {
+ compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+ reg = <0x1f00 0x100>;
+ };
+
+ psc1: psc@2000 { // PSC1
+ compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+ reg = <0x2000 0x100>;
+ interrupts = <2 1 0>;
+ };
+
+ psc2: psc@2200 { // PSC2
+ compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+ reg = <0x2200 0x100>;
+ interrupts = <2 2 0>;
+ };
+
+ psc3: psc@2400 { // PSC3
+ compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+ reg = <0x2400 0x100>;
+ interrupts = <2 3 0>;
+ };
+
+ psc4: psc@2600 { // PSC4
+ compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+ reg = <0x2600 0x100>;
+ interrupts = <2 11 0>;
+ };
+
+ psc5: psc@2800 { // PSC5
+ compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+ reg = <0x2800 0x100>;
+ interrupts = <2 12 0>;
+ };
+
+ psc6: psc@2c00 { // PSC6
+ compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+ reg = <0x2c00 0x100>;
+ interrupts = <2 4 0>;
+ };
+
+ eth0: ethernet@3000 {
+ compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+ reg = <0x3000 0x400>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <2 5 0>;
+ phy-handle = <&phy0>;
+ };
+
+ mdio@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+ reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
+ interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
+ };
+
+ ata@3a00 {
+ compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+ reg = <0x3a00 0x100>;
+ interrupts = <2 7 0>;
+ };
+
+ i2c@3d00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+ reg = <0x3d00 0x40>;
+ interrupts = <2 15 0>;
+ };
+
+ i2c@3d40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+ reg = <0x3d40 0x40>;
+ interrupts = <2 16 0>;
+ };
+
+ sram@8000 {
+ compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+ reg = <0x8000 0x4000>;
+ };
+ };
+
+ pci: pci@f0000d00 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
+ reg = <0xf0000d00 0x100>;
+ // interrupt-map-mask = need to add
+ // interrupt-map = need to add
+ clock-frequency = <0>; // From boot loader
+ interrupts = <2 8 0 2 9 0 2 10 0>;
+ bus-range = <0 0>;
+ // ranges = need to add
+ };
+
+ localbus: localbus {
+ compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xfc000000 0x2000000>;
+ };
+};
diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
index 8dc212d..b369db5 100644
--- a/arch/powerpc/boot/dts/mucmc52.dts
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -11,172 +11,105 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "manroland,mucmc52";
compatible = "manroland,mucmc52";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x04000000>; // 64MB
- };
soc5200@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- reg = <0xf0000000 0x00000100>;
- bus-frequency = <0>; // from bootloader
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
-
gpt0: timer@600 { // GPT 0 in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt1: timer@610 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x630 0x10>;
- interrupts = <1 12 0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
+ timer@640 {
+ status = "disabled";
};
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
- gpio-controller;
- #gpio-cells = <2>;
+ timer@650 {
+ status = "disabled";
};
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
+ timer@660 {
+ status = "disabled";
};
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
+ timer@670 {
+ status = "disabled";
};
- psc@2000 { /* PSC1 in UART mode */
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2000 0x100>;
- interrupts = <2 1 0>;
+ rtc@800 {
+ status = "disabled";
+ };
+
+ can@900 {
+ status = "disabled";
+ };
+
+ can@980 {
+ status = "disabled";
+ };
+
+ spi@f00 {
+ status = "disabled";
+ };
+
+ usb@1000 {
+ status = "disabled";
};
- psc@2200 { /* PSC2 in UART mode */
+ psc@2000 { // PSC1
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2200 0x100>;
- interrupts = <2 2 0>;
};
- psc@2c00 { /* PSC6 in UART mode */
+ psc@2200 { // PSC2
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2c00 0x100>;
- interrupts = <2 4 0>;
};
- ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
+ psc@2400 { // PSC3
+ status = "disabled";
};
- mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
+ psc@2600 { // PSC4
+ status = "disabled";
+ };
+
+ psc@2800 { // PSC5
+ status = "disabled";
+ };
+ psc@2c00 { // PSC6
+ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ };
+
+ mdio@3000 {
phy0: ethernet-phy@0 {
compatible = "intel,lxt971";
reg = <0>;
};
};
- ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <0x3a00 0x100>;
- interrupts = <2 7 0>;
+ i2c@3d00 {
+ status = "disabled";
};
i2c@3d40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d40 0x40>;
- interrupts = <2 16 0>;
hwmon@2c {
compatible = "ad,adm9240";
reg = <0x2c>;
@@ -186,20 +119,9 @@
reg = <0x51>;
};
};
-
- sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
- reg = <0x8000 0x4000>;
- };
};
pci@f0000d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
- reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 */
@@ -208,20 +130,12 @@
0x8000 0 0 3 &mpc5200_pic 0 2 3
0x8000 0 0 4 &mpc5200_pic 0 1 3
>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 10 0>;
- bus-range = <0 0>;
ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
0x02000000 0 0x90000000 0x90000000 0 0x10000000
0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
};
localbus {
- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
-
- #address-cells = <2>;
- #size-cells = <1>;
-
ranges = <0 0 0xff800000 0x00800000
1 0 0x80000000 0x00800000
3 0 0x80000000 0x00800000>;
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index f3e30bb..b2ee689 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -12,244 +12,88 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "phytec,pcm030";
compatible = "phytec,pcm030";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x04000000>; // 64MB
- };
soc5200@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- bus-frequency = <0>; // from bootloader
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
-
- timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
+ timer@600 { // General Purpose Timer
fsl,has-wdt;
};
- timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
- };
-
gpt2: timer@620 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
- reg = <0x630 0x10>;
- interrupts = <1 12 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
- reg = <0x640 0x10>;
- interrupts = <1 13 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
- reg = <0x650 0x10>;
- interrupts = <1 14 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt6: timer@660 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
- reg = <0x660 0x10>;
- interrupts = <1 15 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt7: timer@670 { // General Purpose Timer in GPIO mode
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
- reg = <0x670 0x10>;
- interrupts = <1 16 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
- reg = <0x800 0x100>;
- interrupts = <1 5 0 1 6 0>;
- };
-
- can@900 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 17 0>;
- reg = <0x900 0x80>;
- };
-
- can@980 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 18 0>;
- reg = <0x980 0x80>;
- };
-
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
- spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <0xf00 0x20>;
- interrupts = <2 13 0 2 14 0>;
- };
-
- usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <0x1000 0xff>;
- interrupts = <2 6 0>;
- };
-
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
- };
-
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
- };
-
psc@2000 { /* PSC1 in ac97 mode */
compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
cell-index = <0>;
- reg = <0x2000 0x100>;
- interrupts = <2 1 0>;
};
/* PSC2 port is used by CAN1/2 */
+ psc@2200 {
+ status = "disabled";
+ };
psc@2400 { /* PSC3 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2400 0x100>;
- interrupts = <2 3 0>;
};
/* PSC4 is ??? */
-
+ psc@2600 {
+ status = "disabled";
+ };
+
/* PSC5 is ??? */
+ psc@2800 {
+ status = "disabled";
+ };
psc@2c00 { /* PSC6 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2c00 0x100>;
- interrupts = <2 4 0>;
- };
-
- ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
};
mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
-
phy0: ethernet-phy@0 {
reg = <0>;
};
};
- ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <0x3a00 0x100>;
- interrupts = <2 7 0>;
- };
-
- i2c@3d00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d00 0x40>;
- interrupts = <2 15 0>;
- };
-
i2c@3d40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d40 0x40>;
- interrupts = <2 16 0>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
@@ -267,12 +111,6 @@
};
pci@f0000d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
- reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -283,11 +121,12 @@
0xc800 0 0 2 &mpc5200_pic 1 2 3
0xc800 0 0 3 &mpc5200_pic 1 3 3
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 10 0>;
- bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
};
+
+ localbus {
+ status = "disabled";
+ };
};
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index e0f2702..184e194 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -12,99 +12,37 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "phytec,pcm032";
compatible = "phytec,pcm032";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
memory {
- device_type = "memory";
reg = <0x00000000 0x08000000>; // 128MB
};
soc5200@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- bus-frequency = <0>; // from bootloader
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
-
- timer@600 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
+ timer@600 { // General Purpose Timer
fsl,has-wdt;
};
- timer@610 { // General Purpose Timer
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
- };
-
gpt2: timer@620 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt3: timer@630 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x630 0x10>;
- interrupts = <1 12 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt4: timer@640 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x640 0x10>;
- interrupts = <1 13 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x650 0x10>;
- interrupts = <1 14 0>;
gpio-controller;
#gpio-cells = <2>;
};
@@ -118,138 +56,45 @@
};
gpt7: timer@670 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x670 0x10>;
- interrupts = <1 16 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- rtc@800 { // Real time clock
- compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
- reg = <0x800 0x100>;
- interrupts = <1 5 0 1 6 0>;
- };
-
- can@900 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 17 0>;
- reg = <0x900 0x80>;
- };
-
- can@980 {
- compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
- interrupts = <2 18 0>;
- reg = <0x980 0x80>;
- };
-
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
gpio-controller;
#gpio-cells = <2>;
};
- spi@f00 {
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <0xf00 0x20>;
- interrupts = <2 13 0 2 14 0>;
- };
-
- usb@1000 {
- compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
- reg = <0x1000 0xff>;
- interrupts = <2 6 0>;
- };
-
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
- };
-
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
- };
-
psc@2000 { /* PSC1 is ac97 */
compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
cell-index = <0>;
- reg = <0x2000 0x100>;
- interrupts = <2 1 0>;
};
/* PSC2 port is used by CAN1/2 */
+ psc@2200 {
+ status = "disabled";
+ };
psc@2400 { /* PSC3 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2400 0x100>;
- interrupts = <2 3 0>;
};
/* PSC4 is ??? */
+ psc@2600 {
+ status = "disabled";
+ };
/* PSC5 is ??? */
+ psc@2800 {
+ status = "disabled";
+ };
psc@2c00 { /* PSC6 in UART mode */
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2c00 0x100>;
- interrupts = <2 4 0>;
- };
-
- ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
};
mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
-
phy0: ethernet-phy@0 {
reg = <0>;
};
};
- ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <0x3a00 0x100>;
- interrupts = <2 7 0>;
- };
-
- i2c@3d00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d00 0x40>;
- interrupts = <2 15 0>;
- };
-
i2c@3d40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d40 0x40>;
- interrupts = <2 16 0>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
@@ -259,20 +104,9 @@
reg = <0x52>;
};
};
-
- sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
- reg = <0x8000 0x4000>;
- };
};
pci@f0000d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
- reg = <0xf0000d00 0x100>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -283,20 +117,12 @@
0xc800 0 0 2 &mpc5200_pic 1 2 3
0xc800 0 0 3 &mpc5200_pic 1 3 3
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 10 0>;
- bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
};
localbus {
- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
-
- #address-cells = <2>;
- #size-cells = <1>;
-
ranges = <0 0 0xfe000000 0x02000000
1 0 0xfc000000 0x02000000
2 0 0xfbe00000 0x00200000
@@ -385,4 +211,3 @@
*/
};
};
-
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
index e00441a..49be562 100644
--- a/arch/powerpc/boot/dts/uc101.dts
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -11,79 +11,24 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
/ {
model = "manroland,uc101";
compatible = "manroland,uc101";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&mpc5200_pic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,5200@0 {
- device_type = "cpu";
- reg = <0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <0x4000>; // L1, 16K
- i-cache-size = <0x4000>; // L1, 16K
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x04000000>; // 64MB
- };
soc5200@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc5200b-immr";
- ranges = <0 0xf0000000 0x0000c000>;
- reg = <0xf0000000 0x00000100>;
- bus-frequency = <0>; // from bootloader
- system-frequency = <0>; // from bootloader
-
- cdm@200 {
- compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
- reg = <0x200 0x38>;
- };
-
- mpc5200_pic: interrupt-controller@500 {
- // 5200 interrupts are encoded into two levels;
- interrupt-controller;
- #interrupt-cells = <3>;
- compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
- reg = <0x500 0x80>;
- };
-
gpt0: timer@600 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x600 0x10>;
- interrupts = <1 9 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt1: timer@610 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x610 0x10>;
- interrupts = <1 10 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt2: timer@620 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x620 0x10>;
- interrupts = <1 11 0>;
gpio-controller;
#gpio-cells = <2>;
};
@@ -97,118 +42,81 @@
};
gpt4: timer@640 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x640 0x10>;
- interrupts = <1 13 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt5: timer@650 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x650 0x10>;
- interrupts = <1 14 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt6: timer@660 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x660 0x10>;
- interrupts = <1 15 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpt7: timer@670 { // General Purpose Timer in GPIO mode
- compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
- reg = <0x670 0x10>;
- interrupts = <1 16 0>;
gpio-controller;
#gpio-cells = <2>;
};
- gpio_simple: gpio@b00 {
- compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
- reg = <0xb00 0x40>;
- interrupts = <1 7 0>;
- gpio-controller;
- #gpio-cells = <2>;
+ rtc@800 {
+ status = "disabled";
};
- gpio_wkup: gpio@c00 {
- compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
- reg = <0xc00 0x40>;
- interrupts = <1 8 0 0 3 0>;
- gpio-controller;
- #gpio-cells = <2>;
+ can@900 {
+ status = "disabled";
};
- dma-controller@1200 {
- compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
- reg = <0x1200 0x80>;
- interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
- 3 4 0 3 5 0 3 6 0 3 7 0
- 3 8 0 3 9 0 3 10 0 3 11 0
- 3 12 0 3 13 0 3 14 0 3 15 0>;
+ can@980 {
+ status = "disabled";
};
- xlb@1f00 {
- compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
- reg = <0x1f00 0x100>;
+ spi@f00 {
+ status = "disabled";
};
- psc@2000 { /* PSC1 in UART mode */
- compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2000 0x100>;
- interrupts = <2 1 0>;
+ usb@1000 {
+ status = "disabled";
};
- psc@2200 { /* PSC2 in UART mode */
+ psc@2000 { // PSC1
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2200 0x100>;
- interrupts = <2 2 0>;
};
- psc@2c00 { /* PSC6 in UART mode */
+ psc@2200 { // PSC2
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
- reg = <0x2c00 0x100>;
- interrupts = <2 4 0>;
};
- ethernet@3000 {
- compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
- reg = <0x3000 0x400>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <2 5 0>;
- phy-handle = <&phy0>;
+ psc@2400 { // PSC3
+ status = "disabled";
};
- mdio@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
- reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
- interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
+ psc@2600 { // PSC4
+ status = "disabled";
+ };
+
+ psc@2800 { // PSC5
+ status = "disabled";
+ };
+ psc@2c00 { // PSC6
+ compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+ };
+
+ mdio@3000 {
phy0: ethernet-phy@0 {
compatible = "intel,lxt971";
reg = <0>;
};
};
- ata@3a00 {
- compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
- reg = <0x3a00 0x100>;
- interrupts = <2 7 0>;
+ i2c@3d00 {
+ status = "disabled";
};
i2c@3d40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
- reg = <0x3d40 0x40>;
- interrupts = <2 16 0>;
fsl,preserve-clocking;
clock-frequency = <400000>;
@@ -221,19 +129,13 @@
reg = <0x51>;
};
};
+ };
- sram@8000 {
- compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
- reg = <0x8000 0x4000>;
- };
+ pci@f0000d00 {
+ status = "disabled";
};
localbus {
- compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
-
- #address-cells = <2>;
- #size-cells = <1>;
-
ranges = <0 0 0xff800000 0x00800000
1 0 0x80000000 0x00800000
3 0 0x80000000 0x00800000>;
^ permalink raw reply related
* [PATCH] powerpc: fix call to subpage_protection()
From: Michael Neuling @ 2010-11-18 2:32 UTC (permalink / raw)
To: Jim Keniston; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1290020404.2974.15.camel@localhost>
In:
powerpc/mm: Fix pgtable cache cleanup with CONFIG_PPC_SUBPAGE_PROT
commit d28513bc7f675d28b479db666d572e078ecf182d
Author: David Gibson <david@gibson.dropbear.id.au>
subpage_protection() was changed to to take an mm rather a pgdir but it
didn't change calling site in hashpage_preload(). The change wasn't
noticed at compile time since hashpage_preload() used a void* as the
parameter to subpage_protection().
This is obviously wrong and can trigger the following crash when
CONFIG_SLAB, CONFIG_DEBUG_SLAB, CONFIG_PPC_64K_PAGES
CONFIG_PPC_SUBPAGE_PROT are enabled.
Freeing unused kernel memory: 704k freed
Unable to handle kernel paging request for data at address 0x6b6b6b6b6b6c49b7
Faulting instruction address: 0xc0000000000410f4
cpu 0x2: Vector: 300 (Data Access) at [c00000004233f590]
pc: c0000000000410f4: .hash_preload+0x258/0x338
lr: c000000000041054: .hash_preload+0x1b8/0x338
sp: c00000004233f810
msr: 8000000000009032
dar: 6b6b6b6b6b6c49b7
dsisr: 40000000
current = 0xc00000007e2c0070
paca = 0xc000000007fe0500
pid = 1, comm = init
enter ? for help
[c00000004233f810] c000000000041020 .hash_preload+0x184/0x338 (unreliable)
[c00000004233f8f0] c00000000003ed98 .update_mmu_cache+0xb0/0xd0
[c00000004233f990] c000000000157754 .__do_fault+0x48c/0x5dc
[c00000004233faa0] c000000000158fd0 .handle_mm_fault+0x508/0xa8c
[c00000004233fb90] c0000000006acdd4 .do_page_fault+0x428/0x6ac
[c00000004233fe30] c000000000005260 handle_page_fault+0x20/0x74
--- Exception: 401 (Instruction Access) at 00000000f7937794
SP (ffef72c0) is in userspace
The following changes this subpage_protection() call.
Reported-by: Jim Keniston <jkenisto@linux.vnet.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Tested-by: Jim Keniston <jkenisto@linux.vnet.ibm.com>
cc: David Gibson <david@gibson.dropbear.id.au>
cc: stable@kernel.org (only 2.6.33 and newer)
---
> It boots fine with pseries_defconfig.
>
> Attached is the config file that I've been using, which is probably
> descended over many generations of kernels from some config file in my
> machine's distant past. (Enable DEBUG_SLAB or DEBUG_PAGEALLOC and it
> will fail to boot.) After I run 'make menuconfig' starting from
> pseries_defconfig...
> $ diff config_ok .config | wc -l
> 2052
I narrowed this down to adding the following on pseries_defconfig:
+CONFIG_SLAB=y
+CONFIG_PPC_64K_PAGES=y
+CONFIG_PPC_SUBPAGE_PROT=y
+CONFIG_DEBUG_SLAB=y
To reproduce the fail.
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 83f534d..5e95844 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -1123,7 +1123,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
else
#endif /* CONFIG_PPC_HAS_HASH_64K */
rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
- subpage_protection(pgdir, ea));
+ subpage_protection(mm, ea));
/* Dump some info in case of hash insertion failure, they should
* never happen so it is really useful to know if/when they do
^ permalink raw reply related
* Re: arch/powerpc/*/div64.S
From: Benjamin Herrenschmidt @ 2010-11-18 3:37 UTC (permalink / raw)
To: Albert Cahalan; +Cc: linuxppc-dev
In-Reply-To: <AANLkTinC-DiZNZ4GsWM2+xk+mp=AN1Q82uLAekNB=_FT@mail.gmail.com>
On Sat, 2010-10-02 at 14:16 -0400, Albert Cahalan wrote:
> This looks like duplicated code getting out of sync.
Right, tho your patch actually reverts the fix :-)
I don't know if it's worth considering using common files for some /lib
stuff there tho.. .the runtime env. is quite different...
Ben.
> $ diff -Naurd arch/powerpc/lib/div64.S arch/powerpc/boot/div64.S
> --- arch/powerpc/lib/div64.S 2009-09-09 18:13:59.000000000 -0400
> +++ arch/powerpc/boot/div64.S 2009-09-09 18:13:59.000000000 -0400
> @@ -13,10 +13,10 @@
> * as published by the Free Software Foundation; either version
> * 2 of the License, or (at your option) any later version.
> */
> -#include <asm/ppc_asm.h>
> -#include <asm/processor.h>
> +#include "ppc_asm.h"
>
> -_GLOBAL(__div64_32)
> + .globl __div64_32
> +__div64_32:
> lwz r5,0(r3) # get the dividend into r5/r6
> lwz r6,4(r3)
> cmplw r5,r4
> @@ -33,10 +33,9 @@
> cntlzw r0,r5 # we are shifting the dividend right
> li r10,-1 # to make it < 2^32, and shifting
> srw r10,r10,r0 # the divisor right the same amount,
> - addc r9,r4,r10 # rounding up (so the estimate cannot
> + add r9,r4,r10 # rounding up (so the estimate cannot
> andc r11,r6,r10 # ever be too large, only too small)
> andc r9,r9,r10
> - addze r9,r9
> or r11,r5,r11
> rotlw r9,r9,r0
> rotlw r11,r11,r0
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 1/5] scripts: dtc: Merge in changes from the dtc repository
From: David Gibson @ 2010-11-18 3:41 UTC (permalink / raw)
To: Jon Loeliger
Cc: glikely, devicetree-discuss, linux-kernel, John Bonesio,
linuxppc-dev
In-Reply-To: <E1PIkEl-0006Zt-W7@jdl.com>
On Wed, Nov 17, 2010 at 09:47:55AM -0600, Jon Loeliger wrote:
> > On Tue, Nov 16, 2010 at 12:49:51PM -0800, John Bonesio wrote:
> > > Pull in recent changes from the main dtc repository. These changes primarily
> > > allow multiple device trees to be declared which are merged by dtc. This
> > > feature allows us to include a basic dts file and then provide more informatio
> > n
> > > for the specific system through the merging functionality.
> > >
> > > Signed-off-by: John Bonesio <bones@secretlab.ca>
> >
> > Jon & David, I'll need your input on whether or not this is the best
> > way to handle updating the dtc copy in the kernel tree.
> >
> > g.
>
> Grant,
>
> Yeah, I wondered too. :-) David added it and updated
> in the kernel last round, so he may have some good notion
> of what would be best there.
For now I think just a direct diff updating the in-kernel dtc to
current upstream is the simplest approach. This is how I made the
original commit.
There may be better methods to directly arrange for pulling of the dtc
git tree into the kernel git tree, but I have not had time to
investigate and set up such a scheme.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: linux-next: build warning in Linus' tree
From: Benjamin Herrenschmidt @ 2010-11-18 3:55 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Linus Torvalds, H. Peter Anvin, linuxppc-dev, Jan Beulich,
Arnaud Lacombe
In-Reply-To: <20101025170322.851780f3.sfr@canb.auug.org.au>
On Mon, 2010-10-25 at 17:03 +1100, Stephen Rothwell wrote:
> Hi Arnaud,
>
> On Sun, 24 Oct 2010 23:47:09 -0400 Arnaud Lacombe <lacombar@gmail.com> wrote:
> >
> > The following patch should fix this warning.
>
> I think the following is preferable. Not tested yet, I will test
> tomorrow and submit properly then.
I agree. Tho I don't understand the original problem. Both definitions
have no parenthesis for me and I don't see warnings, or am I missing
some changes still in -next that cause this ?
Cheers,
Ben.
> --
> Cheers,
> Stephen Rothwell sfr@canb.auug.org.au
> http://www.canb.auug.org.au/~sfr/
>
> From: Stephen Rothwell <sfr@canb.auug.org.au>
> Date: Mon, 25 Oct 2010 16:57:47 +1100
> Subject: [PATCH] powerpc: remove second definition of STACK_FRAME_OVERHEAD
>
> Since STACK_FRAME_OVERHEAD is defined in asm/ptrace.h and that
> is ASSEMBER safe, we can just include that instead of going via
> asm-offsets.h.
>
> Eliminated build warnings about a duplicate definition now that
> the asm-offsets.h version has parentheses around the values.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
> ---
> arch/powerpc/kernel/asm-offsets.c | 1 -
> arch/powerpc/kernel/entry_32.S | 1 +
> arch/powerpc/kernel/exceptions-64s.S | 1 +
> arch/powerpc/kernel/fpu.S | 1 +
> arch/powerpc/kernel/head_40x.S | 1 +
> arch/powerpc/kernel/head_44x.S | 1 +
> arch/powerpc/kernel/head_64.S | 1 +
> arch/powerpc/kernel/head_8xx.S | 1 +
> arch/powerpc/kernel/head_fsl_booke.S | 1 +
> arch/powerpc/kernel/misc_32.S | 1 +
> arch/powerpc/kernel/misc_64.S | 1 +
> arch/powerpc/kernel/ppc_save_regs.S | 1 +
> arch/powerpc/kernel/vector.S | 1 +
> arch/powerpc/platforms/pseries/hvCall.S | 1 +
> 14 files changed, 13 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
> index bd0df2e..23e6a93 100644
> --- a/arch/powerpc/kernel/asm-offsets.c
> +++ b/arch/powerpc/kernel/asm-offsets.c
> @@ -209,7 +209,6 @@ int main(void)
> DEFINE(RTASENTRY, offsetof(struct rtas_t, entry));
>
> /* Interrupt register frame */
> - DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD);
> DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
> DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
> #ifdef CONFIG_PPC64
> diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
> index ed4aeb9..c22dc1e 100644
> --- a/arch/powerpc/kernel/entry_32.S
> +++ b/arch/powerpc/kernel/entry_32.S
> @@ -31,6 +31,7 @@
> #include <asm/asm-offsets.h>
> #include <asm/unistd.h>
> #include <asm/ftrace.h>
> +#include <asm/ptrace.h>
>
> #undef SHOW_SYSCALLS
> #undef SHOW_SYSCALLS_TASK
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> index 9f8b01d..8a81799 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -13,6 +13,7 @@
> */
>
> #include <asm/exception-64s.h>
> +#include <asm/ptrace.h>
>
> /*
> * We layout physical memory as follows:
> diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
> index e86c040..de36955 100644
> --- a/arch/powerpc/kernel/fpu.S
> +++ b/arch/powerpc/kernel/fpu.S
> @@ -23,6 +23,7 @@
> #include <asm/thread_info.h>
> #include <asm/ppc_asm.h>
> #include <asm/asm-offsets.h>
> +#include <asm/ptrace.h>
>
> #ifdef CONFIG_VSX
> #define REST_32FPVSRS(n,c,base) \
> diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
> index 8278e8b..9dd21a8 100644
> --- a/arch/powerpc/kernel/head_40x.S
> +++ b/arch/powerpc/kernel/head_40x.S
> @@ -40,6 +40,7 @@
> #include <asm/thread_info.h>
> #include <asm/ppc_asm.h>
> #include <asm/asm-offsets.h>
> +#include <asm/ptrace.h>
>
> /* As with the other PowerPC ports, it is expected that when code
> * execution begins here, the following registers contain valid, yet
> diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
> index 562305b..cbb3436 100644
> --- a/arch/powerpc/kernel/head_44x.S
> +++ b/arch/powerpc/kernel/head_44x.S
> @@ -37,6 +37,7 @@
> #include <asm/thread_info.h>
> #include <asm/ppc_asm.h>
> #include <asm/asm-offsets.h>
> +#include <asm/ptrace.h>
> #include <asm/synch.h>
> #include "head_booke.h"
>
> diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
> index f0dd577..ce41b97 100644
> --- a/arch/powerpc/kernel/head_64.S
> +++ b/arch/powerpc/kernel/head_64.S
> @@ -38,6 +38,7 @@
> #include <asm/page_64.h>
> #include <asm/irqflags.h>
> #include <asm/kvm_book3s_asm.h>
> +#include <asm/ptrace.h>
>
> /* The physical memory is layed out such that the secondary processor
> * spin code sits at 0x0000...0x00ff. On server, the vectors follow
> diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
> index 1f1a04b..1cbf64e 100644
> --- a/arch/powerpc/kernel/head_8xx.S
> +++ b/arch/powerpc/kernel/head_8xx.S
> @@ -29,6 +29,7 @@
> #include <asm/thread_info.h>
> #include <asm/ppc_asm.h>
> #include <asm/asm-offsets.h>
> +#include <asm/ptrace.h>
>
> /* Macro to make the code more readable. */
> #ifdef CONFIG_8xx_CPU6
> diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
> index 529b817..3e02710 100644
> --- a/arch/powerpc/kernel/head_fsl_booke.S
> +++ b/arch/powerpc/kernel/head_fsl_booke.S
> @@ -41,6 +41,7 @@
> #include <asm/ppc_asm.h>
> #include <asm/asm-offsets.h>
> #include <asm/cache.h>
> +#include <asm/ptrace.h>
> #include "head_booke.h"
>
> /* As with the other PowerPC ports, it is expected that when code
> diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
> index a7a570d..094bd98 100644
> --- a/arch/powerpc/kernel/misc_32.S
> +++ b/arch/powerpc/kernel/misc_32.S
> @@ -30,6 +30,7 @@
> #include <asm/processor.h>
> #include <asm/kexec.h>
> #include <asm/bug.h>
> +#include <asm/ptrace.h>
>
> .text
>
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index e514490..206a321 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -25,6 +25,7 @@
> #include <asm/cputable.h>
> #include <asm/thread_info.h>
> #include <asm/kexec.h>
> +#include <asm/ptrace.h>
>
> .text
>
> diff --git a/arch/powerpc/kernel/ppc_save_regs.S b/arch/powerpc/kernel/ppc_save_regs.S
> index 5113bd2..e83ba3f 100644
> --- a/arch/powerpc/kernel/ppc_save_regs.S
> +++ b/arch/powerpc/kernel/ppc_save_regs.S
> @@ -11,6 +11,7 @@
> #include <asm/processor.h>
> #include <asm/ppc_asm.h>
> #include <asm/asm-offsets.h>
> +#include <asm/ptrace.h>
>
> /*
> * Grab the register values as they are now.
> diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
> index fe46048..9de6f39 100644
> --- a/arch/powerpc/kernel/vector.S
> +++ b/arch/powerpc/kernel/vector.S
> @@ -5,6 +5,7 @@
> #include <asm/cputable.h>
> #include <asm/thread_info.h>
> #include <asm/page.h>
> +#include <asm/ptrace.h>
>
> /*
> * load_up_altivec(unused, unused, tsk)
> diff --git a/arch/powerpc/platforms/pseries/hvCall.S b/arch/powerpc/platforms/pseries/hvCall.S
> index 48d2057..fd05fde 100644
> --- a/arch/powerpc/platforms/pseries/hvCall.S
> +++ b/arch/powerpc/platforms/pseries/hvCall.S
> @@ -11,6 +11,7 @@
> #include <asm/processor.h>
> #include <asm/ppc_asm.h>
> #include <asm/asm-offsets.h>
> +#include <asm/ptrace.h>
>
> #define STK_PARM(i) (48 + ((i)-3)*8)
>
^ permalink raw reply
* Re: linux-next: build warning in Linus' tree
From: Arnaud Lacombe @ 2010-11-18 4:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Stephen Rothwell, H. Peter Anvin, linuxppc-dev, Jan Beulich,
Linus Torvalds
In-Reply-To: <1290052544.32570.1.camel@pasglop>
Hi,
On Wed, Nov 17, 2010 at 10:55 PM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Mon, 2010-10-25 at 17:03 +1100, Stephen Rothwell wrote:
>> Hi Arnaud,
>>
>> On Sun, 24 Oct 2010 23:47:09 -0400 Arnaud Lacombe <lacombar@gmail.com> w=
rote:
>> >
>> > The following patch should fix this warning.
>>
>> I think the following is preferable. =A0Not tested yet, I will test
>> tomorrow and submit properly then.
>
> I agree. Tho I don't understand the original problem. Both definitions
> have no parenthesis for me and I don't see warnings, or am I missing
> some changes still in -next that cause this ?
>
The warning was caused by part of the following commit which came
through the x86 tree, afaik during the merge window:
commit 3234282f33b29d349bcada40204fc7c8fda7fe72
Author: Jan Beulich <JBeulich@novell.com>
Date: Tue Oct 19 14:52:26 2010 +0100
x86, asm: Fix CFI macro invocations to deal with shortcomings in gas
It looks to have been fixed by:
commit 95a2f6f72d37762ba1b3d6c8031f66a6467a63df
Author: David Howells <dhowells@redhat.com>
Date: Wed Oct 27 17:28:32 2010 +0100
Partially revert patch that encloses asm-offset.h numbers in brackets
Partially revert patch:
commit 3234282f33b29d349bcada40204fc7c8fda7fe72
Author: Jan Beulich <JBeulich@novell.com>
Date: Tue Oct 19 14:52:26 2010 +0100
x86, asm: Fix CFI macro invocations to deal with shortcomings in ga=
s
[...]
which came in through the mn10300 tree. So if you're no longer seeing
the warning, no ppc specific patch seems to be needed.
- Arnaud
^ permalink raw reply
* [PATCH 0/4] Patches from my local tree
From: mikey @ 2010-11-18 4:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
Below are a few patches from my local tree
^ permalink raw reply
* [PATCH 1/4] powerpc: remove unneeded cpu_setup/restore from POWER7 cputable entry
From: mikey @ 2010-11-18 4:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20101118045241.071482503@neuling.org>
These are not needed so just remove them
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/cputable.c | 2 --
arch/powerpc/kernel/misc.S | 5 -----
2 files changed, 7 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -457,8 +457,6 @@
.dcache_bsize = 128,
.num_pmcs = 6,
.pmc_type = PPC_PMC_IBM,
- .cpu_setup = __setup_cpu_power7,
- .cpu_restore = __restore_cpu_power7,
.oprofile_cpu_type = "ppc64/power7",
.oprofile_type = PPC_OPROFILE_POWER4,
.oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
Index: linux-2.6-ozlabs/arch/powerpc/kernel/misc.S
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/misc.S
+++ linux-2.6-ozlabs/arch/powerpc/kernel/misc.S
@@ -122,8 +122,3 @@
mtlr r0
mr r3,r4
blr
-
-_GLOBAL(__setup_cpu_power7)
-_GLOBAL(__restore_cpu_power7)
- /* place holder */
- blr
^ permalink raw reply
* [PATCH 2/4] powerpc: remove POWER6 oprofile workarounds for POWER7
From: mikey @ 2010-11-18 4:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20101118045241.071482503@neuling.org>
These are not needed on POWER7 so remove them.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/cputable.c | 4 ----
1 file changed, 4 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -459,10 +459,6 @@
.pmc_type = PPC_PMC_IBM,
.oprofile_cpu_type = "ppc64/power7",
.oprofile_type = PPC_OPROFILE_POWER4,
- .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
- .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
- .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
- POWER6_MMCRA_OTHER,
.platform = "power7",
},
{ /* Cell Broadband Engine */
^ permalink raw reply
* [PATCH 3/4] powerpc: add POWER7+ cputable entry
From: mikey @ 2010-11-18 4:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20101118045241.071482503@neuling.org>
This adds the POWER7+ cputable entry for the PVR 0x004a0000. Rest is
the same as vanilla POWER7.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/cputable.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -461,6 +461,22 @@
.oprofile_type = PPC_OPROFILE_POWER4,
.platform = "power7",
},
+ { /* Power7+ */
+ .pvr_mask = 0xffff0000,
+ .pvr_value = 0x004A0000,
+ .cpu_name = "POWER7+ (raw)",
+ .cpu_features = CPU_FTRS_POWER7,
+ .cpu_user_features = COMMON_USER_POWER7,
+ .mmu_features = MMU_FTR_HPTE_TABLE |
+ MMU_FTR_TLBIE_206,
+ .icache_bsize = 128,
+ .dcache_bsize = 128,
+ .num_pmcs = 6,
+ .pmc_type = PPC_PMC_IBM,
+ .oprofile_cpu_type = "ppc64/power7",
+ .oprofile_type = PPC_OPROFILE_POWER4,
+ .platform = "power7+",
+ },
{ /* Cell Broadband Engine */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00700000,
^ permalink raw reply
* [PATCH 4/4] powerpc: hash_preload: avoid avoidable void
From: mikey @ 2010-11-18 4:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20101118045241.071482503@neuling.org>
Change pgdir from a void to real type. Having this as a void is
stupid and has already caused 1 bug.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/mm/hash_utils_64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_utils_64.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_utils_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_utils_64.c
@@ -1070,7 +1070,7 @@
unsigned long access, unsigned long trap)
{
unsigned long vsid;
- void *pgdir;
+ pgd_t *pgdir;
pte_t *ptep;
unsigned long flags;
int rc, ssize, local = 0;
^ permalink raw reply
* [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2010-11-18 5:46 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, Andrew Morton, Linux Kernel list
Hi Linus !
Here are a handful of bug fixes and trivialities for powerpc for you
to pull.
Thanks !
Cheers,
Ben.
The following changes since commit 7957f0a857754c555e07f58a3fb83ac29501478c:
Linus Torvalds (1):
Fix build failure due to hwirq.h needing smp_lock.h
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git merge
Alessio Igor Bogani (1):
powerpc: Update a BKL related comment
Benjamin Herrenschmidt (1):
powerpc: Fix div64 in bootloader
Kumar Gala (2):
powerpc/mm: Fix build error in setup_initial_memory_limit
powerpc/mm: Fix module instruction tlb fault handling on Book-E 64
Michael Neuling (1):
powerpc: Fix call to subpage_protection()
Nishanth Aravamudan (1):
powerpc/pseries: Don't override CONFIG_PPC_PSERIES_DEBUG
kerstin jonsson (1):
powerpc: Set CONFIG_32BIT on ppc32
arch/powerpc/Kconfig | 4 ++++
arch/powerpc/boot/div64.S | 3 ++-
arch/powerpc/kernel/setup_64.c | 5 ++---
arch/powerpc/mm/hash_utils_64.c | 2 +-
arch/powerpc/mm/tlb_low_64e.S | 5 ++++-
arch/powerpc/mm/tlb_nohash.c | 2 +-
arch/powerpc/platforms/pseries/Kconfig | 6 ++++++
arch/powerpc/platforms/pseries/eeh.c | 2 --
arch/powerpc/platforms/pseries/pci_dlpar.c | 2 --
9 files changed, 20 insertions(+), 11 deletions(-)
^ permalink raw reply
* [PATCH 1/2][v4] fsl_rio: move machine_check handler into machine_check_e500 & machine_check_e500mc
From: Shaohui Xie @ 2010-11-18 6:57 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Shaohui Xie, Kumar Gala, Alexandre Bounine, akpm
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Cc: Li Yang <leoli@freescale.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Cc: Alexandre Bounine <alexandre.bounine@idt.com>
---
arch/powerpc/include/asm/rio.h | 5 +++++
arch/powerpc/kernel/traps.c | 13 +++++++++++++
arch/powerpc/sysdev/fsl_rio.c | 15 +++------------
3 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/asm/rio.h b/arch/powerpc/include/asm/rio.h
index 0018bf8..d902abd 100644
--- a/arch/powerpc/include/asm/rio.h
+++ b/arch/powerpc/include/asm/rio.h
@@ -14,5 +14,10 @@
#define ASM_PPC_RIO_H
extern void platform_rio_init(void);
+#ifdef CONFIG_RAPIDIO
+extern int fsl_rio_mcheck_exception(struct pt_regs *);
+#else
+static inline int fsl_rio_mcheck_exception(struct pt_regs *regs) {return 0; }
+#endif
#endif /* ASM_PPC_RIO_H */
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 1b2cdc8..5f6c106 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -55,6 +55,7 @@
#endif
#include <asm/kexec.h>
#include <asm/ppc-opcode.h>
+#include <asm/rio.h>
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -425,6 +426,12 @@ int machine_check_e500mc(struct pt_regs *regs)
unsigned long reason = mcsr;
int recoverable = 1;
+ if (reason & MCSR_BUS_RBERR) {
+ recoverable = fsl_rio_mcheck_exception(regs);
+ if (recoverable == 1)
+ goto silent_out;
+ }
+
printk("Machine check in kernel mode.\n");
printk("Caused by (from MCSR=%lx): ", reason);
@@ -500,6 +507,7 @@ int machine_check_e500mc(struct pt_regs *regs)
reason & MCSR_MEA ? "Effective" : "Physical", addr);
}
+silent_out:
mtspr(SPRN_MCSR, mcsr);
return mfspr(SPRN_MCSR) == 0 && recoverable;
}
@@ -508,6 +516,11 @@ int machine_check_e500(struct pt_regs *regs)
{
unsigned long reason = get_mc_reason(regs);
+ if (reason & MCSR_BUS_RBERR) {
+ if (fsl_rio_mcheck_exception(regs))
+ return 1;
+ }
+
printk("Machine check in kernel mode.\n");
printk("Caused by (from MCSR=%lx): ", reason);
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 4c518d1..ddbcd16 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -260,9 +260,7 @@ struct rio_priv {
static void __iomem *rio_regs_win;
#ifdef CONFIG_E500
-static int (*saved_mcheck_exception)(struct pt_regs *regs);
-
-static int fsl_rio_mcheck_exception(struct pt_regs *regs)
+int fsl_rio_mcheck_exception(struct pt_regs *regs)
{
const struct exception_table_entry *entry = NULL;
unsigned long reason = mfspr(SPRN_MCSR);
@@ -284,11 +282,9 @@ static int fsl_rio_mcheck_exception(struct pt_regs *regs)
}
}
- if (saved_mcheck_exception)
- return saved_mcheck_exception(regs);
- else
- return cur_cpu_spec->machine_check(regs);
+ return 0;
}
+EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
#endif
/**
@@ -1552,11 +1548,6 @@ int fsl_rio_setup(struct platform_device *dev)
fsl_rio_doorbell_init(port);
fsl_rio_port_write_init(port);
-#ifdef CONFIG_E500
- saved_mcheck_exception = ppc_md.machine_check_exception;
- ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
-#endif
-
return 0;
err:
iounmap(priv->regs_win);
--
1.6.4
^ permalink raw reply related
* [PATCH 2/2][v3] rapidio, powerpc/85xx: Error interrupt handler for sRIO.
From: Shaohui Xie @ 2010-11-18 6:57 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Shaohui Xie, Kumar Gala, Alexandre Bounine, akpm
The sRIO controller reports errors to the core with one signal, it uses
register EPWISR to provides the core quick access to where the error occurred.
The EPWISR indicates that there are 4 interrupts sources, port1, port2, message
unit and port write receive, but the sRIO driver does not support port2
for now, still the handler takes care of port2.
Currently the handler only clear error status without any recovery.
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Cc: Li Yang <leoli@freescale.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>
Cc: Alexandre Bounine <alexandre.bounine@idt.com>
---
updated to 37-rc2
arch/powerpc/sysdev/fsl_rio.c | 85 +++++++++++++++++++++++++++++++++++++----
1 files changed, 77 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index ddbcd16..d036df9 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -10,7 +10,7 @@
* - Added Port-Write message handling
* - Added Machine Check exception handling
*
- * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc.
* Zhang Wei <wei.zhang@freescale.com>
*
* Copyright 2005 MontaVista Software, Inc.
@@ -47,15 +47,33 @@
#define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
#define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
+#define IPWSR_CLEAR 0x98
+#define OMSR_CLEAR 0x1cb3
+#define IMSR_CLEAR 0x491
+#define IDSR_CLEAR 0x91
+#define ODSR_CLEAR 0x1c00
+#define LTLEECSR_ENABLE_ALL 0xFFC000FC
+#define ESCSR_CLEAR 0x07120204
+
+#define RIO_PORT1_EDCSR 0x0640
+#define RIO_PORT2_EDCSR 0x0680
+#define RIO_PORT1_IECSR 0x10130
+#define RIO_PORT2_IECSR 0x101B0
+#define RIO_IM0SR 0x13064
+#define RIO_IM1SR 0x13164
+#define RIO_OM0SR 0x13004
+#define RIO_OM1SR 0x13104
+
#define RIO_ATMU_REGS_OFFSET 0x10c00
#define RIO_P_MSG_REGS_OFFSET 0x11000
#define RIO_S_MSG_REGS_OFFSET 0x13000
#define RIO_GCCSR 0x13c
#define RIO_ESCSR 0x158
+#define RIO_PORT2_ESCSR 0x178
#define RIO_CCSR 0x15c
#define RIO_LTLEDCSR 0x0608
-#define RIO_LTLEDCSR_IER 0x80000000
-#define RIO_LTLEDCSR_PRT 0x01000000
+#define RIO_LTLEDCSR_IER 0x80000000
+#define RIO_LTLEDCSR_PRT 0x01000000
#define RIO_LTLEECSR 0x060c
#define RIO_EPWISR 0x10010
#define RIO_ISR_AACR 0x10120
@@ -88,7 +106,10 @@
#define RIO_IPWSR_PWD 0x00000008
#define RIO_IPWSR_PWB 0x00000004
-#define RIO_EPWISR_PINT 0x80000000
+/* EPWISR Error match value */
+#define RIO_EPWISR_PINT1 0x80000000
+#define RIO_EPWISR_PINT2 0x40000000
+#define RIO_EPWISR_MU 0x00000002
#define RIO_EPWISR_PW 0x00000001
#define RIO_MSG_DESC_SIZE 32
@@ -1066,6 +1087,40 @@ static int fsl_rio_doorbell_init(struct rio_mport *mport)
return rc;
}
+static void port_error_handler(struct rio_mport *port, int offset)
+{
+ /*XXX: Error recovery is not implemented, we just clear errors */
+ out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
+
+ if (offset == 0) {
+ out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
+ out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), 0);
+ out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
+ } else {
+ out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
+ out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), 0);
+ out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
+ }
+}
+
+static void msg_unit_error_handler(struct rio_mport *port)
+{
+ struct rio_priv *priv = port->priv;
+
+ /*XXX: Error recovery is not implemented, we just clear errors */
+ out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
+
+ out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR);
+ out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR);
+ out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR);
+ out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR);
+
+ out_be32(&priv->msg_regs->odsr, ODSR_CLEAR);
+ out_be32(&priv->msg_regs->dsr, IDSR_CLEAR);
+
+ out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR);
+}
+
/**
* fsl_rio_port_write_handler - MPC85xx port write interrupt handler
* @irq: Linux interrupt number
@@ -1146,10 +1201,22 @@ fsl_rio_port_write_handler(int irq, void *dev_instance)
}
pw_done:
- if (epwisr & RIO_EPWISR_PINT) {
+ if (epwisr & RIO_EPWISR_PINT1) {
+ tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
+ pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
+ port_error_handler(port, 0);
+ }
+
+ if (epwisr & RIO_EPWISR_PINT2) {
+ tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
+ pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
+ port_error_handler(port, 1);
+ }
+
+ if (epwisr & RIO_EPWISR_MU) {
tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
- out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
+ msg_unit_error_handler(port);
}
return IRQ_HANDLED;
@@ -1260,12 +1327,14 @@ static int fsl_rio_port_write_init(struct rio_mport *mport)
/* Hook up port-write handler */
- rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
- "port-write", (void *)mport);
+ rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler,
+ IRQF_SHARED, "port-write", (void *)mport);
if (rc < 0) {
pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
goto err_out;
}
+ /* Enable Error Interrupt */
+ out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
INIT_WORK(&priv->pw_work, fsl_pw_dpc);
spin_lock_init(&priv->pw_fifo_lock);
--
1.6.4
^ permalink raw reply related
* Re: linux-next: build warning in Linus' tree
From: Jan Beulich @ 2010-11-18 7:45 UTC (permalink / raw)
To: Stephen Rothwell, Benjamin Herrenschmidt
Cc: linuxppc-dev, H.Peter Anvin, Linus Torvalds, Arnaud Lacombe
In-Reply-To: <1290052544.32570.1.camel@pasglop>
>>> On 18.11.10 at 04:55, Benjamin Herrenschmidt <benh@kernel.crashing.org>=
wrote:
> On Mon, 2010-10-25 at 17:03 +1100, Stephen Rothwell wrote:
>> Hi Arnaud,
>>=20
>> On Sun, 24 Oct 2010 23:47:09 -0400 Arnaud Lacombe <lacombar@gmail.com> =
wrote:
>> >
>> > The following patch should fix this warning.
>>=20
>> I think the following is preferable. Not tested yet, I will test
>> tomorrow and submit properly then.
>=20
> I agree. Tho I don't understand the original problem. Both definitions
> have no parenthesis for me and I don't see warnings, or am I missing
> some changes still in -next that cause this ?
There had been parentheses for a short while, but them causing
problems for at least one other arch, they got removed again.
Jan
^ permalink raw reply
* Re: [PATCH] powerpc: fix call to subpage_protection()
From: Michael Ellerman @ 2010-11-18 12:21 UTC (permalink / raw)
To: Michael Neuling; +Cc: Jim Keniston, linuxppc-dev, David Gibson
In-Reply-To: <13149.1290047579@neuling.org>
[-- Attachment #1: Type: text/plain, Size: 1073 bytes --]
On Thu, 2010-11-18 at 13:32 +1100, Michael Neuling wrote:
> In:
> powerpc/mm: Fix pgtable cache cleanup with CONFIG_PPC_SUBPAGE_PROT
> commit d28513bc7f675d28b479db666d572e078ecf182d
> Author: David Gibson <david@gibson.dropbear.id.au>
>
> subpage_protection() was changed to to take an mm rather a pgdir but it
> didn't change calling site in hashpage_preload(). The change wasn't
> noticed at compile time since hashpage_preload() used a void* as the
> parameter to subpage_protection().
...
>
> diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
> index 83f534d..5e95844 100644
> --- a/arch/powerpc/mm/hash_utils_64.c
> +++ b/arch/powerpc/mm/hash_utils_64.c
> @@ -1123,7 +1123,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
> else
> #endif /* CONFIG_PPC_HAS_HASH_64K */
> rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
> - subpage_protection(pgdir, ea));
> + subpage_protection(mm, ea));
Type checking is fun :)
This is stable material no?
cheers
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^ permalink raw reply
* Re: application needs fast access to physical memory
From: Michael Ellerman @ 2010-11-18 12:24 UTC (permalink / raw)
To: steven.lin; +Cc: Steven_Lin, linuxppc-dev
In-Reply-To: <OFEB1252DC.D653C7C7-ON882577DE.0078DABB-862577DE.00792502@notes.teradyne.com>
[-- Attachment #1: Type: text/plain, Size: 797 bytes --]
On Wed, 2010-11-17 at 16:03 -0600, steven.lin@teradyne.com wrote:
> My application needs a fast way to access a specific physical DDR
> memory region. The application runs on an MPC8548 PowerPC which has an
> MMU. I've tried two approaches that are typical for Linux, mmap() and
> using a kernel module that implements read()/write() into this region
> and I'm finding that performance is very slow for both. It's a couple
> orders of magnitude slower than, for example, copying a large buffer
> from one place in the application's virtual memory to another place in
> the application's virtual memory.
The mmap() version should basically run at "full speed", at least once
you've faulted the address range in.
This specific DDR region isn't specifically slow is it ? :)
cheers
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^ permalink raw reply
* RE: application needs fast access to physical memory
From: David Laight @ 2010-11-18 12:52 UTC (permalink / raw)
Cc: linuxppc-dev
In-Reply-To: <1290083062.22575.9.camel@concordia>
=20
> On Wed, 2010-11-17 at 16:03 -0600, steven.lin@teradyne.com wrote:
> > My application needs a fast way to access a specific physical DDR
> > memory region. The application runs on an MPC8548 PowerPC which has
an
> > MMU. I've tried two approaches that are typical for Linux, mmap()
and
> > using a kernel module that implements read()/write() into this
region
> > and I'm finding that performance is very slow for both. It's a
couple
> > orders of magnitude slower than, for example, copying a large buffer
> > from one place in the application's virtual memory to another place
in
> > the application's virtual memory.
>=20
> The mmap() version should basically run at "full speed", at least once
> you've faulted the address range in.
>=20
> This specific DDR region isn't specifically slow is it ? :)
Or being mapped uncached ?
David
^ permalink raw reply
* Re: application needs fast access to physical memory
From: David Gibson @ 2010-11-18 12:54 UTC (permalink / raw)
To: Michael Ellerman; +Cc: Steven_Lin, steven.lin, linuxppc-dev
In-Reply-To: <1290083062.22575.9.camel@concordia>
[-- Attachment #1: Type: text/plain, Size: 1192 bytes --]
On Thu, Nov 18, 2010 at 11:24:22PM +1100, Michael Ellerman wrote:
> On Wed, 2010-11-17 at 16:03 -0600, steven.lin@teradyne.com wrote:
> > My application needs a fast way to access a specific physical DDR
> > memory region. The application runs on an MPC8548 PowerPC which has an
> > MMU. I've tried two approaches that are typical for Linux, mmap() and
> > using a kernel module that implements read()/write() into this region
> > and I'm finding that performance is very slow for both. It's a couple
> > orders of magnitude slower than, for example, copying a large buffer
> > from one place in the application's virtual memory to another place in
> > the application's virtual memory.
>
> The mmap() version should basically run at "full speed", at least once
> you've faulted the address range in.
>
> This specific DDR region isn't specifically slow is it ? :)
The other theory that springs to mind is whatever method you're using
to access the region enabling cacheing?
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply
* Re: application needs fast access to physical memory
From: steven.lin @ 2010-11-18 16:55 UTC (permalink / raw)
To: David Gibson, Michael Ellerman; +Cc: linuxppc-dev
In-Reply-To: <20101118125425.GE7256@yookeroo>
[-- Attachment #1.1: Type: text/plain, Size: 4652 bytes --]
Thanks for the replies.
In the Linux Device Drivers book regarding mmap(), it states:
Mapping a device means associating a range of user-space addresses to
device memory.
Whenever the program reads or writes in the assigned address range, it
is actually
accessing the device. In the X server example, using mmap allows quick
and easy
access to the video card’s memory. For a performance-critical
application like this,
direct access makes a large difference.
For whatever reason, mmap() is definitely not quick and does not appear to
be a direct access to device memory. After the application completes a
large write into physical memory (via the pointer returned from mmap()),
the application performs an ioctl() to query whether the data actually
arrived into the memory region. It seems to take some time before the
associated kernel module actually "sees" the data in the physical memory
region.
There's a few things I should say about this memory region. There's a total
of 512 MB of physical memory. U-Boot passes "mem=256M" as a kernel
parameter to tell Linux to only directly manage the lower 256 MB. The
special region of physical memory that the application is trying to access
is the upper 256 MB of memory not directly managed by Linux. The mmap()
call from the application is:
*memptr = (void *) mmap( NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED,
_fdTerAlloc, (off_t) 0x10000000);
On the kernel module side, the function handling the mmap() file operation
is:
static int ter_alloc_mmap( struct file *pFile, struct vm_area_struct
*vma )
{
if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, vma->vm_end -
vma->vm_start, vma->vm_page_prot))
return -EAGAIN;
vma->vm_ops = &ter_alloc_remap_vm_ops;
ter_alloc_vma_open(vma);
return 0;
}
-Steve Lin
David Gibson
<david@gibson.dro
pbear.id.au> To
Michael Ellerman
11/18/2010 06:54 <michael@ellerman.id.au>
AM cc
steven.lin@teradyne.com,
Steven_Lin@notes.teradyne.com,
linuxppc-dev@lists.ozlabs.org
Subject
Re: application needs fast access
to physical memory
On Thu, Nov 18, 2010 at 11:24:22PM +1100, Michael Ellerman wrote:
> On Wed, 2010-11-17 at 16:03 -0600, steven.lin@teradyne.com wrote:
> > My application needs a fast way to access a specific physical DDR
> > memory region. The application runs on an MPC8548 PowerPC which has an
> > MMU. I've tried two approaches that are typical for Linux, mmap() and
> > using a kernel module that implements read()/write() into this region
> > and I'm finding that performance is very slow for both. It's a couple
> > orders of magnitude slower than, for example, copying a large buffer
> > from one place in the application's virtual memory to another place in
> > the application's virtual memory.
>
> The mmap() version should basically run at "full speed", at least once
> you've faulted the address range in.
>
> This specific DDR region isn't specifically slow is it ? :)
The other theory that springs to mind is whatever method you're using
to access the region enabling cacheing?
--
David Gibson | I'll have my music
baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT
_the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply
* Re: Gianfar TCP checksumming broken in 2.6.35+
From: David Miller @ 2010-11-18 17:06 UTC (permalink / raw)
To: mlcreech; +Cc: linuxppc-dev
In-Reply-To: <AANLkTi=-ZAL-to4qZ0vA20L589fMQm89E9mH9WWOvX0c@mail.gmail.com>
From: "Matthew L. Creech" <mlcreech@gmail.com>
Date: Tue, 2 Nov 2010 18:29:08 -0400
> An upgrade from 2.6.34 to 2.6.35 caused networking to stop working on
> my MPC8313-based board. It turned out that TCP checksums were
> invalid, so I dug through the .35 changelog to try and isolate the
> reason. The change "tcp: Set CHECKSUM_UNNECESSARY in
> tcp_init_nondata_skb" seems to be the specific one that causes
> breakage - if I revert this one-liner, things work again:
>
> http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=2e8e18ef52e7dd1af0a3bd1f7d990a1d0b249586
>
> However, I also noticed that one of my boards was broken while a newer
> prototype (which is very similar, hardware-wise) was not. It turns
> out they're using 2 different revisions of silicon, so the broken
> board still has a 1.0 version microcontroller.
>
> Therefore I'm guessing (just a hunch) that the root cause of the
> problem is MPC8313 errata eTSEC12:
>
> ========
> eTSEC12: Tx IP and TCP/UDP Checksum Generation not supported for some Tx FCB
> offsets
> Description:
> If the Tx FCB (Frame Control Block) 32-byte offset is 0x19, 0x1A, 0x1B,
> 0x1C, 0x1D, 0x1E or 0x1F, IP and TCP/UDP header checksum generation do
> not function properly. The checksum value may be inserted in the wrong
> location or not inserted at all.
> IP and TCP/UDP header checksum generation is not supported in LINUX
> and other systems in which headers are prepended to pre-aligned packet
> data, or where the alignment of the Tx FCB cannot be controlled.
> This behavior applies to pseudo-header checksum insertion as well as
> checksum generation.
> Workaround:
> Align Tx FCB to a 16 or 32-byte boundary.
> If the alignment of TxFCB is not controllable, set TCTRL[TUCSEN]=0 and
> TCTRL[IPCSEN]=0 to disable IP and TCP/UDP header checksum generation.
> Fix plan:
> Fixed in Rev 2.0
> ========
>
> This appears to have been working previously, but doesn't work any
> more. I'm not familiar enough with Dave's checksum/sk_buff changes to
> figure out whether this errata is to blame, though, or how I should
> fix it if it is. Presumably there's some alignment magic needed in
> the sk_buff or gfar_add_fcb() to make sure that the microcontroller is
> happy with the FCB offset?
>
> Any tip on how I can solve this, or at least verify that this errata
> is at fault? Thanks in advance
Can someone please follow up Matthew to get this bug resolved? It has
been sitting around for a long time.
I suspect the gianfar driver, for these chip revisions, will need to
do a software checksum when the offset matches the criteria mentioned
in the errata above.
^ permalink raw reply
* Re: [PATCH] powerpc: fix call to subpage_protection()
From: Jim Keniston @ 2010-11-18 18:23 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <13149.1290047579@neuling.org>
[-- Attachment #1: Type: text/plain, Size: 2938 bytes --]
On Thu, 2010-11-18 at 13:32 +1100, Michael Neuling wrote:
> In:
> powerpc/mm: Fix pgtable cache cleanup with CONFIG_PPC_SUBPAGE_PROT
> commit d28513bc7f675d28b479db666d572e078ecf182d
> Author: David Gibson <david@gibson.dropbear.id.au>
>
> subpage_protection() was changed to to take an mm rather a pgdir but it
> didn't change calling site in hashpage_preload(). The change wasn't
> noticed at compile time since hashpage_preload() used a void* as the
> parameter to subpage_protection().
>
> This is obviously wrong and can trigger the following crash when
> CONFIG_SLAB, CONFIG_DEBUG_SLAB, CONFIG_PPC_64K_PAGES
> CONFIG_PPC_SUBPAGE_PROT are enabled.
>
...
>
> The following changes this subpage_protection() call.
>
> Reported-by: Jim Keniston <jkenisto@linux.vnet.ibm.com>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
> Tested-by: Jim Keniston <jkenisto@linux.vnet.ibm.com>
> cc: David Gibson <david@gibson.dropbear.id.au>
> cc: stable@kernel.org (only 2.6.33 and newer)
> ---
> > It boots fine with pseries_defconfig.
> >
> > Attached is the config file that I've been using, which is probably
> > descended over many generations of kernels from some config file in my
> > machine's distant past. (Enable DEBUG_SLAB or DEBUG_PAGEALLOC and it
> > will fail to boot.) After I run 'make menuconfig' starting from
> > pseries_defconfig...
> > $ diff config_ok .config | wc -l
> > 2052
>
> I narrowed this down to adding the following on pseries_defconfig:
> +CONFIG_SLAB=y
> +CONFIG_PPC_64K_PAGES=y
> +CONFIG_PPC_SUBPAGE_PROT=y
> +CONFIG_DEBUG_SLAB=y
> To reproduce the fail.
I have indeed verified that when I apply those config changes atop
pseries_defconfig, the resulting kernel fails to boot on my Power 5
system without this fix, and boots correctly with this fix. So the
Tested-by line is correct.
Unfortunately, this fix doesn't enable my legacy configuration to boot
with CONFIG_SLAB=y. It still fails in the same way -- console output
attached.
FWIW, this failure isn't an obstacle for me. I'm in no way attached to
my legacy configuration; pseries_defconfig is fine for me. On the other
hand, I can continue testing fixes, and/or make my system available to
other IBMers when I'm not using it, if you want to continue to pursue
this problem.
Thanks.
Jim
>
>
> diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
> index 83f534d..5e95844 100644
> --- a/arch/powerpc/mm/hash_utils_64.c
> +++ b/arch/powerpc/mm/hash_utils_64.c
> @@ -1123,7 +1123,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
> else
> #endif /* CONFIG_PPC_HAS_HASH_64K */
> rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
> - subpage_protection(pgdir, ea));
> + subpage_protection(mm, ea));
>
> /* Dump some info in case of hash insertion failure, they should
> * never happen so it is really useful to know if/when they do
>
>
[-- Attachment #2: linus-oops6 --]
[-- Type: text/plain, Size: 8783 bytes --]
This is with Michael Neuling's subpage_protection fix, using my legacy
.config DEBUG_SLAB configured.
boot: linus
Using 0084e28a bytes for initrd buffer
Please wait, loading kernel...
Allocated 00f00000 bytes for kernel @ 01e00000
Elf64 kernel loaded...
Loading ramdisk...
ramdisk loaded 0084e28a @ 02d00000
OF stdout device is: /vdevice/vty@30000000
Preparing to boot Linux version 2.6.37-rc2-5-ppc64 (jimk@elm3b90) (gcc version 4.3.2 [gcc-4_3-branch revision 141291] (SUSE Linux) ) #9 SMP Wed Nov 17 18:17:23 PST 2010
Max number of cores passed to firmware: 512 (NR_CPUS = 1024)
Calling ibm,client-architecture-support... not implemented
command line: root=/dev/disk/by-id/scsi-SIBM_ST373453LC_3HW1CQ1400007445Q2A4-part3 quiet profile=2 sysrq=1 insmod=sym53c8xx insmod=ipr crashkernel=256M-:128M loglevel=8
memory layout at init:
memory_limit : 0000000000000000 (16 MB aligned)
alloc_bottom : 0000000003550000
alloc_top : 0000000008000000
alloc_top_hi : 0000000070000000
amo_top : 0000000008000000
ram_top : 0000000070000000
instantiating rtas at 0x00000000076a0000... done
boot cpu hw idx 0
starting cpu hw idx 2... done
copying OF device tree...
Building dt strings...
Building dt structure...
Device tree strings 0x0000000003560000 -> 0x000000000356129c
Device tree struct 0x0000000003570000 -> 0x0000000003580000
Calling quiesce...
returning from prom_init
Crash kernel location must be 0x2000000
Reserving 128MB of memory at 32MB for crashkernel (System RAM: 1792MB)
Phyp-dump not supported on this hardware
Allocated 655360 bytes for 1024 pacas at c000000001f30000
Using pSeries machine description
Page orders: linear mapping = 24, virtual = 12, io = 12
Found initrd at 0xc000000002d00000:0xc00000000354e28a
bootconsole [udbg0] enabled
Partition configured for 4 cpus.
CPU maps initialized for 2 threads per core
(thread shift is 1)
Freed 589824 bytes for unused pacas
Starting Linux PPC64 #9 SMP Wed Nov 17 18:17:23 PST 2010
-----------------------------------------------------
ppc64_pft_size = 0x19
physicalMemorySize = 0x70000000
htab_hash_mask = 0x3ffff
-----------------------------------------------------
Initializing cgroup subsys cpuset
Initializing cgroup subsys cpu
Linux version 2.6.37-rc2-5-ppc64 (jimk@elm3b90) (gcc version 4.3.2 [gcc-4_3-branch revision 141291] (SUSE Linux) ) #9 SMP Wed Nov 17 18:17:23 PST 2010
[boot]0012 Setup Arch
Node 0 Memory: 0x0-0x70000000
PCI host bridge /pci@800000020000002 ranges:
IO 0x000003fe00200000..0x000003fe002fffff -> 0x0000000000000000
MEM 0x0000040080000000..0x00000400bfffffff -> 0x00000000c0000000
PCI host bridge /pci@800000020000003 ranges:
IO 0x000003fe00700000..0x000003fe007fffff -> 0x0000000000000000
MEM 0x00000401c0000000..0x00000401ffffffff -> 0x00000000c0000000
EEH: PCI Enhanced I/O Error Handling Enabled
PPC64 nvram contains 7168 bytes
Using dedicated idle loop
Zone PFN ranges:
DMA 0x00000000 -> 0x00007000
Normal empty
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
0: 0x00000000 -> 0x00007000
On node 0 totalpages: 28672
DMA zone: 25 pages used for memmap
DMA zone: 0 pages reserved
DMA zone: 28647 pages, LIFO batch:1
[boot]0015 Setup Done
PERCPU: Embedded 1 pages/cpu @c000000000f00000 s23424 r0 d42112 u262144
pcpu-alloc: s23424 r0 d42112 u262144 alloc=1*1048576
pcpu-alloc: [0] 0 1 2 3
Built 1 zonelists in Node order, mobility grouping on. Total pages: 28647
Policy zone: DMA
Kernel command line: root=/dev/disk/by-id/scsi-SIBM_ST373453LC_3HW1CQ1400007445Q2A4-part3 quiet profile=2 sysrq=1 insmod=sym53c8xx insmod=ipr crashkernel=256M-:128M loglevel=8
kernel profiling enabled (shift: 2)
PID hash table entries: 4096 (order: -1, 32768 bytes)
freeing bootmem node 0
Memory: 1681088k/1835008k available (8192k kernel code, 153920k reserved, 1536k data, 4447k bss, 512k init)
Hierarchical RCU implementation.
RCU-based detection of stalled CPUs is disabled.
NR_IRQS:512
[boot]0020 XICS Init
[boot]0021 XICS Done
pic: no ISA interrupt controller
time_init: decrementer frequency = 207.054000 MHz
time_init: processor frequency = 1654.344000 MHz
clocksource: timebase mult[135191e] shift[22] registered
clockevent: decrementer mult[35017dae] shift[32] cpu[0]
Console: colour dummy device 80x25
console [hvc0] enabled, bootconsole disabled
console [hvc0] enabled, bootconsole disabled
allocated 1146880 bytes of page_cgroup
please try 'cgroup_disable=memory' option if you don't want memory cgroups
pid_max: default: 32768 minimum: 301
Security Framework initialized
SELinux: Disabled at boot.
Dentry cache hash table entries: 262144 (order: 5, 2097152 bytes)
Inode-cache hash table entries: 131072 (order: 4, 1048576 bytes)
Mount-cache hash table entries: 4096
Initializing cgroup subsys ns
ns_cgroup deprecated: consider using the 'clone_children' flag without the ns_cgroup.
Initializing cgroup subsys cpuacct
Initializing cgroup subsys memory
Initializing cgroup subsys devices
Initializing cgroup subsys freezer
irq: irq 2 on host null mapped to virtual irq 16
Brought up 4 CPUs
Node 0 CPUs: 0-3
NET: Registered protocol family 16
IBM eBus Device Driver
POWER5 performance monitor hardware support registered
PCI: Probing PCI hardware
IOMMU table initialized, virtual merging enabled
pci 0000:c0:01.0: PME# supported from D0 D3hot D3cold
pci 0000:c0:01.0: PME# disabled
pci 0000:c0:01.1: PME# supported from D0 D3hot D3cold
pci 0000:c0:01.1: PME# disabled
irq: irq 115 on host null mapped to virtual irq 115
irq: irq 116 on host null mapped to virtual irq 116
pci 0001:cc:01.0: supports D1
irq: irq 150 on host null mapped to virtual irq 150
irq: irq 151 on host null mapped to virtual irq 151
PCI: Probing PCI hardware done
bio: create slab <bio-0> at 0
vgaarb: loaded
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Switching to clocksource timebase
NET: Registered protocol family 2
IP route cache hash table entries: 16384 (order: 1, 131072 bytes)
TCP established hash table entries: 65536 (order: 4, 1048576 bytes)
TCP bind hash table entries: 65536 (order: 4, 1048576 bytes)
TCP: Hash tables configured (established 65536 bind 65536)
TCP reno registered
UDP hash table entries: 2048 (order: 0, 65536 bytes)
UDP-Lite hash table entries: 2048 (order: 0, 65536 bytes)
NET: Registered protocol family 1
PCI: CLS 128 bytes, default 128
Unpacking initramfs...
Initramfs unpacking failed: read error
RTAS daemon started
irq: irq 655360 on host null mapped to virtual irq 17
irq: irq 589825 on host null mapped to virtual irq 18
audit: initializing netlink socket (disabled)
type=2000 audit(1290100141.460:1): initialized
HugeTLB registered 16 MB page size, pre-allocated 0 pages
VFS: Disk quotas dquot_6.5.2
Dquot-cache hash table entries: 8192 (order 0, 65536 bytes)
msgmni has been set to 3284
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
pci_hotplug: PCI Hot Plug PCI Core version: 0.5
rpaphp: RPA HOT Plug PCI Controller Driver version: 0.1
rpaphp: Slot [U787A.001.DNZ00XZ-P1-C1] registered
vio_register_driver: driver hvc_console registering
HVSI: registered 0 devices
Generic RTC Driver v1.07
Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)
Uniform Multi-Platform E-IDE driver
ide-gd driver 1.18
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
mice: PS/2 mouse device common for all mice
EDAC MC: Ver: 2.1.0 Nov 17 2010
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
TCP cubic registered
NET: Registered protocol family 15
registered taskstats version 1
md: Waiting for all devices to be available before autodetect
md: If you don't use raid, use raid=noautodetect
md: Autodetecting RAID arrays.
md: Scanned 0 and added 0 devices.
md: autorun ...
md: ... autorun DONE.
VFS: Cannot open root device "disk/by-id/scsi-SIBM_ST373453LC_3HW1CQ1400007445Q2A4-part3" or unknown-block(0,0)
Please append a correct "root=" boot option; here are the available partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
Call Trace:
[c00000006e78fc30] [c000000000011218] .show_stack+0x6c/0x16c (unreliable)
[c00000006e78fce0] [c00000000054b204] .panic+0x9c/0x200
[c00000006e78fd80] [c000000000781354] .mount_block_root+0x2dc/0x318
[c00000006e78fe50] [c00000000078159c] .prepare_namespace+0x184/0x1cc
[c00000006e78fee0] [c000000000780554] .kernel_init+0x2e4/0x310
[c00000006e78ff90] [c00000000002985c] .kernel_thread+0x54/0x70
Rebooting in 180 seconds..
^ permalink raw reply
* [PATCH] Powerpc: separate CONFIG_RELOCATABLE from CONFIG_CRASHDUMP in boot code
From: Sonny Rao @ 2010-11-18 10:35 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Sonny Rao, Paul Mackerras, linux-kernel, Milton Miller
Fix head_64.S so that we can build a relocatable kernel
that isn't necessarily a crash-dump kernel
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Sonny Rao <sonnyrao@linux.vnet.ibm.com>
---
arch/powerpc/kernel/head_64.S | 6 ++----
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index f0dd577..53b098f 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -96,7 +96,7 @@ __secondary_hold_acknowledge:
.llong hvReleaseData-KERNELBASE
#endif /* CONFIG_PPC_ISERIES */
-#ifdef CONFIG_CRASH_DUMP
+#ifdef CONFIG_RELOCATABLE
/* This flag is set to 1 by a loader if the kernel should run
* at the loaded address instead of the linked address. This
* is used by kexec-tools to keep the the kdump kernel in the
@@ -384,12 +384,10 @@ _STATIC(__after_prom_start)
/* process relocations for the final address of the kernel */
lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
sldi r25,r25,32
-#ifdef CONFIG_CRASH_DUMP
lwz r7,__run_at_load-_stext(r26)
- cmplwi cr0,r7,1 /* kdump kernel ? - stay where we are */
+ cmplwi cr0,r7,1 /* flagged to stay where we are ? */
bne 1f
add r25,r25,r26
-#endif
1: mr r3,r25
bl .relocate
#endif
--
1.5.6.5
^ permalink raw reply related
* [PATCH] powerpc: minor cleanups for machdep.h
From: Sonny Rao @ 2010-11-18 10:39 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Sonny Rao, Paul Mackerras, linux-kernel, Milton Miller
remove stale declaration of setup_pci_ptrs, aparently from ppc before 2.4.0
remove #ifdef around struct existance delcaration
fix spelling of linear
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Sonny Rao <sonnyrao@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/machdep.h | 6 +-----
1 files changed, 1 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index d045b01..8433d36 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -27,9 +27,7 @@ struct iommu_table;
struct rtc_time;
struct file;
struct pci_controller;
-#ifdef CONFIG_KEXEC
struct kimage;
-#endif
#ifdef CONFIG_SMP
struct smp_ops_t {
@@ -72,7 +70,7 @@ struct machdep_calls {
int psize, int ssize);
void (*flush_hash_range)(unsigned long number, int local);
- /* special for kexec, to be called in real mode, linar mapping is
+ /* special for kexec, to be called in real mode, linear mapping is
* destroyed as well */
void (*hpte_clear_all)(void);
@@ -324,8 +322,6 @@ extern sys_ctrler_t sys_ctrler;
#endif /* CONFIG_PPC_PMAC */
-extern void setup_pci_ptrs(void);
-
#ifdef CONFIG_SMP
/* Poor default implementations */
extern void __devinit smp_generic_give_timebase(void);
--
1.5.6.5
^ permalink raw reply related
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