* [PATCH 5/9] powerpc: Don't silently handle machine checks from userspace
From: Anton Blanchard @ 2011-01-12 5:48 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
In-Reply-To: <20110112164318.753a435b@kryten>
If a machine check comes from userspace we send a SIGBUS to the task and
fail to printk anything.
If we are taking machine checks due to bad hardware we want to know about
it right away. Furthermore if we don't complain loudly then it will look
a lot like a bug in the userspace application, potentially causing a lot
of confusion.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
I seem to remember this might be here for X on 32bit. If necessary I can
wrap it in an ifdef CONFIG_PPC32.
Index: powerpc.git/arch/powerpc/kernel/traps.c
===================================================================
--- powerpc.git.orig/arch/powerpc/kernel/traps.c 2011-01-11 13:46:47.391281975 +1100
+++ powerpc.git/arch/powerpc/kernel/traps.c 2011-01-11 13:46:49.141336198 +1100
@@ -626,11 +626,6 @@ void machine_check_exception(struct pt_r
if (recover > 0)
return;
- if (user_mode(regs)) {
- _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
- return;
- }
-
#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
/* the qspan pci read routines can cause machine checks -- Cort
*
^ permalink raw reply
* [PATCH 4/9] powerpc: Remove duplicate debugger hook in machine_check_exception
From: Anton Blanchard @ 2011-01-12 5:47 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
In-Reply-To: <20110112164318.753a435b@kryten>
We are calling debugger_fault_handler twice in machine_check_exception.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: powerpc.git/arch/powerpc/kernel/traps.c
===================================================================
--- powerpc.git.orig/arch/powerpc/kernel/traps.c 2011-01-11 13:46:42.601133580 +1100
+++ powerpc.git/arch/powerpc/kernel/traps.c 2011-01-11 13:46:47.391281975 +1100
@@ -648,8 +648,6 @@ void machine_check_exception(struct pt_r
if (check_io_access(regs))
return;
- if (debugger_fault_handler(regs))
- return;
die("Machine check", regs, SIGBUS);
/* Must die if the interrupt is not recoverable */
^ permalink raw reply
* [PATCH 3/9] powerpc: Never halt RTAS error logging after receiving an unrecoverable machine check
From: Anton Blanchard @ 2011-01-12 5:46 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
In-Reply-To: <20110112164318.753a435b@kryten>
Newer versions of the System p firwmare send a partial RTAS error log in the
machine check handler with a more detailed response appearing sometime later
via check event.
This means at machine check time we do not have enough information to
ascertain exactly what went on. Furthermore, I have found the RTAS error
logs in the machine check handler contain no useful information, so halting on
them makes little sense. If we want to halt it would make more sense to do
it following the error log received sometime later via check event.
In light of this, never halt the error log in the pseries machine
check handler.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: powerpc.git/arch/powerpc/platforms/pseries/ras.c
===================================================================
--- powerpc.git.orig/arch/powerpc/platforms/pseries/ras.c 2010-09-27 21:19:32.805480948 +1000
+++ powerpc.git/arch/powerpc/platforms/pseries/ras.c 2010-10-15 13:23:34.161268941 +1100
@@ -281,7 +281,7 @@ static int recover_mce(struct pt_regs *r
nonfatal = 1;
}
- log_error((char *)err, ERR_TYPE_RTAS_LOG, !nonfatal);
+ log_error((char *)err, ERR_TYPE_RTAS_LOG, 0);
return nonfatal;
}
^ permalink raw reply
* [PATCH 2/9] powerpc: Don't force MSR_RI in machine_check_exception
From: Anton Blanchard @ 2011-01-12 5:45 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
In-Reply-To: <20110112164318.753a435b@kryten>
We should never force MSR_RI on. If we take a machine check with MSR_RI off
then we have no chance of recovering safely.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: powerpc.git/arch/powerpc/kernel/traps.c
===================================================================
--- powerpc.git.orig/arch/powerpc/kernel/traps.c 2011-01-11 13:46:39.541038778 +1100
+++ powerpc.git/arch/powerpc/kernel/traps.c 2011-01-11 13:46:42.601133580 +1100
@@ -627,7 +627,6 @@ void machine_check_exception(struct pt_r
return;
if (user_mode(regs)) {
- regs->msr |= MSR_RI;
_exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
return;
}
@@ -643,10 +642,8 @@ void machine_check_exception(struct pt_r
return;
#endif
- if (debugger_fault_handler(regs)) {
- regs->msr |= MSR_RI;
+ if (debugger_fault_handler(regs))
return;
- }
if (check_io_access(regs))
return;
^ permalink raw reply
* [PATCH 1/9] powerpc: Print 32 bits of DSISR in show_regs
From: Anton Blanchard @ 2011-01-12 5:44 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
In-Reply-To: <20110112164318.753a435b@kryten>
We were printing 64 bits of DSISR in show_regs even though it is 32 bit.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: powerpc.git/arch/powerpc/kernel/process.c
===================================================================
--- powerpc.git.orig/arch/powerpc/kernel/process.c 2010-10-15 13:23:24.911164446 +1100
+++ powerpc.git/arch/powerpc/kernel/process.c 2010-10-15 13:23:28.611206248 +1100
@@ -631,7 +631,7 @@ void show_regs(struct pt_regs * regs)
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
#else
- printk("DAR: "REG", DSISR: "REG"\n", regs->dar, regs->dsisr);
+ printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr);
#endif
printk("TASK = %p[%d] '%s' THREAD: %p",
current, task_pid_nr(current), current->comm, task_thread_info(current));
^ permalink raw reply
* [PATCH 0/9] Machine check handling fixes
From: Anton Blanchard @ 2011-01-12 5:43 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
Here are a number of fixes to our machine check handling, found when
testing our memory uncorrectable error handling.
Anton
^ permalink raw reply
* [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2011-01-12 0:16 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, Andrew Morton, Linux Kernel list
Hi Linus !
Here's the powerpc bunch for this merge window. Small this time, looks
like Kumar was too busy with holidays to send me anything from freescale
this time around.
There's some rework & cleanup of our nvram code, some support for the
POWER7+ processors, various iommu cleanups, etc... in terms of features,
we can note the support for some of IBM System P energy management and
VPHN feature which improves NUMA topology informations under our
hypervisor.
The following changes since commit 5b2eef966cb2ae307aa4ef1767f7307774bc96ca:
Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 (2011-01-10 17:11:39 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next
Anatolij Gustschin (1):
powerpc/5xxx: extend mpc8xxx_gpio driver to support mpc512x gpios
Andreas Schwab (2):
powerpc: Fix PPC_PTRACE_SETHWDEBUG on PPC_BOOK3S
powerpc: Update compat_arch_ptrace
Anton Blanchard (5):
powerpc: Add support for popcnt instructions
powerpc/kdump: Override crash_free_reserved_phys_range to avoid freeing RTAS
powerpc: Hardcode popcnt instructions for old assemblers
powerpc: Fix incorrect comment about interrupt stack allocation
powerpc: iommu: Add device name to iommu error printks
Benjamin Herrenschmidt (16):
powerpc/nvram: Move things out of asm/nvram.h
powerpc/nvram: More flexible nvram_create_partition()
powerpc/nvram: nvram_create_partitions() now uses bytes
powerpc/nvram: Ensure that the partition header/block size is right
powerpc/nvram: Completely clear a new partition
powerpc/nvram: Shuffle code around in nvram_create_partition()
powerpc/nvram: Improve partition removal
powerpc/nvram: Add nvram_find_partition()
powerpc/nvram: Change nvram_setup_partition() to use new helper
powerpc/nvram: Move the log partition stuff to pseries
powerpc/nvram: Rename ppc64,linux partition to ibm,rtas-log
Merge branch 'nvram' into next
Merge remote branch 'jwb/next' into next
powerpc/pseries: Pass phb only to iommu_table_setparms_lpar
Merge remote branch 'gcl/next' into next
powerpc/pseries: Fix build of topology stuff without CONFIG_NUMA
Christian Dietrich (1):
powerpc: Removing undead ifdef __KERNEL__
FUJITA Tomonori (1):
powerpc: enable ARCH_DMA_ADDR_T_64BIT with ARCH_PHYS_ADDR_T_64BIT
Grant Likely (1):
Merge v2.6.37-rc8 into powerpc/next
Heiko Schocher (1):
powerpc/time: printk time stamp init not correct
Ilya Yanok (6):
powerpc/512x: scatter/gather dma fix
powerpc/512x: fix the hanged dma transfer issue
powerpc/512x: add MPC8308 dma support
powerpc/512x: try to free dma descriptors in case of allocation failure
powerpc/83xx: add DMA controller to mpc8308 device-tree node
powerpc/83xx: add mpc8308_p1m DMA controller device-tree node
Jesper Juhl (3):
powerpc/cell: Use vzalloc rather than vmalloc and memset in spu_alloc_lscsa_std
powerpc/iseries: Remove unused mf_getSrcHistory function and caller.
powerpc: Remove unnecessary casts of void ptr
Jesse Larrew (4):
powerpc: Add VPHN firmware feature
powerpc/pseries: Poll VPA for topology changes and update NUMA maps
powerpc: Disable VPHN polling during a suspend operation
powerpc/pseries: Fix VPHN build errors on non-SMP systems
Jim Keniston (2):
powerpc/nvram: Fix NVRAM partition list setup
powerpc/nvram: Handle partition names >= 12 chars
Joe Perches (2):
drivers/char/hvc_vio: Use static const char arrays
powerpc/pci: Use printf extension %pR for struct resource
Lennert Buytenhek (1):
powerpc: Fix two typos in Documentation/powerpc/booting-without-of.txt
Marc Zyngier (1):
powerpc/powermac: Make auto-loading of therm_pm72 possible
Michael Ellerman (2):
powerpc: Consolidate obj-y assignments
powerpc: Record vma->phys_addr in ioremap()
Michael Neuling (4):
powerpc: Remove unneeded cpu_setup/restore from POWER7 cputable entry
powerpc: Remove POWER6 oprofile workarounds for POWER7
powerpc: Add POWER7+ cputable entry
powerpc/mm: Avoid avoidable void* pointer
Nishanth Aravamudan (11):
powerpc/vio: Use dma ops helpers
powerpc/pasemi: Clean up pasemi iommu table initializations
powerpc/cell: Beat dma ops cleanup
powerpc/dart: iommu table cleanup
powerpc/pseries: iommu cleanup
powerpc/macio: Ensure all dma routines get copied over
powerpc: Add memory_hotplug_max()
powerpc/iommu: Use coherent_dma_mask for alloc_coherent
powerpc/pseries: Do not search for dma-window property on dlpar remove
powerpc/pseries: Checking for pdn->parent is redundant
powerpc/pseries: Do not need to check for dma_window == NULL
Sebastian Siewior (1):
of/address: Use propper endianess in get_flags
Sonny Rao (2):
Powerpc: separate CONFIG_RELOCATABLE from CONFIG_CRASHDUMP in boot code
powerpc: Minor cleanups for machdep.h
Srikanth Krishnakar (1):
rtc-cmos.c : Fix warning on PowerPC
Stephen Rothwell (1):
powerpc: Remove second definition of STACK_FRAME_OVERHEAD
Tracey Dent (1):
powerpc/ps3: Replace the use of <module>-objs with <module>-y
Vaidyanathan Srinivasan (2):
powerpc: Cleanup APIs for cpu/thread/core mappings
powerpc: Add support for new hcall H_BEST_ENERGY
Victor Gallardo (3):
powerpc/4xx: Add suspend and idle support
powerpc/4xx: Add Kilauea suspend and idle support
powerpc/4xx: Add Canyonlands suspend and idle support
Will Schmidt (1):
powerpc/pseries: Add kernel parameter to disable batched hcalls
Documentation/kernel-parameters.txt | 8 +
Documentation/powerpc/booting-without-of.txt | 4 +-
Documentation/powerpc/dts-bindings/4xx/cpm.txt | 52 +++
arch/powerpc/Kconfig | 16 +-
arch/powerpc/boot/dts/canyonlands.dts | 31 +-
arch/powerpc/boot/dts/kilauea.dts | 9 +
arch/powerpc/boot/dts/mpc8308_p1m.dts | 8 +
arch/powerpc/boot/dts/mpc8308rdb.dts | 8 +
arch/powerpc/configs/40x/kilauea_defconfig | 5 +
arch/powerpc/configs/44x/canyonlands_defconfig | 3 +
arch/powerpc/include/asm/bitops.h | 9 +
arch/powerpc/include/asm/cputable.h | 9 +-
arch/powerpc/include/asm/cputhreads.h | 15 +-
arch/powerpc/include/asm/device.h | 6 +
arch/powerpc/include/asm/firmware.h | 3 +-
arch/powerpc/include/asm/hvcall.h | 4 +-
arch/powerpc/include/asm/lppaca.h | 5 +-
arch/powerpc/include/asm/machdep.h | 6 +-
arch/powerpc/include/asm/mmzone.h | 5 +
arch/powerpc/include/asm/nvram.h | 52 +--
arch/powerpc/include/asm/ppc-opcode.h | 8 +
arch/powerpc/include/asm/processor.h | 2 -
arch/powerpc/include/asm/prom.h | 2 +-
arch/powerpc/include/asm/topology.h | 15 +-
arch/powerpc/include/asm/vdso_datapage.h | 2 -
arch/powerpc/kernel/Makefile | 9 +-
arch/powerpc/kernel/asm-offsets.c | 1 -
arch/powerpc/kernel/cputable.c | 22 +-
arch/powerpc/kernel/crash_dump.c | 33 ++
arch/powerpc/kernel/dma-iommu.c | 2 +-
arch/powerpc/kernel/entry_32.S | 1 +
arch/powerpc/kernel/exceptions-64s.S | 1 +
arch/powerpc/kernel/fpu.S | 1 +
arch/powerpc/kernel/head_40x.S | 1 +
arch/powerpc/kernel/head_44x.S | 1 +
arch/powerpc/kernel/head_64.S | 7 +-
arch/powerpc/kernel/head_8xx.S | 1 +
arch/powerpc/kernel/head_fsl_booke.S | 1 +
arch/powerpc/kernel/iommu.c | 14 +-
arch/powerpc/kernel/misc.S | 5 -
arch/powerpc/kernel/misc_32.S | 1 +
arch/powerpc/kernel/misc_64.S | 1 +
arch/powerpc/kernel/nvram_64.c | 481 ++++++++---------------
arch/powerpc/kernel/pci_64.c | 3 +-
arch/powerpc/kernel/ppc_ksyms.c | 7 +
arch/powerpc/kernel/ppc_save_regs.S | 1 +
arch/powerpc/kernel/ptrace.c | 22 +-
arch/powerpc/kernel/ptrace32.c | 7 +
arch/powerpc/kernel/rtas.c | 3 +
arch/powerpc/kernel/setup_64.c | 4 +-
arch/powerpc/kernel/smp.c | 19 +-
arch/powerpc/kernel/time.c | 2 +-
arch/powerpc/kernel/vector.S | 1 +
arch/powerpc/kernel/vio.c | 15 +-
arch/powerpc/lib/Makefile | 2 +-
arch/powerpc/lib/hweight_64.S | 110 +++++
arch/powerpc/mm/hash_utils_64.c | 2 +-
arch/powerpc/mm/mmu_context_nohash.c | 12 +-
arch/powerpc/mm/numa.c | 311 ++++++++++++++-
arch/powerpc/mm/pgtable_32.c | 3 +-
arch/powerpc/mm/pgtable_64.c | 2 +
arch/powerpc/platforms/44x/Makefile | 5 +-
arch/powerpc/platforms/Kconfig | 7 +-
arch/powerpc/platforms/cell/beat_iommu.c | 3 +-
arch/powerpc/platforms/cell/spufs/lscsa_alloc.c | 3 +-
arch/powerpc/platforms/chrp/time.c | 4 +
arch/powerpc/platforms/iseries/mf.c | 62 ---
arch/powerpc/platforms/pasemi/iommu.c | 19 +-
arch/powerpc/platforms/powermac/setup.c | 9 +
arch/powerpc/platforms/pseries/Kconfig | 10 +
arch/powerpc/platforms/pseries/Makefile | 1 +
arch/powerpc/platforms/pseries/firmware.c | 1 +
arch/powerpc/platforms/pseries/hvCall.S | 1 +
arch/powerpc/platforms/pseries/iommu.c | 49 +--
arch/powerpc/platforms/pseries/lpar.c | 12 +
arch/powerpc/platforms/pseries/nvram.c | 205 ++++++++++
arch/powerpc/platforms/pseries/pseries_energy.c | 326 +++++++++++++++
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/dart_iommu.c | 9 +-
arch/powerpc/sysdev/mpc8xxx_gpio.c | 75 ++++-
arch/powerpc/sysdev/ppc4xx_cpm.c | 346 ++++++++++++++++
arch/powerpc/sysdev/tsi108_dev.c | 8 +-
drivers/char/hvc_vio.c | 2 +-
drivers/dma/Kconfig | 2 +-
drivers/dma/mpc512x_dma.c | 187 ++++++---
drivers/macintosh/macio_asic.c | 7 +-
drivers/macintosh/therm_pm72.c | 30 +--
drivers/of/address.c | 54 ++--
drivers/ps3/Makefile | 2 +-
drivers/rtc/rtc-cmos.c | 3 +-
include/linux/of_address.h | 6 +-
91 files changed, 2103 insertions(+), 742 deletions(-)
create mode 100644 Documentation/powerpc/dts-bindings/4xx/cpm.txt
create mode 100644 arch/powerpc/lib/hweight_64.S
create mode 100644 arch/powerpc/platforms/pseries/pseries_energy.c
create mode 100644 arch/powerpc/sysdev/ppc4xx_cpm.c
^ permalink raw reply
* Re: [PATCH 00/13] powerpc: Backport 8xx TLB to 2.4
From: Joakim Tjernlund @ 2011-01-11 20:27 UTC (permalink / raw)
To: Willy Tarreau; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <20110111200853.GA21915@1wt.eu>
Willy Tarreau <w@1wt.eu> wrote on 2011/01/11 21:08:53:
>
> On Tue, Jan 11, 2011 at 09:12:44AM +0100, Joakim Tjernlund wrote:
> > Willy Tarreau <w@1wt.eu> wrote on 2011/01/11 07:09:26:
> > >
> > > Hi Joakim,
> > >
> > > On Mon, Jan 10, 2011 at 10:37:46PM +0100, Joakim Tjernlund wrote:
> > > > This is a backport from 2.6 which I did to overcome 8xx CPU
> > > > bugs. 8xx does not update the DAR register when taking a TLB
> > > > error caused by dcbX and icbi insns which makes it very
> > > > tricky to use these insns. Also the dcbst wrongly sets the
> > > > the store bit when faulting into DTLB error.
> > > > A few more bugs very found during development.
> > > >
> > > > I know 2.4 is in strict maintenance mode and 8xx is obsolete
> > > > but as it is still in use I wanted 8xx to age with grace.
> > >
> > > Thank you very much for taking care of this, that's very much appreciated.
> > > I'll look at this ASAP. Just a quick question in order to be certain, did
> > > you have the opportunity to test all of these changes on real hardware ?
> >
> > I tested these on real 8xx HW but I used an older 2.4 linux as we haven't
> > moved forward on 2.4 for quite some time.
> > The affected files were almost identical though.
>
> OK thank you for this precision. If you remember what version it was, we can
> also diff it against mainline and see if we spot any relevant changes that
> we need to take care of.
2.4.21-rc6 is the base version. The we have added bits and pieces.
>
> > Would be great if Scott could give them a spin on 8xx with current 2.4.
>
> Indeed, that would be great. My goal really is that 2.4 users can upgrade
> without wondering about any risk of regression. I appreciate a lot your
> fixes, they mean some people might see that some issues have suddenly
> disappeared. But it's important to stay on the non-reg side as much as
> possible.
Should be faster too :)
^ permalink raw reply
* Re: [PATCH 00/13] powerpc: Backport 8xx TLB to 2.4
From: Willy Tarreau @ 2011-01-11 20:08 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <OFEC114402.5A694921-ONC1257815.002CC8F2-C1257815.002D1C7D@transmode.se>
On Tue, Jan 11, 2011 at 09:12:44AM +0100, Joakim Tjernlund wrote:
> Willy Tarreau <w@1wt.eu> wrote on 2011/01/11 07:09:26:
> >
> > Hi Joakim,
> >
> > On Mon, Jan 10, 2011 at 10:37:46PM +0100, Joakim Tjernlund wrote:
> > > This is a backport from 2.6 which I did to overcome 8xx CPU
> > > bugs. 8xx does not update the DAR register when taking a TLB
> > > error caused by dcbX and icbi insns which makes it very
> > > tricky to use these insns. Also the dcbst wrongly sets the
> > > the store bit when faulting into DTLB error.
> > > A few more bugs very found during development.
> > >
> > > I know 2.4 is in strict maintenance mode and 8xx is obsolete
> > > but as it is still in use I wanted 8xx to age with grace.
> >
> > Thank you very much for taking care of this, that's very much appreciated.
> > I'll look at this ASAP. Just a quick question in order to be certain, did
> > you have the opportunity to test all of these changes on real hardware ?
>
> I tested these on real 8xx HW but I used an older 2.4 linux as we haven't
> moved forward on 2.4 for quite some time.
> The affected files were almost identical though.
OK thank you for this precision. If you remember what version it was, we can
also diff it against mainline and see if we spot any relevant changes that
we need to take care of.
> Would be great if Scott could give them a spin on 8xx with current 2.4.
Indeed, that would be great. My goal really is that 2.4 users can upgrade
without wondering about any risk of regression. I appreciate a lot your
fixes, they mean some people might see that some issues have suddenly
disappeared. But it's important to stay on the non-reg side as much as
possible.
Thanks,
Willy
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/boot/dts: Install dts from the right directory
From: Gerhard Pircher @ 2011-01-11 19:05 UTC (permalink / raw)
To: Ben Hutchings, paulus, benh; +Cc: linuxppc-dev
In-Reply-To: <1294532641.3283.70.camel@localhost>
-------- Original-Nachricht --------
> Datum: Sun, 09 Jan 2011 00:24:01 +0000
> Von: Ben Hutchings <ben@decadent.org.uk>
> An: Benjamin Herrenschmidt <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>
> CC: Gerhard Pircher <gerhard_pircher@gmx.net>, linuxppc-dev@lists.ozlabs.org
> Betreff: [PATCH 1/2] powerpc/boot/dts: Install dts from the right directory
> The dts-installed variable is initialised using a wildcard path that
> will be expanded relative to the build directory. Use the existing
> variable dtstree to generate an absolute wildcard path that will work
> when building in a separate directory.
Wouldn't this patch be a good candidate for the stable kernel series?
> Reported-by: Gerhard Pircher <gerhard_pircher@gmx.net>
> Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
> Tested-by: Gerhard Pircher <gerhard_pircher@gmx.net> [against 2.6.32]
> ---
> arch/powerpc/boot/Makefile | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
> index 96deec6..8917816 100644
> --- a/arch/powerpc/boot/Makefile
> +++ b/arch/powerpc/boot/Makefile
> @@ -368,7 +368,7 @@ INSTALL := install
> extra-installed := $(patsubst $(obj)/%, $(DESTDIR)$(WRAPPER_OBJDIR)/%,
> $(extra-y))
> hostprogs-installed := $(patsubst %, $(DESTDIR)$(WRAPPER_BINDIR)/%,
> $(hostprogs-y))
> wrapper-installed := $(DESTDIR)$(WRAPPER_BINDIR)/wrapper
> -dts-installed := $(patsubst $(obj)/dts/%, $(DESTDIR)$(WRAPPER_DTSDIR)/%,
> $(wildcard $(obj)/dts/*.dts))
> +dts-installed := $(patsubst $(dtstree)/%, $(DESTDIR)$(WRAPPER_DTSDIR)/%,
> $(wildcard $(dtstree)/*.dts))
>
> all-installed := $(extra-installed) $(hostprogs-installed)
> $(wrapper-installed) $(dts-installed)
>
> --
> 1.7.2.3
Gerhard
--
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^ permalink raw reply
* Re: mpc880 linux-2.6.32 slow running processes
From: Joakim Tjernlund @ 2011-01-11 16:00 UTC (permalink / raw)
Cc: michael, linuxppc-dev, RFeany, scottwood, Rafael Beims
In-Reply-To: <OFCA182CE3.B20BFA9C-ONC1257814.005C7CE1-C1257814.005CF1A7@transmode.se>
> Sent by: linuxppc-dev-bounces+joakim.tjernlund=transmode.se@lists.ozlabs.org
>
> Rafael Beims <rbeims@gmail.com> wrote on 2011/01/10 17:35:38:
> > >
> > > Once you have tested it and it works, please send a patch to remove the 8xx workaround.
> > > Make sure Scott is cc:ed
> > >
> > >
> >
> > I tested linux-2.6.33 on my ppc880 board today, and even without the
> > slowdown.patch applied, the board runs processes with good
> > performance.
> > It really seems that the problem is solved from linux-2.6.33 on.
> >
> > I'm not sure what you mean by sending a patch to remove the
> > workaround. The only thing that I did in the 2.6.32 version was to
> > apply the slowdown.patch attached in the message from Michael.
> >
> > Could you clarify please?
>
> Yes, this part in arch/powerpc/mm/pgtable.c:
> #ifdef CONFIG_8xx
> /* On 8xx, cache control instructions (particularly
> * "dcbst" from flush_dcache_icache) fault as write
> * operation if there is an unpopulated TLB entry
> * for the address in question. To workaround that,
> * we invalidate the TLB here, thus avoiding dcbst
> * misbehaviour.
> */
> /* 8xx doesn't care about PID, size or ind args */
> _tlbil_va(addr, 0, 0, 0);
> #endif /* CONFIG_8xx */
>
> Should be removed in >= 2.6.33 kernels.
> My 8xx TLB work fixes this problem more efficiently.
Can you test these 2 patches on recent 2.6 linux:
>From 9024200169bf86b4f34cb3b1ebf68e0056237bc0 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Tue, 11 Jan 2011 13:43:42 +0100
Subject: [PATCH 1/2] powerpc: Move 8xx invalidation of non present TLBs
8xx does not invalidate ~PRESENT TLBs, move the workaround
in mm/fault.c here to keep 8xx quirks localized and expedite
the invalidation faster.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/powerpc/kernel/head_8xx.S | 12 ++++++++++--
arch/powerpc/mm/fault.c | 6 ------
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1f1a04b..6cd99e2 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -221,7 +221,11 @@ DataAccess:
stw r10,_DSISR(r11)
mr r5,r10
mfspr r4,SPRN_DAR
- li r10,0x00f0
+ /* invalidate ~PRESENT TLBs, 8xx MMU don't do this */
+ andis. r10,r5,0x4000
+ beq+ 1f
+ tlbie r4
+1: li r10,0x00f0
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
EXC_XFER_EE_LITE(0x300, handle_page_fault)
@@ -234,7 +238,11 @@ InstructionAccess:
EXCEPTION_PROLOG
mr r4,r12
mr r5,r9
- EXC_XFER_EE_LITE(0x400, handle_page_fault)
+ /* invalidate ~PRESENT TLBs, 8xx MMU don't do this */
+ andis. r10,r5,0x4000
+ beq+ 1f
+ tlbie r4
+1: EXC_XFER_EE_LITE(0x400, handle_page_fault)
/* External interrupt */
EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 1bd712c..31226c8 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -247,12 +247,6 @@ good_area:
goto bad_area;
#endif /* CONFIG_6xx */
#if defined(CONFIG_8xx)
- /* 8xx sometimes need to load a invalid/non-present TLBs.
- * These must be invalidated separately as linux mm don't.
- */
- if (error_code & 0x40000000) /* no translation? */
- _tlbil_va(address, 0, 0, 0);
-
/* The MPC8xx seems to always set 0x80000000, which is
* "undefined". Of those that can be set, this is the only
* one which seems bad.
--
1.7.3.4
and
>From 0ef93601290a75b087495dddeee6062a870f1dc6 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Tue, 11 Jan 2011 13:55:22 +0100
Subject: [PATCH 2/2] powerpc: Remove 8xx redundant dcbst workaround.
On 8xx dcbst fault as write operation if there is an unpopulated TLB entry
for the address in question. There is as of commit
0a2ab51ffb8dfdf51402dcfb446629648c96bc78,
powerpc/8xx: Fixup DAR from buggy dcbX instructions
a better workaround in the TLB error handler so this bad
one can be removed.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/powerpc/mm/pgtable.c | 11 -----------
1 files changed, 0 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index ebc2f38..d3f47a6 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -185,17 +185,6 @@ static pte_t set_pte_filter(pte_t pte, unsigned long addr)
if (!pg)
return pte;
if (!test_bit(PG_arch_1, &pg->flags)) {
-#ifdef CONFIG_8xx
- /* On 8xx, cache control instructions (particularly
- * "dcbst" from flush_dcache_icache) fault as write
- * operation if there is an unpopulated TLB entry
- * for the address in question. To workaround that,
- * we invalidate the TLB here, thus avoiding dcbst
- * misbehaviour.
- */
- /* 8xx doesn't care about PID, size or ind args */
- _tlbil_va(addr, 0, 0, 0);
-#endif /* CONFIG_8xx */
flush_dcache_icache_page(pg);
set_bit(PG_arch_1, &pg->flags);
}
--
1.7.3.4
^ permalink raw reply related
* Re: [PATCH] USB: Fix USB Kconfig dependency problem on 85xx/QoirQ platforms
From: xulei @ 2011-01-11 11:51 UTC (permalink / raw)
To: Kumar Gala; +Cc: Greg KH, linux-usb, linuxppc-dev
In-Reply-To: <F4B27091-DAAF-4E0C-A726-C7111161210C@freescale.com>
Thanks very much.
I'm sorry for that and will get it later.
On =E4=B8=80, 2011-01-10 at 10:22 -0600, Kumar Gala wrote:
> On Jan 10, 2011, at 4:06 AM, Xulei wrote:
>=20
> > For FSL PPC SoCs USB_ARCH_HAS_EHCI currently on depends on PPC_83xx.
> > However that excludes support for USB on 85xx & QorIQ devices. Use
> > FSL_SOC insted which will get us 83xx, 85xx, QorIQ, and 5xxx which al=
l
> > have the same USB IP on them.
> >=20
> > Signed-off-by: Xulei <B33228@freescale.com>
> > Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
> > ---
> > drivers/usb/Kconfig | 2 +-
> > 1 files changed, 1 insertions(+), 1 deletions(-)
> >=20
> > diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
> > index 6a58cb1..d513d3a 100644
> > --- a/drivers/usb/Kconfig
> > +++ b/drivers/usb/Kconfig
> > @@ -57,7 +57,7 @@ config USB_ARCH_HAS_OHCI
> > # some non-PCI hcds implement EHCI
> > config USB_ARCH_HAS_EHCI
> > boolean
> > - default y if PPC_83xx
> > + default y if FSL_SOC
> > default y if SOC_AU1200
> > default y if ARCH_IXP4XX
> > default y if ARCH_W90X900
> > --=20
> > 1.7.0.4
>=20
> This really should have been CC'd to the USB list & maintainer.
>=20
> - k
^ permalink raw reply
* Re: [PATCH 00/13] powerpc: Backport 8xx TLB to 2.4
From: Joakim Tjernlund @ 2011-01-11 10:56 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev, Willy Tarreau
In-Reply-To: <OFEC114402.5A694921-ONC1257815.002CC8F2-C1257815.002D1C7D@LocalDomain>
Joakim Tjernlund/Transmode wrote on 2011/01/11 09:12:44:
>
> Willy Tarreau <w@1wt.eu> wrote on 2011/01/11 07:09:26:
> >
> > Hi Joakim,
> >
> > On Mon, Jan 10, 2011 at 10:37:46PM +0100, Joakim Tjernlund wrote:
> > > This is a backport from 2.6 which I did to overcome 8xx CPU
> > > bugs. 8xx does not update the DAR register when taking a TLB
> > > error caused by dcbX and icbi insns which makes it very
> > > tricky to use these insns. Also the dcbst wrongly sets the
> > > the store bit when faulting into DTLB error.
> > > A few more bugs very found during development.
> > >
> > > I know 2.4 is in strict maintenance mode and 8xx is obsolete
> > > but as it is still in use I wanted 8xx to age with grace.
> >
> > Thank you very much for taking care of this, that's very much appreciated.
> > I'll look at this ASAP. Just a quick question in order to be certain, did
> > you have the opportunity to test all of these changes on real hardware ?
> I tested these on real 8xx HW but I used an older 2.4 linux as we haven't
> moved forward on 2.4 for quite some time.
> The affected files were almost identical though. Would be great if
> Scott could give them a spin on 8xx with current 2.4.
BTW, it occurred to me that the following 8xx quirk is best
done in 8xx code:
>From c1985a3b8b16d96ddce5ef90d5a15e70fb8a2aec Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Tue, 11 Jan 2011 11:24:22 +0100
Subject: [PATCH] 8xx: Move invalidation of non present TLBs
8xx does not invalidate ~PRESENT TLBs, move the workaround
in mm/fault.c here to keep 8xx quirks localized.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 12 ++++++++++--
arch/ppc/mm/fault.c | 7 -------
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 75acaa0..24b206c 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -221,7 +221,11 @@ DataAccess:
mr r5,r20
mfspr r4,DAR
stw r4,_DAR(r21)
- li r20,0x00f0
+ /* invalidate ~PRESENT TLBs, 8xx MMU don't do this */
+ andis. r20,r5,0x4000
+ beq+ 1f
+ tlbie r4
+1: li r20,0x00f0
mtspr DAR,r20 /* Tag DAR */
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
@@ -238,7 +242,11 @@ InstructionAccess:
addi r3,r1,STACK_FRAME_OVERHEAD
mr r4,r22
mr r5,r23
- li r20,MSR_KERNEL
+ /* invalidate ~PRESENT TLBs, 8xx MMU don't do this */
+ andis. r20,r5,0x4000
+ beq+ 1f
+ tlbie r4
+1: li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
FINISH_EXCEPTION(do_page_fault)
diff --git a/arch/ppc/mm/fault.c b/arch/ppc/mm/fault.c
index 874005a..8819fb1 100644
--- a/arch/ppc/mm/fault.c
+++ b/arch/ppc/mm/fault.c
@@ -116,13 +116,6 @@ void do_page_fault(struct pt_regs *regs, unsigned long address,
else
is_write = error_code & 0x02000000;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
-#if defined(CONFIG_8xx)
- /* 8xx does no invalidate TLBs that are ~PRESENT,
- * do it here.
- */
- if (error_code & 0x40000000)
- _tlbie(address);
-#endif
#if defined(CONFIG_XMON) || defined(CONFIG_KGDB)
if (debugger_fault_handler && regs->trap == 0x300) {
debugger_fault_handler(regs);
--
1.7.3.4
Scott, what do you think of this? Is it safe to call tlbie in this context?
Jocke
^ permalink raw reply related
* Re: [PATCH 00/13] powerpc: Backport 8xx TLB to 2.4
From: Joakim Tjernlund @ 2011-01-11 8:12 UTC (permalink / raw)
To: Willy Tarreau; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <20110111060926.GE16301@1wt.eu>
Willy Tarreau <w@1wt.eu> wrote on 2011/01/11 07:09:26:
>
> Hi Joakim,
>
> On Mon, Jan 10, 2011 at 10:37:46PM +0100, Joakim Tjernlund wrote:
> > This is a backport from 2.6 which I did to overcome 8xx CPU
> > bugs. 8xx does not update the DAR register when taking a TLB
> > error caused by dcbX and icbi insns which makes it very
> > tricky to use these insns. Also the dcbst wrongly sets the
> > the store bit when faulting into DTLB error.
> > A few more bugs very found during development.
> >
> > I know 2.4 is in strict maintenance mode and 8xx is obsolete
> > but as it is still in use I wanted 8xx to age with grace.
>
> Thank you very much for taking care of this, that's very much appreciated.
> I'll look at this ASAP. Just a quick question in order to be certain, did
> you have the opportunity to test all of these changes on real hardware ?
I tested these on real 8xx HW but I used an older 2.4 linux as we haven't
moved forward on 2.4 for quite some time.
The affected files were almost identical though. Would be great if
Scott could give them a spin on 8xx with current 2.4.
Jocke
^ permalink raw reply
* Re: [PATCH 00/13] powerpc: Backport 8xx TLB to 2.4
From: Willy Tarreau @ 2011-01-11 6:09 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
Hi Joakim,
On Mon, Jan 10, 2011 at 10:37:46PM +0100, Joakim Tjernlund wrote:
> This is a backport from 2.6 which I did to overcome 8xx CPU
> bugs. 8xx does not update the DAR register when taking a TLB
> error caused by dcbX and icbi insns which makes it very
> tricky to use these insns. Also the dcbst wrongly sets the
> the store bit when faulting into DTLB error.
> A few more bugs very found during development.
>
> I know 2.4 is in strict maintenance mode and 8xx is obsolete
> but as it is still in use I wanted 8xx to age with grace.
Thank you very much for taking care of this, that's very much appreciated.
I'll look at this ASAP. Just a quick question in order to be certain, did
you have the opportunity to test all of these changes on real hardware ?
Thanks,
Willy
^ permalink raw reply
* Re: PCI woes with 2.6.37
From: Benjamin Herrenschmidt @ 2011-01-11 0:53 UTC (permalink / raw)
To: Gary Thomas; +Cc: Linux PPC Development
In-Reply-To: <4D2B1151.9040109@mlbassoc.com>
> I found the problem - a change I had in <2.6.32 that I hadn't
> pushed forward. It seems to be related to how I have the PCI
> controller setup (in RedBoot). Because of this, using these
> settings in my DTS make things work properly:
> ranges = <0x02000000 0x0 0x00000000 0xC0000000 0x0 0x20000000
> 0x01000000 0x0 0x00000000 0xB8000000 0x0 0x00100000>;
> Instead of
> ranges = <0x02000000 0x0 0xC0000000 0xC0000000 0x0 0x20000000
> 0x01000000 0x0 0x00000000 0xB8000000 0x0 0x00100000>;
Right so instead of a 1:1 mapping you have a N:1 mapping. We support
both forms, tho it would have been nice if the fsl PCI code had properly
reconfigured the controller based on the DT.
> Sorry for the noise (wild goose chase), but discussing it did help
> me to work out some PCI issues in general.
>
> Now that this is working, I'm trying to move to the next problem.
> The system works fine, but only to a point. In this [embedded]
> system, I have an SIL SATA controller on the PCI bus.
Ok, those are pretty common and generally work fine.
> On 2.6.28,
> this device is rock solid. On 2.6.32 and now 2.6.37, I have issues.
> Operations work on the device (connected to a SSD), but after some
> arbitrary time, an operation will fail, causing the PCI bus (and
> indeed the whole system) to hang. I've tried to peek in using a
> BDI and once it hangs, even the BDI can't access the CPU any more.
Ugh. Never hit a problem like this I'm afraid.
> I'm pretty lost on this one - it will execute hundreds of SATA operations
> properly and then die. Turning on SATA/SCSI traces, I can see the
> final operation be issued and there seems to be no substantive difference
> between this operation and the previous ones that all worked. In fact
> if I reset and rerun the same program, it _will_ fail but never on
> the same operation :-(
>
> Any ideas what could cause this failure? I have a similar system
> that uses a different SATA controller that I'm going to try. Maybe
> it's something peculiar to the SIL device as opposed to generic PCI
> operations.
Yes, definitely try different controllers. Also check your voltages just
in case....
Other things you can do is double check the settings of things like max
read request size, max payload size etc... in the PCIe config space of
the device and the bridge.
Cheers,
Ben.
^ permalink raw reply
* [PATCH] ehci-fsl: Fix 'have_sysif_regs' detection
From: Peter Tyser @ 2011-01-10 23:34 UTC (permalink / raw)
To: linux-usb; +Cc: Peter Tyser, Anatolij Gustschin, linuxppc-dev, David Brownell
Previously a check was done on an ID register at the base of a CPU's
internal USB registers to determine if system interface regsiters were
present. The check looked for an ID register that had the format
ID[0:5] == ~ID[8:13] as described in the MPC5121 User's Manual to
determine if a MPC5121 or MPC83xx/85xx was being used.
There are two issues with this method:
- The ID register is not defined on the MPC83xx/85xx CPUs, so its
unclear what is being checked on them.
- Newer CPUs such as the P4080 also don't document the ID register, but
do share the same format as the MPC5121. Thus the previous code did
not set 'have_sysif_regs' properly which results in the P4080 not
properly initializing its USB ports.
Using the device tree 'compatible' node is a cleaner way to determine if
'have_sysif_regs' should be set and resolves the USB initialization issue
seen on the P4080.
Tested on a P4080-based system and compile tested on mpc512x_defconfig
with Freescale EHCI driver enabled.
Cc: Anatolij Gustschin <agust@denx.de>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
drivers/usb/host/ehci-fsl.c | 13 -------------
drivers/usb/host/ehci-fsl.h | 3 ---
drivers/usb/host/fsl-mph-dr-of.c | 11 ++++++++---
3 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 86e4289..5c761df 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -52,7 +52,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
struct resource *res;
int irq;
int retval;
- unsigned int temp;
pr_debug("initializing FSL-SOC USB Controller\n");
@@ -126,18 +125,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
goto err3;
}
- /*
- * Check if it is MPC5121 SoC, otherwise set pdata->have_sysif_regs
- * flag for 83xx or 8536 system interface registers.
- */
- if (pdata->big_endian_mmio)
- temp = in_be32(hcd->regs + FSL_SOC_USB_ID);
- else
- temp = in_le32(hcd->regs + FSL_SOC_USB_ID);
-
- if ((temp & ID_MSK) != (~((temp & NID_MSK) >> 8) & ID_MSK))
- pdata->have_sysif_regs = 1;
-
/* Enable USB controller, 83xx or 8536 */
if (pdata->have_sysif_regs)
setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 2c83537..3fabed3 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -19,9 +19,6 @@
#define _EHCI_FSL_H
/* offsets for the non-ehci registers in the FSL SOC USB controller */
-#define FSL_SOC_USB_ID 0x0
-#define ID_MSK 0x3f
-#define NID_MSK 0x3f00
#define FSL_SOC_USB_ULPIVP 0x170
#define FSL_SOC_USB_PORTSC1 0x184
#define PORT_PTS_MSK (3<<30)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 574b99e..341fa81 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -262,19 +262,24 @@ static void fsl_usb2_mpc5121_exit(struct platform_device *pdev)
}
}
-struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
+static struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
.big_endian_desc = 1,
.big_endian_mmio = 1,
.es = 1,
+ .have_sysif_regs = 0,
.le_setup_buf = 1,
.init = fsl_usb2_mpc5121_init,
.exit = fsl_usb2_mpc5121_exit,
};
#endif /* CONFIG_PPC_MPC512x */
+static struct fsl_usb2_platform_data fsl_usb2_mpc8xxx_pd = {
+ .have_sysif_regs = 1,
+};
+
static const struct of_device_id fsl_usb2_mph_dr_of_match[] = {
- { .compatible = "fsl-usb2-mph", },
- { .compatible = "fsl-usb2-dr", },
+ { .compatible = "fsl-usb2-mph", .data = &fsl_usb2_mpc8xxx_pd, },
+ { .compatible = "fsl-usb2-dr", .data = &fsl_usb2_mpc8xxx_pd, },
#ifdef CONFIG_PPC_MPC512x
{ .compatible = "fsl,mpc5121-usb2-dr", .data = &fsl_usb2_mpc5121_pd, },
#endif
--
1.7.0.4
^ permalink raw reply related
* [PATCH 13/13] 8xx: Optimize TLB Miss handlers
From: Joakim Tjernlund @ 2011-01-10 21:37 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
Only update pte w.r.t ACCESSED if it isn't already set
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 5dbbdb4..75acaa0 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -376,8 +376,12 @@ InstructionTLBMiss:
#if 1
/* if !swap, you can delete this */
+ andi. r21, r20, _PAGE_ACCESSED /* test ACCESSED bit */
+ bne+ 4f /* Branch if set */
+ mfspr r21, MD_TWC /* get the pte address */
rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */
stw r20, 0(r21) /* Update pte */
+4:
#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 21 and 28 must be clear.
@@ -449,9 +453,12 @@ DataStoreTLBMiss:
#if 1
/* if !swap, you can delete this */
+ andi. r21, r20, _PAGE_ACCESSED /* test ACCESSED bit */
+ bne+ 4f /* Branch if set */
mfspr r21, MD_TWC /* get the pte address */
rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */
stw r20, 0(r21) /* Update pte */
+4:
#endif
/* Honour kernel RO, User NA */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 12/13] 8xx: Optimize ITLBMiss handler.
From: Joakim Tjernlund @ 2011-01-10 21:37 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
Don't check for kernel space if no modules.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 43bccb1..5dbbdb4 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -347,12 +347,17 @@ InstructionTLBMiss:
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
+#ifdef CONFIG_MODULES
+ /* Since we PIN the first 8MB text, we only get ITLB misses
+ * for modules
+ */
andi. r21, r20, 0x0800 /* Address >= 0x80000000 */
beq 3f
lis r21, swapper_pg_dir@h
ori r21, r21, swapper_pg_dir@l
rlwimi r20, r21, 0, 2, 19
3:
+#endif
lwz r21, 0(r20) /* Get the level 1 entry */
rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 11/13] 8xx: start using dcbX instructions in various copy routines
From: Joakim Tjernlund @ 2011-01-10 21:37 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/misc.S | 18 ------------------
arch/ppc/lib/string.S | 17 -----------------
2 files changed, 0 insertions(+), 35 deletions(-)
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
index c1c3178..6f57957 100644
--- a/arch/ppc/kernel/misc.S
+++ b/arch/ppc/kernel/misc.S
@@ -662,15 +662,7 @@ _GLOBAL(__flush_dcache_icache)
_GLOBAL(clear_page)
li r0,4096/L1_CACHE_LINE_SIZE
mtctr r0
-#ifdef CONFIG_8xx
- li r4, 0
-1: stw r4, 0(r3)
- stw r4, 4(r3)
- stw r4, 8(r3)
- stw r4, 12(r3)
-#else
1: dcbz 0,r3
-#endif
addi r3,r3,L1_CACHE_LINE_SIZE
bdnz 1b
blr
@@ -695,15 +687,6 @@ _GLOBAL(copy_page)
addi r3,r3,-4
addi r4,r4,-4
-#ifdef CONFIG_8xx
- /* don't use prefetch on 8xx */
- li r0,4096/L1_CACHE_LINE_SIZE
- mtctr r0
-1: COPY_16_BYTES
- bdnz 1b
- blr
-
-#else /* not 8xx, we can prefetch */
li r5,4
#if MAX_COPY_PREFETCH > 1
@@ -744,7 +727,6 @@ _GLOBAL(copy_page)
li r0,MAX_COPY_PREFETCH
li r11,4
b 2b
-#endif /* CONFIG_8xx */
/*
* Atomic [test&set] exchange
diff --git a/arch/ppc/lib/string.S b/arch/ppc/lib/string.S
index 6ca54b4..b6ea44b 100644
--- a/arch/ppc/lib/string.S
+++ b/arch/ppc/lib/string.S
@@ -159,14 +159,7 @@ _GLOBAL(cacheable_memzero)
bdnz 4b
3: mtctr r9
li r7,4
-#if !defined(CONFIG_8xx)
10: dcbz r7,r6
-#else
-10: stw r4, 4(r6)
- stw r4, 8(r6)
- stw r4, 12(r6)
- stw r4, 16(r6)
-#endif
addi r6,r6,CACHELINE_BYTES
bdnz 10b
clrlwi r5,r8,32-LG_CACHELINE_BYTES
@@ -261,9 +254,7 @@ _GLOBAL(cacheable_memcpy)
mtctr r0
beq 63f
53:
-#if !defined(CONFIG_8xx)
dcbz r11,r6
-#endif
COPY_16_BYTES
#if L1_CACHE_LINE_SIZE >= 32
COPY_16_BYTES
@@ -443,13 +434,6 @@ _GLOBAL(__copy_tofrom_user)
li r11,4
beq 63f
-#ifdef CONFIG_8xx
- /* Don't use prefetch on 8xx */
- mtctr r0
-53: COPY_16_BYTES_WITHEX(0)
- bdnz 53b
-
-#else /* not CONFIG_8xx */
/* Here we decide how far ahead to prefetch the source */
li r3,4
cmpwi r0,1
@@ -502,7 +486,6 @@ _GLOBAL(__copy_tofrom_user)
li r3,4
li r7,0
bne 114b
-#endif /* CONFIG_8xx */
63: srwi. r0,r5,2
mtctr r0
--
1.7.3.4
^ permalink raw reply related
* [PATCH 10/13] 8xx: Restore _PAGE_WRITETHRU
From: Joakim Tjernlund @ 2011-01-10 21:37 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 8 ++++++++
include/asm-ppc/pgtable.h | 5 +++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 2659a1e..43bccb1 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -435,6 +435,10 @@ DataStoreTLBMiss:
* above.
*/
rlwimi r21, r20, 0, 27, 27
+ /* Insert the WriteThru flag into the TWC from the Linux PTE.
+ * It is bit 25 in the Linux PTE and bit 30 in the TWC
+ */
+ rlwimi r21, r20, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
@@ -571,6 +575,10 @@ DARFixed:
* It is bit 27 of both the Linux PTE and the TWC
*/
rlwimi r21, r20, 0, 27, 27
+ /* Insert the WriteThru flag into the TWC from the Linux PTE.
+ * It is bit 25 in the Linux PTE and bit 30 in the TWC
+ */
+ rlwimi r21, r20, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
mfspr r21, MD_TWC /* get the pte address again */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 2ba37d3..6cfc5fc 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -298,12 +298,13 @@ extern unsigned long vmalloc_start;
#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
-/* These three software bits must be masked out when the entry is loaded
- * into the TLB, 2 SW bits free.
+/* These four software bits must be masked out when the entry is loaded
+ * into the TLB, 1 SW bits left(0x0080).
*/
#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
#define _PAGE_GUARDED 0x0010 /* software: guarded access */
#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
+#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */
/* Setting any bits in the nibble with the follow two controls will
* require a TLB exception handler change. It is assumed unused bits
--
1.7.3.4
^ permalink raw reply related
* [PATCH 09/13] 8xx: Add missing Guarded setting in DTLB Error.
From: Joakim Tjernlund @ 2011-01-10 21:37 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 12 +++++++++---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 0aab8ca..2659a1e 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -565,9 +565,15 @@ DARFixed:
ori r21, r21, 1 /* Set valid bit in physical L2 page */
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21 /* Load pte table base address */
- mfspr r21, MD_TWC /* ....and get the pte address */
- lwz r20, 0(r21) /* Get the pte */
-
+ mfspr r20, MD_TWC /* ....and get the pte address */
+ lwz r20, 0(r20) /* Get the pte */
+ /* Insert the Guarded flag into the TWC from the Linux PTE.
+ * It is bit 27 of both the Linux PTE and the TWC
+ */
+ rlwimi r21, r20, 0, 27, 27
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr MD_TWC, r21
+ mfspr r21, MD_TWC /* get the pte address again */
ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
stw r20, 0(r21) /* and update pte in table */
xori r20, r20, _PAGE_RW /* RW bit is inverted */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 08/13] 8xx: CPU6 errata make DTLB error too big to fit.
From: Joakim Tjernlund @ 2011-01-10 21:37 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
branch to common code in DTLB Miss instead.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 23 ++---------------------
1 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 52ff914..0aab8ca 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -461,6 +461,7 @@ DataStoreTLBMiss:
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
+finish_DTLB:
2: li r21, 0x00f0
mtspr DAR, r21 /* Tag DAR */
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
@@ -570,27 +571,7 @@ DARFixed:
ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
stw r20, 0(r21) /* and update pte in table */
xori r20, r20, _PAGE_RW /* RW bit is inverted */
-
- /* The Linux PTE won't go exactly into the MMU TLB.
- * Software indicator bits 22 and 28 must be clear.
- * Software indicator bits 24, 25, 26, and 27 must be
- * set. All other Linux PTE bits control the behavior
- * of the MMU.
- */
- li r21, 0x00f0
- mtspr DAR, r21 /* Tag DAR */
- rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
- DO_8xx_CPU6(0x3d80, r3)
- mtspr MD_RPN, r20 /* Update TLB entry */
-
- mfspr r20, M_TW /* Restore registers */
- lwz r21, 0(r0)
- mtcr r21
- lwz r21, 4(r0)
-#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0)
-#endif
- rfi
+ b finish_DTLB
2:
mfspr r20, M_TW /* Restore registers */
lwz r21, 0(r0)
--
1.7.3.4
^ permalink raw reply related
* [PATCH 07/13] 8xx: Fixup DAR from buggy dcbX instructions.
From: Joakim Tjernlund @ 2011-01-10 21:37 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 149 +++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 146 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index d992c24..52ff914 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -503,8 +503,17 @@ DataTLBError:
stw r20, 0(r0)
stw r21, 4(r0)
- mfspr r20, DSISR
- andis. r21, r20, 0x4800 /* !translation or protection */
+ mfspr r20, DAR
+ cmpwi cr0, r20, 0x00f0
+ beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
+DARFixed:
+ /* As the DAR fixup may clear store we may have all 3 states zero.
+ * Make sure only 0x0200(store) falls down into DIRTY handling
+ */
+ mfspr r21, DSISR
+ andis. r21, r21, 0x4a00 /* !translation, protection or store */
+ srwi r21, r21, 16
+ cmpwi cr0, r21, 0x0200 /* just store ? */
bne- 2f
/* Only Change bit left now, do it here as it is faster
* than trapping to the C fault handler.
@@ -526,7 +535,7 @@ DataTLBError:
* are initialized in mapin_ram(). This will avoid the problem,
* assuming we only use the dcbi instruction on kernel addresses.
*/
- mfspr r20, DAR
+ /* DAR is in r20 already */
rlwinm r21, r20, 0, 0, 19
ori r21, r21, MD_EVALID
mfspr r20, M_CASID
@@ -610,6 +619,140 @@ DataTLBError:
STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
. = 0x2000
+/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
+ * by decoding the registers used by the dcbx instruction and adding them.
+ * DAR is set to the calculated address and r10 also holds the EA on exit.
+ */
+ /* define if you don't want to use self modifying code */
+#define NO_SELF_MODIFYING_CODE
+FixupDAR:/* Entry point for dcbx workaround. */
+ /* fetch instruction from memory. */
+ mfspr r20, SRR0
+ andis. r21, r20, 0x8000 /* Address >= 0x80000000 */
+ DO_8xx_CPU6(0x3780, r3)
+ mtspr MD_EPN, r20
+ mfspr r21, M_TWB /* Get level 1 table entry address */
+ beq- 3f /* Branch if user space */
+ lis r21, (swapper_pg_dir-PAGE_OFFSET)@h
+ ori r21, r21, (swapper_pg_dir-PAGE_OFFSET)@l
+ rlwimi r21, r20, 32-20, 0xffc /* r21 = r21&~0xffc|(r20>>20)&0xffc */
+3: lwz r21, 0(r21) /* Get the level 1 entry */
+ tophys (r21, r21)
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr MD_TWC, r21 /* Load pte table base address */
+ mfspr r21, MD_TWC /* ....and get the pte address */
+ lwz r21, 0(r21) /* Get the pte */
+ /* concat physical page address(r21) and page offset(r20) */
+ rlwimi r21, r20, 0, 20, 31
+ lwz r21,0(r21)
+/* Check if it really is a dcbx instruction. */
+/* dcbt and dcbtst does not generate DTLB Misses/Errors,
+ * no need to include them here */
+ srwi r20, r21, 26 /* check if major OP code is 31 */
+ cmpwi cr0, r20, 31
+ bne- 141f
+ rlwinm r20, r21, 0, 21, 30
+ cmpwi cr0, r20, 2028 /* Is dcbz? */
+ beq+ 142f
+ cmpwi cr0, r20, 940 /* Is dcbi? */
+ beq+ 142f
+ cmpwi cr0, r20, 108 /* Is dcbst? */
+ beq+ 144f /* Fix up store bit! */
+ cmpwi cr0, r20, 172 /* Is dcbf? */
+ beq+ 142f
+ cmpwi cr0, r20, 1964 /* Is icbi? */
+ beq+ 142f
+141: mfspr r20, DAR /* r20 must hold DAR at exit */
+ b DARFixed /* Nope, go back to normal TLB processing */
+
+144: mfspr r20, DSISR
+ rlwinm r20, r20,0,7,5 /* Clear store bit for buggy dcbst insn */
+ mtspr DSISR, r20
+142: /* continue, it was a dcbx, dcbi instruction. */
+#ifdef CONFIG_8xx_CPU6
+ lwz r3, 8(r0) /* restore r3 from memory */
+#endif
+#ifndef NO_SELF_MODIFYING_CODE
+ andis. r20,r21,0x1f /* test if reg RA is r0 */
+ li r20,modified_instr@l
+ dcbtst r0,r20 /* touch for store */
+ rlwinm r21,r21,0,0,20 /* Zero lower 10 bits */
+ oris r21,r21,640 /* Transform instr. to a "add r20,RA,RB" */
+ ori r21,r21,532
+ stw r21,0(r20) /* store add/and instruction */
+ dcbf 0,r20 /* flush new instr. to memory. */
+ icbi 0,r20 /* invalidate instr. cache line */
+ lwz r21, 4(r0) /* restore r21 from memory */
+ mfspr r20, M_TW /* restore r20 from M_TW */
+ isync /* Wait until new instr is loaded from memory */
+modified_instr:
+ .space 4 /* this is where the add instr. is stored */
+ bne+ 143f
+ subf r20,r0,r20 /* r20=r20-r0, only if reg RA is r0 */
+143: mtdar r20 /* store faulting EA in DAR */
+ b DARFixed /* Go back to normal TLB handling */
+#else
+ mfctr r20
+ mtdar r20 /* save ctr reg in DAR */
+ rlwinm r20, r21, 24, 24, 28 /* offset into jump table for reg RB */
+ addi r20, r20, 150f@l /* add start of table */
+ mtctr r20 /* load ctr with jump address */
+ xor r20, r20, r20 /* sum starts at zero */
+ bctr /* jump into table */
+150:
+ add r20, r20, r0 ;b 151f
+ add r20, r20, r1 ;b 151f
+ add r20, r20, r2 ;b 151f
+ add r20, r20, r3 ;b 151f
+ add r20, r20, r4 ;b 151f
+ add r20, r20, r5 ;b 151f
+ add r20, r20, r6 ;b 151f
+ add r20, r20, r7 ;b 151f
+ add r20, r20, r8 ;b 151f
+ add r20, r20, r9 ;b 151f
+ add r20, r20, r10 ;b 151f
+ add r20, r20, r11 ;b 151f
+ add r20, r20, r12 ;b 151f
+ add r20, r20, r13 ;b 151f
+ add r20, r20, r14 ;b 151f
+ add r20, r20, r15 ;b 151f
+ add r20, r20, r16 ;b 151f
+ add r20, r20, r17 ;b 151f
+ add r20, r20, r18 ;b 151f
+ add r20, r20, r19 ;b 151f
+ mtctr r21 ;b 154f /* r20 needs special handling */
+ mtctr r21 ;b 153f /* r21 needs special handling */
+ add r20, r20, r22 ;b 151f
+ add r20, r20, r23 ;b 151f
+ add r20, r20, r24 ;b 151f
+ add r20, r20, r25 ;b 151f
+ add r20, r20, r26 ;b 151f
+ add r20, r20, r27 ;b 151f
+ add r20, r20, r28 ;b 151f
+ add r20, r20, r29 ;b 151f
+ add r20, r20, r30 ;b 151f
+ add r20, r20, r31
+151:
+ rlwinm. r21,r21,19,24,28 /* offset into jump table for reg RA */
+ beq 152f /* if reg RA is zero, don't add it */
+ addi r21, r21, 150b@l /* add start of table */
+ mtctr r21 /* load ctr with jump address */
+ rlwinm r21,r21,0,16,10 /* make sure we don't execute this more than once */
+ bctr /* jump into table */
+152:
+ mfdar r21
+ mtctr r21 /* restore ctr reg from DAR */
+ mtdar r20 /* save fault EA to DAR */
+ b DARFixed /* Go back to normal TLB handling */
+
+ /* special handling for r20,r21 since these are modified already */
+153: lwz r21, 4(r0) /* load r21 from memory */
+ b 155f
+154: mfspr r21, M_TW /* load r20 from M_TW */
+155: add r20, r20, r21 /* add it */
+ mfctr r21 /* restore r21 */
+ b 151b
+#endif
/*
* This code finishes saving the registers to the exception frame
--
1.7.3.4
^ permalink raw reply related
* [PATCH 06/13] 8xx: Always pin kernel instruction TLB
From: Joakim Tjernlund @ 2011-01-10 21:37 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1294695479-344-1-git-send-email-Joakim.Tjernlund@transmode.se>
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 9 +++++----
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 9eb383b..d992c24 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -777,12 +777,13 @@ start_here:
*/
initial_mmu:
tlbia /* Invalidate all TLB entries */
-#ifdef CONFIG_PIN_TLB
+
+/* Always pin the first 8 MB ITLB to prevent ITLB
+ misses while mucking around with SRR0/SRR1 in asm
+*/
lis r8, MI_RSV4I@h
ori r8, r8, 0x1c00
-#else
- li r8, 0
-#endif
+
mtspr MI_CTR, r8 /* Set instruction MMU control */
#ifdef CONFIG_PIN_TLB
--
1.7.3.4
^ permalink raw reply related
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