* Re: [uclinux-dist-devel] [PATCH] sched: provide scheduler_ipi() callback in response to smp_send_reschedule()
From: Peter Zijlstra @ 2011-01-17 20:16 UTC (permalink / raw)
To: Mike Frysinger
Cc: linux-m32r-ja, linux-mips, linux-ia64, linux-sh, H. Peter Anvin,
Heiko Carstens, Paul Mackerras, Helge Deller, sparclinux,
Linux-Arch, linux-s390, Jesper Nilsson, Jeremy Fitzhardinge,
Russell King, Hirokazu Takata, x86, James E.J. Bottomley,
virtualization, Ingo Molnar, Matt Turner, Fenghua Yu,
user-mode-linux-devel, Konrad Rzeszutek Wilk, Jeff Dike,
Chris Metcalf, xen-devel, Mikael Starvik, linux-m32r,
Ivan Kokshaysky, user-mode-linux-user, uclinux-dist-devel,
Thomas Gleixner, linux-arm-kernel, Richard Henderson, Tony Luck,
linux-parisc, linux-cris-kernel, linux-am33-list, linux-kernel,
Ralf Baechle, Kyle McMartin, Paul Mundt, linux-alpha,
Martin Schwidefsky, linux390, Koichi Yasutake, linuxppc-dev,
David S. Miller
In-Reply-To: <AANLkTik3hE=_34Lbs944MzKpkNzqY+kCxpxmncUM2HB7@mail.gmail.com>
On Mon, 2011-01-17 at 14:49 -0500, Mike Frysinger wrote:
> On Mon, Jan 17, 2011 at 06:07, Peter Zijlstra wrote:
> > Also, while reading through all this, I noticed the blackfin SMP code
> > looks to be broken, it simply discards any IPI when low on memory.
>=20
> not really. see changelog of commit 73a400646b8e26615f3ef1a0a4bc0cd0d5bd=
284c.
Ah, indeed, it appears my tree was simply out of date, very good!
^ permalink raw reply
* [PATCH] powerpc/fsl_msi: Handle msi-available-ranges better
From: Scott Wood @ 2011-01-17 20:25 UTC (permalink / raw)
To: galak; +Cc: devicetree-discuss, linuxppc-dev
Now handles multiple ranges, doesn't make assumptions about interrupt
specifier format, and doesn't claim interrupts that don't correspond to an
available range.
Also has some better error checking.
The device tree binding is updated to clarify some existing assumptions.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
Documentation/powerpc/dts-bindings/fsl/msi-pic.txt | 9 ++-
arch/powerpc/sysdev/fsl_msi.c | 92 ++++++++++++--------
2 files changed, 64 insertions(+), 37 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt b/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
index bcc30ba..c0d80fb 100644
--- a/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
@@ -5,14 +5,21 @@ Required properties:
first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
the parent type.
+
- reg : should contain the address and the length of the shared message
interrupt register set.
+
- msi-available-ranges: use <start count> style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
optional, without this, all the 256 MSI interrupts can be used.
+ Each available range must begin and end on a multiple of 32 (i.e.
+ no splitting an individual MSI register or the associated PIC interrupt).
+
- interrupts : each one of the interrupts here is one entry per 32 MSIs,
and routed to the host interrupt controller. the interrupts should
- be set as edge sensitive.
+ be set as edge sensitive. If msi-available-ranges is present, only
+ the interrupts that correspond to available ranges shall be present.
+
- interrupt-parent: the phandle for the interrupt controller
that services interrupts for this device. for 83xx cpu, the interrupts
are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 108d76f..46e27ac 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
*
* Author: Tony Li <tony.li@freescale.com>
* Jason Jin <Jason.jin@freescale.com>
@@ -273,19 +273,47 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
return 0;
}
+static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
+ struct platform_device *dev,
+ int offset, int irq_index)
+{
+ struct fsl_msi_cascade_data *cascade_data = NULL;
+ int virt_msir;
+
+ virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
+ if (virt_msir == NO_IRQ) {
+ dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
+ __func__, irq_index);
+ return 0;
+ }
+
+ cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
+ if (!cascade_data) {
+ dev_err(&dev->dev, "No memory for MSI cascade data\n");
+ return -ENOMEM;
+ }
+
+ msi->msi_virqs[irq_index] = virt_msir;
+ cascade_data->index = offset + irq_index;
+ cascade_data->msi_data = msi;
+ set_irq_data(virt_msir, cascade_data);
+ set_irq_chained_handler(virt_msir, fsl_msi_cascade);
+
+ return 0;
+}
+
static int __devinit fsl_of_msi_probe(struct platform_device *dev,
const struct of_device_id *match)
{
struct fsl_msi *msi;
struct resource res;
- int err, i, count;
+ int err, i, j, irq_index, count;
int rc;
- int virt_msir;
const u32 *p;
struct fsl_msi_feature *features = match->data;
- struct fsl_msi_cascade_data *cascade_data = NULL;
int len;
u32 offset;
+ static const u32 all_avail[] = { 0, NR_MSI_IRQS };
printk(KERN_DEBUG "Setting up Freescale MSI support\n");
@@ -332,42 +360,34 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev,
goto error_out;
}
- p = of_get_property(dev->dev.of_node, "interrupts", &count);
- if (!p) {
- dev_err(&dev->dev, "no interrupts property found on %s\n",
- dev->dev.of_node->full_name);
- err = -ENODEV;
- goto error_out;
- }
- if (count % 8 != 0) {
- dev_err(&dev->dev, "Malformed interrupts property on %s\n",
- dev->dev.of_node->full_name);
+ p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
+ if (p && len % (2 * sizeof(u32)) != 0) {
+ dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
+ __func__);
err = -EINVAL;
goto error_out;
}
- offset = 0;
- p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
- if (p)
- offset = *p / IRQS_PER_MSI_REG;
-
- count /= sizeof(u32);
- for (i = 0; i < min(count / 2, NR_MSI_REG); i++) {
- virt_msir = irq_of_parse_and_map(dev->dev.of_node, i);
- if (virt_msir != NO_IRQ) {
- cascade_data = kzalloc(
- sizeof(struct fsl_msi_cascade_data),
- GFP_KERNEL);
- if (!cascade_data) {
- dev_err(&dev->dev,
- "No memory for MSI cascade data\n");
- err = -ENOMEM;
+
+ if (!p)
+ p = all_avail;
+
+ for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
+ if (p[i * 2] % IRQS_PER_MSI_REG ||
+ p[i * 2 + 1] % IRQS_PER_MSI_REG) {
+ printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
+ __func__, dev->dev.of_node->full_name,
+ p[i * 2 + 1], p[i * 2]);
+ err = -EINVAL;
+ goto error_out;
+ }
+
+ offset = p[i * 2] / IRQS_PER_MSI_REG;
+ count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
+
+ for (j = 0; j < count; j++, irq_index++) {
+ err = fsl_msi_setup_hwirq(msi, dev, offset, irq_index);
+ if (err)
goto error_out;
- }
- msi->msi_virqs[i] = virt_msir;
- cascade_data->index = i + offset;
- cascade_data->msi_data = msi;
- set_irq_data(virt_msir, (void *)cascade_data);
- set_irq_chained_handler(virt_msir, fsl_msi_cascade);
}
}
--
1.7.0.4
^ permalink raw reply related
* Re: [PATCH] sched: provide scheduler_ipi() callback in response to smp_send_reschedule()
From: Benjamin Herrenschmidt @ 2011-01-17 20:31 UTC (permalink / raw)
To: Peter Zijlstra
Cc: linux-m32r-ja, linux-mips, linux-ia64, linux-sh, H. Peter Anvin,
Heiko Carstens, Paul Mackerras, Helge Deller, sparclinux,
Linux-Arch, linux-s390, Jesper Nilsson, Jeremy Fitzhardinge,
Russell King, Hirokazu Takata, x86, James E.J. Bottomley,
virtualization, Ingo Molnar, Matt Turner, Fenghua Yu,
Mike Frysinger, user-mode-linux-devel, Konrad Rzeszutek Wilk,
Jeff Dike, Chris Metcalf, xen-devel, Mikael Starvik, linux-m32r,
Ivan Kokshaysky, user-mode-linux-user, uclinux-dist-devel,
Thomas Gleixner, linux-arm-kernel, Richard Henderson, Tony Luck,
linux-parisc, linux-cris-kernel, linux-am33-list, linux-kernel,
Ralf Baechle, Kyle McMartin, Paul Mundt, linux-alpha,
Martin Schwidefsky, linux390, Koichi Yasutake, linuxppc-dev,
David S. Miller
In-Reply-To: <1295262433.30950.53.camel@laptop>
On Mon, 2011-01-17 at 12:07 +0100, Peter Zijlstra wrote:
> For future rework of try_to_wake_up() we'd like to push part of that
> onto the CPU the task is actually going to run on, in order to do so we
> need a generic callback from the existing scheduler IPI.
>
> This patch introduces such a generic callback: scheduler_ipi() and
> implements it as a NOP.
>
> I visited existing smp_send_reschedule() implementations and tried to
> add a call to scheduler_ipi() in their handler part, but esp. for MIPS
> I'm not quite sure I actually got all of them.
>
> Also, while reading through all this, I noticed the blackfin SMP code
> looks to be broken, it simply discards any IPI when low on memory.
Beware of false positive, I've used "fake" reschedule IPIs in the past
for other things (like kicking a CPU out of sleep state for unrelated
reasons). Nothing that I know that is upstream today but some of that
might come back. I'd like to avoid having to add an atomic to know if
it's a real reschedule, will the scheduler be smart enough to not bother
with false positives ?
Cheers,
Ben.
> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
> ---
> arch/alpha/kernel/smp.c | 1 +
> arch/arm/kernel/smp.c | 1 +
> arch/blackfin/mach-common/smp.c | 3 ++-
> arch/cris/arch-v32/kernel/smp.c | 13 ++++++++-----
> arch/ia64/kernel/irq_ia64.c | 2 ++
> arch/ia64/xen/irq_xen.c | 10 +++++++++-
> arch/m32r/kernel/smp.c | 2 +-
> arch/mips/kernel/smtc.c | 1 +
> arch/mips/sibyte/bcm1480/smp.c | 7 +++----
> arch/mips/sibyte/sb1250/smp.c | 7 +++----
> arch/mn10300/kernel/smp.c | 2 +-
> arch/parisc/kernel/smp.c | 1 +
> arch/powerpc/kernel/smp.c | 1 +
> arch/s390/kernel/smp.c | 6 +++---
> arch/sh/kernel/smp.c | 2 ++
> arch/sparc/kernel/smp_32.c | 2 +-
> arch/sparc/kernel/smp_64.c | 1 +
> arch/tile/kernel/smp.c | 1 +
> arch/um/kernel/smp.c | 2 +-
> arch/x86/kernel/smp.c | 1 +
> arch/x86/xen/smp.c | 1 +
> include/linux/sched.h | 1 +
> 22 files changed, 46 insertions(+), 22 deletions(-)
>
> diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
> index 42aa078..c4a570b 100644
> --- a/arch/alpha/kernel/smp.c
> +++ b/arch/alpha/kernel/smp.c
> @@ -587,6 +587,7 @@ handle_ipi(struct pt_regs *regs)
> case IPI_RESCHEDULE:
> /* Reschedule callback. Everything to be done
> is done by the interrupt return path. */
> + scheduler_ipi();
> break;
>
> case IPI_CALL_FUNC:
> diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
> index 9066473..ffde790 100644
> --- a/arch/arm/kernel/smp.c
> +++ b/arch/arm/kernel/smp.c
> @@ -579,6 +579,7 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs)
> * nothing more to do - eveything is
> * done on the interrupt return path
> */
> + scheduler_ipi();
> break;
>
> case IPI_CALL_FUNC:
> diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
> index a17107a..e210f8a 100644
> --- a/arch/blackfin/mach-common/smp.c
> +++ b/arch/blackfin/mach-common/smp.c
> @@ -156,6 +156,7 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance)
> case BFIN_IPI_RESCHEDULE:
> /* That's the easiest one; leave it to
> * return_from_int. */
> + scheduler_ipi();
> kfree(msg);
> break;
> case BFIN_IPI_CALL_FUNC:
> @@ -301,7 +302,7 @@ void smp_send_reschedule(int cpu)
>
> msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
> if (!msg)
> - return;
> + return; /* XXX unreliable needs fixing ! */
> INIT_LIST_HEAD(&msg->list);
> msg->type = BFIN_IPI_RESCHEDULE;
>
> diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
> index 84fed3b..86e3c76 100644
> --- a/arch/cris/arch-v32/kernel/smp.c
> +++ b/arch/cris/arch-v32/kernel/smp.c
> @@ -340,15 +340,18 @@ irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id)
>
> ipi = REG_RD(intr_vect, irq_regs[smp_processor_id()], rw_ipi);
>
> + if (ipi.vector & IPI_SCHEDULE) {
> + scheduler_ipi();
> + }
> if (ipi.vector & IPI_CALL) {
> - func(info);
> + func(info);
> }
> if (ipi.vector & IPI_FLUSH_TLB) {
> - if (flush_mm == FLUSH_ALL)
> - __flush_tlb_all();
> - else if (flush_vma == FLUSH_ALL)
> + if (flush_mm == FLUSH_ALL)
> + __flush_tlb_all();
> + else if (flush_vma == FLUSH_ALL)
> __flush_tlb_mm(flush_mm);
> - else
> + else
> __flush_tlb_page(flush_vma, flush_addr);
> }
>
> diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c
> index 9a26015..a580230 100644
> --- a/arch/ia64/kernel/irq_ia64.c
> +++ b/arch/ia64/kernel/irq_ia64.c
> @@ -31,6 +31,7 @@
> #include <linux/irq.h>
> #include <linux/ratelimit.h>
> #include <linux/acpi.h>
> +#include <linux/sched.h>
>
> #include <asm/delay.h>
> #include <asm/intrinsics.h>
> @@ -496,6 +497,7 @@ ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
> smp_local_flush_tlb();
> kstat_incr_irqs_this_cpu(irq, desc);
> } else if (unlikely(IS_RESCHEDULE(vector))) {
> + scheduler_ipi();
> kstat_incr_irqs_this_cpu(irq, desc);
> } else {
> ia64_setreg(_IA64_REG_CR_TPR, vector);
> diff --git a/arch/ia64/xen/irq_xen.c b/arch/ia64/xen/irq_xen.c
> index a3fb7cf..2f235a3 100644
> --- a/arch/ia64/xen/irq_xen.c
> +++ b/arch/ia64/xen/irq_xen.c
> @@ -92,6 +92,8 @@ static unsigned short saved_irq_cnt;
> static int xen_slab_ready;
>
> #ifdef CONFIG_SMP
> +#include <linux/sched.h>
> +
> /* Dummy stub. Though we may check XEN_RESCHEDULE_VECTOR before __do_IRQ,
> * it ends up to issue several memory accesses upon percpu data and
> * thus adds unnecessary traffic to other paths.
> @@ -99,7 +101,13 @@ static int xen_slab_ready;
> static irqreturn_t
> xen_dummy_handler(int irq, void *dev_id)
> {
> + return IRQ_HANDLED;
> +}
>
> +static irqreturn_t
> +xen_resched_handler(int irq, void *dev_id)
> +{
> + scheduler_ipi();
> return IRQ_HANDLED;
> }
>
> @@ -110,7 +118,7 @@ static struct irqaction xen_ipi_irqaction = {
> };
>
> static struct irqaction xen_resched_irqaction = {
> - .handler = xen_dummy_handler,
> + .handler = xen_resched_handler,
> .flags = IRQF_DISABLED,
> .name = "resched"
> };
> diff --git a/arch/m32r/kernel/smp.c b/arch/m32r/kernel/smp.c
> index 31cef20..f0ecc3f 100644
> --- a/arch/m32r/kernel/smp.c
> +++ b/arch/m32r/kernel/smp.c
> @@ -138,7 +138,7 @@ void smp_send_reschedule(int cpu_id)
> *==========================================================================*/
> void smp_reschedule_interrupt(void)
> {
> - /* nothing to do */
> + scheduler_ipi();
> }
>
> /*==========================================================================*
> diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
> index 39c0825..0443e91 100644
> --- a/arch/mips/kernel/smtc.c
> +++ b/arch/mips/kernel/smtc.c
> @@ -931,6 +931,7 @@ static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
> static void ipi_resched_interrupt(void)
> {
> /* Return from interrupt should be enough to cause scheduler check */
> + scheduler_ipi();
> }
>
> static void ipi_call_interrupt(void)
> diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
> index 47b347c..513a301 100644
> --- a/arch/mips/sibyte/bcm1480/smp.c
> +++ b/arch/mips/sibyte/bcm1480/smp.c
> @@ -20,6 +20,7 @@
> #include <linux/delay.h>
> #include <linux/smp.h>
> #include <linux/kernel_stat.h>
> +#include <linux/sched.h>
>
> #include <asm/mmu_context.h>
> #include <asm/io.h>
> @@ -189,10 +190,8 @@ void bcm1480_mailbox_interrupt(void)
> /* Clear the mailbox to clear the interrupt */
> __raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
>
> - /*
> - * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
> - * interrupt will do the reschedule for us
> - */
> + if (actione & SMP_RESCHEDULE_YOURSELF)
> + scheduler_ipi();
>
> if (action & SMP_CALL_FUNCTION)
> smp_call_function_interrupt();
> diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
> index c00a5cb..38e7f6b 100644
> --- a/arch/mips/sibyte/sb1250/smp.c
> +++ b/arch/mips/sibyte/sb1250/smp.c
> @@ -21,6 +21,7 @@
> #include <linux/interrupt.h>
> #include <linux/smp.h>
> #include <linux/kernel_stat.h>
> +#include <linux/sched.h>
>
> #include <asm/mmu_context.h>
> #include <asm/io.h>
> @@ -177,10 +178,8 @@ void sb1250_mailbox_interrupt(void)
> /* Clear the mailbox to clear the interrupt */
> ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
>
> - /*
> - * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
> - * interrupt will do the reschedule for us
> - */
> + if (action & SMP_RESCHEDULE_YOURSELF)
> + scheduler_ipi();
>
> if (action & SMP_CALL_FUNCTION)
> smp_call_function_interrupt();
> diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c
> index 0dcd1c6..17f16ca 100644
> --- a/arch/mn10300/kernel/smp.c
> +++ b/arch/mn10300/kernel/smp.c
> @@ -471,7 +471,7 @@ void smp_send_stop(void)
> */
> static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id)
> {
> - /* do nothing */
> + scheduler_ipi();
> return IRQ_HANDLED;
> }
>
> diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c
> index 69d63d3..f8f7970 100644
> --- a/arch/parisc/kernel/smp.c
> +++ b/arch/parisc/kernel/smp.c
> @@ -155,6 +155,7 @@ ipi_interrupt(int irq, void *dev_id)
>
> case IPI_RESCHEDULE:
> smp_debug(100, KERN_DEBUG "CPU%d IPI_RESCHEDULE\n", this_cpu);
> + scheduler_ipi();
> /*
> * Reschedule callback. Everything to be
> * done is done by the interrupt return path.
> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> index 68034bb..7ee0fc3 100644
> --- a/arch/powerpc/kernel/smp.c
> +++ b/arch/powerpc/kernel/smp.c
> @@ -128,6 +128,7 @@ static irqreturn_t call_function_action(int irq, void *data)
> static irqreturn_t reschedule_action(int irq, void *data)
> {
> /* we just need the return path side effect of checking need_resched */
> + scheduler_ipi();
> return IRQ_HANDLED;
> }
>
> diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
> index 94cf510..61789e8 100644
> --- a/arch/s390/kernel/smp.c
> +++ b/arch/s390/kernel/smp.c
> @@ -163,12 +163,12 @@ static void do_ext_call_interrupt(unsigned int ext_int_code,
>
> /*
> * handle bit signal external calls
> - *
> - * For the ec_schedule signal we have to do nothing. All the work
> - * is done automatically when we return from the interrupt.
> */
> bits = xchg(&S390_lowcore.ext_call_fast, 0);
>
> + if (test_bit(ec_schedule, &bits))
> + scheduler_ipi();
> +
> if (test_bit(ec_call_function, &bits))
> generic_smp_call_function_interrupt();
>
> diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
> index 509b36b..6207561 100644
> --- a/arch/sh/kernel/smp.c
> +++ b/arch/sh/kernel/smp.c
> @@ -20,6 +20,7 @@
> #include <linux/module.h>
> #include <linux/cpu.h>
> #include <linux/interrupt.h>
> +#include <linux/sched.h>
> #include <asm/atomic.h>
> #include <asm/processor.h>
> #include <asm/system.h>
> @@ -323,6 +324,7 @@ void smp_message_recv(unsigned int msg)
> generic_smp_call_function_interrupt();
> break;
> case SMP_MSG_RESCHEDULE:
> + scheduler_ipi();
> break;
> case SMP_MSG_FUNCTION_SINGLE:
> generic_smp_call_function_single_interrupt();
> diff --git a/arch/sparc/kernel/smp_32.c b/arch/sparc/kernel/smp_32.c
> index 91c10fb..042d8c9 100644
> --- a/arch/sparc/kernel/smp_32.c
> +++ b/arch/sparc/kernel/smp_32.c
> @@ -125,7 +125,7 @@ struct linux_prom_registers smp_penguin_ctable __cpuinitdata = { 0 };
>
> void smp_send_reschedule(int cpu)
> {
> - /* See sparc64 */
> + scheduler_ipi();
> }
>
> void smp_send_stop(void)
> diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
> index b6a2b8f..68e26e2 100644
> --- a/arch/sparc/kernel/smp_64.c
> +++ b/arch/sparc/kernel/smp_64.c
> @@ -1369,6 +1369,7 @@ void smp_send_reschedule(int cpu)
> void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
> {
> clear_softint(1 << irq);
> + scheduler_ipi();
> }
>
> /* This is a nop because we capture all other cpus
> diff --git a/arch/tile/kernel/smp.c b/arch/tile/kernel/smp.c
> index 9575b37..91a1ddf 100644
> --- a/arch/tile/kernel/smp.c
> +++ b/arch/tile/kernel/smp.c
> @@ -190,6 +190,7 @@ static irqreturn_t handle_reschedule_ipi(int irq, void *token)
> * profiler count in the meantime.
> */
> __get_cpu_var(irq_stat).irq_resched_count++;
> + scheduler_ipi();
>
> return IRQ_HANDLED;
> }
> diff --git a/arch/um/kernel/smp.c b/arch/um/kernel/smp.c
> index 106bf27..eefb107 100644
> --- a/arch/um/kernel/smp.c
> +++ b/arch/um/kernel/smp.c
> @@ -173,7 +173,7 @@ void IPI_handler(int cpu)
> break;
>
> case 'R':
> - set_tsk_need_resched(current);
> + scheduler_ipi();
> break;
>
> case 'S':
> diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c
> index 513deac..e38c2d8 100644
> --- a/arch/x86/kernel/smp.c
> +++ b/arch/x86/kernel/smp.c
> @@ -202,6 +202,7 @@ void smp_reschedule_interrupt(struct pt_regs *regs)
> {
> ack_APIC_irq();
> inc_irq_stat(irq_resched_count);
> + scheduler_ipi();
> /*
> * KVM uses this interrupt to force a cpu out of guest mode
> */
> diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
> index 72a4c79..6196fb1 100644
> --- a/arch/x86/xen/smp.c
> +++ b/arch/x86/xen/smp.c
> @@ -53,6 +53,7 @@ static irqreturn_t xen_call_function_single_interrupt(int irq, void *dev_id);
> static irqreturn_t xen_reschedule_interrupt(int irq, void *dev_id)
> {
> inc_irq_stat(irq_resched_count);
> + scheduler_ipi();
>
> return IRQ_HANDLED;
> }
> diff --git a/include/linux/sched.h b/include/linux/sched.h
> index 341acbb..aa458dc 100644
> --- a/include/linux/sched.h
> +++ b/include/linux/sched.h
> @@ -2183,6 +2183,7 @@ extern void set_task_comm(struct task_struct *tsk, char *from);
> extern char *get_task_comm(char *to, struct task_struct *tsk);
>
> #ifdef CONFIG_SMP
> +static inline void scheduler_ipi(void) { }
> extern unsigned long wait_task_inactive(struct task_struct *, long match_state);
> #else
> static inline unsigned long wait_task_inactive(struct task_struct *p,
^ permalink raw reply
* Re: [PATCH] sched: provide scheduler_ipi() callback in response to smp_send_reschedule()
From: Peter Zijlstra @ 2011-01-17 20:43 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linux-m32r-ja, linux-mips, linux-ia64, linux-sh, H. Peter Anvin,
Heiko Carstens, Paul Mackerras, Helge Deller, sparclinux,
Linux-Arch, linux-s390, Jesper Nilsson, Jeremy Fitzhardinge,
Russell King, Hirokazu Takata, x86, James E.J. Bottomley,
virtualization, Ingo Molnar, Matt Turner, Fenghua Yu,
Mike Frysinger, user-mode-linux-devel, Konrad Rzeszutek Wilk,
Jeff Dike, Chris Metcalf, xen-devel, Mikael Starvik, linux-m32r,
Ivan Kokshaysky, user-mode-linux-user, uclinux-dist-devel,
Thomas Gleixner, linux-arm-kernel, Richard Henderson, Tony Luck,
linux-parisc, linux-cris-kernel, linux-am33-list, linux-kernel,
Ralf Baechle, Kyle McMartin, Paul Mundt, linux-alpha,
Martin Schwidefsky, linux390, Koichi Yasutake, linuxppc-dev,
David S. Miller
In-Reply-To: <1295296310.2148.29.camel@pasglop>
On Tue, 2011-01-18 at 07:31 +1100, Benjamin Herrenschmidt wrote:
>=20
> Beware of false positive, I've used "fake" reschedule IPIs in the past
> for other things (like kicking a CPU out of sleep state for unrelated
> reasons). Nothing that I know that is upstream today but some of that
> might come back. I'd like to avoid having to add an atomic to know if
> it's a real reschedule, will the scheduler be smart enough to not bother
> with false positives ?=20
Yes it can deal with that, some will be for reschedules, some will be
for ttwu tail ends and x86 too uses this ipi for a few random other
things like kicking kvm out of guest context..
^ permalink raw reply
* [PATCH] watchdog: booke_wdt: clean up status messages
From: Timur Tabi @ 2011-01-17 21:28 UTC (permalink / raw)
To: linuxppc-dev, wim, watchdog
Improve the status messages that are displayed during some operations of the
PowerPC watchdog timer driver. When the watchdog is enabled, the timeout is
displayed as a number of seconds, instead of an obscure "period". The "period"
is the position of a bit in a 64-bit timer register. The higher the value,
the quicker the watchdog timeout occurs. Some people chose a high "period"
value for the timer and get confused as to why the board resets within a
few seconds.
Messages displayed during open and close are now debug messages, so that they
don't clutter the console by default. Finally, printk() is replaced with the
pr_xxx() equivalent.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
drivers/watchdog/booke_wdt.c | 17 ++++++++---------
1 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c
index 7e7ec9c..935d0dd 100644
--- a/drivers/watchdog/booke_wdt.c
+++ b/drivers/watchdog/booke_wdt.c
@@ -221,9 +221,8 @@ static int booke_wdt_open(struct inode *inode, struct file *file)
if (booke_wdt_enabled == 0) {
booke_wdt_enabled = 1;
on_each_cpu(__booke_wdt_enable, NULL, 0);
- printk(KERN_INFO
- "PowerPC Book-E Watchdog Timer Enabled (wdt_period=%d)\n",
- booke_wdt_period);
+ pr_debug("booke_wdt: watchdog enabled (timeout = %llu sec)\n",
+ period_to_sec(booke_wdt_period));
}
spin_unlock(&booke_wdt_lock);
@@ -240,6 +239,7 @@ static int booke_wdt_release(struct inode *inode, struct file *file)
*/
on_each_cpu(__booke_wdt_disable, NULL, 0);
booke_wdt_enabled = 0;
+ pr_debug("booke_wdt: watchdog disabled\n",
#endif
clear_bit(0, &wdt_is_active);
@@ -271,21 +271,20 @@ static int __init booke_wdt_init(void)
{
int ret = 0;
- printk(KERN_INFO "PowerPC Book-E Watchdog Timer Loaded\n");
+ pr_info("PowerPC Book-E Watchdog Timer Loaded\n");
ident.firmware_version = cur_cpu_spec->pvr_value;
ret = misc_register(&booke_wdt_miscdev);
if (ret) {
- printk(KERN_CRIT "Cannot register miscdev on minor=%d: %d\n",
- WATCHDOG_MINOR, ret);
+ pr_err("booke_wdt: cannot register device (minor=%u, ret=%i)\n",
+ WATCHDOG_MINOR, ret);
return ret;
}
spin_lock(&booke_wdt_lock);
if (booke_wdt_enabled == 1) {
- printk(KERN_INFO
- "PowerPC Book-E Watchdog Timer Enabled (wdt_period=%d)\n",
- booke_wdt_period);
+ pr_info("booke_wdt: watchdog enabled (timeout = %llu sec)\n",
+ period_to_sec(booke_wdt_period));
on_each_cpu(__booke_wdt_enable, NULL, 0);
}
spin_unlock(&booke_wdt_lock);
--
1.7.3.4
^ permalink raw reply related
* [PATCH] watchdog: booke_wdt: clean up status messages
From: Timur Tabi @ 2011-01-17 21:29 UTC (permalink / raw)
To: linuxppc-dev, wim, linux-watchdog
Improve the status messages that are displayed during some operations of the
PowerPC watchdog timer driver. When the watchdog is enabled, the timeout is
displayed as a number of seconds, instead of an obscure "period". The "period"
is the position of a bit in a 64-bit timer register. The higher the value,
the quicker the watchdog timeout occurs. Some people chose a high "period"
value for the timer and get confused as to why the board resets within a
few seconds.
Messages displayed during open and close are now debug messages, so that they
don't clutter the console by default. Finally, printk() is replaced with the
pr_xxx() equivalent.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
drivers/watchdog/booke_wdt.c | 17 ++++++++---------
1 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c
index 7e7ec9c..935d0dd 100644
--- a/drivers/watchdog/booke_wdt.c
+++ b/drivers/watchdog/booke_wdt.c
@@ -221,9 +221,8 @@ static int booke_wdt_open(struct inode *inode, struct file *file)
if (booke_wdt_enabled == 0) {
booke_wdt_enabled = 1;
on_each_cpu(__booke_wdt_enable, NULL, 0);
- printk(KERN_INFO
- "PowerPC Book-E Watchdog Timer Enabled (wdt_period=%d)\n",
- booke_wdt_period);
+ pr_debug("booke_wdt: watchdog enabled (timeout = %llu sec)\n",
+ period_to_sec(booke_wdt_period));
}
spin_unlock(&booke_wdt_lock);
@@ -240,6 +239,7 @@ static int booke_wdt_release(struct inode *inode, struct file *file)
*/
on_each_cpu(__booke_wdt_disable, NULL, 0);
booke_wdt_enabled = 0;
+ pr_debug("booke_wdt: watchdog disabled\n",
#endif
clear_bit(0, &wdt_is_active);
@@ -271,21 +271,20 @@ static int __init booke_wdt_init(void)
{
int ret = 0;
- printk(KERN_INFO "PowerPC Book-E Watchdog Timer Loaded\n");
+ pr_info("PowerPC Book-E Watchdog Timer Loaded\n");
ident.firmware_version = cur_cpu_spec->pvr_value;
ret = misc_register(&booke_wdt_miscdev);
if (ret) {
- printk(KERN_CRIT "Cannot register miscdev on minor=%d: %d\n",
- WATCHDOG_MINOR, ret);
+ pr_err("booke_wdt: cannot register device (minor=%u, ret=%i)\n",
+ WATCHDOG_MINOR, ret);
return ret;
}
spin_lock(&booke_wdt_lock);
if (booke_wdt_enabled == 1) {
- printk(KERN_INFO
- "PowerPC Book-E Watchdog Timer Enabled (wdt_period=%d)\n",
- booke_wdt_period);
+ pr_info("booke_wdt: watchdog enabled (timeout = %llu sec)\n",
+ period_to_sec(booke_wdt_period));
on_each_cpu(__booke_wdt_enable, NULL, 0);
}
spin_unlock(&booke_wdt_lock);
--
1.7.3.4
^ permalink raw reply related
* [PATCH] powerpc/mpic: fix mask/unmask timeout message
From: Scott Wood @ 2011-01-17 22:10 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
Don't say that enable timed out when it was disable, and
show which IRQ had the problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/sysdev/mpic.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 7c13426..b0c8469 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -674,7 +674,8 @@ void mpic_unmask_irq(unsigned int irq)
/* make sure mask gets to controller before we return to user */
do {
if (!loops--) {
- printk(KERN_ERR "mpic_enable_irq timeout\n");
+ printk(KERN_ERR "%s: timeout on hwirq %u\n",
+ __func__, src);
break;
}
} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
@@ -695,7 +696,8 @@ void mpic_mask_irq(unsigned int irq)
/* make sure mask gets to controller before we return to user */
do {
if (!loops--) {
- printk(KERN_ERR "mpic_enable_irq timeout\n");
+ printk(KERN_ERR "%s: timeout on hwirq %u\n",
+ __func__, src);
break;
}
} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
--
1.7.0.4
^ permalink raw reply related
* [PATCH] define binding for fsl mpic interrupt controllers
From: Stuart yoder @ 2011-01-17 23:19 UTC (permalink / raw)
To: linuxppc-dev, devicetree-discuss; +Cc: Stuart Yoder
From: Stuart Yoder <stuart.yoder@freescale.com>
define the binding for compatible = "fsl,mpic", including
the definition of 4-cell interrupt specifiers. The
3rd and 4th cells are needed to define additional
types of interrupt source outside the "normal"
external and internal interrupts in FSL SoCs. Define
error interrupt, IPIs, and PIC timer sources.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
---
Documentation/powerpc/dts-bindings/fsl/mpic.txt | 158 +++++++++++++++++------
1 files changed, 116 insertions(+), 42 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/mpic.txt b/Documentation/powerpc/dts-bindings/fsl/mpic.txt
index 71e39cf..e1fe67c 100644
--- a/Documentation/powerpc/dts-bindings/fsl/mpic.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/mpic.txt
@@ -1,42 +1,116 @@
-* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
-
-The OpenPIC specification does not specify which interrupt source has to
-become which interrupt number. This is up to the software implementation
-of the interrupt controller. The only requirement is that every
-interrupt source has to have an unique interrupt number / vector number.
-To accomplish this the current implementation assigns the number zero to
-the first source, the number one to the second source and so on until
-all interrupt sources have their unique number.
-Usually the assigned vector number equals the interrupt number mentioned
-in the documentation for a given core / CPU. This is however not true
-for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
-between internal and external interrupt sources and starts counting at
-zero for both of them.
-
-So what to write for external interrupt source X or internal interrupt
-source Y into the device tree? Here is an example:
-
-The memory map for the interrupt controller in the MPC8544[0] shows,
-that the first interrupt source starts at 0x5_0000 (PIC Register Address
-Map-Interrupt Source Configuration Registers). This source becomes the
-number zero therefore:
- External interrupt 0 = interrupt number 0
- External interrupt 1 = interrupt number 1
- External interrupt 2 = interrupt number 2
- ...
-Every interrupt number allocates 0x20 bytes register space. So to get
-its number it is sufficient to shift the lower 16bits to right by five.
-So for the external interrupt 10 we have:
- 0x0140 >> 5 = 10
-
-After the external sources, the internal sources follow. The in core I2C
-controller on the MPC8544 for instance has the internal source number
-27. Oo obtain its interrupt number we take the lower 16bits of its memory
-address (0x5_0560) and shift it right:
- 0x0560 >> 5 = 43
-
-Therefore the I2C device node for the MPC8544 CPU has to have the
-interrupt number 43 specified in the device tree.
-
-[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
- MPC8544ERM Rev. 1 10/2007
+=====================================================================
+Freescale MPIC Interrupt Controller Node
+Copyright (C) 2010,2011 Freescale Semiconductor Inc.
+=====================================================================
+
+The Freescale MPIC interrupt controller is found on all PowerQUICC
+and QorIQ processors and is compatible with the Open PIC. The
+notable difference from Open PIC binding is the addition of 2
+additional cells in the interrupt specifier defining interrupt type
+information.
+
+PROPERTIES
+
+ - compatible
+ Usage: required
+ Value type: <string>
+ Definition: Shall include "fsl,mpic". Freescale MPIC
+ controlers compatible with this binding have Block
+ Revision Registers BRR1 and BRR2 at offset 0x0 and
+ 0x10 in the MPIC.
+
+ - reg
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: A standard property. Specifies the physical
+ offset and length of the device's registers within the
+ CCSR address space.
+
+ - interrupt-controller
+ Usage: required
+ Value type: <empty>
+ Definition: Specifies that this node is an interrupt
+ controller
+
+ - #interrupt-cells
+ Usage: required
+ Value type: <u32>
+ Definition: Shall be 2 or 4. A value of 2 means that interrupt
+ specifiers do not contain the interrupt-type or type-specific
+ information cells.
+
+ - #address-cells
+ Usage: required
+ Value type: <u32>
+ Definition: Shall be 0.
+
+INTERRUPT SPECIFIER DEFINITION
+
+ Interrupt specifiers consists of 4 cells encoded as
+ follows:
+
+ <1st-cell> interrupt-number
+
+ Identifies the interrupt source. The MPIC
+ contains a block of registers referred
+ to as the "Interrupt Source Configuration
+ Registers". Each source has 32-bytes of
+ registers (vector/priority and destination)
+ in this region. So interrupt 0 is at
+ offset 0x0, interrupt 1 is at offset 0x20,
+ and so on.
+
+ <2nd-cell> level-sense information, encoded as follows:
+ 0 = low-to-high edge triggered
+ 1 = active low level-sensitive
+ 2 = active high level-sensitive
+ 3 = high-to-low edge triggered
+
+ <3rd-cell> interrupt-type
+
+ The following types are supported:
+
+ 0 = external or normal SoC device interrupt
+
+ The interrupt-number field contains
+ the SoC device interrupt number. The
+ type-specific cell is undefined.
+
+ 1 = error interrupt
+
+ The interrupt-number field contains
+ the SoC device interrupt number for
+ the error interrupt. The type-specific
+ cell identifies the specific error
+ interrupt number.
+
+ 2 = MPIC inter-processor interrupt (IPI)
+
+ The interrupt-number field identifies
+ the MPIC IPI number. The type-specific
+ cell is undefined.
+
+ 3 = MPIC timer interrupt
+
+ The interrupt-number field identifies
+ the MPIC timer number. The type-specific
+ cell is undefined.
+
+ <4th-cell> type-specific information
+
+ The type-specific cell is encoded as follows:
+
+ - For interrupt-type 1 (error interrupt),
+ the type-specific field contains the
+ bit number of the error interrupt in the
+ Error Interrupt Summary Register.
+
+EXAMPLE
+
+ mpic: pic@40000 {
+ compatible = "fsl,mpic";
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ #address-cells = <0>;
+ reg = <0x40000 0x40000>;
+ };
--
1.7.2.2
^ permalink raw reply related
* [PATCH v3] ppc: update dynamic dma support
From: Nishanth Aravamudan @ 2011-01-18 0:20 UTC (permalink / raw)
To: sonnyrao, miltonm, Benjamin Herrenschmidt, Paul Mackerras,
Grant Likely, Anton Blanchard, linuxppc-dev
In-Reply-To: <20110117173210.GA11085@us.ibm.com>
On 17.01.2011 [09:32:10 -0800], Nishanth Aravamudan wrote:
> On 07.01.2011 [18:53:34 -0800], Nishanth Aravamudan wrote:
> > On 10.12.2010 [16:07:44 -0800], Nishanth Aravamudan wrote:
> > > On 09.12.2010 [11:09:20 -0800], Nishanth Aravamudan wrote:
> > > > On 26.10.2010 [20:35:17 -0700], Nishanth Aravamudan wrote:
> > > > > If firmware allows us to map all of a partition's memory for DMA on a
> > > > > particular bridge, create a 1:1 mapping of that memory. Add hooks for
> > > > > dealing with hotplug events. Dyanmic DMA windows can use larger than the
> > > > > default page size, and we use the largest one possible.
> > > > >
> > > > > Not-yet-signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
> > > > >
> > > > > ---
> > > > >
> > > > > I've tested this briefly on a machine with suitable firmware/hardware.
> > > > > Things seem to work well, but I want to do more exhaustive I/O testing
> > > > > before asking for upstream merging. I would really appreciate any
> > > > > feedback on the updated approach.
> > > > >
> > > > > Specific questions:
> > > > >
> > > > > Ben, did I hook into the dma_set_mask() platform callback as you
> > > > > expected? Anything I can do better or which perhaps might lead to
> > > > > gotchas later?
> > > > >
> > > > > I've added a disable_ddw option, but perhaps it would be better to
> > > > > just disable the feature if iommu=force?
> > > >
> > > > So for the final version, I probably should document this option in
> > > > kernel-parameters.txt w/ the patch, right?
> > >
> > > Here's an updated version. Ben, think you can pick this up to your tree?
> >
> > Hi Ben,
> >
> > I have a small follow-on patch that tidies up the code a bit and deals
> > with an error condition on dlpar remove of ddw slots. I'm putting it
> > below as a follow-on patch, but I can roll it into the v3 patch and post
> > a v4 if you'd prefer?
>
> Sorry, found a few more cleanups (spaces instead of tabs, etc.).
Sigh, this is just embarassing. Milton pointed out that there is no
reason to clutter the asm/ppc-pci.h with RTAS specific declarations that
only apply to DDW. So I have moved them into iommu.c in this version.
Thanks,
Nish
pseries: ddw cleanups
Use symbolic constants to access RTAS responses.
Disable reconfig notifier's clearing of TCEs and removal of DMA window.
This is handled by firmware currently. If the kernel were to do it, we'd
need a new callback action before the isolation of the slot in question,
or else we'd always get permission errors (firmware revokes the window
automatically).
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index 4ba2338..e4050f6 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -285,6 +285,21 @@ struct direct_window {
const struct dynamic_dma_window_prop *prop;
struct list_head list;
};
+
+/* Dynamic DMA Window support */
+struct ddw_query_response {
+ u32 windows_available;
+ u32 largest_available_block;
+ u32 page_size;
+ u32 migration_capable;
+};
+
+struct ddw_create_response {
+ u32 liobn;
+ u32 addr_hi;
+ u32 addr_lo;
+};
+
static LIST_HEAD(direct_window_list);
/* prevents races between memory on/offline and window creation */
static DEFINE_SPINLOCK(direct_window_list_lock);
@@ -323,7 +338,7 @@ static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
dma_offset = next + be64_to_cpu(maprange->dma_base);
rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
- (u64)dma_offset,
+ dma_offset,
0, limit);
num_tce -= limit;
} while (num_tce > 0 && !rc);
@@ -383,7 +398,7 @@ static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
}
rc = plpar_tce_put_indirect(liobn,
- (u64)dma_offset,
+ dma_offset,
(u64)virt_to_abs(tcep),
limit);
@@ -731,7 +746,8 @@ static u64 dupe_ddw_if_kexec(struct pci_dev *dev, struct device_node *pdn)
return dma_addr;
}
-static int query_ddw(struct pci_dev *dev, const u32 *ddr_avail, u32 *query)
+static int query_ddw(struct pci_dev *dev, const u32 *ddr_avail,
+ struct ddw_query_response *query)
{
struct device_node *dn;
struct pci_dn *pcidn;
@@ -751,7 +767,7 @@ static int query_ddw(struct pci_dev *dev, const u32 *ddr_avail, u32 *query)
if (pcidn->eeh_pe_config_addr)
cfg_addr = pcidn->eeh_pe_config_addr;
buid = pcidn->phb->buid;
- ret = rtas_call(ddr_avail[0], 3, 5, query,
+ ret = rtas_call(ddr_avail[0], 3, 5, (u32 *)query,
cfg_addr, BUID_HI(buid), BUID_LO(buid));
dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
" returned %d\n", ddr_avail[0], cfg_addr, BUID_HI(buid),
@@ -759,7 +775,9 @@ static int query_ddw(struct pci_dev *dev, const u32 *ddr_avail, u32 *query)
return ret;
}
-static int create_ddw(struct pci_dev *dev, const u32 *ddr_avail, u32 *create, int page_shift, int window_shift)
+static int create_ddw(struct pci_dev *dev, const u32 *ddr_avail,
+ struct ddw_create_response *create, int page_shift,
+ int window_shift)
{
struct device_node *dn;
struct pci_dn *pcidn;
@@ -782,15 +800,15 @@ static int create_ddw(struct pci_dev *dev, const u32 *ddr_avail, u32 *create, in
do {
/* extra outputs are LIOBN and dma-addr (hi, lo) */
- ret = rtas_call(ddr_avail[1], 5, 4, &create[0], cfg_addr,
+ ret = rtas_call(ddr_avail[1], 5, 4, (u32 *)create, cfg_addr,
BUID_HI(buid), BUID_LO(buid), page_shift, window_shift);
- } while(rtas_busy_delay(ret));
+ } while (rtas_busy_delay(ret));
dev_info(&dev->dev,
"ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
"(liobn = 0x%x starting addr = %x %x)\n", ddr_avail[1],
cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
- window_shift, ret, create[0], create[1], create[2]);
-
+ window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
+
return ret;
}
@@ -808,7 +826,8 @@ static int create_ddw(struct pci_dev *dev, const u32 *ddr_avail, u32 *create, in
static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
{
int len, ret;
- u32 query[4], create[3];
+ struct ddw_query_response query;
+ struct ddw_create_response create;
int page_shift;
u64 dma_addr, max_addr;
struct device_node *dn;
@@ -846,11 +865,11 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
* of page sizes: supported and supported for migrate-dma.
*/
dn = pci_device_to_OF_node(dev);
- ret = query_ddw(dev, ddr_avail, &query[0]);
+ ret = query_ddw(dev, ddr_avail, &query);
if (ret != 0)
goto out_unlock;
- if (!query[0]) {
+ if (query.windows_available == 0) {
/*
* no additional windows are available for this device.
* We might be able to reallocate the existing window,
@@ -859,23 +878,23 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
dev_dbg(&dev->dev, "no free dynamic windows");
goto out_unlock;
}
- if (query[2] & 4) {
+ if (query.page_size & 4) {
page_shift = 24; /* 16MB */
- } else if (query[2] & 2) {
+ } else if (query.page_size & 2) {
page_shift = 16; /* 64kB */
- } else if (query[2] & 1) {
+ } else if (query.page_size & 1) {
page_shift = 12; /* 4kB */
} else {
dev_dbg(&dev->dev, "no supported direct page size in mask %x",
- query[2]);
+ query.page_size);
goto out_unlock;
}
/* verify the window * number of ptes will map the partition */
/* check largest block * page size > max memory hotplug addr */
max_addr = memory_hotplug_max();
- if (query[1] < (max_addr >> page_shift)) {
+ if (query.largest_available_block < (max_addr >> page_shift)) {
dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
- "%llu-sized pages\n", max_addr, query[1],
+ "%llu-sized pages\n", max_addr, query.largest_available_block,
1ULL << page_shift);
goto out_unlock;
}
@@ -894,19 +913,17 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
goto out_free_prop;
}
- ret = create_ddw(dev, ddr_avail, &create[0], page_shift, len);
+ ret = create_ddw(dev, ddr_avail, &create, page_shift, len);
if (ret != 0)
goto out_free_prop;
- *ddwprop = (struct dynamic_dma_window_prop) {
- .liobn = cpu_to_be32(create[0]),
- .dma_base = cpu_to_be64(((u64)create[1] << 32) + (u64)create[2]),
- .tce_shift = cpu_to_be32(page_shift),
- .window_shift = cpu_to_be32(len)
- };
+ ddwprop->liobn = cpu_to_be32(create.liobn);
+ ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2));
+ ddwprop->tce_shift = cpu_to_be32(page_shift);
+ ddwprop->window_shift = cpu_to_be32(len);
dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
- create[0], dn->full_name);
+ create.liobn, dn->full_name);
window = kzalloc(sizeof(*window), GFP_KERNEL);
if (!window)
@@ -933,7 +950,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
list_add(&window->list, &direct_window_list);
spin_unlock(&direct_window_list_lock);
- dma_addr = of_read_number(&create[1], 2);
+ dma_addr = of_read_number(&create.addr_hi, 2);
set_dma_offset(&dev->dev, dma_addr);
goto out_unlock;
@@ -1015,7 +1032,7 @@ static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
dn = pci_device_to_OF_node(pdev);
dev_dbg(dev, "node is %s\n", dn->full_name);
- /*
+ /*
* the device tree might contain the dma-window properties
* per-device and not neccesarily for the bus. So we need to
* search upwards in the tree until we either hit a dma-window
@@ -1118,7 +1135,15 @@ static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long acti
}
spin_unlock(&direct_window_list_lock);
- remove_ddw(np);
+ /*
+ * Because the notifier runs after isolation of the
+ * slot, we are guaranteed any DMA window has already
+ * been revoked and the TCEs have been marked invalid,
+ * so we don't need a call to remove_ddw(np). However,
+ * if an additional notifier action is added before the
+ * isolate call, we should update this code for
+ * completeness with such a call.
+ */
break;
default:
err = NOTIFY_DONE;
--
Nishanth Aravamudan <nacc@us.ibm.com>
IBM Linux Technology Center
^ permalink raw reply related
* [PATCH 0/2]: powerpc: MPIC binding and 'no-reset' implementation
From: Meador Inge @ 2011-01-18 0:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: minge, devicetree-discuss, Blanchard, Hollis
This patch set provides a binding for the MPIC and implements support
for a new property, specified by that binding, called 'no-reset'.
Signed-off-by: Meador Inge <meador_inge@mentor.com>
CC: Hollis Blanchard <hollis_blanchard@mentor.com>
^ permalink raw reply
* [PATCH 1/2] powerpc: document the MPIC device tree binding
From: Meador Inge @ 2011-01-18 0:52 UTC (permalink / raw)
To: linuxppc-dev; +Cc: minge, devicetree-discuss, Blanchard, Hollis
This binding documents several properties that have been in use for
quite some time, and adds one new property 'no-reset', which controls
whether the MPIC should be reset during runtime initialization.
Signed-off-by: Meador Inge <meador_inge@mentor.com>
CC: Hollis Blanchard <hollis_blanchard@mentor.com>
---
Documentation/powerpc/dts-bindings/mpic.txt | 78
+++++++++++++++++++++++++++
1 files changed, 78 insertions(+), 0 deletions(-)
create mode 100644 Documentation/powerpc/dts-bindings/mpic.txt
diff --git a/Documentation/powerpc/dts-bindings/mpic.txt
b/Documentation/powerpc/dts-bindings/mpic.txt
new file mode 100644
index 0000000..3a67919
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/mpic.txt
@@ -0,0 +1,78 @@
+* MPIC Binding
+
+This binding specifies what properties and child nodes must be available on
+the device tree representation of the "MPIC" interrupt controller. This
+binding is based on the binding defined for Open PIC in [1] and is a
superset
+of that binding.
+
+** Required properties:
+
+ NOTE: Many of these descriptions were paraphrased from [1] to aid
+ readability.
+
+ - name : Specifies the name of the MPIC.
+ - device_type : Specifies the device type of this MPIC. The value
of this
+ property shall be "open-pic".
+ - reg : Specifies the base physical address(s) and size(s) of this
MPIC's
+ addressable register space.
+ - compatible : Specifies the compatibility list for the MPIC. The
property
+ value shall include "chrp,open-pic".
+ - interrupt-controller : The presence of this property identifies
the node
+ as a MPIC. No property value should be
defined.
+ - #address-cells : Specifies the number of cells needed to encode an
+ address. The value of this property shall always
be 0
+ so that 'interrupt-map' nodes do not have to
specify a
+ parent unit address.
+ - #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source.
+
+** Optional properties:
+
+ - no-reset : The presence of this property indicates that the MPIC
+ should not be reset during runtime initialization.
+ - protected-sources : Specifies a list of interrupt sources that are
not
+ available for use and whose corresponding vectors
+ should not be initialized. A typical use case for
+ this property is in AMP systems where multiple
+ independent operating systems need to share
the MPIC
+ without clobbering each other.
+
+** Example:
+
+ mpic: pic@40000 {
+ // This is an interrupt controller node.
+ interrupt-controller;
+
+ // No address cells so that 'interrupt-map' nodes which reference
+ // this MPIC node do not need a parent address specifier.
+ #address-cells = <0>;
+
+ // Two cell to encode interrupt sources.
+ #interrupt-cells = <2>;
+
+ // Offset address of 0x40000 and size of 0x40000.
+ reg = <0x40000 0x40000>;
+
+ // Compatible with Open PIC.
+ compatible = "chrp,open-pic";
+
+ // An Open PIC device.
+ device_type = "open-pic";
+
+ // The sources 0xb1 and 0xb2 are off limits for use and should
not be
+ // initialized by the OS.
+ protected-sources = <0xb1 0xb2>;
+
+ // The MPIC should not be reset.
+ no-reset;
+ };
+
+* References
+
+[1] PowerPC Microprocessor Common Hardware Reference Platform (CHRP)
Binding,
+ Version 1.8, 1998. Published by the Open Firmware Working Group.
+ (http://playground.sun.com/1275/bindings/chrp/chrp1_8a.ps)
+[2] Open Firmware Recommended Practice: Interrupt Mapping, Version 0.9.
1996.
+ Published by the Open Firmware Working Group.
+ (http://playground.sun.com/1275/practice/imap/imap0_9d.pdf)
+
-- 1.6.3.3
^ permalink raw reply related
* [PATCH 2/2] powerpc: make MPIC honor the 'no-reset' device tree property
From: Meador Inge @ 2011-01-18 0:54 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Meador Inge, devicetree-discuss, Blanchard, Hollis
This property, defined in the MPIC binding, tells the kernel not to use
the reset bit in the global configuration register.
Signed-off-by: Meador Inge <meador_inge@mentor.com>
CC: Hollis Blanchard <hollis_blanchard@mentor.com>
---
arch/powerpc/sysdev/mpic.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 30c44e6..44aa2c3 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1157,7 +1157,9 @@ struct mpic * __init mpic_alloc(struct device_node
*node,
mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
/* Reset */
- if (flags & MPIC_WANTS_RESET) {
+ if ((flags & MPIC_WANTS_RESET) &&
+ !of_find_property(node, "no-reset", NULL)) {
+ printk(KERN_DEBUG "mpic: Resetting\n");
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
| MPIC_GREG_GCONF_RESET);
-- 1.6.3.3
^ permalink raw reply related
* Re: [PATCH] define binding for fsl mpic interrupt controllers
From: Meador Inge @ 2011-01-18 1:21 UTC (permalink / raw)
To: Stuart Yoder
Cc: Meador Inge, Blanchard, Hollis, devicetree-discuss, linuxppc-dev
In-Reply-To: <AANLkTim5i89k4OpUBWw0UgMoa5vwN5eSZ1MCs34S0VXB@mail.gmail.com>
Hi Stuart,
> From: Stuart Yoder<stuart.yoder@freescale.com>
>
> define the binding for compatible = "fsl,mpic", including
> the definition of 4-cell interrupt specifiers. The
> 3rd and 4th cells are needed to define additional
> types of interrupt source outside the "normal"
> external and internal interrupts in FSL SoCs. Define
> error interrupt, IPIs, and PIC timer sources.
Recently I posted an RFC concerning a binding for the MPIC [1]. I also
submitted a patch based on that feedback today (patch subject '[PATCH
1/2] powerpc: document the MPIC device tree binding'). You provide much
more information concerning the interrupt sources and how interrupt
specifiers are encoded. I had a few more properties listed: 'name',
'device_type', 'protected-sources', and 'no-reset'. The 'no-reset'
property is a proposed addition to the binding, the others are already
in use.
Perhaps we should merge the proposals?
[1] http://lists.ozlabs.org/pipermail/linuxppc-dev/2010-December/087644.html
> Signed-off-by: Stuart Yoder<stuart.yoder@freescale.com>
> ---
> Documentation/powerpc/dts-bindings/fsl/mpic.txt | 158 +++++++++++++++++------
> 1 files changed, 116 insertions(+), 42 deletions(-)
>
> diff --git a/Documentation/powerpc/dts-bindings/fsl/mpic.txt
> b/Documentation/powerpc/dts-bindings/fsl/mpic.txt
> index 71e39cf..e1fe67c 100644
> --- a/Documentation/powerpc/dts-bindings/fsl/mpic.txt
> +++ b/Documentation/powerpc/dts-bindings/fsl/mpic.txt
> @@ -1,42 +1,116 @@
> -* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
> -
> -The OpenPIC specification does not specify which interrupt source has to
> -become which interrupt number. This is up to the software implementation
> -of the interrupt controller. The only requirement is that every
> -interrupt source has to have an unique interrupt number / vector number.
> -To accomplish this the current implementation assigns the number zero to
> -the first source, the number one to the second source and so on until
> -all interrupt sources have their unique number.
> -Usually the assigned vector number equals the interrupt number mentioned
> -in the documentation for a given core / CPU. This is however not true
> -for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
> -between internal and external interrupt sources and starts counting at
> -zero for both of them.
> -
> -So what to write for external interrupt source X or internal interrupt
> -source Y into the device tree? Here is an example:
> -
> -The memory map for the interrupt controller in the MPC8544[0] shows,
> -that the first interrupt source starts at 0x5_0000 (PIC Register Address
> -Map-Interrupt Source Configuration Registers). This source becomes the
> -number zero therefore:
> - External interrupt 0 = interrupt number 0
> - External interrupt 1 = interrupt number 1
> - External interrupt 2 = interrupt number 2
> - ...
> -Every interrupt number allocates 0x20 bytes register space. So to get
> -its number it is sufficient to shift the lower 16bits to right by five.
> -So for the external interrupt 10 we have:
> - 0x0140>> 5 = 10
> -
> -After the external sources, the internal sources follow. The in core I2C
> -controller on the MPC8544 for instance has the internal source number
> -27. Oo obtain its interrupt number we take the lower 16bits of its memory
> -address (0x5_0560) and shift it right:
> - 0x0560>> 5 = 43
> -
> -Therefore the I2C device node for the MPC8544 CPU has to have the
> -interrupt number 43 specified in the device tree.
> -
> -[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family
> Reference Manual
> - MPC8544ERM Rev. 1 10/2007
> +=====================================================================
> +Freescale MPIC Interrupt Controller Node
> +Copyright (C) 2010,2011 Freescale Semiconductor Inc.
> +=====================================================================
> +
> +The Freescale MPIC interrupt controller is found on all PowerQUICC
> +and QorIQ processors and is compatible with the Open PIC. The
> +notable difference from Open PIC binding is the addition of 2
> +additional cells in the interrupt specifier defining interrupt type
> +information.
> +
> +PROPERTIES
> +
> + - compatible
> + Usage: required
> + Value type:<string>
> + Definition: Shall include "fsl,mpic". Freescale MPIC
> + controlers compatible with this binding have Block
> + Revision Registers BRR1 and BRR2 at offset 0x0 and
> + 0x10 in the MPIC.
> +
> + - reg
> + Usage: required
> + Value type:<prop-encoded-array>
> + Definition: A standard property. Specifies the physical
> + offset and length of the device's registers within the
> + CCSR address space.
> +
> + - interrupt-controller
> + Usage: required
> + Value type:<empty>
> + Definition: Specifies that this node is an interrupt
> + controller
> +
> + - #interrupt-cells
> + Usage: required
> + Value type:<u32>
> + Definition: Shall be 2 or 4. A value of 2 means that interrupt
> + specifiers do not contain the interrupt-type or type-specific
> + information cells.
> +
> + - #address-cells
> + Usage: required
> + Value type:<u32>
> + Definition: Shall be 0.
> +
> +INTERRUPT SPECIFIER DEFINITION
> +
> + Interrupt specifiers consists of 4 cells encoded as
> + follows:
> +
> +<1st-cell> interrupt-number
> +
> + Identifies the interrupt source. The MPIC
> + contains a block of registers referred
> + to as the "Interrupt Source Configuration
> + Registers". Each source has 32-bytes of
> + registers (vector/priority and destination)
> + in this region. So interrupt 0 is at
> + offset 0x0, interrupt 1 is at offset 0x20,
> + and so on.
> +
> +<2nd-cell> level-sense information, encoded as follows:
> + 0 = low-to-high edge triggered
> + 1 = active low level-sensitive
> + 2 = active high level-sensitive
> + 3 = high-to-low edge triggered
> +
> +<3rd-cell> interrupt-type
> +
> + The following types are supported:
> +
> + 0 = external or normal SoC device interrupt
> +
> + The interrupt-number field contains
> + the SoC device interrupt number. The
> + type-specific cell is undefined.
> +
> + 1 = error interrupt
> +
> + The interrupt-number field contains
> + the SoC device interrupt number for
> + the error interrupt. The type-specific
> + cell identifies the specific error
> + interrupt number.
> +
> + 2 = MPIC inter-processor interrupt (IPI)
> +
> + The interrupt-number field identifies
> + the MPIC IPI number. The type-specific
> + cell is undefined.
> +
> + 3 = MPIC timer interrupt
> +
> + The interrupt-number field identifies
> + the MPIC timer number. The type-specific
> + cell is undefined.
> +
> +<4th-cell> type-specific information
> +
> + The type-specific cell is encoded as follows:
> +
> + - For interrupt-type 1 (error interrupt),
> + the type-specific field contains the
> + bit number of the error interrupt in the
> + Error Interrupt Summary Register.
> +
> +EXAMPLE
> +
> + mpic: pic@40000 {
> + compatible = "fsl,mpic";
> + interrupt-controller;
> + #interrupt-cells =<4>;
> + #address-cells =<0>;
> + reg =<0x40000 0x40000>;
> + };
> --
> 1.7.2.2
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
>
>
--
Meador Inge | meador_inge AT mentor.com
Mentor Embedded | http://www.mentor.com/embedded-software
^ permalink raw reply
* 2.6.37-git17 virtual IO boot failure
From: Anton Blanchard @ 2011-01-18 1:31 UTC (permalink / raw)
To: nacc; +Cc: linuxppc-dev
Hi,
I was testing 2.6.37-git17 on a POWER7 with virtual IO and hit this:
Trying to unpack rootfs image as initramfs...
Freeing initrd memory: 7446k freed
vio 30000000: Warning: IOMMU dma not supported: mask
0xffffffffffffffff, table unavailable
vio 4000: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
table unavailable
vio 4001: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
table unavailable
vio 4002: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
table unavailable
vio 4004: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
table unavailable
audit: initializing netlink socket (disabled)
Haven't had a chance to look closer yet.
Anton
^ permalink raw reply
* RE: [PATCH] ATA: Add FSL sata v2 controller support
From: Zang Roy-R61911 @ 2011-01-18 3:01 UTC (permalink / raw)
To: Sergei Shtylyov, Xu Lei-B33228
Cc: jgarzik@pobox.com, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, linux-ide@vger.kernel.org
In-Reply-To: <4D342C6E.6000608@ru.mvista.com>
> -----Original Message-----
> From: Sergei Shtylyov [mailto:sshtylyov@mvista.com]
> Sent: Monday, January 17, 2011 19:48 PM
> To: Xu Lei-B33228
> Cc: linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; jgarzik@pobox.com;
> linux-ide@vger.kernel.org; Zang Roy-R61911
> Subject: Re: [PATCH] ATA: Add FSL sata v2 controller support
>=20
> Hello.
>=20
> On 17-01-2011 10:10, Xulei wrote:
>=20
> > In FSL sata v2 block, the snoop bit of PRDT Word3 description
> > information is at bit28 instead of bit22.
>=20
> > This patch adds FSL sata v2 probe and resolve this difference.
>=20
> > Signed-off-by: Xulei <B33228@freescale.com>
>=20
[snip]
> > diff --git a/arch/powerpc/boot/dts/p1022ds.dts
> b/arch/powerpc/boot/dts/p1022ds.dts
> > index 2bbecbb..9ad41dd 100644
> > --- a/arch/powerpc/boot/dts/p1022ds.dts
> > +++ b/arch/powerpc/boot/dts/p1022ds.dts
> > @@ -475,14 +475,14 @@
> > };
> >
> > sata@18000 {
> > - compatible =3D "fsl,mpc8536-sata", "fsl,pq-sata";
> > + compatible =3D "fsl,p1022-sata", "fsl,pq-sata-v2";
> > reg =3D<0x18000 0x1000>;
> > cell-index =3D<1>;
> > interrupts =3D<74 0x2>;
> > };
> >
> > sata@19000 {
> > - compatible =3D "fsl,mpc8536-sata", "fsl,pq-sata";
> > + compatible =3D "fsl,p1022-sata", "fsl,pq-sata-v2";
> > reg =3D<0x19000 0x1000>;
> > cell-index =3D<2>;
> > interrupts =3D<41 0x2>;
>=20
> Please put this into the separate patch and push thru the PPC tree.
I agree to put to them to separate patches, but should we=20
pull in the separate patches to one candidate tree to make
the function work?
Thanks.
Roy
^ permalink raw reply
* Re: Gianfar TCP checksumming broken in 2.6.35+
From: Alex Dubov @ 2011-01-18 7:56 UTC (permalink / raw)
To: mlcreech; +Cc: linuxppc-dev, davem
It appears that I'm hitting an exactly the same problem with my MPC8548=0Ar=
ev2.0 (errata number eTSEC 49).=0A=0AConsidering that it's close to 3 month=
now since this most unfortunate=0Abug was reported, was there any resoluti=
on/patch that can fix it for good?=0A=0A=0A=0A
^ permalink raw reply
* [PATCH] Fix masking of interrupts for 52xx GPT IRQ.
From: Henk Stegeman @ 2011-01-15 1:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Henk Stegeman
In-Reply-To: <fa686aa41003181102i2a702c61h8ecfe05568c2a42e@mail.gmail.com>
When using the GPT as interrupt controller interupts were missing.
It turned out the IrqEn bit of the GPT is not a mask bit, but it also
disables interrupt generation. This modification masks interrupt one
level down the cascade. Note that masking one level down the cascade
is only valid here because the GPT as interrupt ontroller only serves
one IRQ.
Signed-off-by: Henk Stegeman <henk.stegeman@gmail.com>
---
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 25 ++++++++++++++++++++++---
1 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index 6f8ebe1..9ae2045 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -91,7 +91,7 @@ struct mpc52xx_gpt_priv {
struct irq_host *irqhost;
u32 ipb_freq;
u8 wdt_mode;
-
+ int cascade_virq;
#if defined(CONFIG_GPIOLIB)
struct of_gpio_chip of_gc;
#endif
@@ -136,18 +136,35 @@ DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
static void mpc52xx_gpt_irq_unmask(unsigned int virq)
{
struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
+
+ enable_irq(gpt->cascade_virq);
+
+}
+
+static void mpc52xx_gpt_irq_mask(unsigned int virq)
+{
+ struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
+
+ disable_irq(gpt->cascade_virq);
+}
+
+static void mpc52xx_gpt_irq_enable(unsigned int virq)
+{
+ struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
unsigned long flags;
+ dev_dbg(gpt->dev, "%s %d\n", __func__, virq);
spin_lock_irqsave(&gpt->lock, flags);
setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
spin_unlock_irqrestore(&gpt->lock, flags);
}
-static void mpc52xx_gpt_irq_mask(unsigned int virq)
+static void mpc52xx_gpt_irq_disable(unsigned int virq)
{
struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
unsigned long flags;
+ dev_dbg(gpt->dev, "%s %d\n", __func__, virq);
spin_lock_irqsave(&gpt->lock, flags);
clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
spin_unlock_irqrestore(&gpt->lock, flags);
@@ -184,6 +201,8 @@ static struct irq_chip mpc52xx_gpt_irq_chip = {
.name = "MPC52xx GPT",
.unmask = mpc52xx_gpt_irq_unmask,
.mask = mpc52xx_gpt_irq_mask,
+ .enable = mpc52xx_gpt_irq_enable,
+ .disable = mpc52xx_gpt_irq_disable,
.ack = mpc52xx_gpt_irq_ack,
.set_type = mpc52xx_gpt_irq_set_type,
};
@@ -268,7 +287,7 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
spin_unlock_irqrestore(&gpt->lock, flags);
-
+ gpt->cascade_virq = cascade_virq;
dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
}
--
1.5.4.3
^ permalink raw reply related
* [PATCH] powerpc: perf: Fix frequency calculation for overflowing counters (FSL version)
From: Anton Blanchard @ 2011-01-18 10:44 UTC (permalink / raw)
To: Peter Zijlstra
Cc: linux-kernel, Paul Mackerras, Arnaldo Carvalho de Melo,
Scott Wood, Ingo Molnar, linuxppc-dev
In-Reply-To: <1295285881.30950.218.camel@laptop>
> > Does perf_event_fsl_emb.c need this as well (it has almost the same
> > record_and_restart code)?
>
> I would think so.
Good point:
When fixing the frequency calculations for perf on powerpc I forgot
to fix the FSL version.
If we dont set event->hw.last_period the frequency to period calculations
in perf go haywire and we continually throttle/unthrottle the PMU.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
This is only compile tested.
Index: powerpc.git/arch/powerpc/kernel/perf_event_fsl_emb.c
===================================================================
--- powerpc.git.orig/arch/powerpc/kernel/perf_event_fsl_emb.c 2011-01-18 21:23:57.761644115 +1100
+++ powerpc.git/arch/powerpc/kernel/perf_event_fsl_emb.c 2011-01-18 21:25:28.994477247 +1100
@@ -596,6 +596,7 @@ static void record_and_restart(struct pe
if (left <= 0)
left = period;
record = 1;
+ event->hw.last_period = event->hw.sample_period;
}
if (left < 0x80000000LL)
val = 0x80000000LL - left;
^ permalink raw reply
* Re: [PATCH] ATA: Add FSL sata v2 controller support
From: Sergei Shtylyov @ 2011-01-18 11:27 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Xu Lei-B33228, Sergei Shtylyov, jgarzik@pobox.com,
linux-ide@vger.kernel.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <2239AC579C7D3646A720227A37E0268109001B@039-SN1MPN1-004.039d.mgd.msft.net>
Hello.
On 18-01-2011 6:01, Zang Roy-R61911 wrote:
>>> In FSL sata v2 block, the snoop bit of PRDT Word3 description
>>> information is at bit28 instead of bit22.
>>> This patch adds FSL sata v2 probe and resolve this difference.
>>> Signed-off-by: Xulei<B33228@freescale.com>
> [snip]
>>> diff --git a/arch/powerpc/boot/dts/p1022ds.dts
>> b/arch/powerpc/boot/dts/p1022ds.dts
>>> index 2bbecbb..9ad41dd 100644
>>> --- a/arch/powerpc/boot/dts/p1022ds.dts
>>> +++ b/arch/powerpc/boot/dts/p1022ds.dts
>>> @@ -475,14 +475,14 @@
>>> };
>>>
>>> sata@18000 {
>>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>>> reg =<0x18000 0x1000>;
>>> cell-index =<1>;
>>> interrupts =<74 0x2>;
>>> };
>>>
>>> sata@19000 {
>>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>>> reg =<0x19000 0x1000>;
>>> cell-index =<2>;
>>> interrupts =<41 0x2>;
>> Please put this into the separate patch and push thru the PPC tree.
> I agree to put to them to separate patches, but should we
> pull in the separate patches to one candidate tree to make
> the function work?
I don't understand. What is "candidate tree"?
> Thanks.
> Roy
WBR, Sergei
^ permalink raw reply
* RE: [PATCH] ATA: Add FSL sata v2 controller support
From: Zang Roy-R61911 @ 2011-01-18 11:43 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-ide@vger.kernel.org, Xu Lei-B33228, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, jgarzik@pobox.com
In-Reply-To: <4D357918.4040001@ru.mvista.com>
> -----Original Message-----
> From: Sergei Shtylyov [mailto:sshtylyov@mvista.com]
> Sent: Tuesday, January 18, 2011 19:27 PM
> To: Zang Roy-R61911
> Cc: Sergei Shtylyov; Xu Lei-B33228; linuxppc-dev@lists.ozlabs.org; Gala K=
umar-
> B11780; jgarzik@pobox.com; linux-ide@vger.kernel.org
> Subject: Re: [PATCH] ATA: Add FSL sata v2 controller support
>=20
> Hello.
>=20
> On 18-01-2011 6:01, Zang Roy-R61911 wrote:
>=20
> >>> In FSL sata v2 block, the snoop bit of PRDT Word3 description
> >>> information is at bit28 instead of bit22.
>=20
> >>> This patch adds FSL sata v2 probe and resolve this difference.
>=20
> >>> Signed-off-by: Xulei<B33228@freescale.com>
>=20
> > [snip]
>=20
> >>> diff --git a/arch/powerpc/boot/dts/p1022ds.dts
> >> b/arch/powerpc/boot/dts/p1022ds.dts
> >>> index 2bbecbb..9ad41dd 100644
> >>> --- a/arch/powerpc/boot/dts/p1022ds.dts
> >>> +++ b/arch/powerpc/boot/dts/p1022ds.dts
> >>> @@ -475,14 +475,14 @@
> >>> };
> >>>
> >>> sata@18000 {
> >>> - compatible =3D "fsl,mpc8536-sata", "fsl,pq-sata";
> >>> + compatible =3D "fsl,p1022-sata", "fsl,pq-sata-v2";
> >>> reg =3D<0x18000 0x1000>;
> >>> cell-index =3D<1>;
> >>> interrupts =3D<74 0x2>;
> >>> };
> >>>
> >>> sata@19000 {
> >>> - compatible =3D "fsl,mpc8536-sata", "fsl,pq-sata";
> >>> + compatible =3D "fsl,p1022-sata", "fsl,pq-sata-v2";
> >>> reg =3D<0x19000 0x1000>;
> >>> cell-index =3D<2>;
> >>> interrupts =3D<41 0x2>;
>=20
> >> Please put this into the separate patch and push thru the PPC tre=
e.
>=20
> > I agree to put to them to separate patches, but should we
> > pull in the separate patches to one candidate tree to make
> > the function work?
>=20
> I don't understand. What is "candidate tree"?
Powerpc or ide git repository for upstream to mainline.
It is odd that patches for one function in different trees.
Thanks.
Roy
^ permalink raw reply
* Re: [PATCH] ATA: Add FSL sata v2 controller support
From: Sergei Shtylyov @ 2011-01-18 12:33 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Xu Lei-B33228, Sergei Shtylyov, jgarzik@pobox.com,
linux-ide@vger.kernel.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <2239AC579C7D3646A720227A37E02681090699@039-SN1MPN1-004.039d.mgd.msft.net>
Hello.
On 18-01-2011 14:43, Zang Roy-R61911 wrote:
>> On 18-01-2011 6:01, Zang Roy-R61911 wrote:
>>
>>>>> In FSL sata v2 block, the snoop bit of PRDT Word3 description
>>>>> information is at bit28 instead of bit22.
>>>>> This patch adds FSL sata v2 probe and resolve this difference.
>>>>> Signed-off-by: Xulei<B33228@freescale.com>
>>> [snip]
>>>>> diff --git a/arch/powerpc/boot/dts/p1022ds.dts
>>>> b/arch/powerpc/boot/dts/p1022ds.dts
>>>>> index 2bbecbb..9ad41dd 100644
>>>>> --- a/arch/powerpc/boot/dts/p1022ds.dts
>>>>> +++ b/arch/powerpc/boot/dts/p1022ds.dts
>>>>> @@ -475,14 +475,14 @@
>>>>> };
>>>>>
>>>>> sata@18000 {
>>>>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>>>>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>>>>> reg =<0x18000 0x1000>;
>>>>> cell-index =<1>;
>>>>> interrupts =<74 0x2>;
>>>>> };
>>>>>
>>>>> sata@19000 {
>>>>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>>>>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>>>>> reg =<0x19000 0x1000>;
>>>>> cell-index =<2>;
>>>>> interrupts =<41 0x2>;
>>>> Please put this into the separate patch and push thru the PPC tree.
>>> I agree to put to them to separate patches, but should we
>>> pull in the separate patches to one candidate tree to make
>>> the function work?
>> I don't understand. What is "candidate tree"?
> Powerpc or ide git repository for upstream to mainline.
s/ide/libata/
> It is odd that patches for one function in different trees.
The libata tree doesn't need to be concerned with PPC board specific
device trees. Although it's up to the maintainer... just cross post the patch,
and let the corresponding maintainers fogure it out.
> Thanks.
> Roy
WBR, Sergei
^ permalink raw reply
* Problem with Busybox shell
From: MohanReddy koppula @ 2011-01-18 12:54 UTC (permalink / raw)
To: Linuxppc-dev
Hi All,
I am working on an MPC885 based custom board. I am able to boot up the
linux (linux-2.6.33.7). I could see busybox shell (ash) prompt. But it
is not accepting any inputs, I am not able to enter any command, it
just hangs there. I am using ttyCPM0 terminal.
I suspected if there was any problem in CPM driver interrupts
generation and put some printk's in the interrupt handler and could
see interrupts are raised and data is read, but shell is not taking
the input.
I wrote an init.c and opened the ttyCPM0 and tried to read from it,
but couldn't. I am able to write to ttyCPM0 and see it on the host
minicom.
Please some one help me.
thanks in advance for your help.
-Mohan
^ permalink raw reply
* RE: [PATCH] define binding for fsl mpic interrupt controllers
From: Yoder Stuart-B08248 @ 2011-01-18 19:47 UTC (permalink / raw)
To: Meador Inge
Cc: Blanchard, Hollis, devicetree-discuss@lists.ozlabs.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <4D34EB06.9040908@mentor.com>
> -----Original Message-----
> From: Meador Inge [mailto:meador_inge@mentor.com]
> Sent: Monday, January 17, 2011 7:21 PM
> To: Yoder Stuart-B08248
> Cc: linuxppc-dev@lists.ozlabs.org; devicetree-discuss@lists.ozlabs.org;
> Blanchard, Hollis; Meador Inge
> Subject: Re: [PATCH] define binding for fsl mpic interrupt controllers
>=20
> Hi Stuart,
>=20
> > From: Stuart Yoder<stuart.yoder@freescale.com>
> >
> > define the binding for compatible =3D "fsl,mpic", including the
> > definition of 4-cell interrupt specifiers. The 3rd and 4th cells are
> > needed to define additional types of interrupt source outside the
> > "normal"
> > external and internal interrupts in FSL SoCs. Define error interrupt,
> > IPIs, and PIC timer sources.
>=20
> Recently I posted an RFC concerning a binding for the MPIC [1]. I also
> submitted a patch based on that feedback today (patch subject '[PATCH 1/2=
]
> powerpc: document the MPIC device tree binding'). You provide much more
> information concerning the interrupt sources and how interrupt specifiers
> are encoded. I had a few more properties listed: 'name', 'device_type',
> 'protected-sources', and 'no-reset'. The 'no-reset'
> property is a proposed addition to the binding, the others are already in
> use.
>=20
I'm not sure a complete merge into one binding makes sense. The thing that
motivated creating this new binding with 4 cells was a thread from
last year. See:
http://lists.ozlabs.org/pipermail/devicetree-discuss/2010-January/001489.ht=
ml
Since Freescale had the need to represent additional information
in interrupt specifiers (error ints, timers, ipis), the suggestion
at the end was to add additional cells in a FSL-specific binding.
So this really is a Freescale specific thing and does belong in the
Freescale binding directory.
That being said, if there is consensus on the AMP related properties,
I should probably incorporate those as well-- protected-sources
and no-reset.
I'll separately comment on your mpic binding patch.
Stuart=20
^ permalink raw reply
* RE: [PATCH 1/2] powerpc: document the MPIC device tree binding
From: Yoder Stuart-B08248 @ 2011-01-18 20:21 UTC (permalink / raw)
To: Meador Inge
Cc: Blanchard, Hollis, devicetree-discuss@lists.ozlabs.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <AANLkTi=QX4BfLvPfQDMOgmh90TtX4MQqio6AOZR8JKas@mail.gmail.com>
> From: Meador Inge <meador_inge@mentor.com>
> Date: Mon, Jan 17, 2011 at 6:52 PM
> Subject: [PATCH 1/2] powerpc: document the MPIC device tree binding
> To: linuxppc-dev@lists.ozlabs.org
> Cc: minge <meador_inge@mentor.com>,
> devicetree-discuss@lists.ozlabs.org, "Blanchard, Hollis"
> <Hollis_Blanchard@mentor.com>
>=20
>=20
> This binding documents several properties that have been in use for quite
> some time, and adds one new property 'no-reset', which controls whether t=
he
> MPIC should be reset during runtime initialization.
>=20
> Signed-off-by: Meador Inge <meador_inge@mentor.com>
> CC: Hollis Blanchard <hollis_blanchard@mentor.com>
> ---
> =A0Documentation/powerpc/dts-bindings/mpic.txt | =A0 78
This is really the binding for an open-pic interrupt controller
and I think the name should reflect that-- open-pic.txt.
> +++++++++++++++++++++++++++
> =A01 files changed, 78 insertions(+), 0 deletions(-)
> =A0create mode 100644 Documentation/powerpc/dts-bindings/mpic.txt
>=20
> diff --git a/Documentation/powerpc/dts-bindings/mpic.txt
> b/Documentation/powerpc/dts-bindings/mpic.txt
> new file mode 100644
> index 0000000..3a67919
> --- /dev/null
> +++ b/Documentation/powerpc/dts-bindings/mpic.txt
> @@ -0,0 +1,78 @@
> +* MPIC Binding
> +
> +This binding specifies what properties and child nodes must be
> +available on the device tree representation of the "MPIC" interrupt
> +controller. =A0This binding is based on the binding defined for Open PIC
> +in [1] and is a superset of that binding.
I think it would be better to base this on the ePAPR binding which
was based on the original chrp binding. Properties like "name"
and "device_type" are deprecated not being used in flat device trees.
<http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf>
The proposed new properties really should go back into the ePAPR.=20
> +
> +** Required properties:
> +
> + =A0 NOTE: Many of these descriptions were paraphrased from [1] to aid
> + =A0 =A0 =A0 =A0 readability.
> +
> + =A0 - name : Specifies the name of the MPIC.
Drop this. No DTS files use it.
> + =A0 - device_type : Specifies the device type of this MPIC. =A0The valu=
e
> + of this
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 property shall be "open-pic".
device_type is deprecated, since this is not real open-firmware. In
practice the kernel is matching on device_type, but we want to move
away from that to match on "compatible", just hasn't been implemented
yet.
> + =A0 - reg : Specifies the base physical address(s) and size(s) of this
> + MPIC's
> + =A0 =A0 =A0 =A0 =A0 addressable register space.
> + =A0 - compatible : Specifies the compatibility list for the MPIC. =A0Th=
e
> + property
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0value shall include "chrp,open-pic".
In the ePAPR we modified this to just "open-pic", because this has
nothing to do with chrp anymore. I think just "open-pic" is
what we want.
> + =A0 - interrupt-controller : The presence of this property identifies
> + the node
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0as a MPIC. =A0No=
property value should be
> defined.
> + =A0 - #address-cells : Specifies the number of cells needed to encode a=
n
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0address. =A0The value of thi=
s property shall always
> + be 0
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0so that 'interrupt-map' node=
s do not have to
> + specify a
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0parent unit address.
> + =A0 - #interrupt-cells : Specifies the number of cells needed to encode
> + an
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt source.
Should be 2, correct?
> +** Optional properties:
> +
> + =A0 - no-reset : The presence of this property indicates that the MPIC
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0should not be reset during runtime initi=
alization.
> + =A0 - protected-sources : Specifies a list of interrupt sources that ar=
e
> + not
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 available for use and w=
hose corresponding
> + vectors
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 should not be initializ=
ed. =A0A typical use case
> + for
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 this property is in AMP=
systems where multiple
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 independent operating s=
ystems need to share
> + the MPIC
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 without clobbering each=
other.
I do think you need to include the definition of interrupt
specifiers here. Feel free to cut/paste text from my
Freescale mpic binding.
Stuart
^ permalink raw reply
* Re: [PATCH 1/2] powerpc: document the MPIC device tree binding
From: Scott Wood @ 2011-01-18 20:31 UTC (permalink / raw)
To: Meador Inge; +Cc: Blanchard, Hollis, devicetree-discuss, linuxppc-dev
In-Reply-To: <4D34E448.8000902@mentor.com>
On Mon, 17 Jan 2011 18:52:24 -0600
Meador Inge <meador_inge@mentor.com> wrote:
> +** Required properties:
> +
> + NOTE: Many of these descriptions were paraphrased from [1] to aid
> + readability.
> +
> + - name : Specifies the name of the MPIC.
"name" isn't really a property with flat trees. The appropriate
node name, according to the Generic Names recommendation and ePAPR, is
interrupt-controller.
> + - device_type : Specifies the device type of this MPIC. The value
> of this
> + property shall be "open-pic".
Can we drop device_type, and fix the kernel to look for compatible
instead?
> + - compatible : Specifies the compatibility list for the MPIC. The
> property
> + value shall include "chrp,open-pic".
ePAPR wants just "open-pic". And while chrp,open-pic is common in
existing trees, only one platform currently checks for it.
I'd make in "open-pic" in the binding, and have the kernel accept
either one.
> +** Optional properties:
> +
> + - no-reset : The presence of this property indicates that the MPIC
> + should not be reset during runtime initialization.
> + - protected-sources : Specifies a list of interrupt sources that are
> not
> + available for use and whose corresponding vectors
> + should not be initialized. A typical use case for
> + this property is in AMP systems where multiple
> + independent operating systems need to share
> the MPIC
> + without clobbering each other.
> +
Can we define no-reset as meaning that all vectors are in a sane state
(either directed at other cores, or masked)?
If we do that, maybe we can get rid of protected-sources.
-Scott
^ permalink raw reply
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