* [PATCH 0/2]: powerpc: MPIC binding and 'no-reset' implementation
From: Meador Inge @ 2011-01-18 0:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: minge, devicetree-discuss, Blanchard, Hollis
This patch set provides a binding for the MPIC and implements support
for a new property, specified by that binding, called 'no-reset'.
Signed-off-by: Meador Inge <meador_inge@mentor.com>
CC: Hollis Blanchard <hollis_blanchard@mentor.com>
^ permalink raw reply
* [PATCH 1/2] powerpc: document the MPIC device tree binding
From: Meador Inge @ 2011-01-18 0:52 UTC (permalink / raw)
To: linuxppc-dev; +Cc: minge, devicetree-discuss, Blanchard, Hollis
This binding documents several properties that have been in use for
quite some time, and adds one new property 'no-reset', which controls
whether the MPIC should be reset during runtime initialization.
Signed-off-by: Meador Inge <meador_inge@mentor.com>
CC: Hollis Blanchard <hollis_blanchard@mentor.com>
---
Documentation/powerpc/dts-bindings/mpic.txt | 78
+++++++++++++++++++++++++++
1 files changed, 78 insertions(+), 0 deletions(-)
create mode 100644 Documentation/powerpc/dts-bindings/mpic.txt
diff --git a/Documentation/powerpc/dts-bindings/mpic.txt
b/Documentation/powerpc/dts-bindings/mpic.txt
new file mode 100644
index 0000000..3a67919
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/mpic.txt
@@ -0,0 +1,78 @@
+* MPIC Binding
+
+This binding specifies what properties and child nodes must be available on
+the device tree representation of the "MPIC" interrupt controller. This
+binding is based on the binding defined for Open PIC in [1] and is a
superset
+of that binding.
+
+** Required properties:
+
+ NOTE: Many of these descriptions were paraphrased from [1] to aid
+ readability.
+
+ - name : Specifies the name of the MPIC.
+ - device_type : Specifies the device type of this MPIC. The value
of this
+ property shall be "open-pic".
+ - reg : Specifies the base physical address(s) and size(s) of this
MPIC's
+ addressable register space.
+ - compatible : Specifies the compatibility list for the MPIC. The
property
+ value shall include "chrp,open-pic".
+ - interrupt-controller : The presence of this property identifies
the node
+ as a MPIC. No property value should be
defined.
+ - #address-cells : Specifies the number of cells needed to encode an
+ address. The value of this property shall always
be 0
+ so that 'interrupt-map' nodes do not have to
specify a
+ parent unit address.
+ - #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source.
+
+** Optional properties:
+
+ - no-reset : The presence of this property indicates that the MPIC
+ should not be reset during runtime initialization.
+ - protected-sources : Specifies a list of interrupt sources that are
not
+ available for use and whose corresponding vectors
+ should not be initialized. A typical use case for
+ this property is in AMP systems where multiple
+ independent operating systems need to share
the MPIC
+ without clobbering each other.
+
+** Example:
+
+ mpic: pic@40000 {
+ // This is an interrupt controller node.
+ interrupt-controller;
+
+ // No address cells so that 'interrupt-map' nodes which reference
+ // this MPIC node do not need a parent address specifier.
+ #address-cells = <0>;
+
+ // Two cell to encode interrupt sources.
+ #interrupt-cells = <2>;
+
+ // Offset address of 0x40000 and size of 0x40000.
+ reg = <0x40000 0x40000>;
+
+ // Compatible with Open PIC.
+ compatible = "chrp,open-pic";
+
+ // An Open PIC device.
+ device_type = "open-pic";
+
+ // The sources 0xb1 and 0xb2 are off limits for use and should
not be
+ // initialized by the OS.
+ protected-sources = <0xb1 0xb2>;
+
+ // The MPIC should not be reset.
+ no-reset;
+ };
+
+* References
+
+[1] PowerPC Microprocessor Common Hardware Reference Platform (CHRP)
Binding,
+ Version 1.8, 1998. Published by the Open Firmware Working Group.
+ (http://playground.sun.com/1275/bindings/chrp/chrp1_8a.ps)
+[2] Open Firmware Recommended Practice: Interrupt Mapping, Version 0.9.
1996.
+ Published by the Open Firmware Working Group.
+ (http://playground.sun.com/1275/practice/imap/imap0_9d.pdf)
+
-- 1.6.3.3
^ permalink raw reply related
* [PATCH 2/2] powerpc: make MPIC honor the 'no-reset' device tree property
From: Meador Inge @ 2011-01-18 0:54 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Meador Inge, devicetree-discuss, Blanchard, Hollis
This property, defined in the MPIC binding, tells the kernel not to use
the reset bit in the global configuration register.
Signed-off-by: Meador Inge <meador_inge@mentor.com>
CC: Hollis Blanchard <hollis_blanchard@mentor.com>
---
arch/powerpc/sysdev/mpic.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 30c44e6..44aa2c3 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1157,7 +1157,9 @@ struct mpic * __init mpic_alloc(struct device_node
*node,
mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE),
0x1000);
/* Reset */
- if (flags & MPIC_WANTS_RESET) {
+ if ((flags & MPIC_WANTS_RESET) &&
+ !of_find_property(node, "no-reset", NULL)) {
+ printk(KERN_DEBUG "mpic: Resetting\n");
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
| MPIC_GREG_GCONF_RESET);
-- 1.6.3.3
^ permalink raw reply related
* Re: [PATCH] define binding for fsl mpic interrupt controllers
From: Meador Inge @ 2011-01-18 1:21 UTC (permalink / raw)
To: Stuart Yoder
Cc: Meador Inge, Blanchard, Hollis, devicetree-discuss, linuxppc-dev
In-Reply-To: <AANLkTim5i89k4OpUBWw0UgMoa5vwN5eSZ1MCs34S0VXB@mail.gmail.com>
Hi Stuart,
> From: Stuart Yoder<stuart.yoder@freescale.com>
>
> define the binding for compatible = "fsl,mpic", including
> the definition of 4-cell interrupt specifiers. The
> 3rd and 4th cells are needed to define additional
> types of interrupt source outside the "normal"
> external and internal interrupts in FSL SoCs. Define
> error interrupt, IPIs, and PIC timer sources.
Recently I posted an RFC concerning a binding for the MPIC [1]. I also
submitted a patch based on that feedback today (patch subject '[PATCH
1/2] powerpc: document the MPIC device tree binding'). You provide much
more information concerning the interrupt sources and how interrupt
specifiers are encoded. I had a few more properties listed: 'name',
'device_type', 'protected-sources', and 'no-reset'. The 'no-reset'
property is a proposed addition to the binding, the others are already
in use.
Perhaps we should merge the proposals?
[1] http://lists.ozlabs.org/pipermail/linuxppc-dev/2010-December/087644.html
> Signed-off-by: Stuart Yoder<stuart.yoder@freescale.com>
> ---
> Documentation/powerpc/dts-bindings/fsl/mpic.txt | 158 +++++++++++++++++------
> 1 files changed, 116 insertions(+), 42 deletions(-)
>
> diff --git a/Documentation/powerpc/dts-bindings/fsl/mpic.txt
> b/Documentation/powerpc/dts-bindings/fsl/mpic.txt
> index 71e39cf..e1fe67c 100644
> --- a/Documentation/powerpc/dts-bindings/fsl/mpic.txt
> +++ b/Documentation/powerpc/dts-bindings/fsl/mpic.txt
> @@ -1,42 +1,116 @@
> -* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
> -
> -The OpenPIC specification does not specify which interrupt source has to
> -become which interrupt number. This is up to the software implementation
> -of the interrupt controller. The only requirement is that every
> -interrupt source has to have an unique interrupt number / vector number.
> -To accomplish this the current implementation assigns the number zero to
> -the first source, the number one to the second source and so on until
> -all interrupt sources have their unique number.
> -Usually the assigned vector number equals the interrupt number mentioned
> -in the documentation for a given core / CPU. This is however not true
> -for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
> -between internal and external interrupt sources and starts counting at
> -zero for both of them.
> -
> -So what to write for external interrupt source X or internal interrupt
> -source Y into the device tree? Here is an example:
> -
> -The memory map for the interrupt controller in the MPC8544[0] shows,
> -that the first interrupt source starts at 0x5_0000 (PIC Register Address
> -Map-Interrupt Source Configuration Registers). This source becomes the
> -number zero therefore:
> - External interrupt 0 = interrupt number 0
> - External interrupt 1 = interrupt number 1
> - External interrupt 2 = interrupt number 2
> - ...
> -Every interrupt number allocates 0x20 bytes register space. So to get
> -its number it is sufficient to shift the lower 16bits to right by five.
> -So for the external interrupt 10 we have:
> - 0x0140>> 5 = 10
> -
> -After the external sources, the internal sources follow. The in core I2C
> -controller on the MPC8544 for instance has the internal source number
> -27. Oo obtain its interrupt number we take the lower 16bits of its memory
> -address (0x5_0560) and shift it right:
> - 0x0560>> 5 = 43
> -
> -Therefore the I2C device node for the MPC8544 CPU has to have the
> -interrupt number 43 specified in the device tree.
> -
> -[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family
> Reference Manual
> - MPC8544ERM Rev. 1 10/2007
> +=====================================================================
> +Freescale MPIC Interrupt Controller Node
> +Copyright (C) 2010,2011 Freescale Semiconductor Inc.
> +=====================================================================
> +
> +The Freescale MPIC interrupt controller is found on all PowerQUICC
> +and QorIQ processors and is compatible with the Open PIC. The
> +notable difference from Open PIC binding is the addition of 2
> +additional cells in the interrupt specifier defining interrupt type
> +information.
> +
> +PROPERTIES
> +
> + - compatible
> + Usage: required
> + Value type:<string>
> + Definition: Shall include "fsl,mpic". Freescale MPIC
> + controlers compatible with this binding have Block
> + Revision Registers BRR1 and BRR2 at offset 0x0 and
> + 0x10 in the MPIC.
> +
> + - reg
> + Usage: required
> + Value type:<prop-encoded-array>
> + Definition: A standard property. Specifies the physical
> + offset and length of the device's registers within the
> + CCSR address space.
> +
> + - interrupt-controller
> + Usage: required
> + Value type:<empty>
> + Definition: Specifies that this node is an interrupt
> + controller
> +
> + - #interrupt-cells
> + Usage: required
> + Value type:<u32>
> + Definition: Shall be 2 or 4. A value of 2 means that interrupt
> + specifiers do not contain the interrupt-type or type-specific
> + information cells.
> +
> + - #address-cells
> + Usage: required
> + Value type:<u32>
> + Definition: Shall be 0.
> +
> +INTERRUPT SPECIFIER DEFINITION
> +
> + Interrupt specifiers consists of 4 cells encoded as
> + follows:
> +
> +<1st-cell> interrupt-number
> +
> + Identifies the interrupt source. The MPIC
> + contains a block of registers referred
> + to as the "Interrupt Source Configuration
> + Registers". Each source has 32-bytes of
> + registers (vector/priority and destination)
> + in this region. So interrupt 0 is at
> + offset 0x0, interrupt 1 is at offset 0x20,
> + and so on.
> +
> +<2nd-cell> level-sense information, encoded as follows:
> + 0 = low-to-high edge triggered
> + 1 = active low level-sensitive
> + 2 = active high level-sensitive
> + 3 = high-to-low edge triggered
> +
> +<3rd-cell> interrupt-type
> +
> + The following types are supported:
> +
> + 0 = external or normal SoC device interrupt
> +
> + The interrupt-number field contains
> + the SoC device interrupt number. The
> + type-specific cell is undefined.
> +
> + 1 = error interrupt
> +
> + The interrupt-number field contains
> + the SoC device interrupt number for
> + the error interrupt. The type-specific
> + cell identifies the specific error
> + interrupt number.
> +
> + 2 = MPIC inter-processor interrupt (IPI)
> +
> + The interrupt-number field identifies
> + the MPIC IPI number. The type-specific
> + cell is undefined.
> +
> + 3 = MPIC timer interrupt
> +
> + The interrupt-number field identifies
> + the MPIC timer number. The type-specific
> + cell is undefined.
> +
> +<4th-cell> type-specific information
> +
> + The type-specific cell is encoded as follows:
> +
> + - For interrupt-type 1 (error interrupt),
> + the type-specific field contains the
> + bit number of the error interrupt in the
> + Error Interrupt Summary Register.
> +
> +EXAMPLE
> +
> + mpic: pic@40000 {
> + compatible = "fsl,mpic";
> + interrupt-controller;
> + #interrupt-cells =<4>;
> + #address-cells =<0>;
> + reg =<0x40000 0x40000>;
> + };
> --
> 1.7.2.2
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
>
>
--
Meador Inge | meador_inge AT mentor.com
Mentor Embedded | http://www.mentor.com/embedded-software
^ permalink raw reply
* 2.6.37-git17 virtual IO boot failure
From: Anton Blanchard @ 2011-01-18 1:31 UTC (permalink / raw)
To: nacc; +Cc: linuxppc-dev
Hi,
I was testing 2.6.37-git17 on a POWER7 with virtual IO and hit this:
Trying to unpack rootfs image as initramfs...
Freeing initrd memory: 7446k freed
vio 30000000: Warning: IOMMU dma not supported: mask
0xffffffffffffffff, table unavailable
vio 4000: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
table unavailable
vio 4001: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
table unavailable
vio 4002: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
table unavailable
vio 4004: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
table unavailable
audit: initializing netlink socket (disabled)
Haven't had a chance to look closer yet.
Anton
^ permalink raw reply
* RE: [PATCH] ATA: Add FSL sata v2 controller support
From: Zang Roy-R61911 @ 2011-01-18 3:01 UTC (permalink / raw)
To: Sergei Shtylyov, Xu Lei-B33228
Cc: jgarzik@pobox.com, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, linux-ide@vger.kernel.org
In-Reply-To: <4D342C6E.6000608@ru.mvista.com>
> -----Original Message-----
> From: Sergei Shtylyov [mailto:sshtylyov@mvista.com]
> Sent: Monday, January 17, 2011 19:48 PM
> To: Xu Lei-B33228
> Cc: linuxppc-dev@lists.ozlabs.org; Gala Kumar-B11780; jgarzik@pobox.com;
> linux-ide@vger.kernel.org; Zang Roy-R61911
> Subject: Re: [PATCH] ATA: Add FSL sata v2 controller support
>=20
> Hello.
>=20
> On 17-01-2011 10:10, Xulei wrote:
>=20
> > In FSL sata v2 block, the snoop bit of PRDT Word3 description
> > information is at bit28 instead of bit22.
>=20
> > This patch adds FSL sata v2 probe and resolve this difference.
>=20
> > Signed-off-by: Xulei <B33228@freescale.com>
>=20
[snip]
> > diff --git a/arch/powerpc/boot/dts/p1022ds.dts
> b/arch/powerpc/boot/dts/p1022ds.dts
> > index 2bbecbb..9ad41dd 100644
> > --- a/arch/powerpc/boot/dts/p1022ds.dts
> > +++ b/arch/powerpc/boot/dts/p1022ds.dts
> > @@ -475,14 +475,14 @@
> > };
> >
> > sata@18000 {
> > - compatible =3D "fsl,mpc8536-sata", "fsl,pq-sata";
> > + compatible =3D "fsl,p1022-sata", "fsl,pq-sata-v2";
> > reg =3D<0x18000 0x1000>;
> > cell-index =3D<1>;
> > interrupts =3D<74 0x2>;
> > };
> >
> > sata@19000 {
> > - compatible =3D "fsl,mpc8536-sata", "fsl,pq-sata";
> > + compatible =3D "fsl,p1022-sata", "fsl,pq-sata-v2";
> > reg =3D<0x19000 0x1000>;
> > cell-index =3D<2>;
> > interrupts =3D<41 0x2>;
>=20
> Please put this into the separate patch and push thru the PPC tree.
I agree to put to them to separate patches, but should we=20
pull in the separate patches to one candidate tree to make
the function work?
Thanks.
Roy
^ permalink raw reply
* Re: Gianfar TCP checksumming broken in 2.6.35+
From: Alex Dubov @ 2011-01-18 7:56 UTC (permalink / raw)
To: mlcreech; +Cc: linuxppc-dev, davem
It appears that I'm hitting an exactly the same problem with my MPC8548=0Ar=
ev2.0 (errata number eTSEC 49).=0A=0AConsidering that it's close to 3 month=
now since this most unfortunate=0Abug was reported, was there any resoluti=
on/patch that can fix it for good?=0A=0A=0A=0A
^ permalink raw reply
* [PATCH] Fix masking of interrupts for 52xx GPT IRQ.
From: Henk Stegeman @ 2011-01-15 1:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Henk Stegeman
In-Reply-To: <fa686aa41003181102i2a702c61h8ecfe05568c2a42e@mail.gmail.com>
When using the GPT as interrupt controller interupts were missing.
It turned out the IrqEn bit of the GPT is not a mask bit, but it also
disables interrupt generation. This modification masks interrupt one
level down the cascade. Note that masking one level down the cascade
is only valid here because the GPT as interrupt ontroller only serves
one IRQ.
Signed-off-by: Henk Stegeman <henk.stegeman@gmail.com>
---
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 25 ++++++++++++++++++++++---
1 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index 6f8ebe1..9ae2045 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -91,7 +91,7 @@ struct mpc52xx_gpt_priv {
struct irq_host *irqhost;
u32 ipb_freq;
u8 wdt_mode;
-
+ int cascade_virq;
#if defined(CONFIG_GPIOLIB)
struct of_gpio_chip of_gc;
#endif
@@ -136,18 +136,35 @@ DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
static void mpc52xx_gpt_irq_unmask(unsigned int virq)
{
struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
+
+ enable_irq(gpt->cascade_virq);
+
+}
+
+static void mpc52xx_gpt_irq_mask(unsigned int virq)
+{
+ struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
+
+ disable_irq(gpt->cascade_virq);
+}
+
+static void mpc52xx_gpt_irq_enable(unsigned int virq)
+{
+ struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
unsigned long flags;
+ dev_dbg(gpt->dev, "%s %d\n", __func__, virq);
spin_lock_irqsave(&gpt->lock, flags);
setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
spin_unlock_irqrestore(&gpt->lock, flags);
}
-static void mpc52xx_gpt_irq_mask(unsigned int virq)
+static void mpc52xx_gpt_irq_disable(unsigned int virq)
{
struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
unsigned long flags;
+ dev_dbg(gpt->dev, "%s %d\n", __func__, virq);
spin_lock_irqsave(&gpt->lock, flags);
clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
spin_unlock_irqrestore(&gpt->lock, flags);
@@ -184,6 +201,8 @@ static struct irq_chip mpc52xx_gpt_irq_chip = {
.name = "MPC52xx GPT",
.unmask = mpc52xx_gpt_irq_unmask,
.mask = mpc52xx_gpt_irq_mask,
+ .enable = mpc52xx_gpt_irq_enable,
+ .disable = mpc52xx_gpt_irq_disable,
.ack = mpc52xx_gpt_irq_ack,
.set_type = mpc52xx_gpt_irq_set_type,
};
@@ -268,7 +287,7 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
spin_unlock_irqrestore(&gpt->lock, flags);
-
+ gpt->cascade_virq = cascade_virq;
dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
}
--
1.5.4.3
^ permalink raw reply related
* [PATCH] powerpc: perf: Fix frequency calculation for overflowing counters (FSL version)
From: Anton Blanchard @ 2011-01-18 10:44 UTC (permalink / raw)
To: Peter Zijlstra
Cc: linux-kernel, Paul Mackerras, Arnaldo Carvalho de Melo,
Scott Wood, Ingo Molnar, linuxppc-dev
In-Reply-To: <1295285881.30950.218.camel@laptop>
> > Does perf_event_fsl_emb.c need this as well (it has almost the same
> > record_and_restart code)?
>
> I would think so.
Good point:
When fixing the frequency calculations for perf on powerpc I forgot
to fix the FSL version.
If we dont set event->hw.last_period the frequency to period calculations
in perf go haywire and we continually throttle/unthrottle the PMU.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
This is only compile tested.
Index: powerpc.git/arch/powerpc/kernel/perf_event_fsl_emb.c
===================================================================
--- powerpc.git.orig/arch/powerpc/kernel/perf_event_fsl_emb.c 2011-01-18 21:23:57.761644115 +1100
+++ powerpc.git/arch/powerpc/kernel/perf_event_fsl_emb.c 2011-01-18 21:25:28.994477247 +1100
@@ -596,6 +596,7 @@ static void record_and_restart(struct pe
if (left <= 0)
left = period;
record = 1;
+ event->hw.last_period = event->hw.sample_period;
}
if (left < 0x80000000LL)
val = 0x80000000LL - left;
^ permalink raw reply
* Re: [PATCH] ATA: Add FSL sata v2 controller support
From: Sergei Shtylyov @ 2011-01-18 11:27 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Xu Lei-B33228, Sergei Shtylyov, jgarzik@pobox.com,
linux-ide@vger.kernel.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <2239AC579C7D3646A720227A37E0268109001B@039-SN1MPN1-004.039d.mgd.msft.net>
Hello.
On 18-01-2011 6:01, Zang Roy-R61911 wrote:
>>> In FSL sata v2 block, the snoop bit of PRDT Word3 description
>>> information is at bit28 instead of bit22.
>>> This patch adds FSL sata v2 probe and resolve this difference.
>>> Signed-off-by: Xulei<B33228@freescale.com>
> [snip]
>>> diff --git a/arch/powerpc/boot/dts/p1022ds.dts
>> b/arch/powerpc/boot/dts/p1022ds.dts
>>> index 2bbecbb..9ad41dd 100644
>>> --- a/arch/powerpc/boot/dts/p1022ds.dts
>>> +++ b/arch/powerpc/boot/dts/p1022ds.dts
>>> @@ -475,14 +475,14 @@
>>> };
>>>
>>> sata@18000 {
>>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>>> reg =<0x18000 0x1000>;
>>> cell-index =<1>;
>>> interrupts =<74 0x2>;
>>> };
>>>
>>> sata@19000 {
>>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>>> reg =<0x19000 0x1000>;
>>> cell-index =<2>;
>>> interrupts =<41 0x2>;
>> Please put this into the separate patch and push thru the PPC tree.
> I agree to put to them to separate patches, but should we
> pull in the separate patches to one candidate tree to make
> the function work?
I don't understand. What is "candidate tree"?
> Thanks.
> Roy
WBR, Sergei
^ permalink raw reply
* RE: [PATCH] ATA: Add FSL sata v2 controller support
From: Zang Roy-R61911 @ 2011-01-18 11:43 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-ide@vger.kernel.org, Xu Lei-B33228, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org, jgarzik@pobox.com
In-Reply-To: <4D357918.4040001@ru.mvista.com>
> -----Original Message-----
> From: Sergei Shtylyov [mailto:sshtylyov@mvista.com]
> Sent: Tuesday, January 18, 2011 19:27 PM
> To: Zang Roy-R61911
> Cc: Sergei Shtylyov; Xu Lei-B33228; linuxppc-dev@lists.ozlabs.org; Gala K=
umar-
> B11780; jgarzik@pobox.com; linux-ide@vger.kernel.org
> Subject: Re: [PATCH] ATA: Add FSL sata v2 controller support
>=20
> Hello.
>=20
> On 18-01-2011 6:01, Zang Roy-R61911 wrote:
>=20
> >>> In FSL sata v2 block, the snoop bit of PRDT Word3 description
> >>> information is at bit28 instead of bit22.
>=20
> >>> This patch adds FSL sata v2 probe and resolve this difference.
>=20
> >>> Signed-off-by: Xulei<B33228@freescale.com>
>=20
> > [snip]
>=20
> >>> diff --git a/arch/powerpc/boot/dts/p1022ds.dts
> >> b/arch/powerpc/boot/dts/p1022ds.dts
> >>> index 2bbecbb..9ad41dd 100644
> >>> --- a/arch/powerpc/boot/dts/p1022ds.dts
> >>> +++ b/arch/powerpc/boot/dts/p1022ds.dts
> >>> @@ -475,14 +475,14 @@
> >>> };
> >>>
> >>> sata@18000 {
> >>> - compatible =3D "fsl,mpc8536-sata", "fsl,pq-sata";
> >>> + compatible =3D "fsl,p1022-sata", "fsl,pq-sata-v2";
> >>> reg =3D<0x18000 0x1000>;
> >>> cell-index =3D<1>;
> >>> interrupts =3D<74 0x2>;
> >>> };
> >>>
> >>> sata@19000 {
> >>> - compatible =3D "fsl,mpc8536-sata", "fsl,pq-sata";
> >>> + compatible =3D "fsl,p1022-sata", "fsl,pq-sata-v2";
> >>> reg =3D<0x19000 0x1000>;
> >>> cell-index =3D<2>;
> >>> interrupts =3D<41 0x2>;
>=20
> >> Please put this into the separate patch and push thru the PPC tre=
e.
>=20
> > I agree to put to them to separate patches, but should we
> > pull in the separate patches to one candidate tree to make
> > the function work?
>=20
> I don't understand. What is "candidate tree"?
Powerpc or ide git repository for upstream to mainline.
It is odd that patches for one function in different trees.
Thanks.
Roy
^ permalink raw reply
* Re: [PATCH] ATA: Add FSL sata v2 controller support
From: Sergei Shtylyov @ 2011-01-18 12:33 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Xu Lei-B33228, Sergei Shtylyov, jgarzik@pobox.com,
linux-ide@vger.kernel.org, Gala Kumar-B11780,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <2239AC579C7D3646A720227A37E02681090699@039-SN1MPN1-004.039d.mgd.msft.net>
Hello.
On 18-01-2011 14:43, Zang Roy-R61911 wrote:
>> On 18-01-2011 6:01, Zang Roy-R61911 wrote:
>>
>>>>> In FSL sata v2 block, the snoop bit of PRDT Word3 description
>>>>> information is at bit28 instead of bit22.
>>>>> This patch adds FSL sata v2 probe and resolve this difference.
>>>>> Signed-off-by: Xulei<B33228@freescale.com>
>>> [snip]
>>>>> diff --git a/arch/powerpc/boot/dts/p1022ds.dts
>>>> b/arch/powerpc/boot/dts/p1022ds.dts
>>>>> index 2bbecbb..9ad41dd 100644
>>>>> --- a/arch/powerpc/boot/dts/p1022ds.dts
>>>>> +++ b/arch/powerpc/boot/dts/p1022ds.dts
>>>>> @@ -475,14 +475,14 @@
>>>>> };
>>>>>
>>>>> sata@18000 {
>>>>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>>>>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>>>>> reg =<0x18000 0x1000>;
>>>>> cell-index =<1>;
>>>>> interrupts =<74 0x2>;
>>>>> };
>>>>>
>>>>> sata@19000 {
>>>>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>>>>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>>>>> reg =<0x19000 0x1000>;
>>>>> cell-index =<2>;
>>>>> interrupts =<41 0x2>;
>>>> Please put this into the separate patch and push thru the PPC tree.
>>> I agree to put to them to separate patches, but should we
>>> pull in the separate patches to one candidate tree to make
>>> the function work?
>> I don't understand. What is "candidate tree"?
> Powerpc or ide git repository for upstream to mainline.
s/ide/libata/
> It is odd that patches for one function in different trees.
The libata tree doesn't need to be concerned with PPC board specific
device trees. Although it's up to the maintainer... just cross post the patch,
and let the corresponding maintainers fogure it out.
> Thanks.
> Roy
WBR, Sergei
^ permalink raw reply
* Problem with Busybox shell
From: MohanReddy koppula @ 2011-01-18 12:54 UTC (permalink / raw)
To: Linuxppc-dev
Hi All,
I am working on an MPC885 based custom board. I am able to boot up the
linux (linux-2.6.33.7). I could see busybox shell (ash) prompt. But it
is not accepting any inputs, I am not able to enter any command, it
just hangs there. I am using ttyCPM0 terminal.
I suspected if there was any problem in CPM driver interrupts
generation and put some printk's in the interrupt handler and could
see interrupts are raised and data is read, but shell is not taking
the input.
I wrote an init.c and opened the ttyCPM0 and tried to read from it,
but couldn't. I am able to write to ttyCPM0 and see it on the host
minicom.
Please some one help me.
thanks in advance for your help.
-Mohan
^ permalink raw reply
* RE: [PATCH] define binding for fsl mpic interrupt controllers
From: Yoder Stuart-B08248 @ 2011-01-18 19:47 UTC (permalink / raw)
To: Meador Inge
Cc: Blanchard, Hollis, devicetree-discuss@lists.ozlabs.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <4D34EB06.9040908@mentor.com>
> -----Original Message-----
> From: Meador Inge [mailto:meador_inge@mentor.com]
> Sent: Monday, January 17, 2011 7:21 PM
> To: Yoder Stuart-B08248
> Cc: linuxppc-dev@lists.ozlabs.org; devicetree-discuss@lists.ozlabs.org;
> Blanchard, Hollis; Meador Inge
> Subject: Re: [PATCH] define binding for fsl mpic interrupt controllers
>=20
> Hi Stuart,
>=20
> > From: Stuart Yoder<stuart.yoder@freescale.com>
> >
> > define the binding for compatible =3D "fsl,mpic", including the
> > definition of 4-cell interrupt specifiers. The 3rd and 4th cells are
> > needed to define additional types of interrupt source outside the
> > "normal"
> > external and internal interrupts in FSL SoCs. Define error interrupt,
> > IPIs, and PIC timer sources.
>=20
> Recently I posted an RFC concerning a binding for the MPIC [1]. I also
> submitted a patch based on that feedback today (patch subject '[PATCH 1/2=
]
> powerpc: document the MPIC device tree binding'). You provide much more
> information concerning the interrupt sources and how interrupt specifiers
> are encoded. I had a few more properties listed: 'name', 'device_type',
> 'protected-sources', and 'no-reset'. The 'no-reset'
> property is a proposed addition to the binding, the others are already in
> use.
>=20
I'm not sure a complete merge into one binding makes sense. The thing that
motivated creating this new binding with 4 cells was a thread from
last year. See:
http://lists.ozlabs.org/pipermail/devicetree-discuss/2010-January/001489.ht=
ml
Since Freescale had the need to represent additional information
in interrupt specifiers (error ints, timers, ipis), the suggestion
at the end was to add additional cells in a FSL-specific binding.
So this really is a Freescale specific thing and does belong in the
Freescale binding directory.
That being said, if there is consensus on the AMP related properties,
I should probably incorporate those as well-- protected-sources
and no-reset.
I'll separately comment on your mpic binding patch.
Stuart=20
^ permalink raw reply
* RE: [PATCH 1/2] powerpc: document the MPIC device tree binding
From: Yoder Stuart-B08248 @ 2011-01-18 20:21 UTC (permalink / raw)
To: Meador Inge
Cc: Blanchard, Hollis, devicetree-discuss@lists.ozlabs.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <AANLkTi=QX4BfLvPfQDMOgmh90TtX4MQqio6AOZR8JKas@mail.gmail.com>
> From: Meador Inge <meador_inge@mentor.com>
> Date: Mon, Jan 17, 2011 at 6:52 PM
> Subject: [PATCH 1/2] powerpc: document the MPIC device tree binding
> To: linuxppc-dev@lists.ozlabs.org
> Cc: minge <meador_inge@mentor.com>,
> devicetree-discuss@lists.ozlabs.org, "Blanchard, Hollis"
> <Hollis_Blanchard@mentor.com>
>=20
>=20
> This binding documents several properties that have been in use for quite
> some time, and adds one new property 'no-reset', which controls whether t=
he
> MPIC should be reset during runtime initialization.
>=20
> Signed-off-by: Meador Inge <meador_inge@mentor.com>
> CC: Hollis Blanchard <hollis_blanchard@mentor.com>
> ---
> =A0Documentation/powerpc/dts-bindings/mpic.txt | =A0 78
This is really the binding for an open-pic interrupt controller
and I think the name should reflect that-- open-pic.txt.
> +++++++++++++++++++++++++++
> =A01 files changed, 78 insertions(+), 0 deletions(-)
> =A0create mode 100644 Documentation/powerpc/dts-bindings/mpic.txt
>=20
> diff --git a/Documentation/powerpc/dts-bindings/mpic.txt
> b/Documentation/powerpc/dts-bindings/mpic.txt
> new file mode 100644
> index 0000000..3a67919
> --- /dev/null
> +++ b/Documentation/powerpc/dts-bindings/mpic.txt
> @@ -0,0 +1,78 @@
> +* MPIC Binding
> +
> +This binding specifies what properties and child nodes must be
> +available on the device tree representation of the "MPIC" interrupt
> +controller. =A0This binding is based on the binding defined for Open PIC
> +in [1] and is a superset of that binding.
I think it would be better to base this on the ePAPR binding which
was based on the original chrp binding. Properties like "name"
and "device_type" are deprecated not being used in flat device trees.
<http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf>
The proposed new properties really should go back into the ePAPR.=20
> +
> +** Required properties:
> +
> + =A0 NOTE: Many of these descriptions were paraphrased from [1] to aid
> + =A0 =A0 =A0 =A0 readability.
> +
> + =A0 - name : Specifies the name of the MPIC.
Drop this. No DTS files use it.
> + =A0 - device_type : Specifies the device type of this MPIC. =A0The valu=
e
> + of this
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 property shall be "open-pic".
device_type is deprecated, since this is not real open-firmware. In
practice the kernel is matching on device_type, but we want to move
away from that to match on "compatible", just hasn't been implemented
yet.
> + =A0 - reg : Specifies the base physical address(s) and size(s) of this
> + MPIC's
> + =A0 =A0 =A0 =A0 =A0 addressable register space.
> + =A0 - compatible : Specifies the compatibility list for the MPIC. =A0Th=
e
> + property
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0value shall include "chrp,open-pic".
In the ePAPR we modified this to just "open-pic", because this has
nothing to do with chrp anymore. I think just "open-pic" is
what we want.
> + =A0 - interrupt-controller : The presence of this property identifies
> + the node
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0as a MPIC. =A0No=
property value should be
> defined.
> + =A0 - #address-cells : Specifies the number of cells needed to encode a=
n
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0address. =A0The value of thi=
s property shall always
> + be 0
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0so that 'interrupt-map' node=
s do not have to
> + specify a
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0parent unit address.
> + =A0 - #interrupt-cells : Specifies the number of cells needed to encode
> + an
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt source.
Should be 2, correct?
> +** Optional properties:
> +
> + =A0 - no-reset : The presence of this property indicates that the MPIC
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0should not be reset during runtime initi=
alization.
> + =A0 - protected-sources : Specifies a list of interrupt sources that ar=
e
> + not
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 available for use and w=
hose corresponding
> + vectors
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 should not be initializ=
ed. =A0A typical use case
> + for
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 this property is in AMP=
systems where multiple
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 independent operating s=
ystems need to share
> + the MPIC
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 without clobbering each=
other.
I do think you need to include the definition of interrupt
specifiers here. Feel free to cut/paste text from my
Freescale mpic binding.
Stuart
^ permalink raw reply
* Re: [PATCH 1/2] powerpc: document the MPIC device tree binding
From: Scott Wood @ 2011-01-18 20:31 UTC (permalink / raw)
To: Meador Inge; +Cc: Blanchard, Hollis, devicetree-discuss, linuxppc-dev
In-Reply-To: <4D34E448.8000902@mentor.com>
On Mon, 17 Jan 2011 18:52:24 -0600
Meador Inge <meador_inge@mentor.com> wrote:
> +** Required properties:
> +
> + NOTE: Many of these descriptions were paraphrased from [1] to aid
> + readability.
> +
> + - name : Specifies the name of the MPIC.
"name" isn't really a property with flat trees. The appropriate
node name, according to the Generic Names recommendation and ePAPR, is
interrupt-controller.
> + - device_type : Specifies the device type of this MPIC. The value
> of this
> + property shall be "open-pic".
Can we drop device_type, and fix the kernel to look for compatible
instead?
> + - compatible : Specifies the compatibility list for the MPIC. The
> property
> + value shall include "chrp,open-pic".
ePAPR wants just "open-pic". And while chrp,open-pic is common in
existing trees, only one platform currently checks for it.
I'd make in "open-pic" in the binding, and have the kernel accept
either one.
> +** Optional properties:
> +
> + - no-reset : The presence of this property indicates that the MPIC
> + should not be reset during runtime initialization.
> + - protected-sources : Specifies a list of interrupt sources that are
> not
> + available for use and whose corresponding vectors
> + should not be initialized. A typical use case for
> + this property is in AMP systems where multiple
> + independent operating systems need to share
> the MPIC
> + without clobbering each other.
> +
Can we define no-reset as meaning that all vectors are in a sane state
(either directed at other cores, or masked)?
If we do that, maybe we can get rid of protected-sources.
-Scott
^ permalink raw reply
* Re: Problem with Busybox shell
From: Scott Wood @ 2011-01-18 20:59 UTC (permalink / raw)
To: MohanReddy koppula; +Cc: Linuxppc-dev
In-Reply-To: <AANLkTinSfn+TQvzNWc++qP=4B2tbcHo-2iGv6E8tsq+b@mail.gmail.com>
On Tue, 18 Jan 2011 07:54:42 -0500
MohanReddy koppula <mohanreddykv@gmail.com> wrote:
> Hi All,
>
> I am working on an MPC885 based custom board. I am able to boot up the
> linux (linux-2.6.33.7). I could see busybox shell (ash) prompt. But it
> is not accepting any inputs, I am not able to enter any command, it
> just hangs there. I am using ttyCPM0 terminal.
>
> I suspected if there was any problem in CPM driver interrupts
> generation and put some printk's in the interrupt handler and could
> see interrupts are raised and data is read, but shell is not taking
> the input.
>
> I wrote an init.c and opened the ttyCPM0 and tried to read from it,
> but couldn't. I am able to write to ttyCPM0 and see it on the host
> minicom.
>
> Please some one help me.
Check your pin and clock setup -- perhaps tx is set up correctly but rx
isn't.
-Scott
^ permalink raw reply
* [patch 2/2] spufs: use simple_write_to_buffer()
From: akpm @ 2011-01-18 21:09 UTC (permalink / raw)
To: benh; +Cc: arnd, akinobu.mita, linuxppc-dev, paulus, jk, akpm
From: Akinobu Mita <akinobu.mita@gmail.com>
Simplify several write fileoperations for spufs by using
simple_write_to_buffer().
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Jeremy Kerr <jk@ozlabs.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
arch/powerpc/platforms/cell/spufs/file.c | 27 +++++----------------
1 file changed, 7 insertions(+), 20 deletions(-)
diff -puN arch/powerpc/platforms/cell/spufs/file.c~spufs-use-simple_write_to_buffer arch/powerpc/platforms/cell/spufs/file.c
--- a/arch/powerpc/platforms/cell/spufs/file.c~spufs-use-simple_write_to_buffer
+++ a/arch/powerpc/platforms/cell/spufs/file.c
@@ -219,24 +219,17 @@ spufs_mem_write(struct file *file, const
loff_t pos = *ppos;
int ret;
- if (pos < 0)
- return -EINVAL;
if (pos > LS_SIZE)
return -EFBIG;
- if (size > LS_SIZE - pos)
- size = LS_SIZE - pos;
ret = spu_acquire(ctx);
if (ret)
return ret;
local_store = ctx->ops->get_ls(ctx);
- ret = copy_from_user(local_store + pos, buffer, size);
+ size = simple_write_to_buffer(local_store, LS_SIZE, ppos, buffer, size);
spu_release(ctx);
- if (ret)
- return -EFAULT;
- *ppos = pos + size;
return size;
}
@@ -574,18 +567,15 @@ spufs_regs_write(struct file *file, cons
if (*pos >= sizeof(lscsa->gprs))
return -EFBIG;
- size = min_t(ssize_t, sizeof(lscsa->gprs) - *pos, size);
- *pos += size;
-
ret = spu_acquire_saved(ctx);
if (ret)
return ret;
- ret = copy_from_user((char *)lscsa->gprs + *pos - size,
- buffer, size) ? -EFAULT : size;
+ size = simple_write_to_buffer(lscsa->gprs, sizeof(lscsa->gprs), pos,
+ buffer, size);
spu_release_saved(ctx);
- return ret;
+ return size;
}
static const struct file_operations spufs_regs_fops = {
@@ -630,18 +620,15 @@ spufs_fpcr_write(struct file *file, cons
if (*pos >= sizeof(lscsa->fpcr))
return -EFBIG;
- size = min_t(ssize_t, sizeof(lscsa->fpcr) - *pos, size);
-
ret = spu_acquire_saved(ctx);
if (ret)
return ret;
- *pos += size;
- ret = copy_from_user((char *)&lscsa->fpcr + *pos - size,
- buffer, size) ? -EFAULT : size;
+ size = simple_write_to_buffer(&lscsa->fpcr, sizeof(lscsa->fpcr), pos,
+ buffer, size);
spu_release_saved(ctx);
- return ret;
+ return size;
}
static const struct file_operations spufs_fpcr_fops = {
_
^ permalink raw reply
* [patch 1/2] macintosh: wrong test in fan_{read,write}_reg()
From: akpm @ 2011-01-18 21:09 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev, akpm, roel.kluin
From: roel kluin <roel.kluin@gmail.com>
Fix error test in fan_{read,write}_reg()
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
---
drivers/macintosh/therm_pm72.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff -puN drivers/macintosh/therm_pm72.c~macintosh-wrong-test-in-fan_readwrite_reg drivers/macintosh/therm_pm72.c
--- a/drivers/macintosh/therm_pm72.c~macintosh-wrong-test-in-fan_readwrite_reg
+++ a/drivers/macintosh/therm_pm72.c
@@ -443,7 +443,7 @@ static int fan_read_reg(int reg, unsigne
tries = 0;
for (;;) {
nr = i2c_master_recv(fcu, buf, nb);
- if (nr > 0 || (nr < 0 && nr != ENODEV) || tries >= 100)
+ if (nr > 0 || (nr < 0 && nr != -ENODEV) || tries >= 100)
break;
msleep(10);
++tries;
@@ -464,7 +464,7 @@ static int fan_write_reg(int reg, const
tries = 0;
for (;;) {
nw = i2c_master_send(fcu, buf, nb);
- if (nw > 0 || (nw < 0 && nw != EIO) || tries >= 100)
+ if (nw > 0 || (nw < 0 && nw != -EIO) || tries >= 100)
break;
msleep(10);
++tries;
_
^ permalink raw reply
* Re: [patch 1/2] macintosh: wrong test in fan_{read,write}_reg()
From: Benjamin Herrenschmidt @ 2011-01-18 21:22 UTC (permalink / raw)
To: akpm; +Cc: linuxppc-dev, roel.kluin
In-Reply-To: <201101182109.p0IL992W005451@imap1.linux-foundation.org>
On Tue, 2011-01-18 at 13:09 -0800, akpm@linux-foundation.org wrote:
> From: roel kluin <roel.kluin@gmail.com>
>
> Fix error test in fan_{read,write}_reg()
Thanks, I'll pick that up.
Cheers,
Ben.
> Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
> ---
>
> drivers/macintosh/therm_pm72.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff -puN drivers/macintosh/therm_pm72.c~macintosh-wrong-test-in-fan_readwrite_reg drivers/macintosh/therm_pm72.c
> --- a/drivers/macintosh/therm_pm72.c~macintosh-wrong-test-in-fan_readwrite_reg
> +++ a/drivers/macintosh/therm_pm72.c
> @@ -443,7 +443,7 @@ static int fan_read_reg(int reg, unsigne
> tries = 0;
> for (;;) {
> nr = i2c_master_recv(fcu, buf, nb);
> - if (nr > 0 || (nr < 0 && nr != ENODEV) || tries >= 100)
> + if (nr > 0 || (nr < 0 && nr != -ENODEV) || tries >= 100)
> break;
> msleep(10);
> ++tries;
> @@ -464,7 +464,7 @@ static int fan_write_reg(int reg, const
> tries = 0;
> for (;;) {
> nw = i2c_master_send(fcu, buf, nb);
> - if (nw > 0 || (nw < 0 && nw != EIO) || tries >= 100)
> + if (nw > 0 || (nw < 0 && nw != -EIO) || tries >= 100)
> break;
> msleep(10);
> ++tries;
> _
^ permalink raw reply
* Re: [patch 2/2] spufs: use simple_write_to_buffer()
From: Benjamin Herrenschmidt @ 2011-01-18 21:22 UTC (permalink / raw)
To: akpm; +Cc: linuxppc-dev, paulus, akinobu.mita, arnd, jk
In-Reply-To: <201101182109.p0IL9A3h005454@imap1.linux-foundation.org>
On Tue, 2011-01-18 at 13:09 -0800, akpm@linux-foundation.org wrote:
> From: Akinobu Mita <akinobu.mita@gmail.com>
>
> Simplify several write fileoperations for spufs by using
> simple_write_to_buffer().
I'll pick that one up too.
Cheers,
Ben.
> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Jeremy Kerr <jk@ozlabs.org>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
> ---
>
> arch/powerpc/platforms/cell/spufs/file.c | 27 +++++----------------
> 1 file changed, 7 insertions(+), 20 deletions(-)
>
> diff -puN arch/powerpc/platforms/cell/spufs/file.c~spufs-use-simple_write_to_buffer arch/powerpc/platforms/cell/spufs/file.c
> --- a/arch/powerpc/platforms/cell/spufs/file.c~spufs-use-simple_write_to_buffer
> +++ a/arch/powerpc/platforms/cell/spufs/file.c
> @@ -219,24 +219,17 @@ spufs_mem_write(struct file *file, const
> loff_t pos = *ppos;
> int ret;
>
> - if (pos < 0)
> - return -EINVAL;
> if (pos > LS_SIZE)
> return -EFBIG;
> - if (size > LS_SIZE - pos)
> - size = LS_SIZE - pos;
>
> ret = spu_acquire(ctx);
> if (ret)
> return ret;
>
> local_store = ctx->ops->get_ls(ctx);
> - ret = copy_from_user(local_store + pos, buffer, size);
> + size = simple_write_to_buffer(local_store, LS_SIZE, ppos, buffer, size);
> spu_release(ctx);
>
> - if (ret)
> - return -EFAULT;
> - *ppos = pos + size;
> return size;
> }
>
> @@ -574,18 +567,15 @@ spufs_regs_write(struct file *file, cons
> if (*pos >= sizeof(lscsa->gprs))
> return -EFBIG;
>
> - size = min_t(ssize_t, sizeof(lscsa->gprs) - *pos, size);
> - *pos += size;
> -
> ret = spu_acquire_saved(ctx);
> if (ret)
> return ret;
>
> - ret = copy_from_user((char *)lscsa->gprs + *pos - size,
> - buffer, size) ? -EFAULT : size;
> + size = simple_write_to_buffer(lscsa->gprs, sizeof(lscsa->gprs), pos,
> + buffer, size);
>
> spu_release_saved(ctx);
> - return ret;
> + return size;
> }
>
> static const struct file_operations spufs_regs_fops = {
> @@ -630,18 +620,15 @@ spufs_fpcr_write(struct file *file, cons
> if (*pos >= sizeof(lscsa->fpcr))
> return -EFBIG;
>
> - size = min_t(ssize_t, sizeof(lscsa->fpcr) - *pos, size);
> -
> ret = spu_acquire_saved(ctx);
> if (ret)
> return ret;
>
> - *pos += size;
> - ret = copy_from_user((char *)&lscsa->fpcr + *pos - size,
> - buffer, size) ? -EFAULT : size;
> + size = simple_write_to_buffer(&lscsa->fpcr, sizeof(lscsa->fpcr), pos,
> + buffer, size);
>
> spu_release_saved(ctx);
> - return ret;
> + return size;
> }
>
> static const struct file_operations spufs_fpcr_fops = {
> _
^ permalink raw reply
* Re: 2.6.37-git17 virtual IO boot failure
From: Nishanth Aravamudan @ 2011-01-18 22:47 UTC (permalink / raw)
To: Anton Blanchard; +Cc: sonnyrao, miltonm, linuxppc-dev
In-Reply-To: <20110118123152.50f75a72@kryten>
On 18.01.2011 [12:31:52 +1100], Anton Blanchard wrote:
> Hi,
>
> I was testing 2.6.37-git17 on a POWER7 with virtual IO and hit this:
>
> Trying to unpack rootfs image as initramfs...
> Freeing initrd memory: 7446k freed
> vio 30000000: Warning: IOMMU dma not supported: mask
> 0xffffffffffffffff, table unavailable
> vio 4000: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
> table unavailable
> vio 4001: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
> table unavailable
> vio 4002: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
> table unavailable
> vio 4004: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
> table unavailable
> audit: initializing netlink socket (disabled)
>
> Haven't had a chance to look closer yet.
After debugging a bit, this would appear to be due to the second hunk of
b3c73856ae47d43d0d181f9de1c1c6c0820c4515.
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index b265405..1b695fd 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -1257,6 +1257,10 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
viodev->dev.parent = &vio_bus_device.dev;
viodev->dev.bus = &vio_bus_type;
viodev->dev.release = vio_dev_release;
+ /* needed to ensure proper operation of coherent allocations
+ * later, in case driver doesn't set it explicitly */
+ dma_set_mask(&viodev->dev, DMA_BIT_MASK(64));
+ dma_set_coherent_mask(&viodev->dev, DMA_BIT_MASK(64));
/* register with generic device framework */
if (device_register(&viodev->dev)) {
Milton, Sonny, any thoughts?
Thanks,
Nish
--
Nishanth Aravamudan <nacc@us.ibm.com>
IBM Linux Technology Center
^ permalink raw reply related
* Re: 2.6.37-git17 virtual IO boot failure
From: Nishanth Aravamudan @ 2011-01-19 0:48 UTC (permalink / raw)
To: Anton Blanchard; +Cc: sonnyrao, miltonm, linuxppc-dev
In-Reply-To: <20110118224718.GA19039@us.ibm.com>
On 18.01.2011 [14:47:18 -0800], Nishanth Aravamudan wrote:
> On 18.01.2011 [12:31:52 +1100], Anton Blanchard wrote:
> > Hi,
> >
> > I was testing 2.6.37-git17 on a POWER7 with virtual IO and hit this:
> >
> > Trying to unpack rootfs image as initramfs...
> > Freeing initrd memory: 7446k freed
> > vio 30000000: Warning: IOMMU dma not supported: mask
> > 0xffffffffffffffff, table unavailable
> > vio 4000: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
> > table unavailable
> > vio 4001: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
> > table unavailable
> > vio 4002: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
> > table unavailable
> > vio 4004: Warning: IOMMU dma not supported: mask 0xffffffffffffffff,
> > table unavailable
> > audit: initializing netlink socket (disabled)
> >
> > Haven't had a chance to look closer yet.
>
> After debugging a bit, this would appear to be due to the second hunk of
> b3c73856ae47d43d0d181f9de1c1c6c0820c4515.
>
> diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
> index b265405..1b695fd 100644
> --- a/arch/powerpc/kernel/vio.c
> +++ b/arch/powerpc/kernel/vio.c
> @@ -1257,6 +1257,10 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
> viodev->dev.parent = &vio_bus_device.dev;
> viodev->dev.bus = &vio_bus_type;
> viodev->dev.release = vio_dev_release;
> + /* needed to ensure proper operation of coherent allocations
> + * later, in case driver doesn't set it explicitly */
> + dma_set_mask(&viodev->dev, DMA_BIT_MASK(64));
> + dma_set_coherent_mask(&viodev->dev, DMA_BIT_MASK(64));
>
> /* register with generic device framework */
> if (device_register(&viodev->dev)) {
>
> Milton, Sonny, any thoughts?
A bit more detail after trying a few more kernels on the box that
originally showed the error:
1) This doesn't actually prevent booting, afaict. I think it "just"
disables DMA, which is bad, but not a boot fail, technically.
2) Reverting the above commit definitely prevents those messages.
3) I'm seeing a separate issue with 2.6.37-git17 (that's not present in
2.6.37):
sd 0:4:2:0: [sda] Aborting command: 2A
sd 0:4:2:0: Abort timed out. Resetting bus.
At which point the box locks up :)
So testing fixes is a bit of a challenge right now.
Ben, if you're ok with waiting to see if Milton or Sonny have any ideas,
I'd like to hold off on asking for a revert. In the case they do, I'll
be able to test and send out any proposed fix rapidly.
Thanks,
Nish
--
Nishanth Aravamudan <nacc@us.ibm.com>
IBM Linux Technology Center
^ permalink raw reply
* Re: [PATCH #upstream-fixes] pata_mpc52xx: inherit from ata_bmdma_port_ops
From: Jeff Garzik @ 2011-01-19 1:00 UTC (permalink / raw)
To: Tejun Heo; +Cc: linux-ide, linuxppc-dev, Sergei Shtylyov, Roman Fietze
In-Reply-To: <20110109224820.GB26607@mtj.dyndns.org>
On 01/09/2011 05:48 PM, Tejun Heo wrote:
> pata_mpc52xx supports BMDMA but inherits ata_sff_port_ops which
> triggers BUG_ON() when a DMA command is issued. Fix it.
>
> Signed-off-by: Tejun Heo<tj@kernel.org>
> Reported-by: Roman Fietze<roman.fietze@telemotive.de>
> Cc: Sergei Shtylyov<sshtylyov@mvista.com>
> Cc: stable@kernel.org
> ---
> drivers/ata/pata_mpc52xx.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c
> index 8cc536e..d7d8026 100644
> --- a/drivers/ata/pata_mpc52xx.c
> +++ b/drivers/ata/pata_mpc52xx.c
> @@ -610,7 +610,7 @@ static struct scsi_host_template mpc52xx_ata_sht = {
> };
>
> static struct ata_port_operations mpc52xx_ata_port_ops = {
> - .inherits =&ata_sff_port_ops,
> + .inherits =&ata_bmdma_port_ops,
> .sff_dev_select = mpc52xx_ata_dev_select,
> .set_piomode = mpc52xx_ata_set_piomode,
applied
^ permalink raw reply
* Re: [PATCH] ATA: Add FSL sata v2 controller support
From: Jeff Garzik @ 2011-01-19 1:10 UTC (permalink / raw)
To: Sergei Shtylyov, kumar.gala, Roy Zang; +Cc: Xulei, linuxppc-dev, linux-ide
In-Reply-To: <4D342C6E.6000608@ru.mvista.com>
On 01/17/2011 06:47 AM, Sergei Shtylyov wrote:
> Hello.
>
> On 17-01-2011 10:10, Xulei wrote:
>
>> In FSL sata v2 block, the snoop bit of PRDT Word3 description
>> information is at bit28 instead of bit22.
>
>> This patch adds FSL sata v2 probe and resolve this difference.
>
>> Signed-off-by: Xulei <B33228@freescale.com>
>
> AFAIK, full name is required.
>
>> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> [...]
>
>> diff --git a/arch/powerpc/boot/dts/p1022ds.dts
>> b/arch/powerpc/boot/dts/p1022ds.dts
>> index 2bbecbb..9ad41dd 100644
>> --- a/arch/powerpc/boot/dts/p1022ds.dts
>> +++ b/arch/powerpc/boot/dts/p1022ds.dts
>> @@ -475,14 +475,14 @@
>> };
>>
>> sata@18000 {
>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>> reg =<0x18000 0x1000>;
>> cell-index =<1>;
>> interrupts =<74 0x2>;
>> };
>>
>> sata@19000 {
>> - compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
>> + compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
>> reg =<0x19000 0x1000>;
>> cell-index =<2>;
>> interrupts =<41 0x2>;
>
> Please put this into the separate patch and push thru the PPC tree.
I think it's OK to send 100% of this via the PPC tree. The sata_fsl.c
patch for data_snoop variability directly keys off a call to
platform-specific detail (of_device_is_compatible call).
Acked-by: Jeff Garzik <jgarzik@redhat.com>
^ permalink raw reply
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