* [PATCH] powerpc/ptrace: remove BUG_ON when full register set not available
From: Michael Wolf @ 2011-03-01 20:26 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, anton
In some cases during a threaded core dump not all
the threads will have a full register set. This
will cause problems when the sigkill is sent to
the thread. To solve this problem a poison value
(0xdeadbeef) will be placed in the buffer in place
of the actual register values. This will affect
gpr14 to gpr31.
Signed-off-by: Mike Wolf <mjw@linux.vnet.ibm.com>
----------
--- ptracev2.orig/include/linux/regset.h 2011-02-20 12:15:57.000000000 -0600
+++ ptracev2/include/linux/regset.h 2011-02-28 13:33:36.685302349 -0600
@@ -240,6 +240,34 @@ static inline int user_regset_copyout(un
}
return 0;
}
+/* want the count to be the registers 14-31 inclusive */
+#define POISON_REG_CNT (PT_R31-PT_R14+1)
+static inline int user_regset_copyout_poison(unsigned int *pos,
+ unsigned int *count,
+ void **kbuf, void __user **ubuf,
+ const int start_pos,
+ const int end_pos)
+{
+ long poison_data[POISON_REG_CNT] = { [0 ... POISON_REG_CNT-1] = 0xdeadbeefdeadbeefUL };
+
+ if (*count == 0)
+ return 0;
+ BUG_ON(*pos < start_pos);
+ if (end_pos < 0 || *pos < end_pos) {
+ unsigned int copy = (end_pos < 0 ? *count
+ : min(*count, end_pos - *pos));
+ if (*kbuf) {
+ memset(*kbuf, 0xdeadbeef, copy);
+ *kbuf += copy;
+ } else if (__copy_to_user(*ubuf,poison_data, copy))
+ return -EFAULT;
+ else
+ *ubuf += copy;
+ *pos += copy;
+ *count -= copy;
+ }
+ return 0;
+}
static inline int user_regset_copyin(unsigned int *pos, unsigned int *count,
const void **kbuf,
--- ptracev2.orig/arch/powerpc/kernel/ptrace.c 2011-02-20 12:15:57.000000000 -0600
+++ ptracev2/arch/powerpc/kernel/ptrace.c 2011-03-01 13:49:12.686354353 -0600
@@ -234,11 +234,29 @@ static int gpr_get(struct task_struct *t
if (target->thread.regs == NULL)
return -EIO;
- CHECK_FULL_REGS(target->thread.regs);
- ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
- target->thread.regs,
- 0, offsetof(struct pt_regs, msr));
+ if (!FULL_REGS(target->thread.regs)) {
+ /* Don't have the full register set. Copy out register r0-r13 */
+ ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+ target->thread.regs,
+ 0, sizeof(long)*PT_R14);
+
+ /* Dont want to change the actual register values so rather than read the */
+ /* actual register copy a poison value into the buffer instead */
+ if (!ret)
+ ret = user_regset_copyout_poison(&pos, &count, &kbuf, &ubuf,
+ sizeof(long)*PT_R14, offsetof(struct pt_regs, nip));
+
+ /* Copy out the rest of the registers as usual */
+ if (!ret)
+ ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+ target->thread.regs,
+ offsetof(struct pt_regs, nip), offsetof(struct pt_regs, msr));
+
+ } else
+ ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+ target->thread.regs,
+ 0, offsetof(struct pt_regs, msr));
if (!ret) {
unsigned long msr = get_user_msr(target);
ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
@@ -645,11 +663,29 @@ static int gpr32_get(struct task_struct
if (target->thread.regs == NULL)
return -EIO;
- CHECK_FULL_REGS(target->thread.regs);
-
pos /= sizeof(reg);
count /= sizeof(reg);
+ if(!FULL_REGS(target->thread.regs)) {
+ if (kbuf) {
+ /* Don't have the full register set. Copy out register r0-r13 */
+ for (; count > 0 && pos < PT_R14; --count)
+ *k++ = regs[pos++];
+
+ /* Dont want to change the actual register values so rather than read the */
+ /* actual register copy a poison value into the buffer instead */
+ for (; count > 0 && pos <= PT_R31; --count,pos++)
+ *k++ = 0xdeadbeef;
+
+ } else {
+ for (; count > 0 && pos < PT_R14; --count)
+ if (__put_user((compat_ulong_t) regs[pos++], u++))
+ return -EFAULT;
+ for (; count > 0 && pos <= PT_R31; --count,pos++)
+ if (__put_user((compat_ulong_t) 0xdeadbeef, u++))
+ return -EFAULT;
+ }
+ }
if (kbuf)
for (; count > 0 && pos < PT_MSR; --count)
*k++ = regs[pos++];
^ permalink raw reply
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Ira W. Snyder @ 2011-03-01 19:52 UTC (permalink / raw)
To: Felix Radensky, linuxppc-dev@ozlabs.org
In-Reply-To: <20110301165515.GA23403@ovro.caltech.edu>
On Tue, Mar 01, 2011 at 08:55:15AM -0800, Ira W. Snyder wrote:
[ big snip ]
>
> Thanks, this is exactly what I was going to ask for next. :)
>
> I really don't understand why the P2020 DMA controller isn't behaving
> nicely after my patches.
>
> Can you run a git bisect to figure out which patch in the series causes
> the problems. It should take three or four build + test cycles to narrow
> down which patch breaks the driver. When it is finished, send me the
> output of git bisect.
>
> Like this (assuming you have two branches: master and
> fsldma, where fsldma is master + my patches):
>
> # setup the bisect
> git bisect start
> git bisect bad fsldma
> git bisect good master
>
> # build and test the kernel using the same test as before:
> modprobe dmatest max_channels=1 threads_per_chan=1 iterations=4
>
> # if the test passes:
> git bisect good
>
> # if the test fails:
> git bisect bad
>
> # now build + test again, then mark that good or bad. Repeat until
> # finished.
>
>
> I really appreciate your help in testing this. You've been great at
> providing everything I've asked for.
>
I'd still like the bisect if you have a chance. I've re-reviewed the
patch series, and found the places that change register writes to the
controller.
The patch below changes the register operations back to the original
order. It doesn't make any sense why this would be required, but it is
worth a quick try.
I've added an "XXX" mark where you can comment out a single line if this
patch fails. It is highly unlikely to make any difference, but I'm
really having a hard time understanding what is wrong.
Ira
>From 9e479ce27f8c1819694d7082bb4a27772b4baf52 Mon Sep 17 00:00:00 2001
From: Ira W. Snyder <iws@ovro.caltech.edu>
Date: Tue, 1 Mar 2011 11:43:00 -0800
Subject: [PATCH] fsldma: try and fix 85xx DMA controller
This is just a random guess at what might be wrong. The datasheet
doesn't say that a completed transfer must be aborted before starting a
new transfer (nor does it make much sense). However, the old code did it
anyway.
NOT AT ALL Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
---
drivers/dma/fsldma.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index e4d9d17..d8eedbc 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -213,6 +213,7 @@ static void dma_halt(struct fsldma_chan *chan)
int i;
mode = DMA_IN(chan, &chan->regs->mr, 32);
+ dev_dbg(chan->dev, "%s: dma_halt mode=0x%.8x\n", chan->name, mode);
mode |= FSL_DMA_MR_CA;
DMA_OUT(chan, &chan->regs->mr, mode, 32);
@@ -921,10 +922,24 @@ static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
/*
+ * XXX: Guess at problems
+ *
+ * The 85xx requires that you run this routine before you try to start
+ * the next DMA for an as yet unknown reason. Maybe.
+ */
+ if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
+ dev_dbg(chan->dev, "%s: 85xx, running workaround\n", name);
+ dma_halt(chan);
+ }
+
+ /*
* Program the descriptor's address into the DMA controller,
* then start the DMA transaction
*/
set_cdar(chan, desc->async_tx.phys);
+
+
+ /* XXX: if that doesn't work, comment the "get_cdar()" line below */
get_cdar(chan);
dma_start(chan);
--
1.7.3.4
^ permalink raw reply related
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Ira W. Snyder @ 2011-03-01 16:55 UTC (permalink / raw)
To: Felix Radensky; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <4D6C89A7.8010803@embedded-sol.com>
On Tue, Mar 01, 2011 at 07:52:39AM +0200, Felix Radensky wrote:
> Hi Ira,
>
> On 03/01/2011 02:21 AM, Ira W. Snyder wrote:
> > On Mon, Feb 28, 2011 at 11:27:40PM +0200, Felix Radensky wrote:
> >> Hi Ira,
> >>
> >> On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
> >>> On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
> >>>> Hi Ira,
> >>>>
> >>>>> Thank you very much Felix. The dmesg output shows that the controller
> >>>>> never got an interrupt for the second transaction. The patch below has
> >>>>> extra debugging information that may help determine why this happens.
> >>>>> Please apply it and re-run the test.
> >>>>>
> >>>>> The last section of dmesg (after "Freeing unused kernel memory") is all
> >>>>> I need.
> >>>>>
> >>>> Attached relevant dmesg portion.
> >>>>
> >>> Ok, try this patch on top of the last one.
> >>>
> >>> It looks like you used the dmatest module in multi-channel mode last
> >>> time. One channel makes it easier to debug:
> >>>
> >>> modprobe dmatest max_channels=1 threads_per_chan=2 iterations=1
> >>>
> >>> Thanks for your help in debugging this. Hopefully this is the last
> >>> patch to test. :)
> >>>
> >>> Ira
> >>>
> >> Looks like this was not the last one. The test still fails, see below
> >>
> > From this log, it looks like the DMA controller is not generating an
> > interrupt after the second chain is started. The first chain is finished
> > before the second thread runs and starts its chain.
> >
> > The end-of-segments interrupt is completely missing. The part is not
> > behaving as the datasheet explains it should. Are you sure you applied
> > the patch and rebuilt the kernel? (Just checking to be sure. I'm very
> > appreciative of the amount of help you've given me debugging this!)
> >
> > Can you run this for me:
> >
> > modprobe dmatest max_channels=1 threads_per_chan=1 iterations=4
> >
> > Thanks again,
> > Ira
>
> Without your patches applied the output of the test above looks
> like this:
>
Thanks, this is exactly what I was going to ask for next. :)
I really don't understand why the P2020 DMA controller isn't behaving
nicely after my patches.
Can you run a git bisect to figure out which patch in the series causes
the problems. It should take three or four build + test cycles to narrow
down which patch breaks the driver. When it is finished, send me the
output of git bisect.
Like this (assuming you have two branches: master and
fsldma, where fsldma is master + my patches):
# setup the bisect
git bisect start
git bisect bad fsldma
git bisect good master
# build and test the kernel using the same test as before:
modprobe dmatest max_channels=1 threads_per_chan=1 iterations=4
# if the test passes:
git bisect good
# if the test fails:
git bisect bad
# now build + test again, then mark that good or bad. Repeat until
# finished.
I really appreciate your help in testing this. You've been great at
providing everything I've asked for.
Thanks,
Ira
^ permalink raw reply
* Zero-copy sockets
From: Guillaume Dargaud @ 2011-03-01 14:32 UTC (permalink / raw)
To: linuxppc-dev
Hello all,
I cannot find the option SO_SND_COPYAVOID in socket.h...
Is there another way to do zero-copy network transfers ?
I'm using the 2.6.35 xilinx patched-kernel.
Thanks
--
Guillaume Dargaud
http://www.gdargaud.net/Photo/
^ permalink raw reply
* [PATCH] powerpc: Add pgprot_writecombine
From: Anton Blanchard @ 2011-03-01 6:00 UTC (permalink / raw)
To: benh, linuxppc-dev
A number of drivers are using pgprot_writecombine() to enable write
combining on userspace mappings. Implement it on powerpc.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 89f1587..88b0bd9 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -170,6 +170,7 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre
#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
_PAGE_COHERENT | _PAGE_WRITETHRU))
+#define pgprot_writecombine pgprot_noncached_wc
struct file;
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
^ permalink raw reply related
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Felix Radensky @ 2011-03-01 5:52 UTC (permalink / raw)
To: Ira W. Snyder; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <20110301002156.GC31428@ovro.caltech.edu>
Hi Ira,
On 03/01/2011 02:21 AM, Ira W. Snyder wrote:
> On Mon, Feb 28, 2011 at 11:27:40PM +0200, Felix Radensky wrote:
>> Hi Ira,
>>
>> On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
>>> On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
>>>> Hi Ira,
>>>>
>>>>> Thank you very much Felix. The dmesg output shows that the controller
>>>>> never got an interrupt for the second transaction. The patch below has
>>>>> extra debugging information that may help determine why this happens.
>>>>> Please apply it and re-run the test.
>>>>>
>>>>> The last section of dmesg (after "Freeing unused kernel memory") is all
>>>>> I need.
>>>>>
>>>> Attached relevant dmesg portion.
>>>>
>>> Ok, try this patch on top of the last one.
>>>
>>> It looks like you used the dmatest module in multi-channel mode last
>>> time. One channel makes it easier to debug:
>>>
>>> modprobe dmatest max_channels=1 threads_per_chan=2 iterations=1
>>>
>>> Thanks for your help in debugging this. Hopefully this is the last
>>> patch to test. :)
>>>
>>> Ira
>>>
>> Looks like this was not the last one. The test still fails, see below
>>
> From this log, it looks like the DMA controller is not generating an
> interrupt after the second chain is started. The first chain is finished
> before the second thread runs and starts its chain.
>
> The end-of-segments interrupt is completely missing. The part is not
> behaving as the datasheet explains it should. Are you sure you applied
> the patch and rebuilt the kernel? (Just checking to be sure. I'm very
> appreciative of the amount of help you've given me debugging this!)
>
> Can you run this for me:
>
> modprobe dmatest max_channels=1 threads_per_chan=1 iterations=4
>
> Thanks again,
> Ira
Without your patches applied the output of the test above looks
like this:
__dma_request_channel: success (dma0chan0)
dmatest: Started 1 threads using dma0chan0
of:fsl-elo-dma ffe0c300.dma: irq: channel 0, stat = 0xa
of:fsl-elo-dma ffe0c300.dma: irq: End-of-segments INT
of:fsl-elo-dma ffe0c300.dma: irq: clndar 0x2f34d000, nlndar 0x100000000
of:fsl-elo-dma ffe0c300.dma: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: no pending LDs
of:fsl-elo-dma ffe0c300.dma: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan completed_cookie = 1
of:fsl-elo-dma ffe0c300.dma: LD ef34d000 callback
of:fsl-elo-dma ffe0c300.dma: chan completed_cookie = 1
dma0chan0-copy0: verifying source buffer...
dma0chan0-copy0: verifying dest buffer...
dma0chan0-copy0: #0: No errors with src_off=0xb90 dst_off=0x101c
len=0x2aea
of:fsl-elo-dma ffe0c300.dma: irq: channel 0, stat = 0xa
of:fsl-elo-dma ffe0c300.dma: irq: End-of-segments INT
of:fsl-elo-dma ffe0c300.dma: irq: clndar 0x2f34d000, nlndar 0x100000000
of:fsl-elo-dma ffe0c300.dma: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: no pending LDs
of:fsl-elo-dma ffe0c300.dma: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan completed_cookie = 2
of:fsl-elo-dma ffe0c300.dma: LD ef34d000 callback
of:fsl-elo-dma ffe0c300.dma: chan completed_cookie = 2
dma0chan0-copy0: verifying source buffer...
dma0chan0-copy0: verifying dest buffer...
dma0chan0-copy0: #1: No errors with src_off=0x74a dst_off=0x54d len=0x35f5
of:fsl-elo-dma ffe0c300.dma: irq: channel 0, stat = 0xa
of:fsl-elo-dma ffe0c300.dma: irq: End-of-segments INT
of:fsl-elo-dma ffe0c300.dma: irq: clndar 0x2f34d000, nlndar 0x100000000
of:fsl-elo-dma ffe0c300.dma: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: no pending LDs
of:fsl-elo-dma ffe0c300.dma: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan completed_cookie = 3
of:fsl-elo-dma ffe0c300.dma: LD ef34d000 callback
of:fsl-elo-dma ffe0c300.dma: chan completed_cookie = 3
dma0chan0-copy0: verifying source buffer...
dma0chan0-copy0: verifying dest buffer...
dma0chan0-copy0: #2: No errors with src_off=0x2ad dst_off=0x557 len=0x35e1
of:fsl-elo-dma ffe0c300.dma: irq: channel 0, stat = 0xa
of:fsl-elo-dma ffe0c300.dma: irq: End-of-segments INT
of:fsl-elo-dma ffe0c300.dma: irq: clndar 0x2f34d000, nlndar 0x100000000
of:fsl-elo-dma ffe0c300.dma: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: no pending LDs
of:fsl-elo-dma ffe0c300.dma: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan completed_cookie = 4
of:fsl-elo-dma ffe0c300.dma: LD ef34d000 callback
of:fsl-elo-dma ffe0c300.dma: chan completed_cookie = 4
dma0chan0-copy0: verifying source buffer...
dma0chan0-copy0: verifying dest buffer...
dma0chan0-copy0: #3: No errors with src_off=0x0 dst_off=0x0 len=0x4000
dma0chan0-copy0: terminating after 4 tests, 0 failures (status 0)
Felix.
^ permalink raw reply
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Felix Radensky @ 2011-03-01 5:46 UTC (permalink / raw)
To: Ira W. Snyder; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <20110301002156.GC31428@ovro.caltech.edu>
Hi Ira,
On 03/01/2011 02:21 AM, Ira W. Snyder wrote:
> On Mon, Feb 28, 2011 at 11:27:40PM +0200, Felix Radensky wrote:
>> Hi Ira,
>>
>> On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
>>> On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
>>>> Hi Ira,
>>>>
>>>>> Thank you very much Felix. The dmesg output shows that the controller
>>>>> never got an interrupt for the second transaction. The patch below has
>>>>> extra debugging information that may help determine why this happens.
>>>>> Please apply it and re-run the test.
>>>>>
>>>>> The last section of dmesg (after "Freeing unused kernel memory") is all
>>>>> I need.
>>>>>
>>>> Attached relevant dmesg portion.
>>>>
>>> Ok, try this patch on top of the last one.
>>>
>>> It looks like you used the dmatest module in multi-channel mode last
>>> time. One channel makes it easier to debug:
>>>
>>> modprobe dmatest max_channels=1 threads_per_chan=2 iterations=1
>>>
>>> Thanks for your help in debugging this. Hopefully this is the last
>>> patch to test. :)
>>>
>>> Ira
>>>
>> Looks like this was not the last one. The test still fails, see below
>>
> From this log, it looks like the DMA controller is not generating an
> interrupt after the second chain is started. The first chain is finished
> before the second thread runs and starts its chain.
>
> The end-of-segments interrupt is completely missing. The part is not
> behaving as the datasheet explains it should. Are you sure you applied
> the patch and rebuilt the kernel? (Just checking to be sure. I'm very
> appreciative of the amount of help you've given me debugging this!)
I've double checked and I'm sure I've applied your patch and rebuilt
the kernel.
> Can you run this for me:
>
> modprobe dmatest max_channels=1 threads_per_chan=1 iterations=4
>
> Thanks again,
> Ira
See below.
__dma_request_channel: success (dma0chan0)
dmatest: Started 1 threads using dma0chan0
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7000 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7060 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a70c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7120 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7180 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a71e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7240 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a72a0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7300 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7360 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a73c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7420 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7480 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a74e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: start=0
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: end=14
of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
of:fsl-elo-dma ffe0c300.dma: chan0: irq: stat = 0x8
of:fsl-elo-dma ffe0c300.dma: chan0: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: chan0: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan0: tasklet entry
of:fsl-elo-dma ffe0c300.dma: chan0: completed_cookie=14
of:fsl-elo-dma ffe0c300.dma: chan0: no pending LDs
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7000 callback
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7000 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7060 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a70c0 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7120 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7180 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a71e0 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7240 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a72a0 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7300 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7360 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a73c0 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7420 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7480 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a74e0 free
of:fsl-elo-dma ffe0c300.dma: chan0: tasklet exit
dma0chan0-copy0: verifying source buffer...
dma0chan0-copy0: verifying dest buffer...
dma0chan0-copy0: #0: No errors with src_off=0x43e dst_off=0x3a5 len=0x3605
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a74e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7480 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: start=14
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: end=16
of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
dma0chan0-copy0: #1: test timed out
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7420 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a73c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7360 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7300 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: start=16
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: end=20
of:fsl-elo-dma ffe0c300.dma: chan0: DMA controller still busy
dma0chan0-copy0: #2: test timed out
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a72a0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7240 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a71e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7180 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7120 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a70c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3a7060 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: start=20
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: end=27
of:fsl-elo-dma ffe0c300.dma: chan0: DMA controller still busy
dma0chan0-copy0: #3: test timed out
dma0chan0-copy0: terminating after 4 tests, 3 failures (status 0)
Felix.
^ permalink raw reply
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Ira W. Snyder @ 2011-03-01 0:21 UTC (permalink / raw)
To: Felix Radensky; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <4D6C134C.4070407@embedded-sol.com>
On Mon, Feb 28, 2011 at 11:27:40PM +0200, Felix Radensky wrote:
> Hi Ira,
>
> On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
> > On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
> >> Hi Ira,
> >>
> >>> Thank you very much Felix. The dmesg output shows that the controller
> >>> never got an interrupt for the second transaction. The patch below has
> >>> extra debugging information that may help determine why this happens.
> >>> Please apply it and re-run the test.
> >>>
> >>> The last section of dmesg (after "Freeing unused kernel memory") is all
> >>> I need.
> >>>
> >> Attached relevant dmesg portion.
> >>
> > Ok, try this patch on top of the last one.
> >
> > It looks like you used the dmatest module in multi-channel mode last
> > time. One channel makes it easier to debug:
> >
> > modprobe dmatest max_channels=1 threads_per_chan=2 iterations=1
> >
> > Thanks for your help in debugging this. Hopefully this is the last
> > patch to test. :)
> >
> > Ira
> >
>
> Looks like this was not the last one. The test still fails, see below
>
>From this log, it looks like the DMA controller is not generating an
interrupt after the second chain is started. The first chain is finished
before the second thread runs and starts its chain.
The end-of-segments interrupt is completely missing. The part is not
behaving as the datasheet explains it should. Are you sure you applied
the patch and rebuilt the kernel? (Just checking to be sure. I'm very
appreciative of the amount of help you've given me debugging this!)
Can you run this for me:
modprobe dmatest max_channels=1 threads_per_chan=1 iterations=4
Thanks again,
Ira
^ permalink raw reply
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Felix Radensky @ 2011-02-28 21:27 UTC (permalink / raw)
To: Ira W. Snyder; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <20110228211103.GB31428@ovro.caltech.edu>
Hi Ira,
On 02/28/2011 11:11 PM, Ira W. Snyder wrote:
> On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
>> Hi Ira,
>>
>>> Thank you very much Felix. The dmesg output shows that the controller
>>> never got an interrupt for the second transaction. The patch below has
>>> extra debugging information that may help determine why this happens.
>>> Please apply it and re-run the test.
>>>
>>> The last section of dmesg (after "Freeing unused kernel memory") is all
>>> I need.
>>>
>> Attached relevant dmesg portion.
>>
> Ok, try this patch on top of the last one.
>
> It looks like you used the dmatest module in multi-channel mode last
> time. One channel makes it easier to debug:
>
> modprobe dmatest max_channels=1 threads_per_chan=2 iterations=1
>
> Thanks for your help in debugging this. Hopefully this is the last
> patch to test. :)
>
> Ira
>
Looks like this was not the last one. The test still fails, see below
__dma_request_channel: success (dma0chan0)
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380000 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380060 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3800c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380120 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380180 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3801e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: start=0
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: end=6
of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
dmatest: Started 2 threads using dma0chan0
of:fsl-elo-dma ffe0c300.dma: chan0: irq: stat = 0x8
of:fsl-elo-dma ffe0c300.dma: chan0: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: chan0: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan0: tasklet entry
of:fsl-elo-dma ffe0c300.dma: chan0: completed_cookie=6
of:fsl-elo-dma ffe0c300.dma: chan0: no pending LDs
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380000 callback
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380000 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380060 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3800c0 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380120 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380180 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3801e0 free
of:fsl-elo-dma ffe0c300.dma: chan0: tasklet exit
dma0chan0-copy0: verifying source buffer...
dma0chan0-copy0: verifying dest buffer...
dma0chan0-copy0: #0: No errors with src_off=0xf92 dst_off=0xf46 len=0x14ad
dma0chan0-copy0: terminating after 1 tests, 0 failures (status 0)
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef3801e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380180 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef380120 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: start=6
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: end=9
of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
dma0chan0-copy1: #0: test timed out
dma0chan0-copy1: terminating after 1 tests, 1 failures (status 0)
Felix.
^ permalink raw reply
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Ira W. Snyder @ 2011-02-28 21:11 UTC (permalink / raw)
To: Felix Radensky; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <4D6C0275.6000807@embedded-sol.com>
On Mon, Feb 28, 2011 at 10:15:49PM +0200, Felix Radensky wrote:
> Hi Ira,
>
> > Thank you very much Felix. The dmesg output shows that the controller
> > never got an interrupt for the second transaction. The patch below has
> > extra debugging information that may help determine why this happens.
> > Please apply it and re-run the test.
> >
> > The last section of dmesg (after "Freeing unused kernel memory") is all
> > I need.
> >
>
> Attached relevant dmesg portion.
>
Ok, try this patch on top of the last one.
It looks like you used the dmatest module in multi-channel mode last
time. One channel makes it easier to debug:
modprobe dmatest max_channels=1 threads_per_chan=2 iterations=1
Thanks for your help in debugging this. Hopefully this is the last
patch to test. :)
Ira
>From 58bc23c3b68f8db0aa09434fdeb6aef641a5eadd Mon Sep 17 00:00:00 2001
From: Ira W. Snyder <iws@ovro.caltech.edu>
Date: Mon, 28 Feb 2011 12:55:55 -0800
Subject: [PATCH] fsldma: enable end-of-segments interrupt on last descriptor
This is a hack to manually set the end-of-segments interrupt on the last
descriptor in each chain. It appears that the P2020RDB controller
doesn't generate the end-of-links interrupt as explained in the
datasheet.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
---
drivers/dma/fsldma.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index b82b76e..e4d9d17 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -141,7 +141,7 @@ static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
u64 snoop_bits;
snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
- ? FSL_DMA_SNEN : 0;
+ ? FSL_DMA_SNEN : (u64)(0x8);
desc->hw.next_ln_addr = CPU_TO_DMA(chan,
DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
@@ -165,7 +165,6 @@ static void dma_init(struct fsldma_chan *chan)
* BWC - Bandwidth sharing among channels
*/
DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
- | FSL_DMA_MR_EOSIE | FSL_DMA_MR_EOLSIE
| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32);
break;
case FSL_DMA_IP_83XX:
--
1.7.3.4
^ permalink raw reply related
* [PATCH 2/5] RapidIO: Modify configuration to support PCI-SRIO controller
From: Alexandre Bounine @ 2011-02-28 20:51 UTC (permalink / raw)
To: akpm, linux-kernel, linuxppc-dev
Cc: Ralf Baechle, Alexandre Bounine, Ingo Molnar, Thomas Moll
In-Reply-To: <1298926265-5381-1-git-send-email-alexandre.bounine@idt.com>
1. Add an option to include RapidIO support if the PCI is available.
2. Add FSL_RIO configuration option to enable controller selection.
3. Add RapidIO support option into x86 and MIPS architectures.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
---
arch/mips/Kconfig | 10 ++++++++++
arch/powerpc/Kconfig | 10 +++++++++-
arch/powerpc/sysdev/Makefile | 2 +-
arch/x86/Kconfig | 10 ++++++++++
drivers/net/rionet.c | 4 ++--
drivers/rapidio/rio-sysfs.c | 1 +
6 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index f5ecc05..c451163 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2336,6 +2336,16 @@ source "drivers/pcmcia/Kconfig"
source "drivers/pci/hotplug/Kconfig"
+config RAPIDIO
+ bool "RapidIO support"
+ depends on PCI
+ default n
+ help
+ If you say Y here, the kernel will include drivers and
+ infrastructure code to support RapidIO interconnect devices.
+
+source "drivers/rapidio/Kconfig"
+
endmenu
menu "Executable file formats"
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7d69e9b..9a7628a 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -767,11 +767,19 @@ config HAS_RAPIDIO
config RAPIDIO
bool "RapidIO support"
- depends on HAS_RAPIDIO
+ depends on HAS_RAPIDIO || PCI
help
If you say Y here, the kernel will include drivers and
infrastructure code to support RapidIO interconnect devices.
+config FSL_RIO
+ bool "Freescale Embedded SRIO Controller support"
+ depends on RAPIDIO && HAS_RAPIDIO
+ default "n"
+ ---help---
+ Include support for RapidIO controller on Freescale embedded
+ processors (MPC8548, MPC8641, etc).
+
source "drivers/rapidio/Kconfig"
endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 9c29734..1e0c933 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
-obj-$(CONFIG_RAPIDIO) += fsl_rio.o
+obj-$(CONFIG_FSL_RIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d5ed94d..11c1dc5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2104,6 +2104,16 @@ source "drivers/pcmcia/Kconfig"
source "drivers/pci/hotplug/Kconfig"
+config RAPIDIO
+ bool "RapidIO support"
+ depends on PCI
+ default n
+ help
+ If you say Y here, the kernel will include drivers and
+ infrastructure code to support RapidIO interconnect devices.
+
+source "drivers/rapidio/Kconfig"
+
endmenu
diff --git a/drivers/net/rionet.c b/drivers/net/rionet.c
index 44150f2..678e577 100644
--- a/drivers/net/rionet.c
+++ b/drivers/net/rionet.c
@@ -382,7 +382,7 @@ static void rionet_remove(struct rio_dev *rdev)
struct rionet_peer *peer, *tmp;
free_pages((unsigned long)rionet_active, rdev->net->hport->sys_size ?
- __ilog2(sizeof(void *)) + 4 : 0);
+ __fls(sizeof(void *)) + 4 : 0);
unregister_netdev(ndev);
free_netdev(ndev);
@@ -450,7 +450,7 @@ static int rionet_setup_netdev(struct rio_mport *mport)
}
rionet_active = (struct rio_dev **)__get_free_pages(GFP_KERNEL,
- mport->sys_size ? __ilog2(sizeof(void *)) + 4 : 0);
+ mport->sys_size ? __fls(sizeof(void *)) + 4 : 0);
if (!rionet_active) {
rc = -ENOMEM;
goto out;
diff --git a/drivers/rapidio/rio-sysfs.c b/drivers/rapidio/rio-sysfs.c
index 76b4185..e3ebfec 100644
--- a/drivers/rapidio/rio-sysfs.c
+++ b/drivers/rapidio/rio-sysfs.c
@@ -14,6 +14,7 @@
#include <linux/rio.h>
#include <linux/rio_drv.h>
#include <linux/stat.h>
+#include <linux/capability.h>
#include "rio.h"
--
1.7.3.1
^ permalink raw reply related
* [PATCH 5/5] RapidIO: remove mport resource reservation from common RIO code
From: Alexandre Bounine @ 2011-02-28 20:51 UTC (permalink / raw)
To: akpm, linux-kernel, linuxppc-dev; +Cc: Alexandre Bounine, Thomas Moll
In-Reply-To: <1298926265-5381-1-git-send-email-alexandre.bounine@idt.com>
Removes resource reservation from the common sybsystem initialization code
and make it part of mport driver initialization. This resolves conflict
with resource reservation by device specific mport drivers.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
---
arch/powerpc/sysdev/fsl_rio.c | 9 +++++++++
drivers/rapidio/rio.c | 14 +-------------
2 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 7d35a12..f25ad15 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1432,6 +1432,14 @@ int fsl_rio_setup(struct platform_device *dev)
port->iores.flags = IORESOURCE_MEM;
port->iores.name = "rio_io_win";
+ if (request_resource(&iomem_resource, &port->iores) < 0) {
+ dev_err(&dev->dev, "RIO: Error requesting master port region"
+ " 0x%016llx-0x%016llx\n",
+ (u64)port->iores.start, (u64)port->iores.end);
+ rc = -ENOMEM;
+ goto err_res;
+ }
+
priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
@@ -1536,6 +1544,7 @@ int fsl_rio_setup(struct platform_device *dev)
return 0;
err:
iounmap(priv->regs_win);
+err_res:
kfree(priv);
err_priv:
kfree(port);
diff --git a/drivers/rapidio/rio.c b/drivers/rapidio/rio.c
index 9a7b216..c29719c 100644
--- a/drivers/rapidio/rio.c
+++ b/drivers/rapidio/rio.c
@@ -1137,20 +1137,9 @@ static int __devinit rio_init(void)
int __devinit rio_init_mports(void)
{
- int rc = 0;
struct rio_mport *port;
list_for_each_entry(port, &rio_mports, node) {
- if (!request_mem_region(port->iores.start,
- resource_size(&port->iores),
- port->name)) {
- printk(KERN_ERR
- "RIO: Error requesting master port region 0x%016llx-0x%016llx\n",
- (u64)port->iores.start, (u64)port->iores.end);
- rc = -ENOMEM;
- goto out;
- }
-
if (port->host_deviceid >= 0)
rio_enum_mport(port);
else
@@ -1159,8 +1148,7 @@ int __devinit rio_init_mports(void)
rio_init();
- out:
- return rc;
+ return 0;
}
device_initcall_sync(rio_init_mports);
--
1.7.3.1
^ permalink raw reply related
* [PATCH 4/5] RapidIO: Modify mport ID assignment
From: Alexandre Bounine @ 2011-02-28 20:51 UTC (permalink / raw)
To: akpm, linux-kernel, linuxppc-dev; +Cc: Alexandre Bounine, Thomas Moll
In-Reply-To: <1298926265-5381-1-git-send-email-alexandre.bounine@idt.com>
Changes mport ID and host destination ID assignment to implement unified
method common to all mport drivers. Makes "riohdid=" kernel command line
parameter common for all architectures with support for more that one
host destination ID assignment.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
---
arch/powerpc/sysdev/fsl_rio.c | 25 -------------------------
drivers/rapidio/rio.c | 26 ++++++++++++++++++++++++++
include/linux/rio.h | 1 +
3 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 6995907..7d35a12 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1288,28 +1288,6 @@ err_out:
return rc;
}
-static char *cmdline = NULL;
-
-static int fsl_rio_get_hdid(int index)
-{
- /* XXX Need to parse multiple entries in some format */
- if (!cmdline)
- return -1;
-
- return simple_strtol(cmdline, NULL, 0);
-}
-
-static int fsl_rio_get_cmdline(char *s)
-{
- if (!s)
- return 0;
-
- cmdline = s;
- return 1;
-}
-
-__setup("riohdid=", fsl_rio_get_cmdline);
-
static inline void fsl_rio_info(struct device *dev, u32 ccsr)
{
const char *str;
@@ -1439,7 +1417,6 @@ int fsl_rio_setup(struct platform_device *dev)
rc = -ENOMEM;
goto err_port;
}
- port->id = 0;
port->index = 0;
priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
@@ -1470,8 +1447,6 @@ int fsl_rio_setup(struct platform_device *dev)
priv->dev = &dev->dev;
port->ops = ops;
- port->host_deviceid = fsl_rio_get_hdid(port->id);
-
port->priv = priv;
port->phys_efptr = 0x100;
rio_register_mport(port);
diff --git a/drivers/rapidio/rio.c b/drivers/rapidio/rio.c
index f861b72..9a7b216 100644
--- a/drivers/rapidio/rio.c
+++ b/drivers/rapidio/rio.c
@@ -32,6 +32,7 @@
#include "rio.h"
static LIST_HEAD(rio_mports);
+static unsigned char next_portid;
/**
* rio_local_get_device_id - Get the base/extended device id for a port
@@ -1164,8 +1165,33 @@ int __devinit rio_init_mports(void)
device_initcall_sync(rio_init_mports);
+static int hdids[RIO_MAX_MPORTS + 1];
+
+static int rio_get_hdid(int index)
+{
+ if (!hdids[0] || hdids[0] <= index || index >= RIO_MAX_MPORTS)
+ return -1;
+
+ return hdids[index + 1];
+}
+
+static int rio_hdid_setup(char *str)
+{
+ (void)get_options(str, ARRAY_SIZE(hdids), hdids);
+ return 1;
+}
+
+__setup("riohdid=", rio_hdid_setup);
+
void rio_register_mport(struct rio_mport *port)
{
+ if (next_portid >= RIO_MAX_MPORTS) {
+ pr_err("RIO: reached specified max number of mports\n");
+ return;
+ }
+
+ port->id = next_portid++;
+ port->host_deviceid = rio_get_hdid(port->id);
list_add_tail(&port->node, &rio_mports);
}
diff --git a/include/linux/rio.h b/include/linux/rio.h
index b6bcb16..4e37a7c 100644
--- a/include/linux/rio.h
+++ b/include/linux/rio.h
@@ -24,6 +24,7 @@
#define RIO_NO_HOPCOUNT -1
#define RIO_INVALID_DESTID 0xffff
+#define RIO_MAX_MPORTS 8
#define RIO_MAX_MPORT_RESOURCES 16
#define RIO_MAX_DEV_RESOURCES 16
--
1.7.3.1
^ permalink raw reply related
* [PATCH 3/5] RapidIO: Modify subsystem and driver initialization sequence
From: Alexandre Bounine @ 2011-02-28 20:51 UTC (permalink / raw)
To: akpm, linux-kernel, linuxppc-dev; +Cc: Alexandre Bounine, Thomas Moll
In-Reply-To: <1298926265-5381-1-git-send-email-alexandre.bounine@idt.com>
Subsystem initialization sequence modified to support presence of multiple
RapidIO controllers in the system. The new sequence is compatible with
initialization of PCI devices.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
---
arch/powerpc/sysdev/fsl_rio.c | 10 +---------
drivers/net/rionet.c | 2 +-
drivers/rapidio/rio.c | 6 ++++--
include/linux/rio.h | 1 -
4 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 4c28226..6995907 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1575,18 +1575,10 @@ err_ops:
static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev,
const struct of_device_id *match)
{
- int rc;
printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
dev->dev.of_node->full_name);
- rc = fsl_rio_setup(dev);
- if (rc)
- goto out;
-
- /* Enumerate all registered ports */
- rc = rio_init_mports();
-out:
- return rc;
+ return fsl_rio_setup(dev);
};
static const struct of_device_id fsl_of_rio_rpn_ids[] = {
diff --git a/drivers/net/rionet.c b/drivers/net/rionet.c
index 678e577..26afbaa 100644
--- a/drivers/net/rionet.c
+++ b/drivers/net/rionet.c
@@ -571,5 +571,5 @@ static void __exit rionet_exit(void)
rio_unregister_driver(&rionet_driver);
}
-module_init(rionet_init);
+late_initcall(rionet_init);
module_exit(rionet_exit);
diff --git a/drivers/rapidio/rio.c b/drivers/rapidio/rio.c
index d520dba..f861b72 100644
--- a/drivers/rapidio/rio.c
+++ b/drivers/rapidio/rio.c
@@ -1134,8 +1134,6 @@ static int __devinit rio_init(void)
return 0;
}
-device_initcall(rio_init);
-
int __devinit rio_init_mports(void)
{
int rc = 0;
@@ -1158,10 +1156,14 @@ int __devinit rio_init_mports(void)
rio_disc_mport(port);
}
+ rio_init();
+
out:
return rc;
}
+device_initcall_sync(rio_init_mports);
+
void rio_register_mport(struct rio_mport *port)
{
list_add_tail(&port->node, &rio_mports);
diff --git a/include/linux/rio.h b/include/linux/rio.h
index efed116..b6bcb16 100644
--- a/include/linux/rio.h
+++ b/include/linux/rio.h
@@ -395,7 +395,6 @@ union rio_pw_msg {
};
/* Architecture and hardware-specific functions */
-extern int rio_init_mports(void);
extern void rio_register_mport(struct rio_mport *);
extern int rio_open_inb_mbox(struct rio_mport *, void *, int, int);
extern void rio_close_inb_mbox(struct rio_mport *, int);
--
1.7.3.1
^ permalink raw reply related
* [PATCH 1/5] RapidIO: Add architecture specific callbacks
From: Alexandre Bounine @ 2011-02-28 20:51 UTC (permalink / raw)
To: akpm, linux-kernel, linuxppc-dev; +Cc: Alexandre Bounine, Thomas Moll
In-Reply-To: <1298926265-5381-1-git-send-email-alexandre.bounine@idt.com>
Extend number of mport callback functions to eliminate direct linking of
architecture specific mport operations.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com>
---
arch/powerpc/sysdev/fsl_rio.c | 52 +++++++++++++++++++++-------------------
drivers/rapidio/rio.c | 38 ++++++++++++++++++++---------
include/linux/rio.h | 23 ++++++++++++++----
include/linux/rio_drv.h | 7 +++--
4 files changed, 75 insertions(+), 45 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 8c6cab0..4c28226 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -482,7 +482,7 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
}
/**
- * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
+ * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
* @mport: Master port with outbound message queue
* @rdev: Target of outbound message
* @mbox: Outbound mailbox
@@ -492,8 +492,8 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
* Adds the @buffer message to the MPC85xx outbound message queue. Returns
* %0 on success or %-EINVAL on failure.
*/
-int
-rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
+static int
+fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
void *buffer, size_t len)
{
struct rio_priv *priv = mport->priv;
@@ -502,9 +502,8 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
+ priv->msg_tx_ring.tx_slot;
int ret = 0;
- pr_debug
- ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
- rdev->destid, mbox, (int)buffer, len);
+ pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
+ "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
ret = -EINVAL;
@@ -554,8 +553,6 @@ rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
return ret;
}
-EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
-
/**
* fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
* @irq: Linux interrupt number
@@ -600,7 +597,7 @@ fsl_rio_tx_handler(int irq, void *dev_instance)
}
/**
- * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
+ * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
* @mport: Master port implementing the outbound message unit
* @dev_id: Device specific pointer to pass on event
* @mbox: Mailbox to open
@@ -610,7 +607,8 @@ fsl_rio_tx_handler(int irq, void *dev_instance)
* and enables the outbound message unit. Returns %0 on success and
* %-EINVAL or %-ENOMEM on failure.
*/
-int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
+static int
+fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
{
int i, j, rc = 0;
struct rio_priv *priv = mport->priv;
@@ -706,14 +704,14 @@ int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entr
}
/**
- * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
+ * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
* @mport: Master port implementing the outbound message unit
* @mbox: Mailbox to close
*
* Disables the outbound message unit, free all buffers, and
* frees the outbound message interrupt.
*/
-void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
+static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
{
struct rio_priv *priv = mport->priv;
/* Disable inbound message unit */
@@ -770,7 +768,7 @@ fsl_rio_rx_handler(int irq, void *dev_instance)
}
/**
- * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
+ * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
* @mport: Master port implementing the inbound message unit
* @dev_id: Device specific pointer to pass on event
* @mbox: Mailbox to open
@@ -780,7 +778,8 @@ fsl_rio_rx_handler(int irq, void *dev_instance)
* and enables the inbound message unit. Returns %0 on success
* and %-EINVAL or %-ENOMEM on failure.
*/
-int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
+static int
+fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
{
int i, rc = 0;
struct rio_priv *priv = mport->priv;
@@ -844,14 +843,14 @@ int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entri
}
/**
- * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
+ * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
* @mport: Master port implementing the inbound message unit
* @mbox: Mailbox to close
*
* Disables the inbound message unit, free all buffers, and
* frees the inbound message interrupt.
*/
-void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
+static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
{
struct rio_priv *priv = mport->priv;
/* Disable inbound message unit */
@@ -866,7 +865,7 @@ void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
}
/**
- * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
+ * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
* @mport: Master port implementing the inbound message unit
* @mbox: Inbound mailbox number
* @buf: Buffer to add to inbound queue
@@ -874,12 +873,12 @@ void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
* Adds the @buf buffer to the MPC85xx inbound message queue. Returns
* %0 on success or %-EINVAL on failure.
*/
-int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
+static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
{
int rc = 0;
struct rio_priv *priv = mport->priv;
- pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
+ pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
priv->msg_rx_ring.rx_slot);
if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
@@ -898,17 +897,15 @@ int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
return rc;
}
-EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
-
/**
- * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
+ * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
* @mport: Master port implementing the inbound message unit
* @mbox: Inbound mailbox number
*
* Gets the next available inbound message from the inbound message queue.
* A pointer to the message is returned on success or NULL on failure.
*/
-void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
+static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
{
struct rio_priv *priv = mport->priv;
u32 phys_buf, virt_buf;
@@ -945,8 +942,6 @@ void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
return buf;
}
-EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
-
/**
* fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
* @irq: Linux interrupt number
@@ -1431,6 +1426,13 @@ int fsl_rio_setup(struct platform_device *dev)
ops->cwrite = fsl_rio_config_write;
ops->dsend = fsl_rio_doorbell_send;
ops->pwenable = fsl_rio_pw_enable;
+ ops->open_outb_mbox = fsl_open_outb_mbox;
+ ops->open_inb_mbox = fsl_open_inb_mbox;
+ ops->close_outb_mbox = fsl_close_outb_mbox;
+ ops->close_inb_mbox = fsl_close_inb_mbox;
+ ops->add_outb_message = fsl_add_outb_message;
+ ops->add_inb_buffer = fsl_add_inb_buffer;
+ ops->get_inb_message = fsl_get_inb_message;
port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
if (!port) {
diff --git a/drivers/rapidio/rio.c b/drivers/rapidio/rio.c
index cc2a3b7..d520dba 100644
--- a/drivers/rapidio/rio.c
+++ b/drivers/rapidio/rio.c
@@ -68,9 +68,13 @@ int rio_request_inb_mbox(struct rio_mport *mport,
void (*minb) (struct rio_mport * mport, void *dev_id, int mbox,
int slot))
{
- int rc = 0;
+ int rc = -ENOSYS;
+ struct resource *res;
- struct resource *res = kmalloc(sizeof(struct resource), GFP_KERNEL);
+ if (mport->ops->open_inb_mbox == NULL)
+ goto out;
+
+ res = kmalloc(sizeof(struct resource), GFP_KERNEL);
if (res) {
rio_init_mbox_res(res, mbox, mbox);
@@ -88,7 +92,7 @@ int rio_request_inb_mbox(struct rio_mport *mport,
/* Hook the inbound message callback */
mport->inb_msg[mbox].mcback = minb;
- rc = rio_open_inb_mbox(mport, dev_id, mbox, entries);
+ rc = mport->ops->open_inb_mbox(mport, dev_id, mbox, entries);
} else
rc = -ENOMEM;
@@ -106,10 +110,13 @@ int rio_request_inb_mbox(struct rio_mport *mport,
*/
int rio_release_inb_mbox(struct rio_mport *mport, int mbox)
{
- rio_close_inb_mbox(mport, mbox);
+ if (mport->ops->close_inb_mbox) {
+ mport->ops->close_inb_mbox(mport, mbox);
- /* Release the mailbox resource */
- return release_resource(mport->inb_msg[mbox].res);
+ /* Release the mailbox resource */
+ return release_resource(mport->inb_msg[mbox].res);
+ } else
+ return -ENOSYS;
}
/**
@@ -129,9 +136,13 @@ int rio_request_outb_mbox(struct rio_mport *mport,
int entries,
void (*moutb) (struct rio_mport * mport, void *dev_id, int mbox, int slot))
{
- int rc = 0;
+ int rc = -ENOSYS;
+ struct resource *res;
- struct resource *res = kmalloc(sizeof(struct resource), GFP_KERNEL);
+ if (mport->ops->open_outb_mbox == NULL)
+ goto out;
+
+ res = kmalloc(sizeof(struct resource), GFP_KERNEL);
if (res) {
rio_init_mbox_res(res, mbox, mbox);
@@ -149,7 +160,7 @@ int rio_request_outb_mbox(struct rio_mport *mport,
/* Hook the inbound message callback */
mport->outb_msg[mbox].mcback = moutb;
- rc = rio_open_outb_mbox(mport, dev_id, mbox, entries);
+ rc = mport->ops->open_outb_mbox(mport, dev_id, mbox, entries);
} else
rc = -ENOMEM;
@@ -167,10 +178,13 @@ int rio_request_outb_mbox(struct rio_mport *mport,
*/
int rio_release_outb_mbox(struct rio_mport *mport, int mbox)
{
- rio_close_outb_mbox(mport, mbox);
+ if (mport->ops->close_outb_mbox) {
+ mport->ops->close_outb_mbox(mport, mbox);
- /* Release the mailbox resource */
- return release_resource(mport->outb_msg[mbox].res);
+ /* Release the mailbox resource */
+ return release_resource(mport->outb_msg[mbox].res);
+ } else
+ return -ENOSYS;
}
/**
diff --git a/include/linux/rio.h b/include/linux/rio.h
index ff681eb..efed116 100644
--- a/include/linux/rio.h
+++ b/include/linux/rio.h
@@ -241,7 +241,7 @@ struct rio_mport {
struct rio_msg inb_msg[RIO_MAX_MBOX];
struct rio_msg outb_msg[RIO_MAX_MBOX];
int host_deviceid; /* Host device ID */
- struct rio_ops *ops; /* maintenance transaction functions */
+ struct rio_ops *ops; /* low-level architecture-dependent routines */
unsigned char id; /* port ID, unique among all ports */
unsigned char index; /* port index, unique among all port
interfaces of the same type */
@@ -285,6 +285,13 @@ struct rio_net {
* @cwrite: Callback to perform network write of config space.
* @dsend: Callback to send a doorbell message.
* @pwenable: Callback to enable/disable port-write message handling.
+ * @open_outb_mbox: Callback to initialize outbound mailbox.
+ * @close_outb_mbox: Callback to shut down outbound mailbox.
+ * @open_inb_mbox: Callback to initialize inbound mailbox.
+ * @close_inb_mbox: Callback to shut down inbound mailbox.
+ * @add_outb_message: Callback to add a message to an outbound mailbox queue.
+ * @add_inb_buffer: Callback to add a buffer to an inbound mailbox queue.
+ * @get_inb_message: Callback to get a message from an inbound mailbox queue.
*/
struct rio_ops {
int (*lcread) (struct rio_mport *mport, int index, u32 offset, int len,
@@ -297,6 +304,16 @@ struct rio_ops {
u8 hopcount, u32 offset, int len, u32 data);
int (*dsend) (struct rio_mport *mport, int index, u16 destid, u16 data);
int (*pwenable) (struct rio_mport *mport, int enable);
+ int (*open_outb_mbox)(struct rio_mport *mport, void *dev_id,
+ int mbox, int entries);
+ void (*close_outb_mbox)(struct rio_mport *mport, int mbox);
+ int (*open_inb_mbox)(struct rio_mport *mport, void *dev_id,
+ int mbox, int entries);
+ void (*close_inb_mbox)(struct rio_mport *mport, int mbox);
+ int (*add_outb_message)(struct rio_mport *mport, struct rio_dev *rdev,
+ int mbox, void *buffer, size_t len);
+ int (*add_inb_buffer)(struct rio_mport *mport, int mbox, void *buf);
+ void *(*get_inb_message)(struct rio_mport *mport, int mbox);
};
#define RIO_RESOURCE_MEM 0x00000100
@@ -380,10 +397,6 @@ union rio_pw_msg {
/* Architecture and hardware-specific functions */
extern int rio_init_mports(void);
extern void rio_register_mport(struct rio_mport *);
-extern int rio_hw_add_outb_message(struct rio_mport *, struct rio_dev *, int,
- void *, size_t);
-extern int rio_hw_add_inb_buffer(struct rio_mport *, int, void *);
-extern void *rio_hw_get_inb_message(struct rio_mport *, int);
extern int rio_open_inb_mbox(struct rio_mport *, void *, int, int);
extern void rio_close_inb_mbox(struct rio_mport *, int);
extern int rio_open_outb_mbox(struct rio_mport *, void *, int, int);
diff --git a/include/linux/rio_drv.h b/include/linux/rio_drv.h
index e09e565..229b3ca 100644
--- a/include/linux/rio_drv.h
+++ b/include/linux/rio_drv.h
@@ -317,7 +317,8 @@ static inline int rio_add_outb_message(struct rio_mport *mport,
struct rio_dev *rdev, int mbox,
void *buffer, size_t len)
{
- return rio_hw_add_outb_message(mport, rdev, mbox, buffer, len);
+ return mport->ops->add_outb_message(mport, rdev, mbox,
+ buffer, len);
}
extern int rio_request_inb_mbox(struct rio_mport *, void *, int, int,
@@ -336,7 +337,7 @@ extern int rio_release_inb_mbox(struct rio_mport *, int);
static inline int rio_add_inb_buffer(struct rio_mport *mport, int mbox,
void *buffer)
{
- return rio_hw_add_inb_buffer(mport, mbox, buffer);
+ return mport->ops->add_inb_buffer(mport, mbox, buffer);
}
/**
@@ -348,7 +349,7 @@ static inline int rio_add_inb_buffer(struct rio_mport *mport, int mbox,
*/
static inline void *rio_get_inb_message(struct rio_mport *mport, int mbox)
{
- return rio_hw_get_inb_message(mport, mbox);
+ return mport->ops->get_inb_message(mport, mbox);
}
/* Doorbell management */
--
1.7.3.1
^ permalink raw reply related
* [PATCH 0/5] RapidIO: configuration and initialization changes
From: Alexandre Bounine @ 2011-02-28 20:51 UTC (permalink / raw)
To: akpm, linux-kernel, linuxppc-dev; +Cc: Alexandre Bounine, Thomas Moll
This set of patches eliminates RapidIO dependency on PowerPC architecture and
makes it available to other architectures (x86 and MIPS).
It also enables support of new platform independent RapidIO controllers such
as PCI-to-SRIO and PCI Express-to-SRIO.
Alexandre Bounine (5):
RapidIO: Add architecture specific callbacks
RapidIO: Modify configuration to support PCI-SRIO controller
RapidIO: Modify subsystem and driver initialization sequence
RapidIO: Modify mport ID assignment
RapidIO: remove mport resource reservation from common RIO code
arch/mips/Kconfig | 10 ++++
arch/powerpc/Kconfig | 10 ++++-
arch/powerpc/sysdev/Makefile | 2 +-
arch/powerpc/sysdev/fsl_rio.c | 96 ++++++++++++++++-------------------------
arch/x86/Kconfig | 10 ++++
drivers/net/rionet.c | 6 +-
drivers/rapidio/rio-sysfs.c | 1 +
drivers/rapidio/rio.c | 84 ++++++++++++++++++++++++-----------
include/linux/rio.h | 25 ++++++++---
include/linux/rio_drv.h | 7 ++-
10 files changed, 151 insertions(+), 100 deletions(-)
--
1.7.3.1
^ permalink raw reply
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Felix Radensky @ 2011-02-28 20:15 UTC (permalink / raw)
To: Ira W. Snyder; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <20110228195350.GA31428@ovro.caltech.edu>
[-- Attachment #1: Type: text/plain, Size: 395 bytes --]
Hi Ira,
> Thank you very much Felix. The dmesg output shows that the controller
> never got an interrupt for the second transaction. The patch below has
> extra debugging information that may help determine why this happens.
> Please apply it and re-run the test.
>
> The last section of dmesg (after "Freeing unused kernel memory") is all
> I need.
>
Attached relevant dmesg portion.
Felix.
[-- Attachment #2: dmesg.txt --]
[-- Type: text/plain, Size: 23041 bytes --]
Freeing unused kernel memory: 136k init
__dma_request_channel: success (dma0chan0)
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd000 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd060 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd0c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd120 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd180 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd1e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd240 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd2a0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd300 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: start=0
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: end=9
of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
of:fsl-elo-dma ffe0c300.dma: chan0: irq: stat = 0x6
of:fsl-elo-dma ffe0c300.dma: chan0: irq: End-of-segment INT
of:fsl-elo-dma ffe0c300.dma: chan0: irq: controller not idle!
of:fsl-elo-dma ffe0c300.dma: chan0: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan0: irq: stat = 0xa
of:fsl-elo-dma ffe0c300.dma: chan0: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: chan0: irq: End-of-segment INT
of:fsl-elo-dma ffe0c300.dma: chan0: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan0: tasklet entry
of:fsl-elo-dma ffe0c300.dma: chan0: completed_cookie=9
of:fsl-elo-dma ffe0c300.dma: chan0: no pending LDs
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd000 callback
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd000 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd060 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd0c0 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd120 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd180 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd1e0 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd240 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd2a0 free
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd300 free
of:fsl-elo-dma ffe0c300.dma: chan0: tasklet exit
dma0chan0-copy0: verifying source buffer...
dma0chan0-copy0: verifying dest buffer...
dma0chan0-copy0: #0: No errors with src_off=0x12b2 dst_off=0x1d7d len=0x2065
dma0chan0-copy0: terminating after 1 tests, 0 failures (status 0)
dmatest: Started 2 threads using dma0chan0
private_candidate: dma0chan0 busy
__dma_request_channel: success (dma0chan1)
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd300 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd2a0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd240 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd1e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: LD ef2cd180 allocated
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: start=9
of:fsl-elo-dma ffe0c300.dma: chan0: assign cookies: end=14
of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca000 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca060 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca0c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca120 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca180 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: assign cookies: start=0
of:fsl-elo-dma ffe0c300.dma: chan1: assign cookies: end=5
of:fsl-elo-dma ffe0c300.dma: chan1: idle, starting controller
of:fsl-elo-dma ffe0c300.dma: chan1: irq: stat = 0x6
of:fsl-elo-dma ffe0c300.dma: chan1: irq: End-of-segment INT
of:fsl-elo-dma ffe0c300.dma: chan1: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan1: irq: stat = 0xa
of:fsl-elo-dma ffe0c300.dma: chan1: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: chan1: irq: End-of-segment INT
of:fsl-elo-dma ffe0c300.dma: chan1: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan1: tasklet entry
of:fsl-elo-dma ffe0c300.dma: chan1: completed_cookie=5
of:fsl-elo-dma ffe0c300.dma: chan1: no pending LDs
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca000 callback
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca000 free
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca060 free
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca0c0 free
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca120 free
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca180 free
of:fsl-elo-dma ffe0c300.dma: chan1: tasklet exit
dma0chan1-copy0: verifying source buffer...
dma0chan1-copy0: verifying dest buffer...
dma0chan1-copy0: #0: No errors with src_off=0x1abf dst_off=0x240 len=0x1079
dma0chan1-copy0: terminating after 1 tests, 0 failures (status 0)
dmatest: Started 2 threads using dma0chan1
private_candidate: dma0chan0 busy
private_candidate: dma0chan1 busy
__dma_request_channel: success (dma0chan2)
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca180 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca120 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca0c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca060 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca000 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca1e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca240 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca2a0 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: LD ef2ca300 allocated
of:fsl-elo-dma ffe0c300.dma: chan1: assign cookies: start=5
of:fsl-elo-dma ffe0c300.dma: chan1: assign cookies: end=14
of:fsl-elo-dma ffe0c300.dma: chan1: idle, starting controller
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d000 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: assign cookies: start=0
of:fsl-elo-dma ffe0c300.dma: chan2: assign cookies: end=1
of:fsl-elo-dma ffe0c300.dma: chan2: idle, starting controller
of:fsl-elo-dma ffe0c300.dma: chan2: irq: stat = 0xa
of:fsl-elo-dma ffe0c300.dma: chan2: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: chan2: irq: End-of-segment INT
of:fsl-elo-dma ffe0c300.dma: chan2: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan2: tasklet entry
of:fsl-elo-dma ffe0c300.dma: chan2: completed_cookie=1
of:fsl-elo-dma ffe0c300.dma: chan2: no pending LDs
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d000 callback
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d000 free
of:fsl-elo-dma ffe0c300.dma: chan2: tasklet exit
dma0chan2-copy0: verifying source buffer...
dma0chan2-copy0: verifying dest buffer...
dma0chan2-copy0: #0: No errors with src_off=0x1837 dst_off=0x3bac len=0x73
dma0chan2-copy0: terminating after 1 tests, 0 failures (status 0)
dmatest: Started 2 threads using dma0chan2
private_candidate: dma0chan0 busy
private_candidate: dma0chan1 busy
private_candidate: dma0chan2 busy
__dma_request_channel: success (dma0chan3)
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d000 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d060 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d0c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d120 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d180 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d1e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d240 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: LD ef34d2a0 allocated
of:fsl-elo-dma ffe0c300.dma: chan2: assign cookies: start=1
of:fsl-elo-dma ffe0c300.dma: chan2: assign cookies: end=9
of:fsl-elo-dma ffe0c300.dma: chan2: idle, starting controller
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338000 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338060 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef3380c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338120 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: assign cookies: start=0
of:fsl-elo-dma ffe0c300.dma: chan3: assign cookies: end=4
of:fsl-elo-dma ffe0c300.dma: chan3: idle, starting controller
of:fsl-elo-dma ffe0c300.dma: chan3: irq: stat = 0x6
of:fsl-elo-dma ffe0c300.dma: chan3: irq: End-of-segment INT
of:fsl-elo-dma ffe0c300.dma: chan3: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan3: irq: stat = 0xa
of:fsl-elo-dma ffe0c300.dma: chan3: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: chan3: irq: End-of-segment INT
of:fsl-elo-dma ffe0c300.dma: chan3: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan3: tasklet entry
of:fsl-elo-dma ffe0c300.dma: chan3: completed_cookie=4
of:fsl-elo-dma ffe0c300.dma: chan3: no pending LDs
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338000 callback
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338000 free
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338060 free
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef3380c0 free
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338120 free
of:fsl-elo-dma ffe0c300.dma: chan3: tasklet exit
dmatest: Started 2 threads using dma0chan3
private_candidate: dma0chan0 busy
private_candidate: dma0chan1 busy
private_candidate: dma0chan2 busy
private_candidate: dma0chan3 busy
__dma_request_channel: success (dma1chan0)
dma0chan3-copy0: verifying source buffer...
dma0chan3-copy0: verifying dest buffer...
dma0chan3-copy0: #0: No errors with src_off=0x13a6 dst_off=0xd9c len=0xf40
dma0chan3-copy0: terminating after 1 tests, 0 failures (status 0)
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338120 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef3380c0 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338060 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338000 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338180 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef3381e0 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef338240 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: LD ef3382a0 allocated
of:fsl-elo-dma ffe0c300.dma: chan3: assign cookies: start=4
of:fsl-elo-dma ffe0c300.dma: chan3: assign cookies: end=12
of:fsl-elo-dma ffe0c300.dma: chan3: idle, starting controller
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3000 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3060 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b30c0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3120 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3180 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b31e0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3240 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b32a0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3300 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3360 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b33c0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: assign cookies: start=0
of:fsl-elo-dma ffe21300.dma: chan0: assign cookies: end=11
of:fsl-elo-dma ffe21300.dma: chan0: idle, starting controller
of:fsl-elo-dma ffe21300.dma: chan0: irq: stat = 0x6
of:fsl-elo-dma ffe21300.dma: chan0: irq: End-of-segment INT
of:fsl-elo-dma ffe21300.dma: chan0: irq: controller not idle!
of:fsl-elo-dma ffe21300.dma: chan0: irq: Exit
of:fsl-elo-dma ffe21300.dma: chan0: irq: stat = 0xa
of:fsl-elo-dma ffe21300.dma: chan0: irq: End-of-link INT
of:fsl-elo-dma ffe21300.dma: chan0: irq: End-of-segment INT
of:fsl-elo-dma ffe21300.dma: chan0: irq: Exit
of:fsl-elo-dma ffe21300.dma: chan0: tasklet entry
of:fsl-elo-dma ffe21300.dma: chan0: completed_cookie=11
of:fsl-elo-dma ffe21300.dma: chan0: no pending LDs
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3000 callback
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3000 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3060 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b30c0 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3120 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3180 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b31e0 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3240 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b32a0 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3300 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3360 free
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b33c0 free
of:fsl-elo-dma ffe21300.dma: chan0: tasklet exit
dma1chan0-copy0: verifying source buffer...
dma1chan0-copy0: verifying dest buffer...
dma1chan0-copy0: #0: No errors with src_off=0x63a dst_off=0x1342 len=0x28b3
dma1chan0-copy0: terminating after 1 tests, 0 failures (status 0)
dmatest: Started 2 threads using dma1chan0
private_candidate: dma0chan0 busy
private_candidate: dma0chan1 busy
private_candidate: dma0chan2 busy
private_candidate: dma0chan3 busy
private_candidate: dma1chan0 busy
__dma_request_channel: success (dma1chan1)
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b33c0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3360 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3300 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b32a0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3240 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b31e0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3180 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3120 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b30c0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3060 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3000 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3420 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b3480 allocated
of:fsl-elo-dma ffe21300.dma: chan0: LD ef3b34e0 allocated
of:fsl-elo-dma ffe21300.dma: chan0: assign cookies: start=11
of:fsl-elo-dma ffe21300.dma: chan0: assign cookies: end=25
of:fsl-elo-dma ffe21300.dma: chan0: idle, starting controller
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae000 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae060 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae0c0 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae120 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae180 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae1e0 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae240 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae2a0 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae300 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae360 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae3c0 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae420 allocated
of:fsl-elo-dma ffe21300.dma: chan1: assign cookies: start=0
of:fsl-elo-dma ffe21300.dma: chan1: assign cookies: end=12
of:fsl-elo-dma ffe21300.dma: chan1: idle, starting controller
of:fsl-elo-dma ffe21300.dma: chan1: irq: stat = 0x6
of:fsl-elo-dma ffe21300.dma: chan1: irq: End-of-segment INT
of:fsl-elo-dma ffe21300.dma: chan1: irq: controller not idle!
of:fsl-elo-dma ffe21300.dma: chan1: irq: Exit
of:fsl-elo-dma ffe21300.dma: chan1: irq: stat = 0xa
of:fsl-elo-dma ffe21300.dma: chan1: irq: End-of-link INT
of:fsl-elo-dma ffe21300.dma: chan1: irq: End-of-segment INT
of:fsl-elo-dma ffe21300.dma: chan1: irq: Exit
of:fsl-elo-dma ffe21300.dma: chan1: tasklet entry
of:fsl-elo-dma ffe21300.dma: chan1: completed_cookie=12
of:fsl-elo-dma ffe21300.dma: chan1: no pending LDs
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae000 callback
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae000 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae060 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae0c0 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae120 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae180 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae1e0 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae240 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae2a0 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae300 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae360 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae3c0 free
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae420 free
of:fsl-elo-dma ffe21300.dma: chan1: tasklet exit
dmatest: Started 2 threads using dma1chan1
private_candidate: dma0chan0 busy
private_candidate: dma0chan1 busy
private_candidate: dma0chan2 busy
private_candidate: dma0chan3 busy
private_candidate: dma1chan0 busy
private_candidate: dma1chan1 busy
__dma_request_channel: success (dma1chan2)
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae420 allocated
of:fsl-elo-dma ffe21300.dma: chan1: LD ef3ae3c0 allocated
of:fsl-elo-dma ffe21300.dma: chan1: assign cookies: start=12
of:fsl-elo-dma ffe21300.dma: chan1: assign cookies: end=14
of:fsl-elo-dma ffe21300.dma: chan1: idle, starting controller
dma1chan1-copy0: verifying source buffer...
dma1chan1-copy0: verifying dest buffer...
dma1chan1-copy0: #0: No errors with src_off=0x6d7 dst_off=0xdd6 len=0x2bad
dma1chan1-copy0: terminating after 1 tests, 0 failures (status 0)
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b000 allocated
of:fsl-elo-dma ffe21300.dma: chan2: assign cookies: start=0
of:fsl-elo-dma ffe21300.dma: chan2: assign cookies: end=1
of:fsl-elo-dma ffe21300.dma: chan2: idle, starting controller
of:fsl-elo-dma ffe21300.dma: chan2: irq: stat = 0xa
of:fsl-elo-dma ffe21300.dma: chan2: irq: End-of-link INT
of:fsl-elo-dma ffe21300.dma: chan2: irq: End-of-segment INT
of:fsl-elo-dma ffe21300.dma: chan2: irq: Exit
of:fsl-elo-dma ffe21300.dma: chan2: tasklet entry
of:fsl-elo-dma ffe21300.dma: chan2: completed_cookie=1
of:fsl-elo-dma ffe21300.dma: chan2: no pending LDs
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b000 callback
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b000 free
of:fsl-elo-dma ffe21300.dma: chan2: tasklet exit
dmatest: Started 2 threads using dma1chan2
private_candidate: dma0chan0 busy
private_candidate: dma0chan1 busy
private_candidate: dma0chan2 busy
private_candidate: dma0chan3 busy
private_candidate: dma1chan0 busy
private_candidate: dma1chan1 busy
private_candidate: dma1chan2 busy
__dma_request_channel: success (dma1chan3)
dma1chan2-copy0: verifying source buffer...
dma1chan2-copy0: verifying dest buffer...
dma1chan2-copy0: #0: No errors with src_off=0x39c9 dst_off=0x2def len=0x5c
dma1chan2-copy0: terminating after 1 tests, 0 failures (status 0)
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b000 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b060 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b0c0 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b120 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b180 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b1e0 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b240 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b2a0 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b300 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b360 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b3c0 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b420 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b480 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b4e0 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b540 allocated
of:fsl-elo-dma ffe21300.dma: chan2: LD ef37b5a0 allocated
of:fsl-elo-dma ffe21300.dma: chan2: assign cookies: start=1
of:fsl-elo-dma ffe21300.dma: chan2: assign cookies: end=17
of:fsl-elo-dma ffe21300.dma: chan2: idle, starting controller
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af000 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af060 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af0c0 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af120 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af180 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af1e0 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af240 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af2a0 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af300 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af360 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af3c0 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af420 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af480 allocated
of:fsl-elo-dma ffe21300.dma: chan3: assign cookies: start=0
of:fsl-elo-dma ffe21300.dma: chan3: assign cookies: end=13
of:fsl-elo-dma ffe21300.dma: chan3: idle, starting controller
of:fsl-elo-dma ffe21300.dma: chan3: irq: stat = 0x6
of:fsl-elo-dma ffe21300.dma: chan3: irq: End-of-segment INT
of:fsl-elo-dma ffe21300.dma: chan3: irq: controller not idle!
of:fsl-elo-dma ffe21300.dma: chan3: irq: Exit
of:fsl-elo-dma ffe21300.dma: chan3: irq: stat = 0xa
of:fsl-elo-dma ffe21300.dma: chan3: irq: End-of-link INT
of:fsl-elo-dma ffe21300.dma: chan3: irq: End-of-segment INT
of:fsl-elo-dma ffe21300.dma: chan3: irq: Exit
of:fsl-elo-dma ffe21300.dma: chan3: tasklet entry
of:fsl-elo-dma ffe21300.dma: chan3: completed_cookie=13
of:fsl-elo-dma ffe21300.dma: chan3: no pending LDs
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af000 callback
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af000 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af060 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af0c0 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af120 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af180 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af1e0 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af240 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af2a0 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af300 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af360 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af3c0 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af420 free
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af480 free
of:fsl-elo-dma ffe21300.dma: chan3: tasklet exit
dmatest: Started 2 threads using dma1chan3
private_candidate: dma0chan0 busy
private_candidate: dma0chan1 busy
private_candidate: dma0chan2 busy
private_candidate: dma0chan3 busy
private_candidate: dma1chan0 busy
private_candidate: dma1chan1 busy
private_candidate: dma1chan2 busy
private_candidate: dma1chan3 busy
__dma_request_channel: fail ((null))
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af480 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af420 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af3c0 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af360 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af300 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af2a0 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af240 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af1e0 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af180 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af120 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af0c0 allocated
of:fsl-elo-dma ffe21300.dma: chan3: LD ef3af060 allocated
of:fsl-elo-dma ffe21300.dma: chan3: assign cookies: start=13
of:fsl-elo-dma ffe21300.dma: chan3: assign cookies: end=25
of:fsl-elo-dma ffe21300.dma: chan3: idle, starting controller
dma1chan3-copy0: verifying source buffer...
dma1chan3-copy0: verifying dest buffer...
dma1chan3-copy0: #0: No errors with src_off=0x751 dst_off=0x5a0 len=0x3084
dma1chan3-copy0: terminating after 1 tests, 0 failures (status 0)
dma0chan0-copy1: #0: test timed out
dma0chan0-copy1: terminating after 1 tests, 1 failures (status 0)
dma0chan1-copy1: #0: test timed out
dma0chan1-copy1: terminating after 1 tests, 1 failures (status 0)
dma0chan2-copy1: #0: test timed out
dma0chan2-copy1: terminating after 1 tests, 1 failures (status 0)
dma0chan3-copy1: #0: test timed out
dma0chan3-copy1: terminating after 1 tests, 1 failures (status 0)
dma1chan0-copy1: #0: test timed out
dma1chan0-copy1: terminating after 1 tests, 1 failures (status 0)
dma1chan1-copy1: #0: test timed out
dma1chan1-copy1: terminating after 1 tests, 1 failures (status 0)
dma1chan2-copy1: #0: test timed out
dma1chan2-copy1: terminating after 1 tests, 1 failures (status 0)
dma1chan3-copy1: #0: test timed out
dma1chan3-copy1: terminating after 1 tests, 1 failures (status 0)
^ permalink raw reply
* [PATCH] powerpc/macintosh: Fix __devexit annotation in rack-meter.c
From: Grant Likely @ 2011-02-28 19:59 UTC (permalink / raw)
Cc: linuxppc-dev
The following warning was seen building rack-meter.c
WARNING: drivers/built-in.o(.text+0xac784): Section mismatch in reference from the function rackmeter_shutdown() to the function .devexit.text:rackmeter_stop_cpu_sniffer()
The function rackmeter_shutdown() references a function in an exit section.
Often the function rackmeter_stop_cpu_sniffer() has valid usage outside the exit section
and the fix is to remove the __devexit annotation of rackmeter_stop_cpu_sniffer.
This patch resolves the warning by removing the __devexit annotation from
rackmeter_stop_cpu_sniffer().
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
drivers/macintosh/rack-meter.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/macintosh/rack-meter.c b/drivers/macintosh/rack-meter.c
index 39f660b..2637c13 100644
--- a/drivers/macintosh/rack-meter.c
+++ b/drivers/macintosh/rack-meter.c
@@ -283,7 +283,7 @@ static void __devinit rackmeter_init_cpu_sniffer(struct rackmeter *rm)
}
}
-static void __devexit rackmeter_stop_cpu_sniffer(struct rackmeter *rm)
+static void rackmeter_stop_cpu_sniffer(struct rackmeter *rm)
{
cancel_delayed_work_sync(&rm->cpu[0].sniffer);
cancel_delayed_work_sync(&rm->cpu[1].sniffer);
^ permalink raw reply related
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Ira W. Snyder @ 2011-02-28 19:53 UTC (permalink / raw)
To: Felix Radensky; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <4D6BEDCE.3020102@embedded-sol.com>
On Mon, Feb 28, 2011 at 08:47:42PM +0200, Felix Radensky wrote:
> <br>
> Hi Ira,<br>
> <br>
> Attached dmesg output.<br>
> <br>
> Felix.<br>
> <br>
> <pre>On Mon, Feb 28, 2011 at 01:36:38PM +0200, Felix Radensky wrote:
> > Hi Ira,
> >
> > I've tried your patches with linux-2.6.38-rc6 on P2020RDB.
> > DMA test fails with the following errors if threads_per_chan != 1
> >
> > dma0chan0-copy1: terminating after 1 tests, 1 failures (status 0)
> > dma0chan0-copy2: #0: test timed out
> >
> > I've run the test like this:
> >
> > modprobe dmatest threads_per_chan=2 iterations=1
> >
>
> Thanks Felix. This works fine on the 83xx DMA controller. When you have
> a chance, can you add "#define DEBUG 1" as the first line of
> drivers/dma/fsldma.c and then rerun your test with:
>
> modprobe dmatest threads_per_chan=2 iterations=1 max_channels=1
>
> And send me the dmesg output.
>
> I don't quite understand the difference between links and lists in the
> 85xx controller yet. I'll work my way through the datasheet this morning
> and send out a fixed patch.
>
> Thanks very much for running the tests!
>
> Ira
[ snip most of dmesg output ]
> Freeing unused kernel memory: 136k init
> __dma_request_channel: success (dma0chan0)
> of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
> dmatest: Started 2 threads using dma0chan0
> of:fsl-elo-dma ffe0c300.dma: chan0: irq: stat = 0x8
> of:fsl-elo-dma ffe0c300.dma: chan0: irq: End-of-link INT
> of:fsl-elo-dma ffe0c300.dma: chan0: irq: Exit
> of:fsl-elo-dma ffe0c300.dma: chan0: tasklet entry
> of:fsl-elo-dma ffe0c300.dma: chan0: completed_cookie=1
> of:fsl-elo-dma ffe0c300.dma: chan0: no pending LDs
> of:fsl-elo-dma ffe0c300.dma: chan0: tasklet exit
> dma0chan0-copy0: verifying source buffer...
> dma0chan0-copy0: verifying dest buffer...
> dma0chan0-copy0: #0: No errors with src_off=0x3a2 dst_off=0xc1e len=0x2ce5
> dma0chan0-copy0: terminating after 1 tests, 0 failures (status 0)
> of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
> dma0chan0-copy1: #0: test timed out
> dma0chan0-copy1: terminating after 1 tests, 1 failures (status 0)
Thank you very much Felix. The dmesg output shows that the controller
never got an interrupt for the second transaction. The patch below has
extra debugging information that may help determine why this happens.
Please apply it and re-run the test.
The last section of dmesg (after "Freeing unused kernel memory") is all
I need.
Thanks again,
Ira
>From 8935444cb18c921332ebe1d055531e54f0c100e9 Mon Sep 17 00:00:00 2001
From: Ira W. Snyder <iws@ovro.caltech.edu>
Date: Mon, 28 Feb 2011 11:33:17 -0800
Subject: [PATCH] fsldma: try and debug 85xx controller
1 - reduce the maximum transfer size to 1000 bytes to force chains
2 - re-enable end-of-segment interrupts to see what the hardware does
3 - enable end-of-list interrupts to see what the hardware does
4 - debug cookies (this shouldn't be a problem, but just in case)
NOT AT ALL Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
---
drivers/dma/fsldma.c | 16 ++++++++++++++++
drivers/dma/fsldma.h | 3 ++-
2 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 3dc27a9..b82b76e 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -24,6 +24,9 @@
*
*/
+#define DEBUG 1
+#define FSL_DMA_LD_DEBUG 1
+
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pci.h>
@@ -162,6 +165,7 @@ static void dma_init(struct fsldma_chan *chan)
* BWC - Bandwidth sharing among channels
*/
DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
+ | FSL_DMA_MR_EOSIE | FSL_DMA_MR_EOLSIE
| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32);
break;
case FSL_DMA_IP_83XX:
@@ -389,6 +393,7 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
* that make up this transaction
*/
cookie = chan->common.cookie;
+ dev_dbg(chan->dev, "%s: assign cookies: start=%d\n", chan->name, cookie);
list_for_each_entry(child, &desc->tx_list, node) {
cookie++;
if (cookie < DMA_MIN_COOKIE)
@@ -397,6 +402,7 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
child->async_tx.cookie = cookie;
}
+ dev_dbg(chan->dev, "%s: assign cookies: end=%d\n", chan->name, cookie);
chan->common.cookie = cookie;
/* put this transaction onto the tail of the pending queue */
@@ -1018,6 +1024,16 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
stat &= ~FSL_DMA_SR_EOLNI;
}
+ if (stat & FSL_DMA_SR_EOLSI) {
+ dev_dbg(chan->dev, "%s: irq: End-of-list INT\n", name);
+ stat &= ~FSL_DMA_SR_EOLSI;
+ }
+
+ if (stat & FSL_DMA_SR_EOSI) {
+ dev_dbg(chan->dev, "%s: irq: End-of-segment INT\n", name);
+ stat &= ~FSL_DMA_SR_EOSI;
+ }
+
/* check that the DMA controller is really idle */
if (!dma_is_idle(chan))
dev_err(chan->dev, "%s: irq: controller not idle!\n", name);
diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 9cb5aa5..322aa0c 100644
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -73,7 +73,8 @@
#define FSL_DMA_EOSIE 0x8
#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
-#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
+//#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
+#define FSL_DMA_BCR_MAX_CNT 1000
#define FSL_DMA_DGSR_TE 0x80
#define FSL_DMA_DGSR_CH 0x20
--
1.7.3.4
^ permalink raw reply related
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Felix Radensky @ 2011-02-28 18:47 UTC (permalink / raw)
To: Ira W. Snyder, linuxppc-dev@ozlabs.org
[-- Attachment #1: Type: text/html, Size: 2589 bytes --]
[-- Attachment #2: dmesg.txt --]
[-- Type: text/plain, Size: 12674 bytes --]
Using P2020 RDB machine description
Memory CAM mapping: 256/256/256 Mb, residual: 256Mb
Linux version 2.6.38-rc6 (felix@felix.lan) (gcc version 4.2.2) #6 Mon Feb 28 20:40:18 IST 2011
Found legacy serial port 0 for /soc@ffe00000/serial@4500
mem=ffe04500, taddr=ffe04500, irq=0, clk=600000000, speed=0
Found legacy serial port 1 for /soc@ffe00000/serial@4600
mem=ffe04600, taddr=ffe04600, irq=0, clk=600000000, speed=0
bootconsole [udbg0] enabled
Found FSL PCI host bridge at 0x00000000ffe09000. Firmware bus number: 0->255
PCI host bridge /pcie@ffe09000 ranges:
MEM 0x00000000a0000000..0x00000000bfffffff -> 0x00000000a0000000
IO 0x00000000ffc30000..0x00000000ffc3ffff -> 0x0000000000000000
/pcie@ffe09000: PCICSRBAR @ 0xfff00000
Found FSL PCI host bridge at 0x00000000ffe0a000. Firmware bus number: 0->0
PCI host bridge /pcie@ffe0a000 ranges:
MEM 0x00000000c0000000..0x00000000dfffffff -> 0x00000000c0000000
IO 0x00000000ffc20000..0x00000000ffc2ffff -> 0x0000000000000000
/pcie@ffe0a000: PCICSRBAR @ 0xfff00000
MPC85xx RDB board from Freescale Semiconductor
Top of RAM: 0x40000000, Total RAM: 0x40000000
Memory hole size: 0MB
Zone PFN ranges:
DMA 0x00000000 -> 0x00030000
Normal empty
HighMem 0x00030000 -> 0x00040000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
0: 0x00000000 -> 0x00040000
On node 0 totalpages: 262144
free_area_init_node: node 0, pgdat c02ecfcc, node_mem_map c030e000
DMA zone: 1536 pages used for memmap
DMA zone: 0 pages reserved
DMA zone: 195072 pages, LIFO batch:31
HighMem zone: 512 pages used for memmap
HighMem zone: 65024 pages, LIFO batch:15
MMU: Allocated 1088 bytes of context maps for 255 contexts
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096
Kernel command line: root=/dev/nfs rw nfsroot=10.0.0.10:/opt/eldk/4.2/ppc_85xxDP ip=10.0.0.30:10.0.0.10::255.0.0.0:P2020RDB:eth0:off console=ttyS0,115200 ramdisk_size=700000 cache-sram-size=0x10000
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
High memory: 262140k
Memory: 1036340k/1048576k available (2928k kernel code, 12236k reserved, 104k data, 83k bss, 136k init)
Kernel virtual memory layout:
* 0xfffcf000..0xfffff000 : fixmap
* 0xffc00000..0xffe00000 : highmem PTEs
* 0xffbda000..0xffc00000 : early ioremap
* 0xf1000000..0xffbda000 : vmalloc & ioremap
SLUB: Genslabs=15, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:512 nr_irqs:512 16
mpic: Setting up MPIC " OpenPIC " version 1.2 at ffe40000, max 2 CPUs
mpic: ISU size: 256, shift: 8, mask: ff
mpic: Initializing for 256 sources
time_init: decrementer frequency = 75.000000 MHz
time_init: processor frequency = 1200.000000 MHz
clocksource: timebase mult[3555555] shift[22] registered
clockevent: decrementer mult[13333333] shift[32] cpu[0]
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
NET: Registered protocol family 16
PCI: Probing PCI hardware
pci 0000:00:00.0: [1957:0070] type 1 class 0x000b20
pci 0000:00:00.0: ignoring class b20 (doesn't match header type 01)
pci 0000:00:00.0: supports D1 D2
pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:00:00.0: PME# disabled
pci 0000:00:00.0: PCI bridge to [bus 01-ff]
pci 0000:00:00.0: bridge window [io 0x0000-0x0000] (disabled)
pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff] (disabled)
pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff pref] (disabled)
pci 0001:02:00.0: [1957:0070] type 1 class 0x000b20
pci 0001:02:00.0: ignoring class b20 (doesn't match header type 01)
pci 0001:02:00.0: supports D1 D2
pci 0001:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold
pci 0001:02:00.0: PME# disabled
pci 0001:02:00.0: PCI bridge to [bus 03-ff]
pci 0001:02:00.0: bridge window [io 0x0000-0x0000] (disabled)
pci 0001:02:00.0: bridge window [mem 0x00000000-0x000fffff] (disabled)
pci 0001:02:00.0: bridge window [mem 0x00000000-0x000fffff pref] (disabled)
pcibios_allocate_bus_resources: i=0 flags 0x100 start 0xef050d7c end 0x0
pcibios_allocate_bus_resources: i=1 flags 0x200 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=0 flags 0x100 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=1 flags 0x200 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=2 flags 0x0 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=3 flags 0x0 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=0 flags 0x100 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=1 flags 0x200 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=0 flags 0x100 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=1 flags 0x200 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=2 flags 0x0 start 0x4000 end 0x0
pcibios_allocate_bus_resources: i=3 flags 0x0 start 0x4000 end 0x0
PCI 0000:00 Cannot reserve Legacy IO [io 0xffbed000-0xffbedfff]
PCI 0001:02 Cannot reserve Legacy IO [io 0xffbdb000-0xffbdbfff]
pci 0000:00:00.0: PCI bridge to [bus 01-01]
pci 0000:00:00.0: bridge window [io 0xffbed000-0xffbfcfff]
pci 0000:00:00.0: bridge window [mem 0xa0000000-0xbfffffff]
pci 0000:00:00.0: bridge window [mem pref disabled]
pci 0000:00:00.0: enabling device (0106 -> 0107)
pci 0001:02:00.0: PCI bridge to [bus 03-03]
pci 0001:02:00.0: bridge window [io 0xffbdb000-0xffbeafff]
pci 0001:02:00.0: bridge window [mem 0xc0000000-0xdfffffff]
pci 0001:02:00.0: bridge window [mem pref disabled]
pci 0001:02:00.0: enabling device (0106 -> 0107)
pci_bus 0000:00: resource 0 [io 0xffbed000-0xffbfcfff]
pci_bus 0000:00: resource 1 [mem 0xa0000000-0xbfffffff]
pci_bus 0000:01: resource 0 [io 0xffbed000-0xffbfcfff]
pci_bus 0000:01: resource 1 [mem 0xa0000000-0xbfffffff]
pci_bus 0001:02: resource 0 [io 0xffbdb000-0xffbeafff]
pci_bus 0001:02: resource 1 [mem 0xc0000000-0xdfffffff]
pci_bus 0001:03: resource 0 [io 0xffbdb000-0xffbeafff]
pci_bus 0001:03: resource 1 [mem 0xc0000000-0xdfffffff]
vgaarb: loaded
Freescale Elo / Elo Plus DMA driver
Switching to clocksource timebase
Switched to NOHz mode on CPU #0
NET: Registered protocol family 2
IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
TCP: Hash tables configured (established 131072 bind 65536)
TCP reno registered
UDP hash table entries: 512 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 512 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 0 bytes, default 32
irq: irq 42 on host /soc@ffe00000/pic@40000 mapped to virtual irq 42
irq: irq 19 on host /soc@ffe00000/pic@40000 mapped to virtual irq 19
irq: irq 17 on host /soc@ffe00000/pic@40000 mapped to virtual irq 17
irq: irq 18 on host /soc@ffe00000/pic@40000 mapped to virtual irq 18
irq: irq 43 on host /soc@ffe00000/pic@40000 mapped to virtual irq 43
irq: irq 59 on host /soc@ffe00000/pic@40000 mapped to virtual irq 59
irq: irq 76 on host /soc@ffe00000/pic@40000 mapped to virtual irq 76
of:fsl-elo-dma ffe0c300.dma: #0 (fsl,eloplus-dma-channel), irq 76
irq: irq 77 on host /soc@ffe00000/pic@40000 mapped to virtual irq 77
of:fsl-elo-dma ffe0c300.dma: #1 (fsl,eloplus-dma-channel), irq 77
irq: irq 78 on host /soc@ffe00000/pic@40000 mapped to virtual irq 78
of:fsl-elo-dma ffe0c300.dma: #2 (fsl,eloplus-dma-channel), irq 78
irq: irq 79 on host /soc@ffe00000/pic@40000 mapped to virtual irq 79
of:fsl-elo-dma ffe0c300.dma: #3 (fsl,eloplus-dma-channel), irq 79
of:fsl-elo-dma ffe0c300.dma: request channel 0 IRQ
of:fsl-elo-dma ffe0c300.dma: request channel 1 IRQ
of:fsl-elo-dma ffe0c300.dma: request channel 2 IRQ
of:fsl-elo-dma ffe0c300.dma: request channel 3 IRQ
irq: irq 47 on host /soc@ffe00000/pic@40000 mapped to virtual irq 47
irq: irq 16 on host /soc@ffe00000/pic@40000 mapped to virtual irq 16
irq: irq 20 on host /soc@ffe00000/pic@40000 mapped to virtual irq 20
of:fsl-elo-dma ffe21300.dma: #0 (fsl,eloplus-dma-channel), irq 20
irq: irq 21 on host /soc@ffe00000/pic@40000 mapped to virtual irq 21
of:fsl-elo-dma ffe21300.dma: #1 (fsl,eloplus-dma-channel), irq 21
irq: irq 22 on host /soc@ffe00000/pic@40000 mapped to virtual irq 22
of:fsl-elo-dma ffe21300.dma: #2 (fsl,eloplus-dma-channel), irq 22
irq: irq 23 on host /soc@ffe00000/pic@40000 mapped to virtual irq 23
of:fsl-elo-dma ffe21300.dma: #3 (fsl,eloplus-dma-channel), irq 23
of:fsl-elo-dma ffe21300.dma: request channel 0 IRQ
of:fsl-elo-dma ffe21300.dma: request channel 1 IRQ
of:fsl-elo-dma ffe21300.dma: request channel 2 IRQ
of:fsl-elo-dma ffe21300.dma: request channel 3 IRQ
irq: irq 28 on host /soc@ffe00000/pic@40000 mapped to virtual irq 28
irq: irq 29 on host /soc@ffe00000/pic@40000 mapped to virtual irq 29
irq: irq 30 on host /soc@ffe00000/pic@40000 mapped to virtual irq 30
irq: irq 34 on host /soc@ffe00000/pic@40000 mapped to virtual irq 34
irq: irq 35 on host /soc@ffe00000/pic@40000 mapped to virtual irq 35
irq: irq 36 on host /soc@ffe00000/pic@40000 mapped to virtual irq 36
irq: irq 40 on host /soc@ffe00000/pic@40000 mapped to virtual irq 40
irq: irq 31 on host /soc@ffe00000/pic@40000 mapped to virtual irq 31
irq: irq 32 on host /soc@ffe00000/pic@40000 mapped to virtual irq 32
irq: irq 33 on host /soc@ffe00000/pic@40000 mapped to virtual irq 33
irq: irq 72 on host /soc@ffe00000/pic@40000 mapped to virtual irq 72
irq: irq 45 on host /soc@ffe00000/pic@40000 mapped to virtual irq 45
irq: irq 58 on host /soc@ffe00000/pic@40000 mapped to virtual irq 58
irq: irq 224 on host /soc@ffe00000/pic@40000 mapped to virtual irq 224
irq: irq 225 on host /soc@ffe00000/pic@40000 mapped to virtual irq 225
irq: irq 226 on host /soc@ffe00000/pic@40000 mapped to virtual irq 226
irq: irq 227 on host /soc@ffe00000/pic@40000 mapped to virtual irq 227
irq: irq 228 on host /soc@ffe00000/pic@40000 mapped to virtual irq 228
irq: irq 229 on host /soc@ffe00000/pic@40000 mapped to virtual irq 229
irq: irq 230 on host /soc@ffe00000/pic@40000 mapped to virtual irq 230
irq: irq 231 on host /soc@ffe00000/pic@40000 mapped to virtual irq 231
Setting up Freescale MSI support
msgmni has been set to 1512
Freescale DIU driver
Serial: 8250/16550 driver, 2 ports, IRQ sharing enabled
serial8250.0: ttyS0 at MMIO 0xffe04500 (irq = 42) is a 16550A
console [ttyS0] enabled, bootconsole disabled
serial8250.0: ttyS1 at MMIO 0xffe04600 (irq = 42) is a 16550A
Fixed MDIO Bus: probed
eth0: Gianfar Ethernet Controller Version 1.2, 00:04:9f:ec:a1:02
eth0: Running with NAPI enabled
eth0: RX BD ring size for Q[0]: 256
eth0: TX BD ring size for Q[0]: 256
eth1: Gianfar Ethernet Controller Version 1.2, 00:04:9f:ec:a1:11
eth1: Running with NAPI enabled
eth1: RX BD ring size for Q[0]: 256
eth1: TX BD ring size for Q[0]: 256
eth2: Gianfar Ethernet Controller Version 1.2, 00:04:9f:ec:a1:01
eth2: Running with NAPI enabled
eth2: RX BD ring size for Q[0]: 256
eth2: TX BD ring size for Q[0]: 256
Freescale PowerQUICC MII Bus: probed
irq: irq 3 on host /soc@ffe00000/pic@40000 mapped to virtual irq 24
Freescale PowerQUICC MII Bus: probed
of:mpc-i2c ffe03000.i2c: timeout 1000000 us
of:mpc-i2c ffe03100.i2c: timeout 1000000 us
TCP cubic registered
NET: Registered protocol family 17
IP-Config: Complete:
device=eth0, addr=10.0.0.30, mask=255.0.0.0, gw=255.255.255.255,
host=P2020RDB, domain=, nis-domain=(none),
bootserver=10.0.0.10, rootserver=10.0.0.10, rootpath=
PHY: 0:01 - Link is Up - 1000/Full
VFS: Mounted root (nfs filesystem) on device 0:11.
Freeing unused kernel memory: 136k init
__dma_request_channel: success (dma0chan0)
of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
dmatest: Started 2 threads using dma0chan0
of:fsl-elo-dma ffe0c300.dma: chan0: irq: stat = 0x8
of:fsl-elo-dma ffe0c300.dma: chan0: irq: End-of-link INT
of:fsl-elo-dma ffe0c300.dma: chan0: irq: Exit
of:fsl-elo-dma ffe0c300.dma: chan0: tasklet entry
of:fsl-elo-dma ffe0c300.dma: chan0: completed_cookie=1
of:fsl-elo-dma ffe0c300.dma: chan0: no pending LDs
of:fsl-elo-dma ffe0c300.dma: chan0: tasklet exit
dma0chan0-copy0: verifying source buffer...
dma0chan0-copy0: verifying dest buffer...
dma0chan0-copy0: #0: No errors with src_off=0x3a2 dst_off=0xc1e len=0x2ce5
dma0chan0-copy0: terminating after 1 tests, 0 failures (status 0)
of:fsl-elo-dma ffe0c300.dma: chan0: idle, starting controller
dma0chan0-copy1: #0: test timed out
dma0chan0-copy1: terminating after 1 tests, 1 failures (status 0)
^ permalink raw reply
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Ira W. Snyder @ 2011-02-28 17:16 UTC (permalink / raw)
To: Felix Radensky; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <4D6B88C6.2000404@embedded-sol.com>
On Mon, Feb 28, 2011 at 01:36:38PM +0200, Felix Radensky wrote:
> Hi Ira,
>
> I've tried your patches with linux-2.6.38-rc6 on P2020RDB.
> DMA test fails with the following errors if threads_per_chan != 1
>
> dma0chan0-copy1: terminating after 1 tests, 1 failures (status 0)
> dma0chan0-copy2: #0: test timed out
>
> I've run the test like this:
>
> modprobe dmatest threads_per_chan=2 iterations=1
>
Thanks Felix. This works fine on the 83xx DMA controller. When you have
a chance, can you add "#define DEBUG 1" as the first line of
drivers/dma/fsldma.c and then rerun your test with:
modprobe dmatest threads_per_chan=2 iterations=1 max_channels=1
And send me the dmesg output.
I don't quite understand the difference between links and lists in the
85xx controller yet. I'll work my way through the datasheet this morning
and send out a fixed patch.
Thanks very much for running the tests!
Ira
^ permalink raw reply
* Re: [PATCH 0/8] fsldma: lockup fixes
From: Felix Radensky @ 2011-02-28 11:36 UTC (permalink / raw)
To: Ira W. Snyder, linuxppc-dev@ozlabs.org
Hi Ira,
I've tried your patches with linux-2.6.38-rc6 on P2020RDB.
DMA test fails with the following errors if threads_per_chan != 1
dma0chan0-copy1: terminating after 1 tests, 1 failures (status 0)
dma0chan0-copy2: #0: test timed out
I've run the test like this:
modprobe dmatest threads_per_chan=2 iterations=1
Felix.
^ permalink raw reply
* [PATCH V12 4/4] ptp: Added a clock driver for the National Semiconductor PHYTER.
From: Richard Cochran @ 2011-02-28 7:58 UTC (permalink / raw)
To: linux-kernel
Cc: Thomas Gleixner, Rodolfo Giometti, Arnd Bergmann, Peter Zijlstra,
linux-api, devicetree-discuss, Russell King, Paul Mackerras,
John Stultz, linux-arm-kernel, netdev, Mike Frysinger,
Christoph Lameter, linuxppc-dev, David Miller, Alan Cox,
Krzysztof Halasa
In-Reply-To: <cover.1298878618.git.richard.cochran@omicron.at>
This patch adds support for the PTP clock found on the DP83640.
The basic clock operations and one external time stamp have
been implemented.
Signed-off-by: Richard Cochran <richard.cochran@omicron.at>
---
drivers/net/phy/Makefile | 1 +
drivers/net/phy/dp83640.c | 1012 +++++++++++++++++++++++++++++++++++++++++
drivers/net/phy/dp83640_reg.h | 267 +++++++++++
drivers/ptp/Kconfig | 19 +
4 files changed, 1299 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/phy/dp83640.c
create mode 100644 drivers/net/phy/dp83640_reg.h
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY) += fixed.o
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
+obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 0000000..74f751e
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1012 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/ethtool.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/net_tstamp.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/ptp_classify.h>
+#include <linux/ptp_clock_kernel.h>
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID 0x20005ce1
+#define PAGESEL 0x13
+#define LAYER4 0x02
+#define LAYER2 0x01
+#define MAX_RXTS 4
+#define MAX_TXTS 4
+#define N_EXT_TS 1
+#define PSF_PTPVER 2
+#define PSF_EVNT 0x4000
+#define PSF_RX 0x2000
+#define PSF_TX 0x1000
+#define EXT_EVENT 1
+#define EXT_GPIO 1
+#define CAL_EVENT 2
+#define CAL_GPIO 9
+#define CAL_TRIGGER 2
+
+/* phyter seems to miss the mark by 16 ns */
+#define ADJTIME_FIX 16
+
+#if defined(__BIG_ENDIAN)
+#define ENDIAN_FLAG 0
+#elif defined(__LITTLE_ENDIAN)
+#define ENDIAN_FLAG PSF_ENDIAN
+#endif
+
+#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
+
+struct phy_rxts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+ u16 seqid; /* sequenceId[15:0] */
+ u16 msgtype; /* messageType[3:0], hash[11:0] */
+};
+
+struct phy_txts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+};
+
+struct rxts {
+ struct list_head list;
+ unsigned long tmo;
+ u64 ns;
+ u16 seqid;
+ u8 msgtype;
+ u16 hash;
+};
+
+struct dp83640_clock;
+
+struct dp83640_private {
+ struct list_head list;
+ struct dp83640_clock *clock;
+ struct phy_device *phydev;
+ struct work_struct ts_work;
+ int hwts_tx_en;
+ int hwts_rx_en;
+ int layer;
+ int version;
+ /* remember state of cfg0 during calibration */
+ int cfg0;
+ /* remember the last event time stamp */
+ struct phy_txts edata;
+ /* list of rx timestamps */
+ struct list_head rxts;
+ struct list_head rxpool;
+ struct rxts rx_pool_data[MAX_RXTS];
+ /* protects above three fields from concurrent access */
+ spinlock_t rx_lock;
+ /* queues of incoming and outgoing packets */
+ struct sk_buff_head rx_queue;
+ struct sk_buff_head tx_queue;
+};
+
+struct dp83640_clock {
+ /* protects extended registers from concurrent access */
+ struct mutex extreg_lock;
+ /* remembers which page was last selected */
+ int page;
+ /* our advertised capabilities */
+ struct ptp_clock_info caps;
+ /* the one phyter from which we shall read */
+ struct dp83640_private *chosen;
+ /* list of the other attached phyters, not chosen */
+ struct list_head phylist;
+ /* reference to our PTP hardware clock */
+ struct ptp_clock *ptp_clock;
+};
+
+/* globals */
+
+static int chosen_phy = -1;
+static ushort cal_gpio = 4;
+static char *mii_busid = "0";
+
+module_param(chosen_phy, int, 0444);
+module_param(cal_gpio, ushort, 0444);
+module_param(mii_busid, charp, 0444);
+
+MODULE_PARM_DESC(chosen_phy, \
+ "The address of the PHY to use for the ancillary clock features");
+MODULE_PARM_DESC(cal_gpio, \
+ "Which GPIO line to use for synchronizing multiple PHYs");
+MODULE_PARM_DESC(mii_busid, \
+ "The ID of the MII bus to which the PHYs are connected");
+
+static void rx_timestamp_work(struct work_struct *work);
+
+/* extended register access functions */
+
+#define BROADCAST_ADDR 31
+
+static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
+{
+ return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
+}
+
+static int ext_read(struct phy_device *phydev, int page, u32 regnum)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+ int val;
+
+ if (dp83640->clock->page != page) {
+ broadcast_write(phydev->bus, PAGESEL, page);
+ dp83640->clock->page = page;
+ }
+ val = phy_read(phydev, regnum);
+
+ return val;
+}
+
+static void ext_write(int broadcast, struct phy_device *phydev,
+ int page, u32 regnum, u16 val)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+
+ if (dp83640->clock->page != page) {
+ broadcast_write(phydev->bus, PAGESEL, page);
+ dp83640->clock->page = page;
+ }
+ if (broadcast)
+ broadcast_write(phydev->bus, regnum, val);
+ else
+ phy_write(phydev, regnum, val);
+}
+
+static int tdr_write(int bc, struct phy_device *dev,
+ const struct timespec *ts, u16 cmd)
+{
+ ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
+ ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
+ ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
+ ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
+
+ ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
+
+ return 0;
+}
+
+/* convert phy timestamps into driver timestamps */
+
+static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
+{
+ u32 sec;
+
+ sec = p->sec_lo;
+ sec |= p->sec_hi << 16;
+
+ rxts->ns = p->ns_lo;
+ rxts->ns |= (p->ns_hi & 0x3fff) << 16;
+ rxts->ns += ((u64)sec) * 1000000000ULL;
+ rxts->seqid = p->seqid;
+ rxts->msgtype = (p->msgtype >> 12) & 0xf;
+ rxts->hash = p->msgtype & 0x0fff;
+ rxts->tmo = jiffies + HZ;
+}
+
+static u64 phy2txts(struct phy_txts *p)
+{
+ u64 ns;
+ u32 sec;
+
+ sec = p->sec_lo;
+ sec |= p->sec_hi << 16;
+
+ ns = p->ns_lo;
+ ns |= (p->ns_hi & 0x3fff) << 16;
+ ns += ((u64)sec) * 1000000000ULL;
+
+ return ns;
+}
+
+/* ptp clock methods */
+
+static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ u64 rate;
+ int neg_adj = 0;
+ u16 hi, lo;
+
+ if (ppb < 0) {
+ neg_adj = 1;
+ ppb = -ppb;
+ }
+ rate = ppb;
+ rate <<= 26;
+ rate = div_u64(rate, 1953125);
+
+ hi = (rate >> 16) & PTP_RATE_HI_MASK;
+ if (neg_adj)
+ hi |= PTP_RATE_DIR;
+
+ lo = rate & 0xffff;
+
+ mutex_lock(&clock->extreg_lock);
+
+ ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
+ ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
+
+ mutex_unlock(&clock->extreg_lock);
+
+ return 0;
+}
+
+static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ struct timespec ts;
+ int err;
+
+ delta += ADJTIME_FIX;
+
+ ts = ns_to_timespec(delta);
+
+ mutex_lock(&clock->extreg_lock);
+
+ err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
+
+ mutex_unlock(&clock->extreg_lock);
+
+ return err;
+}
+
+static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ unsigned int val[4];
+
+ mutex_lock(&clock->extreg_lock);
+
+ ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
+
+ val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
+ val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
+ val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
+ val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
+
+ mutex_unlock(&clock->extreg_lock);
+
+ ts->tv_nsec = val[0] | (val[1] << 16);
+ ts->tv_sec = val[2] | (val[3] << 16);
+
+ return 0;
+}
+
+static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
+ const struct timespec *ts)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ int err;
+
+ mutex_lock(&clock->extreg_lock);
+
+ err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
+
+ mutex_unlock(&clock->extreg_lock);
+
+ return err;
+}
+
+static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *rq, int on)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ u16 evnt;
+
+ switch (rq->type) {
+ case PTP_CLK_REQ_EXTTS:
+ if (rq->extts.index != 0)
+ return -EINVAL;
+ evnt = EVNT_WR | (EXT_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
+ if (on) {
+ evnt |= (EXT_GPIO & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
+ evnt |= EVNT_RISE;
+ }
+ ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
+ return 0;
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
+static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
+
+static void enable_status_frames(struct phy_device *phydev, bool on)
+{
+ u16 cfg0 = 0, ver;
+
+ if (on)
+ cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
+
+ ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
+
+ ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
+ ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
+
+ if (!phydev->attached_dev) {
+ pr_err("expected to find an attached netdevice\n");
+ BUG();
+ }
+
+ if (on) {
+ if (dev_mc_add(phydev->attached_dev, status_frame_dst))
+ pr_warning("dp83640: failed to add mc address\n");
+ } else {
+ if (dev_mc_del(phydev->attached_dev, status_frame_dst))
+ pr_warning("dp83640: failed to delete mc address\n");
+ }
+}
+
+static bool is_status_frame(struct sk_buff *skb, int type)
+{
+ struct ethhdr *h = eth_hdr(skb);
+
+ if (PTP_CLASS_V2_L2 == type &&
+ !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
+ return true;
+ else
+ return false;
+}
+
+static int expired(struct rxts *rxts)
+{
+ return time_after(jiffies, rxts->tmo);
+}
+
+/* Caller must hold rx_lock. */
+static void prune_rx_ts(struct dp83640_private *dp83640)
+{
+ struct list_head *this, *next;
+ struct rxts *rxts;
+
+ list_for_each_safe(this, next, &dp83640->rxts) {
+ rxts = list_entry(this, struct rxts, list);
+ if (expired(rxts)) {
+ list_del_init(&rxts->list);
+ list_add(&rxts->list, &dp83640->rxpool);
+ }
+ }
+}
+
+/* synchronize the phyters so they act as one clock */
+
+static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
+{
+ int val;
+ phy_write(phydev, PAGESEL, 0);
+ val = phy_read(phydev, PHYCR2);
+ if (on)
+ val |= BC_WRITE;
+ else
+ val &= ~BC_WRITE;
+ phy_write(phydev, PHYCR2, val);
+ phy_write(phydev, PAGESEL, init_page);
+}
+
+static void recalibrate(struct dp83640_clock *clock)
+{
+ s64 now, diff;
+ struct phy_txts event_ts;
+ struct timespec ts;
+ struct list_head *this;
+ struct dp83640_private *tmp;
+ struct phy_device *master = clock->chosen->phydev;
+ u16 cfg0, evnt, ptp_trig, trigger, val;
+
+ trigger = CAL_TRIGGER;
+
+ mutex_lock(&clock->extreg_lock);
+
+ /*
+ * enable broadcast, disable status frames, enable ptp clock
+ */
+ list_for_each(this, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ enable_broadcast(tmp->phydev, clock->page, 1);
+ tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
+ ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
+ ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
+ }
+ enable_broadcast(master, clock->page, 1);
+ cfg0 = ext_read(master, PAGE5, PSF_CFG0);
+ ext_write(0, master, PAGE5, PSF_CFG0, 0);
+ ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
+
+ /*
+ * enable an event timestamp
+ */
+ evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
+ evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
+ evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
+
+ list_for_each(this, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
+ }
+ ext_write(0, master, PAGE5, PTP_EVNT, evnt);
+
+ /*
+ * configure a trigger
+ */
+ ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
+ ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
+ ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
+ ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
+
+ /* load trigger */
+ val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
+ val |= TRIG_LOAD;
+ ext_write(0, master, PAGE4, PTP_CTL, val);
+
+ /* enable trigger */
+ val &= ~TRIG_LOAD;
+ val |= TRIG_EN;
+ ext_write(0, master, PAGE4, PTP_CTL, val);
+
+ /* disable trigger */
+ val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
+ val |= TRIG_DIS;
+ ext_write(0, master, PAGE4, PTP_CTL, val);
+
+ /*
+ * read out and correct offsets
+ */
+ val = ext_read(master, PAGE4, PTP_STS);
+ pr_info("master PTP_STS 0x%04hx", val);
+ val = ext_read(master, PAGE4, PTP_ESTS);
+ pr_info("master PTP_ESTS 0x%04hx", val);
+ event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
+ event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
+ event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
+ event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
+ now = phy2txts(&event_ts);
+
+ list_for_each(this, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ val = ext_read(tmp->phydev, PAGE4, PTP_STS);
+ pr_info("slave PTP_STS 0x%04hx", val);
+ val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
+ pr_info("slave PTP_ESTS 0x%04hx", val);
+ event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
+ event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
+ event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
+ event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
+ diff = now - (s64) phy2txts(&event_ts);
+ pr_info("slave offset %lld nanoseconds\n", diff);
+ diff += ADJTIME_FIX;
+ ts = ns_to_timespec(diff);
+ tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
+ }
+
+ /*
+ * restore status frames
+ */
+ list_for_each(this, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
+ }
+ ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
+
+ mutex_unlock(&clock->extreg_lock);
+}
+
+/* time stamping methods */
+
+static void decode_evnt(struct dp83640_private *dp83640,
+ struct phy_txts *phy_txts, u16 ests)
+{
+ struct ptp_clock_event event;
+ int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
+
+ switch (words) { /* fall through in every case */
+ case 3:
+ dp83640->edata.sec_hi = phy_txts->sec_hi;
+ case 2:
+ dp83640->edata.sec_lo = phy_txts->sec_lo;
+ case 1:
+ dp83640->edata.ns_hi = phy_txts->ns_hi;
+ case 0:
+ dp83640->edata.ns_lo = phy_txts->ns_lo;
+ }
+
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 0;
+ event.timestamp = phy2txts(&dp83640->edata);
+
+ ptp_clock_event(dp83640->clock->ptp_clock, &event);
+}
+
+static void decode_rxts(struct dp83640_private *dp83640,
+ struct phy_rxts *phy_rxts)
+{
+ struct rxts *rxts;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dp83640->rx_lock, flags);
+
+ prune_rx_ts(dp83640);
+
+ if (list_empty(&dp83640->rxpool)) {
+ pr_warning("dp83640: rx timestamp pool is empty\n");
+ goto out;
+ }
+ rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
+ list_del_init(&rxts->list);
+ phy2rxts(phy_rxts, rxts);
+ list_add_tail(&rxts->list, &dp83640->rxts);
+out:
+ spin_unlock_irqrestore(&dp83640->rx_lock, flags);
+}
+
+static void decode_txts(struct dp83640_private *dp83640,
+ struct phy_txts *phy_txts)
+{
+ struct skb_shared_hwtstamps shhwtstamps;
+ struct sk_buff *skb;
+ u64 ns;
+
+ /* We must already have the skb that triggered this. */
+
+ skb = skb_dequeue(&dp83640->tx_queue);
+
+ if (!skb) {
+ pr_warning("dp83640: have timestamp but tx_queue empty\n");
+ return;
+ }
+ ns = phy2txts(phy_txts);
+ memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+ shhwtstamps.hwtstamp = ns_to_ktime(ns);
+ skb_complete_tx_timestamp(skb, &shhwtstamps);
+}
+
+static void decode_status_frame(struct dp83640_private *dp83640,
+ struct sk_buff *skb)
+{
+ struct phy_rxts *phy_rxts;
+ struct phy_txts *phy_txts;
+ u8 *ptr;
+ int len, size;
+ u16 ests, type;
+
+ ptr = skb->data + 2;
+
+ for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
+
+ type = *(u16 *)ptr;
+ ests = type & 0x0fff;
+ type = type & 0xf000;
+ len -= sizeof(type);
+ ptr += sizeof(type);
+
+ if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
+
+ phy_rxts = (struct phy_rxts *) ptr;
+ decode_rxts(dp83640, phy_rxts);
+ size = sizeof(*phy_rxts);
+
+ } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
+
+ phy_txts = (struct phy_txts *) ptr;
+ decode_txts(dp83640, phy_txts);
+ size = sizeof(*phy_txts);
+
+ } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
+
+ phy_txts = (struct phy_txts *) ptr;
+ decode_evnt(dp83640, phy_txts, ests);
+ size = sizeof(*phy_txts);
+
+ } else {
+ size = 0;
+ break;
+ }
+ ptr += size;
+ }
+}
+
+static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
+{
+ u16 *seqid;
+ u8 *msgtype, *data = skb_mac_header(skb);
+
+ /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
+ /* We assume that the IPv4 header has no options. */
+
+ switch (type) {
+ case PTP_CLASS_V1_IPV4:
+ msgtype = data + 42 + 32;
+ seqid = (u16 *)(data + 42 + 30);
+ break;
+ case PTP_CLASS_V1_IPV6:
+ msgtype = data + 62 + 32;
+ seqid = (u16 *)(data + 62 + 30);
+ break;
+ case PTP_CLASS_V2_IPV4:
+ msgtype = data + 42 + 0;
+ seqid = (u16 *)(data + 42 + 30);
+ break;
+ case PTP_CLASS_V2_IPV6:
+ msgtype = data + 62 + 0;
+ seqid = (u16 *)(data + 62 + 30);
+ break;
+ case PTP_CLASS_V2_L2:
+ msgtype = data + 14 + 0;
+ seqid = (u16 *)(data + 14 + 30);
+ break;
+ case PTP_CLASS_V2_VLAN:
+ msgtype = data + 18 + 0;
+ seqid = (u16 *)(data + 18 + 30);
+ break;
+ default:
+ return 0;
+ }
+
+ return ((*msgtype & 0xf) == rxts->msgtype && *seqid == rxts->seqid);
+}
+
+static struct dp83640_clock phyter_clock = {
+ .extreg_lock = __MUTEX_INITIALIZER(phyter_clock.extreg_lock),
+ .phylist = LIST_HEAD_INIT(phyter_clock.phylist),
+ .caps = {
+ .owner = THIS_MODULE,
+ .name = "dp83640 timer",
+ .max_adj = 1953124,
+ .n_alarm = 0,
+ .n_ext_ts = N_EXT_TS,
+ .n_per_out = 0,
+ .pps = 0,
+ .adjfreq = ptp_dp83640_adjfreq,
+ .adjtime = ptp_dp83640_adjtime,
+ .gettime = ptp_dp83640_gettime,
+ .settime = ptp_dp83640_settime,
+ .enable = ptp_dp83640_enable,
+ },
+};
+DEFINE_MUTEX(clock_lock); /* protects the one and only dp83640_clock */
+
+static int choose_this_phy(struct phy_device *phydev)
+{
+ if (chosen_phy == -1 && !phyter_clock.chosen)
+ return 1;
+
+ if (chosen_phy == phydev->addr)
+ return 1;
+
+ return 0;
+}
+
+static int dp83640_probe(struct phy_device *phydev)
+{
+ struct dp83640_private *dp83640;
+ int err = -ENOMEM, i;
+
+ if (strcmp(phydev->bus->id, mii_busid)) {
+ pr_err("phyter on bus %s but expected bus %s\n",
+ phydev->bus->id, mii_busid);
+ return -EINVAL;
+ }
+
+ if (phydev->addr == BROADCAST_ADDR)
+ return 0;
+
+ dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
+ if (!dp83640)
+ return err;
+
+ dp83640->phydev = phydev;
+ INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
+
+ INIT_LIST_HEAD(&dp83640->rxts);
+ INIT_LIST_HEAD(&dp83640->rxpool);
+ for (i = 0; i < MAX_RXTS; i++)
+ list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
+
+ phydev->priv = dp83640;
+
+ spin_lock_init(&dp83640->rx_lock);
+ skb_queue_head_init(&dp83640->rx_queue);
+ skb_queue_head_init(&dp83640->tx_queue);
+
+ mutex_lock(&clock_lock);
+
+ dp83640->clock = &phyter_clock;
+
+ if (choose_this_phy(phydev)) {
+ phyter_clock.chosen = dp83640;
+ phyter_clock.ptp_clock = ptp_clock_register(&phyter_clock.caps);
+ if (IS_ERR(phyter_clock.ptp_clock)) {
+ err = PTR_ERR(phyter_clock.ptp_clock);
+ goto no_register;
+ }
+ } else
+ list_add_tail(&dp83640->list, &phyter_clock.phylist);
+
+ if (phyter_clock.chosen && !list_empty(&phyter_clock.phylist))
+ recalibrate(&phyter_clock);
+ else
+ enable_broadcast(dp83640->phydev, phyter_clock.page, 1);
+
+ mutex_unlock(&clock_lock);
+
+ return 0;
+
+no_register:
+ phyter_clock.chosen = NULL;
+ kfree(dp83640);
+ mutex_unlock(&clock_lock);
+ return err;
+}
+
+static void dp83640_remove(struct phy_device *phydev)
+{
+ struct list_head *this, *next;
+ struct dp83640_private *tmp, *dp83640 = phydev->priv;
+
+ enable_status_frames(phydev, false);
+ cancel_work_sync(&dp83640->ts_work);
+ mutex_lock(&clock_lock);
+
+ if (dp83640 == phyter_clock.chosen) {
+ ptp_clock_unregister(phyter_clock.ptp_clock);
+ phyter_clock.chosen = NULL;
+ } else {
+ list_for_each_safe(this, next, &phyter_clock.phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ if (tmp == dp83640) {
+ list_del_init(&tmp->list);
+ break;
+ }
+ }
+ }
+
+ mutex_unlock(&clock_lock);
+ kfree(dp83640);
+}
+
+static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+ struct hwtstamp_config cfg;
+ u16 txcfg0, rxcfg0;
+
+ if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+ return -EFAULT;
+
+ if (cfg.flags) /* reserved for future extensions */
+ return -EINVAL;
+
+ switch (cfg.tx_type) {
+ case HWTSTAMP_TX_OFF:
+ dp83640->hwts_tx_en = 0;
+ break;
+ case HWTSTAMP_TX_ON:
+ dp83640->hwts_tx_en = 1;
+ break;
+ default:
+ return -ERANGE;
+ }
+
+ switch (cfg.rx_filter) {
+ case HWTSTAMP_FILTER_NONE:
+ dp83640->hwts_rx_en = 0;
+ dp83640->layer = 0;
+ dp83640->version = 0;
+ break;
+ case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
+ case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+ case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+ dp83640->hwts_rx_en = 1;
+ dp83640->layer = LAYER4;
+ dp83640->version = 1;
+ break;
+ case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+ case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+ case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+ dp83640->hwts_rx_en = 1;
+ dp83640->layer = LAYER4;
+ dp83640->version = 2;
+ break;
+ case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+ case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+ case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+ dp83640->hwts_rx_en = 1;
+ dp83640->layer = LAYER2;
+ dp83640->version = 2;
+ break;
+ case HWTSTAMP_FILTER_PTP_V2_EVENT:
+ case HWTSTAMP_FILTER_PTP_V2_SYNC:
+ case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+ dp83640->hwts_rx_en = 1;
+ dp83640->layer = LAYER4|LAYER2;
+ dp83640->version = 2;
+ break;
+ default:
+ return -ERANGE;
+ }
+
+ txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
+ rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
+
+ if (dp83640->layer & LAYER2) {
+ txcfg0 |= TX_L2_EN;
+ rxcfg0 |= RX_L2_EN;
+ }
+ if (dp83640->layer & LAYER4) {
+ txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
+ rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
+ }
+
+ if (dp83640->hwts_tx_en)
+ txcfg0 |= TX_TS_EN;
+
+ if (dp83640->hwts_rx_en)
+ rxcfg0 |= RX_TS_EN;
+
+ mutex_lock(&dp83640->clock->extreg_lock);
+
+ if (dp83640->hwts_tx_en || dp83640->hwts_rx_en) {
+ enable_status_frames(phydev, true);
+ ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
+ }
+
+ ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
+ ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
+
+ mutex_unlock(&dp83640->clock->extreg_lock);
+
+ return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+}
+
+static void rx_timestamp_work(struct work_struct *work)
+{
+ struct dp83640_private *dp83640 =
+ container_of(work, struct dp83640_private, ts_work);
+ struct list_head *this, *next;
+ struct rxts *rxts;
+ struct skb_shared_hwtstamps *shhwtstamps;
+ struct sk_buff *skb;
+ unsigned int type;
+ unsigned long flags;
+
+ /* Deliver each deferred packet, with or without a time stamp. */
+
+ while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
+ type = SKB_PTP_TYPE(skb);
+ spin_lock_irqsave(&dp83640->rx_lock, flags);
+ list_for_each_safe(this, next, &dp83640->rxts) {
+ rxts = list_entry(this, struct rxts, list);
+ if (match(skb, type, rxts)) {
+ shhwtstamps = skb_hwtstamps(skb);
+ memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+ shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
+ list_del_init(&rxts->list);
+ list_add(&rxts->list, &dp83640->rxpool);
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&dp83640->rx_lock, flags);
+ netif_rx(skb);
+ }
+
+ /* Clear out expired time stamps. */
+
+ spin_lock_irqsave(&dp83640->rx_lock, flags);
+ prune_rx_ts(dp83640);
+ spin_unlock_irqrestore(&dp83640->rx_lock, flags);
+}
+
+static bool dp83640_rxtstamp(struct phy_device *phydev,
+ struct sk_buff *skb, int type)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+
+ if (!dp83640->hwts_rx_en)
+ return false;
+
+ if (is_status_frame(skb, type)) {
+ decode_status_frame(dp83640, skb);
+ /* Let the stack drop this frame. */
+ return false;
+ }
+
+ SKB_PTP_TYPE(skb) = type;
+ skb_queue_tail(&dp83640->rx_queue, skb);
+ schedule_work(&dp83640->ts_work);
+
+ return true;
+}
+
+static void dp83640_txtstamp(struct phy_device *phydev,
+ struct sk_buff *skb, int type)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+
+ if (!dp83640->hwts_tx_en) {
+ kfree_skb(skb);
+ return;
+ }
+ skb_queue_tail(&dp83640->tx_queue, skb);
+ schedule_work(&dp83640->ts_work);
+}
+
+static struct phy_driver dp83640_driver = {
+ .phy_id = DP83640_PHY_ID,
+ .phy_id_mask = 0xfffffff0,
+ .name = "NatSemi DP83640",
+ .features = PHY_BASIC_FEATURES,
+ .flags = 0,
+ .probe = dp83640_probe,
+ .remove = dp83640_remove,
+ .config_aneg = genphy_config_aneg,
+ .read_status = genphy_read_status,
+ .hwtstamp = dp83640_hwtstamp,
+ .rxtstamp = dp83640_rxtstamp,
+ .txtstamp = dp83640_txtstamp,
+ .driver = {.owner = THIS_MODULE,}
+};
+
+static int __init dp83640_init(void)
+{
+ return phy_driver_register(&dp83640_driver);
+}
+
+static void __exit dp83640_exit(void)
+{
+ phy_driver_unregister(&dp83640_driver);
+}
+
+MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
+MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
+MODULE_LICENSE("GPL");
+
+module_init(dp83640_init);
+module_exit(dp83640_exit);
+
+static struct mdio_device_id dp83640_tbl[] = {
+ { DP83640_PHY_ID, 0xfffffff0 },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h
new file mode 100644
index 0000000..e7fe411
--- /dev/null
+++ b/drivers/net/phy/dp83640_reg.h
@@ -0,0 +1,267 @@
+/* dp83640_reg.h
+ * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011
+ */
+#ifndef HAVE_DP83640_REGISTERS
+#define HAVE_DP83640_REGISTERS
+
+#define PAGE0 0x0000
+#define PHYCR2 0x001c /* PHY Control Register 2 */
+
+#define PAGE4 0x0004
+#define PTP_CTL 0x0014 /* PTP Control Register */
+#define PTP_TDR 0x0015 /* PTP Time Data Register */
+#define PTP_STS 0x0016 /* PTP Status Register */
+#define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
+#define PTP_RATEL 0x0018 /* PTP Rate Low Register */
+#define PTP_RATEH 0x0019 /* PTP Rate High Register */
+#define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
+#define PTP_WRCKSUM 0x001b /* PTP Write Checksum */
+#define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
+#define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
+#define PTP_ESTS 0x001e /* PTP Event Status Register */
+#define PTP_EDATA 0x001f /* PTP Event Data Register */
+
+#define PAGE5 0x0005
+#define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
+#define PTP_EVNT 0x0015 /* PTP Event Configuration Register */
+#define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */
+#define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */
+#define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
+#define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */
+#define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */
+#define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */
+#define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */
+#define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */
+#define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
+#define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
+
+#define PAGE6 0x0006
+#define PTP_COC 0x0014 /* PTP Clock Output Control Register */
+#define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
+#define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
+#define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
+#define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */
+#define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */
+#define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */
+#define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
+#define PTP_ETR 0x001c /* PTP Ethernet Type Register */
+#define PTP_OFF 0x001d /* PTP Offset Register */
+#define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */
+#define PTP_RXHASH 0x001f /* PTP Receive Hash Register */
+
+/* Bit definitions for the PHYCR2 register */
+#define BC_WRITE (1<<11) /* Broadcast Write Enable */
+
+/* Bit definitions for the PTP_CTL register */
+#define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
+#define TRIG_SEL_MASK (0x7)
+#define TRIG_DIS (1<<9) /* Disable PTP Trigger */
+#define TRIG_EN (1<<8) /* Enable PTP Trigger */
+#define TRIG_READ (1<<7) /* Read PTP Trigger */
+#define TRIG_LOAD (1<<6) /* Load PTP Trigger */
+#define PTP_RD_CLK (1<<5) /* Read PTP Clock */
+#define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */
+#define PTP_STEP_CLK (1<<3) /* Step PTP Clock */
+#define PTP_ENABLE (1<<2) /* Enable PTP Clock */
+#define PTP_DISABLE (1<<1) /* Disable PTP Clock */
+#define PTP_RESET (1<<0) /* Reset PTP Clock */
+
+/* Bit definitions for the PTP_STS register */
+#define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */
+#define RXTS_RDY (1<<10) /* Receive Timestamp Ready */
+#define TRIG_DONE (1<<9) /* PTP Trigger Done */
+#define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */
+#define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
+#define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
+#define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
+#define EVENT_IE (1<<0) /* Event Interrupt Enable */
+
+/* Bit definitions for the PTP_TSTS register */
+#define TRIG7_ERROR (1<<15) /* Trigger 7 Error */
+#define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
+#define TRIG6_ERROR (1<<13) /* Trigger 6 Error */
+#define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */
+#define TRIG5_ERROR (1<<11) /* Trigger 5 Error */
+#define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */
+#define TRIG4_ERROR (1<<9) /* Trigger 4 Error */
+#define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */
+#define TRIG3_ERROR (1<<7) /* Trigger 3 Error */
+#define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */
+#define TRIG2_ERROR (1<<5) /* Trigger 2 Error */
+#define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */
+#define TRIG1_ERROR (1<<3) /* Trigger 1 Error */
+#define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */
+#define TRIG0_ERROR (1<<1) /* Trigger 0 Error */
+#define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
+
+/* Bit definitions for the PTP_RATEH register */
+#define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */
+#define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */
+#define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
+#define PTP_RATE_HI_MASK (0x3ff)
+
+/* Bit definitions for the PTP_ESTS register */
+#define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */
+#define EVNTS_MISSED_MASK (0x7)
+#define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */
+#define EVNT_TS_LEN_MASK (0x3)
+#define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */
+#define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */
+#define EVNT_NUM_MASK (0x7)
+#define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */
+#define EVENT_DET (1<<0) /* PTP Event Detected */
+
+/* Bit definitions for the PTP_EDATA register */
+#define E7_RISE (1<<15) /* Indicates direction of Event 7 */
+#define E7_DET (1<<14) /* Indicates Event 7 detected */
+#define E6_RISE (1<<13) /* Indicates direction of Event 6 */
+#define E6_DET (1<<12) /* Indicates Event 6 detected */
+#define E5_RISE (1<<11) /* Indicates direction of Event 5 */
+#define E5_DET (1<<10) /* Indicates Event 5 detected */
+#define E4_RISE (1<<9) /* Indicates direction of Event 4 */
+#define E4_DET (1<<8) /* Indicates Event 4 detected */
+#define E3_RISE (1<<7) /* Indicates direction of Event 3 */
+#define E3_DET (1<<6) /* Indicates Event 3 detected */
+#define E2_RISE (1<<5) /* Indicates direction of Event 2 */
+#define E2_DET (1<<4) /* Indicates Event 2 detected */
+#define E1_RISE (1<<3) /* Indicates direction of Event 1 */
+#define E1_DET (1<<2) /* Indicates Event 1 detected */
+#define E0_RISE (1<<1) /* Indicates direction of Event 0 */
+#define E0_DET (1<<0) /* Indicates Event 0 detected */
+
+/* Bit definitions for the PTP_TRIG register */
+#define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */
+#define TRIG_PER (1<<14) /* generate a periodic signal */
+#define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */
+#define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */
+#define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */
+#define TRIG_GPIO_MASK (0xf)
+#define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
+#define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */
+#define TRIG_CSEL_MASK (0x7)
+#define TRIG_WR (1<<0) /* Trigger Configuration Write */
+
+/* Bit definitions for the PTP_EVNT register */
+#define EVNT_RISE (1<<14) /* Event Rise Detect Enable */
+#define EVNT_FALL (1<<13) /* Event Fall Detect Enable */
+#define EVNT_SINGLE (1<<12) /* enable single event capture operation */
+#define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */
+#define EVNT_GPIO_MASK (0xf)
+#define EVNT_SEL_SHIFT (1) /* Event Select */
+#define EVNT_SEL_MASK (0x7)
+#define EVNT_WR (1<<0) /* Event Configuration Write */
+
+/* Bit definitions for the PTP_TXCFG0 register */
+#define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */
+#define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */
+#define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */
+#define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */
+#define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */
+#define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */
+#define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */
+#define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
+#define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
+#define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
+#define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
+#define TX_PTP_VER_MASK (0xf)
+#define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
+
+/* Bit definitions for the PTP_TXCFG1 register */
+#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
+#define BYTE0_MASK_MASK (0xff)
+#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
+#define BYTE0_DATA_MASK (0xff)
+
+/* Bit definitions for the PSF_CFG0 register */
+#define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */
+#define MAC_SRC_ADD_MASK (0x3)
+#define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */
+#define MIN_PRE_MASK (0x7)
+#define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */
+#define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */
+#define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */
+#define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */
+#define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */
+#define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */
+#define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */
+#define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
+
+/* Bit definitions for the PTP_RXCFG0 register */
+#define DOMAIN_EN (1<<15) /* Domain Match Enable */
+#define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */
+#define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */
+#define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */
+#define RX_SLAVE (1<<11) /* Receive Slave Only */
+#define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */
+#define IP1588_EN_MASK (0xf)
+#define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
+#define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
+#define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
+#define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
+#define RX_PTP_VER_MASK (0xf)
+#define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
+
+/* Bit definitions for the PTP_RXCFG1 register */
+#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
+#define BYTE0_MASK_MASK (0xff)
+#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
+#define BYTE0_DATA_MASK (0xff)
+
+/* Bit definitions for the PTP_RXCFG3 register */
+#define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */
+#define TS_MIN_IFG_MASK (0xf)
+#define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */
+#define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */
+#define TS_APPEND (1<<9) /* Append Timestamp for L2 */
+#define TS_INSERT (1<<8) /* Enable Timestamp Insertion */
+#define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */
+#define PTP_DOMAIN_MASK (0xff)
+
+/* Bit definitions for the PTP_RXCFG4 register */
+#define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */
+#define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */
+#define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */
+#define TS_SEC_LEN_MASK (0x3)
+#define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */
+#define RXTS_NS_OFF_MASK (0x3f)
+#define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */
+#define RXTS_SEC_OFF_MASK (0x3f)
+
+/* Bit definitions for the PTP_COC register */
+#define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
+#define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
+#define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
+#define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
+#define PTP_CLKDIV_MASK (0xff)
+
+/* Bit definitions for the PSF_CFG1 register */
+#define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */
+#define PTPRESERVED_MASK (0xf)
+#define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */
+#define VERSIONPTP_MASK (0xf)
+#define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */
+#define TRANSPORT_SPECIFIC_MASK (0xf)
+#define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */
+#define MESSAGETYPE_MASK (0xf)
+
+/* Bit definitions for the PTP_SFDCFG register */
+#define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */
+#define TX_SFD_GPIO_MASK (0xf)
+#define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */
+#define RX_SFD_GPIO_MASK (0xf)
+
+/* Bit definitions for the PTP_INTCTL register */
+#define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */
+#define PTP_INT_GPIO_MASK (0xf)
+
+/* Bit definitions for the PTP_CLKSRC register */
+#define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */
+#define CLK_SRC_MASK (0x3)
+#define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
+#define CLK_SRC_PER_MASK (0x7f)
+
+/* Bit definitions for the PTP_OFF register */
+#define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */
+#define PTP_OFFSET_MASK (0xff)
+
+#endif
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index fcfafd0..68d7201 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -53,4 +53,23 @@ config PTP_1588_CLOCK_IXP46X
To compile this driver as a module, choose M here: the module
will be called ptp_ixp46x.
+comment "Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks."
+ depends on PTP_1588_CLOCK && (PHYLIB=n || NETWORK_PHY_TIMESTAMPING=n)
+
+config DP83640_PHY
+ tristate "Driver for the National Semiconductor DP83640 PHYTER"
+ depends on PTP_1588_CLOCK
+ depends on NETWORK_PHY_TIMESTAMPING
+ depends on PHYLIB
+ ---help---
+ Supports the DP83640 PHYTER with IEEE 1588 features.
+
+ This driver adds support for using the DP83640 as a PTP
+ clock. This clock is only useful if your PTP programs are
+ getting hardware time stamps on the PTP Ethernet packets
+ using the SO_TIMESTAMPING API.
+
+ In order for this to work, your MAC driver must also
+ implement the skb_tx_timetamp() function.
+
endmenu
--
1.7.0.4
^ permalink raw reply related
* [PATCH V12 3/4] ptp: Added a clock driver for the IXP46x.
From: Richard Cochran @ 2011-02-28 7:58 UTC (permalink / raw)
To: linux-kernel
Cc: Thomas Gleixner, Rodolfo Giometti, Arnd Bergmann, Peter Zijlstra,
linux-api, devicetree-discuss, Russell King, Paul Mackerras,
John Stultz, linux-arm-kernel, netdev, Mike Frysinger,
Christoph Lameter, linuxppc-dev, David Miller, Alan Cox,
Krzysztof Halasa
In-Reply-To: <cover.1298878618.git.richard.cochran@omicron.at>
This patch adds a driver for the hardware time stamping unit found on the
IXP465. The basic clock operations and an external trigger are implemented.
Signed-off-by: Richard Cochran <richard.cochran@omicron.at>
Acked-by: John Stultz <johnstul@us.ibm.com>
---
arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | 78 ++++++
drivers/net/arm/ixp4xx_eth.c | 192 ++++++++++++++-
drivers/ptp/Kconfig | 13 +
drivers/ptp/Makefile | 1 +
drivers/ptp/ptp_ixp46x.c | 332 +++++++++++++++++++++++++
5 files changed, 613 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
create mode 100644 drivers/ptp/ptp_ixp46x.c
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 0000000..292d55e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF0000029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+ u32 ch_control; /* 0x40 Time Synchronization Channel Control */
+ u32 ch_event; /* 0x44 Time Synchronization Channel Event */
+ u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
+ u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
+ u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
+ u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
+ u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+ u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+ u32 control; /* 0x00 Time Sync Control Register */
+ u32 event; /* 0x04 Time Sync Event Register */
+ u32 addend; /* 0x08 Time Sync Addend Register */
+ u32 accum; /* 0x0C Time Sync Accumulator Register */
+ u32 test; /* 0x10 Time Sync Test Register */
+ u32 unused; /* 0x14 */
+ u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+ u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+ u32 systime_lo; /* 0x20 SystemTime_Low Register */
+ u32 systime_hi; /* 0x24 SystemTime_High Register */
+ u32 trgt_lo; /* 0x28 TargetTime_Low Register */
+ u32 trgt_hi; /* 0x2C TargetTime_High Register */
+ u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
+ u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
+ u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
+ u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
+
+ struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 9eb9b98..fa08c17 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
#include <linux/etherdevice.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/net_tstamp.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
+#include <linux/ptp_classify.h>
#include <linux/slab.h>
+#include <mach/ixp46x_ts.h>
#include <mach/npe.h>
#include <mach/qmgr.h>
@@ -67,6 +70,10 @@
#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
#define TXDONE_QUEUE 31
+#define PTP_SLAVE_MODE 1
+#define PTP_MASTER_MODE 2
+#define PORT2CHANNEL(p) NPE_ID(p->id)
+
/* TX Control Registers */
#define TX_CNTRL0_TX_EN 0x01
#define TX_CNTRL0_HALFDUPLEX 0x02
@@ -171,6 +178,8 @@ struct port {
int id; /* logical port ID */
int speed, duplex;
u8 firmware[4];
+ int hwts_tx_en;
+ int hwts_rx_en;
};
/* NPE message structure */
@@ -246,6 +255,169 @@ static int ports_open;
static struct port *npe_port_tab[MAX_NPES];
static struct dma_pool *dma_pool;
+static struct sock_filter ptp_filter[] = {
+ PTP_FILTER
+};
+
+static int match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seq)
+{
+ unsigned int type;
+ u16 *hi, *id;
+ u8 *lo, *data = skb->data;
+
+ type = sk_run_filter(skb, ptp_filter);
+
+ if (PTP_CLASS_V1_IPV4 == type) {
+
+ id = (u16 *)(data + 42 + 30);
+ hi = (u16 *)(data + 42 + 22);
+ lo = data + 42 + 24;
+
+ return (uid_hi == *hi &&
+ 0 == memcmp(&uid_lo, lo, sizeof(uid_lo)) &&
+ seq == *id);
+ }
+
+ return 0;
+}
+
+static void do_rx_timestamp(struct port *port, struct sk_buff *skb)
+{
+ struct skb_shared_hwtstamps *shhwtstamps;
+ struct ixp46x_ts_regs *regs;
+ u64 ns;
+ u32 ch, hi, lo, val;
+ u16 uid, seq;
+
+ if (!port->hwts_rx_en)
+ return;
+
+ ch = PORT2CHANNEL(port);
+
+ regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+ val = __raw_readl(®s->channel[ch].ch_event);
+
+ if (!(val & RX_SNAPSHOT_LOCKED))
+ return;
+
+ lo = __raw_readl(®s->channel[ch].src_uuid_lo);
+ hi = __raw_readl(®s->channel[ch].src_uuid_hi);
+
+ uid = hi & 0xffff;
+ seq = (hi >> 16) & 0xffff;
+
+ if (!match(skb, htons(uid), htonl(lo), htons(seq)))
+ goto out;
+
+ lo = __raw_readl(®s->channel[ch].rx_snap_lo);
+ hi = __raw_readl(®s->channel[ch].rx_snap_hi);
+ ns = ((u64) hi) << 32;
+ ns |= lo;
+ ns <<= TICKS_NS_SHIFT;
+
+ shhwtstamps = skb_hwtstamps(skb);
+ memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+ shhwtstamps->hwtstamp = ns_to_ktime(ns);
+out:
+ __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
+}
+
+static void do_tx_timestamp(struct port *port, struct sk_buff *skb)
+{
+ struct skb_shared_hwtstamps shhwtstamps;
+ struct ixp46x_ts_regs *regs;
+ struct skb_shared_info *shtx;
+ u64 ns;
+ u32 ch, cnt, hi, lo, val;
+
+ shtx = skb_shinfo(skb);
+ if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
+ shtx->tx_flags |= SKBTX_IN_PROGRESS;
+ else
+ return;
+
+ ch = PORT2CHANNEL(port);
+
+ regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+ /*
+ * This really stinks, but we have to poll for the Tx time stamp.
+ * Usually, the time stamp is ready after 4 to 6 microseconds.
+ */
+ for (cnt = 0; cnt < 100; cnt++) {
+ val = __raw_readl(®s->channel[ch].ch_event);
+ if (val & TX_SNAPSHOT_LOCKED)
+ break;
+ udelay(1);
+ }
+ if (!(val & TX_SNAPSHOT_LOCKED)) {
+ shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
+ return;
+ }
+
+ lo = __raw_readl(®s->channel[ch].tx_snap_lo);
+ hi = __raw_readl(®s->channel[ch].tx_snap_hi);
+ ns = ((u64) hi) << 32;
+ ns |= lo;
+ ns <<= TICKS_NS_SHIFT;
+
+ memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+ shhwtstamps.hwtstamp = ns_to_ktime(ns);
+ skb_tstamp_tx(skb, &shhwtstamps);
+
+ __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
+}
+
+static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
+{
+ struct hwtstamp_config cfg;
+ struct ixp46x_ts_regs *regs;
+ struct port *port = netdev_priv(netdev);
+ int ch;
+
+ if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+ return -EFAULT;
+
+ if (cfg.flags) /* reserved for future extensions */
+ return -EINVAL;
+
+ ch = PORT2CHANNEL(port);
+ regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+ switch (cfg.tx_type) {
+ case HWTSTAMP_TX_OFF:
+ port->hwts_tx_en = 0;
+ break;
+ case HWTSTAMP_TX_ON:
+ port->hwts_tx_en = 1;
+ break;
+ default:
+ return -ERANGE;
+ }
+
+ switch (cfg.rx_filter) {
+ case HWTSTAMP_FILTER_NONE:
+ port->hwts_rx_en = 0;
+ break;
+ case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+ port->hwts_rx_en = PTP_SLAVE_MODE;
+ __raw_writel(0, ®s->channel[ch].ch_control);
+ break;
+ case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+ port->hwts_rx_en = PTP_MASTER_MODE;
+ __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control);
+ break;
+ default:
+ return -ERANGE;
+ }
+
+ /* Clear out any old time stamps. */
+ __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
+ ®s->channel[ch].ch_event);
+
+ return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+}
static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
int write, u16 cmd)
@@ -573,6 +745,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
debug_pkt(dev, "eth_poll", skb->data, skb->len);
+ do_rx_timestamp(port, skb);
skb->protocol = eth_type_trans(skb, dev);
dev->stats.rx_packets++;
dev->stats.rx_bytes += skb->len;
@@ -679,14 +852,12 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
return NETDEV_TX_OK;
}
memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
- dev_kfree_skb(skb);
#endif
phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
if (dma_mapping_error(&dev->dev, phys)) {
-#ifdef __ARMEB__
dev_kfree_skb(skb);
-#else
+#ifndef __ARMEB__
kfree(mem);
#endif
dev->stats.tx_dropped++;
@@ -728,6 +899,13 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
#if DEBUG_TX
printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
#endif
+
+ do_tx_timestamp(port, skb);
+ skb_tx_timestamp(skb);
+
+#ifndef __ARMEB__
+ dev_kfree_skb(skb);
+#endif
return NETDEV_TX_OK;
}
@@ -783,6 +961,9 @@ static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
if (!netif_running(dev))
return -EINVAL;
+ if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP)
+ return hwtstamp_ioctl(dev, req, cmd);
+
return phy_mii_ioctl(port->phydev, req, cmd);
}
@@ -1171,6 +1352,11 @@ static int __devinit eth_init_one(struct platform_device *pdev)
char phy_id[MII_BUS_ID_SIZE + 3];
int err;
+ if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
+ pr_err("ixp4xx_eth: bad ptp filter\n");
+ return -EINVAL;
+ }
+
if (!(dev = alloc_etherdev(sizeof(struct port))))
return -ENOMEM;
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index 12eb844..fcfafd0 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -40,4 +40,17 @@ config PTP_1588_CLOCK_GIANFAR
To compile this driver as a module, choose M here: the module
will be called gianfar_ptp.
+config PTP_1588_CLOCK_IXP46X
+ tristate "Intel IXP46x as PTP clock"
+ depends on PTP_1588_CLOCK
+ depends on IXP4XX_ETH
+ help
+ This driver adds support for using the IXP46X as a PTP
+ clock. This clock is only useful if your PTP programs are
+ getting hardware time stamps on the PTP Ethernet packets
+ using the SO_TIMESTAMPING API.
+
+ To compile this driver as a module, choose M here: the module
+ will be called ptp_ixp46x.
+
endmenu
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
index 480e2af..f6933e8 100644
--- a/drivers/ptp/Makefile
+++ b/drivers/ptp/Makefile
@@ -4,3 +4,4 @@
ptp-y := ptp_clock.o ptp_chardev.o ptp_sysfs.o
obj-$(CONFIG_PTP_1588_CLOCK) += ptp.o
+obj-$(CONFIG_PTP_1588_CLOCK_IXP46X) += ptp_ixp46x.o
diff --git a/drivers/ptp/ptp_ixp46x.c b/drivers/ptp/ptp_ixp46x.c
new file mode 100644
index 0000000..e78545f
--- /dev/null
+++ b/drivers/ptp/ptp_ixp46x.c
@@ -0,0 +1,332 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/ptp_clock_kernel.h>
+#include <mach/ixp46x_ts.h>
+
+#define DRIVER "ptp_ixp46x"
+#define N_EXT_TS 2
+#define MASTER_GPIO 8
+#define MASTER_IRQ 25
+#define SLAVE_GPIO 7
+#define SLAVE_IRQ 24
+
+struct ixp_clock {
+ struct ixp46x_ts_regs *regs;
+ struct ptp_clock *ptp_clock;
+ struct ptp_clock_info caps;
+ int exts0_enabled;
+ int exts1_enabled;
+};
+
+DEFINE_SPINLOCK(register_lock);
+
+/*
+ * Register access functions
+ */
+
+static u64 sys_time_read(struct ixp46x_ts_regs *regs)
+{
+ u64 ns;
+ u32 lo, hi;
+
+ lo = __raw_readl(®s->systime_lo);
+ hi = __raw_readl(®s->systime_hi);
+
+ ns = ((u64) hi) << 32;
+ ns |= lo;
+ ns <<= TICKS_NS_SHIFT;
+
+ return ns;
+}
+
+static void sys_time_write(struct ixp46x_ts_regs *regs, u64 ns)
+{
+ u32 hi, lo;
+
+ ns >>= TICKS_NS_SHIFT;
+ hi = ns >> 32;
+ lo = ns & 0xffffffff;
+
+ __raw_writel(lo, ®s->systime_lo);
+ __raw_writel(hi, ®s->systime_hi);
+}
+
+/*
+ * Interrupt service routine
+ */
+
+static irqreturn_t isr(int irq, void *priv)
+{
+ struct ixp_clock *ixp_clock = priv;
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+ struct ptp_clock_event event;
+ u32 ack = 0, lo, hi, val;
+
+ val = __raw_readl(®s->event);
+
+ if (val & TSER_SNS) {
+ ack |= TSER_SNS;
+ if (ixp_clock->exts0_enabled) {
+ hi = __raw_readl(®s->asms_hi);
+ lo = __raw_readl(®s->asms_lo);
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 0;
+ event.timestamp = ((u64) hi) << 32;
+ event.timestamp |= lo;
+ event.timestamp <<= TICKS_NS_SHIFT;
+ ptp_clock_event(ixp_clock->ptp_clock, &event);
+ }
+ }
+
+ if (val & TSER_SNM) {
+ ack |= TSER_SNM;
+ if (ixp_clock->exts1_enabled) {
+ hi = __raw_readl(®s->amms_hi);
+ lo = __raw_readl(®s->amms_lo);
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 1;
+ event.timestamp = ((u64) hi) << 32;
+ event.timestamp |= lo;
+ event.timestamp <<= TICKS_NS_SHIFT;
+ ptp_clock_event(ixp_clock->ptp_clock, &event);
+ }
+ }
+
+ if (val & TTIPEND)
+ ack |= TTIPEND; /* this bit seems to be always set */
+
+ if (ack) {
+ __raw_writel(ack, ®s->event);
+ return IRQ_HANDLED;
+ } else
+ return IRQ_NONE;
+}
+
+/*
+ * PTP clock operations
+ */
+
+static int ptp_ixp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+{
+ u64 adj;
+ u32 diff, addend;
+ int neg_adj = 0;
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+
+ if (ppb < 0) {
+ neg_adj = 1;
+ ppb = -ppb;
+ }
+ addend = DEFAULT_ADDEND;
+ adj = addend;
+ adj *= ppb;
+ diff = div_u64(adj, 1000000000ULL);
+
+ addend = neg_adj ? addend - diff : addend + diff;
+
+ __raw_writel(addend, ®s->addend);
+
+ return 0;
+}
+
+static int ptp_ixp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+ s64 now;
+ unsigned long flags;
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+
+ spin_lock_irqsave(®ister_lock, flags);
+
+ now = sys_time_read(regs);
+ now += delta;
+ sys_time_write(regs, now);
+
+ spin_unlock_irqrestore(®ister_lock, flags);
+
+ return 0;
+}
+
+static int ptp_ixp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
+{
+ u64 ns;
+ u32 remainder;
+ unsigned long flags;
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+
+ spin_lock_irqsave(®ister_lock, flags);
+
+ ns = sys_time_read(regs);
+
+ spin_unlock_irqrestore(®ister_lock, flags);
+
+ ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+ ts->tv_nsec = remainder;
+ return 0;
+}
+
+static int ptp_ixp_settime(struct ptp_clock_info *ptp,
+ const struct timespec *ts)
+{
+ u64 ns;
+ unsigned long flags;
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+
+ ns = ts->tv_sec * 1000000000ULL;
+ ns += ts->tv_nsec;
+
+ spin_lock_irqsave(®ister_lock, flags);
+
+ sys_time_write(regs, ns);
+
+ spin_unlock_irqrestore(®ister_lock, flags);
+
+ return 0;
+}
+
+static int ptp_ixp_enable(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *rq, int on)
+{
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+
+ switch (rq->type) {
+ case PTP_CLK_REQ_EXTTS:
+ switch (rq->extts.index) {
+ case 0:
+ ixp_clock->exts0_enabled = on ? 1 : 0;
+ break;
+ case 1:
+ ixp_clock->exts1_enabled = on ? 1 : 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_ixp_caps = {
+ .owner = THIS_MODULE,
+ .name = "IXP46X timer",
+ .max_adj = 66666655,
+ .n_ext_ts = N_EXT_TS,
+ .pps = 0,
+ .adjfreq = ptp_ixp_adjfreq,
+ .adjtime = ptp_ixp_adjtime,
+ .gettime = ptp_ixp_gettime,
+ .settime = ptp_ixp_settime,
+ .enable = ptp_ixp_enable,
+};
+
+/* module operations */
+
+static struct ixp_clock ixp_clock;
+
+static int setup_interrupt(int gpio)
+{
+ int irq;
+
+ gpio_line_config(gpio, IXP4XX_GPIO_IN);
+
+ irq = gpio_to_irq(gpio);
+
+ if (NO_IRQ == irq)
+ return NO_IRQ;
+
+ if (set_irq_type(irq, IRQF_TRIGGER_FALLING)) {
+ pr_err("cannot set trigger type for irq %d\n", irq);
+ return NO_IRQ;
+ }
+
+ if (request_irq(irq, isr, 0, DRIVER, &ixp_clock)) {
+ pr_err("request_irq failed for irq %d\n", irq);
+ return NO_IRQ;
+ }
+
+ return irq;
+}
+
+static void __exit ptp_ixp_exit(void)
+{
+ free_irq(MASTER_IRQ, &ixp_clock);
+ free_irq(SLAVE_IRQ, &ixp_clock);
+ ptp_clock_unregister(ixp_clock.ptp_clock);
+}
+
+static int __init ptp_ixp_init(void)
+{
+ if (!cpu_is_ixp46x())
+ return -ENODEV;
+
+ ixp_clock.regs =
+ (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+ ixp_clock.caps = ptp_ixp_caps;
+
+ ixp_clock.ptp_clock = ptp_clock_register(&ixp_clock.caps);
+
+ if (IS_ERR(ixp_clock.ptp_clock))
+ return PTR_ERR(ixp_clock.ptp_clock);
+
+ __raw_writel(DEFAULT_ADDEND, &ixp_clock.regs->addend);
+ __raw_writel(1, &ixp_clock.regs->trgt_lo);
+ __raw_writel(0, &ixp_clock.regs->trgt_hi);
+ __raw_writel(TTIPEND, &ixp_clock.regs->event);
+
+ if (MASTER_IRQ != setup_interrupt(MASTER_GPIO)) {
+ pr_err("failed to setup gpio %d as irq\n", MASTER_GPIO);
+ goto no_master;
+ }
+ if (SLAVE_IRQ != setup_interrupt(SLAVE_GPIO)) {
+ pr_err("failed to setup gpio %d as irq\n", SLAVE_GPIO);
+ goto no_slave;
+ }
+
+ return 0;
+no_slave:
+ free_irq(MASTER_IRQ, &ixp_clock);
+no_master:
+ ptp_clock_unregister(ixp_clock.ptp_clock);
+ return -ENODEV;
+}
+
+module_init(ptp_ixp_init);
+module_exit(ptp_ixp_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
+MODULE_DESCRIPTION("PTP clock using the IXP46X timer");
+MODULE_LICENSE("GPL");
--
1.7.0.4
^ permalink raw reply related
* [PATCH V12 2/4] ptp: Added a clock that uses the eTSEC found on the MPC85xx.
From: Richard Cochran @ 2011-02-28 7:57 UTC (permalink / raw)
To: linux-kernel
Cc: Thomas Gleixner, Rodolfo Giometti, Arnd Bergmann, Peter Zijlstra,
linux-api, devicetree-discuss, Russell King, Paul Mackerras,
John Stultz, linux-arm-kernel, netdev, Mike Frysinger,
Christoph Lameter, linuxppc-dev, David Miller, Alan Cox,
Krzysztof Halasa
In-Reply-To: <cover.1298878618.git.richard.cochran@omicron.at>
The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps, one alarm, and the PPS callback.
Signed-off-by: Richard Cochran <richard.cochran@omicron.at>
---
.../devicetree/bindings/net/fsl-tsec-phy.txt | 54 ++
arch/powerpc/boot/dts/mpc8313erdb.dts | 13 +
arch/powerpc/boot/dts/mpc8572ds.dts | 13 +
arch/powerpc/boot/dts/p2020ds.dts | 13 +
arch/powerpc/boot/dts/p2020rdb.dts | 13 +
drivers/net/Makefile | 1 +
drivers/net/gianfar_ptp.c | 579 ++++++++++++++++++++
drivers/ptp/Kconfig | 13 +
8 files changed, 699 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/gianfar_ptp.c
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index edb7ae1..2c6be03 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -74,3 +74,57 @@ Example:
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - fsl,tclk-period Timer reference clock period in nanoseconds.
+ - fsl,tmr-prsc Prescaler, divides the output clock.
+ - fsl,tmr-add Frequency compensation value.
+ - fsl,tmr-fiper1 Fixed interval period pulse generator.
+ - fsl,tmr-fiper2 Fixed interval period pulse generator.
+ - fsl,max-adj Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClock microseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1 = 1000000 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <100>;
+ fsl,tmr-add = <0x999999A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <659999998>;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..502e17c 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,19 @@
sleep = <&pmc 0x00300000>;
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <100>;
+ fsl,tmr-add = <0x999999A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <659999998>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index cafc128..f6c04d2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -324,6 +324,19 @@
};
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <68 2 69 2 70 2 71 2>;
+ interrupt-parent = < &mpic >;
+ fsl,tclk-period = <5>;
+ fsl,tmr-prsc = <200>;
+ fsl,tmr-add = <0xAAAAAAAB>;
+ fsl,tmr-fiper1 = <0x3B9AC9FB>;
+ fsl,tmr-fiper2 = <0x3B9AC9FB>;
+ fsl,max-adj = <499999999>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 1101914..3956daf 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -336,6 +336,19 @@
phy_type = "ulpi";
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <68 2 69 2 70 2>;
+ interrupt-parent = < &mpic >;
+ fsl,tclk-period = <5>;
+ fsl,tmr-prsc = <200>;
+ fsl,tmr-add = <0xCCCCCCCD>;
+ fsl,tmr-fiper1 = <0x3B9AC9FB>;
+ fsl,tmr-fiper2 = <0x0001869B>;
+ fsl,max-adj = <249999999>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index da4cb0d..a6229cb 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -396,6 +396,19 @@
phy_type = "ulpi";
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <68 2 69 2 70 2>;
+ interrupt-parent = < &mpic >;
+ fsl,tclk-period = <5>;
+ fsl,tmr-prsc = <200>;
+ fsl,tmr-add = <0xCCCCCCCD>;
+ fsl,tmr-fiper1 = <0x3B9AC9FB>;
+ fsl,tmr-fiper2 = <0x0001869B>;
+ fsl,max-adj = <249999999>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b90738d..c303f5f 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_ATL2) += atlx/
obj-$(CONFIG_ATL1E) += atl1e/
obj-$(CONFIG_ATL1C) += atl1c/
obj-$(CONFIG_GIANFAR) += gianfar_driver.o
+obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
obj-$(CONFIG_TEHUTI) += tehuti.o
obj-$(CONFIG_ENIC) += enic/
obj-$(CONFIG_JME) += jme.o
diff --git a/drivers/net/gianfar_ptp.c b/drivers/net/gianfar_ptp.c
new file mode 100644
index 0000000..23d2eb5
--- /dev/null
+++ b/drivers/net/gianfar_ptp.c
@@ -0,0 +1,579 @@
+/*
+ * PTP 1588 clock using the eTSEC
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/device.h>
+#include <linux/hrtimer.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/timex.h>
+#include <linux/io.h>
+
+#include <linux/ptp_clock_kernel.h>
+
+#include "gianfar.h"
+
+/*
+ * gianfar ptp registers
+ * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
+ */
+struct gianfar_ptp_registers {
+ u32 tmr_ctrl; /* Timer control register */
+ u32 tmr_tevent; /* Timestamp event register */
+ u32 tmr_temask; /* Timer event mask register */
+ u32 tmr_pevent; /* Timestamp event register */
+ u32 tmr_pemask; /* Timer event mask register */
+ u32 tmr_stat; /* Timestamp status register */
+ u32 tmr_cnt_h; /* Timer counter high register */
+ u32 tmr_cnt_l; /* Timer counter low register */
+ u32 tmr_add; /* Timer drift compensation addend register */
+ u32 tmr_acc; /* Timer accumulator register */
+ u32 tmr_prsc; /* Timer prescale */
+ u8 res1[4];
+ u32 tmroff_h; /* Timer offset high */
+ u32 tmroff_l; /* Timer offset low */
+ u8 res2[8];
+ u32 tmr_alarm1_h; /* Timer alarm 1 high register */
+ u32 tmr_alarm1_l; /* Timer alarm 1 high register */
+ u32 tmr_alarm2_h; /* Timer alarm 2 high register */
+ u32 tmr_alarm2_l; /* Timer alarm 2 high register */
+ u8 res3[48];
+ u32 tmr_fiper1; /* Timer fixed period interval */
+ u32 tmr_fiper2; /* Timer fixed period interval */
+ u32 tmr_fiper3; /* Timer fixed period interval */
+ u8 res4[20];
+ u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
+};
+
+/* Bit definitions for the TMR_CTRL register */
+#define ALM1P (1<<31) /* Alarm1 output polarity */
+#define ALM2P (1<<30) /* Alarm2 output polarity */
+#define FS (1<<28) /* FIPER start indication */
+#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
+#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
+#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
+#define TCLK_PERIOD_MASK (0x3ff)
+#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
+#define FRD (1<<14) /* FIPER Realignment Disable */
+#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
+#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
+#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
+#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
+#define COPH (1<<7) /* Generated clock output phase. */
+#define CIPH (1<<6) /* External oscillator input clock phase */
+#define TMSR (1<<5) /* Timer soft reset. */
+#define BYP (1<<3) /* Bypass drift compensated clock */
+#define TE (1<<2) /* 1588 timer enable. */
+#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
+#define CKSEL_MASK (0x3)
+
+/* Bit definitions for the TMR_TEVENT register */
+#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
+#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
+#define ALM2 (1<<17) /* Current time = alarm time register 2 */
+#define ALM1 (1<<16) /* Current time = alarm time register 1 */
+#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
+#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
+#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
+
+/* Bit definitions for the TMR_TEMASK register */
+#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
+#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
+#define ALM2EN (1<<17) /* Timer ALM2 event enable */
+#define ALM1EN (1<<16) /* Timer ALM1 event enable */
+#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
+#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
+
+/* Bit definitions for the TMR_PEVENT register */
+#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
+#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
+#define RXP (1<<0) /* PTP frame has been received */
+
+/* Bit definitions for the TMR_PEMASK register */
+#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
+#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
+#define RXPEN (1<<0) /* Receive PTP packet event enable */
+
+/* Bit definitions for the TMR_STAT register */
+#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
+#define STAT_VEC_MASK (0x3f)
+
+/* Bit definitions for the TMR_PRSC register */
+#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
+#define PRSC_OCK_MASK (0xffff)
+
+
+#define DRIVER "gianfar_ptp"
+#define DEFAULT_CKSEL 1
+#define N_ALARM 1 /* first alarm is used internally to reset fipers */
+#define N_EXT_TS 2
+#define REG_SIZE sizeof(struct gianfar_ptp_registers)
+
+struct etsects {
+ struct gianfar_ptp_registers *regs;
+ spinlock_t lock; /* protects regs */
+ struct ptp_clock *clock;
+ struct ptp_clock_info caps;
+ struct resource *rsrc;
+ int irq;
+ u64 alarm_interval; /* for periodic alarm */
+ u64 alarm_value;
+ u32 tclk_period; /* nanoseconds */
+ u32 tmr_prsc;
+ u32 tmr_add;
+ u32 cksel;
+ u32 tmr_fiper1;
+ u32 tmr_fiper2;
+};
+
+/*
+ * Register access functions
+ */
+
+static u64 tmr_cnt_read(struct etsects *etsects)
+{
+ u64 ns;
+ u32 lo, hi;
+
+ lo = gfar_read(&etsects->regs->tmr_cnt_l);
+ hi = gfar_read(&etsects->regs->tmr_cnt_h);
+ ns = ((u64) hi) << 32;
+ ns |= lo;
+ return ns;
+}
+
+static void tmr_cnt_write(struct etsects *etsects, u64 ns)
+{
+ u32 hi = ns >> 32;
+ u32 lo = ns & 0xffffffff;
+
+ gfar_write(&etsects->regs->tmr_cnt_l, lo);
+ gfar_write(&etsects->regs->tmr_cnt_h, hi);
+}
+
+static void set_alarm(struct etsects *etsects)
+{
+ u64 ns;
+ u32 lo, hi;
+
+ ns = tmr_cnt_read(etsects) + 1500000000ULL;
+ ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
+ ns -= etsects->tclk_period;
+ hi = ns >> 32;
+ lo = ns & 0xffffffff;
+ gfar_write(&etsects->regs->tmr_alarm1_l, lo);
+ gfar_write(&etsects->regs->tmr_alarm1_h, hi);
+}
+
+static void set_fipers(struct etsects *etsects)
+{
+ u32 tmr_ctrl = gfar_read(&etsects->regs->tmr_ctrl);
+
+ gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl & (~TE));
+ gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
+ gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
+ gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+ set_alarm(etsects);
+ gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|TE);
+}
+
+/*
+ * Interrupt service routine
+ */
+
+static irqreturn_t isr(int irq, void *priv)
+{
+ struct etsects *etsects = priv;
+ struct ptp_clock_event event;
+ u64 ns;
+ u32 ack = 0, lo, hi, mask, val;
+
+ val = gfar_read(&etsects->regs->tmr_tevent);
+
+ if (val & ETS1) {
+ ack |= ETS1;
+ hi = gfar_read(&etsects->regs->tmr_etts1_h);
+ lo = gfar_read(&etsects->regs->tmr_etts1_l);
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 0;
+ event.timestamp = ((u64) hi) << 32;
+ event.timestamp |= lo;
+ ptp_clock_event(etsects->clock, &event);
+ }
+
+ if (val & ETS2) {
+ ack |= ETS2;
+ hi = gfar_read(&etsects->regs->tmr_etts2_h);
+ lo = gfar_read(&etsects->regs->tmr_etts2_l);
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 1;
+ event.timestamp = ((u64) hi) << 32;
+ event.timestamp |= lo;
+ ptp_clock_event(etsects->clock, &event);
+ }
+
+ if (val & ALM2) {
+ ack |= ALM2;
+ if (etsects->alarm_value) {
+ event.type = PTP_CLOCK_ALARM;
+ event.index = 0;
+ event.timestamp = etsects->alarm_value;
+ ptp_clock_event(etsects->clock, &event);
+ }
+ if (etsects->alarm_interval) {
+ ns = etsects->alarm_value + etsects->alarm_interval;
+ hi = ns >> 32;
+ lo = ns & 0xffffffff;
+ spin_lock(&etsects->lock);
+ gfar_write(&etsects->regs->tmr_alarm2_l, lo);
+ gfar_write(&etsects->regs->tmr_alarm2_h, hi);
+ spin_unlock(&etsects->lock);
+ etsects->alarm_value = ns;
+ } else {
+ gfar_write(&etsects->regs->tmr_tevent, ALM2);
+ spin_lock(&etsects->lock);
+ mask = gfar_read(&etsects->regs->tmr_temask);
+ mask &= ~ALM2EN;
+ gfar_write(&etsects->regs->tmr_temask, mask);
+ spin_unlock(&etsects->lock);
+ etsects->alarm_value = 0;
+ etsects->alarm_interval = 0;
+ }
+ }
+
+ if (val & PP1) {
+ ack |= PP1;
+ event.type = PTP_CLOCK_PPS;
+ ptp_clock_event(etsects->clock, &event);
+ }
+
+ if (ack) {
+ gfar_write(&etsects->regs->tmr_tevent, ack);
+ return IRQ_HANDLED;
+ } else
+ return IRQ_NONE;
+}
+
+/*
+ * PTP clock operations
+ */
+
+static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+{
+ u64 adj;
+ u32 diff, tmr_add;
+ int neg_adj = 0;
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+
+ if (ppb < 0) {
+ neg_adj = 1;
+ ppb = -ppb;
+ }
+ tmr_add = etsects->tmr_add;
+ adj = tmr_add;
+ adj *= ppb;
+ diff = div_u64(adj, 1000000000ULL);
+
+ tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
+
+ gfar_write(&etsects->regs->tmr_add, tmr_add);
+
+ return 0;
+}
+
+static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+ s64 now;
+ unsigned long flags;
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+
+ spin_lock_irqsave(&etsects->lock, flags);
+
+ now = tmr_cnt_read(etsects);
+ now += delta;
+ tmr_cnt_write(etsects, now);
+
+ spin_unlock_irqrestore(&etsects->lock, flags);
+
+ set_fipers(etsects);
+
+ return 0;
+}
+
+static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
+{
+ u64 ns;
+ u32 remainder;
+ unsigned long flags;
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+
+ spin_lock_irqsave(&etsects->lock, flags);
+
+ ns = tmr_cnt_read(etsects);
+
+ spin_unlock_irqrestore(&etsects->lock, flags);
+
+ ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+ ts->tv_nsec = remainder;
+ return 0;
+}
+
+static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
+ const struct timespec *ts)
+{
+ u64 ns;
+ unsigned long flags;
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+
+ ns = ts->tv_sec * 1000000000ULL;
+ ns += ts->tv_nsec;
+
+ spin_lock_irqsave(&etsects->lock, flags);
+
+ tmr_cnt_write(etsects, ns);
+ set_fipers(etsects);
+
+ spin_unlock_irqrestore(&etsects->lock, flags);
+
+ return 0;
+}
+
+static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *rq, int on)
+{
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+ unsigned long flags;
+ u32 bit, mask;
+
+ switch (rq->type) {
+ case PTP_CLK_REQ_EXTTS:
+ switch (rq->extts.index) {
+ case 0:
+ bit = ETS1EN;
+ break;
+ case 1:
+ bit = ETS2EN;
+ break;
+ default:
+ return -EINVAL;
+ }
+ spin_lock_irqsave(&etsects->lock, flags);
+ mask = gfar_read(&etsects->regs->tmr_temask);
+ if (on)
+ mask |= bit;
+ else
+ mask &= ~bit;
+ gfar_write(&etsects->regs->tmr_temask, mask);
+ spin_unlock_irqrestore(&etsects->lock, flags);
+ return 0;
+
+ case PTP_CLK_REQ_PPS:
+ spin_lock_irqsave(&etsects->lock, flags);
+ mask = gfar_read(&etsects->regs->tmr_temask);
+ if (on)
+ mask |= PP1EN;
+ else
+ mask &= ~PP1EN;
+ gfar_write(&etsects->regs->tmr_temask, mask);
+ spin_unlock_irqrestore(&etsects->lock, flags);
+ return 0;
+
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_gianfar_caps = {
+ .owner = THIS_MODULE,
+ .name = "gianfar clock",
+ .max_adj = 512000,
+ .n_alarm = N_ALARM,
+ .n_ext_ts = N_EXT_TS,
+ .n_per_out = 0,
+ .pps = 1,
+ .adjfreq = ptp_gianfar_adjfreq,
+ .adjtime = ptp_gianfar_adjtime,
+ .gettime = ptp_gianfar_gettime,
+ .settime = ptp_gianfar_settime,
+ .enable = ptp_gianfar_enable,
+};
+
+/* OF device tree */
+
+static int get_of_u32(struct device_node *node, char *str, u32 *val)
+{
+ int plen;
+ const u32 *prop = of_get_property(node, str, &plen);
+
+ if (!prop || plen != sizeof(*prop))
+ return -1;
+ *val = *prop;
+ return 0;
+}
+
+static int gianfar_ptp_probe(struct platform_device *dev)
+{
+ struct device_node *node = dev->dev.of_node;
+ struct etsects *etsects;
+ struct timespec now;
+ int err = -ENOMEM;
+ u32 tmr_ctrl;
+
+ etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
+ if (!etsects)
+ goto no_memory;
+
+ err = -ENODEV;
+
+ etsects->caps = ptp_gianfar_caps;
+ etsects->cksel = DEFAULT_CKSEL;
+
+ if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
+ get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
+ get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
+ get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
+ get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
+ get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
+ pr_err("device tree node missing required elements\n");
+ goto no_node;
+ }
+
+ etsects->irq = platform_get_irq(dev, 0);
+
+ if (etsects->irq == NO_IRQ) {
+ pr_err("irq not in device tree\n");
+ goto no_node;
+ }
+ if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
+ pr_err("request_irq failed\n");
+ goto no_node;
+ }
+
+ etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!etsects->rsrc) {
+ pr_err("no resource\n");
+ goto no_resource;
+ }
+ if (request_resource(&ioport_resource, etsects->rsrc)) {
+ pr_err("resource busy\n");
+ goto no_resource;
+ }
+
+ spin_lock_init(&etsects->lock);
+
+ etsects->regs = ioremap(etsects->rsrc->start,
+ 1 + etsects->rsrc->end - etsects->rsrc->start);
+ if (!etsects->regs) {
+ pr_err("ioremap ptp registers failed\n");
+ goto no_ioremap;
+ }
+ getnstimeofday(&now);
+ ptp_gianfar_settime(&etsects->caps, &now);
+
+ tmr_ctrl =
+ (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
+ (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
+
+ gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
+ gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
+ gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
+ gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
+ gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+ set_alarm(etsects);
+ gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FS|RTPE|TE);
+
+ etsects->clock = ptp_clock_register(&etsects->caps);
+ if (IS_ERR(etsects->clock)) {
+ err = PTR_ERR(etsects->clock);
+ goto no_clock;
+ }
+
+ dev_set_drvdata(&dev->dev, etsects);
+
+ return 0;
+
+no_clock:
+no_ioremap:
+ release_resource(etsects->rsrc);
+no_resource:
+ free_irq(etsects->irq, etsects);
+no_node:
+ kfree(etsects);
+no_memory:
+ return err;
+}
+
+static int gianfar_ptp_remove(struct platform_device *dev)
+{
+ struct etsects *etsects = dev_get_drvdata(&dev->dev);
+
+ gfar_write(&etsects->regs->tmr_temask, 0);
+ gfar_write(&etsects->regs->tmr_ctrl, 0);
+
+ ptp_clock_unregister(etsects->clock);
+ iounmap(etsects->regs);
+ release_resource(etsects->rsrc);
+ free_irq(etsects->irq, etsects);
+ kfree(etsects);
+
+ return 0;
+}
+
+static struct of_device_id match_table[] = {
+ { .compatible = "fsl,etsec-ptp" },
+ {},
+};
+
+static struct platform_driver gianfar_ptp_driver = {
+ .driver = {
+ .name = "gianfar_ptp",
+ .of_match_table = match_table,
+ .owner = THIS_MODULE,
+ },
+ .probe = gianfar_ptp_probe,
+ .remove = gianfar_ptp_remove,
+};
+
+/* module operations */
+
+static int __init ptp_gianfar_init(void)
+{
+ return platform_driver_register(&gianfar_ptp_driver);
+}
+
+module_init(ptp_gianfar_init);
+
+static void __exit ptp_gianfar_exit(void)
+{
+ platform_driver_unregister(&gianfar_ptp_driver);
+}
+
+module_exit(ptp_gianfar_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
+MODULE_DESCRIPTION("PTP clock using the eTSEC");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index 70d4bb1..12eb844 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -27,4 +27,17 @@ config PTP_1588_CLOCK
To compile this driver as a module, choose M here: the module
will be called ptp.
+config PTP_1588_CLOCK_GIANFAR
+ tristate "Freescale eTSEC as PTP clock"
+ depends on PTP_1588_CLOCK
+ depends on GIANFAR
+ help
+ This driver adds support for using the eTSEC as a PTP
+ clock. This clock is only useful if your PTP programs are
+ getting hardware time stamps on the PTP Ethernet packets
+ using the SO_TIMESTAMPING API.
+
+ To compile this driver as a module, choose M here: the module
+ will be called gianfar_ptp.
+
endmenu
--
1.7.0.4
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