* [PATCH 06/28] powerpc: platforms/86xx irq_data conversion.
From: Lennert Buytenhek @ 2011-03-07 23:59 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <cover.1299541392.git.buytenh@wantstofly.org>
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
---
arch/powerpc/platforms/86xx/gef_pic.c | 22 +++++++++++-----------
arch/powerpc/platforms/86xx/pic.c | 5 ++++-
2 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c
index 6df9e25..0adfe3b 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.c
+++ b/arch/powerpc/platforms/86xx/gef_pic.c
@@ -95,6 +95,7 @@ static int gef_pic_cascade_irq;
void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
unsigned int cascade_irq;
/*
@@ -106,17 +107,16 @@ void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
-
+ chip->irq_eoi(&desc->irq_data);
}
-static void gef_pic_mask(unsigned int virq)
+static void gef_pic_mask(struct irq_data *d)
{
unsigned long flags;
unsigned int hwirq;
u32 mask;
- hwirq = gef_irq_to_hw(virq);
+ hwirq = gef_irq_to_hw(d->irq);
raw_spin_lock_irqsave(&gef_pic_lock, flags);
mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
@@ -125,21 +125,21 @@ static void gef_pic_mask(unsigned int virq)
raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
}
-static void gef_pic_mask_ack(unsigned int virq)
+static void gef_pic_mask_ack(struct irq_data *d)
{
/* Don't think we actually have to do anything to ack an interrupt,
* we just need to clear down the devices interrupt and it will go away
*/
- gef_pic_mask(virq);
+ gef_pic_mask(d);
}
-static void gef_pic_unmask(unsigned int virq)
+static void gef_pic_unmask(struct irq_data *d)
{
unsigned long flags;
unsigned int hwirq;
u32 mask;
- hwirq = gef_irq_to_hw(virq);
+ hwirq = gef_irq_to_hw(d->irq);
raw_spin_lock_irqsave(&gef_pic_lock, flags);
mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
@@ -150,9 +150,9 @@ static void gef_pic_unmask(unsigned int virq)
static struct irq_chip gef_pic_chip = {
.name = "gefp",
- .mask = gef_pic_mask,
- .mask_ack = gef_pic_mask_ack,
- .unmask = gef_pic_unmask,
+ .irq_mask = gef_pic_mask,
+ .irq_mask_ack = gef_pic_mask_ack,
+ .irq_unmask = gef_pic_unmask,
};
diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c
index 668275d..cbe3363 100644
--- a/arch/powerpc/platforms/86xx/pic.c
+++ b/arch/powerpc/platforms/86xx/pic.c
@@ -19,10 +19,13 @@
#ifdef CONFIG_PPC_I8259
static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
unsigned int cascade_irq = i8259_irq();
+
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
+
+ chip->irq_eoi(&desc->irq_data);
}
#endif /* CONFIG_PPC_I8259 */
--
1.7.4
^ permalink raw reply related
* [PATCH 05/28] powerpc: platforms/85xx irq_data conversion.
From: Lennert Buytenhek @ 2011-03-07 23:59 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <cover.1299541392.git.buytenh@wantstofly.org>
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
---
arch/powerpc/platforms/85xx/ksi8560.c | 3 +-
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 3 +-
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 3 +-
arch/powerpc/platforms/85xx/sbc8560.c | 3 +-
arch/powerpc/platforms/85xx/socrates_fpga_pic.c | 40 +++++++++++-----------
arch/powerpc/platforms/85xx/stx_gp3.c | 3 +-
arch/powerpc/platforms/85xx/tqm85xx.c | 3 +-
7 files changed, 32 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c
index f4d36b5..64447e4 100644
--- a/arch/powerpc/platforms/85xx/ksi8560.c
+++ b/arch/powerpc/platforms/85xx/ksi8560.c
@@ -56,12 +56,13 @@ static void machine_restart(char *cmd)
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
+ chip->irq_eoi(&desc->irq_data);
}
static void __init ksi8560_pic_init(void)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 9438a89..1352d11 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -50,12 +50,13 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
+ chip->irq_eoi(&desc->irq_data);
}
#endif /* CONFIG_CPM2 */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 8190bc2..793ead7 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -47,12 +47,13 @@
#ifdef CONFIG_PPC_I8259
static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ) {
generic_handle_irq(cascade_irq);
}
- desc->chip->eoi(irq);
+ chip->irq_eoi(&desc->irq_data);
}
#endif /* CONFIG_PPC_I8259 */
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index a5ad1c7..d7e28ec 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -41,12 +41,13 @@
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
+ chip->irq_eoi(&desc->irq_data);
}
#endif /* CONFIG_CPM2 */
diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
index d48527f..79d85ac 100644
--- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
+++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
@@ -93,6 +93,7 @@ static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq)
void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
unsigned int cascade_irq;
/*
@@ -103,17 +104,16 @@ void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc)
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
-
+ chip->irq_eoi(&desc->irq_data);
}
-static void socrates_fpga_pic_ack(unsigned int virq)
+static void socrates_fpga_pic_ack(struct irq_data *d)
{
unsigned long flags;
unsigned int hwirq, irq_line;
uint32_t mask;
- hwirq = socrates_fpga_irq_to_hw(virq);
+ hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
@@ -124,14 +124,14 @@ static void socrates_fpga_pic_ack(unsigned int virq)
raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
}
-static void socrates_fpga_pic_mask(unsigned int virq)
+static void socrates_fpga_pic_mask(struct irq_data *d)
{
unsigned long flags;
unsigned int hwirq;
int irq_line;
u32 mask;
- hwirq = socrates_fpga_irq_to_hw(virq);
+ hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
@@ -142,14 +142,14 @@ static void socrates_fpga_pic_mask(unsigned int virq)
raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
}
-static void socrates_fpga_pic_mask_ack(unsigned int virq)
+static void socrates_fpga_pic_mask_ack(struct irq_data *d)
{
unsigned long flags;
unsigned int hwirq;
int irq_line;
u32 mask;
- hwirq = socrates_fpga_irq_to_hw(virq);
+ hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
@@ -161,14 +161,14 @@ static void socrates_fpga_pic_mask_ack(unsigned int virq)
raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
}
-static void socrates_fpga_pic_unmask(unsigned int virq)
+static void socrates_fpga_pic_unmask(struct irq_data *d)
{
unsigned long flags;
unsigned int hwirq;
int irq_line;
u32 mask;
- hwirq = socrates_fpga_irq_to_hw(virq);
+ hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
@@ -179,14 +179,14 @@ static void socrates_fpga_pic_unmask(unsigned int virq)
raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
}
-static void socrates_fpga_pic_eoi(unsigned int virq)
+static void socrates_fpga_pic_eoi(struct irq_data *d)
{
unsigned long flags;
unsigned int hwirq;
int irq_line;
u32 mask;
- hwirq = socrates_fpga_irq_to_hw(virq);
+ hwirq = socrates_fpga_irq_to_hw(d->irq);
irq_line = fpga_irqs[hwirq].irq_line;
raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags);
@@ -197,7 +197,7 @@ static void socrates_fpga_pic_eoi(unsigned int virq)
raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags);
}
-static int socrates_fpga_pic_set_type(unsigned int virq,
+static int socrates_fpga_pic_set_type(struct irq_data *d,
unsigned int flow_type)
{
unsigned long flags;
@@ -205,7 +205,7 @@ static int socrates_fpga_pic_set_type(unsigned int virq,
int polarity;
u32 mask;
- hwirq = socrates_fpga_irq_to_hw(virq);
+ hwirq = socrates_fpga_irq_to_hw(d->irq);
if (fpga_irqs[hwirq].type != IRQ_TYPE_NONE)
return -EINVAL;
@@ -233,12 +233,12 @@ static int socrates_fpga_pic_set_type(unsigned int virq,
static struct irq_chip socrates_fpga_pic_chip = {
.name = "FPGA-PIC",
- .ack = socrates_fpga_pic_ack,
- .mask = socrates_fpga_pic_mask,
- .mask_ack = socrates_fpga_pic_mask_ack,
- .unmask = socrates_fpga_pic_unmask,
- .eoi = socrates_fpga_pic_eoi,
- .set_type = socrates_fpga_pic_set_type,
+ .irq_ack = socrates_fpga_pic_ack,
+ .irq_mask = socrates_fpga_pic_mask,
+ .irq_mask_ack = socrates_fpga_pic_mask_ack,
+ .irq_unmask = socrates_fpga_pic_unmask,
+ .irq_eoi = socrates_fpga_pic_eoi,
+ .irq_set_type = socrates_fpga_pic_set_type,
};
static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq,
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index bc33d18..2b62b06 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -46,12 +46,13 @@
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
+ chip->irq_eoi(&desc->irq_data);
}
#endif /* CONFIG_CPM2 */
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 5e847d0..2265b68 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -44,12 +44,13 @@
static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
int cascade_irq;
while ((cascade_irq = cpm2_get_irq()) >= 0)
generic_handle_irq(cascade_irq);
- desc->chip->eoi(irq);
+ chip->irq_eoi(&desc->irq_data);
}
#endif /* CONFIG_CPM2 */
--
1.7.4
^ permalink raw reply related
* [PATCH 04/28] powerpc: platforms/82xx irq_data conversion.
From: Lennert Buytenhek @ 2011-03-07 23:59 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <cover.1299541392.git.buytenh@wantstofly.org>
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
---
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 27 ++++++++++++-------------
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
index 5a55d87..a0cd8ae 100644
--- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
@@ -39,10 +39,10 @@ struct pq2ads_pci_pic {
#define NUM_IRQS 32
-static void pq2ads_pci_mask_irq(unsigned int virq)
+static void pq2ads_pci_mask_irq(struct irq_data *d)
{
- struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
- int irq = NUM_IRQS - virq_to_hw(virq) - 1;
+ struct pq2ads_pci_pic *priv = get_irq_chip_data(d->irq);
+ int irq = NUM_IRQS - virq_to_hw(d->irq) - 1;
if (irq != -1) {
unsigned long flags;
@@ -55,10 +55,10 @@ static void pq2ads_pci_mask_irq(unsigned int virq)
}
}
-static void pq2ads_pci_unmask_irq(unsigned int virq)
+static void pq2ads_pci_unmask_irq(struct irq_data *d)
{
- struct pq2ads_pci_pic *priv = get_irq_chip_data(virq);
- int irq = NUM_IRQS - virq_to_hw(virq) - 1;
+ struct pq2ads_pci_pic *priv = get_irq_chip_data(d->irq);
+ int irq = NUM_IRQS - virq_to_hw(d->irq) - 1;
if (irq != -1) {
unsigned long flags;
@@ -71,18 +71,17 @@ static void pq2ads_pci_unmask_irq(unsigned int virq)
static struct irq_chip pq2ads_pci_ic = {
.name = "PQ2 ADS PCI",
- .end = pq2ads_pci_unmask_irq,
- .mask = pq2ads_pci_mask_irq,
- .mask_ack = pq2ads_pci_mask_irq,
- .ack = pq2ads_pci_mask_irq,
- .unmask = pq2ads_pci_unmask_irq,
- .enable = pq2ads_pci_unmask_irq,
- .disable = pq2ads_pci_mask_irq
+ .irq_mask = pq2ads_pci_mask_irq,
+ .irq_mask_ack = pq2ads_pci_mask_irq,
+ .irq_ack = pq2ads_pci_mask_irq,
+ .irq_unmask = pq2ads_pci_unmask_irq,
+ .irq_enable = pq2ads_pci_unmask_irq,
+ .irq_disable = pq2ads_pci_mask_irq
};
static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
{
- struct pq2ads_pci_pic *priv = desc->handler_data;
+ struct pq2ads_pci_pic *priv = get_irq_desc_data(desc);
u32 stat, mask, pend;
int bit;
--
1.7.4
^ permalink raw reply related
* [PATCH 03/28] powerpc: platforms/52xx irq_data conversion.
From: Lennert Buytenhek @ 2011-03-07 23:59 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <cover.1299541392.git.buytenh@wantstofly.org>
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
---
arch/powerpc/platforms/52xx/media5200.c | 21 ++++----
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 26 +++++-----
arch/powerpc/platforms/52xx/mpc52xx_pic.c | 80 ++++++++++++++--------------
3 files changed, 64 insertions(+), 63 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
index 2c7780c..2bd1e6c 100644
--- a/arch/powerpc/platforms/52xx/media5200.c
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -49,45 +49,46 @@ struct media5200_irq {
};
struct media5200_irq media5200_irq;
-static void media5200_irq_unmask(unsigned int virq)
+static void media5200_irq_unmask(struct irq_data *d)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&media5200_irq.lock, flags);
val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
- val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq);
+ val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[d->irq].hwirq);
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
spin_unlock_irqrestore(&media5200_irq.lock, flags);
}
-static void media5200_irq_mask(unsigned int virq)
+static void media5200_irq_mask(struct irq_data *d)
{
unsigned long flags;
u32 val;
spin_lock_irqsave(&media5200_irq.lock, flags);
val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
- val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq));
+ val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[d->irq].hwirq));
out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
spin_unlock_irqrestore(&media5200_irq.lock, flags);
}
static struct irq_chip media5200_irq_chip = {
.name = "Media5200 FPGA",
- .unmask = media5200_irq_unmask,
- .mask = media5200_irq_mask,
- .mask_ack = media5200_irq_mask,
+ .irq_unmask = media5200_irq_unmask,
+ .irq_mask = media5200_irq_mask,
+ .irq_mask_ack = media5200_irq_mask,
};
void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
{
+ struct irq_chip *chip = get_irq_desc_chip(desc);
int sub_virq, val;
u32 status, enable;
/* Mask off the cascaded IRQ */
raw_spin_lock(&desc->lock);
- desc->chip->mask(virq);
+ chip->irq_mask(&desc->irq_data);
raw_spin_unlock(&desc->lock);
/* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
@@ -105,9 +106,9 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
/* Processing done; can reenable the cascade now */
raw_spin_lock(&desc->lock);
- desc->chip->ack(virq);
+ chip->irq_ack(&desc->irq_data);
if (!(desc->status & IRQ_DISABLED))
- desc->chip->unmask(virq);
+ chip->irq_unmask(&desc->irq_data);
raw_spin_unlock(&desc->lock);
}
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index e0d703c..fe6cc5d 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -135,9 +135,9 @@ DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
* Cascaded interrupt controller hooks
*/
-static void mpc52xx_gpt_irq_unmask(unsigned int virq)
+static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
{
- struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
+ struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(d->irq);
unsigned long flags;
spin_lock_irqsave(&gpt->lock, flags);
@@ -145,9 +145,9 @@ static void mpc52xx_gpt_irq_unmask(unsigned int virq)
spin_unlock_irqrestore(&gpt->lock, flags);
}
-static void mpc52xx_gpt_irq_mask(unsigned int virq)
+static void mpc52xx_gpt_irq_mask(struct irq_data *d)
{
- struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
+ struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(d->irq);
unsigned long flags;
spin_lock_irqsave(&gpt->lock, flags);
@@ -155,20 +155,20 @@ static void mpc52xx_gpt_irq_mask(unsigned int virq)
spin_unlock_irqrestore(&gpt->lock, flags);
}
-static void mpc52xx_gpt_irq_ack(unsigned int virq)
+static void mpc52xx_gpt_irq_ack(struct irq_data *d)
{
- struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
+ struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(d->irq);
out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
}
-static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type)
+static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
- struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
+ struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(d->irq);
unsigned long flags;
u32 reg;
- dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, virq, flow_type);
+ dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
spin_lock_irqsave(&gpt->lock, flags);
reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
@@ -184,10 +184,10 @@ static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type)
static struct irq_chip mpc52xx_gpt_irq_chip = {
.name = "MPC52xx GPT",
- .unmask = mpc52xx_gpt_irq_unmask,
- .mask = mpc52xx_gpt_irq_mask,
- .ack = mpc52xx_gpt_irq_ack,
- .set_type = mpc52xx_gpt_irq_set_type,
+ .irq_unmask = mpc52xx_gpt_irq_unmask,
+ .irq_mask = mpc52xx_gpt_irq_mask,
+ .irq_ack = mpc52xx_gpt_irq_ack,
+ .irq_set_type = mpc52xx_gpt_irq_set_type,
};
void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
index 4bf4bf7..9f3ed58 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -155,47 +155,47 @@ static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
/*
* IRQ[0-3] interrupt irq_chip
*/
-static void mpc52xx_extirq_mask(unsigned int virq)
+static void mpc52xx_extirq_mask(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&intr->ctrl, 11 - l2irq);
}
-static void mpc52xx_extirq_unmask(unsigned int virq)
+static void mpc52xx_extirq_unmask(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->ctrl, 11 - l2irq);
}
-static void mpc52xx_extirq_ack(unsigned int virq)
+static void mpc52xx_extirq_ack(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->ctrl, 27-l2irq);
}
-static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
+static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type)
{
u32 ctrl_reg, type;
int irq;
int l2irq;
void *handler = handle_level_irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
@@ -214,44 +214,44 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
ctrl_reg |= (type << (22 - (l2irq * 2)));
out_be32(&intr->ctrl, ctrl_reg);
- __set_irq_handler_unlocked(virq, handler);
+ __set_irq_handler_unlocked(d->irq, handler);
return 0;
}
static struct irq_chip mpc52xx_extirq_irqchip = {
.name = "MPC52xx External",
- .mask = mpc52xx_extirq_mask,
- .unmask = mpc52xx_extirq_unmask,
- .ack = mpc52xx_extirq_ack,
- .set_type = mpc52xx_extirq_set_type,
+ .irq_mask = mpc52xx_extirq_mask,
+ .irq_unmask = mpc52xx_extirq_unmask,
+ .irq_ack = mpc52xx_extirq_ack,
+ .irq_set_type = mpc52xx_extirq_set_type,
};
/*
* Main interrupt irq_chip
*/
-static int mpc52xx_null_set_type(unsigned int virq, unsigned int flow_type)
+static int mpc52xx_null_set_type(struct irq_data *d, unsigned int flow_type)
{
return 0; /* Do nothing so that the sense mask will get updated */
}
-static void mpc52xx_main_mask(unsigned int virq)
+static void mpc52xx_main_mask(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->main_mask, 16 - l2irq);
}
-static void mpc52xx_main_unmask(unsigned int virq)
+static void mpc52xx_main_unmask(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&intr->main_mask, 16 - l2irq);
@@ -259,32 +259,32 @@ static void mpc52xx_main_unmask(unsigned int virq)
static struct irq_chip mpc52xx_main_irqchip = {
.name = "MPC52xx Main",
- .mask = mpc52xx_main_mask,
- .mask_ack = mpc52xx_main_mask,
- .unmask = mpc52xx_main_unmask,
- .set_type = mpc52xx_null_set_type,
+ .irq_mask = mpc52xx_main_mask,
+ .irq_mask_ack = mpc52xx_main_mask,
+ .irq_unmask = mpc52xx_main_unmask,
+ .irq_set_type = mpc52xx_null_set_type,
};
/*
* Peripherals interrupt irq_chip
*/
-static void mpc52xx_periph_mask(unsigned int virq)
+static void mpc52xx_periph_mask(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->per_mask, 31 - l2irq);
}
-static void mpc52xx_periph_unmask(unsigned int virq)
+static void mpc52xx_periph_unmask(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&intr->per_mask, 31 - l2irq);
@@ -292,43 +292,43 @@ static void mpc52xx_periph_unmask(unsigned int virq)
static struct irq_chip mpc52xx_periph_irqchip = {
.name = "MPC52xx Peripherals",
- .mask = mpc52xx_periph_mask,
- .mask_ack = mpc52xx_periph_mask,
- .unmask = mpc52xx_periph_unmask,
- .set_type = mpc52xx_null_set_type,
+ .irq_mask = mpc52xx_periph_mask,
+ .irq_mask_ack = mpc52xx_periph_mask,
+ .irq_unmask = mpc52xx_periph_unmask,
+ .irq_set_type = mpc52xx_null_set_type,
};
/*
* SDMA interrupt irq_chip
*/
-static void mpc52xx_sdma_mask(unsigned int virq)
+static void mpc52xx_sdma_mask(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&sdma->IntMask, l2irq);
}
-static void mpc52xx_sdma_unmask(unsigned int virq)
+static void mpc52xx_sdma_unmask(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&sdma->IntMask, l2irq);
}
-static void mpc52xx_sdma_ack(unsigned int virq)
+static void mpc52xx_sdma_ack(struct irq_data *d)
{
int irq;
int l2irq;
- irq = irq_map[virq].hwirq;
+ irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
out_be32(&sdma->IntPend, 1 << l2irq);
@@ -336,10 +336,10 @@ static void mpc52xx_sdma_ack(unsigned int virq)
static struct irq_chip mpc52xx_sdma_irqchip = {
.name = "MPC52xx SDMA",
- .mask = mpc52xx_sdma_mask,
- .unmask = mpc52xx_sdma_unmask,
- .ack = mpc52xx_sdma_ack,
- .set_type = mpc52xx_null_set_type,
+ .irq_mask = mpc52xx_sdma_mask,
+ .irq_unmask = mpc52xx_sdma_unmask,
+ .irq_ack = mpc52xx_sdma_ack,
+ .irq_set_type = mpc52xx_null_set_type,
};
/**
--
1.7.4
^ permalink raw reply related
* [PATCH 02/28] powerpc: platforms/512x irq_data conversion.
From: Lennert Buytenhek @ 2011-03-07 23:59 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <cover.1299541392.git.buytenh@wantstofly.org>
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
---
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c | 14 +++++++-------
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
index 4ecf4cf..fde0ea5 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
@@ -59,9 +59,9 @@ irq_to_pic_bit(unsigned int irq)
}
static void
-cpld_mask_irq(unsigned int irq)
+cpld_mask_irq(struct irq_data *d)
{
- unsigned int cpld_irq = (unsigned int)irq_map[irq].hwirq;
+ unsigned int cpld_irq = (unsigned int)irq_map[d->irq].hwirq;
void __iomem *pic_mask = irq_to_pic_mask(cpld_irq);
out_8(pic_mask,
@@ -69,9 +69,9 @@ cpld_mask_irq(unsigned int irq)
}
static void
-cpld_unmask_irq(unsigned int irq)
+cpld_unmask_irq(struct irq_data *d)
{
- unsigned int cpld_irq = (unsigned int)irq_map[irq].hwirq;
+ unsigned int cpld_irq = (unsigned int)irq_map[d->irq].hwirq;
void __iomem *pic_mask = irq_to_pic_mask(cpld_irq);
out_8(pic_mask,
@@ -80,9 +80,9 @@ cpld_unmask_irq(unsigned int irq)
static struct irq_chip cpld_pic = {
.name = "CPLD PIC",
- .mask = cpld_mask_irq,
- .ack = cpld_mask_irq,
- .unmask = cpld_unmask_irq,
+ .irq_mask = cpld_mask_irq,
+ .irq_ack = cpld_mask_irq,
+ .irq_unmask = cpld_unmask_irq,
};
static int
--
1.7.4
^ permalink raw reply related
* [PATCH 01/28] powerpc: mpic irq_data conversion.
From: Lennert Buytenhek @ 2011-03-07 23:59 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <cover.1299541392.git.buytenh@wantstofly.org>
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
---
arch/powerpc/include/asm/mpic.h | 6 +-
arch/powerpc/platforms/pasemi/setup.c | 4 +-
arch/powerpc/sysdev/mpic.c | 131 +++++++++++++++++----------------
arch/powerpc/sysdev/mpic.h | 5 +-
arch/powerpc/sysdev/mpic_pasemi_msi.c | 18 ++--
arch/powerpc/sysdev/mpic_u3msi.c | 18 ++--
6 files changed, 92 insertions(+), 90 deletions(-)
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index e000cce..946ec49 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -467,11 +467,11 @@ extern void mpic_request_ipis(void);
void smp_mpic_message_pass(int target, int msg);
/* Unmask a specific virq */
-extern void mpic_unmask_irq(unsigned int irq);
+extern void mpic_unmask_irq(struct irq_data *d);
/* Mask a specific virq */
-extern void mpic_mask_irq(unsigned int irq);
+extern void mpic_mask_irq(struct irq_data *d);
/* EOI a specific virq */
-extern void mpic_end_irq(unsigned int irq);
+extern void mpic_end_irq(struct irq_data *d);
/* Fetch interrupt from a given mpic */
extern unsigned int mpic_get_one_irq(struct mpic *mpic);
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index f372ec1..a6067b3 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -240,7 +240,7 @@ static __init void pas_init_IRQ(void)
nmi_virq = irq_create_mapping(NULL, *nmiprop);
mpic_irq_set_priority(nmi_virq, 15);
set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
- mpic_unmask_irq(nmi_virq);
+ mpic_unmask_irq(irq_get_irq_data(nmi_virq));
}
of_node_put(mpic_node);
@@ -266,7 +266,7 @@ static int pas_machine_check_handler(struct pt_regs *regs)
if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) {
printk(KERN_ERR "NMI delivered\n");
debugger(regs);
- mpic_end_irq(nmi_virq);
+ mpic_end_irq(irq_get_irq_data(nmi_virq));
goto out;
}
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index b0c8469..95712f6 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -611,7 +611,7 @@ static struct mpic *mpic_find(unsigned int irq)
if (irq < NUM_ISA_INTERRUPTS)
return NULL;
- return irq_to_desc(irq)->chip_data;
+ return get_irq_chip_data(irq);
}
/* Determine if the linux irq is an IPI */
@@ -636,16 +636,16 @@ static inline u32 mpic_physmask(u32 cpumask)
#ifdef CONFIG_SMP
/* Get the mpic structure from the IPI number */
-static inline struct mpic * mpic_from_ipi(unsigned int ipi)
+static inline struct mpic * mpic_from_ipi(struct irq_data *d)
{
- return irq_to_desc(ipi)->chip_data;
+ return irq_data_get_irq_chip_data(d);
}
#endif
/* Get the mpic structure from the irq number */
static inline struct mpic * mpic_from_irq(unsigned int irq)
{
- return irq_to_desc(irq)->chip_data;
+ return get_irq_chip_data(irq);
}
/* Send an EOI */
@@ -660,13 +660,13 @@ static inline void mpic_eoi(struct mpic *mpic)
*/
-void mpic_unmask_irq(unsigned int irq)
+void mpic_unmask_irq(struct irq_data *d)
{
unsigned int loops = 100000;
- struct mpic *mpic = mpic_from_irq(irq);
- unsigned int src = mpic_irq_to_hw(irq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
+ unsigned int src = mpic_irq_to_hw(d->irq);
- DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
+ DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
@@ -681,13 +681,13 @@ void mpic_unmask_irq(unsigned int irq)
} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
}
-void mpic_mask_irq(unsigned int irq)
+void mpic_mask_irq(struct irq_data *d)
{
unsigned int loops = 100000;
- struct mpic *mpic = mpic_from_irq(irq);
- unsigned int src = mpic_irq_to_hw(irq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
+ unsigned int src = mpic_irq_to_hw(d->irq);
- DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
+ DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
@@ -703,12 +703,12 @@ void mpic_mask_irq(unsigned int irq)
} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
}
-void mpic_end_irq(unsigned int irq)
+void mpic_end_irq(struct irq_data *d)
{
- struct mpic *mpic = mpic_from_irq(irq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
#ifdef DEBUG_IRQ
- DBG("%s: end_irq: %d\n", mpic->name, irq);
+ DBG("%s: end_irq: %d\n", mpic->name, d->irq);
#endif
/* We always EOI on end_irq() even for edge interrupts since that
* should only lower the priority, the MPIC should have properly
@@ -720,51 +720,51 @@ void mpic_end_irq(unsigned int irq)
#ifdef CONFIG_MPIC_U3_HT_IRQS
-static void mpic_unmask_ht_irq(unsigned int irq)
+static void mpic_unmask_ht_irq(struct irq_data *d)
{
- struct mpic *mpic = mpic_from_irq(irq);
- unsigned int src = mpic_irq_to_hw(irq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
+ unsigned int src = mpic_irq_to_hw(d->irq);
- mpic_unmask_irq(irq);
+ mpic_unmask_irq(d);
- if (irq_to_desc(irq)->status & IRQ_LEVEL)
+ if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
mpic_ht_end_irq(mpic, src);
}
-static unsigned int mpic_startup_ht_irq(unsigned int irq)
+static unsigned int mpic_startup_ht_irq(struct irq_data *d)
{
- struct mpic *mpic = mpic_from_irq(irq);
- unsigned int src = mpic_irq_to_hw(irq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
+ unsigned int src = mpic_irq_to_hw(d->irq);
- mpic_unmask_irq(irq);
- mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
+ mpic_unmask_irq(d);
+ mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status);
return 0;
}
-static void mpic_shutdown_ht_irq(unsigned int irq)
+static void mpic_shutdown_ht_irq(struct irq_data *d)
{
- struct mpic *mpic = mpic_from_irq(irq);
- unsigned int src = mpic_irq_to_hw(irq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
+ unsigned int src = mpic_irq_to_hw(d->irq);
- mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status);
- mpic_mask_irq(irq);
+ mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status);
+ mpic_mask_irq(d);
}
-static void mpic_end_ht_irq(unsigned int irq)
+static void mpic_end_ht_irq(struct irq_data *d)
{
- struct mpic *mpic = mpic_from_irq(irq);
- unsigned int src = mpic_irq_to_hw(irq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
+ unsigned int src = mpic_irq_to_hw(d->irq);
#ifdef DEBUG_IRQ
- DBG("%s: end_irq: %d\n", mpic->name, irq);
+ DBG("%s: end_irq: %d\n", mpic->name, d->irq);
#endif
/* We always EOI on end_irq() even for edge interrupts since that
* should only lower the priority, the MPIC should have properly
* latched another edge interrupt coming in anyway
*/
- if (irq_to_desc(irq)->status & IRQ_LEVEL)
+ if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
mpic_ht_end_irq(mpic, src);
mpic_eoi(mpic);
}
@@ -772,23 +772,23 @@ static void mpic_end_ht_irq(unsigned int irq)
#ifdef CONFIG_SMP
-static void mpic_unmask_ipi(unsigned int irq)
+static void mpic_unmask_ipi(struct irq_data *d)
{
- struct mpic *mpic = mpic_from_ipi(irq);
- unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
+ struct mpic *mpic = mpic_from_ipi(d);
+ unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0];
- DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
+ DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
}
-static void mpic_mask_ipi(unsigned int irq)
+static void mpic_mask_ipi(struct irq_data *d)
{
/* NEVER disable an IPI... that's just plain wrong! */
}
-static void mpic_end_ipi(unsigned int irq)
+static void mpic_end_ipi(struct irq_data *d)
{
- struct mpic *mpic = mpic_from_ipi(irq);
+ struct mpic *mpic = mpic_from_ipi(d);
/*
* IPIs are marked IRQ_PER_CPU. This has the side effect of
@@ -802,10 +802,11 @@ static void mpic_end_ipi(unsigned int irq)
#endif /* CONFIG_SMP */
-int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
+int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
+ bool force)
{
- struct mpic *mpic = mpic_from_irq(irq);
- unsigned int src = mpic_irq_to_hw(irq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
+ unsigned int src = mpic_irq_to_hw(d->irq);
if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
int cpuid = irq_choose_cpu(cpumask);
@@ -848,15 +849,15 @@ static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
}
}
-int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
+int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
{
- struct mpic *mpic = mpic_from_irq(virq);
- unsigned int src = mpic_irq_to_hw(virq);
- struct irq_desc *desc = irq_to_desc(virq);
+ struct mpic *mpic = mpic_from_irq(d->irq);
+ unsigned int src = mpic_irq_to_hw(d->irq);
+ struct irq_desc *desc = irq_to_desc(d->irq);
unsigned int vecpri, vold, vnew;
DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
- mpic, virq, src, flow_type);
+ mpic, d->irq, src, flow_type);
if (src >= mpic->irq_count)
return -EINVAL;
@@ -907,28 +908,28 @@ void mpic_set_vector(unsigned int virq, unsigned int vector)
}
static struct irq_chip mpic_irq_chip = {
- .mask = mpic_mask_irq,
- .unmask = mpic_unmask_irq,
- .eoi = mpic_end_irq,
- .set_type = mpic_set_irq_type,
+ .irq_mask = mpic_mask_irq,
+ .irq_unmask = mpic_unmask_irq,
+ .irq_eoi = mpic_end_irq,
+ .irq_set_type = mpic_set_irq_type,
};
#ifdef CONFIG_SMP
static struct irq_chip mpic_ipi_chip = {
- .mask = mpic_mask_ipi,
- .unmask = mpic_unmask_ipi,
- .eoi = mpic_end_ipi,
+ .irq_mask = mpic_mask_ipi,
+ .irq_unmask = mpic_unmask_ipi,
+ .irq_eoi = mpic_end_ipi,
};
#endif /* CONFIG_SMP */
#ifdef CONFIG_MPIC_U3_HT_IRQS
static struct irq_chip mpic_irq_ht_chip = {
- .startup = mpic_startup_ht_irq,
- .shutdown = mpic_shutdown_ht_irq,
- .mask = mpic_mask_irq,
- .unmask = mpic_unmask_ht_irq,
- .eoi = mpic_end_ht_irq,
- .set_type = mpic_set_irq_type,
+ .irq_startup = mpic_startup_ht_irq,
+ .irq_shutdown = mpic_shutdown_ht_irq,
+ .irq_mask = mpic_mask_irq,
+ .irq_unmask = mpic_unmask_ht_irq,
+ .irq_eoi = mpic_end_ht_irq,
+ .irq_set_type = mpic_set_irq_type,
};
#endif /* CONFIG_MPIC_U3_HT_IRQS */
@@ -1060,12 +1061,12 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic->hc_irq = mpic_irq_chip;
mpic->hc_irq.name = name;
if (flags & MPIC_PRIMARY)
- mpic->hc_irq.set_affinity = mpic_set_affinity;
+ mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
#ifdef CONFIG_MPIC_U3_HT_IRQS
mpic->hc_ht_irq = mpic_irq_ht_chip;
mpic->hc_ht_irq.name = name;
if (flags & MPIC_PRIMARY)
- mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
+ mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
#endif /* CONFIG_MPIC_U3_HT_IRQS */
#ifdef CONFIG_SMP
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h
index e4a6df7..13f3e89 100644
--- a/arch/powerpc/sysdev/mpic.h
+++ b/arch/powerpc/sysdev/mpic.h
@@ -34,9 +34,10 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic)
}
#endif
-extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type);
+extern int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type);
extern void mpic_set_vector(unsigned int virq, unsigned int vector);
-extern int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask);
+extern int mpic_set_affinity(struct irq_data *d,
+ const struct cpumask *cpumask, bool force);
extern void mpic_reset_core(int cpu);
#endif /* _POWERPC_SYSDEV_MPIC_H */
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c
index 320ad5a..0b7794a 100644
--- a/arch/powerpc/sysdev/mpic_pasemi_msi.c
+++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c
@@ -43,24 +43,24 @@ static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
{
pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
mask_msi_irq(data);
- mpic_mask_irq(data->irq);
+ mpic_mask_irq(data);
}
static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
{
pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
- mpic_unmask_irq(data->irq);
+ mpic_unmask_irq(data);
unmask_msi_irq(data);
}
static struct irq_chip mpic_pasemi_msi_chip = {
- .irq_shutdown = mpic_pasemi_msi_mask_irq,
- .irq_mask = mpic_pasemi_msi_mask_irq,
- .irq_unmask = mpic_pasemi_msi_unmask_irq,
- .eoi = mpic_end_irq,
- .set_type = mpic_set_irq_type,
- .set_affinity = mpic_set_affinity,
- .name = "PASEMI-MSI",
+ .irq_shutdown = mpic_pasemi_msi_mask_irq,
+ .irq_mask = mpic_pasemi_msi_mask_irq,
+ .irq_unmask = mpic_pasemi_msi_unmask_irq,
+ .irq_eoi = mpic_end_irq,
+ .irq_set_type = mpic_set_irq_type,
+ .irq_set_affinity = mpic_set_affinity,
+ .name = "PASEMI-MSI",
};
static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index a2b028b..71900ac 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -26,23 +26,23 @@ static struct mpic *msi_mpic;
static void mpic_u3msi_mask_irq(struct irq_data *data)
{
mask_msi_irq(data);
- mpic_mask_irq(data->irq);
+ mpic_mask_irq(data);
}
static void mpic_u3msi_unmask_irq(struct irq_data *data)
{
- mpic_unmask_irq(data->irq);
+ mpic_unmask_irq(data);
unmask_msi_irq(data);
}
static struct irq_chip mpic_u3msi_chip = {
- .irq_shutdown = mpic_u3msi_mask_irq,
- .irq_mask = mpic_u3msi_mask_irq,
- .irq_unmask = mpic_u3msi_unmask_irq,
- .eoi = mpic_end_irq,
- .set_type = mpic_set_irq_type,
- .set_affinity = mpic_set_affinity,
- .name = "MPIC-U3MSI",
+ .irq_shutdown = mpic_u3msi_mask_irq,
+ .irq_mask = mpic_u3msi_mask_irq,
+ .irq_unmask = mpic_u3msi_unmask_irq,
+ .irq_eoi = mpic_end_irq,
+ .irq_set_type = mpic_set_irq_type,
+ .irq_set_affinity = mpic_set_affinity,
+ .name = "MPIC-U3MSI",
};
static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
--
1.7.4
^ permalink raw reply related
* [PATCH,v2 00/28] powerpc: irq_data conversion.
From: Lennert Buytenhek @ 2011-03-07 23:58 UTC (permalink / raw)
To: linuxppc-dev
This patch converts powerpc over to the new irq_data based irq_chip
functions, as was done earlier for ARM and most other architectures.
struct irq_data is described here:
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=ff7dcd44dd446db2c3e13bdedf2d52b8e0127f16
The new irq_chip functions are described here:
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=f8822657e799b02c55556c99a601261e207a299d
This patch set is also available from:
git://git.kernel.org/pub/scm/linux/kernel/git/buytenh/powerpc_irq_data.git
http://git.kernel.org/?p=linux/kernel/git/buytenh/powerpc_irq_data.git
v2: fixes build failures (build-tested on all powerpc (32/64b)
defconfigs), and has been split into a patch series. It has still
had only limited run-time testing.
Lennert Buytenhek (28):
powerpc: mpic irq_data conversion.
powerpc: platforms/512x irq_data conversion.
powerpc: platforms/52xx irq_data conversion.
powerpc: platforms/82xx irq_data conversion.
powerpc: platforms/85xx irq_data conversion.
powerpc: platforms/86xx irq_data conversion.
powerpc: platforms/8xx irq_data conversion.
powerpc: platforms/cell irq_data conversion.
powerpc: platforms/chrp irq_data conversion.
powerpc: platforms/embedded6xx irq_data conversion.
powerpc: platforms/iseries irq_data conversion.
powerpc: platforms/powermac irq_data conversion.
powerpc: platforms/ps3 irq_data conversion.
powerpc: platforms/pseries irq_data conversion.
powerpc: sysdev/cpm1 irq_data conversion.
powerpc: sysdev/cpm2_pic irq_data conversion.
powerpc: sysdev/fsl_msi irq_data conversion.
powerpc: sysdev/i8259 irq_data conversion.
powerpc: sysdev/ipic irq_data conversion.
powerpc: sysdev/mpc8xx_pic irq_data conversion.
powerpc: sysdev/mpc8xxx_gpio irq_data conversion.
powerpc: sysdev/mv64x60_pic irq_data conversion.
powerpc: sysdev/qe_lib/qe_ic irq_data conversion.
powerpc: sysdev/tsi108_pci irq_data conversion.
powerpc: sysdev/uic irq_data conversion.
powerpc: sysdev/xilinx_intc irq_data conversion.
powerpc: core irq_data conversion.
powerpc: Enable GENERIC_HARDIRQS_NO_DEPRECATED.
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/mpic.h | 6 +-
arch/powerpc/include/asm/qe_ic.h | 19 ++--
arch/powerpc/kernel/irq.c | 23 +++-
arch/powerpc/kernel/machine_kexec.c | 21 ++--
arch/powerpc/platforms/512x/mpc5121_ads_cpld.c | 14 +-
arch/powerpc/platforms/52xx/media5200.c | 21 ++--
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 26 ++--
arch/powerpc/platforms/52xx/mpc52xx_pic.c | 80 +++++++-------
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 27 ++---
arch/powerpc/platforms/85xx/ksi8560.c | 3 +-
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 3 +-
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 3 +-
arch/powerpc/platforms/85xx/sbc8560.c | 3 +-
arch/powerpc/platforms/85xx/socrates_fpga_pic.c | 40 ++++----
arch/powerpc/platforms/85xx/stx_gp3.c | 3 +-
arch/powerpc/platforms/85xx/tqm85xx.c | 3 +-
arch/powerpc/platforms/86xx/gef_pic.c | 22 ++--
arch/powerpc/platforms/86xx/pic.c | 5 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 9 +-
arch/powerpc/platforms/cell/axon_msi.c | 3 +-
arch/powerpc/platforms/cell/beat_interrupt.c | 36 +++---
arch/powerpc/platforms/cell/interrupt.c | 30 +++--
arch/powerpc/platforms/cell/setup.c | 6 +-
arch/powerpc/platforms/cell/spider-pic.c | 43 ++++----
arch/powerpc/platforms/chrp/setup.c | 5 +-
arch/powerpc/platforms/embedded6xx/flipper-pic.c | 32 +++---
arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 41 ++++----
arch/powerpc/platforms/iseries/irq.c | 43 ++++---
arch/powerpc/platforms/pasemi/setup.c | 4 +-
arch/powerpc/platforms/powermac/pic.c | 48 ++++----
arch/powerpc/platforms/ps3/interrupt.c | 40 ++++----
arch/powerpc/platforms/pseries/setup.c | 5 +-
arch/powerpc/platforms/pseries/xics.c | 89 ++++++++-------
arch/powerpc/sysdev/cpm1.c | 18 ++--
arch/powerpc/sysdev/cpm2_pic.c | 32 +++---
arch/powerpc/sysdev/fsl_msi.c | 19 ++--
arch/powerpc/sysdev/i8259.c | 42 ++++----
arch/powerpc/sysdev/ipic.c | 54 +++++-----
arch/powerpc/sysdev/mpc8xx_pic.c | 32 +++---
arch/powerpc/sysdev/mpc8xxx_gpio.c | 42 ++++----
arch/powerpc/sysdev/mpic.c | 131 +++++++++++-----------
arch/powerpc/sysdev/mpic.h | 5 +-
arch/powerpc/sysdev/mpic_pasemi_msi.c | 18 ++--
arch/powerpc/sysdev/mpic_u3msi.c | 18 ++--
arch/powerpc/sysdev/mv64x60_pic.c | 46 ++++----
arch/powerpc/sysdev/qe_lib/qe_ic.c | 20 ++--
arch/powerpc/sysdev/tsi108_pci.c | 41 +++----
arch/powerpc/sysdev/uic.c | 59 +++++-----
arch/powerpc/sysdev/xilinx_intc.c | 48 ++++----
50 files changed, 722 insertions(+), 660 deletions(-)
--
1.7.4
^ permalink raw reply
* Re: Mpc8315erdb openvpn segmentation fault
From: Scott Wood @ 2011-03-07 20:22 UTC (permalink / raw)
To: Vasanth Ragavendran; +Cc: linuxppc-dev
In-Reply-To: <31086738.post@talk.nabble.com>
On Mon, 7 Mar 2011 03:09:27 -0800
Vasanth Ragavendran <ragavendrapec@yahoo.co.in> wrote:
>
> i'm facing a problem. i've installed openvpn on mpc8315erdb board and when i
> give the command
>
> openvpn --mktun --dev tap0 i get the error
>
>
>
> [root@mpc8315erdb /]# openvpn --mktun --dev tap0
> Sat Jan 1 01:04:21 2000 OpenVPNUnable to handle kernel paging request for
> data
> at address 0x00000000
> 2.0.9 ppc-rpm-lFaulting instruction address: 0xc90a208c
> inux-gnu [SSL] [Oops: Kernel access of bad area, sig: 11 [#1]
> MPC831x RDB
> Modules linked in: tun
> **bleep**: c90a208c LR: c90a2068 CTR: c0288e58
> REGS: c294fd80 TRAP: 0300 Not tainted (2.6.29.6)
> MSR: 00009032 <EE,ME,IR,DR> CR: 24002424 XER: 20000000
> DAR: 00000000, DSISR: 20000000
> TASK = c70b6440[1635] 'openvpn' THREAD: c294e000
> GPR00: 00000001 c294fe30 c70b6440 c03ebcf4 bfafa0d4 0000001c c294fe58
> 0fd8dc58
> GPR08: 00000000 00000001 ffffffe7 00000000 84002428 100787e0 07ff9000
> 00000004
> GPR16: 00000000 00000000 bfafa930 00010000 00010000 ffffffff 00000005
> 3b9aca00
> GPR24: c7023d20 c294fe3c bfafa0b8 c653e6e0 00000000 c040baf4 bfafa0b8
> 800454ca
> Call Trace:
> [c294fe30] [c90a2068] 0xc90a2068 (unreliable)
> [c294fe90] [c008054c] 0xc008054c
> [c294fea0] [c00809c4] 0xc00809c4
> [c294ff10] [c0080c9c] 0xc0080c9c
> [c294ff40] [c001141c] 0xc001141c
> --- Exception: c01 at 0xfce8268
> LR = 0xfd6bdec
> Instruction dump:
> 4bfffecc 9b81001b 480008ed 3d20c90a 38000001 8129306c 81620308 2f890000
> 830201a4 83ab0014 817d0124 419e0014 <800b0000> 7c090010 7c000110 7c0000d0
> LZO] [EPOLL] bui---[ end trace 54eee2a93ccf53d1 ]---
> lt on Mar 2 2011
> Sat Jan 1 01:04:21 2000 IMPORTANT: OpenVPN's default port number is now
> 1194, b
> ased on an official port number assignment by IANA. OpenVPN 2.0-beta16 and
> earl
> ier used 5000 as the default port.
> Sat Jan 1 01:04:21 2000 ******* WARNING *******: all encryption and
> authenticat
> ion features disabled -- all data will be tunnelled as cleartext
> Segmentation fault
>
>
>
> Some one plz help me out! wat does this mean? Coz with the same kernel image
> and the same settings i'm able to successfully run the above command on
> another mpc8315erdb board. but it fails on one of the board! any ideas would
> be of great help to me!! plz!
Please turn on CONFIG_KALLSYMS, so that symbols will be reported in the
crash dump, and let us know which kernel you're using.
Are the other boards where it does not fail running the same kernel? Same
userspace? Same U-Boot? Anything else different?
-Scott
^ permalink raw reply
* Mpc8315erdb openvpn segmentation fault
From: Vasanth Ragavendran @ 2011-03-07 11:09 UTC (permalink / raw)
To: linuxppc-dev
i'm facing a problem. i've installed openvpn on mpc8315erdb board and when i
give the command
openvpn --mktun --dev tap0 i get the error
[root@mpc8315erdb /]# openvpn --mktun --dev tap0
Sat Jan 1 01:04:21 2000 OpenVPNUnable to handle kernel paging request for
data
at address 0x00000000
2.0.9 ppc-rpm-lFaulting instruction address: 0xc90a208c
inux-gnu [SSL] [Oops: Kernel access of bad area, sig: 11 [#1]
MPC831x RDB
Modules linked in: tun
**bleep**: c90a208c LR: c90a2068 CTR: c0288e58
REGS: c294fd80 TRAP: 0300 Not tainted (2.6.29.6)
MSR: 00009032 <EE,ME,IR,DR> CR: 24002424 XER: 20000000
DAR: 00000000, DSISR: 20000000
TASK = c70b6440[1635] 'openvpn' THREAD: c294e000
GPR00: 00000001 c294fe30 c70b6440 c03ebcf4 bfafa0d4 0000001c c294fe58
0fd8dc58
GPR08: 00000000 00000001 ffffffe7 00000000 84002428 100787e0 07ff9000
00000004
GPR16: 00000000 00000000 bfafa930 00010000 00010000 ffffffff 00000005
3b9aca00
GPR24: c7023d20 c294fe3c bfafa0b8 c653e6e0 00000000 c040baf4 bfafa0b8
800454ca
Call Trace:
[c294fe30] [c90a2068] 0xc90a2068 (unreliable)
[c294fe90] [c008054c] 0xc008054c
[c294fea0] [c00809c4] 0xc00809c4
[c294ff10] [c0080c9c] 0xc0080c9c
[c294ff40] [c001141c] 0xc001141c
--- Exception: c01 at 0xfce8268
LR = 0xfd6bdec
Instruction dump:
4bfffecc 9b81001b 480008ed 3d20c90a 38000001 8129306c 81620308 2f890000
830201a4 83ab0014 817d0124 419e0014 <800b0000> 7c090010 7c000110 7c0000d0
LZO] [EPOLL] bui---[ end trace 54eee2a93ccf53d1 ]---
lt on Mar 2 2011
Sat Jan 1 01:04:21 2000 IMPORTANT: OpenVPN's default port number is now
1194, b
ased on an official port number assignment by IANA. OpenVPN 2.0-beta16 and
earl
ier used 5000 as the default port.
Sat Jan 1 01:04:21 2000 ******* WARNING *******: all encryption and
authenticat
ion features disabled -- all data will be tunnelled as cleartext
Segmentation fault
Some one plz help me out! wat does this mean? Coz with the same kernel image
and the same settings i'm able to successfully run the above command on
another mpc8315erdb board. but it fails on one of the board! any ideas would
be of great help to me!! plz!
--
View this message in context: http://old.nabble.com/Mpc8315erdb-openvpn-segmentation-fault-tp31086738p31086738.html
Sent from the linuxppc-dev mailing list archive at Nabble.com.
^ permalink raw reply
* Re: vmsplice bad address
From: Benjamin Herrenschmidt @ 2011-03-07 9:35 UTC (permalink / raw)
To: Guillaume Dargaud; +Cc: Linuxppc-dev
In-Reply-To: <201103031401.55649.dargaud@lpsc.in2p3.fr>
On Thu, 2011-03-03 at 14:01 +0100, Guillaume Dargaud wrote:
> Hello all,
> I'm trying to use the vmsplice/splice combination to so socket writes in zero-copy mode since it seems to be the big
> bottle neck in my application.
>
> Here's a simplified code:
>
> // This buffer is actually outside kernel space,
> // in reserved contiguous physical memory (custom kernel compilation)
> #define BUFFER_PHY_BASE 0x7000000
> #define BUFFER_SIZE 0x1000000
> memfd=open("/dev/mem", O_RDWR | O_SYNC)
> Base=(unsigned char*)mmap(0, BUFFER_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, memfd, BUFFER_PHY_BASE);
>
> sockfd = socket(AF_INET, SOCK_STREAM, 0)
>
> int pfd[2]; pipe(pfd);
>
> struct iovec iov;
> iov.iov_base=Base;
> iov.iov_len=BUFFER_SIZE;
> printf("Pipe %d/%d, base:0x%x, size:0x%x\n", pfd[0], pfd[1], iov.iov_base, iov.iov_len);
> vmsplice(pfd[1], &iov, 1, SPLICE_F_GIFT)
> splice(pfd[0], NULL, sockfd, NULL, BUFFER_SIZE, SPLICE_F_MOVE)
>
> I get the following:
> Pipe 6/7, base:0x480cf000, size:0x1000000
> vmsplice: Bad address
>
>
> Any idea what is wrong in my use of vmsplice ?
I'm not completely surprised ... I wouldn't expect vmsplice to work
on /dev/mem ... No struct page backing the memory for example.
Ben.
^ permalink raw reply
* [PATCH] driver/FSL SATA: Update RX_WATER_MARK for TRANSCFG
From: Prabhakar Kushwaha @ 2011-03-07 4:29 UTC (permalink / raw)
To: linux-ide; +Cc: meet2prabhu, jgarzik, linuxppc-dev, Prabhakar Kushwaha
RX_WATER_MARK sets the number of locations in Rx FIFO that can be used before
the transport layer instructs the link layer to transmit HOLDS. Note that it
can take some time for the HOLDs to get to the other end, and that in the
interim there must be enough room in the FIFO to absorb all data that could
arrive.
Update the new recommended value to 16.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch master)
This patch is already gone through review of linuxppc-dev mail list.
Making CC linuxppc-dev@lists.ozlabs.org
drivers/ata/sata_fsl.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index 895771c..29d2f29 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -186,6 +186,11 @@ enum {
COMMANDSTAT = 0x20,
};
+/* TRANSCFG (transport-layer) configuration control */
+enum {
+ TRANSCFG_RX_WATER_MARK = (1 << 4),
+};
+
/* PHY (link-layer) configuration control */
enum {
PHY_BIST_ENABLE = 0x01,
@@ -1305,6 +1310,7 @@ static int sata_fsl_probe(struct platform_device *ofdev,
struct sata_fsl_host_priv *host_priv = NULL;
int irq;
struct ata_host *host;
+ u32 temp;
struct ata_port_info pi = sata_fsl_port_info[0];
const struct ata_port_info *ppi[] = { &pi, NULL };
@@ -1319,6 +1325,12 @@ static int sata_fsl_probe(struct platform_device *ofdev,
ssr_base = hcr_base + 0x100;
csr_base = hcr_base + 0x140;
+ if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
+ temp = ioread32(csr_base + TRANSCFG);
+ temp = temp & 0xffffffe0;
+ iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
+ }
+
DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
--
1.7.3
^ permalink raw reply related
* [PATCH] driver/FSL SATA:Fix wrong Device Error Register usage
From: Prabhakar Kushwaha @ 2011-03-07 4:30 UTC (permalink / raw)
To: linux-ide
Cc: meet2prabhu, Ashish Kalra, jgarzik, linuxppc-dev,
Prabhakar Kushwaha
When a single device error is detected, the device under the error is indicated
by the error bit set in the DER. There is a one to one mapping between register
bit and devices on Port multiplier(PMP) i.e. bit 0 represents PMP device 0 and
bit 1 represents PMP device 1 etc.
Current implementation treats Device error register value as device number not
set of bits representing multiple device on PMP. It is changed to consider bit
level.
No need to check for each set bit as all command is going to be aborted.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Ashish Kalra <B00888@freescale.com>
---
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch master)
This patch is already gone through review of linuxppc-dev mail list.
Making CC linuxppc-dev@lists.ozlabs.org
drivers/ata/sata_fsl.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index b0214d0..895771c 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -1040,12 +1040,14 @@ static void sata_fsl_error_intr(struct ata_port *ap)
/* find out the offending link and qc */
if (ap->nr_pmp_links) {
+ unsigned int dev_num;
dereg = ioread32(hcr_base + DE);
iowrite32(dereg, hcr_base + DE);
iowrite32(cereg, hcr_base + CE);
- if (dereg < ap->nr_pmp_links) {
- link = &ap->pmp_link[dereg];
+ dev_num = ffs(dereg)-1;
+ if (dev_num < ap->nr_pmp_links) {
+ link = &ap->pmp_link[dev_num];
ehi = &link->eh_info;
qc = ata_qc_from_tag(ap, link->active_tag);
/*
--
1.7.3
^ permalink raw reply related
* [PATCH] powerpc/mm: Move the STAB0 location to 0x8000 to make room in low memory
From: Benjamin Herrenschmidt @ 2011-03-07 4:09 UTC (permalink / raw)
To: linuxppc-dev
Recent linux-next builds with allmodconfig fail due to lack of space
between 0x3000 and 0x6000. We have a hard block at 0x7000 but we can
spare a page by moving the STAB0 from 0x6000 to 0x8000.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Seems to still boot on legacy iSeries...
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index acac35d..ae7b3ef 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -27,7 +27,7 @@
#define STE_VSID_SHIFT 12
/* Location of cpu0's segment table */
-#define STAB0_PAGE 0x6
+#define STAB0_PAGE 0x8
#define STAB0_OFFSET (STAB0_PAGE << 12)
#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 8a81799..70f0f99 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -977,20 +977,6 @@ _GLOBAL(do_stab_bolted)
rfid
b . /* prevent speculative execution */
-/*
- * Space for CPU0's segment table.
- *
- * On iSeries, the hypervisor must fill in at least one entry before
- * we get control (with relocate on). The address is given to the hv
- * as a page number (see xLparMap below), so this must be at a
- * fixed address (the linker can't compute (u64)&initial_stab >>
- * PAGE_SHIFT).
- */
- . = STAB0_OFFSET /* 0x6000 */
- .globl initial_stab
-initial_stab:
- .space 4096
-
#ifdef CONFIG_PPC_PSERIES
/*
* Data area reserved for FWNMI option.
@@ -1027,3 +1013,18 @@ xLparMap:
#ifdef CONFIG_PPC_PSERIES
. = 0x8000
#endif /* CONFIG_PPC_PSERIES */
+
+/*
+ * Space for CPU0's segment table.
+ *
+ * On iSeries, the hypervisor must fill in at least one entry before
+ * we get control (with relocate on). The address is given to the hv
+ * as a page number (see xLparMap above), so this must be at a
+ * fixed address (the linker can't compute (u64)&initial_stab >>
+ * PAGE_SHIFT).
+ */
+ . = STAB0_OFFSET /* 0x8000 */
+ .globl initial_stab
+initial_stab:
+ .space 4096
+
^ permalink raw reply related
* [PATCH] powerpc/iseries: Fix early init access to lppaca
From: Benjamin Herrenschmidt @ 2011-03-07 4:02 UTC (permalink / raw)
To: linuxppc-dev
The combination of commit
8154c5d22d91cd16bd9985b0638c8957e4688d0e and
93c22703efa72c7527dbd586d1951c1f4a85fd70
Broke boot on iSeries.
The problem is that iSeries very early boot code, which generates
the device-tree and runs before our normal early initializations
does need access the lppaca's very early, before the PACA array is
initialized, and in fact even before the boot PACA has been
initialized (it contains all 0's at this stage).
However, the first patch above makes that code use the new
llpaca_of(cpu) accessor, which itself is changed by the second patch to
use the PACA array.
We fix that by reverting iSeries to directly dereferencing the array. In
addition, we fix all iterators in the iSeries code to always skip CPU
whose number is above 63 which is the maximum size of that array and
the maximum number of supported CPUs on these machines.
Additionally, we make sure the boot_paca is properly initialized
in our early startup code.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index 380d48b..26b8c80 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -33,9 +33,25 @@
//
//----------------------------------------------------------------------------
#include <linux/cache.h>
+#include <linux/threads.h>
#include <asm/types.h>
#include <asm/mmu.h>
+/*
+ * We only have to have statically allocated lppaca structs on
+ * legacy iSeries, which supports at most 64 cpus.
+ */
+#ifdef CONFIG_PPC_ISERIES
+#if NR_CPUS < 64
+#define NR_LPPACAS NR_CPUS
+#else
+#define NR_LPPACAS 64
+#endif
+#else /* not iSeries */
+#define NR_LPPACAS 1
+#endif
+
+
/* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k
* alignment is sufficient to prevent this */
struct lppaca {
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index ebf9846..f4adf89 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -27,20 +27,6 @@ extern unsigned long __toc_start;
#ifdef CONFIG_PPC_BOOK3S
/*
- * We only have to have statically allocated lppaca structs on
- * legacy iSeries, which supports at most 64 cpus.
- */
-#ifdef CONFIG_PPC_ISERIES
-#if NR_CPUS < 64
-#define NR_LPPACAS NR_CPUS
-#else
-#define NR_LPPACAS 64
-#endif
-#else /* not iSeries */
-#define NR_LPPACAS 1
-#endif
-
-/*
* The structure which the hypervisor knows about - this structure
* should not cross a page boundary. The vpa_init/register_vpa call
* is now known to fail if the lppaca structure crosses a page
diff --git a/arch/powerpc/platforms/iseries/dt.c b/arch/powerpc/platforms/iseries/dt.c
index fdb7384..f0491cc 100644
--- a/arch/powerpc/platforms/iseries/dt.c
+++ b/arch/powerpc/platforms/iseries/dt.c
@@ -242,8 +242,8 @@ static void __init dt_cpus(struct iseries_flat_dt *dt)
pft_size[0] = 0; /* NUMA CEC cookie, 0 for non NUMA */
pft_size[1] = __ilog2(HvCallHpt_getHptPages() * HW_PAGE_SIZE);
- for (i = 0; i < NR_CPUS; i++) {
- if (lppaca_of(i).dyn_proc_status >= 2)
+ for (i = 0; i < NR_LPPACAS; i++) {
+ if (lppaca[i].dyn_proc_status >= 2)
continue;
snprintf(p, 32 - (p - buf), "@%d", i);
@@ -251,7 +251,7 @@ static void __init dt_cpus(struct iseries_flat_dt *dt)
dt_prop_str(dt, "device_type", device_type_cpu);
- index = lppaca_of(i).dyn_hv_phys_proc_index;
+ index = lppaca[i].dyn_hv_phys_proc_index;
d = &xIoHriProcessorVpd[index];
dt_prop_u32(dt, "i-cache-size", d->xInstCacheSize * 1024);
diff --git a/arch/powerpc/platforms/iseries/setup.c b/arch/powerpc/platforms/iseries/setup.c
index b086341..2946ae1 100644
--- a/arch/powerpc/platforms/iseries/setup.c
+++ b/arch/powerpc/platforms/iseries/setup.c
@@ -680,6 +680,7 @@ void * __init iSeries_early_setup(void)
* on but calling this function multiple times is fine.
*/
identify_cpu(0, mfspr(SPRN_PVR));
+ initialise_paca(&boot_paca, 0);
powerpc_firmware_features |= FW_FEATURE_ISERIES;
powerpc_firmware_features |= FW_FEATURE_LPAR;
^ permalink raw reply related
* Re: [PATCH] fsl_pci: Add support for FSL PCIe controllers v2.x
From: Kumar Gala @ 2011-03-05 21:29 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: meet2prabhu, linuxppc-dev
In-Reply-To: <1298540104-16545-1-git-send-email-prabhakar@freescale.com>
On Feb 24, 2011, at 3:35 AM, Prabhakar Kushwaha wrote:
> FSL PCIe controller v2.1:
> - New MSI inbound window
> - Same Inbound windows address as PCIe controller v1.x
>=20
> Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
>=20
> FSL PCIe controller v2.2 and v2.3:
> - Different addresses for PCIe inbound window 3,2,1
> - Exposed PCIe inbound window 0
> - New PCIe interrupt status register
>=20
> Added new config and interrupt Status register to struct ccsr_pci & =
updated
> pit_t array size to reflect the 4 inbound windows.
>=20
> Device tree is used to maintain backward compatibility i.e. update =
inbound
> window 1 index depending upon "compatible" field witin PCIE node.
>=20
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
> Acked-by: Kumar Gala <kumar.gala@freescale.com>
> ---
>=20
> Based upon =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git =
(branch master )
>=20
> arch/powerpc/sysdev/fsl_pci.c | 15 +++++++++++----
> arch/powerpc/sysdev/fsl_pci.h | 17 ++++++++++-------
> 2 files changed, 21 insertions(+), 11 deletions(-)
applied to next
- k=
^ permalink raw reply
* [PATCH] powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e
From: Kumar Gala @ 2011-03-05 21:05 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Kumar Gala
From: Kumar Gala <kumar.gala@freescale.com>
If the spin table is located in the linear mapping (which can happen if
we have 4G or more of memory) we need to access the spin table via a
cacheable coherent mapping like we do on ppc32 (and do explicit cache
flush).
See the following commit for the ppc32 version of this issue:
commit d1d47ec6e62ab08d2ebb925fd9203abfad3adfbf
Author: Peter Tyser <ptyser@xes-inc.com>
Date: Fri Dec 18 16:50:37 2009 -0600
powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmem
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/platforms/85xx/smp.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 5c91a99..0d00ff9 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -91,10 +91,14 @@ smp_85xx_kick_cpu(int nr)
while ((__secondary_hold_acknowledge != nr) && (++n < 1000))
mdelay(1);
#else
+ smp_generic_kick_cpu(nr);
+
out_be64((u64 *)(bptr_vaddr + BOOT_ENTRY_ADDR_UPPER),
__pa((u64)*((unsigned long long *) generic_secondary_smp_init)));
- smp_generic_kick_cpu(nr);
+ if (!ioremappable)
+ flush_dcache_range((ulong)bptr_vaddr,
+ (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY));
#endif
local_irq_restore(flags);
--
1.7.2.3
^ permalink raw reply related
* [PATCH] powerpc/pseries: Enable Chelsio network and iWARP drivers
From: Anton Blanchard @ 2011-03-05 12:00 UTC (permalink / raw)
To: benh, linuxppc-dev
Ensure the Chelsio T3/T4 network drivers and iWARP drivers are
enabled in the pseries config.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: linux-2.6/arch/powerpc/configs/pseries_defconfig
===================================================================
--- linux-2.6.orig/arch/powerpc/configs/pseries_defconfig 2011-03-05 22:58:38.886562678 +1100
+++ linux-2.6/arch/powerpc/configs/pseries_defconfig 2011-03-05 22:58:40.346615219 +1100
@@ -189,6 +189,7 @@ CONFIG_TIGON3=y
CONFIG_BNX2=m
CONFIG_CHELSIO_T1=m
CONFIG_CHELSIO_T3=m
+CONFIG_CHELSIO_T4=m
CONFIG_EHEA=y
CONFIG_IXGBE=m
CONFIG_IXGB=m
@@ -255,6 +256,8 @@ CONFIG_INFINIBAND_USER_MAD=m
CONFIG_INFINIBAND_USER_ACCESS=m
CONFIG_INFINIBAND_MTHCA=m
CONFIG_INFINIBAND_EHCA=m
+CONFIG_INFINIBAND_CXGB3=m
+CONFIG_INFINIBAND_CXGB4=m
CONFIG_MLX4_INFINIBAND=m
CONFIG_INFINIBAND_IPOIB=m
CONFIG_INFINIBAND_IPOIB_CM=y
^ permalink raw reply
* Re: [PATCH v4 2/2] add icswx support
From: Benjamin Herrenschmidt @ 2011-03-04 23:13 UTC (permalink / raw)
To: Tseng-Hui (Frank) Lin; +Cc: tsenglin, linuxppc-dev
In-Reply-To: <1299280053.28840.96.camel@flin.austin.ibm.com>
On Fri, 2011-03-04 at 17:07 -0600, Tseng-Hui (Frank) Lin wrote:
> I don't have any measurable numbers. That's why I made it an option in
> case people wants to disable it. I do agree that the kernel has so many
> options that we should refrain from adding more. If the chance that the
> lazy switching slows down the execution is really low, we should just
> take out the option. Is there any one has an idea how much the numbers
> are?
Well, per-cpu loads are notoriously inefficient due to nasty codegen,
but often cache hot as well, I wouldn't worry too much. Just remove the
option for now. We can always add it back if it ever becomes desirable,
but I very much doubt it.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v3 0/9] fsldma: lockup fixes
From: Felix Radensky @ 2011-03-04 22:28 UTC (permalink / raw)
To: Ira W. Snyder, linuxppc-dev
In-Reply-To: <1299174901-16762-1-git-send-email-iws@ovro.caltech.edu>
Hi Ira,
I've successfully tested this version on P2020RDB,
with 10 threads per channel, 100000 iterations per
thread.
Tested-by: Felix Radensky <felix@embedded-sol.com>
Felix.
^ permalink raw reply
* Re: [PATCH v4 2/2] add icswx support
From: Tseng-Hui (Frank) Lin @ 2011-03-04 23:07 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: tsenglin, linuxppc-dev
In-Reply-To: <1299278441.8833.915.camel@pasglop>
On Sat, 2011-03-05 at 09:40 +1100, Benjamin Herrenschmidt wrote:
> > The lazy switching checks the shadow variable first before setting ACOP
> > register. This saves mtspr() only if the new value is the same as
> > current. If there are several coprocessors on the system, the ACOP
> > register may have to be changed frequently. In that case, the lazy
> > switching will not save time. In extreme case when the ACOP register
> > needs to be changed every time, it actually slows down the execution by
> > the additional shadow variable checking.
>
> By how much ? Is it even measurable ?
>
I don't have any measurable numbers. That's why I made it an option in
case people wants to disable it. I do agree that the kernel has so many
options that we should refrain from adding more. If the chance that the
lazy switching slows down the execution is really low, we should just
take out the option. Is there any one has an idea how much the numbers
are?
> Cheers,
> Ben.
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH] Fix masking of interrupts for 52xx GPT IRQ.
From: Benjamin Herrenschmidt @ 2011-03-04 22:41 UTC (permalink / raw)
To: Henk Stegeman; +Cc: linuxppc-dev
In-Reply-To: <AANLkTi=Wq_uF14TXWQ3ooOpbkroJfM_DOWZXJfCWDHcX@mail.gmail.com>
On Fri, 2011-03-04 at 23:40 +0100, Henk Stegeman wrote:
> What if the unmask/mask functions are dropped and only interrupt
> enable/disable functions are provided?
No, that's backward. enable/disable are handled by the core, leave them
there.
> I.e: rename the old unmask/mask functions to enable/disable and
> register them as enable/disable? I did try that, and it works too, no
> spurious IRQ's and no missing IRQ's.
>
Ben.
^ permalink raw reply
* Re: [PATCH v4 2/2] add icswx support
From: Benjamin Herrenschmidt @ 2011-03-04 22:40 UTC (permalink / raw)
To: Tseng-Hui (Frank) Lin; +Cc: tsenglin, linuxppc-dev
In-Reply-To: <1299277344.28840.79.camel@flin.austin.ibm.com>
On Fri, 2011-03-04 at 16:22 -0600, Tseng-Hui (Frank) Lin wrote:
> > Well, I don't know how you use icswx on P7+, but on Prism it's
> > definitely issued directly by userspace.
> >
> OK. You've got a point. I wasn't aware of Prism. HFI device driver is
> currently the only icswx user on P7. Could you point me to more
> information about how Prism uses icswx from user space?
Let's ignore that for now, there's a whole infrastructure for it and it
hasn't been published yet, maybe later this year... We can look at
exposing the feature to userspace then.
> > You don't need to. You allocate and initialize the structure, and you
> > compare & swap the pointer. If somebody beat you, you trash your copy.
> >
> Is atomic_cmpxchg() the one to do the trick?
No, just cmpxchg()
> The lazy switching checks the shadow variable first before setting ACOP
> register. This saves mtspr() only if the new value is the same as
> current. If there are several coprocessors on the system, the ACOP
> register may have to be changed frequently. In that case, the lazy
> switching will not save time. In extreme case when the ACOP register
> needs to be changed every time, it actually slows down the execution by
> the additional shadow variable checking.
By how much ? Is it even measurable ?
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] Fix masking of interrupts for 52xx GPT IRQ.
From: Henk Stegeman @ 2011-03-04 22:40 UTC (permalink / raw)
To: Grant Likely, Benjamin Herrenschmidt, linuxppc-dev
In-Reply-To: <AANLkTim8W6np1A1d=SKFNS5ze8FmrbUekoZaY8_a=46A@mail.gmail.com>
What if the unmask/mask functions are dropped and only interrupt
enable/disable functions are provided?
I.e: rename the old unmask/mask functions to enable/disable and
register them as enable/disable? I did try that, and it works too, no
spurious IRQ's and no missing IRQ's.
Cheers,
Henk.
On Wed, Mar 2, 2011 at 10:30 PM, Grant Likely <grant.likely@secretlab.ca> w=
rote:
> [fixed top-posted reply]
>
> On Wed, Feb 9, 2011 at 3:16 AM, Henk Stegeman <henk.stegeman@gmail.com> w=
rote:
>> On Mon, Feb 7, 2011 at 12:05 AM, Benjamin Herrenschmidt
>> <benh@kernel.crashing.org> wrote:
>>> On Sat, 2011-01-15 at 02:28 +0100, Henk Stegeman wrote:
>>>> When using the GPT as interrupt controller interupts were missing.
>>>> It turned out the IrqEn bit of the GPT is not a mask bit, but it also
>>>> disables interrupt generation. This modification masks interrupt one
>>>> level down the cascade. Note that masking one level down the cascade
>>>> is only valid here because the GPT as interrupt ontroller only serves
>>>> one IRQ.
>>>
>>> I'm not too sure here... You shouldn't implemen t both mask/unmask and
>>> enable/disable on the same irq_chip and certainly not cal
>>> enable_irq/disable_irq from a mask or an unmask callback...
>>>
>>> Now, I'm not familiar with the HW here, can you tell me more about what
>>> exactly is happening, how things are layed out and what you are trying
>>> to fix ?
>>>
> [...]
>> Because the old code in the unmask/mask function did enable/disable
>> and I didn't want to just drop that code, I provided it via the
>> enable/disable function.
>> What is wrong by implementing & registering both mask/unmask and
>> enable/disable for the same irq_chip?
>> If it is wrong it would be nice to let the kernel print a big fat
>> warning when this is registered.
>
> After some digging, yes Ben is right. =A0It doesn't make much sense to
> provide an enable/disable function along with the mask/unmask. =A0I
> think you can safely drop the old enable/disable code. =A0I'm going to
> drop this patch from my tree and you can respin and retest.
>
> g.
>
>>
>> Cheers,
>>
>> Henk
>>
>
>>>
>>>> Signed-off-by: Henk Stegeman <henk.stegeman@gmail.com>
>>>> ---
>>>> =A0arch/powerpc/platforms/52xx/mpc52xx_gpt.c | =A0 25 ++++++++++++++++=
++++++---
>>>> =A01 files changed, 22 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/=
platforms/52xx/mpc52xx_gpt.c
>>>> index 6f8ebe1..9ae2045 100644
>>>> --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
>>>> +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
>>>> @@ -91,7 +91,7 @@ struct mpc52xx_gpt_priv {
>>>> =A0 =A0 =A0 struct irq_host *irqhost;
>>>> =A0 =A0 =A0 u32 ipb_freq;
>>>> =A0 =A0 =A0 u8 wdt_mode;
>>>> -
>>>> + =A0 =A0 int cascade_virq;
>>>> =A0#if defined(CONFIG_GPIOLIB)
>>>> =A0 =A0 =A0 struct of_gpio_chip of_gc;
>>>> =A0#endif
>>>> @@ -136,18 +136,35 @@ DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
>>>> =A0static void mpc52xx_gpt_irq_unmask(unsigned int virq)
>>>> =A0{
>>>> =A0 =A0 =A0 struct mpc52xx_gpt_priv *gpt =3D get_irq_chip_data(virq);
>>>> +
>>>> + =A0 =A0 enable_irq(gpt->cascade_virq);
>>>> +
>>>> +}
>>>> +
>>>> +static void mpc52xx_gpt_irq_mask(unsigned int virq)
>>>> +{
>>>> + =A0 =A0 struct mpc52xx_gpt_priv *gpt =3D get_irq_chip_data(virq);
>>>> +
>>>> + =A0 =A0 disable_irq(gpt->cascade_virq);
>>>> +}
>>>> +
>>>> +static void mpc52xx_gpt_irq_enable(unsigned int virq)
>>>> +{
>>>> + =A0 =A0 struct mpc52xx_gpt_priv *gpt =3D get_irq_chip_data(virq);
>>>> =A0 =A0 =A0 unsigned long flags;
>>>>
>>>> + =A0 =A0 dev_dbg(gpt->dev, "%s %d\n", __func__, virq);
>>>> =A0 =A0 =A0 spin_lock_irqsave(&gpt->lock, flags);
>>>> =A0 =A0 =A0 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
>>>> =A0 =A0 =A0 spin_unlock_irqrestore(&gpt->lock, flags);
>>>> =A0}
>>>>
>>>> -static void mpc52xx_gpt_irq_mask(unsigned int virq)
>>>> +static void mpc52xx_gpt_irq_disable(unsigned int virq)
>>>> =A0{
>>>> =A0 =A0 =A0 struct mpc52xx_gpt_priv *gpt =3D get_irq_chip_data(virq);
>>>> =A0 =A0 =A0 unsigned long flags;
>>>>
>>>> + =A0 =A0 dev_dbg(gpt->dev, "%s %d\n", __func__, virq);
>>>> =A0 =A0 =A0 spin_lock_irqsave(&gpt->lock, flags);
>>>> =A0 =A0 =A0 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
>>>> =A0 =A0 =A0 spin_unlock_irqrestore(&gpt->lock, flags);
>>>> @@ -184,6 +201,8 @@ static struct irq_chip mpc52xx_gpt_irq_chip =3D {
>>>> =A0 =A0 =A0 .name =3D "MPC52xx GPT",
>>>> =A0 =A0 =A0 .unmask =3D mpc52xx_gpt_irq_unmask,
>>>> =A0 =A0 =A0 .mask =3D mpc52xx_gpt_irq_mask,
>>>> + =A0 =A0 .enable =3D mpc52xx_gpt_irq_enable,
>>>> + =A0 =A0 .disable =3D mpc52xx_gpt_irq_disable,
>>>> =A0 =A0 =A0 .ack =3D mpc52xx_gpt_irq_ack,
>>>> =A0 =A0 =A0 .set_type =3D mpc52xx_gpt_irq_set_type,
>>>> =A0};
>>>> @@ -268,7 +287,7 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt=
, struct device_node *node)
>>>> =A0 =A0 =A0 if ((mode & MPC52xx_GPT_MODE_MS_MASK) =3D=3D 0)
>>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_be32(&gpt->regs->mode, mode | MPC52xx_=
GPT_MODE_MS_IC);
>>>> =A0 =A0 =A0 spin_unlock_irqrestore(&gpt->lock, flags);
>>>> -
>>>> + =A0 =A0 gpt->cascade_virq =3D cascade_virq;
>>>> =A0 =A0 =A0 dev_dbg(gpt->dev, "%s() complete. virq=3D%i\n", __func__, =
cascade_virq);
>>>> =A0}
>>>>
>>>
>>>
>>>
>>
>
>
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>
^ permalink raw reply
* Re: [PATCH v4 2/2] add icswx support
From: Tseng-Hui (Frank) Lin @ 2011-03-04 22:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: tsenglin, linuxppc-dev
In-Reply-To: <1299270417.8833.897.camel@pasglop>
On Sat, 2011-03-05 at 07:26 +1100, Benjamin Herrenschmidt wrote:
> On Fri, 2011-03-04 at 11:29 -0600, Tseng-Hui (Frank) Lin wrote:
> > On Fri, 2011-03-04 at 12:02 +1100, Benjamin Herrenschmidt wrote:
> > > On Wed, 2011-03-02 at 11:20 -0600, Tseng-Hui (Frank) Lin wrote:
> > >
> > > > +#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
> > >
> > > Do we want a userspace visible feature as well ? Or some other way to
> > > inform userspace that we support icswx ?
> > >
> > Does a user space program really need to know about icswx? Only
> > coprocessor drivers need to know about icswx. Shouldn't user space
> > programs talk to the coprocessor drivers instead?
>
> Well, I don't know how you use icswx on P7+, but on Prism it's
> definitely issued directly by userspace.
>
OK. You've got a point. I wasn't aware of Prism. HFI device driver is
currently the only icswx user on P7. Could you point me to more
information about how Prism uses icswx from user space?
> > Thought about that. However, multiple threads can call use_cop() at the
> > same time. Without the spinlock being setup in advance, how do I
> > guarantee allocating struct copro_data and modifying the pointer in the
> > mm_context to be atomic?
>
> You don't need to. You allocate and initialize the structure, and you
> compare & swap the pointer. If somebody beat you, you trash your copy.
>
Is atomic_cmpxchg() the one to do the trick?
> > > I'm not sure I totally get the point of having an ifdef here. Can't you
> > > make it unconditional ? Or do you expect distros to turn that off in
> > > which case what's the point ?
> > >
> > There is only one coprocessor, HFI, using icswx at this moment. The lazy
> > switching makes sense. However, in the future, if more types of
> > coprocessors are added, the lazy switching may actually be a bad idea.
> > This option allows users to turn off the lazy switching.
>
> No user in real life plays with kernel config options. Care to explain
> why the lazy switching would be a problem ?
>
The lazy switching checks the shadow variable first before setting ACOP
register. This saves mtspr() only if the new value is the same as
current. If there are several coprocessors on the system, the ACOP
register may have to be changed frequently. In that case, the lazy
switching will not save time. In extreme case when the ACOP register
needs to be changed every time, it actually slows down the execution by
the additional shadow variable checking.
> > Same concern as above. I need something initialized in advance to
> > guarantee allocating memory and updating the pointer are safe when it
> > happens in use_cop().
>
> No you don't, see above.
>
> Cheers,
> Ben.
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH v4 2/2] add icswx support
From: Benjamin Herrenschmidt @ 2011-03-04 20:26 UTC (permalink / raw)
To: Tseng-Hui (Frank) Lin; +Cc: tsenglin, linuxppc-dev
In-Reply-To: <1299259794.28840.57.camel@flin.austin.ibm.com>
On Fri, 2011-03-04 at 11:29 -0600, Tseng-Hui (Frank) Lin wrote:
> On Fri, 2011-03-04 at 12:02 +1100, Benjamin Herrenschmidt wrote:
> > On Wed, 2011-03-02 at 11:20 -0600, Tseng-Hui (Frank) Lin wrote:
> >
> > > +#define CPU_FTR_ICSWX LONG_ASM_CONST(0x1000000000000000)
> >
> > Do we want a userspace visible feature as well ? Or some other way to
> > inform userspace that we support icswx ?
> >
> Does a user space program really need to know about icswx? Only
> coprocessor drivers need to know about icswx. Shouldn't user space
> programs talk to the coprocessor drivers instead?
Well, I don't know how you use icswx on P7+, but on Prism it's
definitely issued directly by userspace.
> Thought about that. However, multiple threads can call use_cop() at the
> same time. Without the spinlock being setup in advance, how do I
> guarantee allocating struct copro_data and modifying the pointer in the
> mm_context to be atomic?
You don't need to. You allocate and initialize the structure, and you
compare & swap the pointer. If somebody beat you, you trash your copy.
> > I'm not sure I totally get the point of having an ifdef here. Can't you
> > make it unconditional ? Or do you expect distros to turn that off in
> > which case what's the point ?
> >
> There is only one coprocessor, HFI, using icswx at this moment. The lazy
> switching makes sense. However, in the future, if more types of
> coprocessors are added, the lazy switching may actually be a bad idea.
> This option allows users to turn off the lazy switching.
No user in real life plays with kernel config options. Care to explain
why the lazy switching would be a problem ?
> Same concern as above. I need something initialized in advance to
> guarantee allocating memory and updating the pointer are safe when it
> happens in use_cop().
No you don't, see above.
Cheers,
Ben.
^ permalink raw reply
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