* Re: any chance to use a modern linux kernel on Pegasos1 G3 ?
From: Gerhard Pircher @ 2011-03-15 20:08 UTC (permalink / raw)
To: Sven Luther; +Cc: ppc.addon, linuxppc-dev, acrux_it
In-Reply-To: <20110315174924.GA24001@z-innov.com>
-------- Original-Nachricht --------
> Datum: Tue, 15 Mar 2011 18:49:24 +0100
> Von: Sven Luther <sven@z-innov.com>
> An: Gerhard Pircher <gerhard_pircher@gmx.net>
> CC: nello martuscielli <ppc.addon@gmail.com>, linuxppc-dev@lists.ozlabs.org, acrux_it@libero.it
> Betreff: Re: any chance to use a modern linux kernel on Pegasos1 G3 ?
> On Tue, Mar 15, 2011 at 06:14:48PM +0100, Gerhard Pircher wrote:
[...]
> > On the other side you mentioned this workaround in
> > arch/ppc/kernel/prom_init.c to me some time ago:
> >
> > unsigned long __init prom_init(int r3, int r4, prom_entry pp) :
> > > node = call_prom("finddevice", 1, 1, "/");
> > > rc = call_prom("getprop", 4, 1, node, "model", model,
> sizeof(model));
> > > if (rc > 0 && !strncmp (model, "Pegasos", 7)
> > > && strncmp (model, "Pegasos2", 8)) {
> > > /* Pegasos 1 has a broken translate method in the OF,
> > > * and furthermore the BATs are mapped 1:1 so the phys
> > > * address calculated above is correct, so let's use
> > > * it directly.
> > > */
> > > } else if (offset == 0) {
> > > /* If we are already running at 0xc0000000, we assume
> we were
> > > * loaded by an OF bootloader which did set a BAT for
> us.
> > > * This breaks OF translate so we force phys to be 0.
> > > */
> > > prom_print("(already at 0xc0000000) phys=0\n");
> > > phys = 0;
> > > } else if (call_prom("getprop", 4, 1, prom_chosen, "mmu",
> > > &prom_mmu, sizeof(prom_mmu)) <= 0) {
> > > prom_print(" no MMU found\n");
> > > } else if (call_prom_ret("call-method", 4, 4, result,
> "translate",
> > > prom_mmu, &_stext, 1) != 0) {
> > > prom_print(" (translate failed)\n");
> > > } else {
> > > /* We assume the phys. address size is 3 cells */
> > > phys = result[2];
> > > }
> >
> > Can anybody comment, if this "broken translate method in the OF" would
> > still be needed for arch/powerpc?
>
> Well, since this is long dead hardware not produced anymore, i don't see
> how the OF could have unbroken itself by moving to powerpc.
>
> It has been age since i looked into this, but to the best of my knowledge
> (and i wrote the above code or at least the earlier versions) it should
> be still broken.
Any idea then, how the workaround can be ported to arch/powerpc/ or if
there is a better one available?
regards,
Gerhard
--
Empfehlen Sie GMX DSL Ihren Freunden und Bekannten und wir
belohnen Sie mit bis zu 50,- Euro! https://freundschaftswerbung.gmx.de
^ permalink raw reply
* [git pull] Please pull powerpc.git next branch
From: Kumar Gala @ 2011-03-15 21:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
The following changes since commit 964a29962c278ddff8a199f23d7c9ef35152a0fe:
powerpc/pseries: Disable MSI using new interface if possible (2011-03-11 14:18:24 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
Anatolij Gustschin (1):
powerpc/mpc8xxx_gpio: simplify searching for 'fsl, qoriq-gpio' compatiable
Holger Brunck (3):
powerpc/83xx: rename and update kmeter1
powerpc/82xx: rename and update mgcoge board support
powerpc/8xx: remove obsolete mgsuvd board
Julia Lawall (1):
drivers/serial/ucc_uart.c: Add of_node_put to avoid memory leak
Kumar Gala (1):
powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e
Liu Yu (1):
powerpc/85xx: Workaroudn e500 CPU erratum A005
Prabhakar Kushwaha (1):
powerpc/fsl_pci: Add support for FSL PCIe controllers v2.x
Scott Wood (1):
powerpc/fsl_msi: Handle msi-available-ranges better
Shan Hai (1):
powerpc/85xx: Fix SPE float to integer conversion failure
Stuart Yoder (1):
powerpc/fsl: define binding for fsl mpic interrupt controllers
Vasiliy Kulikov (1):
powerpc/85xx: Fix signedness bug in cache-sram
Vivek Mahajan (1):
powerpc/fsl: 85xx: document cache sram bindings
Xulei (2):
ATA: Add FSL sata v2 controller support
powerpc/85xx: Update sata controller compatible for p1022ds board
.../devicetree/bindings/powerpc/fsl/cache_sram.txt | 20 ++
.../devicetree/bindings/powerpc/fsl/mpic.txt | 253 ++++++++++++++++----
.../devicetree/bindings/powerpc/fsl/msi-pic.txt | 9 +-
arch/powerpc/boot/dts/kmeter1.dts | 69 +++---
arch/powerpc/boot/dts/mgcoge.dts | 47 ++--
arch/powerpc/boot/dts/mgsuvd.dts | 163 -------------
arch/powerpc/boot/dts/p1022ds.dts | 4 +-
arch/powerpc/configs/83xx/kmeter1_defconfig | 7 +-
arch/powerpc/configs/mgcoge_defconfig | 9 +-
arch/powerpc/configs/mgsuvd_defconfig | 81 -------
arch/powerpc/include/asm/reg.h | 2 +
arch/powerpc/math-emu/math_efp.c | 65 +++++-
arch/powerpc/platforms/82xx/Makefile | 2 +-
arch/powerpc/platforms/82xx/{mgcoge.c => km82xx.c} | 62 ++++--
arch/powerpc/platforms/83xx/Makefile | 2 +-
.../powerpc/platforms/83xx/{kmeter1.c => km83xx.c} | 46 +++--
arch/powerpc/platforms/85xx/smp.c | 6 +-
arch/powerpc/platforms/8xx/Kconfig | 6 -
arch/powerpc/platforms/8xx/Makefile | 1 -
arch/powerpc/platforms/8xx/mgsuvd.c | 92 -------
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 4 +-
arch/powerpc/sysdev/fsl_msi.c | 92 +++++---
arch/powerpc/sysdev/fsl_pci.c | 15 +-
arch/powerpc/sysdev/fsl_pci.h | 17 +-
arch/powerpc/sysdev/mpc8xxx_gpio.c | 4 +-
drivers/ata/sata_fsl.c | 25 ++-
drivers/tty/serial/ucc_uart.c | 67 +++---
27 files changed, 584 insertions(+), 586 deletions(-)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt
delete mode 100644 arch/powerpc/boot/dts/mgsuvd.dts
delete mode 100644 arch/powerpc/configs/mgsuvd_defconfig
rename arch/powerpc/platforms/82xx/{mgcoge.c => km82xx.c} (69%)
rename arch/powerpc/platforms/83xx/{kmeter1.c => km83xx.c} (80%)
delete mode 100644 arch/powerpc/platforms/8xx/mgsuvd.c
^ permalink raw reply
* Re: any chance to use a modern linux kernel on Pegasos1 G3 ?
From: Sven Luther @ 2011-03-15 21:41 UTC (permalink / raw)
To: Gerhard Pircher; +Cc: sven.luther, ppc.addon, linuxppc-dev, acrux_it
In-Reply-To: <20110315200855.240730@gmx.net>
On Tue, Mar 15, 2011 at 09:08:55PM +0100, Gerhard Pircher wrote:
>
> > Well, since this is long dead hardware not produced anymore, i don't see
> > how the OF could have unbroken itself by moving to powerpc.
> >
> > It has been age since i looked into this, but to the best of my knowledge
> > (and i wrote the above code or at least the earlier versions) it should
> > be still broken.
> Any idea then, how the workaround can be ported to arch/powerpc/ or if
> there is a better one available?
Sorry, it has been years since i looked these parts of the linux kernel, so i don't really
know how the arch/powerpc code handles this differently. Your best guess is to hunt for the
code yourself, and find the place. I don't remember though if debugging at that time is
easily possible though.
Friendly,
Sven Luther
^ permalink raw reply
* [PATCH] crypto: caam - de-CHIP-ify device tree compatibles
From: Kim Phillips @ 2011-03-15 21:52 UTC (permalink / raw)
To: linux-crypto, linuxppc-dev, devicetree-discuss
Cc: Scott Wood, Steve Cornelius, Kumar Gala, Herbert Xu
- all the integration parameters have been captured by the binding.
- the block name really uniquely identifies this hardware.
Some advocate putting SoC names everywhere in case software needs
to work around some chip-specific bug, but more precise SoC
information already exists in SVR, and board information already
exists in the top-level device tree node.
Note that sometimes the SoC name is a worse identifier than the
block version, as the block version can change between revisions
of the same SoC.
As a matter of historical reference, neither SEC versions 2.x
nor 3.x (driven by talitos) ever needed CHIP references.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Kumar Gala <kumar.gala@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
---
.../devicetree/bindings/crypto/fsl-sec4.txt | 64 ++++++++------------
arch/powerpc/boot/dts/p4080ds.dts | 32 ++++-------
2 files changed, 37 insertions(+), 59 deletions(-)
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
index 568aa3c..bf57ecd 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
@@ -38,7 +38,7 @@ in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
=====================================================================
-P4080 SEC 4 Node
+SEC 4 Node
Description
@@ -53,7 +53,7 @@ PROPERTIES
- compatible
Usage: required
Value type: <string>
- Definition: Must include "fsl,p4080-sec-v4.0","fsl,sec-v4.0"
+ Definition: Must include "fsl,sec-v4.0"
- #address-cells
Usage: required
@@ -105,7 +105,7 @@ PROPERTIES
EXAMPLE
crypto@300000 {
- compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0";
+ compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
@@ -115,7 +115,7 @@ EXAMPLE
};
=====================================================================
-P4080 Job Ring (JR) Node
+Job Ring (JR) Node
Child of the crypto node defines data processing interface to SEC 4
across the peripheral bus for purposes of processing
@@ -127,7 +127,7 @@ P4080 Job Ring (JR) Node
- compatible
Usage: required
Value type: <string>
- Definition: Must include "fsl,p4080-sec-v4.0-job-ring","fsl,sec-v4.0-job-ring"
+ Definition: Must include "fsl,sec-v4.0-job-ring"
- reg
Usage: required
@@ -163,8 +163,7 @@ P4080 Job Ring (JR) Node
EXAMPLE
jr@1000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
fsl,liodn = <0x081>;
interrupt-parent = <&mpic>;
@@ -173,7 +172,7 @@ EXAMPLE
=====================================================================
-P4080 Run Time Integrity Check (RTIC) Node
+Run Time Integrity Check (RTIC) Node
Child node of the crypto node. Defines a register space that
contains up to 5 sets of addresses and their lengths (sizes) that
@@ -186,7 +185,7 @@ P4080 Run Time Integrity Check (RTIC) Node
- compatible
Usage: required
Value type: <string>
- Definition: Must include "fsl,p4080-sec-v4.0-rtic","fsl,sec-v4.0-rtic".
+ Definition: Must include "fsl,sec-v4.0-rtic".
- #address-cells
Usage: required
@@ -219,8 +218,7 @@ P4080 Run Time Integrity Check (RTIC) Node
EXAMPLE
rtic@6000 {
- compatible = "fsl,p4080-sec-v4.0-rtic",
- "fsl,sec-v4.0-rtic";
+ compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
@@ -228,7 +226,7 @@ EXAMPLE
};
=====================================================================
-P4080 Run Time Integrity Check (RTIC) Memory Node
+Run Time Integrity Check (RTIC) Memory Node
A child node that defines individual RTIC memory regions that are used to
perform run-time integrity check of memory areas that should not modified.
The node defines a register that contains the memory address &
@@ -238,7 +236,7 @@ P4080 Run Time Integrity Check (RTIC) Memory Node
- compatible
Usage: required
Value type: <string>
- Definition: Must include "fsl,p4080-sec-v4.0-rtic-memory","fsl,sec-v4.0-rtic-memory".
+ Definition: Must include "fsl,sec-v4.0-rtic-memory".
- reg
Usage: required
@@ -270,15 +268,14 @@ P4080 Run Time Integrity Check (RTIC) Memory Node
EXAMPLE
rtic-a@0 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
fsl,liodn = <0x03c>;
fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
};
=====================================================================
-P4080 Secure Non-Volatile Storage (SNVS) Node
+Secure Non-Volatile Storage (SNVS) Node
Node defines address range and the associated
interrupt for the SNVS function. This function
@@ -288,7 +285,7 @@ P4080 Secure Non-Volatile Storage (SNVS) Node
- compatible
Usage: required
Value type: <string>
- Definition: Must include "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon".
+ Definition: Must include "fsl,sec-v4.0-mon".
- reg
Usage: required
@@ -315,7 +312,7 @@ P4080 Secure Non-Volatile Storage (SNVS) Node
EXAMPLE
sec_mon@314000 {
- compatible = "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon";
+ compatible = "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <93 2>;
@@ -325,7 +322,7 @@ EXAMPLE
FULL EXAMPLE
crypto: crypto@300000 {
- compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0";
+ compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
@@ -334,73 +331,64 @@ FULL EXAMPLE
interrupts = <92 2>;
sec_jr0: jr@1000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <88 2>;
};
sec_jr1: jr@2000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <89 2>;
};
sec_jr2: jr@3000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <90 2>;
};
sec_jr3: jr@4000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <91 2>;
};
rtic@6000 {
- compatible = "fsl,p4080-sec-v4.0-rtic",
- "fsl,sec-v4.0-rtic";
+ compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
- compatible = "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon";
+ compatible = "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <93 2>;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 0430d24..927f94d 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -423,7 +423,7 @@
};
crypto: crypto@300000 {
- compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0";
+ compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
@@ -432,74 +432,64 @@
interrupts = <92 2>;
sec_jr0: jr@1000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <88 2>;
};
sec_jr1: jr@2000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <89 2>;
};
sec_jr2: jr@3000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <90 2>;
};
sec_jr3: jr@4000 {
- compatible = "fsl,p4080-sec-v4.0-job-ring",
- "fsl,sec-v4.0-job-ring";
+ compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <91 2>;
};
rtic@6000 {
- compatible = "fsl,p4080-sec-v4.0-rtic",
- "fsl,sec-v4.0-rtic";
+ compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
- compatible = "fsl,p4080-sec-v4.0-rtic-memory",
- "fsl,sec-v4.0-rtic-memory";
+ compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
- compatible = "fsl,p4080-sec-v4.0-mon",
- "fsl,sec-v4.0-mon";
+ compatible = "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupt-parent = <&mpic>;
interrupts = <93 2>;
--
1.7.4.1
^ permalink raw reply related
* Re: any chance to use a modern linux kernel on Pegasos1 G3 ?
From: acrux @ 2011-03-16 0:23 UTC (permalink / raw)
To: Sven Luther; +Cc: ppc.addon, linuxppc-dev
In-Reply-To: <20110315214149.GA26249@z-innov.com>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On Tue, 15 Mar 2011 22:41:49 +0100
Sven Luther <sven.luther@z-innov.com> wrote:
> On Tue, Mar 15, 2011 at 09:08:55PM +0100, Gerhard Pircher wrote:
> >
> > > Well, since this is long dead hardware not produced anymore, i
> > > don't see how the OF could have unbroken itself by moving to
> > > powerpc.
> > >
> > > It has been age since i looked into this, but to the best of my
> > > knowledge (and i wrote the above code or at least the earlier
> > > versions) it should be still broken.
> > Any idea then, how the workaround can be ported to arch/powerpc/ or
> > if there is a better one available?
>
> Sorry, it has been years since i looked these parts of the linux
> kernel, so i don't really know how the arch/powerpc code handles this
> differently. Your best guess is to hunt for the code yourself, and
> find the place. I don't remember though if debugging at that time is
> easily possible though.
>
if chrp support doesn't anymore include Pegasos1 it could be nice to
remove all that dead code. Albeit it's fun that nobody cared about for
it during the ppc=>powerpc switch as Pegasos1 was retired in 2003
and linux-2.6.17 was released in 2006... about three years.
my regards,
Nico
- --
GNU/Linux on Power Architecture
CRUX PPC - http://cruxppc.org/
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iEYEARECAAYFAk2AAvwACgkQxq34tDeO7LiAMgCfSOueU5IE+CGJQFm56C2vIQdl
WpUAn1MsjAZb/nt1SFtfiB1gLdx79lwX
=LULL
-----END PGP SIGNATURE-----
^ permalink raw reply
* Re: [PATCH] crypto: caam - de-CHIP-ify device tree compatibles
From: Grant Likely @ 2011-03-16 0:59 UTC (permalink / raw)
To: Kim Phillips
Cc: Herbert Xu, Steve Cornelius, devicetree-discuss, linux-crypto,
Scott Wood, linuxppc-dev, Kumar Gala
In-Reply-To: <20110315165220.d4fb60bc.kim.phillips@freescale.com>
On Tue, Mar 15, 2011 at 04:52:20PM -0500, Kim Phillips wrote:
> - all the integration parameters have been captured by the binding.
> - the block name really uniquely identifies this hardware.
>
> Some advocate putting SoC names everywhere in case software needs
> to work around some chip-specific bug, but more precise SoC
> information already exists in SVR, and board information already
> exists in the top-level device tree node.
>
> Note that sometimes the SoC name is a worse identifier than the
> block version, as the block version can change between revisions
> of the same SoC.
>
> As a matter of historical reference, neither SEC versions 2.x
> nor 3.x (driven by talitos) ever needed CHIP references.
>
> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
<sigh> Very well. As long as some level of versioning is used on the
compatible values, I guess I can live with it.
Acked-off-by: Grant Likely <grant.likely@secretlab.ca>
> Cc: Kumar Gala <kumar.gala@freescale.com>
> Cc: Scott Wood <scottwood@freescale.com>
> ---
> .../devicetree/bindings/crypto/fsl-sec4.txt | 64 ++++++++------------
> arch/powerpc/boot/dts/p4080ds.dts | 32 ++++-------
> 2 files changed, 37 insertions(+), 59 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> index 568aa3c..bf57ecd 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> @@ -38,7 +38,7 @@ in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
> up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
>
> =====================================================================
> -P4080 SEC 4 Node
> +SEC 4 Node
>
> Description
>
> @@ -53,7 +53,7 @@ PROPERTIES
> - compatible
> Usage: required
> Value type: <string>
> - Definition: Must include "fsl,p4080-sec-v4.0","fsl,sec-v4.0"
> + Definition: Must include "fsl,sec-v4.0"
>
> - #address-cells
> Usage: required
> @@ -105,7 +105,7 @@ PROPERTIES
>
> EXAMPLE
> crypto@300000 {
> - compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0";
> + compatible = "fsl,sec-v4.0";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x300000 0x10000>;
> @@ -115,7 +115,7 @@ EXAMPLE
> };
>
> =====================================================================
> -P4080 Job Ring (JR) Node
> +Job Ring (JR) Node
>
> Child of the crypto node defines data processing interface to SEC 4
> across the peripheral bus for purposes of processing
> @@ -127,7 +127,7 @@ P4080 Job Ring (JR) Node
> - compatible
> Usage: required
> Value type: <string>
> - Definition: Must include "fsl,p4080-sec-v4.0-job-ring","fsl,sec-v4.0-job-ring"
> + Definition: Must include "fsl,sec-v4.0-job-ring"
>
> - reg
> Usage: required
> @@ -163,8 +163,7 @@ P4080 Job Ring (JR) Node
>
> EXAMPLE
> jr@1000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x1000 0x1000>;
> fsl,liodn = <0x081>;
> interrupt-parent = <&mpic>;
> @@ -173,7 +172,7 @@ EXAMPLE
>
>
> =====================================================================
> -P4080 Run Time Integrity Check (RTIC) Node
> +Run Time Integrity Check (RTIC) Node
>
> Child node of the crypto node. Defines a register space that
> contains up to 5 sets of addresses and their lengths (sizes) that
> @@ -186,7 +185,7 @@ P4080 Run Time Integrity Check (RTIC) Node
> - compatible
> Usage: required
> Value type: <string>
> - Definition: Must include "fsl,p4080-sec-v4.0-rtic","fsl,sec-v4.0-rtic".
> + Definition: Must include "fsl,sec-v4.0-rtic".
>
> - #address-cells
> Usage: required
> @@ -219,8 +218,7 @@ P4080 Run Time Integrity Check (RTIC) Node
>
> EXAMPLE
> rtic@6000 {
> - compatible = "fsl,p4080-sec-v4.0-rtic",
> - "fsl,sec-v4.0-rtic";
> + compatible = "fsl,sec-v4.0-rtic";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x6000 0x100>;
> @@ -228,7 +226,7 @@ EXAMPLE
> };
>
> =====================================================================
> -P4080 Run Time Integrity Check (RTIC) Memory Node
> +Run Time Integrity Check (RTIC) Memory Node
> A child node that defines individual RTIC memory regions that are used to
> perform run-time integrity check of memory areas that should not modified.
> The node defines a register that contains the memory address &
> @@ -238,7 +236,7 @@ P4080 Run Time Integrity Check (RTIC) Memory Node
> - compatible
> Usage: required
> Value type: <string>
> - Definition: Must include "fsl,p4080-sec-v4.0-rtic-memory","fsl,sec-v4.0-rtic-memory".
> + Definition: Must include "fsl,sec-v4.0-rtic-memory".
>
> - reg
> Usage: required
> @@ -270,15 +268,14 @@ P4080 Run Time Integrity Check (RTIC) Memory Node
>
> EXAMPLE
> rtic-a@0 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x00 0x20 0x100 0x80>;
> fsl,liodn = <0x03c>;
> fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
> };
>
> =====================================================================
> -P4080 Secure Non-Volatile Storage (SNVS) Node
> +Secure Non-Volatile Storage (SNVS) Node
>
> Node defines address range and the associated
> interrupt for the SNVS function. This function
> @@ -288,7 +285,7 @@ P4080 Secure Non-Volatile Storage (SNVS) Node
> - compatible
> Usage: required
> Value type: <string>
> - Definition: Must include "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon".
> + Definition: Must include "fsl,sec-v4.0-mon".
>
> - reg
> Usage: required
> @@ -315,7 +312,7 @@ P4080 Secure Non-Volatile Storage (SNVS) Node
>
> EXAMPLE
> sec_mon@314000 {
> - compatible = "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon";
> + compatible = "fsl,sec-v4.0-mon";
> reg = <0x314000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <93 2>;
> @@ -325,7 +322,7 @@ EXAMPLE
> FULL EXAMPLE
>
> crypto: crypto@300000 {
> - compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0";
> + compatible = "fsl,sec-v4.0";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x300000 0x10000>;
> @@ -334,73 +331,64 @@ FULL EXAMPLE
> interrupts = <92 2>;
>
> sec_jr0: jr@1000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x1000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <88 2>;
> };
>
> sec_jr1: jr@2000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x2000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <89 2>;
> };
>
> sec_jr2: jr@3000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x3000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <90 2>;
> };
>
> sec_jr3: jr@4000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x4000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <91 2>;
> };
>
> rtic@6000 {
> - compatible = "fsl,p4080-sec-v4.0-rtic",
> - "fsl,sec-v4.0-rtic";
> + compatible = "fsl,sec-v4.0-rtic";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x6000 0x100>;
> ranges = <0x0 0x6100 0xe00>;
>
> rtic_a: rtic-a@0 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x00 0x20 0x100 0x80>;
> };
>
> rtic_b: rtic-b@20 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x20 0x20 0x200 0x80>;
> };
>
> rtic_c: rtic-c@40 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x40 0x20 0x300 0x80>;
> };
>
> rtic_d: rtic-d@60 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x60 0x20 0x500 0x80>;
> };
> };
> };
>
> sec_mon: sec_mon@314000 {
> - compatible = "fsl,p4080-sec-v4.0-mon", "fsl,sec-v4.0-mon";
> + compatible = "fsl,sec-v4.0-mon";
> reg = <0x314000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <93 2>;
> diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
> index 0430d24..927f94d 100644
> --- a/arch/powerpc/boot/dts/p4080ds.dts
> +++ b/arch/powerpc/boot/dts/p4080ds.dts
> @@ -423,7 +423,7 @@
> };
>
> crypto: crypto@300000 {
> - compatible = "fsl,p4080-sec-v4.0", "fsl,sec-v4.0";
> + compatible = "fsl,sec-v4.0";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x300000 0x10000>;
> @@ -432,74 +432,64 @@
> interrupts = <92 2>;
>
> sec_jr0: jr@1000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x1000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <88 2>;
> };
>
> sec_jr1: jr@2000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x2000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <89 2>;
> };
>
> sec_jr2: jr@3000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x3000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <90 2>;
> };
>
> sec_jr3: jr@4000 {
> - compatible = "fsl,p4080-sec-v4.0-job-ring",
> - "fsl,sec-v4.0-job-ring";
> + compatible = "fsl,sec-v4.0-job-ring";
> reg = <0x4000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <91 2>;
> };
>
> rtic@6000 {
> - compatible = "fsl,p4080-sec-v4.0-rtic",
> - "fsl,sec-v4.0-rtic";
> + compatible = "fsl,sec-v4.0-rtic";
> #address-cells = <1>;
> #size-cells = <1>;
> reg = <0x6000 0x100>;
> ranges = <0x0 0x6100 0xe00>;
>
> rtic_a: rtic-a@0 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x00 0x20 0x100 0x80>;
> };
>
> rtic_b: rtic-b@20 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x20 0x20 0x200 0x80>;
> };
>
> rtic_c: rtic-c@40 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x40 0x20 0x300 0x80>;
> };
>
> rtic_d: rtic-d@60 {
> - compatible = "fsl,p4080-sec-v4.0-rtic-memory",
> - "fsl,sec-v4.0-rtic-memory";
> + compatible = "fsl,sec-v4.0-rtic-memory";
> reg = <0x60 0x20 0x500 0x80>;
> };
> };
> };
>
> sec_mon: sec_mon@314000 {
> - compatible = "fsl,p4080-sec-v4.0-mon",
> - "fsl,sec-v4.0-mon";
> + compatible = "fsl,sec-v4.0-mon";
> reg = <0x314000 0x1000>;
> interrupt-parent = <&mpic>;
> interrupts = <93 2>;
> --
> 1.7.4.1
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply
* linux-next: build failure after merge of the final tree (ubi tree related)
From: Stephen Rothwell @ 2011-03-16 6:50 UTC (permalink / raw)
To: Artem Bityutskiy; +Cc: linux-next, Paul Mackerras, linux-kernel, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 659 bytes --]
Hi all,
After merging the final tree, today's linux-next build (powerpc
allyesconfig) failed like this:
drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_write':
drivers/mtd/ubi/io.c:1348: error: 'PAGE_KERNEL' undeclared (first use in this function)
drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_all_ff':
drivers/mtd/ubi/io.c:1412: error: 'PAGE_KERNEL' undeclared (first use in this function)
Caused by commit 823ed5091113 ("UBI: allocate write checking buffer on demand").
I don't know how to fix this, so I have left it for today.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 490 bytes --]
^ permalink raw reply
* Re: any chance to use a modern linux kernel on Pegasos1 G3 ?
From: Sven Luther @ 2011-03-16 8:14 UTC (permalink / raw)
To: acrux; +Cc: Sven Luther, ppc.addon, linuxppc-dev
In-Reply-To: <20110316012319.b436ee11.acrux_it@libero.it>
On Wed, Mar 16, 2011 at 01:23:19AM +0100, acrux wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> On Tue, 15 Mar 2011 22:41:49 +0100
> Sven Luther <sven.luther@z-innov.com> wrote:
>
> > On Tue, Mar 15, 2011 at 09:08:55PM +0100, Gerhard Pircher wrote:
> > >
> > > > Well, since this is long dead hardware not produced anymore, i
> > > > don't see how the OF could have unbroken itself by moving to
> > > > powerpc.
> > > >
> > > > It has been age since i looked into this, but to the best of my
> > > > knowledge (and i wrote the above code or at least the earlier
> > > > versions) it should be still broken.
> > > Any idea then, how the workaround can be ported to arch/powerpc/ or
> > > if there is a better one available?
> >
> > Sorry, it has been years since i looked these parts of the linux
> > kernel, so i don't really know how the arch/powerpc code handles this
> > differently. Your best guess is to hunt for the code yourself, and
> > find the place. I don't remember though if debugging at that time is
> > easily possible though.
> >
>
> if chrp support doesn't anymore include Pegasos1 it could be nice to
> remove all that dead code. Albeit it's fun that nobody cared about for
> it during the ppc=>powerpc switch as Pegasos1 was retired in 2003
> and linux-2.6.17 was released in 2006... about three years.
Also, the Pegasos2 OF implementation corrected these issues.
Notice that 2006 was also the year that debian sabotaged all powerpc work,
and had me expulsed because some people in the debian-installer team didn't
support technical critics and had more political pull inside debian than
myself. This happening after almost a decade of me giving my time to debian,
i kind of lost interest at that point, and nobody stepped up to take over my
work.
And on top of that, Franz Pop commited suicide last year, which could possibly
have been avoided if debian's leadership would have showed more maturity and
responsability back then.
Sorry for the off topic rant, but this is something which did take a really
long time for me to get over, and i believe that the debian folk are still not
ready to let it go. I am still censored on debian mailing lists today and probably
banned from irc channels.
Sadly,
Sven Luther
^ permalink raw reply
* Re: linux-next: build failure after merge of the final tree (ubi tree related)
From: Artem Bityutskiy @ 2011-03-16 7:22 UTC (permalink / raw)
To: ext Stephen Rothwell
Cc: linux-next, Paul Mackerras, linux-kernel, linuxppc-dev
In-Reply-To: <20110316175041.67c4f371.sfr@canb.auug.org.au>
On Wed, 2011-03-16 at 17:50 +1100, ext Stephen Rothwell wrote:
> Hi all,
>
> After merging the final tree, today's linux-next build (powerpc
> allyesconfig) failed like this:
>
> drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_write':
> drivers/mtd/ubi/io.c:1348: error: 'PAGE_KERNEL' undeclared (first use in this function)
> drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_all_ff':
> drivers/mtd/ubi/io.c:1412: error: 'PAGE_KERNEL' undeclared (first use in this function)
>
> Caused by commit 823ed5091113 ("UBI: allocate write checking buffer on demand").
>
> I don't know how to fix this, so I have left it for today.
Hmm, strange, include <linux/vmalloc.h> should be enough to use
__vmalloc with 'PAGE_KERNEL' AFAICS, and we have this include... I'll
try to look better.
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply
* Re: linux-next: build failure after merge of the final tree (ubi tree related)
From: Benjamin Herrenschmidt @ 2011-03-16 10:15 UTC (permalink / raw)
To: Artem.Bityutskiy
Cc: ext Stephen Rothwell, linux-next, Paul Mackerras, linux-kernel,
linuxppc-dev
In-Reply-To: <1300260170.2817.4.camel@localhost>
On Wed, 2011-03-16 at 09:22 +0200, Artem Bityutskiy wrote:
> On Wed, 2011-03-16 at 17:50 +1100, ext Stephen Rothwell wrote:
> > Hi all,
> >
> > After merging the final tree, today's linux-next build (powerpc
> > allyesconfig) failed like this:
> >
> > drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_write':
> > drivers/mtd/ubi/io.c:1348: error: 'PAGE_KERNEL' undeclared (first use in this function)
> > drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_all_ff':
> > drivers/mtd/ubi/io.c:1412: error: 'PAGE_KERNEL' undeclared (first use in this function)
> >
> > Caused by commit 823ed5091113 ("UBI: allocate write checking buffer on demand").
> >
> > I don't know how to fix this, so I have left it for today.
>
> Hmm, strange, include <linux/vmalloc.h> should be enough to use
> __vmalloc with 'PAGE_KERNEL' AFAICS, and we have this include... I'll
> try to look better.
Try adding asm/pgtable.h
Cheers,
Ben.
^ permalink raw reply
* Re: linux-next: build failure after merge of the final tree (ubi tree related)
From: Artem Bityutskiy @ 2011-03-16 10:27 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: ext Stephen Rothwell, linux-next, Paul Mackerras, linux-kernel,
linuxppc-dev
In-Reply-To: <1300270508.22236.1168.camel@pasglop>
On Wed, 2011-03-16 at 21:15 +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2011-03-16 at 09:22 +0200, Artem Bityutskiy wrote:
> > On Wed, 2011-03-16 at 17:50 +1100, ext Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > After merging the final tree, today's linux-next build (powerpc
> > > allyesconfig) failed like this:
> > >
> > > drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_write':
> > > drivers/mtd/ubi/io.c:1348: error: 'PAGE_KERNEL' undeclared (first use in this function)
> > > drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_all_ff':
> > > drivers/mtd/ubi/io.c:1412: error: 'PAGE_KERNEL' undeclared (first use in this function)
> > >
> > > Caused by commit 823ed5091113 ("UBI: allocate write checking buffer on demand").
> > >
> > > I don't know how to fix this, so I have left it for today.
> >
> > Hmm, strange, include <linux/vmalloc.h> should be enough to use
> > __vmalloc with 'PAGE_KERNEL' AFAICS, and we have this include... I'll
> > try to look better.
>
> Try adding asm/pgtable.h
Thanks, that's what I was thinking about as well.
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply
* Re: linux-next: build failure after merge of the final tree (ubi tree related)
From: Artem Bityutskiy @ 2011-03-16 11:48 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linux-next, Paul Mackerras, linux-kernel, linuxppc-dev
In-Reply-To: <20110316175041.67c4f371.sfr@canb.auug.org.au>
On Wed, 2011-03-16 at 17:50 +1100, Stephen Rothwell wrote:
> After merging the final tree, today's linux-next build (powerpc
> allyesconfig) failed like this:
>
> drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_write':
> drivers/mtd/ubi/io.c:1348: error: 'PAGE_KERNEL' undeclared (first use in this function)
> drivers/mtd/ubi/io.c: In function 'ubi_dbg_check_all_ff':
> drivers/mtd/ubi/io.c:1412: error: 'PAGE_KERNEL' undeclared (first use in this function)
>
> Caused by commit 823ed5091113 ("UBI: allocate write checking buffer on demand").
>
> I don't know how to fix this, so I have left it for today.
Fixed, sorry for the hassle and thank you!
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply
* Powerpc gcc error for mpc8315erdb board
From: Vasanth Ragavendran @ 2011-03-16 12:25 UTC (permalink / raw)
To: linuxppc-dev
Hi
I am facing a problem with my powerpc gcc. Actually i am using a ltib to
configure the kernel and the file system for my mpc8315erdb board from linux
2.6 host machine. and the installation of kernel and filesystem is
successful. i don't have "make" installed in the board and i wanted to
compile cgic library (an ANSI C library for cgi) for the board, hence i
compiled it on the linux host machine itself but instead of using gcc i used
powerpc-e300c3-linux-gnu-gcc which corresponds to the gcc of the mpc8315erdb
board. however i get an error saying
powerpc-e300c3-linux-gnu-gcc: error trying to exec 'cc1': execvp: No such
file or directory
however powerpc-e300c3-linux-gnu-gcc is present in /usr/local/bin on the
linux host machine and this directory is part of the path. so powerpc does
exist on the host machine.
if the error comes on the host linux then i would look for
/usr/libexec/gcc/i486-slackware-linux/4.2.4/ but how do i rectify in this
scenario. the makefile for the cgic was modified according to the powerpc
architecture and i am attaching here. Kindly help! plz!
http://old.nabble.com/file/p31162962/Makefile Makefile
--
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^ permalink raw reply
* Powerpc gcc error for mpc8315erdb board
From: Vasanth Ragavendran @ 2011-03-16 12:27 UTC (permalink / raw)
To: linuxppc-dev
Hi
I am facing a problem with my powerpc gcc. Actually i am using a ltib to
configure the kernel and the file system for my mpc8315erdb board from linux
2.6 host machine. and the installation of kernel and filesystem is
successful. i don't have "make" installed in the board and i wanted to
compile cgic library (an ANSI C library for cgi) for the board, hence i
compiled it on the linux host machine itself but instead of using gcc i used
powerpc-e300c3-linux-gnu-gcc which corresponds to the gcc of the mpc8315erdb
board. however i get an error saying
powerpc-e300c3-linux-gnu-gcc: error trying to exec 'cc1': execvp: No such
file or directory
however powerpc-e300c3-linux-gnu-gcc is present in /usr/local/bin on the
linux host machine and this directory is part of the path. so powerpc does
exist on the host machine.
if the error comes on the host linux then i would look for
/usr/libexec/gcc/i486-slackware-linux/4.2.4/ but how do i rectify in this
scenario. the makefile for the cgic was modified according to the powerpc
architecture and i am attaching here below. Kindly help! plz!
http://old.nabble.com/file/p31162979/Makefile Makefile
--
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Sent from the linuxppc-dev mailing list archive at Nabble.com.
^ permalink raw reply
* Re: [PATCH] powerpc: perf: Handle events that raise an exception without overflowing
From: Ingo Molnar @ 2011-03-16 12:50 UTC (permalink / raw)
To: Anton Blanchard; +Cc: linuxppc-dev, paulus, a.p.zijlstra, acme
In-Reply-To: <20110309143842.6c22845e@kryten>
* Anton Blanchard <anton@samba.org> wrote:
>
> Events on POWER7 can roll back if a speculative event doesn't
> eventually complete. Unfortunately in some rare cases they will
> raise a performance monitor exception. We need to catch this to
> ensure we reset the PMC. In all cases the PMC will be 256 or less
> cycles from overflow.
>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> Cc: stable@kernel.org
> ---
>
> I would prefer not to add the PVR check, but I think we want to limit
> this workaround to POWER7. Would a cpu feature be preferable?
There was no objection from the PowerPC folks so i'll send this fix Linuswards, ok?
Thanks,
Ingo
^ permalink raw reply
* [PATCH v2] powerpc/ptrace: remove BUG_ON when full register set not available
From: Michael Wolf @ 2011-03-16 13:37 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, anton
In some cases during a threaded core dump not all
the threads will have a full register set. This
will cause problems when the sigkill is sent to
the thread. To solve this problem a poison value
(0xdeadbeef) will be placed in the buffer in place
of the actual register values. This will affect
gpr14 to gpr31.
Signed-off-by: Mike Wolf <mjw@linux.vnet.ibm.com>
----------
--- linux-2.6.32-71.el6.ppc64.orig/arch/powerpc/include/asm/ptrace.h 2010-08-31 23:56:50.000000000 -0500
+++ linux-2.6.32-71.el6.ppc64/arch/powerpc/include/asm/ptrace.h 2011-03-14 11:43:33.176667099 -0500
@@ -123,8 +123,14 @@ extern int ptrace_put_reg(struct task_st
#define TRAP(regs) ((regs)->trap & ~0xF)
#ifdef __powerpc64__
#define CHECK_FULL_REGS(regs) BUG_ON(regs->trap & 1)
+#define PARTIAL_REG_FILL 0xdeadbeefdeadbeefUL
+#define PARTIAL_REG_START 14
+#define PARTIAL_REG_END 31
#else
#define CHECK_FULL_REGS(regs) \
+#define PARTIAL_REG_FILL 0xdeadbeef
+#define PARTIAL_REG_START 14
+#define PARTIAL_REG_END 31
do { \
if ((regs)->trap & 1) \
printk(KERN_CRIT "%s: partial register set\n", __func__); \
--- linux-2.6.32-71.el6.ppc64.orig/arch/powerpc/kernel/ptrace.c 2009-12-02 21:51:21.000000000 -0600
+++ linux-2.6.32-71.el6.ppc64/arch/powerpc/kernel/ptrace.c 2011-03-14 13:01:51.955586126 -0500
@@ -125,11 +125,16 @@ static int gpr_get(struct task_struct *t
void *kbuf, void __user *ubuf)
{
int ret;
+ int partial_reg;
if (target->thread.regs == NULL)
return -EIO;
- CHECK_FULL_REGS(target->thread.regs);
+ if (!FULL_REGS(target->thread.regs))
+ /* We have a partial register set. Fill 14-31 with bogus values */
+ for(partial_reg=PARTIAL_REG_START;partial_reg <= PARTIAL_REG_END;
+ partial_reg++)
+ target->thread.regs->gpr[partial_reg] = PARTIAL_REG_FILL;
ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
target->thread.regs,
@@ -536,11 +541,16 @@ static int gpr32_get(struct task_struct
compat_ulong_t *k = kbuf;
compat_ulong_t __user *u = ubuf;
compat_ulong_t reg;
+ int partial_reg;
if (target->thread.regs == NULL)
return -EIO;
- CHECK_FULL_REGS(target->thread.regs);
+ if (!FULL_REGS(target->thread.regs))
+ /* We have a partial register set. Fill 14-31 with bogus values */
+ for(partial_reg=PARTIAL_REG_START;partial_reg <= PARTIAL_REG_END;
+ partial_reg++)
+ target->thread.regs->gpr[partial_reg] = PARTIAL_REG_FILL;
pos /= sizeof(reg);
count /= sizeof(reg);
^ permalink raw reply
* Re: [PATCH V12 0/4] ptp: IEEE 1588 hardware clock support
From: Richard Cochran @ 2011-03-16 14:26 UTC (permalink / raw)
To: linux-kernel
Cc: Thomas Gleixner, Rodolfo Giometti, Arnd Bergmann, Peter Zijlstra,
linux-api, devicetree-discuss, Russell King, Paul Mackerras,
John Stultz, linux-arm-kernel, netdev, Mike Frysinger,
Christoph Lameter, linuxppc-dev, David Miller, Alan Cox,
Krzysztof Halasa
In-Reply-To: <cover.1298878618.git.richard.cochran@omicron.at>
On Mon, Feb 28, 2011 at 08:57:03AM +0100, Richard Cochran wrote:
> * PHC Patch ChangeLog
> ** v12
> *** gianfar_ptp
> - fixed up device tree
> - inlined the header file
> - use platform_ calls instead of deprecated of_ calls
> - removed static global single instance
> - removed John Stultz's ack from this patch
@Thomas and John:
Can I get your acks on the remaining patches?
Can this be merged for 2.6.39?
Thanks,
Richard
^ permalink raw reply
* Re: [PATCH 3/4 v5] video, sm501: add OF binding to support SM501
From: Paul Mundt @ 2011-03-16 15:36 UTC (permalink / raw)
To: Heiko Schocher
Cc: linux-fbdev, devicetree-discuss, Samuel Ortiz, Vincent Sanders,
linux-kernel, Ben Dooks, Randy Dunlap, linuxppc-dev,
Wolfgang Denk
In-Reply-To: <4D7F14B0.1030008@denx.de>
On Tue, Mar 15, 2011 at 08:26:40AM +0100, Heiko Schocher wrote:
> > 0003-video-sm501-add-OF-binding-to-support-SM501.patch has no obvious style problems and is ready for submission.
> >
> > Documentation/powerpc/dts-bindings/sm501.txt | 34 +++++++++++++++++++++
> > drivers/mfd/sm501.c | 9 +++++-
> > drivers/video/sm501fb.c | 42 ++++++++++++++++++++++++--
> > 3 files changed, 81 insertions(+), 4 deletions(-)
> > create mode 100644 Documentation/powerpc/dts-bindings/sm501.txt
>
> This patchset is pending know for a while. I got Acked by from
>
> Samuel Ortiz for the mfd part, see here:
>
> http://www.spinics.net/lists/linux-fbdev/msg02550.html
> http://linux.derkeiler.com/Mailing-Lists/Kernel/2011-01/msg11798.html
>
> and for the DTS part from Benjamin Herrenschmidt:
>
> http://lists.ozlabs.org/pipermail/linuxppc-dev/2011-February/088279.html
>
> Are there some more issues?
>
Not that I remember off the top of my head, but I think they've been lost
in my backlog. Could you re-send the current series with the appropriate
acked-bys? If there's nothing else obvious outstanding I'll roll them in.
^ permalink raw reply
* Re: [PATCH] powerpc: perf: Handle events that raise an exception without overflowing
From: Benjamin Herrenschmidt @ 2011-03-16 20:34 UTC (permalink / raw)
To: Ingo Molnar; +Cc: linuxppc-dev, paulus, Anton Blanchard, acme, a.p.zijlstra
In-Reply-To: <20110316125053.GA7387@elte.hu>
On Wed, 2011-03-16 at 13:50 +0100, Ingo Molnar wrote:
> * Anton Blanchard <anton@samba.org> wrote:
>
> >
> > Events on POWER7 can roll back if a speculative event doesn't
> > eventually complete. Unfortunately in some rare cases they will
> > raise a performance monitor exception. We need to catch this to
> > ensure we reset the PMC. In all cases the PMC will be 256 or less
> > cycles from overflow.
> >
> > Signed-off-by: Anton Blanchard <anton@samba.org>
> > Cc: stable@kernel.org
> > ---
> >
> > I would prefer not to add the PVR check, but I think we want to limit
> > this workaround to POWER7. Would a cpu feature be preferable?
>
> There was no objection from the PowerPC folks so i'll send this fix Linuswards, ok?
Ah yes.
Ack.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v2 21/28] powerpc: sysdev/mpc8xxx_gpio irq_data conversion.
From: Peter Korsgaard @ 2011-03-16 21:25 UTC (permalink / raw)
To: Lennert Buytenhek; +Cc: Thomas Gleixner, linuxppc-dev
In-Reply-To: <20110309082658.GR16649@mail.wantstofly.org>
>>>>> "Lennert" == Lennert Buytenhek <buytenh@wantstofly.org> writes:
Lennert> Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
Lennert> ---
Lennert> v2: get_irq_chip_data(d->irq) => irq_data_get_irq_chip_data(d)
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
--
Bye, Peter Korsgaard
^ permalink raw reply
* [PATCH 1/4] powerpc/mpc512x: Add initial support for TWR-MPC5125
From: Vladimir Ermakov @ 2011-03-16 23:29 UTC (permalink / raw)
To: linuxppc-dev
Adds Freescale TWR-MPC5125 device tree and platform code.
Currently following is supported:
- NAND
- FEC1 and FEC2
- RTC
- PSC UART
Signed-off-by: Vladimir Ermakov <vooon341@gmail.com>
---
diff --git a/arch/powerpc/boot/dts/mpc5125twr.dts b/arch/powerpc/boot/dts/mpc5125twr.dts
new file mode 100644
index 0000000..54f568f
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5125twr.dts
@@ -0,0 +1,394 @@
+/*
+ * STx/Freescale ADS5125 MPC5125 silicon
+ *
+ * Copyright (C) 2009 Freescale Semiconductor Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mpc5125ads";
+ compatible = "fsl,mpc5125ads";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,5125@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <0x20>; // 32 bytes
+ i-cache-line-size = <0x20>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
+ bus-frequency = <198000000>; // 198 MHz csb bus
+ clock-frequency = <396000000>; // 396 MHz ppc core
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>; // 256MB at 0
+ };
+
+ sram@30000000 {
+ compatible = "fsl,mpc5121-sram";
+ reg = <0x30000000 0x08000>; // 32K at 0x30000000
+ };
+
+ nfc@40000000 {
+ compatible = "fsl,mpc5125-nfc";
+ reg = <0x40000000 0x100000>; // 1M at 0x40000000
+ interrupts = <6 0x8>;
+ interrupt-parent = < &ipic >;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <1>;
+ write-size = <4096>;
+ spare-size = <128>;
+ chips = <1>;
+ // NOTE: partition map different than in BSP
+ nand-spl@0 {
+ label = "loader";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ uboot@100000 {
+ label = "uboot";
+ reg = <0x00100000 0x00100000>;
+ read-only;
+ };
+ uboot-env@200000 {
+ label = "uboot-env";
+ reg = <0x00200000 0x00100000>;
+ read-only;
+ };
+ kernel300000 {
+ label = "kernel";
+ reg = <0x00300000 0x00800000>;
+ };
+ device-tree00000 {
+ label = "device-tree";
+ reg = <0x00b00000 0x00100000>;
+ };
+ ramboot-rootfs@c00000 {
+ label = "ramboot-rootfs";
+ reg = <0x00c00000 0x00800000>;
+ };
+ rootfs@1400000 {
+ label = "rootfs";
+ reg = <0x01400000 0x01400000>;
+ };
+ user@2800000 {
+ label = "user";
+ reg = <0x02800000 0x01400000>;
+ };
+ SRAM@4200000 {
+ label = "SRAM"; // NVRAM emul
+ reg = <0x04200000 0x01400000>;
+ };
+ prom@5600000 {
+ label = "prom";
+ reg = <0x05600000 0x01400000>;
+ };
+ //data@2800000 {
+ // label = "data";
+ // reg = <0x28000000 0xeac00000>;
+ //};
+ };
+
+ soc@80000000 {
+ compatible = "fsl,mpc5121-immr";
+ device_type = "soc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ ranges = <0x0 0x80000000 0x400000>;
+ reg = <0x80000000 0x400000>;
+ bus-frequency = <66000000>; // 66 MHz ips bus
+
+
+ // IPIC
+ // interrupts cell = <intr #, sense>
+ // sense values match linux IORESOURCE_IRQ_* defines:
+ // sense == 8: Level, low assertion
+ // sense == 2: Edge, high-to-low change
+ //
+ ipic: interrupt-controller@c00 {
+ compatible = "fsl,mpc5121-ipic", "fsl,ipic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0xc00 0x100>;
+ };
+
+ rtc@a00 { // Real time clock
+ compatible = "fsl,mpc5121-rtc";
+ reg = <0xa00 0x100>;
+ interrupts = <79 0x8 80 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ reset@e00 { // Reset module
+ compatible = "fsl,mpc5121-reset";
+ reg = <0xe00 0x100>;
+ };
+
+ clock@f00 { // Clock control
+ compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
+ reg = <0xf00 0x100>;
+ };
+
+ pmc@1000{ // Power Management Controller
+ compatible = "fsl,mpc5121-pmc";
+ reg = <0x1000 0x100>;
+ interrupts = <83 0x2>;
+ interrupt-parent = < &ipic >;
+ };
+
+ gpio@1100 {
+ compatible = "fsl,mpc5125-gpio";
+ cell-index = <0>;
+ reg = <0x1100 0x080>;
+ interrupts = <78 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ gpio@1180 {
+ compatible = "fsl,mpc5125-gpio1";
+ cell-index = <1>;
+ reg = <0x1180 0x080>;
+ interrupts = <78 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ can@1300 { // CAN rev.2
+ compatible = "fsl,mpc5121-mscan";
+ cell-index = <0>;
+ interrupts = <12 0x8>;
+ interrupt-parent = < &ipic >;
+ reg = <0x1300 0x80>;
+ };
+
+ can@1380 {
+ compatible = "fsl,mpc5121-mscan";
+ cell-index = <1>;
+ interrupts = <13 0x8>;
+ interrupt-parent = < &ipic >;
+ reg = <0x1380 0x80>;
+ };
+
+ sdhc@1500 {
+ compatible = "fsl,mpc5125-sdhc";
+ interrupts = <8 0x8>;
+ interrupt-parent = < &ipic >;
+ reg = <0x1500 0x100>;
+ };
+
+ i2c@1700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-i2c";
+ cell-index = <0>;
+ reg = <0x1700 0x20>;
+ interrupts = <0x9 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl5200-clocking;
+ };
+
+ i2c@1720 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-i2c";
+ cell-index = <1>;
+ reg = <0x1720 0x20>;
+ interrupts = <0xa 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl5200-clocking;
+ };
+
+ i2c@1740 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-i2c";
+ cell-index = <2>;
+ reg = <0x1740 0x20>;
+ interrupts = <0xb 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl5200-clocking;
+ };
+
+ i2ccontrol@1760 {
+ compatible = "fsl,mpc5121-i2c-ctrl";
+ reg = <0x1760 0x8>;
+ };
+
+ //diu@2100 {
+ // device_type = "display";
+ // compatible = "fsl-diu";
+ // reg = <0x2100 0x100>;
+ // interrupts = <64 0x8>;
+ // interrupt-parent = < &ipic >;
+ //};
+
+ // MPC5125e has two more CAN ports
+ // but they are not used on ADS5125
+ //can@2300 {
+ // compatible = "fsl,mpc5121-mscan";
+ // cell-index = <2>;
+ // interrupts = <90 0x8>;
+ // interrupt-parent = < &ipic >;
+ // reg = <0x2300 0x80>;
+ //};
+
+ //can@2380 {
+ // compatible = "fsl,mpc5121-mscan";
+ // cell-index = <3>;
+ // interrupts = <91 0x8>;
+ // interrupt-parent = < &ipic >;
+ // reg = <0x2380 0x80>;
+ //};
+
+ mdio@2800 {
+ device_type = "mdio";
+ compatible = "fsl,mpc5121-fec-mdio";
+ reg = <0x2800 0x800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@2800 {
+ device_type = "network";
+ compatible = "fsl,mpc5121-fec";
+ reg = <0x2800 0x800>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <4 0x8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy0 >;
+ };
+
+ // USB ULPI1
+ //usb@3000 {
+ // device_type = "usb";
+ // compatible = "fsl-usb2-dr";
+ // reg = <0x3000 0x400>;
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // interrupt-parent = < &ipic >;
+ // interrupts = <43 0x8>;
+ // dr_mode = "host";
+ // phy_type = "ulpi";
+ // big-endian-regs;
+ //};
+
+ // USB ULPI2
+ //usb@4000 {
+ // device_type = "usb";
+ // compatible = "fsl-usb2-dr";
+ // reg = <0x4000 0x400>;
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // interrupt-parent = < &ipic >;
+ // interrupts = <44 0x8>;
+ // dr_mode = "otg";
+ // phy_type = "ulpi";
+ // big-endian-regs;
+ //};
+
+ mdio@4800 {
+ device_type = "mdio";
+ compatible = "fsl,mpc5121-fec-mdio";
+ reg = <0x4800 0x800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@0 {
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@4800 {
+ device_type = "network";
+ compatible = "fsl,mpc5121-fec";
+ reg = <0x4800 0x800>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <5 0x8>;
+ interrupt-parent = < &ipic >;
+ phy-handle = < &phy1 >;
+ };
+
+ // IO control
+ ioctl@a000 {
+ compatible = "fsl,mpc5125-ioctl";
+ reg = <0xA000 0x1000>;
+ };
+
+ // PSC0 in ac97 mode
+ //ac97@11000 {
+ // device_type = "sound";
+ // compatible = "fsl,mpc5125-psc-ac97", "fsl,mpc5125-psc";
+ // cell-index = <0>;
+ // reg = <0x11000 0x100>;
+ // interrupts = <40 0x8>;
+ // interrupt-parent = < &ipic >;
+ // fsl,mode = "ac97-slave";
+ // rx-fifo-size = <384>;
+ // tx-fifo-size = <384>;
+ //};
+
+ // 5125 PSCs are not 52xx or 5121 PSC compatible
+ // PSC1 uart0 aka ttyPSC0
+ serial@11100 {
+ device_type = "serial";
+ compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+ port-number = <0>;
+ cell-index = <1>;
+ reg = <0x11100 0x100>;
+ interrupts = <40 0x8 71 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,rx-fifo-size = <16>;
+ fsl,tx-fifo-size = <16>;
+ nodcd;
+ };
+
+ // PSC9 uart1 aka ttyPSC1
+ serial@11900 {
+ device_type = "serial";
+ compatible = "fsl,mpc5125-psc-uart", "fsl,mpc5125-psc";
+ port-number = <1>;
+ cell-index = <9>;
+ reg = <0x11900 0x100>;
+ interrupts = <40 0x8 32 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,rx-fifo-size = <16>;
+ fsl,tx-fifo-size = <16>;
+ nodcd;
+ };
+
+ pscfifo@11f00 {
+ compatible = "fsl,mpc5121-psc-fifo";
+ reg = <0x11f00 0x100>;
+ interrupts = <40 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+
+ dma@14000 {
+ compatible = "fsl,mpc5121-dma"; // old name: "mpc512x-dma2"
+ reg = <0x14000 0x1800>;
+ interrupts = <65 0x8>;
+ interrupt-parent = < &ipic >;
+ };
+ };
+};
diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig
index 27b0651..0dde4b0 100644
--- a/arch/powerpc/platforms/512x/Kconfig
+++ b/arch/powerpc/platforms/512x/Kconfig
@@ -26,6 +26,20 @@ config MPC5121_GENERIC
Compatible boards include: Protonic LVT base boards (ZANMCU
and VICVT2).
+config PPC_MPC5125
+ bool "Generic support for MPC5125 based boards"
+ depends on PPC_MPC512x
+ select DEFAULT_UIMAGE
+ select PPC_INDIRECT_PCI
+ default n
+
+config MPC5125_TWR
+ bool "Freescale MPC5125 Tower system"
+ depends on PPC_MPC512x
+ select PPC_MPC5125
+ help
+ This option enables support for the MPC5125 TWR board.
+
config PDM360NG
bool "ifm PDM360NG board"
depends on PPC_MPC512x
diff --git a/arch/powerpc/platforms/512x/Makefile b/arch/powerpc/platforms/512x/Makefile
index 4efc1c4..5c17561 100644
--- a/arch/powerpc/platforms/512x/Makefile
+++ b/arch/powerpc/platforms/512x/Makefile
@@ -5,3 +5,4 @@ obj-y += clock.o mpc512x_shared.o
obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o mpc5121_ads_cpld.o
obj-$(CONFIG_MPC5121_GENERIC) += mpc5121_generic.o
obj-$(CONFIG_PDM360NG) += pdm360ng.o
+obj-$(CONFIG_MPC5125_TWR) += mpc5125_twr.o
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 3dc2a8d..962c0ba 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -669,6 +669,13 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
clk->rate = mclk_src / mclk_div;
}
+
+#ifdef CONFIG_PPC_MPC5125
+#define PSC_PREFIX "mpc5125"
+#else
+#define PSC_PREFIX "mpc5121"
+#endif
+
/*
* Find all psc nodes in device tree and assign a clock
* with name "psc%d_mclk" and dev pointing at the device
@@ -680,7 +687,7 @@ static void psc_clks_init(void)
const u32 *cell_index;
struct platform_device *ofdev;
- for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+ for_each_compatible_node(np, NULL, "fsl," PSC_PREFIX "-psc") {
cell_index = of_get_property(np, "cell-index", NULL);
if (cell_index) {
int pscnum = *cell_index;
diff --git a/arch/powerpc/platforms/512x/mpc5125_twr.c b/arch/powerpc/platforms/512x/mpc5125_twr.c
new file mode 100644
index 0000000..c35b0d8
--- /dev/null
+++ b/arch/powerpc/platforms/512x/mpc5125_twr.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2010 LimePC Multimedia Technologies Co., Limited
+ * Copyright (C) 2011 Vladimir Ermakov <vooon341@gmail.com>
+ *
+ * Based on original Freescale Semiconductor BSP
+ * written by Cloudy Chen <chen_yunsong@mtcera.com>
+ *
+ * MPC5125 Tower board setup
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/prom.h>
+#include <asm/time.h>
+
+#include <sysdev/fsl_soc.h>
+
+#include <linux/bootmem.h>
+#include <asm/rheap.h>
+
+#include "mpc512x.h"
+
+static void mpc5125_psc_iopad_init(void __iomem *ioctl, char *name)
+{
+ struct device_node *np;
+ const u32 *cell_index;
+ char *default_psc = "fsl,mpc5125-psc";
+ char *psc_name;
+
+ if (name)
+ psc_name = name;
+ else
+ psc_name = default_psc;
+
+ for_each_compatible_node(np, NULL, psc_name) {
+ cell_index = of_get_property(np, "cell-index", NULL);
+ if (cell_index) {
+ u8 __iomem *pscioctl;
+ int psc_num = *cell_index;
+ if (psc_num > 1)
+ continue;
+
+ pscioctl = ioctl + 0x76 + 5 * psc_num;
+ out_8(pscioctl++, 0x07);
+ out_8(pscioctl++, 0x03);
+ out_8(pscioctl++, 0x03);
+ out_8(pscioctl++, 0x03);
+ out_8(pscioctl++, 0x03);
+ }
+ }
+}
+
+static void mpc5125_fec2_usb_io_init(void __iomem *ioctl, int isusb)
+{
+#define FEC2_INIT 0
+#define USB_INIT 1
+ int i;
+ const u8 offset[12] = {
+ 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a,
+ 0x6b, 0x6c, 0x6d, 0x6e
+ };
+ const u8 init[2][12] = {
+ [FEC2_INIT] = {
+ 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43, 0x43,
+ 0x43, 0x43, 0x43, 0x43},
+ [USB_INIT] = {
+ 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03}
+ };
+
+ isusb = (isusb) ? USB_INIT : FEC2_INIT;
+ for (i = 0; i < ARRAY_SIZE(offset); i++)
+ out_8(ioctl + offset[i], init[isusb][i]);
+#undef FEC2_INIT
+#undef USB_INIT
+}
+
+static void __init mpc5125_board_setup(void)
+{
+ struct device_node *np;
+
+ /*
+ * io pad config
+ */
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-ioctl");
+ if (np) {
+ void __iomem *ioctl = of_iomap(np, 0);
+
+ mpc5125_psc_iopad_init(ioctl, NULL);
+ mpc5125_fec2_usb_io_init(ioctl, 0);
+
+ of_node_put(np);
+ iounmap(ioctl);
+ }
+}
+
+static void __init mpc5125_ads_setup_arch(void)
+{
+ printk(KERN_INFO "MPC5125 ADS board from Freescale Semiconductor\n");
+
+ mpc5125_board_setup();
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+ { .name = "soc", },
+ {},
+};
+
+static void __init mpc5125_ads_declare_of_platform_devices(void)
+{
+ struct device_node *np;
+
+ if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
+ printk(KERN_ERR __FILE__ ": "
+ "Error while probing of_platform bus\n");
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,mpc5125-nfc");
+ if (np) {
+ of_platform_device_create(np, NULL, NULL);
+ of_node_put(np);
+ }
+}
+
+static void __init mpc5125_ads_init(void)
+{
+ mpc5125_ads_declare_of_platform_devices();
+ mpc5121_clk_init();
+ mpc512x_restart_init();
+ mpc512x_psc_fifo_init("fsl,mpc5125-psc");
+}
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc5125_ads_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "fsl,mpc5125ads");
+}
+
+define_machine(mpc5125_ads) {
+ .name = "MPC5125 ADS",
+ .probe = mpc5125_ads_probe,
+ .setup_arch = mpc5125_ads_setup_arch,
+ .init = mpc5125_ads_init,
+ .init_IRQ = mpc512x_init_IRQ,
+ .get_irq = ipic_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+ .restart = mpc512x_restart,
+};
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h
index 1ab6d11..70c66c6 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -13,8 +13,10 @@
#define __MPC512X_H__
extern void __init mpc512x_init_IRQ(void);
extern void __init mpc512x_init(void);
+extern void __init mpc512x_restart_init(void);
extern int __init mpc5121_clk_init(void);
-void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_declare_of_platform_devices(void);
+extern void __init mpc512x_psc_fifo_init(char *psc_name);
extern void mpc512x_restart(char *cmd);
extern void mpc512x_init_diu(void);
extern void mpc512x_setup_diu(void);
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index e41ebbd..411fc9d 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -32,7 +32,7 @@
static struct mpc512x_reset_module __iomem *reset_module_base;
-static void __init mpc512x_restart_init(void)
+void __init mpc512x_restart_init(void)
{
struct device_node *np;
@@ -401,15 +401,19 @@ static unsigned int __init get_fifo_size(struct device_node *np,
((u32)(_base) + sizeof(struct mpc52xx_psc)))
/* Init PSC FIFO space for TX and RX slices */
-void __init mpc512x_psc_fifo_init(void)
+void __init mpc512x_psc_fifo_init(char *psc_name)
{
struct device_node *np;
void __iomem *psc;
unsigned int tx_fifo_size;
unsigned int rx_fifo_size;
+ char *default_psc = "fsl,mpc5121-psc";
int fifobase = 0; /* current fifo address in 32 bit words */
- for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
+ if (!psc_name)
+ psc_name = default_psc;
+
+ for_each_compatible_node(np, NULL, psc_name) {
tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size");
rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size");
@@ -461,5 +465,5 @@ void __init mpc512x_init(void)
mpc512x_declare_of_platform_devices();
mpc5121_clk_init();
mpc512x_restart_init();
- mpc512x_psc_fifo_init();
+ mpc512x_psc_fifo_init(NULL);
}
^ permalink raw reply related
* Re: any chance to use a modern linux kernel on Pegasos1 G3 ?
From: nello martuscielli @ 2011-03-16 23:39 UTC (permalink / raw)
To: Gerhard Pircher; +Cc: linuxppc-dev, acrux_it
In-Reply-To: <20110315171448.100300@gmx.net>
hi all,
here instead the log from serial debug console booting the last
working kernel i.e. linux-2.16.62 compiled with arch=ppc .
[...]
do_load: dev="/ide/disk:0" dlen=11 args="CRUX root=/dev/hdb
video=radeonfb:800x600" alen=41
do_load: alstr=""
try_load: dev="/ide/disk:0" dlen=11 args="CRUX root=/dev/hdb
video=radeonfb:800x600" alen=41
create_well_formed_chain: pkg=0xFD57D58 parent=0xFD53B90
currpkg=0xFD53B90 inst=0xFE6EE50
pkg=/pci@80000000 parent=/ currpkg=/ currinst=/
create_well_formed_chain: pkg=0xFD53B90 parent=0x0 currpkg=0xFD53B90
inst=0xFE6EE50
pkg=/ parent= currpkg=/ currinst=/
pkg=0xFD57D58:/pci@80000000 parent=0xFE6EE50:/
inst=0xFE6EEA8:/pci@80000000 instparent=0xFE6EE50
ata_disk_open: pkg=0xFD5B870 parent=0xFD5B2C8
ata_disk_open: CTLR=0x0 ID=0x0
ata_disk_open: args="0"
deblocker open
ata_disk_max_transfer: 512
deblocker open: block-size=0x200 max-transfer=0x200
deblocker open: return 0
open-package: ret=0:no error r=-1
ata_disk_open: $open-package deblocker ret=0
ata_disk_open: deblocker=0xFE6EFC8
disk-label open
disk-label open: self=0xFE702B0 s->buf=0xFE71000
disk-label open: return 0
open-package: ret=0:no error r=-1
ata_disk_open: $open-package disk-label ret=0
ata_disk_open: disklabel=0xFE70258
disk-label load: addr=0x400000 loadargs=CRUX root=/dev/hdb
video=radeonfb:800x600 args=0,CRUX root=/dev/hdb
video=radeonfb:800x600
file_system: e=0xFD00008 disk=0xFE6EF58 loc=0x0 start=0x0
path=0xFE703C0 buf=0xFE71000 size=512
file_system: probing filesys dos-partition
dos_partition: enter
dos-partition: boot_sect_sig0/1=0x55.0xAA jump=0x0 boot_signature=0x0
drive_number=0x0
dos_partition: partition=0 size=0x32F8E start=0x3F typ=0x6
flag=0x80 shd=0x1 ssect=0x1 scyl=0x0 ehd=0xFE esect=0x3F ecyl=0xC
file_system: e=0xFD00008 disk=0xFE6EF58 loc=0x7E00 start=0x3F
path=0xFE703C2 buf=0xFE71000 size=512
file_system: probing filesys dos-partition
file_system: probing filesys dos-fat
file_system: return end (-4089)
file_system: return end (-4089)
disk-label return len=1782093 ret=end (-4089)
ata_disk_close
disk-label close:
checking exec type Fcode
fcode_is_exec: load=0x400000 loadlen=1782093
checking exec type Forth
checking exec type ELF
f_go:
checking exec type Fcode
fcode_is_exec: load=0x400000 loadlen=1782093
checking exec type Forth
checking exec type ELF
alloc_aligned: a 0xFD548E8 align 0xFD5491C size 0xFD54918 addr 0xFD54914
alloc_constrained: min 0x0, max 0xFFFFFFFF, align 0x1000, mask
0xFFFFFFFF, size 0x7E0000, addr 0x300000
alloc_constrained: acells 0x1 scells 0x1 t1 0xC t2 0xFD5490C u1
0xFD54910 u2 0xFD54914 u3 0xFD54918
alloc_constrained: allocator_block 0xFD54930, next 0x0 addr 0x300000
size 0xFD00000
alloc_constrained: fsblock 0x0
alloc_constrained: addr[] 0x300000
alloc_constrained: bsize[] 0xFD00000
alloc_constrained: passed min check
alloc_constrained: addr 0x300000, align 0xFFF, off 0x69696969
sum 0x0
alloc_constrained: passed align check
alloc_constrained: passed max check
alloc_constrained: passed mask check
alloc_constrained: passed full size check
alloc_constrained: passed size check
i'm not an expert but from a quick logs comparison I saw two times the
alloc_aligned,alloc_constrained section instead in the working one i
see it only one time.
Maybe it's an usefull observation.
cheers,
Nell
--
1861 - 2011: 150 years of Italian Unity
^ permalink raw reply
* [PATCH 2/4] serial: Add initial support for TWR-MPC5125
From: Vladimir Ermakov @ 2011-03-16 23:33 UTC (permalink / raw)
To: linuxppc-dev
Adds PSC UART support for MPC5125 SoC.
MPC5125 has different registers than in MPC5121.
Signed-off-by: Vladimir Ermakov <vooon341@gmail.com>
---
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
index 2966df6..7bff52f 100644
--- a/arch/powerpc/include/asm/mpc52xx_psc.h
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -150,6 +150,51 @@
/* Structure of the hardware registers */
struct mpc52xx_psc {
+#ifdef CONFIG_PPC_MPC5125
+ u8 mr1; /* PSC + 0x00 */
+ u8 reserved0[3];
+ u8 mr2; /* PSC + 0x04 */
+ u8 reserved1[3];
+ u16 mpc52xx_psc_status; /* PSC + 0x08 */
+ u8 reserved2[2];
+ u8 mpc52xx_psc_clock_select; /* PSC + 0x0c */
+ u8 reserved3[3];
+ u8 command; /* PSC + 0x10 */
+ u8 reserved4[3];
+ union { /* PSC + 0x14 */
+ u8 buffer_8;
+ u16 buffer_16;
+ u32 buffer_32;
+ } buffer;
+#define mpc52xx_psc_buffer_8 buffer.buffer_8
+#define mpc52xx_psc_buffer_16 buffer.buffer_16
+#define mpc52xx_psc_buffer_32 buffer.buffer_32
+ u8 mpc52xx_psc_ipcr; /* PSC + 0x18 */
+ u8 reserved5[3];
+ u8 mpc52xx_psc_acr; /* PSC + 0x1c */
+ u8 reserved6[3];
+ u16 mpc52xx_psc_isr; /* PSC + 0x20 */
+ u8 reserved7[2];
+ u16 mpc52xx_psc_imr; /* PSC + 0x24 */
+ u8 reserved8[2];
+ u8 ctur; /* PSC + 0x28 */
+ u8 reserved9[3];
+ u8 ctlr; /* PSC + 0x2c */
+ u8 reserved10[3];
+ u32 ccr; /* PSC + 0x30 */
+ u32 ac97slots; /* PSC + 0x34 */
+ u32 ac97cmd; /* PSC + 0x38 */
+ u32 ac97data; /* PSC + 0x3c */
+ u8 reserved11[4];
+ u8 ip; /* PSC + 0x44 */
+ u8 reserved12[3];
+ u8 op1; /* PSC + 0x48 */
+ u8 reserved13[3];
+ u8 op0; /* PSC + 0x4c */
+ u8 reserved14[3];
+ u32 sicr; /* PSC + 0x50 */
+ u8 reserved15[4];
+#else
u8 mode; /* PSC + 0x00 */
u8 reserved0[3];
union { /* PSC + 0x04 */
@@ -212,6 +257,7 @@ struct mpc52xx_psc {
u8 reserved16[3];
u8 irfdr; /* PSC + 0x54 */
u8 reserved17[3];
+#endif
};
struct mpc52xx_psc_fifo {
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index a0bcd8a..8e4c6b0 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -128,7 +128,11 @@ static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
u16 prescaler, unsigned int divisor)
{
/* select prescaler */
+#ifdef CONFIG_PPC_MPC5125
+ out_8(&psc->mpc52xx_psc_clock_select, prescaler >> 8);
+#else
out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
+#endif
out_8(&psc->ctur, divisor >> 8);
out_8(&psc->ctlr, divisor & 0xff);
}
@@ -345,7 +349,11 @@ static unsigned int psc_fifoc_irq;
static void mpc512x_psc_fifo_init(struct uart_port *port)
{
/* /32 prescaler */
+#ifdef CONFIG_PPC_MPC5125
+ out_8(&PSC(port)->mpc52xx_psc_clock_select, 0xdd);
+#else
out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
+#endif
out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
@@ -816,9 +824,14 @@ mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
out_8(&psc->command, MPC52xx_PSC_RST_TX);
/* Send new mode settings */
+#ifdef CONFIG_PPC_MPC5125
+ out_8(&psc->mr1, mr1);
+ out_8(&psc->mr2, mr2);
+#else
out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
out_8(&psc->mode, mr1);
out_8(&psc->mode, mr2);
+#endif
baud = psc_ops->set_baudrate(port, new, old);
/* Update the per-port timeout */
@@ -1107,8 +1120,12 @@ mpc52xx_console_get_options(struct uart_port *port,
pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
/* Read the mode registers */
+#ifdef CONFIG_PPC_MPC5125
+ mr1 = in_8(&psc->mr1);
+#else
out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
mr1 = in_8(&psc->mode);
+#endif
/* CT{U,L}R are write-only ! */
*baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
@@ -1296,9 +1313,13 @@ static struct of_device_id mpc52xx_uart_of_match[] = {
/* binding used by efika: */
{ .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
#endif
-#ifdef CONFIG_PPC_MPC512x
+#if defined(CONFIG_PPC_MPC512x) && !defined(CONFIG_PPC_MPC5125)
{ .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
#endif
+#ifdef CONFIG_PPC_MPC5125
+ { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc512x_psc_ops, },
+#endif
+
{},
};
^ permalink raw reply related
* [PATCH 3/4] fs_enet: Add initial support for TWR-MPC5125
From: Vladimir Ermakov @ 2011-03-16 23:37 UTC (permalink / raw)
To: linuxppc-dev
Add PHY interface selection.
On TWR-MPC5125 PHY2 connected through RMII.
Signed-off-by: Vladimir Ermakov <vooon341@gmail.com>
---
diff --git a/drivers/net/fs_enet/Kconfig b/drivers/net/fs_enet/Kconfig
index fc073b5..132966b 100644
--- a/drivers/net/fs_enet/Kconfig
+++ b/drivers/net/fs_enet/Kconfig
@@ -32,3 +32,16 @@ config FS_ENET_MDIO_FCC
tristate "MDIO driver for FCC"
depends on FS_ENET && CPM2
select MDIO_BITBANG
+
+choice FS_ENET_RCNTRL
+ prompt "PHY connection interface"
+ default FS_ENET_MII
+ depends on FS_ENET_MPC5121_FEC
+
+config FS_ENET_RCNTRL_MII
+ bool "MII"
+
+config FS_ENET_RCNTRL_RMII
+ bool "RMII"
+
+endchoice
diff --git a/drivers/net/fs_enet/fec.h b/drivers/net/fs_enet/fec.h
index e980527..468be6e 100644
--- a/drivers/net/fs_enet/fec.h
+++ b/drivers/net/fs_enet/fec.h
@@ -26,6 +26,7 @@
#define FEC_RCNTRL_BC_REJ 0x00000010
#define FEC_RCNTRL_PROM 0x00000008
#define FEC_RCNTRL_MII_MODE 0x00000004
+#define FEC_RCNTRL_RMII_MODE 0x00000124
#define FEC_RCNTRL_DRT 0x00000002
#define FEC_RCNTRL_LOOP 0x00000001
@@ -33,6 +34,11 @@
#define FEC_TCNTRL_HBC 0x00000002
#define FEC_TCNTRL_GTS 0x00000001
+#ifdef CONFIG_FS_ENET_RCNTRL_MII
+#define FEC_RCNTRL_PHY_MODE FEC_RCNTRL_MII_MODE
+#else /* CONFIG_FS_ENET_RCNTRL_RMII */
+#define FEC_RCNTRL_PHY_MODE FEC_RCNTRL_RMII_MODE
+#endif
/*
diff --git a/drivers/net/fs_enet/mac-fec.c b/drivers/net/fs_enet/mac-fec.c
index 61035fc..d43e56d 100644
--- a/drivers/net/fs_enet/mac-fec.c
+++ b/drivers/net/fs_enet/mac-fec.c
@@ -319,13 +319,13 @@ static void restart(struct net_device *dev)
#ifndef CONFIG_FS_ENET_MPC5121_FEC
FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);
- FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
+ FW(fecp, r_cntrl, FEC_RCNTRL_PHY_MODE); /* MII/RMII enable */
#else
/*
- * Only set MII mode - do not touch maximum frame length
+ * Only set MII/RMII mode - do not touch maximum frame length
* configured before.
*/
- FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE);
+ FS(fecp, r_cntrl, FEC_RCNTRL_PHY_MODE);
#endif
/*
* adjust to duplex mode
@@ -381,7 +381,7 @@ static void stop(struct net_device *dev)
/* shut down FEC1? that's where the mii bus is */
if (fpi->has_phy) {
- FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
+ FS(fecp, r_cntrl, FEC_RCNTRL_PHY_MODE); /* MII/RMII enable */
FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
FW(fecp, ievent, FEC_ENET_MII);
FW(fecp, mii_speed, feci->mii_speed);
diff --git a/drivers/net/fs_enet/mii-fec.c b/drivers/net/fs_enet/mii-fec.c
index 7e840d3..bb61ff6 100644
--- a/drivers/net/fs_enet/mii-fec.c
+++ b/drivers/net/fs_enet/mii-fec.c
@@ -161,7 +161,7 @@ static int __devinit fs_enet_mdio_probe(struct platform_device *ofdev)
fec->mii_speed = speed << 1;
- setbits32(&fec->fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
+ setbits32(&fec->fecp->fec_r_cntrl, FEC_RCNTRL_PHY_MODE);
setbits32(&fec->fecp->fec_ecntrl, FEC_ECNTRL_PINMUX |
FEC_ECNTRL_ETHER_EN);
out_be32(&fec->fecp->fec_ievent, FEC_ENET_MII);
^ permalink raw reply related
* [PATCH 4/4] mtd/nand: Add initial support for TWR-MPC5125
From: Vladimir Ermakov @ 2011-03-16 23:46 UTC (permalink / raw)
To: linuxppc-dev
Adds NAND Flash Controller driver for MPC5125.
Also adds chip id for Micron's NAND used in TWR-MPC5125.
Driver ported from original Freescale BSP (kernel 2.6.29.1).
Signed-off-by: Vladimir Ermakov <vooon341@gmail.com>
---
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index a92054e..eb660a8 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -472,6 +472,26 @@ config MTD_NAND_MPC5121_NFC
This enables the driver for the NAND flash controller on the
MPC5121 SoC.
+config MTD_NAND_MPC5125_NFC
+ tristate "MPC5125 built-in NAND Flash Controller support"
+ depends on PPC_MPC512x
+ help
+ This enables the driver for the NAND flash controller on the
+ MPC5125 SoC.
+
+config MTD_NAND_MPC5125_HWECC
+ bool "Enable hardware ECC"
+ depends on MTD_NAND_MPC5125_NFC
+ help
+ This enables the support for Software ECC handling. By
+ default FSL NAND controller Hardware ECC is supported.
+
+config NFC_DMA_ENABLE
+ bool "Enable NAND Flash DMA"
+ depends on MTD_NAND_MPC5125_NFC
+ help
+ This enables the nfc dma support
+
config MTD_NAND_MXC
tristate "MXC NAND support"
depends on IMX_HAVE_PLATFORM_MXC_NAND
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 5745d83..bd354cd 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o
obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o
obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
+obj-$(CONFIG_MTD_NAND_MPC5125_NFC) += mpc5125_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
diff --git a/drivers/mtd/nand/mpc5125_nfc.c b/drivers/mtd/nand/mpc5125_nfc.c
new file mode 100644
index 0000000..aea3186
--- /dev/null
+++ b/drivers/mtd/nand/mpc5125_nfc.c
@@ -0,0 +1,1290 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * MPC5125 Nand driver.
+ *
+ * Based on original driver from Freescale Semiconductor
+ * written by Shaohui Xie <b21989@freescale.com> on basis
+ * of drivers/mtd/nand/mpc5121_nfc.c.
+ * Modyfied by Cloudy Chen <chen_yunsong@mtcera.com>.
+ * Reworked by Vladimir Ermakov <vooon341@gmail.com>.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/gfp.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include "mpc5125_nfc.h"
+
+#define DRV_NAME "mpc5125_nfc"
+
+#define SPARE_BUFFER_MAX_SIZE 0x400
+#define DATA_BUFFER_MAX_SIZE 0x2000
+
+/* Timeouts */
+#define NFC_RESET_TIMEOUT 1000 /* 1 ms */
+#define NFC_TIMEOUT (HZ / 10) /* 1/10 s */
+
+#ifdef CONFIG_NFC_DMA_ENABLE
+#define NFC_DMA_ENABLE 1
+#else
+#define NFC_DMA_ENABLE 0
+#endif
+
+struct mpc5125_nfc_prv {
+ struct mtd_info mtd;
+ struct nand_chip chip;
+ int irq;
+ void __iomem *regs;
+ struct clk *clk;
+ wait_queue_head_t irq_waitq;
+ uint column;
+ int spareonly;
+ u32 irq_stat;
+ u32 wait_timeout;
+ void __iomem *csreg;
+ struct device *dev;
+ void *data_buffers;
+ dma_addr_t data_buffers_phyaddr;
+ void *ops_buffer;
+ dma_addr_t ops_buffer_phyaddr;
+ void *tmp_buf;
+ unsigned int sync_flags;
+};
+
+static int get_status;
+static int get_id;
+
+#define NFC_IRQ_ENABLE (IDLE_EN_MASK|WERR_EN_MASK)
+#define NFC_IRQ_MASK (IDLE_IRQ_MASK|WERR_IRQ_MASK)
+
+#define MPC5125_NFC_ECC_STATUS_ADD (NFC_SPARE_AREA(0)+0xf0)
+
+#if 1
+/* for ECC_MODE=0x6 45bytes*2 */
+static struct nand_ecclayout nand_hw_eccoob_4k_128 = {
+ .eccbytes = 90, /* actually 72 but only room for 64 */
+ .eccpos = {
+ /* 9 bytes of ecc for each 512 bytes of data */
+ 19, 20, 21, 22, 23, 24, 25, 26, 27,
+ 28, 29, 30, 31, 32, 33, 34, 35, 36,
+ 37, 38, 39, 40, 41, 42, 43, 44, 45,
+ 46, 47, 48, 49, 50, 51, 52, 53, 54,
+ 55, 56, 57, 58, 59, 60, 61, 62, 63,
+
+ 83, 84, 85, 86, 87, 88, 89, 90, 91,
+ 92, 93, 94, 95, 96, 97, 98, 99, 100,
+ 101,102, 103, 104, 105, 106, 107, 108, 109,
+ 110,111, 112, 113, 114, 115, 116, 117, 118,
+ 119,120, 121, 122, 123, 124, 125, 126, 127
+ /* 120, 121, 122, 123, 124, 125, 126, 127, */
+ },
+ .oobavail = 30,
+ .oobfree = {
+ {4, 15},
+ {68, 15}
+ }
+};
+#else
+/* for ECC_MODE=0x5 30bytes*2 */
+static struct nand_ecclayout nand_hw_eccoob_4k_128 = {
+ .eccbytes = 60, /* actually 72 but only room for 64 */
+ .eccpos = {
+ /* 9 bytes of ecc for each 512 bytes of data */
+ 34, 35, 36, 37, 38, 39, 40, 41, 42,
+ 43, 44, 45, 46, 47, 48, 49, 50, 51,
+ 52, 53, 54, 55, 56, 57, 58, 59, 60,
+ 61, 62, 63,
+
+ 98, 99, 100,
+ 101,102, 103, 104, 105, 106, 107, 108, 109,
+ 110,111, 112, 113, 114, 115, 116, 117, 118,
+ 119,120, 121, 122, 123, 124, 125, 126, 127
+ /* 120, 121, 122, 123, 124, 125, 126, 127, */
+ },
+ .oobavail = 48,
+ .oobfree = {
+ {8, 24},
+ {68, 24}
+ }
+};
+#endif
+
+static struct nand_ecclayout nand_hw_eccoob_4k_218 = {
+ .eccbytes = 64, /* actually 144 but only room for 64 */
+ .eccpos = {
+ /* 18 bytes of ecc for each 512 bytes of data */
+ 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 33, 34, 35, 36, 37, 38, 39, 40, 41,
+ 42, 43, 44, 45, 46, 47, 48, 49, 50,
+ 59, 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, 71, 72, 73, 74, 75, 76,
+ 85, 86, 87, 88, 89, 90, 91, 92, 93,
+ 94, /* 95, 96, 97, 98, 99, 100, 101, 102,
+ 111, 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127, 128,
+ 137, 138, 139, 140, 141, 142, 143, 144, 145,
+ 146, 147, 148, 149, 150, 151, 152, 153, 154,
+ 163, 164, 165, 166, 167, 168, 169, 170, 171,
+ 172, 173, 174, 175, 176, 177, 178, 179, 180,
+ 189, 190, 191, 192, 193, 194, 195, 196, 197,
+ 198, 199, 200, 201, 202, 203, 204, 205, 206, */
+ },
+ .oobavail = 4,
+ .oobfree = {
+ {0, 5}, {26, 8},
+ {52, 8}, {78, 8},
+ {104, 8}, {130, 8},
+ {156, 8}, {182, 8}
+ }
+};
+
+
+#if NFC_DMA_ENABLE
+static void mpc5125_dma_config(struct mtd_info *mtd, struct nand_chip *chip, unsigned isRead);
+static void mpc5125_nand_dma_wait(struct mtd_info *mtd, struct nand_chip *chip);
+#endif
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *mpc5125_nfc_pprobes[] = { "cmdlinepart", NULL };
+#endif
+
+/* Read NFC register */
+static inline u32 nfc_read(struct mtd_info *mtd, uint reg)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ return in_be32(prv->regs + reg);
+}
+
+/* Write NFC register */
+static inline void nfc_write(struct mtd_info *mtd, uint reg, u32 val)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ out_be32(prv->regs + reg, val);
+}
+
+/* Set bits in NFC register */
+static inline void nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
+{
+ nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
+}
+
+/* Clear bits in NFC register */
+static inline void nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
+{
+ nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
+}
+
+
+static inline void
+nfc_set_field(struct mtd_info *mtd, u32 reg, u32 mask, u32 shift, u32 val)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ out_be32(prv->regs + reg,
+ (in_be32(prv->regs + reg) & (~mask))
+ | val << shift);
+}
+
+static inline int
+nfc_get_field(struct mtd_info *mtd, u32 reg, u32 field_mask)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ return in_be32(prv->regs + reg) & field_mask;
+}
+
+static inline u8 nfc_check_status(struct mtd_info *mtd)
+{
+ u8 fls_status = 0;
+ fls_status = nfc_get_field(mtd, NFC_FLASH_STATUS2, STATUS_BYTE1_MASK);
+ return fls_status;
+}
+
+/* clear cmd_done and cmd_idle falg for the coming command */
+static void mpc5125_nfc_clear(struct mtd_info *mtd)
+{
+ nfc_write(mtd, NFC_IRQ_STATUS, 1 << CMD_DONE_CLEAR_SHIFT);
+ nfc_write(mtd, NFC_IRQ_STATUS, 1 << IDLE_CLEAR_SHIFT);
+ nfc_write(mtd, NFC_IRQ_STATUS, 1 << WERR_CLEAR_SHIFT);
+}
+
+/* Wait for operation complete */
+static void mpc5125_nfc_done(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+ int rv;
+ unsigned int wait_time = NFC_TIMEOUT;
+
+ mpc5125_nfc_clear(mtd);
+ nfc_set(mtd, NFC_IRQ_STATUS, NFC_IRQ_ENABLE);
+ prv->wait_timeout = 0;
+ prv->sync_flags = 0;
+ nfc_set_field(mtd, NFC_FLASH_CMD2, START_MASK,
+ START_SHIFT, 1);
+
+ if ((nfc_read(mtd, NFC_IRQ_STATUS) & NFC_IRQ_MASK) == 0){
+ rv = wait_event_timeout(prv->irq_waitq,
+ (nfc_read(mtd, NFC_IRQ_STATUS) & NFC_IRQ_MASK), wait_time);
+
+ if (!rv) {
+ prv->irq_stat = nfc_read(mtd, NFC_IRQ_STATUS);
+
+ if(!prv->sync_flags)
+ dev_warn(prv->dev, "Lost irq.\n");
+
+ dev_warn(prv->dev,
+ "Timeout while waiting for interrupt.\n");
+ prv->wait_timeout = 1;
+ }
+ }
+
+ mpc5125_nfc_clear(mtd);
+}
+
+static inline u8 mpc5125_nfc_get_id(struct mtd_info *mtd, int col)
+{
+ u32 flash_id1 = 0;
+ u8 *pid;
+
+ flash_id1 = nfc_read(mtd, NFC_FLASH_STATUS1);
+ pid = (u8 *)&flash_id1;
+
+ return *(pid + col);
+}
+
+static inline u8 mpc5125_nfc_get_status(struct mtd_info *mtd)
+{
+ u32 flash_status = 0;
+ u8 *pstatus;
+
+ flash_status = nfc_read(mtd, NFC_FLASH_STATUS2);
+ pstatus = (u8 *)&flash_status;
+
+ return *(pstatus + 3);
+}
+
+/* Invoke command cycle */
+static inline void
+mpc5125_nfc_send_cmd(struct mtd_info *mtd, u32 cmd_byte1,
+ u32 cmd_byte2, u32 cmd_code)
+{
+ mpc5125_nfc_clear(mtd);
+ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
+ CMD_BYTE1_SHIFT, cmd_byte1);
+
+ nfc_set_field(mtd, NFC_FLASH_CMD1, CMD_BYTE2_MASK,
+ CMD_BYTE2_SHIFT, cmd_byte2);
+
+ nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
+ BUFNO_SHIFT, 0);
+
+ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
+ CMD_CODE_SHIFT, cmd_code);
+
+ if (cmd_code == RANDOM_OUT_CMD_CODE)
+ nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
+ BUFNO_SHIFT, 1);
+}
+
+/* Receive ID and status from NAND flash */
+static inline void
+mpc5125_nfc_send_one_byte(struct mtd_info *mtd, u32 cmd_byte1, u32 cmd_code)
+{
+ mpc5125_nfc_clear(mtd);
+ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
+ CMD_BYTE1_SHIFT, cmd_byte1);
+
+ nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
+ BUFNO_SHIFT, 0);
+
+ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_CODE_MASK,
+ CMD_CODE_SHIFT, cmd_code);
+}
+
+/* NFC interrupt handler */
+static irqreturn_t mpc5125_nfc_irq(int irq, void *data)
+{
+ struct mtd_info *mtd = data;
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ prv->irq_stat = nfc_read(mtd, NFC_IRQ_STATUS);
+ nfc_clear(mtd, NFC_IRQ_STATUS, NFC_IRQ_ENABLE);
+ wake_up(&prv->irq_waitq);
+ /*mpc5125_nfc_clear(mtd);*/
+ prv->sync_flags |= 1;
+
+ return IRQ_HANDLED;
+}
+
+/* Do address cycle(s) */
+static void mpc5125_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
+{
+
+ if (column != -1) {
+ nfc_set_field(mtd, NFC_COL_ADDR,
+ COL_ADDR_MASK,
+ COL_ADDR_SHIFT, column);
+ }
+
+ if (page != -1) {
+ nfc_set_field(mtd, NFC_ROW_ADDR,
+ ROW_ADDR_MASK,
+ ROW_ADDR_SHIFT, page);
+ }
+ /* DMA Disable */
+#if (NFC_DMA_ENABLE<1)
+ nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_MASK);
+#endif
+ /* PAGE_CNT = 2 */
+ nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
+ CONFIG_PAGE_CNT_SHIFT, 0x2);
+}
+
+
+/* Control chips select signal on ADS5125 board */
+static void ads5125_select_chip(struct mtd_info *mtd, int chip)
+{
+
+ if ((chip < 0)||(chip > 3)) {
+ nfc_set_field(mtd, NFC_ROW_ADDR,
+ ROW_ADDR_CHIP_SEL_RB_MASK,
+ ROW_ADDR_CHIP_SEL_RB_SHIFT, 0);
+
+ nfc_set_field(mtd, NFC_ROW_ADDR,
+ ROW_ADDR_CHIP_SEL_MASK,
+ ROW_ADDR_CHIP_SEL_SHIFT, 0);
+ return;
+ }
+
+ nfc_set_field(mtd, NFC_ROW_ADDR,
+ ROW_ADDR_CHIP_SEL_RB_MASK,
+ ROW_ADDR_CHIP_SEL_RB_SHIFT, (1<<chip));
+
+ nfc_set_field(mtd, NFC_ROW_ADDR,
+ ROW_ADDR_CHIP_SEL_MASK,
+ ROW_ADDR_CHIP_SEL_SHIFT, (1<<chip));
+}
+
+/* Read NAND Ready/Busy signal */
+static int mpc5125_nfc_dev_ready(struct mtd_info *mtd)
+{
+ /*
+ * NFC handles ready/busy signal internally. Therefore, this function
+ * always returns status as ready.
+ */
+ return 1;
+}
+
+/* Write command to NAND flash */
+static void mpc5125_nfc_command(struct mtd_info *mtd, unsigned command,
+ int column, int page)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ prv->column = (column >= 0) ? column : 0;
+ prv->spareonly = 0;
+ get_id = 0;
+ get_status = 0;
+
+
+ switch (command) {
+ case NAND_CMD_PAGEPROG:
+#if (NFC_DMA_ENABLE)
+ mpc5125_nfc_send_cmd(mtd,
+ PROGRAM_PAGE_CMD_BYTE1,
+ PROGRAM_PAGE_CMD_BYTE2,
+ DMA_PROGRAM_PAGE_CMD_CODE);
+ /*
+ nfc_set_field(mtd, NFC_FLASH_CMD2, CMD_BYTE1_MASK,
+ CMD_BYTE1_SHIFT, READ_STATUS_CMD_BYTE);
+ */
+ mpc5125_dma_config(mtd, chip, 0);
+#else
+ mpc5125_nfc_send_cmd(mtd,
+ PROGRAM_PAGE_CMD_BYTE1,
+ PROGRAM_PAGE_CMD_BYTE2,
+ PROGRAM_PAGE_CMD_CODE);
+#endif
+ break;
+ /*
+ * NFC does not support sub-page reads and writes,
+ * so emulate them using full page transfers.
+ */
+ case NAND_CMD_READ0:
+ column = 0;
+ goto read0;
+ break;
+
+ case NAND_CMD_READ1:
+ prv->column += 256;
+ command = NAND_CMD_READ0;
+ column = 0;
+ goto read0;
+ break;
+
+ case NAND_CMD_READOOB:
+ prv->spareonly = 1;
+ command = NAND_CMD_READ0;
+ column = 0;
+
+read0:
+ mpc5125_nfc_send_cmd(mtd,
+ PAGE_READ_CMD_BYTE1,
+ PAGE_READ_CMD_BYTE2,
+ READ_PAGE_CMD_CODE);
+#if NFC_DMA_ENABLE
+ mpc5125_dma_config(mtd, chip, 1);
+#endif
+ break;
+
+ case NAND_CMD_SEQIN:
+ mpc5125_nfc_command(mtd, NAND_CMD_READ0, column, page);
+ column = 0;
+ break;
+
+ case NAND_CMD_ERASE1:
+ mpc5125_nfc_send_cmd(mtd,
+ ERASE_CMD_BYTE1,
+ ERASE_CMD_BYTE2,
+ ERASE_CMD_CODE);
+ break;
+
+ case NAND_CMD_ERASE2:
+ return;
+
+ case NAND_CMD_READID:
+ get_id = 1;
+ mpc5125_nfc_send_one_byte(mtd, command, READ_ID_CMD_CODE);
+ break;
+
+ case NAND_CMD_STATUS:
+ get_status = 1;
+ mpc5125_nfc_send_one_byte(mtd, command, STATUS_READ_CMD_CODE);
+ break;
+
+ case NAND_CMD_RNDOUT:
+ mpc5125_nfc_send_cmd(mtd,
+ RANDOM_OUT_CMD_BYTE1,
+ RANDOM_OUT_CMD_BYTE2,
+ RANDOM_OUT_CMD_CODE);
+ break;
+
+ default:
+ return;
+ }
+
+ mpc5125_nfc_addr_cycle(mtd, column, page);
+ mpc5125_nfc_done(mtd);
+
+#if (NFC_DMA_ENABLE)
+ /* mpc5125_nand_dma_wait(mtd, chip); */
+ nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_MASK);
+#endif
+}
+
+/* Copy data from/to NFC spare buffers. */
+static void mpc5125_nfc_copy_spare(struct mtd_info *mtd, uint offset,
+ u8 *buffer, uint size, int wr)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct mpc5125_nfc_prv *prv = nand->priv;
+ u16 ooblen = mtd->oobsize;
+ u8 i, count;
+ uint sbsize, blksize;
+
+ /*
+ * NAND spare area is available through NFC spare buffers.
+ * The NFC divides spare area into (page_size / 512) chunks.
+ * Each chunk is placed into separate spare memory area, using
+ * first (spare_size / num_of_chunks) bytes of the buffer.
+ *
+ * For NAND device in which the spare area is not divided fully
+ * by the number of chunks, number of used bytes in each spare
+ * buffer is rounded down to the nearest even number of bytes,
+ * and all remaining bytes are added to the last used spare area.
+ *
+ * For more information read section 26.6.10 of MPC5121e
+ * Microcontroller Reference Manual, Rev. 3.
+ */
+
+ /* Calculate number of valid bytes in each spare buffer */
+ count = mtd->writesize >> 11;
+ count = (count > 0) ? count : 1;
+ sbsize = (ooblen / count >> 1) << 1;
+
+ for (i=0; (i < count) && size; i++) {
+ blksize = min(sbsize, size);
+ if (wr)
+ memcpy_toio(prv->regs + NFC_SPARE_AREA(i),
+ buffer, blksize);
+ else
+ memcpy_fromio(buffer,
+ prv->regs + NFC_SPARE_AREA(i), blksize);
+
+ buffer += blksize;
+ offset += blksize;
+ size -= blksize;
+ }
+}
+
+/* Copy data from/to NFC main and spare buffers */
+static void
+mpc5125_nfc_buf_copy(struct mtd_info *mtd, u8 *buf, int len, int wr)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+ uint c = prv->column;
+ uint l;
+
+ /* Handle spare area access */
+ if (prv->spareonly || c >= mtd->writesize) {
+ /* Calculate offset from beginning of spare area */
+ if (c >= mtd->writesize)
+ c -= mtd->writesize;
+
+ prv->column += len;
+#if NFC_DMA_ENABLE
+ if (wr)
+ memcpy(prv->ops_buffer, buf, len);
+ else
+ memcpy(buf, prv->ops_buffer, len);
+#else
+ mpc5125_nfc_copy_spare(mtd, c, buf, len, wr);
+#endif
+ return;
+ }
+
+ /*
+ * Handle main area access - limit copy length to prevent
+ * crossing main/spare boundary.
+ */
+ l = min((uint)len, mtd->writesize - c);
+ prv->column += l;
+
+ if (wr) {
+#if NFC_DMA_ENABLE
+ memcpy(prv->data_buffers+c, buf, len);
+#else
+ unsigned int size, i;
+ for (i=(c/PAGE_2K); i < 4; i++) {
+ size = min(len, PAGE_2K);
+ memcpy_toio(prv->regs + NFC_MAIN_AREA(i) + c, buf, size);
+ buf += size;
+ len -= size;
+ if (!len)
+ break;
+ }
+#endif
+ } else {
+ if (get_status) {
+ get_status = 0;
+ *buf = mpc5125_nfc_get_status(mtd);
+ } else if (l == 1 && c <= 3 && get_id) {
+ *buf = mpc5125_nfc_get_id(mtd, c);
+ } else {
+ unsigned int size, i;
+#if NFC_DMA_ENABLE
+ if (len == mtd->writesize)
+ memcpy(buf, prv->data_buffers+c, len);
+ else
+#endif
+ for (i=(c/PAGE_2K); i < 4; i++) {
+ size = min(len, PAGE_2K);
+ memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(i) + c, size);
+ buf += size;
+ len -= size;
+ if (!len)
+ break;
+ }
+ }
+ }
+}
+
+/* Read data from NFC buffers */
+static void mpc5125_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+ mpc5125_nfc_buf_copy(mtd, buf, len, 0);
+}
+
+/* Write data to NFC buffers */
+static void mpc5125_nfc_write_buf(struct mtd_info *mtd,
+ const u_char *buf, int len)
+{
+ mpc5125_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
+}
+
+/* Compare buffer with NAND flash */
+static int mpc5125_nfc_verify_buf(struct mtd_info *mtd,
+ const u_char *buf, int len)
+{
+ u_char tmp[256];
+ uint bsize;
+
+ while (len) {
+ bsize = min(len, 256);
+ mpc5125_nfc_read_buf(mtd, tmp, bsize);
+
+ if (memcmp(buf, tmp, bsize))
+ return 1;
+
+ buf += bsize;
+ len -= bsize;
+ }
+
+ return 0;
+}
+
+/* Read byte from NFC buffers */
+static u8 mpc5125_nfc_read_byte(struct mtd_info *mtd)
+{
+ u8 tmp;
+
+ mpc5125_nfc_read_buf(mtd, &tmp, sizeof(tmp));
+
+ return tmp;
+}
+
+/* Read word from NFC buffers */
+static u16 mpc5125_nfc_read_word(struct mtd_info *mtd)
+{
+ u16 tmp;
+
+ mpc5125_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
+
+ return tmp;
+}
+
+/*
+ * Read NFC configuration from Reset Config Word
+ *
+ */
+static int mpc5125_nfc_read_hw_config(struct mtd_info *mtd)
+{
+ uint rcw_pagesize = 0;
+ uint rcw_sparesize = 0;
+
+ /* TODO */
+ rcw_pagesize = 4096;
+ rcw_sparesize = 128;
+ mtd->writesize = rcw_pagesize;
+ mtd->oobsize = rcw_sparesize;
+
+ return 0;
+}
+
+/* Free driver resources */
+static void mpc5125_nfc_free(struct device *dev, struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ if (prv->clk) {
+ clk_disable(prv->clk);
+ clk_put(prv->clk);
+ }
+
+ if (prv->csreg)
+ iounmap(prv->csreg);
+}
+
+static void mpc5125_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_MODE_MASK,
+ CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
+ return;
+}
+
+/*
+ * Function to correct the detected errors. This NFC corrects all the errors
+ * detected. So this function is not required.
+ */
+static int mpc5125_nand_correct_data(struct mtd_info *mtd, u_char * dat,
+ u_char * read_ecc, u_char * calc_ecc)
+{
+ panic("Shouldn't be called here: %d\n", __LINE__);
+ return 0; /* FIXME */
+}
+
+/*
+ * Function to calculate the ECC for the data to be stored in the Nand device.
+ * This NFC has a hardware RS(511,503) ECC engine together with the RS ECC
+ * CONTROL blocks are responsible for detection and correction of up to
+ * 4 symbols of 9 bits each in 528 byte page.
+ * So this function is not required.
+ */
+static int mpc5125_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat,
+ u_char * ecc_code)
+{
+ panic(KERN_ERR "Shouldn't be called here %d \n", __LINE__);
+ return 0; /* FIXME */
+}
+
+static int mpc5125_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page, int sndcmd)
+{
+
+ if (sndcmd) {
+ mpc5125_nfc_command(mtd, NAND_CMD_READ0, 0, page);
+ sndcmd = 0;
+ }
+
+#if NFC_DMA_ENABLE
+{
+ struct mpc5125_nfc_prv *prv = chip->priv;
+ memcpy(chip->oob_poi, prv->ops_buffer, mtd->oobsize);
+}
+#else
+ mpc5125_nfc_copy_spare(mtd, 0, chip->oob_poi, mtd->oobsize, 0);
+#endif
+ return sndcmd;
+}
+
+static int mpc5125_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+// unsigned int stat;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+ mpc5125_nfc_command(mtd, NAND_CMD_READ0, 0, page);
+#if NFC_DMA_ENABLE
+ memcpy(prv->ops_buffer, chip->oob_poi, mtd->oobsize);
+#else
+ mpc5125_nfc_copy_spare(mtd, 0, chip->oob_poi, mtd->oobsize, 1);
+#endif
+ mpc5125_nfc_command(mtd, NAND_CMD_PAGEPROG, 0, page);
+
+ if (prv->wait_timeout) {
+ dev_err(prv->dev, "%s wait timeout.\n", __FUNCTION__);
+ return -EIO;
+ }
+ if (prv->irq_stat & WERR_IRQ_MASK) {
+ dev_err(prv->dev, "%s faield.\n", __FUNCTION__);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int mpc5125_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t * buf, int page)
+{
+ unsigned int stat;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+ u8 *erase_page_check, ecc_bytes = 0;
+ const u8 ecc_bytes_map[] = {0, 8, 12, 15, 23, 30, 45, 60};
+
+ stat = nfc_read(mtd, NFC_FLASH_CONFIG);
+ stat >>= 17;
+ stat &= 0x7;
+ ecc_bytes = ecc_bytes_map[stat];
+
+ erase_page_check = (u8 *)(PAGE_virtual_2K - ecc_bytes + prv->regs);
+ stat = nfc_read(mtd, MPC5125_NFC_ECC_STATUS_ADD + 4);
+
+ if (stat & 0x80) {
+ /*check the page is erased*/
+ if (stat & 0x3f) {
+ mtd->ecc_stats.failed++;
+ dev_warn(prv->dev, "Uncorrectable RS-ECC Error\n");
+ }
+
+ } else if (stat & 0x3f) {
+ /* dev_notice(prv->dev, "Correctable ECC %d\n", stat & 0x3f); */
+ mtd->ecc_stats.corrected += stat & 0x3f;
+ }
+
+#if NFC_DMA_ENABLE
+ memcpy(buf, prv->data_buffers, mtd->writesize);
+ memcpy(chip->oob_poi, prv->ops_buffer, mtd->oobsize);
+#else
+ mpc5125_nfc_buf_copy(mtd, buf, mtd->writesize, 0);
+ mpc5125_nfc_copy_spare(mtd, 0, chip->oob_poi, mtd->oobsize, 0);
+#endif
+
+ return 0;
+}
+
+static void mpc5125_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf)
+{
+#if NFC_DMA_ENABLE
+ struct mpc5125_nfc_prv *prv = chip->priv;
+ memcpy(prv->data_buffers, buf, mtd->writesize);
+ memcpy(prv->ops_buffer, chip->oob_poi, mtd->oobsize);
+#else
+ mpc5125_nfc_buf_copy(mtd, buf, mtd->writesize, 1);
+ mpc5125_nfc_copy_spare(mtd, 0, chip->oob_poi, mtd->oobsize, 1);
+#endif
+}
+
+static int chip_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int page, int cached, int raw)
+{
+ int status;
+#if (NFC_DMA_ENABLE<1)
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+#endif
+ if (unlikely(raw))
+ chip->ecc.write_page_raw(mtd, chip, buf);
+ else
+ chip->ecc.write_page(mtd, chip, buf);
+
+ /*
+ * Cached progamming disabled for now, Not sure if its worth the
+ * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
+ */
+ cached = 0;
+
+ if (!cached || !(chip->options & NAND_CACHEPRG)) {
+#if NFC_DMA_ENABLE
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, 0x00, page);
+#else
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+#endif
+
+ status = chip->waitfunc(mtd, chip);
+ /*
+ * See if operation failed and additional status checks are
+ * available
+ */
+ if ((status & NAND_STATUS_FAIL) && (chip->errstat))
+ status = chip->errstat(mtd, chip, FL_WRITING, status,
+ page);
+
+ if (status & NAND_STATUS_FAIL)
+ return -EIO;
+ } else {
+#if NFC_DMA_ENABLE
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, 0x00, page);
+#else
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+#endif
+ status = chip->waitfunc(mtd, chip);
+ }
+ if (nfc_get_field(mtd, NFC_IRQ_STATUS, WERR_IRQ_MASK|WERR_STATUS_MASK)) {
+ printk(KERN_ERR "%s line:%d write page %d failed\n", __FUNCTION__, __LINE__, page);
+ nfc_set_field(mtd, NFC_IRQ_STATUS,
+ WERR_CLEAR_MASK,
+ WERR_CLEAR_SHIFT, 1);
+ return -EIO;
+ }
+ return 0;
+}
+
+#if NFC_DMA_ENABLE
+static void mpc5125_dma_config(struct mtd_info *mtd,
+ struct nand_chip *chip, unsigned isRead)
+{
+ struct mpc5125_nfc_prv *prv = chip->priv;
+ nfc_write(mtd, NFC_DMA1_ADDR, prv->data_buffers_phyaddr);
+ nfc_write(mtd, NFC_DMA2_ADDR, prv->ops_buffer_phyaddr);
+
+ if (isRead)
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_DMA_REQ_MASK,
+ CONFIG_DMA_REQ_SHIFT, 1);
+ else
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_DMA_REQ_MASK,
+ CONFIG_DMA_REQ_SHIFT, 0);
+
+ nfc_set_field(mtd, NFC_FLASH_COMMAND_REPEAT,
+ COMMAND_REPEAT_MASK,
+ COMMAND_REPEAT_SHIFT, 0);
+ nfc_set_field(mtd, NFC_FLASH_CMD2, BUFNO_MASK,
+ BUFNO_SHIFT, 0);
+}
+
+static void mpc5125_nand_dma_wait(struct mtd_info *mtd,
+ struct nand_chip *chip)
+{
+ struct mpc5125_nfc_prv *prv = chip->priv;
+ int rv;
+
+ if ((DMA_BUSY_MASK|ECC_BUSY_MASK|RESIDUE_BUSY_MASK) &
+ nfc_read(mtd, NFC_IRQ_STATUS)) {
+ rv = wait_event_timeout(prv->irq_waitq,
+ (nfc_read(mtd, NFC_IRQ_STATUS) &
+ (CMD_DONE_IRQ_MASK|IDLE_IRQ_MASK)) ==
+ (CMD_DONE_IRQ_MASK|IDLE_IRQ_MASK),
+ NFC_TIMEOUT * 4);
+ if (!rv) {
+ prv->irq_stat = nfc_read(mtd, NFC_IRQ_STATUS);
+ dev_err(prv->dev, "%s timeout status: %08x\n", __FUNCTION__, prv->irq_stat);
+ prv->wait_timeout = 1;
+ }
+ }
+}
+
+/**
+ * nand_read_page_raw - [Intern] read raw page data without ecc
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: buffer to store read data
+ */
+static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int page)
+{
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ memcpy(buf, prv->data_buffers, mtd->writesize);
+ memcpy(chip->oob_poi, prv->ops_buffer, mtd->oobsize);
+
+ return 0;
+}
+
+/**
+ * nand_write_page_raw - [Intern] raw page write function
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+ * @buf: data buffer
+ */
+static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf)
+{
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ memcpy(prv->data_buffers, buf, mtd->writesize);
+ memcpy(prv->ops_buffer, chip->oob_poi, mtd->oobsize);
+ mpc5125_dma_config(mtd, chip, 0);
+}
+#endif
+
+static int __devinit mpc5125_nfc_probe(struct platform_device *op)
+{
+ struct device_node *dn = op->dev.of_node;
+ struct device *dev = &op->dev;
+ struct mpc5125_nfc_prv *prv;
+ struct resource res;
+ struct mtd_info *mtd;
+#ifdef CONFIG_MTD_PARTITIONS
+ struct mtd_partition *parts;
+#endif
+ struct nand_chip *chip;
+ unsigned long regs_paddr, regs_size;
+ const __be32 *chips_no;
+ int retval = 0;
+ int len;
+
+ prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
+ if (!prv) {
+ dev_err(dev, "Memory exhausted!\n");
+ return -ENOMEM;
+ }
+
+ mtd = &prv->mtd;
+ chip = &prv->chip;
+
+ mtd->priv = chip;
+ chip->priv = prv;
+ prv->dev = dev;
+
+ /* Read NFC configuration from Reset Config Word */
+ retval = mpc5125_nfc_read_hw_config(mtd);
+ if (retval) {
+ dev_err(dev, "Unable to read NFC config!\n");
+ return retval;
+ }
+
+ /* speed up nand flash r/w add by cloudy */
+ {
+ volatile u32 *nfc_div = ioremap(0x80000f80, sizeof(u32));
+ if (!nfc_div)
+ dev_err(dev, "Unable to speed up nfc !\n");
+ else {
+#ifdef CONFIG_MTD_NAND_MPC5125_HWECC
+ *nfc_div = 0x1430 << 16;
+#else
+ *nfc_div = 0x2860 << 16;
+#endif
+ iounmap(nfc_div);
+ }
+ }
+
+ prv->irq = irq_of_parse_and_map(dn, 0);
+ if (prv->irq == NO_IRQ) {
+ dev_err(dev, "Error mapping IRQ!\n");
+ return -EINVAL;
+ }
+
+ retval = of_address_to_resource(dn, 0, &res);
+ if (retval) {
+ dev_err(dev, "Error parsing memory region!\n");
+ return retval;
+ }
+
+ chips_no = of_get_property(dn, "chips", &len);
+ if (!chips_no || len != sizeof(*chips_no)) {
+ dev_err(dev, "Invalid/missing 'chips' property!\n");
+ return -EINVAL;
+ }
+
+ regs_paddr = res.start;
+ regs_size = res.end - res.start + 1;
+
+ if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
+ dev_err(dev, "Error requesting memory region!\n");
+ return -EBUSY;
+ }
+
+ prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
+ if (!prv->regs) {
+ dev_err(dev, "Error mapping memory region!\n");
+ return -ENOMEM;
+ }
+
+ prv->data_buffers = dma_alloc_coherent(dev, DATA_BUFFER_MAX_SIZE,
+ &prv->data_buffers_phyaddr, GFP_KERNEL);
+ if (!prv->data_buffers) {
+ return -ENOMEM;
+ }
+
+ prv->ops_buffer = dma_alloc_coherent(dev, SPARE_BUFFER_MAX_SIZE,
+ &prv->ops_buffer_phyaddr, GFP_KERNEL);
+ if (!prv->ops_buffer) {
+ dma_free_coherent(dev, DATA_BUFFER_MAX_SIZE,
+ prv->data_buffers, prv->data_buffers_phyaddr);
+ return -ENOMEM;
+ }
+
+ /* Enable NFC clock */
+ prv->clk = clk_get(dev, "nfc_clk");
+ if (!prv->clk) {
+ dev_err(dev, "Unable to acquire NFC clock!\n");
+ retval = -ENODEV;
+ goto error;
+ }
+
+ clk_enable(prv->clk);
+ init_waitqueue_head(&prv->irq_waitq);
+ retval = devm_request_irq(dev, prv->irq, &mpc5125_nfc_irq,
+ 0, DRV_NAME, mtd);
+ if (retval) {
+ dev_err(dev, "Error requesting IRQ!\n");
+ goto error;
+ }
+
+ mtd->name = "MPC5125 NAND";
+ chip->write_page = chip_nand_write_page;
+ chip->dev_ready = mpc5125_nfc_dev_ready;
+ chip->cmdfunc = mpc5125_nfc_command;
+ chip->read_byte = mpc5125_nfc_read_byte;
+ chip->read_word = mpc5125_nfc_read_word;
+ chip->read_buf = mpc5125_nfc_read_buf;
+ chip->write_buf = mpc5125_nfc_write_buf;
+ chip->verify_buf = mpc5125_nfc_verify_buf;
+ chip->select_chip = ads5125_select_chip;
+ chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
+
+#ifdef CONFIG_MTD_NAND_MPC5125_HWECC
+ chip->ecc.read_page = mpc5125_nand_read_page;
+ chip->ecc.write_page = mpc5125_nand_write_page;
+ chip->ecc.read_oob = mpc5125_nand_read_oob;
+ chip->ecc.write_oob = mpc5125_nand_write_oob;
+ chip->ecc.calculate = mpc5125_nand_calculate_ecc;
+ chip->ecc.hwctl = mpc5125_nand_enable_hwecc;
+ chip->ecc.correct = mpc5125_nand_correct_data;
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.size = 512; /* RS-ECC is applied for both MAIN+SPARE not MAIN alone */
+ chip->ecc.bytes = 9; /* used for both main and spare area */
+ chip->ecc.layout = &nand_hw_eccoob_4k_128;
+
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_SRAM_ADDR_MASK,
+ CONFIG_ECC_SRAM_ADDR_SHIFT,
+ (MPC5125_NFC_ECC_STATUS_ADD>>3) & 0x00001ff);
+
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_MODE_MASK,
+ CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
+
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_CMD_TIMEOUT_MASK,
+ CONFIG_CMD_TIMEOUT_SHIFT, 0xf);
+
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_SRAM_REQ_MASK,
+ CONFIG_ECC_SRAM_REQ_SHIFT, 1);
+
+#else
+#if NFC_DMA_ENABLE
+ chip->ecc.read_page_raw = nand_read_page_raw;
+ chip->ecc.write_page_raw = nand_write_page_raw;
+#endif
+ chip->ecc.mode = NAND_ECC_SOFT;
+ chip->ecc.layout = &nand_hw_eccoob_4k_128;
+
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_MODE_MASK,
+ CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
+
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ECC_SRAM_REQ_MASK,
+ CONFIG_ECC_SRAM_REQ_SHIFT, 0);
+#endif /* CONFIG_MTD_NAND_MPC5125_HWECC */
+
+ /* SET SECTOR SIZE */
+ nfc_write(mtd, NFC_SECTOR_SIZE, PAGE_virtual_2K);
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_PAGE_CNT_MASK,
+ CONFIG_PAGE_CNT_SHIFT, 2);
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_ADDR_AUTO_INCR_MASK,
+ CONFIG_ADDR_AUTO_INCR_SHIFT, 0);
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_BUFNO_AUTO_INCR_MASK,
+ CONFIG_BUFNO_AUTO_INCR_SHIFT, 1);
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_16BIT_MASK,
+ CONFIG_16BIT_SHIFT, 0);
+
+#if NFC_DMA_ENABLE
+ nfc_set_field(mtd, NFC_DMA_CONFIG, DMA_CONFIG_DMA1_CNT_MASK,
+ DMA_CONFIG_DMA1_CNT_SHIFT, PAGE_2K);
+ nfc_set_field(mtd, NFC_DMA_CONFIG, DMA_CONFIG_DMA2_CNT_MASK,
+ DMA_CONFIG_DMA2_CNT_SHIFT, PAGE_64);
+ nfc_set_field(mtd, NFC_DMA_CONFIG, DMA_CONFIG_DMA1_ACT_MASK,
+ DMA_CONFIG_DMA1_ACT_SHIFT, 1);
+ nfc_set_field(mtd, NFC_DMA_CONFIG, DMA_CONFIG_DMA2_OFFSET_MASK,
+ DMA_CONFIG_DMA2_OFFSET_SHIFT, (PAGE_2K>>1));
+ nfc_set_field(mtd, NFC_DMA_CONFIG, DMA_CONFIG_DMA2_ACT_MASK,
+ DMA_CONFIG_DMA2_ACT_SHIFT, 1);
+#endif
+
+ /* SET FAST_FLASH = 1 */
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_FAST_FLASH_MASK,
+ CONFIG_FAST_FLASH_SHIFT, 1);
+ nfc_set_field(mtd, NFC_FLASH_CONFIG,
+ CONFIG_BOOT_MODE_MASK,
+ CONFIG_BOOT_MODE_SHIFT, 0);
+
+ /* Detect NAND chips */
+ if (nand_scan(mtd, be32_to_cpup(chips_no))) {
+ dev_err(dev, "NAND Flash not found !\n");
+ devm_free_irq(dev, prv->irq, mtd);
+ retval = -ENXIO;
+ goto error;
+ }
+
+ dev_set_drvdata(dev, mtd);
+
+ /* Register device in MTD */
+#ifdef CONFIG_MTD_PARTITIONS
+ retval = parse_mtd_partitions(mtd, mpc5125_nfc_pprobes, &parts, 0);
+#ifdef CONFIG_MTD_OF_PARTS
+ if (retval == 0)
+ retval = of_mtd_parse_partitions(dev, dn, &parts);
+#endif
+ if (retval < 0) {
+ dev_err(dev, "Error parsing MTD partitions!\n");
+ devm_free_irq(dev, prv->irq, mtd);
+ retval = -EINVAL;
+ goto error;
+ }
+
+ if (retval > 0)
+ retval = add_mtd_partitions(mtd, parts, retval);
+ else
+#endif
+ retval = add_mtd_device(mtd);
+
+ if (retval) {
+ dev_err(dev, "Error adding MTD device!\n");
+ devm_free_irq(dev, prv->irq, mtd);
+ goto error;
+ }
+
+ return 0;
+error:
+ dma_free_coherent(dev, DATA_BUFFER_MAX_SIZE, prv->data_buffers, prv->data_buffers_phyaddr);
+ dma_free_coherent(dev, SPARE_BUFFER_MAX_SIZE, prv->ops_buffer, prv->ops_buffer_phyaddr);
+ mpc5125_nfc_free(dev, mtd);
+ return retval;
+}
+
+static int __exit mpc5125_nfc_remove(struct platform_device *op)
+{
+ struct device *dev = &op->dev;
+ struct mtd_info *mtd = dev_get_drvdata(dev);
+ struct nand_chip *chip = mtd->priv;
+ struct mpc5125_nfc_prv *prv = chip->priv;
+
+ nand_release(mtd);
+ devm_free_irq(dev, prv->irq, mtd);
+ dma_free_coherent(dev, DATA_BUFFER_MAX_SIZE, prv->data_buffers, prv->data_buffers_phyaddr);
+ dma_free_coherent(dev, SPARE_BUFFER_MAX_SIZE, prv->ops_buffer, prv->ops_buffer_phyaddr);
+ mpc5125_nfc_free(dev, mtd);
+
+ return 0;
+}
+
+static struct of_device_id mpc5125_nfc_match[] __devinitdata = {
+ { .compatible = "fsl,mpc5125-nfc", },
+ {},
+};
+
+static struct platform_driver mpc5125_nfc_driver = {
+ .probe = mpc5125_nfc_probe,
+ .remove = __devexit_p(mpc5125_nfc_remove),
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = mpc5125_nfc_match,
+ },
+};
+
+static int __init mpc5125_nfc_init(void)
+{
+ return platform_driver_register(&mpc5125_nfc_driver);
+}
+
+module_init(mpc5125_nfc_init);
+
+static void __exit mpc5125_nfc_cleanup(void)
+{
+ platform_driver_unregister(&mpc5125_nfc_driver);
+}
+
+module_exit(mpc5125_nfc_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MPC5125 NAND MTD driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/mpc5125_nfc.h b/drivers/mtd/nand/mpc5125_nfc.h
new file mode 100644
index 0000000..5cb312c
--- /dev/null
+++ b/drivers/mtd/nand/mpc5125_nfc.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Shaohui Xie <b21989@freescale.com>
+ *
+ * Description:
+ * MPC5125 Nand driver.
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef MPC5125_NFC_H
+#define MPC5125_NFC_H
+
+/* Addresses for NFC MAIN RAM BUFFER areas */
+#define NFC_MAIN_AREA(n) ((n) * 0x1000)
+
+/* Addresses for NFC SPARE BUFFER areas */
+#define NFC_SPARE_BUFFERS 8
+#define NFC_SPARE_LEN 0x10
+#define NFC_SPARE_AREA(n) (0x800 + NFC_MAIN_AREA(n))
+
+#define PAGE_2K 0x0800
+#define PAGE_virtual_2K 0x0840
+#define PAGE_64 0x0040
+
+/* MPC5125 NFC registers */
+/* Typical Flash Commands */
+#define READ_PAGE_CMD_CODE 0x7EE0
+#define DMA_READ_PAGE_CMD_CODE 0x7EE0
+#define PROGRAM_PAGE_CMD_CODE 0x7FC0
+#define ERASE_CMD_CODE 0x4EC0
+#define READ_ID_CMD_CODE 0x4804
+#define RESET_CMD_CODE 0x4040
+#define DMA_PROGRAM_PAGE_CMD_CODE 0xFFC0
+#define RANDOM_IN_CMD_CODE 0x7140
+#define RANDOM_OUT_CMD_CODE 0x70E0
+#define STATUS_READ_CMD_CODE 0x4068
+
+#define PAGE_READ_CMD_BYTE1 0x00
+#define PAGE_READ_CMD_BYTE2 0x30
+#define PROGRAM_PAGE_CMD_BYTE1 0x80
+#define PROGRAM_PAGE_CMD_BYTE2 0x10
+#define READ_STATUS_CMD_BYTE 0x70
+#define ERASE_CMD_BYTE1 0x60
+#define ERASE_CMD_BYTE2 0xD0
+#define READ_ID_CMD_BYTE 0x90
+#define RESET_CMD_BYTE 0xFF
+#define RANDOM_OUT_CMD_BYTE1 0x05
+#define RANDOM_OUT_CMD_BYTE2 0xE0
+
+/* NFC ECC mode define */
+#define ECC_BYPASS 0x0
+#define ECC_8_BYTE 0x1
+#define ECC_12_BYTE 0x2
+#define ECC_15_BYTE 0x3
+#define ECC_23_BYTE 0x4
+#define ECC_30_BYTE 0x5
+#define ECC_45_BYTE 0x6
+#define ECC_60_BYTE 0x7
+#define ECC_ERROR 1
+#define ECC_RIGHT 0
+
+/***************** Module-Relative Register Offsets *************************/
+#define NFC_SRAM_BUFFER 0x0000
+#define NFC_FLASH_CMD1 0x3F00
+#define NFC_FLASH_CMD2 0x3F04
+#define NFC_COL_ADDR 0x3F08
+#define NFC_ROW_ADDR 0x3F0c
+#define NFC_FLASH_COMMAND_REPEAT 0x3F10
+#define NFC_ROW_ADDR_INC 0x3F14
+#define NFC_FLASH_STATUS1 0x3F18
+#define NFC_FLASH_STATUS2 0x3F1c
+#define NFC_DMA1_ADDR 0x3F20
+#define NFC_DMA2_ADDR 0x3F34
+#define NFC_DMA_CONFIG 0x3F24
+#define NFC_CACHE_SWAP 0x3F28
+#define NFC_SECTOR_SIZE 0x3F2c
+#define NFC_FLASH_CONFIG 0x3F30
+#define NFC_IRQ_STATUS 0x3F38
+
+/***************** Module-Relative Register Reset Value *********************/
+#define NFC_SRAM_BUFFER_RSTVAL 0x00000000
+#define NFC_FLASH_CMD1_RSTVAL 0x30FF0000
+#define NFC_FLASH_CMD2_RSTVAL 0x007EE000
+#define NFC_COL_ADDR_RSTVAL 0x00000000
+#define NFC_ROW_ADDR_RSTVAL 0x11000000
+#define NFC_FLASH_COMMAND_REPEAT_RSTVAL 0x00000000
+#define NFC_ROW_ADDR_INC_RSTVAL 0x00000001
+#define NFC_FLASH_STATUS1_RSTVAL 0x00000000
+#define NFC_FLASH_STATUS2_RSTVAL 0x00000000
+#define NFC_DMA1_ADDR_RSTVAL 0x00000000
+#define NFC_DMA2_ADDR_RSTVAL 0x00000000
+#define NFC_DMA_CONFIG_RSTVAL 0x00000000
+#define NFC_CACHE_SWAP_RSTVAL 0x0FFE0FFE
+#define NFC_SECTOR_SIZE_RSTVAL 0x00000420
+#define NFC_FLASH_CONFIG_RSTVAL 0x000EA631
+#define NFC_IRQ_STATUS_RSTVAL 0x04000000
+
+/***************** Module-Relative Register Mask *************************/
+
+/* NFC_FLASH_CMD1 Field */
+#define CMD1_MASK 0xFFFF0000
+#define CMD1_SHIFT 0
+#define CMD_BYTE2_MASK 0xFF000000
+#define CMD_BYTE2_SHIFT 24
+#define CMD_BYTE3_MASK 0x00FF0000
+#define CMD_BYTE3_SHIFT 16
+
+/* NFC_FLASH_CM2 Field */
+#define CMD2_MASK 0xFFFFFF07
+#define CMD2_SHIFT 0
+#define CMD_BYTE1_MASK 0xFF000000
+#define CMD_BYTE1_SHIFT 24
+#define CMD_CODE_MASK 0x00FFFF00
+#define CMD_CODE_SHIFT 8
+#define BUFNO_MASK 0x00000006
+#define BUFNO_SHIFT 1
+#define BUSY_MASK 0x00000001
+#define BUSY_SHIFT 0
+#define START_MASK 0x00000001
+#define START_SHIFT 0
+
+/* NFC_COL_ADDR Field */
+#define COL_ADDR_MASK 0x0000FFFF
+#define COL_ADDR_SHIFT 0
+#define COL_ADDR_COL_ADDR2_MASK 0x0000FF00
+#define COL_ADDR_COL_ADDR2_SHIFT 8
+#define COL_ADDR_COL_ADDR1_MASK 0x000000FF
+#define COL_ADDR_COL_ADDR1_SHIFT 0
+
+/* NFC_ROW_ADDR Field */
+#define ROW_ADDR_MASK 0x00FFFFFF
+#define ROW_ADDR_SHIFT 0
+#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
+#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
+#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
+#define ROW_ADDR_CHIP_SEL_SHIFT 24
+#define ROW_ADDR_ROW_ADDR3_MASK 0x00FF0000
+#define ROW_ADDR_ROW_ADDR3_SHIFT 16
+#define ROW_ADDR_ROW_ADDR2_MASK 0x0000FF00
+#define ROW_ADDR_ROW_ADDR2_SHIFT 8
+#define ROW_ADDR_ROW_ADDR1_MASK 0x000000FF
+#define ROW_ADDR_ROW_ADDR1_SHIFT 0
+
+/* NFC_FLASH_COMMAND_REPEAT Field */
+#define COMMAND_REPEAT_MASK 0x0000FFFF
+#define COMMAND_REPEAT_SHIFT 0
+#define COMMAND_REPEAT_REPEAT_COUNT_MASK 0x0000FFFF
+#define COMMAND_REPEAT_REPEAT_COUNT_SHIFT 0
+
+/* NFC_ROW_ADDR_INC Field */
+#define ROW_ADDR_INC_MASK 0x00FFFFFF
+#define ROW_ADDR_INC_SHIFT 0
+#define ROW_ADDR_INC_ROW_ADDR3_INC_MASK 0x00FF0000
+#define ROW_ADDR_INC_ROW_ADDR3_INC_SHIFT 16
+#define ROW_ADDR_INC_ROW_ADDR2_INC_MASK 0x0000FF00
+#define ROW_ADDR_INC_ROW_ADDR2_INC_SHIFT 8
+#define ROW_ADDR_INC_ROW_ADDR1_INC_MASK 0x000000FF
+#define ROW_ADDR_INC_ROW_ADDR1_INC_SHIFT 0
+
+/* NFC_FLASH_STATUS1 Field */
+#define STATUS1_MASK 0xFFFFFFFF
+#define STATUS1_SHIFT 0
+#define STATUS1_ID_BYTE1_MASK 0xFF000000
+#define STATUS1_ID_BYTE1_SHIFT 24
+#define STATUS1_ID_BYTE2_MASK 0x00FF0000
+#define STATUS1_ID_BYTE2_SHIFT 16
+#define STATUS1_ID_BYTE3_MASK 0x0000FF00
+#define STATUS1_ID_BYTE3_SHIFT 8
+#define STATUS1_ID_BYTE4_MASK 0x000000FF
+#define STATUS1_ID_BYTE4_SHIFT 0
+
+/* NFC_FLASH_STATUS2 Field */
+#define STATUS2_MASK 0xFF0000FF
+#define STATUS2_SHIFT 0
+#define STATUS2_ID_BYTE5_MASK 0xFF000000
+#define STATUS2_ID_BYTE5_SHIFT 24
+#define STATUS_BYTE1_MASK 0x000000FF
+#define STATUS2_STATUS_BYTE1_SHIFT 0
+
+/* NFC_DMA1_ADDR Field */
+#define DMA1_ADDR_MASK 0xFFFFFFFF
+#define DMA1_ADDR_SHIFT 0
+#define DMA1_ADDR_DMA1_ADDR_MASK 0xFFFFFFFF
+#define DMA1_ADDR_DMA1_ADDR_SHIFT 0
+
+/* DMA2_ADDR Field */
+#define DMA2_ADDR_MASK 0xFFFFFFFF
+#define DMA2_ADDR_SHIFT 0
+#define DMA2_ADDR_DMA2_ADDR_MASK 0xFFFFFFFF
+#define DMA2_ADDR_DMA2_ADDR_SHIFT 0
+
+/* DMA_CONFIG Field */
+#define DMA_CONFIG_MASK 0xFFFFFFFF
+#define DMA_CONFIG_SHIFT 0
+#define DMA_CONFIG_DMA1_CNT_MASK 0xFFF00000
+#define DMA_CONFIG_DMA1_CNT_SHIFT 20
+#define DMA_CONFIG_DMA2_CNT_MASK 0x000FE000
+#define DMA_CONFIG_DMA2_CNT_SHIFT 13
+#define DMA_CONFIG_DMA2_OFFSET_MASK 0x00001FC0
+#define DMA_CONFIG_DMA2_OFFSET_SHIFT 2
+#define DMA_CONFIG_DMA1_ACT_MASK 0x00000002
+#define DMA_CONFIG_DMA1_ACT_SHIFT 1
+#define DMA_CONFIG_DMA2_ACT_MASK 0x00000001
+#define DMA_CONFIG_DMA2_ACT_SHIFT 0
+
+/* NFC_CACHE_SWAP Field */
+#define CACHE_SWAP_MASK 0x0FFE0FFE
+#define CACHE_SWAP_SHIFT 1
+#define CACHE_SWAP_CACHE_SWAP_ADDR2_MASK 0x0FFE0000
+#define CACHE_SWAP_CACHE_SWAP_ADDR2_SHIFT 17
+#define CACHE_SWAP_CACHE_SWAP_ADDR1_MASK 0x00000FFE
+#define CACHE_SWAP_CACHE_SWAP_ADDR1_SHIFT 1
+
+/* NFC_SECTOR_SIZE Field */
+#define SECTOR_SIZE_MASK 0x00001FFF
+#define SECTOR_SIZE_SHIFT 0
+#define SECTOR_SIZE_SECTOR_SIZE_MASK 0x00001FFF
+#define SECTOR_SIZE_SECTOR_SIZE_SHIFT 0
+
+/* NFC_FLASH_CONFIG Field */
+#define CONFIG_MASK 0xFFFFFFFF
+#define CONFIG_SHIFT 0
+#define CONFIG_STOP_ON_WERR_MASK 0x80000000
+#define CONFIG_STOP_ON_WERR_SHIFT 31
+#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
+#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
+#define CONFIG_ECC_SRAM_REQ_MASK 0x00200000
+#define CONFIG_ECC_SRAM_REQ_SHIFT 21
+#define CONFIG_DMA_REQ_MASK 0x00100000
+#define CONFIG_DMA_REQ_SHIFT 20
+#define CONFIG_ECC_MODE_MASK 0x000E0000
+#define CONFIG_ECC_MODE_SHIFT 17
+#define CONFIG_FAST_FLASH_MASK 0x00010000
+#define CONFIG_FAST_FLASH_SHIFT 16
+#define CONFIG_ID_COUNT_MASK 0x0000E000
+#define CONFIG_ID_COUNT_SHIFT 13
+#define CONFIG_CMD_TIMEOUT_MASK 0x00001F00
+#define CONFIG_CMD_TIMEOUT_SHIFT 8
+#define CONFIG_16BIT_MASK 0x00000080
+#define CONFIG_16BIT_SHIFT 7
+#define CONFIG_BOOT_MODE_MASK 0x00000040
+#define CONFIG_BOOT_MODE_SHIFT 6
+#define CONFIG_ADDR_AUTO_INCR_MASK 0x00000020
+#define CONFIG_ADDR_AUTO_INCR_SHIFT 5
+#define CONFIG_BUFNO_AUTO_INCR_MASK 0x00000010
+#define CONFIG_BUFNO_AUTO_INCR_SHIFT 4
+#define CONFIG_PAGE_CNT_MASK 0x0000000F
+#define CONFIG_PAGE_CNT_SHIFT 0
+
+/* NFC_IRQ_STATUS Field */
+#define MASK 0xEFFC003F
+#define SHIFT 0
+#define WERR_IRQ_MASK 0x80000000
+#define WERR_IRQ_SHIFT 31
+#define CMD_DONE_IRQ_MASK 0x40000000
+#define CMD_DONE_IRQ_SHIFT 30
+#define IDLE_IRQ_MASK 0x20000000
+#define IDLE_IRQ_SHIFT 29
+#define WERR_STATUS_MASK 0x08000000
+#define WERR_STATUS_SHIFT 27
+#define FLASH_CMD_BUSY_MASK 0x04000000
+#define FLASH_CMD_BUSY_SHIFT 26
+#define RESIDUE_BUSY_MASK 0x02000000
+#define RESIDUE_BUSY_SHIFT 25
+#define ECC_BUSY_MASK 0x01000000
+#define ECC_BUSY_SHIFT 24
+#define DMA_BUSY_MASK 0x00800000
+#define DMA_BUSY_SHIFT 23
+#define WERR_EN_MASK 0x00400000
+#define WERR_EN_SHIFT 22
+#define CMD_DONE_EN_MASK 0x00200000
+#define CMD_DONE_EN_SHIFT 21
+#define IDLE_EN_MASK 0x00100000
+#define IDLE_EN_SHIFT 20
+#define WERR_CLEAR_MASK 0x00080000
+#define WERR_CLEAR_SHIFT 19
+#define CMD_DONE_CLEAR_MASK 0x00040000
+#define CMD_DONE_CLEAR_SHIFT 18
+#define IDLE_CLEAR_MASK 0x00020000
+#define IDLE_CLEAR_SHIFT 17
+#define RESIDUE_BUFF_NO_MASK 0x00000030
+#define RESIDUE_BUFF_NO_SHIFT 4
+#define ECC_BUFF_NO_MASK 0x000000C0
+#define ECC_BUFF_NO_SHIFT 2
+#define DMA_BUFF_NO_MASK 0x00000003
+
+#endif /* MPC5125_NFC_H */
+
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 00cf1b0..6755191 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -66,6 +66,8 @@ struct nand_flash_dev nand_flash_ids[] = {
{"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
+ {"NAND 4GiB 3,3V 8-bit", 0x68, 4096, 4096, 0x100000, 0},
+
/*
* These are the new chips with large page size. The pagesize and the
* erasesize is determined from the extended id bytes
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