* mscan status on DENX Linux 2.6 Kernel Tree
From: moises.dominguez @ 2011-04-07 9:10 UTC (permalink / raw)
To: linuxppc-dev
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Hi,
Up to now I've been working ltib over and ads5121 based board.
So as not to work with frozen images I would like to change to u-boot and
kernel from denx. I did the following:
- Download and compile u-boot: OK.
- Download and kernel (mpc512x_defconfig): compilation fails if I enable
"Freescale MPC5xxx onboard CAN controller" with this message:
.
LD kernel/built-in.o
CC drivers/net/can/mscan/mscan.o
CC drivers/net/can/mscan/mpc5xxx_can.o
drivers/net/can/mscan/mpc5xxx_can.c: In function 'mpc5xxx_can_probe':
drivers/net/can/mscan/mpc5xxx_can.c:263: error: 'of_dev' undeclared (first
use in this function)
.
I have not much experience with this stuff but I've notice that there are
recent patches on mpc5xxx.c file, last from 2011-02-28 so I suppose this
should work.
Am I missing something? I also wonder if ads5121-Rev4 is fully supported in
Linux Denx.
Thanks,
Moises.
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^ permalink raw reply
* [PATCH][v2] powerpc/85xx: P1020 DTS : re-organize dts files
From: Prabhakar Kushwaha @ 2011-04-07 9:10 UTC (permalink / raw)
To: linuxppc-dev, devicetree-discuss
Cc: meet2prabhu, kumar.gala, Prabhakar Kushwaha
Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
files for P1020 based systems to use dtsi file
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Kumar Gala <kumar.gala@freescale.com>
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master)
Please see mpc5200b.dtsi for reference.
Tested on P1020RDB
Changes for v2: Incorporated Grant Likely's comment
-updated model name
arch/powerpc/boot/dts/p1020rdb.dts | 316 +------------------------------
arch/powerpc/boot/dts/p1020si.dtsi | 377 ++++++++++++++++++++++++++++++++++++
2 files changed, 380 insertions(+), 313 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index e0668f8..7ed4793 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,12 +9,11 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "p1020si.dtsi"
+
/ {
- model = "fsl,P1020";
+ model = "fsl,P1020RDB";
compatible = "fsl,P1020RDB";
- #address-cells = <2>;
- #size-cells = <2>;
aliases {
serial0 = &serial0;
@@ -26,34 +25,11 @@
pci1 = &pci1;
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,P1020@0 {
- device_type = "cpu";
- reg = <0x0>;
- next-level-cache = <&L2>;
- };
-
- PowerPC,P1020@1 {
- device_type = "cpu";
- reg = <0x1>;
- next-level-cache = <&L2>;
- };
- };
-
memory {
device_type = "memory";
};
localbus@ffe05000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
- reg = <0 0xffe05000 0 0x1000>;
- interrupts = <19 2>;
- interrupt-parent = <&mpic>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,88 +141,14 @@
};
soc@ffe00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "fsl,p1020-immr", "simple-bus";
- ranges = <0x0 0x0 0xffe00000 0x100000>;
- bus-frequency = <0>; // Filled out by uboot.
-
- ecm-law@0 {
- compatible = "fsl,ecm-law";
- reg = <0x0 0x1000>;
- fsl,num-laws = <12>;
- };
-
- ecm@1000 {
- compatible = "fsl,p1020-ecm", "fsl,ecm";
- reg = <0x1000 0x1000>;
- interrupts = <16 2>;
- interrupt-parent = <&mpic>;
- };
-
- memory-controller@2000 {
- compatible = "fsl,p1020-memory-controller";
- reg = <0x2000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
-
i2c@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
-
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
-
spi@7000 {
- cell-index = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,espi";
- reg = <0x7000 0x1000>;
- interrupts = <59 0x2>;
- interrupt-parent = <&mpic>;
- mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
@@ -294,66 +196,7 @@
};
};
- gpio: gpio-controller@f000 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8572-gpio";
- reg = <0xf000 0x100>;
- interrupts = <47 0x2>;
- interrupt-parent = <&mpic>;
- gpio-controller;
- };
-
- L2: l2-cache-controller@20000 {
- compatible = "fsl,p1020-l2-cache-controller";
- reg = <0x20000 0x1000>;
- cache-line-size = <32>; // 32 bytes
- cache-size = <0x40000>; // L2,256K
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
-
- dma@21300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,eloplus-dma";
- reg = <0x21300 0x4>;
- ranges = <0x0 0x21100 0x200>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x0 0x80>;
- cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <20 2>;
- };
- dma-channel@80 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x80 0x80>;
- cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <21 2>;
- };
- dma-channel@100 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x100 0x80>;
- cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <22 2>;
- };
- dma-channel@180 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x180 0x80>;
- cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <23 2>;
- };
- };
-
mdio@24000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-mdio";
- reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
@@ -369,10 +212,6 @@
};
mdio@25000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-tbi";
- reg = <0x25000 0x1000 0xb1030 0x4>;
tbi0: tbi-phy@11 {
reg = <0x11>;
@@ -381,97 +220,25 @@
};
enet0: ethernet@b0000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb0000 0x1000>;
- interrupts = <29 2 30 2 34 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb4000 0x1000>;
- interrupts = <17 2 18 2 24 2>;
- };
};
enet1: ethernet@b1000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb1000 0x1000>;
- interrupts = <35 2 36 2 40 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb5000 0x1000>;
- interrupts = <51 2 52 2 67 2>;
- };
};
enet2: ethernet@b2000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb2000 0x1000>;
- interrupts = <31 2 32 2 33 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb6000 0x1000>;
- interrupts = <25 2 26 2 27 2>;
- };
};
usb@22000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl-usb2-dr";
- reg = <0x22000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <28 0x2>;
phy_type = "ulpi";
};
@@ -481,82 +248,15 @@
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl-usb2-dr";
- reg = <0x23000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <46 0x2>;
phy_type = "ulpi";
};
*/
- sdhci@2e000 {
- compatible = "fsl,p1020-esdhc", "fsl,esdhc";
- reg = <0x2e000 0x1000>;
- interrupts = <72 0x2>;
- interrupt-parent = <&mpic>;
- /* Filled in by U-Boot */
- clock-frequency = <0>;
- };
-
- crypto@30000 {
- compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
- "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
- reg = <0x30000 0x10000>;
- interrupts = <45 2 58 2>;
- interrupt-parent = <&mpic>;
- fsl,num-channels = <4>;
- fsl,channel-fifo-len = <24>;
- fsl,exec-units-mask = <0xbfe>;
- fsl,descriptor-types-mask = <0x3ab0ebf>;
- };
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x40000 0x40000>;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- };
-
- msi@41600 {
- compatible = "fsl,p1020-msi", "fsl,mpic-msi";
- reg = <0x41600 0x80>;
- msi-available-ranges = <0 0x100>;
- interrupts = <
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0>;
- interrupt-parent = <&mpic>;
- };
-
- global-utilities@e0000 { //global utilities block
- compatible = "fsl,p1020-guts";
- reg = <0xe0000 0x1000>;
- fsl,has-rstcr;
- };
};
pci0: pcie@ffe09000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0 0xffe09000 0 0x1000>;
- bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
@@ -573,18 +273,8 @@
};
pci1: pcie@ffe0a000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0 0xffe0a000 0 0x1000>;
- bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
new file mode 100644
index 0000000..f6f1100
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020si.dtsi
@@ -0,0 +1,377 @@
+/*
+ * P1020si Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ compatible = "fsl,P1020";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P1020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P1020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ localbus@ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p1020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <16 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p1020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p1020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2,256K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ mdio@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x24000 0x1000 0xb0030 0x4>;
+
+ };
+
+ mdio@25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x25000 0x1000 0xb1030 0x4>;
+
+ };
+
+ enet0: ethernet@b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb0000 0x1000>;
+ interrupts = <29 2 30 2 34 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb4000 0x1000>;
+ interrupts = <17 2 18 2 24 2>;
+ };
+ };
+
+ enet1: ethernet@b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb1000 0x1000>;
+ interrupts = <35 2 36 2 40 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb5000 0x1000>;
+ interrupts = <51 2 52 2 67 2>;
+ };
+ };
+
+ enet2: ethernet@b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb2000 0x1000>;
+ interrupts = <31 2 32 2 33 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb6000 0x1000>;
+ interrupts = <25 2 26 2 27 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ };
+
+ /* USB2 is shared with localbus, so it must be disabled
+ by default. We can't put 'status = "disabled";' here
+ since U-Boot doesn't clear the status property when
+ it enables USB2. OTOH, U-Boot does create a new node
+ when there isn't any. So, just comment it out.
+ usb@23000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <46 0x2>;
+ phy_type = "ulpi";
+ };
+ */
+
+ sdhci@2e000 {
+ compatible = "fsl,p1020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi@41600 {
+ compatible = "fsl,p1020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,p1020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ pci1: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+};
--
1.7.3
^ permalink raw reply related
* Re: known working sata_sil24.c setup on powerpc platforms?
From: Martyn Welch @ 2011-04-07 8:27 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <BANLkTimXgi26RHHxyBLoN8YqaDy_PL-hGQ@mail.gmail.com>
On 06/04/11 18:00, Leon Woestenberg wrote:
> Hello,
>
> after investigating problems with sata_sil24.c on a freescale p2020
> soc, I wonder if this driver works on powerpc at all?
>
> Does anyone know of a working setup of sata_sil24 on a big endian
> powerpc system?
>
Yes, I think we even use it on a p2020 board, though I think our current
kernel on that product is 2.6.34.
Martyn
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748 | Barbirolli Square, Manchester,
E martyn.welch@ge.com | M2 3AB VAT:GB 927559189
^ permalink raw reply
* Re: [PATCH] powerpc: Free up some CPU feature bits by moving out MMU-related features
From: Matt Evans @ 2011-04-07 8:17 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <D5DE7F16-B3E0-4F5C-9A2C-0052C6B6D2D1@kernel.crashing.org>
On 07/04/11 17:06, Kumar Gala wrote:
>
> On Apr 7, 2011, at 12:48 AM, Matt Evans wrote:
>
>> diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
>> index be3cdf9..7b0fe7c 100644
>> --- a/arch/powerpc/include/asm/cputable.h
>> +++ b/arch/powerpc/include/asm/cputable.h
>> @@ -178,22 +178,15 @@ extern const char *powerpc_base_platform;
>> #define LONG_ASM_CONST(x) 0
>> #endif
>>
>> -#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
>> -#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
>> -#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
>> #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
>> #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
>> #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
>> #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
>> -#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
>> -#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
>> #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
>> #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
>> #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
>> #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
>> #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
>> -#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
>> -#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
>> #define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
>> #define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
>> #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
>> @@ -205,9 +198,10 @@ extern const char *powerpc_base_platform;
>
> Seems like SAO should move into MMU features
I would argue it's the core/nest that orders/disorders things rather than the MMU.
Cheers,
Matt
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: P1020 DTS : re-organize dts files
From: Grant Likely @ 2011-04-07 8:09 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: meet2prabhu, devicetree-discuss, linuxppc-dev, B11780
In-Reply-To: <1302157534-16746-1-git-send-email-prabhakar@freescale.com>
On Thu, Apr 07, 2011 at 11:55:34AM +0530, Prabhakar Kushwaha wrote:
> Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
> files for P1020 based systems to use dtsi file.
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Acked-by: Kumar Gala <kumar.gala@freescale.com>
> ---
> Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master)
>
> Please see mpc5200b.dtsi for reference.
>
> Tested on P1020RDB
Minor comments below, but I think this looks good.
g.
>
> arch/powerpc/boot/dts/p1020rdb.dts | 315 +-----------------------------
> arch/powerpc/boot/dts/p1020si.dtsi | 378 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 380 insertions(+), 313 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
>
> diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
> index e0668f8..8ae5ddf 100644
> --- a/arch/powerpc/boot/dts/p1020rdb.dts
> +++ b/arch/powerpc/boot/dts/p1020rdb.dts
> @@ -9,12 +9,10 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "p1020si.dtsi"
> +
> / {
> - model = "fsl,P1020";
Model here should actually reflect the name of the board, not the soc.
I don't think you want to remove it from here, but it definitely looks
like it needs to be fixed.
> compatible = "fsl,P1020RDB";
> - #address-cells = <2>;
> - #size-cells = <2>;
>
> aliases {
> serial0 = &serial0;
> @@ -26,34 +24,11 @@
> pci1 = &pci1;
> };
>
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,P1020@0 {
> - device_type = "cpu";
> - reg = <0x0>;
> - next-level-cache = <&L2>;
> - };
> -
> - PowerPC,P1020@1 {
> - device_type = "cpu";
> - reg = <0x1>;
> - next-level-cache = <&L2>;
> - };
> - };
> -
> memory {
> device_type = "memory";
> };
>
> localbus@ffe05000 {
> - #address-cells = <2>;
> - #size-cells = <1>;
> - compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
> - reg = <0 0xffe05000 0 0x1000>;
> - interrupts = <19 2>;
> - interrupt-parent = <&mpic>;
>
> /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
> ranges = <0x0 0x0 0x0 0xef000000 0x01000000
> @@ -165,88 +140,14 @@
> };
>
> soc@ffe00000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "soc";
> - compatible = "fsl,p1020-immr", "simple-bus";
> - ranges = <0x0 0x0 0xffe00000 0x100000>;
> - bus-frequency = <0>; // Filled out by uboot.
> -
> - ecm-law@0 {
> - compatible = "fsl,ecm-law";
> - reg = <0x0 0x1000>;
> - fsl,num-laws = <12>;
> - };
> -
> - ecm@1000 {
> - compatible = "fsl,p1020-ecm", "fsl,ecm";
> - reg = <0x1000 0x1000>;
> - interrupts = <16 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - memory-controller@2000 {
> - compatible = "fsl,p1020-memory-controller";
> - reg = <0x2000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> - };
> -
> i2c@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - cell-index = <0>;
> - compatible = "fsl-i2c";
> - reg = <0x3000 0x100>;
> - interrupts = <43 2>;
> - interrupt-parent = <&mpic>;
> - dfsrr;
> rtc@68 {
> compatible = "dallas,ds1339";
> reg = <0x68>;
> };
> };
>
> - i2c@3100 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - cell-index = <1>;
> - compatible = "fsl-i2c";
> - reg = <0x3100 0x100>;
> - interrupts = <43 2>;
> - interrupt-parent = <&mpic>;
> - dfsrr;
> - };
> -
> - serial0: serial@4500 {
> - cell-index = <0>;
> - device_type = "serial";
> - compatible = "ns16550";
> - reg = <0x4500 0x100>;
> - clock-frequency = <0>;
> - interrupts = <42 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - serial1: serial@4600 {
> - cell-index = <1>;
> - device_type = "serial";
> - compatible = "ns16550";
> - reg = <0x4600 0x100>;
> - clock-frequency = <0>;
> - interrupts = <42 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> spi@7000 {
> - cell-index = <0>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,espi";
> - reg = <0x7000 0x1000>;
> - interrupts = <59 0x2>;
> - interrupt-parent = <&mpic>;
> - mode = "cpu";
>
> fsl_m25p80@0 {
> #address-cells = <1>;
> @@ -294,66 +195,7 @@
> };
> };
>
> - gpio: gpio-controller@f000 {
> - #gpio-cells = <2>;
> - compatible = "fsl,mpc8572-gpio";
> - reg = <0xf000 0x100>;
> - interrupts = <47 0x2>;
> - interrupt-parent = <&mpic>;
> - gpio-controller;
> - };
> -
> - L2: l2-cache-controller@20000 {
> - compatible = "fsl,p1020-l2-cache-controller";
> - reg = <0x20000 0x1000>;
> - cache-line-size = <32>; // 32 bytes
> - cache-size = <0x40000>; // L2,256K
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> - };
> -
> - dma@21300 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,eloplus-dma";
> - reg = <0x21300 0x4>;
> - ranges = <0x0 0x21100 0x200>;
> - cell-index = <0>;
> - dma-channel@0 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x0 0x80>;
> - cell-index = <0>;
> - interrupt-parent = <&mpic>;
> - interrupts = <20 2>;
> - };
> - dma-channel@80 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x80 0x80>;
> - cell-index = <1>;
> - interrupt-parent = <&mpic>;
> - interrupts = <21 2>;
> - };
> - dma-channel@100 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x100 0x80>;
> - cell-index = <2>;
> - interrupt-parent = <&mpic>;
> - interrupts = <22 2>;
> - };
> - dma-channel@180 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x180 0x80>;
> - cell-index = <3>;
> - interrupt-parent = <&mpic>;
> - interrupts = <23 2>;
> - };
> - };
> -
> mdio@24000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,etsec2-mdio";
> - reg = <0x24000 0x1000 0xb0030 0x4>;
>
> phy0: ethernet-phy@0 {
> interrupt-parent = <&mpic>;
> @@ -369,10 +211,6 @@
> };
>
> mdio@25000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,etsec2-tbi";
> - reg = <0x25000 0x1000 0xb1030 0x4>;
>
> tbi0: tbi-phy@11 {
> reg = <0x11>;
> @@ -381,97 +219,25 @@
> };
>
> enet0: ethernet@b0000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> fixed-link = <1 1 1000 0 0>;
> phy-connection-type = "rgmii-id";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb0000 0x1000>;
> - interrupts = <29 2 30 2 34 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb4000 0x1000>;
> - interrupts = <17 2 18 2 24 2>;
> - };
> };
>
> enet1: ethernet@b1000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> phy-handle = <&phy0>;
> tbi-handle = <&tbi0>;
> phy-connection-type = "sgmii";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb1000 0x1000>;
> - interrupts = <35 2 36 2 40 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb5000 0x1000>;
> - interrupts = <51 2 52 2 67 2>;
> - };
> };
>
> enet2: ethernet@b2000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> phy-handle = <&phy1>;
> phy-connection-type = "rgmii-id";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb2000 0x1000>;
> - interrupts = <31 2 32 2 33 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb6000 0x1000>;
> - interrupts = <25 2 26 2 27 2>;
> - };
> };
>
> usb@22000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl-usb2-dr";
> - reg = <0x22000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <28 0x2>;
> phy_type = "ulpi";
> };
>
> @@ -481,82 +247,15 @@
> it enables USB2. OTOH, U-Boot does create a new node
> when there isn't any. So, just comment it out.
> usb@23000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl-usb2-dr";
> - reg = <0x23000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <46 0x2>;
> phy_type = "ulpi";
> };
> */
>
> - sdhci@2e000 {
> - compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> - reg = <0x2e000 0x1000>;
> - interrupts = <72 0x2>;
> - interrupt-parent = <&mpic>;
> - /* Filled in by U-Boot */
> - clock-frequency = <0>;
> - };
> -
> - crypto@30000 {
> - compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> - "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> - reg = <0x30000 0x10000>;
> - interrupts = <45 2 58 2>;
> - interrupt-parent = <&mpic>;
> - fsl,num-channels = <4>;
> - fsl,channel-fifo-len = <24>;
> - fsl,exec-units-mask = <0xbfe>;
> - fsl,descriptor-types-mask = <0x3ab0ebf>;
> - };
> -
> - mpic: pic@40000 {
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <2>;
> - reg = <0x40000 0x40000>;
> - compatible = "chrp,open-pic";
> - device_type = "open-pic";
> - };
> -
> - msi@41600 {
> - compatible = "fsl,p1020-msi", "fsl,mpic-msi";
> - reg = <0x41600 0x80>;
> - msi-available-ranges = <0 0x100>;
> - interrupts = <
> - 0xe0 0
> - 0xe1 0
> - 0xe2 0
> - 0xe3 0
> - 0xe4 0
> - 0xe5 0
> - 0xe6 0
> - 0xe7 0>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - global-utilities@e0000 { //global utilities block
> - compatible = "fsl,p1020-guts";
> - reg = <0xe0000 0x1000>;
> - fsl,has-rstcr;
> - };
> };
>
> pci0: pcie@ffe09000 {
> - compatible = "fsl,mpc8548-pcie";
> - device_type = "pci";
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - reg = <0 0xffe09000 0 0x1000>;
> - bus-range = <0 255>;
> ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
> 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
> - clock-frequency = <33333333>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> pcie@0 {
> reg = <0x0 0x0 0x0 0x0 0x0>;
> #size-cells = <2>;
> @@ -573,18 +272,8 @@
> };
>
> pci1: pcie@ffe0a000 {
> - compatible = "fsl,mpc8548-pcie";
> - device_type = "pci";
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - reg = <0 0xffe0a000 0 0x1000>;
> - bus-range = <0 255>;
> ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
> 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
> - clock-frequency = <33333333>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> pcie@0 {
> reg = <0x0 0x0 0x0 0x0 0x0>;
> #size-cells = <2>;
> diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
> new file mode 100644
> index 0000000..7b87d00
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p1020si.dtsi
> @@ -0,0 +1,378 @@
> +/*
> + * P1020si Device Tree Source
> + *
> + * Copyright 2011 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/ {
> + model = "fsl,P1020";
> + compatible = "fsl,P1020";
I think you should drop both of these properties from the include
file. Leave it to the board to actually define them.
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,P1020@0 {
> + device_type = "cpu";
> + reg = <0x0>;
> + next-level-cache = <&L2>;
> + };
> +
> + PowerPC,P1020@1 {
> + device_type = "cpu";
> + reg = <0x1>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + localbus@ffe05000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
> + reg = <0 0xffe05000 0 0x1000>;
> + interrupts = <19 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + soc@ffe00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + compatible = "fsl,p1020-immr", "simple-bus";
> + ranges = <0x0 0x0 0xffe00000 0x100000>;
> + bus-frequency = <0>; // Filled out by uboot.
> +
> + ecm-law@0 {
> + compatible = "fsl,ecm-law";
> + reg = <0x0 0x1000>;
> + fsl,num-laws = <12>;
> + };
> +
> + ecm@1000 {
> + compatible = "fsl,p1020-ecm", "fsl,ecm";
> + reg = <0x1000 0x1000>;
> + interrupts = <16 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + memory-controller@2000 {
> + compatible = "fsl,p1020-memory-controller";
> + reg = <0x2000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + i2c@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <0>;
> + compatible = "fsl-i2c";
> + reg = <0x3000 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + i2c@3100 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <1>;
> + compatible = "fsl-i2c";
> + reg = <0x3100 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + serial0: serial@4500 {
> + cell-index = <0>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4500 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + serial1: serial@4600 {
> + cell-index = <1>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4600 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + spi@7000 {
> + cell-index = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,espi";
> + reg = <0x7000 0x1000>;
> + interrupts = <59 0x2>;
> + interrupt-parent = <&mpic>;
> + mode = "cpu";
> + };
> +
> + gpio: gpio-controller@f000 {
> + #gpio-cells = <2>;
> + compatible = "fsl,mpc8572-gpio";
> + reg = <0xf000 0x100>;
> + interrupts = <47 0x2>;
> + interrupt-parent = <&mpic>;
> + gpio-controller;
> + };
> +
> + L2: l2-cache-controller@20000 {
> + compatible = "fsl,p1020-l2-cache-controller";
> + reg = <0x20000 0x1000>;
> + cache-line-size = <32>; // 32 bytes
> + cache-size = <0x40000>; // L2,256K
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + dma@21300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0x21300 0x4>;
> + ranges = <0x0 0x21100 0x200>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <20 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <21 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <22 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <23 2>;
> + };
> + };
> +
> + mdio@24000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,etsec2-mdio";
> + reg = <0x24000 0x1000 0xb0030 0x4>;
> +
> + };
> +
> + mdio@25000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,etsec2-tbi";
> + reg = <0x25000 0x1000 0xb1030 0x4>;
> +
> + };
> +
> + enet0: ethernet@b0000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb0000 0x1000>;
> + interrupts = <29 2 30 2 34 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb4000 0x1000>;
> + interrupts = <17 2 18 2 24 2>;
> + };
> + };
> +
> + enet1: ethernet@b1000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb1000 0x1000>;
> + interrupts = <35 2 36 2 40 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb5000 0x1000>;
> + interrupts = <51 2 52 2 67 2>;
> + };
> + };
> +
> + enet2: ethernet@b2000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb2000 0x1000>;
> + interrupts = <31 2 32 2 33 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb6000 0x1000>;
> + interrupts = <25 2 26 2 27 2>;
> + };
> + };
> +
> + usb@22000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x22000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <28 0x2>;
> + };
> +
> + /* USB2 is shared with localbus, so it must be disabled
> + by default. We can't put 'status = "disabled";' here
> + since U-Boot doesn't clear the status property when
> + it enables USB2. OTOH, U-Boot does create a new node
> + when there isn't any. So, just comment it out.
> + usb@23000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x23000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <46 0x2>;
> + phy_type = "ulpi";
> + };
> + */
> +
> + sdhci@2e000 {
> + compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> + reg = <0x2e000 0x1000>;
> + interrupts = <72 0x2>;
> + interrupt-parent = <&mpic>;
> + /* Filled in by U-Boot */
> + clock-frequency = <0>;
> + };
> +
> + crypto@30000 {
> + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> + reg = <0x30000 0x10000>;
> + interrupts = <45 2 58 2>;
> + interrupt-parent = <&mpic>;
> + fsl,num-channels = <4>;
> + fsl,channel-fifo-len = <24>;
> + fsl,exec-units-mask = <0xbfe>;
> + fsl,descriptor-types-mask = <0x3ab0ebf>;
> + };
> +
> + mpic: pic@40000 {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + reg = <0x40000 0x40000>;
> + compatible = "chrp,open-pic";
> + device_type = "open-pic";
> + };
> +
> + msi@41600 {
> + compatible = "fsl,p1020-msi", "fsl,mpic-msi";
> + reg = <0x41600 0x80>;
> + msi-available-ranges = <0 0x100>;
> + interrupts = <
> + 0xe0 0
> + 0xe1 0
> + 0xe2 0
> + 0xe3 0
> + 0xe4 0
> + 0xe5 0
> + 0xe6 0
> + 0xe7 0>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + global-utilities@e0000 { //global utilities block
> + compatible = "fsl,p1020-guts";
> + reg = <0xe0000 0x1000>;
> + fsl,has-rstcr;
> + };
> + };
> +
> + pci0: pcie@ffe09000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe09000 0 0x1000>;
> + bus-range = <0 255>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + pci1: pcie@ffe0a000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe0a000 0 0x1000>;
> + bus-range = <0 255>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +};
> --
> 1.7.3
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply
* Re: halt/reset on assert?
From: Benjamin Herrenschmidt @ 2011-04-07 7:55 UTC (permalink / raw)
To: Evan Lavelle; +Cc: linuxppc-dev, Andreas Schwab
In-Reply-To: <4D9C6413.8030103@cyconix.com>
On Wed, 2011-04-06 at 14:01 +0100, Evan Lavelle wrote:
> #define MY_ASSERT(expr) if(!(expr)) BUG()
Make it
#define MY_ASSERT(expr) do { if .... } while(0)
To ensure it has proper single statement semantics in C.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Free up some CPU feature bits by moving out MMU-related features
From: Kumar Gala @ 2011-04-07 7:06 UTC (permalink / raw)
To: Matt Evans; +Cc: linuxppc-dev
In-Reply-To: <4D9D5042.6080500@ozlabs.org>
On Apr 7, 2011, at 12:48 AM, Matt Evans wrote:
> diff --git a/arch/powerpc/include/asm/cputable.h =
b/arch/powerpc/include/asm/cputable.h
> index be3cdf9..7b0fe7c 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -178,22 +178,15 @@ extern const char *powerpc_base_platform;
> #define LONG_ASM_CONST(x) 0
> #endif
>=20
> -#define CPU_FTR_SLB =
LONG_ASM_CONST(0x0000000100000000)
> -#define CPU_FTR_16M_PAGE =
LONG_ASM_CONST(0x0000000200000000)
> -#define CPU_FTR_TLBIEL =
LONG_ASM_CONST(0x0000000400000000)
> #define CPU_FTR_IABR =
LONG_ASM_CONST(0x0000002000000000)
> #define CPU_FTR_MMCRA =
LONG_ASM_CONST(0x0000004000000000)
> #define CPU_FTR_CTRL =
LONG_ASM_CONST(0x0000008000000000)
> #define CPU_FTR_SMT =
LONG_ASM_CONST(0x0000010000000000)
> -#define CPU_FTR_LOCKLESS_TLBIE =
LONG_ASM_CONST(0x0000040000000000)
> -#define CPU_FTR_CI_LARGE_PAGE =
LONG_ASM_CONST(0x0000100000000000)
> #define CPU_FTR_PAUSE_ZERO =
LONG_ASM_CONST(0x0000200000000000)
> #define CPU_FTR_PURR =
LONG_ASM_CONST(0x0000400000000000)
> #define CPU_FTR_CELL_TB_BUG =
LONG_ASM_CONST(0x0000800000000000)
> #define CPU_FTR_SPURR =
LONG_ASM_CONST(0x0001000000000000)
> #define CPU_FTR_DSCR =
LONG_ASM_CONST(0x0002000000000000)
> -#define CPU_FTR_1T_SEGMENT =
LONG_ASM_CONST(0x0004000000000000)
> -#define CPU_FTR_NO_SLBIE_B =
LONG_ASM_CONST(0x0008000000000000)
> #define CPU_FTR_VSX =
LONG_ASM_CONST(0x0010000000000000)
> #define CPU_FTR_SAO =
LONG_ASM_CONST(0x0020000000000000)
> #define CPU_FTR_CP_USE_DCBTZ =
LONG_ASM_CONST(0x0040000000000000)
> @@ -205,9 +198,10 @@ extern const char *powerpc_base_platform;
Seems like SAO should move into MMU features
- k=
^ permalink raw reply
* [PATCH] powerpc/85xx: P1020 DTS : re-organize dts files
From: Prabhakar Kushwaha @ 2011-04-07 6:25 UTC (permalink / raw)
To: linuxppc-dev, devicetree-discuss; +Cc: meet2prabhu, B11780, Prabhakar Kushwaha
Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
files for P1020 based systems to use dtsi file.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Kumar Gala <kumar.gala@freescale.com>
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master)
Please see mpc5200b.dtsi for reference.
Tested on P1020RDB
arch/powerpc/boot/dts/p1020rdb.dts | 315 +-----------------------------
arch/powerpc/boot/dts/p1020si.dtsi | 378 ++++++++++++++++++++++++++++++++++++
2 files changed, 380 insertions(+), 313 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index e0668f8..8ae5ddf 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,12 +9,10 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "p1020si.dtsi"
+
/ {
- model = "fsl,P1020";
compatible = "fsl,P1020RDB";
- #address-cells = <2>;
- #size-cells = <2>;
aliases {
serial0 = &serial0;
@@ -26,34 +24,11 @@
pci1 = &pci1;
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,P1020@0 {
- device_type = "cpu";
- reg = <0x0>;
- next-level-cache = <&L2>;
- };
-
- PowerPC,P1020@1 {
- device_type = "cpu";
- reg = <0x1>;
- next-level-cache = <&L2>;
- };
- };
-
memory {
device_type = "memory";
};
localbus@ffe05000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
- reg = <0 0xffe05000 0 0x1000>;
- interrupts = <19 2>;
- interrupt-parent = <&mpic>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,88 +140,14 @@
};
soc@ffe00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "fsl,p1020-immr", "simple-bus";
- ranges = <0x0 0x0 0xffe00000 0x100000>;
- bus-frequency = <0>; // Filled out by uboot.
-
- ecm-law@0 {
- compatible = "fsl,ecm-law";
- reg = <0x0 0x1000>;
- fsl,num-laws = <12>;
- };
-
- ecm@1000 {
- compatible = "fsl,p1020-ecm", "fsl,ecm";
- reg = <0x1000 0x1000>;
- interrupts = <16 2>;
- interrupt-parent = <&mpic>;
- };
-
- memory-controller@2000 {
- compatible = "fsl,p1020-memory-controller";
- reg = <0x2000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
-
i2c@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
-
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
-
spi@7000 {
- cell-index = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,espi";
- reg = <0x7000 0x1000>;
- interrupts = <59 0x2>;
- interrupt-parent = <&mpic>;
- mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
@@ -294,66 +195,7 @@
};
};
- gpio: gpio-controller@f000 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8572-gpio";
- reg = <0xf000 0x100>;
- interrupts = <47 0x2>;
- interrupt-parent = <&mpic>;
- gpio-controller;
- };
-
- L2: l2-cache-controller@20000 {
- compatible = "fsl,p1020-l2-cache-controller";
- reg = <0x20000 0x1000>;
- cache-line-size = <32>; // 32 bytes
- cache-size = <0x40000>; // L2,256K
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
-
- dma@21300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,eloplus-dma";
- reg = <0x21300 0x4>;
- ranges = <0x0 0x21100 0x200>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x0 0x80>;
- cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <20 2>;
- };
- dma-channel@80 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x80 0x80>;
- cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <21 2>;
- };
- dma-channel@100 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x100 0x80>;
- cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <22 2>;
- };
- dma-channel@180 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x180 0x80>;
- cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <23 2>;
- };
- };
-
mdio@24000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-mdio";
- reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
@@ -369,10 +211,6 @@
};
mdio@25000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-tbi";
- reg = <0x25000 0x1000 0xb1030 0x4>;
tbi0: tbi-phy@11 {
reg = <0x11>;
@@ -381,97 +219,25 @@
};
enet0: ethernet@b0000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb0000 0x1000>;
- interrupts = <29 2 30 2 34 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb4000 0x1000>;
- interrupts = <17 2 18 2 24 2>;
- };
};
enet1: ethernet@b1000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb1000 0x1000>;
- interrupts = <35 2 36 2 40 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb5000 0x1000>;
- interrupts = <51 2 52 2 67 2>;
- };
};
enet2: ethernet@b2000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb2000 0x1000>;
- interrupts = <31 2 32 2 33 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb6000 0x1000>;
- interrupts = <25 2 26 2 27 2>;
- };
};
usb@22000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl-usb2-dr";
- reg = <0x22000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <28 0x2>;
phy_type = "ulpi";
};
@@ -481,82 +247,15 @@
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl-usb2-dr";
- reg = <0x23000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <46 0x2>;
phy_type = "ulpi";
};
*/
- sdhci@2e000 {
- compatible = "fsl,p1020-esdhc", "fsl,esdhc";
- reg = <0x2e000 0x1000>;
- interrupts = <72 0x2>;
- interrupt-parent = <&mpic>;
- /* Filled in by U-Boot */
- clock-frequency = <0>;
- };
-
- crypto@30000 {
- compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
- "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
- reg = <0x30000 0x10000>;
- interrupts = <45 2 58 2>;
- interrupt-parent = <&mpic>;
- fsl,num-channels = <4>;
- fsl,channel-fifo-len = <24>;
- fsl,exec-units-mask = <0xbfe>;
- fsl,descriptor-types-mask = <0x3ab0ebf>;
- };
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x40000 0x40000>;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- };
-
- msi@41600 {
- compatible = "fsl,p1020-msi", "fsl,mpic-msi";
- reg = <0x41600 0x80>;
- msi-available-ranges = <0 0x100>;
- interrupts = <
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0>;
- interrupt-parent = <&mpic>;
- };
-
- global-utilities@e0000 { //global utilities block
- compatible = "fsl,p1020-guts";
- reg = <0xe0000 0x1000>;
- fsl,has-rstcr;
- };
};
pci0: pcie@ffe09000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0 0xffe09000 0 0x1000>;
- bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
@@ -573,18 +272,8 @@
};
pci1: pcie@ffe0a000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0 0xffe0a000 0 0x1000>;
- bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
new file mode 100644
index 0000000..7b87d00
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020si.dtsi
@@ -0,0 +1,378 @@
+/*
+ * P1020si Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P1020";
+ compatible = "fsl,P1020";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P1020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P1020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ localbus@ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p1020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <16 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p1020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p1020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2,256K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ mdio@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x24000 0x1000 0xb0030 0x4>;
+
+ };
+
+ mdio@25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x25000 0x1000 0xb1030 0x4>;
+
+ };
+
+ enet0: ethernet@b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb0000 0x1000>;
+ interrupts = <29 2 30 2 34 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb4000 0x1000>;
+ interrupts = <17 2 18 2 24 2>;
+ };
+ };
+
+ enet1: ethernet@b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb1000 0x1000>;
+ interrupts = <35 2 36 2 40 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb5000 0x1000>;
+ interrupts = <51 2 52 2 67 2>;
+ };
+ };
+
+ enet2: ethernet@b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb2000 0x1000>;
+ interrupts = <31 2 32 2 33 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb6000 0x1000>;
+ interrupts = <25 2 26 2 27 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ };
+
+ /* USB2 is shared with localbus, so it must be disabled
+ by default. We can't put 'status = "disabled";' here
+ since U-Boot doesn't clear the status property when
+ it enables USB2. OTOH, U-Boot does create a new node
+ when there isn't any. So, just comment it out.
+ usb@23000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <46 0x2>;
+ phy_type = "ulpi";
+ };
+ */
+
+ sdhci@2e000 {
+ compatible = "fsl,p1020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi@41600 {
+ compatible = "fsl,p1020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,p1020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ pci1: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+};
--
1.7.3
^ permalink raw reply related
* [PATCH] powerpc: Free up some CPU feature bits by moving out MMU-related features
From: Matt Evans @ 2011-04-07 5:48 UTC (permalink / raw)
To: linuxppc-dev
Some of the 64bit PPC CPU features are MMU-related, so this patch moves
them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to
mmu_has_feature(), and seven feature bits are freed as a result.
Signed-off-by: Matt Evans <matt@ozlabs.org>
---
Boot-tested on pseries and G5.
arch/powerpc/include/asm/cputable.h | 52 ++++++++++++++-------------
arch/powerpc/include/asm/mmu.h | 28 +++++++++++++++
arch/powerpc/include/asm/mmu_context.h | 2 +-
arch/powerpc/kernel/cputable.c | 39 ++++++++++-----------
arch/powerpc/kernel/entry_64.S | 8 ++--
arch/powerpc/kernel/exceptions-64s.S | 4 +-
arch/powerpc/kernel/process.c | 4 +-
arch/powerpc/kernel/prom.c | 17 +++++----
arch/powerpc/kernel/setup_64.c | 2 +-
arch/powerpc/mm/hash_low_64.S | 8 ++--
arch/powerpc/mm/hash_native_64.c | 8 ++--
arch/powerpc/mm/hash_utils_64.c | 18 +++++-----
arch/powerpc/mm/hugetlbpage.c | 2 +-
arch/powerpc/mm/slb.c | 4 +-
arch/powerpc/mm/slb_low.S | 8 ++--
arch/powerpc/mm/stab.c | 2 +-
arch/powerpc/platforms/iseries/exception.S | 2 +-
arch/powerpc/platforms/iseries/setup.c | 4 +-
arch/powerpc/platforms/pseries/lpar.c | 2 +-
arch/powerpc/xmon/xmon.c | 2 +-
20 files changed, 123 insertions(+), 93 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index be3cdf9..7b0fe7c 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -178,22 +178,15 @@ extern const char *powerpc_base_platform;
#define LONG_ASM_CONST(x) 0
#endif
-#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
-#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
-#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
-#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
@@ -205,9 +198,10 @@ extern const char *powerpc_base_platform;
#ifndef __ASSEMBLY__
-#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
- CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
- CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
+#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+
+#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
+ MMU_FTR_16M_PAGE)
/* We only set the altivec features if the kernel was compiled with altivec
* support
@@ -405,41 +399,49 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
- CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
- CPU_FTR_POPCNTB)
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
+ CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
- CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
- CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | CPU_FTR_SPURR | \
+ CPU_FTR_REAL_LE | CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
- CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
- CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | CPU_FTR_SPURR | \
+ CPU_FTR_REAL_LE | CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
- CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
+ CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
CPU_FTR_UNALIGNED_LD_STD)
#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | \
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
- CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_PURR | CPU_FTR_REAL_LE)
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
+/* MMU feature bit sets for various CPUs */
+#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
+ MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
+#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
+#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
+#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | \
+ MMU_FTR_TLBIE_206
+#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+ MMU_FTR_CI_LARGE_PAGE
+#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+ MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
+
#ifdef __powerpc64__
#define CPU_FTRS_POSSIBLE \
(CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
- CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
- CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
+ CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_VSX)
#else
enum {
CPU_FTRS_POSSIBLE =
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index bb40a06..388189e 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -70,6 +70,34 @@
*/
#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
+/* MMU is SLB-based
+ */
+#define MMU_FTR_SLB ASM_CONST(0x02000000)
+
+/* Support 16M large pages
+ */
+#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
+
+/* Supports TLBIEL variant
+ */
+#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
+
+/* Supports tlbies w/o locking
+ */
+#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
+
+/* Large pages can be marked CI
+ */
+#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
+
+/* 1T segments available
+ */
+#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
+
+/* Doesn't support the B bit (1T segment) in SLBIE
+ */
+#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
+
#ifndef __ASSEMBLY__
#include <asm/cputable.h>
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index 81fb412..8e13f65 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -67,7 +67,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* sub architectures.
*/
#ifdef CONFIG_PPC_STD_MMU_64
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
switch_slb(tsk, next);
else
switch_stab(tsk, next);
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index c9b68d0..387c549 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -199,7 +199,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER4 (gp)",
.cpu_features = CPU_FTRS_POWER4,
.cpu_user_features = COMMON_USER_POWER4,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER4,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -214,7 +214,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER4+ (gq)",
.cpu_features = CPU_FTRS_POWER4,
.cpu_user_features = COMMON_USER_POWER4,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER4,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -230,7 +230,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_PPC970,
.cpu_user_features = COMMON_USER_POWER4 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PPC970,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -248,7 +248,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_PPC970,
.cpu_user_features = COMMON_USER_POWER4 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PPC970,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -284,7 +284,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_PPC970,
.cpu_user_features = COMMON_USER_POWER4 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PPC970,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -302,7 +302,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_PPC970,
.cpu_user_features = COMMON_USER_POWER4 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PPC970,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -318,7 +318,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER5 (gr)",
.cpu_features = CPU_FTRS_POWER5,
.cpu_user_features = COMMON_USER_POWER5,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER5,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -338,7 +338,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER5+ (gs)",
.cpu_features = CPU_FTRS_POWER5,
.cpu_user_features = COMMON_USER_POWER5_PLUS,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER5,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -354,7 +354,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER5+ (gs)",
.cpu_features = CPU_FTRS_POWER5,
.cpu_user_features = COMMON_USER_POWER5_PLUS,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER5,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -371,7 +371,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER5+",
.cpu_features = CPU_FTRS_POWER5,
.cpu_user_features = COMMON_USER_POWER5_PLUS,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER5,
.icache_bsize = 128,
.dcache_bsize = 128,
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
@@ -385,7 +385,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_POWER6,
.cpu_user_features = COMMON_USER_POWER6 |
PPC_FEATURE_POWER6_EXT,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER6,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -404,7 +404,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER6 (architected)",
.cpu_features = CPU_FTRS_POWER6,
.cpu_user_features = COMMON_USER_POWER6,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER6,
.icache_bsize = 128,
.dcache_bsize = 128,
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
@@ -417,8 +417,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7 (architected)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
.oprofile_type = PPC_OPROFILE_POWER4,
@@ -431,8 +430,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7 (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -447,8 +445,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7+ (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -465,7 +462,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
PPC_FEATURE_SMT,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_CELL,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 4,
@@ -480,7 +477,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "PA6T",
.cpu_features = CPU_FTRS_PA6T,
.cpu_user_features = COMMON_USER_PA6T,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PA6T,
.icache_bsize = 64,
.dcache_bsize = 64,
.num_pmcs = 6,
@@ -497,7 +494,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER4 (compatible)",
.cpu_features = CPU_FTRS_COMPATIBLE,
.cpu_user_features = COMMON_USER_PPC64,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index d82878c..32c2605 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -462,10 +462,10 @@ BEGIN_FTR_SECTION
FTR_SECTION_ELSE_NESTED(95)
clrrdi r6,r8,40 /* get its 1T ESID */
clrrdi r9,r1,40 /* get current sp 1T ESID */
- ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95)
+ ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
FTR_SECTION_ELSE
b 2f
-ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
clrldi. r0,r6,2 /* is new ESID c00000000? */
cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
cror eq,4*cr1+eq,eq
@@ -479,7 +479,7 @@ BEGIN_FTR_SECTION
li r9,MMU_SEGSIZE_1T /* insert B field */
oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
/* Update the last bolted SLB. No write barriers are needed
* here, provided we only update the current CPU's SLB shadow
@@ -491,7 +491,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
- /* No need to check for CPU_FTR_NO_SLBIE_B here, since when
+ /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
* we have 1TB segments, the only CPUs known to have the errata
* only support less than 1TB of system memory and we'll never
* actually hit this code path.
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index c532cb2..2279294 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -74,7 +74,7 @@ BEGIN_FTR_SECTION
EXCEPTION_PROLOG_PSERIES_1(data_access_common)
FTR_SECTION_ELSE
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
-ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
. = 0x380
.globl data_access_slb_pSeries
@@ -750,7 +750,7 @@ _STATIC(do_hash_page)
BEGIN_FTR_SECTION
andis. r0,r4,0x0020 /* Is it a segment table fault? */
bne- do_ste_alloc /* If so handle it */
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
clrrdi r11,r1,THREAD_SHIFT
lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index f74f355..65c3802 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -755,11 +755,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
_ALIGN_UP(sizeof(struct thread_info), 16);
#ifdef CONFIG_PPC_STD_MMU_64
- if (cpu_has_feature(CPU_FTR_SLB)) {
+ if (mmu_has_feature(MMU_FTR_SLB)) {
unsigned long sp_vsid;
unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
- if (cpu_has_feature(CPU_FTR_1T_SEGMENT))
+ if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
<< SLB_VSID_SHIFT_1T;
else
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 05b7139..b48b04f 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -123,18 +123,19 @@ static void __init move_device_tree(void)
*/
static struct ibm_pa_feature {
unsigned long cpu_features; /* CPU_FTR_xxx bit */
+ unsigned long mmu_features; /* MMU_FTR_xxx bit */
unsigned int cpu_user_ftrs; /* PPC_FEATURE_xxx bit */
unsigned char pabyte; /* byte number in ibm,pa-features */
unsigned char pabit; /* bit number (big-endian) */
unsigned char invert; /* if 1, pa bit set => clear feature */
} ibm_pa_features[] __initdata = {
- {0, PPC_FEATURE_HAS_MMU, 0, 0, 0},
- {0, PPC_FEATURE_HAS_FPU, 0, 1, 0},
- {CPU_FTR_SLB, 0, 0, 2, 0},
- {CPU_FTR_CTRL, 0, 0, 3, 0},
- {CPU_FTR_NOEXECUTE, 0, 0, 6, 0},
- {CPU_FTR_NODSISRALIGN, 0, 1, 1, 1},
- {CPU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0},
+ {0, 0, PPC_FEATURE_HAS_MMU, 0, 0, 0},
+ {0, 0, PPC_FEATURE_HAS_FPU, 0, 1, 0},
+ {0, MMU_FTR_SLB, 0, 0, 2, 0},
+ {CPU_FTR_CTRL, 0, 0, 0, 3, 0},
+ {CPU_FTR_NOEXECUTE, 0, 0, 0, 6, 0},
+ {CPU_FTR_NODSISRALIGN, 0, 0, 1, 1, 1},
+ {0, MMU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0},
{CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0},
};
@@ -166,9 +167,11 @@ static void __init scan_features(unsigned long node, unsigned char *ftrs,
if (bit ^ fp->invert) {
cur_cpu_spec->cpu_features |= fp->cpu_features;
cur_cpu_spec->cpu_user_features |= fp->cpu_user_ftrs;
+ cur_cpu_spec->mmu_features |= fp->mmu_features;
} else {
cur_cpu_spec->cpu_features &= ~fp->cpu_features;
cur_cpu_spec->cpu_user_features &= ~fp->cpu_user_ftrs;
+ cur_cpu_spec->mmu_features &= ~fp->mmu_features;
}
}
}
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 5a0401f..2902f48 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -425,7 +425,7 @@ void __init setup_system(void)
static u64 slb0_limit(void)
{
- if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
+ if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
return 1UL << SID_SHIFT_1T;
}
return 1UL << SID_SHIFT;
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 3079f6b..36def97 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -118,7 +118,7 @@ _GLOBAL(__hash_page_4K)
BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
/* Calc va and put it in r29 */
rldicr r29,r5,28,63-28
rldicl r3,r3,0,36
@@ -401,7 +401,7 @@ _GLOBAL(__hash_page_4K)
BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
/* Calc va and put it in r29 */
rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */
rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */
@@ -715,7 +715,7 @@ BEGIN_FTR_SECTION
andi. r0,r31,_PAGE_NO_CACHE
/* If so, bail out and refault as a 4k page */
bne- ht64_bail_ok
-END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_CI_LARGE_PAGE)
/* Prepare new PTE value (turn access RW into DIRTY, then
* add BUSY and ACCESSED)
*/
@@ -736,7 +736,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
/* Calc va and put it in r29 */
rldicr r29,r5,28,63-28
rldicl r3,r3,0,36
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 784a400..c23eef2 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -98,8 +98,8 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize)
static inline void tlbie(unsigned long va, int psize, int ssize, int local)
{
- unsigned int use_local = local && cpu_has_feature(CPU_FTR_TLBIEL);
- int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+ unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
+ int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
if (use_local)
use_local = mmu_psize_defs[psize].tlbiel;
@@ -503,7 +503,7 @@ static void native_flush_hash_range(unsigned long number, int local)
} pte_iterate_hashed_end();
}
- if (cpu_has_feature(CPU_FTR_TLBIEL) &&
+ if (mmu_has_feature(MMU_FTR_TLBIEL) &&
mmu_psize_defs[psize].tlbiel && local) {
asm volatile("ptesync":::"memory");
for (i = 0; i < number; i++) {
@@ -517,7 +517,7 @@ static void native_flush_hash_range(unsigned long number, int local)
}
asm volatile("ptesync":::"memory");
} else {
- int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+ int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
if (lock_tlbie)
raw_spin_lock(&native_tlbie_lock);
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index a5991fa..2f0b834 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -258,11 +258,11 @@ static int __init htab_dt_scan_seg_sizes(unsigned long node,
for (; size >= 4; size -= 4, ++prop) {
if (prop[0] == 40) {
DBG("1T segment support detected\n");
- cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
+ cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
return 1;
}
}
- cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
+ cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
return 0;
}
@@ -288,7 +288,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
if (prop != NULL) {
DBG("Page sizes from device-tree:\n");
size /= 4;
- cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
+ cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
while(size > 0) {
unsigned int shift = prop[0];
unsigned int slbenc = prop[1];
@@ -316,7 +316,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
break;
case 0x18:
idx = MMU_PAGE_16M;
- cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
+ cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
break;
case 0x22:
idx = MMU_PAGE_16G;
@@ -411,7 +411,7 @@ static void __init htab_init_page_sizes(void)
* Not in the device-tree, let's fallback on known size
* list for 16M capable GP & GR
*/
- if (cpu_has_feature(CPU_FTR_16M_PAGE))
+ if (mmu_has_feature(MMU_FTR_16M_PAGE))
memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
sizeof(mmu_psize_defaults_gp));
found:
@@ -441,7 +441,7 @@ static void __init htab_init_page_sizes(void)
mmu_vmalloc_psize = MMU_PAGE_64K;
if (mmu_linear_psize == MMU_PAGE_4K)
mmu_linear_psize = MMU_PAGE_64K;
- if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
+ if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
/*
* Don't use 64k pages for ioremap on pSeries, since
* that would stop us accessing the HEA ethernet.
@@ -598,7 +598,7 @@ static void __init htab_initialize(void)
/* Initialize page sizes */
htab_init_page_sizes();
- if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
+ if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
mmu_kernel_ssize = MMU_SEGSIZE_1T;
mmu_highuser_ssize = MMU_SEGSIZE_1T;
printk(KERN_INFO "Using 1TB segments\n");
@@ -739,7 +739,7 @@ void __init early_init_mmu(void)
/* Initialize stab / SLB management except on iSeries
*/
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
slb_initialize();
else if (!firmware_has_feature(FW_FEATURE_ISERIES))
stab_initialize(get_paca()->stab_real);
@@ -756,7 +756,7 @@ void __cpuinit early_init_mmu_secondary(void)
* in real mode on pSeries and we want a virutal address on
* iSeries anyway
*/
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
slb_initialize();
else
stab_initialize(get_paca()->stab_addr);
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 9bb249c..0b9a5c1 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -529,7 +529,7 @@ static int __init hugetlbpage_init(void)
{
int psize;
- if (!cpu_has_feature(CPU_FTR_16M_PAGE))
+ if (!mmu_has_feature(MMU_FTR_16M_PAGE))
return -ENODEV;
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 1d98ecc..3657531 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -166,7 +166,7 @@ static inline int esids_match(unsigned long addr1, unsigned long addr2)
int esid_1t_count;
/* System is not 1T segment size capable. */
- if (!cpu_has_feature(CPU_FTR_1T_SEGMENT))
+ if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
return (GET_ESID(addr1) == GET_ESID(addr2));
esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
@@ -201,7 +201,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
*/
hard_irq_disable();
offset = get_paca()->slb_cache_ptr;
- if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) &&
+ if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
offset <= SLB_CACHE_ENTRIES) {
int i;
asm volatile("isync" : : : "memory");
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 95ce355..ef653dc 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -58,7 +58,7 @@ _GLOBAL(slb_miss_kernel_load_linear)
li r11,0
BEGIN_FTR_SECTION
b slb_finish_load
-END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
b slb_finish_load_1T
1:
@@ -87,7 +87,7 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
6:
BEGIN_FTR_SECTION
b slb_finish_load
-END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -138,11 +138,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
ld r9,PACACONTEXTID(r13)
BEGIN_FTR_SECTION
cmpldi r10,0x1000
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
rldimi r10,r9,USER_ESID_BITS,0
BEGIN_FTR_SECTION
bge slb_finish_load_1T
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
b slb_finish_load
8: /* invalid EA */
diff --git a/arch/powerpc/mm/stab.c b/arch/powerpc/mm/stab.c
index 446a018..41e3164 100644
--- a/arch/powerpc/mm/stab.c
+++ b/arch/powerpc/mm/stab.c
@@ -243,7 +243,7 @@ void __init stabs_alloc(void)
{
int cpu;
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
return;
for_each_possible_cpu(cpu) {
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index 32a56c6..703b1c9 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -157,7 +157,7 @@ BEGIN_FTR_SECTION
FTR_SECTION_ELSE
EXCEPTION_PROLOG_1(PACA_EXGEN)
EXCEPTION_PROLOG_ISERIES_1
-ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
b data_access_common
.do_stab_bolted_iSeries:
diff --git a/arch/powerpc/platforms/iseries/setup.c b/arch/powerpc/platforms/iseries/setup.c
index 2946ae1..81cb8d2 100644
--- a/arch/powerpc/platforms/iseries/setup.c
+++ b/arch/powerpc/platforms/iseries/setup.c
@@ -249,7 +249,7 @@ static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
unsigned long i;
unsigned long mem_blocks = 0;
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
max_entries);
else
@@ -634,7 +634,7 @@ static int __init iseries_probe(void)
hpte_init_iSeries();
/* iSeries does not support 16M pages */
- cur_cpu_spec->cpu_features &= ~CPU_FTR_16M_PAGE;
+ cur_cpu_spec->mmu_features &= ~MMU_FTR_16M_PAGE;
return 1;
}
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index ca5d589..6f0ed3a 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -573,7 +573,7 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
unsigned long i, pix, rc;
unsigned long flags = 0;
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
- int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+ int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
unsigned long param[9];
unsigned long va;
unsigned long hash, index, shift, hidx, slot;
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 33794c1..57500eb 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2663,7 +2663,7 @@ static void dump_stab(void)
void dump_segments(void)
{
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
dump_slb();
else
dump_stab();
--
1.7.0.4
^ permalink raw reply related
* RE: known working sata_sil24.c setup on powerpc platforms?
From: Kushwaha Prabhakar-B32579 @ 2011-04-07 4:48 UTC (permalink / raw)
To: Leon Woestenberg
Cc: Linux PPC, Tejun Heo, Jeff Garzik, Moffett, Kyle D,
linux-ide@vger.kernel.org
In-Reply-To: <BANLkTinjn5nt4-0cSo6nUfG8Vt1UrL2Q0g@mail.gmail.com>
Hi Leon,
Can you please check p2020rdb.dts for IDSEL entries for pci0/1 node?
In order to work in legacy mode, IDSEL entries are required.=20
--Prabhakar
> -----Original Message-----
> From: linux-ide-owner@vger.kernel.org [mailto:linux-ide-
> owner@vger.kernel.org] On Behalf Of Leon Woestenberg
> Sent: Thursday, April 07, 2011 12:20 AM
> To: Jeff Garzik
> Cc: Moffett, Kyle D; Linux PPC; linux-ide@vger.kernel.org; Tejun Heo
> Subject: Re: known working sata_sil24.c setup on powerpc platforms?
>=20
> Hello Jeff, all,
>=20
> On Wed, Apr 6, 2011 at 8:12 PM, Jeff Garzik <jeff@garzik.org> wrote:
> > On 04/06/2011 01:48 PM, Moffett, Kyle D wrote:
> >> On Apr 06, 2011, at 13:00, Leon Woestenberg wrote:
> >>> after investigating problems with sata_sil24.c on a freescale p2020
> >>> soc, I wonder if this driver works on powerpc at all?
> >>>
> >>> Does anyone know of a working setup of sata_sil24 on a big endian
> >>> powerpc system?
> >>
> >> Our P2020 boards work fine with legacy PCI interrupts (I think it's a
> >> sil3124 over PCI-E); the only deficiency is that MSI does not seem to
> work.
> >>
> >
> > We've definitely had issues with sata_sil24 + MSI, also...
> >
> > sata_sil24 does work on big endian in general.
> >
>=20
> On my system, I have the contrary to Kyle's experience (thanks for
> sharing).
>=20
> PowerPC P2020RDB
> vanilla 2.6.38
> Sil3132 on mini-PCI Express card
>=20
>=20
> Enabling msi gets me further than disabling it (default).
>=20
> modprobe sata_sil
>=20
> [ 8.834613] sata_sil24 0001:03:00.0: version 1.1
> [ 8.885581] scsi0 : sata_sil24
> [ 8.901420] scsi1 : sata_sil24
> [ 8.904642] ata1: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0004000 irq 16
> [ 8.911961] ata2: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0006000 irq 16
> [ 11.095127] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
> [ 14.906986] eth0: no IPv6 routers present
> [ 16.099016] ata1.00: qc timeout (cmd 0xec)
> [ 16.103128] ata1.00: failed to IDENTIFY (I/O error, err_mask=3D0x4)
> [ 18.299050] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
> [ 28.303026] ata1.00: qc timeout (cmd 0xec)
> [ 28.307139] ata1.00: failed to IDENTIFY (I/O error, err_mask=3D0x4)
> [ 28.313233] ata1: limiting SATA link speed to 1.5 Gbps
> [ 30.523059] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 10)
>=20
>=20
> modprobe sata_sil msi=3D1
>=20
> [ 92.984120] sata_sil24 0001:03:00.0: version 1.1
> [ 92.988897] irq: irq 0 on host /soc@ffe00000/msi@41600 mapped to
> virtual irq 41
> [ 92.996229] sata_sil24 0001:03:00.0: Using MSI
> [ 93.000675] sata_sil24 0001:03:00.0: enabling bus mastering
> [ 93.011628] scsi2 : sata_sil24
> [ 93.022463] scsi3 : sata_sil24
> [ 93.025695] ata3: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0004000 irq 41
> [ 93.033023] ata4: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0006000 irq 41
> [ 95.203029] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
> [ 95.209045] ata3: spurious interrupt (slot_stat 0x0 active_tag
> -84148995 sactive 0x0)
> [ 95.217171] ata3.00: ATA-7: INTEL SSDSA2M080G2GN, 2CV102HD, max
> UDMA/133
> [ 95.223882] ata3.00: 156301488 sectors, multi 1: LBA48 NCQ (depth
> 31/32)
> [ 95.230905] ata3.00: configured for UDMA/100
> [ 95.235399] scsi 2:0:0:0: Direct-Access ATA INTEL
> SSDSA2M080 2CV1 PQ: 0 ANSI: 5
> [ 95.244002] sd 2:0:0:0: Attached scsi generic sg0 type 0
> [ 95.252041] sd 2:0:0:0: [sda] 156301488 512-byte logical blocks:
> (80.0 GB/74.5 GiB)
> [ 95.260219] sd 2:0:0:0: [sda] Write Protect is off
> [ 95.265063] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00
> [ 95.270500] sd 2:0:0:0: [sda] Write cache: enabled, read cache:
> enabled, doesn't support DPO or FUA
> [ 95.283779] sda: sda1 sda2 sda3 sda4
> [ 95.289482] sd 2:0:0:0: [sda] Attached SCSI disk
> [ 95.965897] EXT3-fs: barriers not enabled
> [ 95.977279] kjournald starting. Commit interval 5 seconds
> [ 95.983296] EXT3-fs (sda2): using internal journal
> [ 95.988143] EXT3-fs (sda2): recovery complete
> [ 95.992504] EXT3-fs (sda2): mounted filesystem with writeback data
> mode
> [ 96.111587] NTFS volume version 3.1.
> [ 97.331005] ata4: SATA link down (SStatus 0 SControl 0)
>=20
> root@p1020rdb:~# dd if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D1000
> 1000+0 records in
> 1000+0 records out
> 4096000 bytes (4.1 MB) copied, 0.0315629 s, 130 MB/s root@p1020rdb:~# dd
> if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D10000
> 10000+0 records in
> 10000+0 records out
> 40960000 bytes (41 MB) copied, 0.471802 s, 86.8 MB/s
>=20
> root@p1020rdb:~# dd if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D100000
>=20
> That stalls, I see the controller fail. See dmesg below:
>=20
> ^C^Cdd: reading `/dev/sda': Input/output error
> 51804+0 records in
> 51804+0 records out
> 212189184 bytes (212 MB) copied, 85.6537 s, 2.5 MB/s
> dd: closing input file `/dev/sda': Bad file descriptor
>=20
>=20
> [ 92.984120] sata_sil24 0001:03:00.0: version 1.1
> [ 92.988897] irq: irq 0 on host /soc@ffe00000/msi@41600 mapped to
> virtual irq 41
> [ 92.996229] sata_sil24 0001:03:00.0: Using MSI
> [ 93.000675] sata_sil24 0001:03:00.0: enabling bus mastering
> [ 93.011628] scsi2 : sata_sil24
> [ 93.022463] scsi3 : sata_sil24
> [ 93.025695] ata3: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0004000 irq 41
> [ 93.033023] ata4: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0006000 irq 41
> [ 95.203029] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
> [ 95.209045] ata3: spurious interrupt (slot_stat 0x0 active_tag
> -84148995 sactive 0x0)
> [ 95.217171] ata3.00: ATA-7: INTEL SSDSA2M080G2GN, 2CV102HD, max
> UDMA/133
> [ 95.223882] ata3.00: 156301488 sectors, multi 1: LBA48 NCQ (depth
> 31/32)
> [ 95.230905] ata3.00: configured for UDMA/100
> [ 95.235399] scsi 2:0:0:0: Direct-Access ATA INTEL
> SSDSA2M080 2CV1 PQ: 0 ANSI: 5
> [ 95.244002] sd 2:0:0:0: Attached scsi generic sg0 type 0
> [ 95.252041] sd 2:0:0:0: [sda] 156301488 512-byte logical blocks:
> (80.0 GB/74.5 GiB)
> [ 95.260219] sd 2:0:0:0: [sda] Write Protect is off
> [ 95.265063] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00
> [ 95.270500] sd 2:0:0:0: [sda] Write cache: enabled, read cache:
> enabled, doesn't support DPO or FUA
> [ 95.283779] sda: sda1 sda2 sda3 sda4
> [ 95.289482] sd 2:0:0:0: [sda] Attached SCSI disk
> [ 95.965897] EXT3-fs: barriers not enabled
> [ 95.977279] kjournald starting. Commit interval 5 seconds
> [ 95.983296] EXT3-fs (sda2): using internal journal
> [ 95.988143] EXT3-fs (sda2): recovery complete
> [ 95.992504] EXT3-fs (sda2): mounted filesystem with writeback data
> mode
> [ 96.111587] NTFS volume version 3.1.
> [ 97.331005] ata4: SATA link down (SStatus 0 SControl 0)
> [ 285.891036] ata3.00: exception Emask 0x0 SAct 0x3 SErr 0x0 action 0x6
> frozen [ 285.898099] ata3.00: failed command: READ FPDMA QUEUED [
> 285.903250] ata3.00: cmd 60/00:00:e0:53:06/01:00:00:00:00/40 tag 0 ncq
> 131072 in
> [ 285.903255] res 40/00:00:00:00:00/00:00:00:00:00/00 Emask
> 0x4 (timeout)
> [ 285.918028] ata3.00: status: { DRDY } [ 285.921689] ata3.00: failed
> command: READ FPDMA QUEUED [ 285.926836] ata3.00: cmd
> 60/00:08:e0:52:06/01:00:00:00:00/40 tag 1 ncq 131072 in
> [ 285.926841] res 40/00:00:00:00:00/00:00:00:00:00/00 Emask
> 0x4 (timeout)
> [ 285.941615] ata3.00: status: { DRDY } [ 285.945281] ata3: hard
> resetting link [ 288.055034] ata3: SATA link up 3.0 Gbps (SStatus 123
> SControl 0) [ 293.058999] ata3.00: qc timeout (cmd 0xec) [ 293.063106]
> ata3.00: failed to IDENTIFY (I/O error, err_mask=3D0x4) [ 293.069198]
> ata3.00: revalidation failed (errno=3D-5) [ 293.074077] ata3: hard
> resetting link [ 295.259018] ata3: SATA link up 3.0 Gbps (SStatus 123
> SControl 0)
>=20
> What can I do next to investigate and help fix this issue?
>=20
>=20
> Regards,
> --
> Leon
> --
> To unsubscribe from this list: send the line "unsubscribe linux-ide" in
> the body of a message to majordomo@vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: sdhc/mpc8536 - SDCard always detected like read-only - SOLVED.
From: Wolfram Sang @ 2011-04-07 4:51 UTC (permalink / raw)
To: Carlos Roberto Moratelli; +Cc: linuxppc-dev
In-Reply-To: <1302127065.2647.60.camel@moratelli-host.digitel.com.br>
[-- Attachment #1: Type: text/plain, Size: 649 bytes --]
> Reading the MPC8536E Chip Errata I saw the SDHC_WP signal polarity is
> reversed to the silicon revision 1.0.
>
> Unfortunately my prototype board is using revision 1.0. So, I asked to
> my hardware team workaround putting an extra inverter for the SDHC_WP
> signal.
>
> Now its working fine!
OK, nice. I fail to see from a glimpse how all this is related to the
timeout-errors you were seeing (-110), but if it works now, all is fine, I
guess.
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]
^ permalink raw reply
* Re: [PATCH] POWER: perf_event: Skip updating kernel counters if register value shrinks
From: Benjamin Herrenschmidt @ 2011-04-07 4:22 UTC (permalink / raw)
To: Eric B Munson
Cc: a.p.zijlstra, linux-kernel, paulus, anton, acme, mingo,
linuxppc-dev
In-Reply-To: <20110406212733.GB2596@mgebm.net>
> > Doesn't that mean that power_pmu_read() can only ever increase the value of
> > the perf_event and so will essentially -stop- once the counter rolls over ?
> >
> > Similar comments every where you do this type of comparison.
> >
> > Cheers,
> > Ben.
>
> Sorry for the nag, but am I missing something about the way the register and
> the previous values are reset in the overflow interrupt handler?
Well, not all counters get interrupts right ? Some counters are just
free running... I'm not sure when that power_pmu_read() function is
actually used by the core, I'm not that familiar with perf, but I'd say
better safe than sorry. When comparing counter values, doing in a way
that is generally safe vs. wraparounds. Eventually do a helper for that.
Cheers,
Ben.
^ permalink raw reply
* [PATCH] powerpc: Use new CPU feature bit to select 2.06 tlbie
From: Michael Neuling @ 2011-04-07 4:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1301986248.2549.141.camel@pasglop>
This removes MMU_FTR_TLBIE_206 as we can now use CPU_FTR_HVMODE_206. It
also changes the logic to select which tlbie to use to be based on this
new CPU feature bit.
This also duplicates the ASM_FTR_IF/SET/CLR defines for CPU features
(copied from MMU features).
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
Subject: Re: [PATCH 04/15] powerpc: Define CPU feature for Architected 2.06 HV mode
> > > +#define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x00000008000000
00)
> >
> > FYI With this patch we could remove MMU_FTR_TLBIE_206.
>
> We could... care to send a patch ? :-)
Sure... How about this?
Mikey
arch/powerpc/include/asm/feature-fixups.h | 13 +++++++++++++
arch/powerpc/include/asm/mmu.h | 5 -----
arch/powerpc/kernel/cputable.c | 9 +++------
arch/powerpc/mm/hash_native_64.c | 8 ++++----
4 files changed, 20 insertions(+), 15 deletions(-)
Index: clone1/arch/powerpc/include/asm/feature-fixups.h
===================================================================
--- clone1.orig/arch/powerpc/include/asm/feature-fixups.h
+++ clone1/arch/powerpc/include/asm/feature-fixups.h
@@ -146,6 +146,19 @@
#ifndef __ASSEMBLY__
+#define ASM_FTR_IF(section_if, section_else, msk, val) \
+ stringify_in_c(BEGIN_FTR_SECTION) \
+ section_if "; " \
+ stringify_in_c(FTR_SECTION_ELSE) \
+ section_else "; " \
+ stringify_in_c(ALT_FTR_SECTION_END((msk), (val)))
+
+#define ASM_FTR_IFSET(section_if, section_else, msk) \
+ ASM_FTR_IF(section_if, section_else, (msk), (msk))
+
+#define ASM_FTR_IFCLR(section_if, section_else, msk) \
+ ASM_FTR_IF(section_if, section_else, (msk), 0)
+
#define ASM_MMU_FTR_IF(section_if, section_else, msk, val) \
stringify_in_c(BEGIN_MMU_FTR_SECTION) \
section_if "; " \
Index: clone1/arch/powerpc/include/asm/mmu.h
===================================================================
--- clone1.orig/arch/powerpc/include/asm/mmu.h
+++ clone1/arch/powerpc/include/asm/mmu.h
@@ -56,11 +56,6 @@
*/
#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
-/* This indicates that the processor uses the ISA 2.06 server tlbie
- * mnemonics
- */
-#define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000)
-
/* Enable use of TLB reservation. Processor should support tlbsrx.
* instruction and MAS0[WQ].
*/
Index: clone1/arch/powerpc/kernel/cputable.c
===================================================================
--- clone1.orig/arch/powerpc/kernel/cputable.c
+++ clone1/arch/powerpc/kernel/cputable.c
@@ -417,8 +417,7 @@
.cpu_name = "POWER7 (architected)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTR_HPTE_TABLE,
.icache_bsize = 128,
.dcache_bsize = 128,
.oprofile_type = PPC_OPROFILE_POWER4,
@@ -433,8 +432,7 @@
.cpu_name = "POWER7 (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTR_HPTE_TABLE,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -451,8 +449,7 @@
.cpu_name = "POWER7+ (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTR_HPTE_TABLE,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
Index: clone1/arch/powerpc/mm/hash_native_64.c
===================================================================
--- clone1.orig/arch/powerpc/mm/hash_native_64.c
+++ clone1/arch/powerpc/mm/hash_native_64.c
@@ -50,9 +50,9 @@
case MMU_PAGE_4K:
va &= ~0xffful;
va |= ssize << 8;
- asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0),
+ asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0),
%2)
- : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+ : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206)
: "memory");
break;
default:
@@ -61,9 +61,9 @@
va |= penc << 12;
va |= ssize << 8;
va |= 1; /* L */
- asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0),
+ asm volatile( ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0),
%2)
- : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+ : : "r" (va), "r"(0), "i" (CPU_FTR_HVMODE_206)
: "memory");
break;
}
^ permalink raw reply
* Re: [PATCH 1/1] powerpc/eeh: Add support for ibm,configure-pe RTAS call
From: Benjamin Herrenschmidt @ 2011-04-07 3:35 UTC (permalink / raw)
To: Richard A Lary; +Cc: linuxppc-dev
In-Reply-To: <4D9CEE45.9000904@linux.vnet.ibm.com>
On Wed, 2011-04-06 at 15:50 -0700, Richard A Lary wrote:
> From: Richard A. Lary <rlary@linux.vnet.ibm.com>
>
> Added support for ibm,configure-pe RTAS call introduced with
> PAPR 2.2.
Care to tell us a bit about the difference ? :-) There's nothing obvious
in the code.... Also you added calls to rtas_configure_bridge() and
eeh_restore_bars() to eeh_slot_error_Detail(), that might want some
explanation as well.
Cheers,
Ben.
> Signed-off-by: Richard A. Lary <rlary@linux.vnet.ibm.com>
> ---
> arch/powerpc/platforms/pseries/eeh.c | 13 12 + 1 - 0 !
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> Index: b/arch/powerpc/platforms/pseries/eeh.c
> ===================================================================
> --- a/arch/powerpc/platforms/pseries/eeh.c
> +++ b/arch/powerpc/platforms/pseries/eeh.c
> @@ -95,6 +95,7 @@ static int ibm_slot_error_detail;
> static int ibm_get_config_addr_info;
> static int ibm_get_config_addr_info2;
> static int ibm_configure_bridge;
> +static int ibm_configure_pe;
>
> int eeh_subsystem_enabled;
> EXPORT_SYMBOL(eeh_subsystem_enabled);
> @@ -263,6 +264,8 @@ void eeh_slot_error_detail(struct pci_dn
> pci_regs_buf[0] = 0;
>
> rtas_pci_enable(pdn, EEH_THAW_MMIO);
> + rtas_configure_bridge(pdn);
> + eeh_restore_bars(pdn);
> loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN);
>
> rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen);
> @@ -896,6 +899,7 @@ void
> rtas_configure_bridge(struct pci_dn *pdn)
> {
> int config_addr;
> + int token;
> int rc;
>
> /* Use PE configuration address, if present */
> @@ -903,7 +907,13 @@ rtas_configure_bridge(struct pci_dn *pdn
> if (pdn->eeh_pe_config_addr)
> config_addr = pdn->eeh_pe_config_addr;
>
> - rc = rtas_call(ibm_configure_bridge,3,1, NULL,
> + /* Use new configure-pe function, if supported */
> + if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE)
> + token = ibm_configure_pe;
> + else
> + token = ibm_configure_bridge;
> +
> + rc = rtas_call(token, 3, 1, NULL,
> config_addr,
> BUID_HI(pdn->phb->buid),
> BUID_LO(pdn->phb->buid));
> @@ -1079,6 +1089,7 @@ void __init eeh_init(void)
> ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
> ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
> ibm_configure_bridge = rtas_token ("ibm,configure-bridge");
> + ibm_configure_pe = rtas_token("ibm,configure-pe");
>
> if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
> return;
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH 1/1] powerpc/eeh: Add support for ibm,configure-pe RTAS call
From: Richard A Lary @ 2011-04-06 22:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: rlary
From: Richard A. Lary <rlary@linux.vnet.ibm.com>
Added support for ibm,configure-pe RTAS call introduced with
PAPR 2.2.
Signed-off-by: Richard A. Lary <rlary@linux.vnet.ibm.com>
---
arch/powerpc/platforms/pseries/eeh.c | 13 12 + 1 - 0 !
1 file changed, 12 insertions(+), 1 deletion(-)
Index: b/arch/powerpc/platforms/pseries/eeh.c
===================================================================
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -95,6 +95,7 @@ static int ibm_slot_error_detail;
static int ibm_get_config_addr_info;
static int ibm_get_config_addr_info2;
static int ibm_configure_bridge;
+static int ibm_configure_pe;
int eeh_subsystem_enabled;
EXPORT_SYMBOL(eeh_subsystem_enabled);
@@ -263,6 +264,8 @@ void eeh_slot_error_detail(struct pci_dn
pci_regs_buf[0] = 0;
rtas_pci_enable(pdn, EEH_THAW_MMIO);
+ rtas_configure_bridge(pdn);
+ eeh_restore_bars(pdn);
loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN);
rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen);
@@ -896,6 +899,7 @@ void
rtas_configure_bridge(struct pci_dn *pdn)
{
int config_addr;
+ int token;
int rc;
/* Use PE configuration address, if present */
@@ -903,7 +907,13 @@ rtas_configure_bridge(struct pci_dn *pdn
if (pdn->eeh_pe_config_addr)
config_addr = pdn->eeh_pe_config_addr;
- rc = rtas_call(ibm_configure_bridge,3,1, NULL,
+ /* Use new configure-pe function, if supported */
+ if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE)
+ token = ibm_configure_pe;
+ else
+ token = ibm_configure_bridge;
+
+ rc = rtas_call(token, 3, 1, NULL,
config_addr,
BUID_HI(pdn->phb->buid),
BUID_LO(pdn->phb->buid));
@@ -1079,6 +1089,7 @@ void __init eeh_init(void)
ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
ibm_configure_bridge = rtas_token ("ibm,configure-bridge");
+ ibm_configure_pe = rtas_token("ibm,configure-pe");
if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
return;
^ permalink raw reply
* Re: sdhc/mpc8536 - SDCard always detected like read-only - SOLVED.
From: Carlos Roberto Moratelli @ 2011-04-06 21:57 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linuxppc-dev
In-Reply-To: <1302110338.2647.21.camel@moratelli-host.digitel.com.br>
Wolfram,
Reading the MPC8536E Chip Errata I saw the SDHC_WP signal polarity is
reversed to the silicon revision 1.0.
Unfortunately my prototype board is using revision 1.0. So, I asked to
my hardware team workaround putting an extra inverter for the SDHC_WP
signal.
Now its working fine!
Thanks,
Moratelli
Em Qua, 2011-04-06 às 14:18 -0300, Carlos Roberto Moratelli escreveu:
> I will try address the issue in details.
>
> When I insert the SDCard, the same is detect like read-only:
>
> mmcblk0: mmc0:b368 NCard 966 MiB (ro)
> mmcblk0:
> mmc0: starting CMD18 arg 00000000 flags 000000b5
> mmc0: blksz 512 blocks 8 flags 00000200 tsac 100 ms nsac 0
> mmc0: CMD12 arg 00000000 flags 0000049d
> sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x00000001
> sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x0000000a
> sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x00000001
> mmc0: req done (CMD18): 0: 00000900 00000000 00000000 00000000
> mmc0: 4096 bytes transferred: 0
> mmc0: (CMD12): 0: 00000b00 00000000 00000000 00000000
> p1
>
> So, I just can mount the filesystem read-only. I can read the fat32
> without problems.
>
> I tested your sugestion. I used sdhci,wp-inverted in my dtb. This
> changed the behavior. Now the SDCard is detected without the read-only
> flag:
>
> mmcblk0: mmc0:b368 NCard 966 MiB
> mmcblk0:
> mmc0: starting CMD18 arg 00000000 flags 000000b5
> mmc0: blksz 512 blocks 8 flags 00000200 tsac 100 ms nsac 0
> mmc0: CMD12 arg 00000000 flags 0000049d
> sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x00000001
> sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x0000000a
> sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x00000001
> mmc0: req done (CMD18): 0: 00000900 00000000 00000000 00000000
> mmc0: 4096 bytes transferred: 0
> mmc0: (CMD12): 0: 00000b00 00000000 00000000 00000000
> p1
>
> And, I can mount a rw filesystem:
>
> #mount /dev/mmcblock1 /mnt
> #cat /proc/mounts
> ...
> /dev/mmcblock1 /mnt vfat
> rw,relatime,fmask=0000,dmask=0000,allow_utime=0022,codepage=cp437,iocharset=iso8859-1,shortname=mixed,errors=remount-ro 0 0
> ...
>
> So, I can copy files to the mounted SDCard. But, When I try to umount I
> see the following error mensagens:
>
> #cp /etc/shadow /mnt
> #ls /mnt
> shadow
> #umount /mnt
> mmc0: Timeout waiting for hardware interrupt.
> mmcblk0: error -110 transferring data, sector 5944, nr 1, card status
> 0x900
> end_request: I/O error, dev mmcblk0, sector 5944
> mmc0: Timeout waiting for hardware interrupt.
> mmcblk0: error -110 transferring data, sector 5936, nr 1, card status
> 0x900
> end_request: I/O error, dev mmcblk0, sector 5936
> Buffer I/O error on device mmcblk0p1, logical block 3888
> mmc0: Timeout waiting for hardware interrupt.
> mmcblk0: error -110 transferring data, sector 2049, nr 1, card status
> 0x900
> end_request: I/O error, dev mmcblk0, sector 2049
> Buffer I/O error on device mmcblk0p1, logical block 1
> mmc0: Timeout waiting for hardware interrupt.
> mmcblk0: error -110 transferring data, sector 2080, nr 1, card status
> 0x900
> end_request: I/O error, dev mmcblk0, sector 2080
> ...
>
> I think I need the sdhci,wp-inverted in my dtb. But, it appears that
> more something is necessary.
>
> Has someone faced this situation?
>
> Thanks by the help until here.
>
> Regards,
>
> Moratelli
>
>
>
> Em Qua, 2011-04-06 às 01:48 +0200, Wolfram Sang escreveu:
> > > sdhci@2e000 {
> > > compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
> > > reg = <0x2e000 0x1000>;
> > > interrupts = <72 0x2>;
> > > interrupt-parent = <&mpic>;
> > > /* Filled in by U-Boot */
> > > clock-frequency = <0>;
> > > };
> >
> > Hmm, I am not too familiar with those SoCs, yet some 83xx needed
> >
> > sdhci,wp-inverted;
> >
> > here. Maybe yours, too? Would fit the symptoms.
> >
> > Regards,
> >
> > Wolfram
> >
>
^ permalink raw reply
* Re: Using dmaengine on Freescale P2020 RDB
From: Ira W. Snyder @ 2011-04-06 21:28 UTC (permalink / raw)
To: Chuck Ketcham; +Cc: linuxppc-dev
In-Reply-To: <523835.3776.qm@web36403.mail.mud.yahoo.com>
On Wed, Apr 06, 2011 at 01:29:05PM -0700, Chuck Ketcham wrote:
> Ira,
>
> Thanks for the reference to the CARMA drivers. I will have to take a look at that.
>
> In my case, CONFIG_NET_DMA is not enabled. However, I did notice the following entry in my p2020rdb.dts file that may have something to do with dma channels being allocated -- can anyone interpret this?:
>
> dma@21300 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "fsl,eloplus-dma";
> reg = <0x21300 0x4>;
> ranges = <0x0 0x21100 0x200>;
> cell-index = <0>;
> dma-channel@0 {
> compatible = "fsl,eloplus-dma-channel";
> reg = <0x0 0x80>;
> cell-index = <0>;
> interrupt-parent = <&mpic>;
> interrupts = <20 2>;
> };
> dma-channel@80 {
> compatible = "fsl,eloplus-dma-channel";
> reg = <0x80 0x80>;
> cell-index = <1>;
> interrupt-parent = <&mpic>;
> interrupts = <21 2>;
> };
> dma-channel@100 {
> compatible = "fsl,eloplus-dma-channel";
> reg = <0x100 0x80>;
> cell-index = <2>;
> interrupt-parent = <&mpic>;
> interrupts = <22 2>;
> };
> dma-channel@180 {
> compatible = "fsl,eloplus-dma-channel";
> reg = <0x180 0x80>;
> cell-index = <3>;
> interrupt-parent = <&mpic>;
> interrupts = <23 2>;
> };
> };
>
>
Your DTS file looks fine. It is what I would expect to see. The channels
are not allocated by anything here.
Turning on CONFIG_DMADEVICES_DEBUG may give you some insight into how
the dmaengine core is allocating the channels. I don't have any better
advice. I'm afraid you'll have to figure out who is requesting all of
the channels on your own.
Ira
> --- On Wed, 4/6/11, Ira W. Snyder <iws@ovro.caltech.edu> wrote:
>
> > From: Ira W. Snyder <iws@ovro.caltech.edu>
> > Subject: Re: Using dmaengine on Freescale P2020 RDB
> > To: "Chuck Ketcham" <chuckk2333@yahoo.com>
> > Cc: linuxppc-dev@lists.ozlabs.org
> > Date: Wednesday, April 6, 2011, 1:10 PM
> > On Wed, Apr 06, 2011 at 12:40:58PM
> > -0700, Chuck Ketcham wrote:
> > > All,
> > >
> > > I have a Freescale P2020 Reference Design Board.
> > I am investigating the possibility of using the dmaengine
> > capability in the 2.6.32.13 kernel to transfer data from
> > memory out onto the PCIe bus. As a first step, I
> > thought I would try the DMA test client (dmatest.ko) to make
> > sure the dmaengine was functioning. I know this
> > doesn't transfer anything over PCIe but only transfers from
> > one memory buffer to another, but I figured I need to get
> > this working first. Anyway I built dmatest.ko and ran
> > it (with insmod), and discovered it didn't do
> > anything. I added some printk's to the kernel to
> > investigate what was going on and I found that all attempts
> > to find a channel within dma_request_channel were
> > unsuccessful. Three of the channels were not used
> > because they were already publicly allocated. One
> > channel was not used because it didn't have DMA_MEMCPY
> > capability.
> > >
> > > Here are my questions then:
> > > 1. Is the dmaengine the appropriate method to use for
> > transferring data from memory out onto the PCIe bus?
> > > 2. If dmaengine is correct, what can I do to free up a
> > channel for my own use?
> > >
> >
> > I use the Freescale DMA engine to transfer lots of data out
> > to PCI, on
> > an 8349EA chip. The P2020 DMA engine uses the same driver.
> >
> > I hunch you have enabled CONFIG_NET_DMA, which will claim
> > the channels.
> > You should disable it to use the devices for other uses.
> >
> > If you want an example of using the DMA engine to transfer
> > from DDR
> > memory to the PowerPC local bus, search the mailing list
> > archives for
> > "CARMA Board Drivers" (RFCv7 was the latest posting).
> > Transferring from
> > DDR to PCI works exactly the same way.
> >
> > Hope it helps,
> > Ira
> > _______________________________________________
> > Linuxppc-dev mailing list
> > Linuxppc-dev@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/linuxppc-dev
> >
>
^ permalink raw reply
* Re: [PATCH] POWER: perf_event: Skip updating kernel counters if register value shrinks
From: Eric B Munson @ 2011-04-06 21:27 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: a.p.zijlstra, linux-kernel, paulus, anton, acme, mingo,
linuxppc-dev
In-Reply-To: <1301551476.2407.61.camel@pasglop>
[-- Attachment #1: Type: text/plain, Size: 2241 bytes --]
On Thu, 31 Mar 2011, Benjamin Herrenschmidt wrote:
> On Wed, 2011-03-30 at 14:36 -0400, Eric B Munson wrote:
> > On Wed, 30 Mar 2011, Benjamin Herrenschmidt wrote:
> >
> > > On Tue, 2011-03-29 at 10:25 -0400, Eric B Munson wrote:
> > > > Here I made the assumption that the hardware would never remove more events in
> > > > a speculative roll back than it had added. This is not a situation I
> > > > encoutered in my limited testing, so I didn't think underflow was possible. I
> > > > will send out a V2 using the signed 32 bit delta and remeber to CC stable
> > > > this time.
> > >
> > > I'm not thinking about underflow but rollover... or that isn't possible
> > > with those counters ? IE. They don't wrap back to 0 after hitting
> > > ffffffff ?
> > >
> >
> > They do roll over to 0 after ffffffff, but I thought that case was already
> > covered by the perf_event_interrupt. Are you concerned that we will reset a
> > counter and speculative roll back will underflow that counter?
>
> No, but take this part of the patch:
>
> > --- a/arch/powerpc/kernel/perf_event.c
> > +++ b/arch/powerpc/kernel/perf_event.c
> > @@ -416,6 +416,15 @@ static void power_pmu_read(struct perf_event *event)
> > prev = local64_read(&event->hw.prev_count);
> > barrier();
> > val = read_pmc(event->hw.idx);
> > + /*
> > + * POWER7 can roll back counter values, if the new value is
> > + * smaller than the previous value it will cause the delta
> > + * and the counter to have bogus values. If this is the
> > + * case skip updating anything until the counter grows again.
> > + * This can lead to a small lack of precision in the counters.
> > + */
> > + if (val < prev)
> > + return;
> > } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
>
> Doesn't that mean that power_pmu_read() can only ever increase the value of
> the perf_event and so will essentially -stop- once the counter rolls over ?
>
> Similar comments every where you do this type of comparison.
>
> Cheers,
> Ben.
Sorry for the nag, but am I missing something about the way the register and
the previous values are reset in the overflow interrupt handler?
Thanks,
Eric
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 490 bytes --]
^ permalink raw reply
* Re: known working sata_sil24.c setup on powerpc platforms?
From: Felix Radensky @ 2011-04-06 21:05 UTC (permalink / raw)
To: Leon Woestenberg; +Cc: linuxppc-dev
In-Reply-To: <BANLkTimMatkioUudyaiy+r68=MyrJqiYQg@mail.gmail.com>
Hi Leon,
On 04/06/2011 11:58 PM, Leon Woestenberg wrote:
> Hello Felix,
>
> On Wed, Apr 6, 2011 at 10:49 PM, Felix Radensky<felix@embedded-sol.com> wrote:
>> I think there's a hardware problem with mini PCI-E slot
>> on P2020RDB related to legacy IRQ routing. See this
>> thread for details
>> http://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg40037.html
>>
>
> Unfortunately the PCIe is slot already occupied, so that's why I
> searched for and found the Mini PCIe Sil3132 card.
>
> Legacy IRQ routing on PCIe is broken in what sense? Software (device
> tree, kernel) or silicon (p2020) ?
It's a board design problem specific to P2020RDB. Maybe it's
fixed in latest board revisions. I have P2020RDB rev C and the
problem is still there. Freescale people on the list should know
better.
> On the MSI side, I'm getting quite far on transfers, but at one point
> the device stalls. Maybe a race condition in interrupt handling in
> sata_sil24.c?
Sorry, cannot help you with that. I have no experience with
sata_sil24.
Felix.
^ permalink raw reply
* Re: known working sata_sil24.c setup on powerpc platforms?
From: Leon Woestenberg @ 2011-04-06 20:58 UTC (permalink / raw)
To: Felix Radensky; +Cc: linuxppc-dev
In-Reply-To: <4D9CD1D6.6030600@embedded-sol.com>
Hello Felix,
On Wed, Apr 6, 2011 at 10:49 PM, Felix Radensky <felix@embedded-sol.com> wrote:
> I think there's a hardware problem with mini PCI-E slot
> on P2020RDB related to legacy IRQ routing. See this
> thread for details
> http://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg40037.html
>
Thanks for the heads-up.
> You may have better luck with PCI-E slot and mini PCI-E to
> PCI-E adapter.
>
Unfortunately the PCIe is slot already occupied, so that's why I
searched for and found the Mini PCIe Sil3132 card.
Legacy IRQ routing on PCIe is broken in what sense? Software (device
tree, kernel) or silicon (p2020) ?
On the MSI side, I'm getting quite far on transfers, but at one point
the device stalls. Maybe a race condition in interrupt handling in
sata_sil24.c?
Regards,
--
Leon
^ permalink raw reply
* Re: known working sata_sil24.c setup on powerpc platforms?
From: Felix Radensky @ 2011-04-06 20:49 UTC (permalink / raw)
To: linuxppc-dev, leon.woestenberg
In-Reply-To: <BANLkTinjn5nt4-0cSo6nUfG8Vt1UrL2Q0g@mail.gmail.com>
Hi Leon,
I think there's a hardware problem with mini PCI-E slot
on P2020RDB related to legacy IRQ routing. See this
thread for details
http://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg40037.html
You may have better luck with PCI-E slot and mini PCI-E to
PCI-E adapter.
Felix.
^ permalink raw reply
* Re: Revert 737a3bb9416ce2a7c7a4170852473a4fcc9c67e8 ?
From: Gabriel Paubert @ 2011-04-06 20:43 UTC (permalink / raw)
To: Dave Airlie; +Cc: Greg KH, linuxppc-dev, LKML, Uwe Kleine-König
In-Reply-To: <BANLkTimAJ-s_3A3L1YGfoFLmd4bpu2jWVA@mail.gmail.com>
On Wed, Apr 06, 2011 at 06:46:55PM +1000, Dave Airlie wrote:
> 2011/4/6 Uwe Kleine-König <u.kleine-koenig@pengutronix.de>:
> > Hi Gabriel,
> >
> > On Tue, Apr 05, 2011 at 01:52:59AM +0200, Gabriel Paubert wrote:
> >> I've had the following funny crashes on PPC machines, with
> >> cataleptic X server as a consequence:
> >>
> >> kernel: [drm] Setting GART location based on new memory map
> >> kernel: Oops: Exception in kernel mode, sig: 4 [#1]
> >> kernel: CHRP
> >> kernel: last sysfs file: /sys/devices/pci0001:01/0001:01:08.0/resource
> >> kernel: NIP: c05648fc LR: c0226f58 CTR: 00000008
> >> kernel: REGS: ddb53d20 TRAP: 0700 Not tainted (2.6.38)
> >> kernel: MSR: 00089032 <EE,ME,IR,DR> CR: 48044482 XER: 00000000
> >> kernel: TASK = ddab12b0[3040] 'Xorg' THREAD: ddb52000
> >> kernel: GPR00: c0226f34 ddb53dd0 ddab12b0 00000000 c0509e6c 00000000 00000000 00000000
> >> kernel: GPR08: 00000000 00000000 00000000 00000000 28044488 101f3d8c bf8166b4 00002c00
> >> kernel: GPR16: 101b9458 1006f1a0 101ebe0c 00000001 101ebe08 00000000 df9efc20 df9efc00
> >> kernel: GPR24: c0591e54 80546440 ddacf660 df9efc00 c0506048 c0480210 00a00000 df9ef800
> >> kernel: NIP [c05648fc] platform_device_register_resndata+0x4/0xa4
> >> kernel: LR [c0226f58] radeon_cp_init+0xd08/0x10c4
> >> kernel: Call Trace:
> >> kernel: [ddb53dd0] [c0226f34] radeon_cp_init+0xce4/0x10c4 (unreliable)
> >> kernel: [ddb53df0] [c020801c] drm_ioctl+0x2c0/0x3e4
> >> kernel: [ddb53eb0] [c0091264] do_vfs_ioctl+0x674/0x710
> >> kernel: [ddb53f10] [c0091340] sys_ioctl+0x40/0x70
> >> kernel: [ddb53f40] [c00111a8] ret_from_syscall+0x0/0x38
> >> kernel: --- Exception: c01 at 0xfc54a78
> >> kernel: LR = 0xfc549dc
> >> kernel: Instruction dump:
> >> kernel: 736f2e31 32002f75 73722f6c 69622f6c 6962786b 6c617669 65722e73 6f2e3132
> >> kernel: 006c6962 786b6266 696c652e 736f2e31 <002f7573> 722f6c69 622f6c69 62786b62
> >> kernel: ---[ end trace ed79daba161e31d9 ]---
> >>
> >> As you can see, the processor is trying to execute ASCII strings like
> >> "/usr/lib/libxkb" and has trouble digesting them :-)
> >>
> >> The backtrace is actually missing radeon_cp_init_microcode and radeon_do_init_cp
> >> which are inlined inside radeon_cp_init.
> >>
> >> The trouble is that radeon_cp_init_microcode calls platform_device_register_simple
> >> which is a simple inline wrapper around platform_device_register_resndata, which
> >> happens to be already freed and overwritten with something looking like a list
> >> of filenames, since I have a non modular kernel.
> >>
> >> For now I have locally reverted 737a3bb9416ce2a7c7a4170852473a4fcc9c67e8
> >> which simply added an _init_or_module section attribute to
> >> platform_device_register_resndata, and X is up again...
> >>
> >> Now it may be that it is the ioctl that does not have the right to do
> >> this. Actually I thought that the name radeon_cp that is registered there
> >> would appear somwhere under /sys (or /proc) but failed to find it...
> > I don't know for sure, but it looks strange to me that an ioctl can
> > register a device. But the fear for such code in the kernel made me
> > choose not to squash 737a3bb941 into 44f28bdea094. So my POV is that if
> > the maintainer of the radeon driver thinks registering the device is OK,
> > reverting 737a3bb9416 is fine for me.
>
> This is the old DRM driver for radeon, which relies on userspace to
> start X then calls the kernel
> to initialise the hardware. Due to this model, there is no device we
> can hang off (the PCI device
> might already be bound to fbdev), so we are forced to create a
> platform device to load the firmware.
>
> So its ugly, unless someone can suggest a better device to hang things
> off I don't know of another way.
>
The probem is that, at least on one of my machines, the new driver
does not work: the system hangs (apparently solid, but it's before
networking starts up and I've not yet hooked up a serial console),
after the "radeon: ib pool ready" message.
With the old driver, I've found some combinations of configuration
options that works. They all fail when DRM_RADEON_KMS is enabled.
Gabriel
> Dave.
^ permalink raw reply
* Re: Using dmaengine on Freescale P2020 RDB
From: Chuck Ketcham @ 2011-04-06 20:29 UTC (permalink / raw)
To: Ira W. Snyder; +Cc: linuxppc-dev
In-Reply-To: <20110406201029.GC7312@ovro.caltech.edu>
Ira,=0A=0AThanks for the reference to the CARMA drivers. I will have to ta=
ke a look at that.=0A=0AIn my case, CONFIG_NET_DMA is not enabled. However=
, I did notice the following entry in my p2020rdb.dts file that may have so=
mething to do with dma channels being allocated -- can anyone interpret thi=
s?:=0A=0A dma@21300 {=0A #address-cel=
ls =3D <1>;=0A #size-cells =3D <1>;=0A =
compatible =3D "fsl,eloplus-dma";=0A reg =
=3D <0x21300 0x4>;=0A ranges =3D <0x0 0x21100 0x200>=
;=0A cell-index =3D <0>;=0A d=
ma-channel@0 {=0A compatible =3D "fsl,eloplu=
s-dma-channel";=0A reg =3D <0x0 0x80>;=0A =
cell-index =3D <0>;=0A =
interrupt-parent =3D <&mpic>;=0A int=
errupts =3D <20 2>;=0A };=0A =
dma-channel@80 {=0A compatible =3D "fsl,elop=
lus-dma-channel";=0A reg =3D <0x80 0x80>;=0A=
cell-index =3D <1>;=0A =
interrupt-parent =3D <&mpic>;=0A =
interrupts =3D <21 2>;=0A };=0A =
dma-channel@100 {=0A compatible =3D "fsl,=
eloplus-dma-channel";=0A reg =3D <0x100 0x80=
>;=0A cell-index =3D <2>;=0A =
interrupt-parent =3D <&mpic>;=0A =
interrupts =3D <22 2>;=0A };=0A =
dma-channel@180 {=0A compatible =3D =
"fsl,eloplus-dma-channel";=0A reg =3D <0x180=
0x80>;=0A cell-index =3D <3>;=0A =
interrupt-parent =3D <&mpic>;=0A =
interrupts =3D <23 2>;=0A };=0A =
};=0A=0A=0A=0A--- On Wed, 4/6/11, Ira W. Snyder <iws@ovro.caltech.edu>=
wrote:=0A=0A> From: Ira W. Snyder <iws@ovro.caltech.edu>=0A> Subject: Re: =
Using dmaengine on Freescale P2020 RDB=0A> To: "Chuck Ketcham" <chuckk2333@=
yahoo.com>=0A> Cc: linuxppc-dev@lists.ozlabs.org=0A> Date: Wednesday, April=
6, 2011, 1:10 PM=0A> On Wed, Apr 06, 2011 at 12:40:58PM=0A> -0700, Chuck K=
etcham wrote:=0A> > All,=0A> > =0A> > I have a Freescale P2020 Reference De=
sign Board.=A0=0A> I am investigating the possibility of using the dmaengin=
e=0A> capability in the 2.6.32.13 kernel to transfer data from=0A> memory o=
ut onto the PCIe bus.=A0 As a first step, I=0A> thought I would try the DMA=
test client (dmatest.ko) to make=0A> sure the dmaengine was functioning.=
=A0 I know this=0A> doesn't transfer anything over PCIe but only transfers =
from=0A> one memory buffer to another, but I figured I need to get=0A> this=
working first.=A0 Anyway I built dmatest.ko and ran=0A> it (with insmod), =
and discovered it didn't do=0A> anything.=A0 I added some printk's to the k=
ernel to=0A> investigate what was going on and I found that all attempts=0A=
> to find a channel within dma_request_channel were=0A> unsuccessful.=A0 Th=
ree of the channels were not used=0A> because they were already publicly al=
located.=A0 One=0A> channel was not used because it didn't have DMA_MEMCPY=
=0A> capability.=0A> > =0A> > Here are my questions then:=0A> > 1. Is the d=
maengine the appropriate method to use for=0A> transferring data from memor=
y out onto the PCIe bus?=0A> > 2. If dmaengine is correct, what can I do to=
free up a=0A> channel for my own use?=0A> > =0A> =0A> I use the Freescale =
DMA engine to transfer lots of data out=0A> to PCI, on=0A> an 8349EA chip. =
The P2020 DMA engine uses the same driver.=0A> =0A> I hunch you have enable=
d CONFIG_NET_DMA, which will claim=0A> the channels.=0A> You should disable=
it to use the devices for other uses.=0A> =0A> If you want an example of u=
sing the DMA engine to transfer=0A> from DDR=0A> memory to the PowerPC loca=
l bus, search the mailing list=0A> archives for=0A> "CARMA Board Drivers" (=
RFCv7 was the latest posting).=0A> Transferring from=0A> DDR to PCI works e=
xactly the same way.=0A> =0A> Hope it helps,=0A> Ira=0A> __________________=
_____________________________=0A> Linuxppc-dev mailing list=0A> Linuxppc-de=
v@lists.ozlabs.org=0A> https://lists.ozlabs.org/listinfo/linuxppc-dev=0A>
^ permalink raw reply
* Re: Using dmaengine on Freescale P2020 RDB
From: Ira W. Snyder @ 2011-04-06 20:10 UTC (permalink / raw)
To: Chuck Ketcham; +Cc: linuxppc-dev
In-Reply-To: <327152.93855.qm@web36406.mail.mud.yahoo.com>
On Wed, Apr 06, 2011 at 12:40:58PM -0700, Chuck Ketcham wrote:
> All,
>
> I have a Freescale P2020 Reference Design Board. I am investigating the possibility of using the dmaengine capability in the 2.6.32.13 kernel to transfer data from memory out onto the PCIe bus. As a first step, I thought I would try the DMA test client (dmatest.ko) to make sure the dmaengine was functioning. I know this doesn't transfer anything over PCIe but only transfers from one memory buffer to another, but I figured I need to get this working first. Anyway I built dmatest.ko and ran it (with insmod), and discovered it didn't do anything. I added some printk's to the kernel to investigate what was going on and I found that all attempts to find a channel within dma_request_channel were unsuccessful. Three of the channels were not used because they were already publicly allocated. One channel was not used because it didn't have DMA_MEMCPY capability.
>
> Here are my questions then:
> 1. Is the dmaengine the appropriate method to use for transferring data from memory out onto the PCIe bus?
> 2. If dmaengine is correct, what can I do to free up a channel for my own use?
>
I use the Freescale DMA engine to transfer lots of data out to PCI, on
an 8349EA chip. The P2020 DMA engine uses the same driver.
I hunch you have enabled CONFIG_NET_DMA, which will claim the channels.
You should disable it to use the devices for other uses.
If you want an example of using the DMA engine to transfer from DDR
memory to the PowerPC local bus, search the mailing list archives for
"CARMA Board Drivers" (RFCv7 was the latest posting). Transferring from
DDR to PCI works exactly the same way.
Hope it helps,
Ira
^ permalink raw reply
* Using dmaengine on Freescale P2020 RDB
From: Chuck Ketcham @ 2011-04-06 19:40 UTC (permalink / raw)
To: linuxppc-dev
All,
I have a Freescale P2020 Reference Design Board. I am investigating the possibility of using the dmaengine capability in the 2.6.32.13 kernel to transfer data from memory out onto the PCIe bus. As a first step, I thought I would try the DMA test client (dmatest.ko) to make sure the dmaengine was functioning. I know this doesn't transfer anything over PCIe but only transfers from one memory buffer to another, but I figured I need to get this working first. Anyway I built dmatest.ko and ran it (with insmod), and discovered it didn't do anything. I added some printk's to the kernel to investigate what was going on and I found that all attempts to find a channel within dma_request_channel were unsuccessful. Three of the channels were not used because they were already publicly allocated. One channel was not used because it didn't have DMA_MEMCPY capability.
Here are my questions then:
1. Is the dmaengine the appropriate method to use for transferring data from memory out onto the PCIe bus?
2. If dmaengine is correct, what can I do to free up a channel for my own use?
Thank you.
Chuck
^ permalink raw reply
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