* [PATCH] lib: Consolidate DEBUG_PER_CPU_MAPS
From: Stephen Boyd @ 2011-04-07 19:20 UTC (permalink / raw)
To: Andrew Morton; +Cc: linux-arch, x86, linuxppc-dev, linux-kernel
DEBUG_PER_CPU_MAPS is used in lib/cpumask.c as well as in
inlcude/linux/cpumask.h and thus it has outgrown its use within x86
and powerpc alone. Any arch with SMP support may want to get some
more debugging, so make this option generic.
Cc: linux-arch@vger.kernel.org
Cc: x86@kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
I don't know what tree to send this through, so I'm sending it to
Andrew. I suppose mm is as good as anything.
arch/powerpc/Kconfig.debug | 12 ------------
arch/x86/Kconfig.debug | 11 -----------
lib/Kconfig.debug | 11 +++++++++++
3 files changed, 11 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 2d38a50..12a8d18 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -44,18 +44,6 @@ config DEBUG_STACK_USAGE
This option will slow down process creation somewhat.
-config DEBUG_PER_CPU_MAPS
- bool "Debug access to per_cpu maps"
- depends on DEBUG_KERNEL
- depends on SMP
- default n
- ---help---
- Say Y to verify that the per_cpu map being accessed has
- been setup. Adds a fair amount of code to kernel memory
- and decreases performance.
-
- Say N if unsure.
-
config HCALL_STATS
bool "Hypervisor call instrumentation"
depends on PPC_PSERIES && DEBUG_FS && TRACEPOINTS
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index 615e188..1bf8839 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -75,17 +75,6 @@ config DEBUG_STACK_USAGE
This option will slow down process creation somewhat.
-config DEBUG_PER_CPU_MAPS
- bool "Debug access to per_cpu maps"
- depends on DEBUG_KERNEL
- depends on SMP
- ---help---
- Say Y to verify that the per_cpu map being accessed has
- been setup. Adds a fair amount of code to kernel memory
- and decreases performance.
-
- Say N if unsure.
-
config X86_PTDUMP
bool "Export kernel pagetable layout to userspace via debugfs"
depends on DEBUG_KERNEL
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index c768bcd..c792431 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -993,6 +993,17 @@ config DEBUG_FORCE_WEAK_PER_CPU
To ensure that generic code follows the above rules, this
option forces all percpu variables to be defined as weak.
+config DEBUG_PER_CPU_MAPS
+ bool "Debug access to per_cpu maps"
+ depends on DEBUG_KERNEL
+ depends on SMP
+ help
+ Say Y to verify that the per_cpu map being accessed has
+ been set up. This adds a fair amount of code to kernel memory
+ and decreases performance.
+
+ Say N if unsure.
+
config LKDTM
tristate "Linux Kernel Dump Test Tool Module"
depends on DEBUG_FS
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
^ permalink raw reply related
* Re: [PATCH] drivers: char: hvc: add arm JTAG DCC console support
From: Mike Frysinger @ 2011-04-07 18:57 UTC (permalink / raw)
To: RONETIX - Asen Dimov
Cc: Randy Dunlap, Daniel Walker, Arnd Bergmann, Nicolas Pitre,
Tony Lindgren, linux-arm-msm, Greg Kroah-Hartman, linux-kernel,
FUJITA Tomonori, Andrew Morton, linuxppc-dev, Alan Cox
In-Reply-To: <4D9E04F0.5010004@ronetix.at>
On Thu, Apr 7, 2011 at 14:39, RONETIX - Asen Dimov wrote:
> On 11/30/2010 09:25 PM, Daniel Walker wrote:
>> This driver adds a basic console that uses the arm JTAG
>> DCC to transfer data back and forth. It has support for
>> ARMv6 and ARMv7.
>>
>> This console is created under the HVC driver, and should be named
>> /dev/hvcX (or /dev/hvc0 for example).
>>
>> =C2=A0drivers/char/Kconfig =C2=A0 | =C2=A0 =C2=A09 +++
>> =C2=A0drivers/char/Makefile =C2=A0| =C2=A0 =C2=A01 +
>> =C2=A0drivers/char/hvc_dcc.c | =C2=A0133
>> ++++++++++++++++++++++++++++++++++++++++++++++++
>
> ...
>
> this DCC driver implements "one channel", but what about implementing
> "multiple channels". For example reserve few(3) bits for channel number,
> and two bits for carried data, then fill the rest bytes with with some da=
ta
> and send the word(32 bits) over DCC. On the Linux side writing on /dev/hv=
cX
> puts the number X as channel number, and on the other side the CPU
> emulator gets the data and redistribute it to TCP/IP socket.
>
> I have started write some code implementing this. Are there any one
> interested
> in this multiple channels, and are there any one started to work on it?
this sort of multiplexing of the data stream sounds like the job for
userspace ? or maybe a line discipline ? inserting structured data
into the kernel driver doesnt sound right to me ...
-mike
^ permalink raw reply
* Re: [PATCH] drivers: char: hvc: add arm JTAG DCC console support
From: RONETIX - Asen Dimov @ 2011-04-07 18:39 UTC (permalink / raw)
To: Daniel Walker
Cc: Randy Dunlap, Mike Frysinger, Arnd Bergmann, Nicolas Pitre,
Tony Lindgren, linux-arm-msm, Greg Kroah-Hartman, linux-kernel,
FUJITA Tomonori, Andrew Morton, linuxppc-dev, Alan Cox
In-Reply-To: <1291145141-18301-1-git-send-email-dwalker@codeaurora.org>
Hello,
On 11/30/2010 09:25 PM, Daniel Walker wrote:
> This driver adds a basic console that uses the arm JTAG
> DCC to transfer data back and forth. It has support for
> ARMv6 and ARMv7.
>
> This console is created under the HVC driver, and should be named
> /dev/hvcX (or /dev/hvc0 for example).
>
> Cc: Tony Lindgren<tony@atomide.com>
> Cc: Arnd Bergmann<arnd@arndb.de>
> Cc: Nicolas Pitre<nico@fluxnic.net>
> Cc: Greg Kroah-Hartman<gregkh@suse.de>
> Cc: Mike Frysinger<vapier@gentoo.org>
> Signed-off-by: Daniel Walker<dwalker@codeaurora.org>
> ---
> drivers/char/Kconfig | 9 +++
> drivers/char/Makefile | 1 +
> drivers/char/hvc_dcc.c | 133 ++++++++++++++++++++++++++++++++++++++++++++++++
...
this DCC driver implements "one channel", but what about implementing
"multiple channels". For example reserve few(3) bits for channel number,
and two bits for carried data, then fill the rest bytes with with some data
and send the word(32 bits) over DCC. On the Linux side writing on /dev/hvcX
puts the number X as channel number, and on the other side the CPU
emulator gets the data and redistribute it to TCP/IP socket.
I have started write some code implementing this. Are there any one
interested
in this multiple channels, and are there any one started to work on it?
Regards,
Asen
^ permalink raw reply
* Re: [PATCH] rtas: Only sleep in rtas_busy_delay if we have useful work to do
From: Nishanth Aravamudan @ 2011-04-07 18:11 UTC (permalink / raw)
To: Anton Blanchard; +Cc: paulus, linuxppc-dev, miltonm
In-Reply-To: <20110407215407.4f6ca50f@kryten>
On 07.04.2011 [21:54:07 +1000], Anton Blanchard wrote:
>
> RTAS returns extended error codes as a hint of how long the
> OS might want to wait before retrying a call. If we have nothing
> else useful to do we may as well call back straight away.
>
> This was found when testing the new dynamic dma window feature.
> Firmware split the zeroing of the TCE table into 32k chunks but
> returned 9901 (which is a suggested wait of 10ms). All up this took
> about 10 minutes to complete since msleep is jiffies based and will
> round 10ms up to 20ms.
>
> With the patch below we take 3 seconds to complete the same test.
> The hint firmware is returning in the RTAS call should definitely
> be decreased, but even if we slept 1ms each iteration this would
> take 32s.
>
> Signed-off-by: Anton Blanchard <anton@samba.org>
Acked-by: Nishanth Aravamudan <nacc@us.ibm.com>
> ---
>
> Index: linux-2.6/arch/powerpc/kernel/rtas.c
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/kernel/rtas.c 2011-04-05 11:19:35.023234011 +1000
> +++ linux-2.6/arch/powerpc/kernel/rtas.c 2011-04-07 21:25:24.646414629 +1000
> @@ -494,7 +494,7 @@ unsigned int rtas_busy_delay(int status)
>
> might_sleep();
> ms = rtas_busy_delay_time(status);
> - if (ms)
> + if (ms && need_resched())
> msleep(ms);
>
> return ms;
^ permalink raw reply
* Re: Problem with mini-PCI-E slot on P2020RDB
From: Leon Woestenberg @ 2011-04-07 17:20 UTC (permalink / raw)
To: linuxppc-dev
Cc: Mahajan Vivek-B08308, Felix Radensky, Aggrwal Poonam-B10812,
Kushwaha Prabhakar-B32579
In-Reply-To: <4B2A946E.4040907@embedded-sol.com>
Hello,
On Thu, Dec 17, 2009 at 9:28 PM, Felix Radensky <felix@embedded-sol.com> wr=
ote:
> Kumar Gala wrote:
>> On Dec 17, 2009, at 2:59 AM, Mahajan Vivek-B08308 wrote:
>>>> Thanks a lot. If I understand you correctly, the only way I can get
>>>> ath9k driver to work on this board using legacy interrupts is to wait =
for a
>>>> hardware fix. Right ?
>>>>
>>> Correct
>>
>> I'm confused. =A0What's the issue with IRQ0 on the P2020RDB? =A0Is it us=
ed for
>> another purpose?
>
> There's a problem with IRQ0 with respect to mini-PCI-E slot. I have Ather=
os
> wireless card plugged
> into it. ath9k wireless driver for this card uses legacy PCI-E interrupts=
,
> and I get "irq 16: nobody cared"
> message when driver executes request_irq(). Vivek has come to a conclusio=
n
> that the problem is
> related to incorrect IRQ0 routing for mini-PCI-E slot on P2020RDB.
>
I would like to understand this issue better, as I seem to be running
into something similar, and it puts my board design on hold.
Can someone (from Freescale) explain what happens if a PCI Express end
point on the mini-PCIe slot raises a legacy interrupt, and where this
goes wrong?
>From what document or source code file can I conclude that the PCIe
legacy interrupt is shared with IRQ0?
I found this:
P1020E/P2020E RDB System Errata, Last Update: 2/15/2010:
Problem:IRQ0 held low
Fix: Add 4.7K pull-up (to 3.3.V) for RTC_INT_N.
See R420 in Rev D schematic.
Add 4.7K pull-up (to 3.3.V) for MCU_INT_N.
See R423 in Rev D schematic.
Regards,
--=20
Leon
^ permalink raw reply
* Re: halt/reset on assert?
From: kevin diggs @ 2011-04-07 17:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Andreas Schwab, linuxppc-dev, Evan Lavelle
In-Reply-To: <1302162933.2458.33.camel@pasglop>
On Thu, Apr 7, 2011 at 2:55 AM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Wed, 2011-04-06 at 14:01 +0100, Evan Lavelle wrote:
>> #define MY_ASSERT(expr) if(!(expr)) BUG()
>
> Make it
>
> #define MY_ASSERT(expr) do { if .... } while(0)
>
> To ensure it has proper single statement semantics in C.
>
So THAT'S why they do this!!!!!! Now I just have to figure out what
'proper single statement semantics' means!
THANKS!!!
kevin
> Cheers,
> Ben.
^ permalink raw reply
* Re: known working sata_sil24.c setup on powerpc platforms?
From: Leon Woestenberg @ 2011-04-07 16:54 UTC (permalink / raw)
To: Martyn Welch; +Cc: linuxppc-dev
In-Reply-To: <4D9D7575.1030200@ge.com>
Hello Martyn,
thanks for a confirmation.
On Thu, Apr 7, 2011 at 10:27 AM, Martyn Welch <martyn.welch@ge.com> wrote:
> On 06/04/11 18:00, Leon Woestenberg wrote:
>>
>> Does anyone know of a working setup of sata_sil24 on a big endian
>> powerpc system?
>
> Yes, I think we even use it on a p2020 board, though I think our current
> kernel on that product is 2.6.34.
>
Could you check if that's using MSI or legacy interrupting on PCIe?
Thanks in advance for the effort,
Regards,
--
Leon
^ permalink raw reply
* [PATCH V3] POWER: perf_event: Skip updating kernel counters if register value shrinks
From: Eric B Munson @ 2011-04-07 16:52 UTC (permalink / raw)
To: benh
Cc: a.p.zijlstra, linux-kernel, paulus, anton, acme, mingo,
linuxppc-dev, stable, Eric B Munson
Because of speculative event roll back, it is possible for some event coutners
to decrease between reads on POWER7. This causes a problem with the way that
counters are updated. Delta calues are calculated in a 64 bit value and the
top 32 bits are masked. If the register value has decreased, this leaves us
with a very large positive value added to the kernel counters. This patch
protects against this by skipping the update if the delta would be negative.
This can lead to a lack of precision in the coutner values, but from my testing
the value is typcially fewer than 10 samples at a time.
Signed-off-by: Eric B Munson <emunson@mgebm.net>
Cc: stable@kernel.org
---
Changes from V2:
Create a helper that should handle counter roll back as well as registers that
might be allowed to roll over
Changes from V1:
Updated patch leader
Added stable CC
Use an s32 to hold delta values and discard any values that are less than 0
arch/powerpc/kernel/perf_event.c | 40 +++++++++++++++++++++++++++++++------
1 files changed, 33 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 97e0ae4..78bf933 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -398,6 +398,28 @@ static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
return 0;
}
+static u64 check_and_compute_delta(s64 prev, s64 val)
+{
+ /*
+ * Because the PerfMon registers are only 32 bits wide, the delta
+ * should not overflow.
+ */
+ u64 delta = 0;
+
+ /*
+ * POWER7 can roll back counter values, if the new value is smaller
+ * than the previous value it will cause the delta and the counter to
+ * have bogus values unless we rolled a counter over. If this is the
+ * case or prev < val, calculate the delta nd return it, otherwise
+ * return 0. This can lead to a small lack of precision in the
+ * counters.
+ */
+ if (((prev & 0x80000000) && !(val & 0x80000000)) || (val > prev))
+ delta = (val - prev) & 0xfffffffful;
+
+ return delta;
+}
+
static void power_pmu_read(struct perf_event *event)
{
s64 val, delta, prev;
@@ -416,10 +438,11 @@ static void power_pmu_read(struct perf_event *event)
prev = local64_read(&event->hw.prev_count);
barrier();
val = read_pmc(event->hw.idx);
+ delta = check_and_compute_delta(prev, val);
+ if (!delta)
+ return;
} while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
- /* The counters are only 32 bits wide */
- delta = (val - prev) & 0xfffffffful;
local64_add(delta, &event->count);
local64_sub(delta, &event->hw.period_left);
}
@@ -449,8 +472,9 @@ static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
val = (event->hw.idx == 5) ? pmc5 : pmc6;
prev = local64_read(&event->hw.prev_count);
event->hw.idx = 0;
- delta = (val - prev) & 0xfffffffful;
- local64_add(delta, &event->count);
+ delta = check_and_compute_delta(prev, val);
+ if (delta)
+ local64_add(delta, &event->count);
}
}
@@ -458,14 +482,16 @@ static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
unsigned long pmc5, unsigned long pmc6)
{
struct perf_event *event;
- u64 val;
+ u64 val, prev;
int i;
for (i = 0; i < cpuhw->n_limited; ++i) {
event = cpuhw->limited_counter[i];
event->hw.idx = cpuhw->limited_hwidx[i];
val = (event->hw.idx == 5) ? pmc5 : pmc6;
- local64_set(&event->hw.prev_count, val);
+ prev = local64_read(&event->hw.prev_count);
+ if (check_and_compute_delta(prev, val))
+ local64_set(&event->hw.prev_count, val);
perf_event_update_userpage(event);
}
}
@@ -1197,7 +1223,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
/* we don't have to worry about interrupts here */
prev = local64_read(&event->hw.prev_count);
- delta = (val - prev) & 0xfffffffful;
+ delta = check_and_compute_delta(prev, val);
local64_add(delta, &event->count);
/*
--
1.7.1
^ permalink raw reply related
* Re: known working sata_sil24.c setup on powerpc platforms?
From: Leon Woestenberg @ 2011-04-07 16:52 UTC (permalink / raw)
To: Kushwaha Prabhakar-B32579
Cc: Linux PPC, Tejun Heo, Jeff Garzik, Moffett, Kyle D,
linux-ide@vger.kernel.org
In-Reply-To: <071A08F2C6A57E4E94D980ECA553F87416BDD0@039-SN1MPN1-004.039d.mgd.msft.net>
Hello Prabhakar,
thanks for your response. My answer below:
On Thu, Apr 7, 2011 at 6:48 AM, Kushwaha Prabhakar-B32579
<B32579@freescale.com> wrote:
> Hi Leon,
>
> Can you please check p2020rdb.dts for IDSEL entries for pci0/1 node?
>
> In order to work in legacy mode, IDSEL entries are required.
>
No, the p1020rdb and p2020rdb do not have the IDSEL entries:
http://lxr.linux.no/#linux+v2.6.38/arch/powerpc/boot/dts/p2020rdb.dts
whereas the p2020ds has:
http://lxr.linux.no/#linux+v2.6.38/arch/powerpc/boot/dts/p2020ds.dts
What would the correct IDSEL entries be?
Also, did you see the reference to Felix' thread?
"Problem with mini-PCI-E slot on P2020RDB"
Best regards,
Leon.
> --Prabhakar
>
>> -----Original Message-----
>> From: linux-ide-owner@vger.kernel.org [mailto:linux-ide-
>> owner@vger.kernel.org] On Behalf Of Leon Woestenberg
>> Sent: Thursday, April 07, 2011 12:20 AM
>> To: Jeff Garzik
>> Cc: Moffett, Kyle D; Linux PPC; linux-ide@vger.kernel.org; Tejun Heo
>> Subject: Re: known working sata_sil24.c setup on powerpc platforms?
>>
>> Hello Jeff, all,
>>
>> On Wed, Apr 6, 2011 at 8:12 PM, Jeff Garzik <jeff@garzik.org> wrote:
>> > On 04/06/2011 01:48 PM, Moffett, Kyle D wrote:
>> >> On Apr 06, 2011, at 13:00, Leon Woestenberg wrote:
>> >>> after investigating problems with sata_sil24.c on a freescale p2020
>> >>> soc, I wonder if this driver works on powerpc at all?
>> >>>
>> >>> Does anyone know of a working setup of sata_sil24 on a big endian
>> >>> powerpc system?
>> >>
>> >> Our P2020 boards work fine with legacy PCI interrupts (I think it's a
>> >> sil3124 over PCI-E); the only deficiency is that MSI does not seem to
>> work.
>> >>
>> >
>> > We've definitely had issues with sata_sil24 + MSI, also...
>> >
>> > sata_sil24 does work on big endian in general.
>> >
>>
>> On my system, I have the contrary to Kyle's experience (thanks for
>> sharing).
>>
>> PowerPC P2020RDB
>> vanilla 2.6.38
>> Sil3132 on mini-PCI Express card
>>
>>
>> Enabling msi gets me further than disabling it (default).
>>
>> modprobe sata_sil
>>
>> [ =A0 =A08.834613] sata_sil24 0001:03:00.0: version 1.1
>> [ =A0 =A08.885581] scsi0 : sata_sil24
>> [ =A0 =A08.901420] scsi1 : sata_sil24
>> [ =A0 =A08.904642] ata1: SATA max UDMA/100 host m128@0xc0000000 port
>> 0xc0004000 irq 16
>> [ =A0 =A08.911961] ata2: SATA max UDMA/100 host m128@0xc0000000 port
>> 0xc0006000 irq 16
>> [ =A0 11.095127] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
>> [ =A0 14.906986] eth0: no IPv6 routers present
>> [ =A0 16.099016] ata1.00: qc timeout (cmd 0xec)
>> [ =A0 16.103128] ata1.00: failed to IDENTIFY (I/O error, err_mask=3D0x4)
>> [ =A0 18.299050] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
>> [ =A0 28.303026] ata1.00: qc timeout (cmd 0xec)
>> [ =A0 28.307139] ata1.00: failed to IDENTIFY (I/O error, err_mask=3D0x4)
>> [ =A0 28.313233] ata1: limiting SATA link speed to 1.5 Gbps
>> [ =A0 30.523059] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 10)
>>
>>
>> modprobe sata_sil msi=3D1
>>
>> [ =A0 92.984120] sata_sil24 0001:03:00.0: version 1.1
>> [ =A0 92.988897] irq: irq 0 on host /soc@ffe00000/msi@41600 mapped to
>> virtual irq 41
>> [ =A0 92.996229] sata_sil24 0001:03:00.0: Using MSI
>> [ =A0 93.000675] sata_sil24 0001:03:00.0: enabling bus mastering
>> [ =A0 93.011628] scsi2 : sata_sil24
>> [ =A0 93.022463] scsi3 : sata_sil24
>> [ =A0 93.025695] ata3: SATA max UDMA/100 host m128@0xc0000000 port
>> 0xc0004000 irq 41
>> [ =A0 93.033023] ata4: SATA max UDMA/100 host m128@0xc0000000 port
>> 0xc0006000 irq 41
>> [ =A0 95.203029] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
>> [ =A0 95.209045] ata3: spurious interrupt (slot_stat 0x0 active_tag
>> -84148995 sactive 0x0)
>> [ =A0 95.217171] ata3.00: ATA-7: INTEL SSDSA2M080G2GN, 2CV102HD, max
>> UDMA/133
>> [ =A0 95.223882] ata3.00: 156301488 sectors, multi 1: LBA48 NCQ (depth
>> 31/32)
>> [ =A0 95.230905] ata3.00: configured for UDMA/100
>> [ =A0 95.235399] scsi 2:0:0:0: Direct-Access =A0 =A0 ATA =A0 =A0 =A0INTE=
L
>> SSDSA2M080 2CV1 PQ: 0 ANSI: 5
>> [ =A0 95.244002] sd 2:0:0:0: Attached scsi generic sg0 type 0
>> [ =A0 95.252041] sd 2:0:0:0: [sda] 156301488 512-byte logical blocks:
>> (80.0 GB/74.5 GiB)
>> [ =A0 95.260219] sd 2:0:0:0: [sda] Write Protect is off
>> [ =A0 95.265063] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00
>> [ =A0 95.270500] sd 2:0:0:0: [sda] Write cache: enabled, read cache:
>> enabled, doesn't support DPO or FUA
>> [ =A0 95.283779] =A0sda: sda1 sda2 sda3 sda4
>> [ =A0 95.289482] sd 2:0:0:0: [sda] Attached SCSI disk
>> [ =A0 95.965897] EXT3-fs: barriers not enabled
>> [ =A0 95.977279] kjournald starting. =A0Commit interval 5 seconds
>> [ =A0 95.983296] EXT3-fs (sda2): using internal journal
>> [ =A0 95.988143] EXT3-fs (sda2): recovery complete
>> [ =A0 95.992504] EXT3-fs (sda2): mounted filesystem with writeback data
>> mode
>> [ =A0 96.111587] NTFS volume version 3.1.
>> [ =A0 97.331005] ata4: SATA link down (SStatus 0 SControl 0)
>>
>> root@p1020rdb:~# dd if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D1000
>> 1000+0 records in
>> 1000+0 records out
>> 4096000 bytes (4.1 MB) copied, 0.0315629 s, 130 MB/s root@p1020rdb:~# dd
>> if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D10000
>> 10000+0 records in
>> 10000+0 records out
>> 40960000 bytes (41 MB) copied, 0.471802 s, 86.8 MB/s
>>
>> root@p1020rdb:~# dd if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D100000
>>
>> That stalls, I see the controller fail. See dmesg below:
>>
>> ^C^Cdd: reading `/dev/sda': Input/output error
>> 51804+0 records in
>> 51804+0 records out
>> 212189184 bytes (212 MB) copied, 85.6537 s, 2.5 MB/s
>> dd: closing input file `/dev/sda': Bad file descriptor
>>
>>
>> [ =A0 92.984120] sata_sil24 0001:03:00.0: version 1.1
>> [ =A0 92.988897] irq: irq 0 on host /soc@ffe00000/msi@41600 mapped to
>> virtual irq 41
>> [ =A0 92.996229] sata_sil24 0001:03:00.0: Using MSI
>> [ =A0 93.000675] sata_sil24 0001:03:00.0: enabling bus mastering
>> [ =A0 93.011628] scsi2 : sata_sil24
>> [ =A0 93.022463] scsi3 : sata_sil24
>> [ =A0 93.025695] ata3: SATA max UDMA/100 host m128@0xc0000000 port
>> 0xc0004000 irq 41
>> [ =A0 93.033023] ata4: SATA max UDMA/100 host m128@0xc0000000 port
>> 0xc0006000 irq 41
>> [ =A0 95.203029] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
>> [ =A0 95.209045] ata3: spurious interrupt (slot_stat 0x0 active_tag
>> -84148995 sactive 0x0)
>> [ =A0 95.217171] ata3.00: ATA-7: INTEL SSDSA2M080G2GN, 2CV102HD, max
>> UDMA/133
>> [ =A0 95.223882] ata3.00: 156301488 sectors, multi 1: LBA48 NCQ (depth
>> 31/32)
>> [ =A0 95.230905] ata3.00: configured for UDMA/100
>> [ =A0 95.235399] scsi 2:0:0:0: Direct-Access =A0 =A0 ATA =A0 =A0 =A0INTE=
L
>> SSDSA2M080 2CV1 PQ: 0 ANSI: 5
>> [ =A0 95.244002] sd 2:0:0:0: Attached scsi generic sg0 type 0
>> [ =A0 95.252041] sd 2:0:0:0: [sda] 156301488 512-byte logical blocks:
>> (80.0 GB/74.5 GiB)
>> [ =A0 95.260219] sd 2:0:0:0: [sda] Write Protect is off
>> [ =A0 95.265063] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00
>> [ =A0 95.270500] sd 2:0:0:0: [sda] Write cache: enabled, read cache:
>> enabled, doesn't support DPO or FUA
>> [ =A0 95.283779] =A0sda: sda1 sda2 sda3 sda4
>> [ =A0 95.289482] sd 2:0:0:0: [sda] Attached SCSI disk
>> [ =A0 95.965897] EXT3-fs: barriers not enabled
>> [ =A0 95.977279] kjournald starting. =A0Commit interval 5 seconds
>> [ =A0 95.983296] EXT3-fs (sda2): using internal journal
>> [ =A0 95.988143] EXT3-fs (sda2): recovery complete
>> [ =A0 95.992504] EXT3-fs (sda2): mounted filesystem with writeback data
>> mode
>> [ =A0 96.111587] NTFS volume version 3.1.
>> [ =A0 97.331005] ata4: SATA link down (SStatus 0 SControl 0)
>> [ =A0285.891036] ata3.00: exception Emask 0x0 SAct 0x3 SErr 0x0 action 0=
x6
>> frozen [ =A0285.898099] ata3.00: failed command: READ FPDMA QUEUED [
>> 285.903250] ata3.00: cmd 60/00:00:e0:53:06/01:00:00:00:00/40 tag 0 ncq
>> 131072 in
>> [ =A0285.903255] =A0 =A0 =A0 =A0 =A0res 40/00:00:00:00:00/00:00:00:00:00=
/00 Emask
>> 0x4 (timeout)
>> [ =A0285.918028] ata3.00: status: { DRDY } [ =A0285.921689] ata3.00: fai=
led
>> command: READ FPDMA QUEUED [ =A0285.926836] ata3.00: cmd
>> 60/00:08:e0:52:06/01:00:00:00:00/40 tag 1 ncq 131072 in
>> [ =A0285.926841] =A0 =A0 =A0 =A0 =A0res 40/00:00:00:00:00/00:00:00:00:00=
/00 Emask
>> 0x4 (timeout)
>> [ =A0285.941615] ata3.00: status: { DRDY } [ =A0285.945281] ata3: hard
>> resetting link [ =A0288.055034] ata3: SATA link up 3.0 Gbps (SStatus 123
>> SControl 0) [ =A0293.058999] ata3.00: qc timeout (cmd 0xec) [ =A0293.063=
106]
>> ata3.00: failed to IDENTIFY (I/O error, err_mask=3D0x4) [ =A0293.069198]
>> ata3.00: revalidation failed (errno=3D-5) [ =A0293.074077] ata3: hard
>> resetting link [ =A0295.259018] ata3: SATA link up 3.0 Gbps (SStatus 123
>> SControl 0)
>>
>> What can I do next to investigate and help fix this issue?
>>
>>
>> Regards,
>> --
>> Leon
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-ide" in
>> the body of a message to majordomo@vger.kernel.org More majordomo info a=
t
>> http://vger.kernel.org/majordomo-info.html
>
>
>
--=20
Leon
^ permalink raw reply
* Re: [PATCH] POWER: perf_event: Skip updating kernel counters if register value shrinks
From: Eric B Munson @ 2011-04-07 16:16 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: a.p.zijlstra, linux-kernel, paulus, anton, acme, mingo,
linuxppc-dev
In-Reply-To: <1302150177.2458.30.camel@pasglop>
[-- Attachment #1: Type: text/plain, Size: 1147 bytes --]
On Thu, 07 Apr 2011, Benjamin Herrenschmidt wrote:
>
> > > Doesn't that mean that power_pmu_read() can only ever increase the value of
> > > the perf_event and so will essentially -stop- once the counter rolls over ?
> > >
> > > Similar comments every where you do this type of comparison.
> > >
> > > Cheers,
> > > Ben.
> >
> > Sorry for the nag, but am I missing something about the way the register and
> > the previous values are reset in the overflow interrupt handler?
>
> Well, not all counters get interrupts right ? Some counters are just
> free running... I'm not sure when that power_pmu_read() function is
> actually used by the core, I'm not that familiar with perf, but I'd say
> better safe than sorry. When comparing counter values, doing in a way
> that is generally safe vs. wraparounds. Eventually do a helper for that.
>
> Cheers,
> Ben.
I am honestly not sure, I was under the assumption that all counters would
generate an interrupt if they overflowed. I do not have the hardware docs to
prove this, so I will have a V3 that (I think/hope) addresses your concerns out
momentarily.
Eric
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 490 bytes --]
^ permalink raw reply
* Re: [PATCH][v2] powerpc/85xx: P1020 DTS : re-organize dts files
From: Grant Likely @ 2011-04-07 14:29 UTC (permalink / raw)
To: Prabhakar Kushwaha
Cc: meet2prabhu, devicetree-discuss, linuxppc-dev, kumar.gala
In-Reply-To: <1302167455-21538-1-git-send-email-prabhakar@freescale.com>
On Thu, Apr 07, 2011 at 02:40:55PM +0530, Prabhakar Kushwaha wrote:
> Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
> files for P1020 based systems to use dtsi file
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Acked-by: Kumar Gala <kumar.gala@freescale.com>
Looks good to me.
Acked-by: Grant Likely <grant.likelY@secretlab.ca>
g.
> ---
> Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master)
>
> Please see mpc5200b.dtsi for reference.
>
> Tested on P1020RDB
>
> Changes for v2: Incorporated Grant Likely's comment
> -updated model name
>
> arch/powerpc/boot/dts/p1020rdb.dts | 316 +------------------------------
> arch/powerpc/boot/dts/p1020si.dtsi | 377 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 380 insertions(+), 313 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
>
> diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
> index e0668f8..7ed4793 100644
> --- a/arch/powerpc/boot/dts/p1020rdb.dts
> +++ b/arch/powerpc/boot/dts/p1020rdb.dts
> @@ -9,12 +9,11 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "p1020si.dtsi"
> +
> / {
> - model = "fsl,P1020";
> + model = "fsl,P1020RDB";
> compatible = "fsl,P1020RDB";
> - #address-cells = <2>;
> - #size-cells = <2>;
>
> aliases {
> serial0 = &serial0;
> @@ -26,34 +25,11 @@
> pci1 = &pci1;
> };
>
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,P1020@0 {
> - device_type = "cpu";
> - reg = <0x0>;
> - next-level-cache = <&L2>;
> - };
> -
> - PowerPC,P1020@1 {
> - device_type = "cpu";
> - reg = <0x1>;
> - next-level-cache = <&L2>;
> - };
> - };
> -
> memory {
> device_type = "memory";
> };
>
> localbus@ffe05000 {
> - #address-cells = <2>;
> - #size-cells = <1>;
> - compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
> - reg = <0 0xffe05000 0 0x1000>;
> - interrupts = <19 2>;
> - interrupt-parent = <&mpic>;
>
> /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
> ranges = <0x0 0x0 0x0 0xef000000 0x01000000
> @@ -165,88 +141,14 @@
> };
>
> soc@ffe00000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "soc";
> - compatible = "fsl,p1020-immr", "simple-bus";
> - ranges = <0x0 0x0 0xffe00000 0x100000>;
> - bus-frequency = <0>; // Filled out by uboot.
> -
> - ecm-law@0 {
> - compatible = "fsl,ecm-law";
> - reg = <0x0 0x1000>;
> - fsl,num-laws = <12>;
> - };
> -
> - ecm@1000 {
> - compatible = "fsl,p1020-ecm", "fsl,ecm";
> - reg = <0x1000 0x1000>;
> - interrupts = <16 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - memory-controller@2000 {
> - compatible = "fsl,p1020-memory-controller";
> - reg = <0x2000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> - };
> -
> i2c@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - cell-index = <0>;
> - compatible = "fsl-i2c";
> - reg = <0x3000 0x100>;
> - interrupts = <43 2>;
> - interrupt-parent = <&mpic>;
> - dfsrr;
> rtc@68 {
> compatible = "dallas,ds1339";
> reg = <0x68>;
> };
> };
>
> - i2c@3100 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - cell-index = <1>;
> - compatible = "fsl-i2c";
> - reg = <0x3100 0x100>;
> - interrupts = <43 2>;
> - interrupt-parent = <&mpic>;
> - dfsrr;
> - };
> -
> - serial0: serial@4500 {
> - cell-index = <0>;
> - device_type = "serial";
> - compatible = "ns16550";
> - reg = <0x4500 0x100>;
> - clock-frequency = <0>;
> - interrupts = <42 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - serial1: serial@4600 {
> - cell-index = <1>;
> - device_type = "serial";
> - compatible = "ns16550";
> - reg = <0x4600 0x100>;
> - clock-frequency = <0>;
> - interrupts = <42 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> spi@7000 {
> - cell-index = <0>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,espi";
> - reg = <0x7000 0x1000>;
> - interrupts = <59 0x2>;
> - interrupt-parent = <&mpic>;
> - mode = "cpu";
>
> fsl_m25p80@0 {
> #address-cells = <1>;
> @@ -294,66 +196,7 @@
> };
> };
>
> - gpio: gpio-controller@f000 {
> - #gpio-cells = <2>;
> - compatible = "fsl,mpc8572-gpio";
> - reg = <0xf000 0x100>;
> - interrupts = <47 0x2>;
> - interrupt-parent = <&mpic>;
> - gpio-controller;
> - };
> -
> - L2: l2-cache-controller@20000 {
> - compatible = "fsl,p1020-l2-cache-controller";
> - reg = <0x20000 0x1000>;
> - cache-line-size = <32>; // 32 bytes
> - cache-size = <0x40000>; // L2,256K
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> - };
> -
> - dma@21300 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,eloplus-dma";
> - reg = <0x21300 0x4>;
> - ranges = <0x0 0x21100 0x200>;
> - cell-index = <0>;
> - dma-channel@0 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x0 0x80>;
> - cell-index = <0>;
> - interrupt-parent = <&mpic>;
> - interrupts = <20 2>;
> - };
> - dma-channel@80 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x80 0x80>;
> - cell-index = <1>;
> - interrupt-parent = <&mpic>;
> - interrupts = <21 2>;
> - };
> - dma-channel@100 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x100 0x80>;
> - cell-index = <2>;
> - interrupt-parent = <&mpic>;
> - interrupts = <22 2>;
> - };
> - dma-channel@180 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x180 0x80>;
> - cell-index = <3>;
> - interrupt-parent = <&mpic>;
> - interrupts = <23 2>;
> - };
> - };
> -
> mdio@24000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,etsec2-mdio";
> - reg = <0x24000 0x1000 0xb0030 0x4>;
>
> phy0: ethernet-phy@0 {
> interrupt-parent = <&mpic>;
> @@ -369,10 +212,6 @@
> };
>
> mdio@25000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,etsec2-tbi";
> - reg = <0x25000 0x1000 0xb1030 0x4>;
>
> tbi0: tbi-phy@11 {
> reg = <0x11>;
> @@ -381,97 +220,25 @@
> };
>
> enet0: ethernet@b0000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> fixed-link = <1 1 1000 0 0>;
> phy-connection-type = "rgmii-id";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb0000 0x1000>;
> - interrupts = <29 2 30 2 34 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb4000 0x1000>;
> - interrupts = <17 2 18 2 24 2>;
> - };
> };
>
> enet1: ethernet@b1000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> phy-handle = <&phy0>;
> tbi-handle = <&tbi0>;
> phy-connection-type = "sgmii";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb1000 0x1000>;
> - interrupts = <35 2 36 2 40 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb5000 0x1000>;
> - interrupts = <51 2 52 2 67 2>;
> - };
> };
>
> enet2: ethernet@b2000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> phy-handle = <&phy1>;
> phy-connection-type = "rgmii-id";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb2000 0x1000>;
> - interrupts = <31 2 32 2 33 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb6000 0x1000>;
> - interrupts = <25 2 26 2 27 2>;
> - };
> };
>
> usb@22000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl-usb2-dr";
> - reg = <0x22000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <28 0x2>;
> phy_type = "ulpi";
> };
>
> @@ -481,82 +248,15 @@
> it enables USB2. OTOH, U-Boot does create a new node
> when there isn't any. So, just comment it out.
> usb@23000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl-usb2-dr";
> - reg = <0x23000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <46 0x2>;
> phy_type = "ulpi";
> };
> */
>
> - sdhci@2e000 {
> - compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> - reg = <0x2e000 0x1000>;
> - interrupts = <72 0x2>;
> - interrupt-parent = <&mpic>;
> - /* Filled in by U-Boot */
> - clock-frequency = <0>;
> - };
> -
> - crypto@30000 {
> - compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> - "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> - reg = <0x30000 0x10000>;
> - interrupts = <45 2 58 2>;
> - interrupt-parent = <&mpic>;
> - fsl,num-channels = <4>;
> - fsl,channel-fifo-len = <24>;
> - fsl,exec-units-mask = <0xbfe>;
> - fsl,descriptor-types-mask = <0x3ab0ebf>;
> - };
> -
> - mpic: pic@40000 {
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <2>;
> - reg = <0x40000 0x40000>;
> - compatible = "chrp,open-pic";
> - device_type = "open-pic";
> - };
> -
> - msi@41600 {
> - compatible = "fsl,p1020-msi", "fsl,mpic-msi";
> - reg = <0x41600 0x80>;
> - msi-available-ranges = <0 0x100>;
> - interrupts = <
> - 0xe0 0
> - 0xe1 0
> - 0xe2 0
> - 0xe3 0
> - 0xe4 0
> - 0xe5 0
> - 0xe6 0
> - 0xe7 0>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - global-utilities@e0000 { //global utilities block
> - compatible = "fsl,p1020-guts";
> - reg = <0xe0000 0x1000>;
> - fsl,has-rstcr;
> - };
> };
>
> pci0: pcie@ffe09000 {
> - compatible = "fsl,mpc8548-pcie";
> - device_type = "pci";
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - reg = <0 0xffe09000 0 0x1000>;
> - bus-range = <0 255>;
> ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
> 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
> - clock-frequency = <33333333>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> pcie@0 {
> reg = <0x0 0x0 0x0 0x0 0x0>;
> #size-cells = <2>;
> @@ -573,18 +273,8 @@
> };
>
> pci1: pcie@ffe0a000 {
> - compatible = "fsl,mpc8548-pcie";
> - device_type = "pci";
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - reg = <0 0xffe0a000 0 0x1000>;
> - bus-range = <0 255>;
> ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
> 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
> - clock-frequency = <33333333>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> pcie@0 {
> reg = <0x0 0x0 0x0 0x0 0x0>;
> #size-cells = <2>;
> diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
> new file mode 100644
> index 0000000..f6f1100
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p1020si.dtsi
> @@ -0,0 +1,377 @@
> +/*
> + * P1020si Device Tree Source
> + *
> + * Copyright 2011 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/ {
> + compatible = "fsl,P1020";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,P1020@0 {
> + device_type = "cpu";
> + reg = <0x0>;
> + next-level-cache = <&L2>;
> + };
> +
> + PowerPC,P1020@1 {
> + device_type = "cpu";
> + reg = <0x1>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + localbus@ffe05000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
> + reg = <0 0xffe05000 0 0x1000>;
> + interrupts = <19 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + soc@ffe00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + compatible = "fsl,p1020-immr", "simple-bus";
> + ranges = <0x0 0x0 0xffe00000 0x100000>;
> + bus-frequency = <0>; // Filled out by uboot.
> +
> + ecm-law@0 {
> + compatible = "fsl,ecm-law";
> + reg = <0x0 0x1000>;
> + fsl,num-laws = <12>;
> + };
> +
> + ecm@1000 {
> + compatible = "fsl,p1020-ecm", "fsl,ecm";
> + reg = <0x1000 0x1000>;
> + interrupts = <16 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + memory-controller@2000 {
> + compatible = "fsl,p1020-memory-controller";
> + reg = <0x2000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + i2c@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <0>;
> + compatible = "fsl-i2c";
> + reg = <0x3000 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + i2c@3100 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <1>;
> + compatible = "fsl-i2c";
> + reg = <0x3100 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + serial0: serial@4500 {
> + cell-index = <0>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4500 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + serial1: serial@4600 {
> + cell-index = <1>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4600 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + spi@7000 {
> + cell-index = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,espi";
> + reg = <0x7000 0x1000>;
> + interrupts = <59 0x2>;
> + interrupt-parent = <&mpic>;
> + mode = "cpu";
> + };
> +
> + gpio: gpio-controller@f000 {
> + #gpio-cells = <2>;
> + compatible = "fsl,mpc8572-gpio";
> + reg = <0xf000 0x100>;
> + interrupts = <47 0x2>;
> + interrupt-parent = <&mpic>;
> + gpio-controller;
> + };
> +
> + L2: l2-cache-controller@20000 {
> + compatible = "fsl,p1020-l2-cache-controller";
> + reg = <0x20000 0x1000>;
> + cache-line-size = <32>; // 32 bytes
> + cache-size = <0x40000>; // L2,256K
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + dma@21300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0x21300 0x4>;
> + ranges = <0x0 0x21100 0x200>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <20 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <21 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <22 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <23 2>;
> + };
> + };
> +
> + mdio@24000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,etsec2-mdio";
> + reg = <0x24000 0x1000 0xb0030 0x4>;
> +
> + };
> +
> + mdio@25000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,etsec2-tbi";
> + reg = <0x25000 0x1000 0xb1030 0x4>;
> +
> + };
> +
> + enet0: ethernet@b0000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb0000 0x1000>;
> + interrupts = <29 2 30 2 34 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb4000 0x1000>;
> + interrupts = <17 2 18 2 24 2>;
> + };
> + };
> +
> + enet1: ethernet@b1000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb1000 0x1000>;
> + interrupts = <35 2 36 2 40 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb5000 0x1000>;
> + interrupts = <51 2 52 2 67 2>;
> + };
> + };
> +
> + enet2: ethernet@b2000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb2000 0x1000>;
> + interrupts = <31 2 32 2 33 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb6000 0x1000>;
> + interrupts = <25 2 26 2 27 2>;
> + };
> + };
> +
> + usb@22000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x22000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <28 0x2>;
> + };
> +
> + /* USB2 is shared with localbus, so it must be disabled
> + by default. We can't put 'status = "disabled";' here
> + since U-Boot doesn't clear the status property when
> + it enables USB2. OTOH, U-Boot does create a new node
> + when there isn't any. So, just comment it out.
> + usb@23000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x23000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <46 0x2>;
> + phy_type = "ulpi";
> + };
> + */
> +
> + sdhci@2e000 {
> + compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> + reg = <0x2e000 0x1000>;
> + interrupts = <72 0x2>;
> + interrupt-parent = <&mpic>;
> + /* Filled in by U-Boot */
> + clock-frequency = <0>;
> + };
> +
> + crypto@30000 {
> + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> + reg = <0x30000 0x10000>;
> + interrupts = <45 2 58 2>;
> + interrupt-parent = <&mpic>;
> + fsl,num-channels = <4>;
> + fsl,channel-fifo-len = <24>;
> + fsl,exec-units-mask = <0xbfe>;
> + fsl,descriptor-types-mask = <0x3ab0ebf>;
> + };
> +
> + mpic: pic@40000 {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + reg = <0x40000 0x40000>;
> + compatible = "chrp,open-pic";
> + device_type = "open-pic";
> + };
> +
> + msi@41600 {
> + compatible = "fsl,p1020-msi", "fsl,mpic-msi";
> + reg = <0x41600 0x80>;
> + msi-available-ranges = <0 0x100>;
> + interrupts = <
> + 0xe0 0
> + 0xe1 0
> + 0xe2 0
> + 0xe3 0
> + 0xe4 0
> + 0xe5 0
> + 0xe6 0
> + 0xe7 0>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + global-utilities@e0000 { //global utilities block
> + compatible = "fsl,p1020-guts";
> + reg = <0xe0000 0x1000>;
> + fsl,has-rstcr;
> + };
> + };
> +
> + pci0: pcie@ffe09000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe09000 0 0x1000>;
> + bus-range = <0 255>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + pci1: pcie@ffe0a000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe0a000 0 0x1000>;
> + bus-range = <0 255>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +};
> --
> 1.7.3
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply
* Re: Revert 737a3bb9416ce2a7c7a4170852473a4fcc9c67e8 ?
From: Michel Dänzer @ 2011-04-07 14:04 UTC (permalink / raw)
To: Gabriel Paubert
Cc: Greg KH, Uwe Kleine-König, Dave Airlie, linuxppc-dev, LKML
In-Reply-To: <20110406204327.GA11148@iram.es>
On Mit, 2011-04-06 at 22:43 +0200, Gabriel Paubert wrote:=20
>=20
> The probem is that, at least on one of my machines, the new driver
> does not work: the system hangs (apparently solid, but it's before
> networking starts up and I've not yet hooked up a serial console),=20
> after the "radeon: ib pool ready" message.
Does radeon.agpmode=3D-1 radeon.no_wb=3D1 help?
You might be able to get more information via netconsole if you prevent
the radeon module from loading automatically (or load it with
radeon.modeset=3D0 first) and then load it e.g. via ssh with modeset=3D1.
It would be interesting to see at least all agp/drm/radeon related
kernel messages before the problem occurs.
--=20
Earthling Michel D=C3=A4nzer | http://www.vmware.c=
om
Libre software enthusiast | Debian, X and DRI developer
^ permalink raw reply
* [PATCH] rtas: Only sleep in rtas_busy_delay if we have useful work to do
From: Anton Blanchard @ 2011-04-07 11:54 UTC (permalink / raw)
To: benh, paulus; +Cc: nacc, linuxppc-dev, miltonm
RTAS returns extended error codes as a hint of how long the
OS might want to wait before retrying a call. If we have nothing
else useful to do we may as well call back straight away.
This was found when testing the new dynamic dma window feature.
Firmware split the zeroing of the TCE table into 32k chunks but
returned 9901 (which is a suggested wait of 10ms). All up this took
about 10 minutes to complete since msleep is jiffies based and will
round 10ms up to 20ms.
With the patch below we take 3 seconds to complete the same test.
The hint firmware is returning in the RTAS call should definitely
be decreased, but even if we slept 1ms each iteration this would
take 32s.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: linux-2.6/arch/powerpc/kernel/rtas.c
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/rtas.c 2011-04-05 11:19:35.023234011 +1000
+++ linux-2.6/arch/powerpc/kernel/rtas.c 2011-04-07 21:25:24.646414629 +1000
@@ -494,7 +494,7 @@ unsigned int rtas_busy_delay(int status)
might_sleep();
ms = rtas_busy_delay_time(status);
- if (ms)
+ if (ms && need_resched())
msleep(ms);
return ms;
^ permalink raw reply
* Re: Revert 737a3bb9416ce2a7c7a4170852473a4fcc9c67e8 ?
From: Gabriel Paubert @ 2011-04-07 11:33 UTC (permalink / raw)
To: Dave Airlie; +Cc: Greg KH, linuxppc-dev, LKML, Uwe Kleine-König
In-Reply-To: <BANLkTimAJ-s_3A3L1YGfoFLmd4bpu2jWVA@mail.gmail.com>
Hi Dave,
sorry, in my previous message I forgot the strace
output, which is an inifinite loop of the following:
--- SIGALRM (Alarm clock) @ 0 (0) ---
sigreturn() = ? (mask now [])
ioctl(7, 0xc0286429, 0xffdf9bb8) = -1 EBUSY (Device or resource busy)
--- SIGALRM (Alarm clock) @ 0 (0) ---
sigreturn() = ? (mask now [])
ioctl(7, 0xc0286429, 0xffdf9bb8) = -1 EBUSY (Device or resource busy)
Note: fd 7 is /dev/dri/card0.
Regards,
Gabriel
^ permalink raw reply
* Re: Revert 737a3bb9416ce2a7c7a4170852473a4fcc9c67e8 ?
From: Gabriel Paubert @ 2011-04-07 11:25 UTC (permalink / raw)
To: Dave Airlie; +Cc: Greg KH, linuxppc-dev, LKML, Uwe Kleine-König
In-Reply-To: <BANLkTimAJ-s_3A3L1YGfoFLmd4bpu2jWVA@mail.gmail.com>
Hi Dave,
> This is the old DRM driver for radeon, which relies on userspace to
> start X then calls the kernel
Actually, even the old DRM driver occasionally hangs on this machine,
I suspect a missing barrier, but I might be completely off base.
The system is up, only X uses 100% of one core and according to
gdb X is there:
(gdb) info stack
#0 0x0fbafb08 in ioctl () from /lib/libc.so.6
#1 0x0f7be1c8 in drmDMA () from /usr/lib/libdrm.so.2
#2 0x0f65330c in ?? () from /usr/lib/xorg/modules/drivers/radeon_drv.so
#3 0x0f65380c in ?? () from /usr/lib/xorg/modules/drivers/radeon_drv.so
#4 0x0f6f89b8 in ?? () from /usr/lib/xorg/modules/drivers/radeon_drv.so
#5 0x0f562538 in ?? () from /usr/lib/xorg/modules/libexa.so
#6 0x0f56298c in ?? () from /usr/lib/xorg/modules/libexa.so
#7 0x0f56351c in ?? () from /usr/lib/xorg/modules/libexa.so
#8 0x0f55fba0 in ?? () from /usr/lib/xorg/modules/libexa.so
#9 0x0f56ab18 in ?? () from /usr/lib/xorg/modules/libexa.so
#10 0x0f56b810 in ?? () from /usr/lib/xorg/modules/libexa.so
#11 0x100f168c in ?? ()
#12 0x100df0fc in CompositePicture ()
#13 0x0f56a748 in ?? () from /usr/lib/xorg/modules/libexa.so
#14 0x100dee08 in CompositeTrapezoids ()
#15 0x100eb318 in ?? ()
#16 0x100e3ae8 in ?? ()
#17 0x1004a1f0 in ?? ()
#18 0x1001d0d4 in ?? ()
#19 0x0faea63c in ?? () from /lib/libc.so.6
#20 0x0faea800 in __libc_start_main () from /lib/libc.so.6
#21 0x00000000 in ?? ()
I don't know how to get more details.
Regards,
Gabriel
^ permalink raw reply
* mscan status on DENX Linux 2.6 Kernel Tree
From: moises.dominguez @ 2011-04-07 9:10 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 922 bytes --]
Hi,
Up to now I've been working ltib over and ads5121 based board.
So as not to work with frozen images I would like to change to u-boot and
kernel from denx. I did the following:
- Download and compile u-boot: OK.
- Download and kernel (mpc512x_defconfig): compilation fails if I enable
"Freescale MPC5xxx onboard CAN controller" with this message:
.
LD kernel/built-in.o
CC drivers/net/can/mscan/mscan.o
CC drivers/net/can/mscan/mpc5xxx_can.o
drivers/net/can/mscan/mpc5xxx_can.c: In function 'mpc5xxx_can_probe':
drivers/net/can/mscan/mpc5xxx_can.c:263: error: 'of_dev' undeclared (first
use in this function)
.
I have not much experience with this stuff but I've notice that there are
recent patches on mpc5xxx.c file, last from 2011-02-28 so I suppose this
should work.
Am I missing something? I also wonder if ads5121-Rev4 is fully supported in
Linux Denx.
Thanks,
Moises.
[-- Attachment #2: Type: text/html, Size: 4028 bytes --]
^ permalink raw reply
* [PATCH][v2] powerpc/85xx: P1020 DTS : re-organize dts files
From: Prabhakar Kushwaha @ 2011-04-07 9:10 UTC (permalink / raw)
To: linuxppc-dev, devicetree-discuss
Cc: meet2prabhu, kumar.gala, Prabhakar Kushwaha
Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
files for P1020 based systems to use dtsi file
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Kumar Gala <kumar.gala@freescale.com>
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master)
Please see mpc5200b.dtsi for reference.
Tested on P1020RDB
Changes for v2: Incorporated Grant Likely's comment
-updated model name
arch/powerpc/boot/dts/p1020rdb.dts | 316 +------------------------------
arch/powerpc/boot/dts/p1020si.dtsi | 377 ++++++++++++++++++++++++++++++++++++
2 files changed, 380 insertions(+), 313 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index e0668f8..7ed4793 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,12 +9,11 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "p1020si.dtsi"
+
/ {
- model = "fsl,P1020";
+ model = "fsl,P1020RDB";
compatible = "fsl,P1020RDB";
- #address-cells = <2>;
- #size-cells = <2>;
aliases {
serial0 = &serial0;
@@ -26,34 +25,11 @@
pci1 = &pci1;
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,P1020@0 {
- device_type = "cpu";
- reg = <0x0>;
- next-level-cache = <&L2>;
- };
-
- PowerPC,P1020@1 {
- device_type = "cpu";
- reg = <0x1>;
- next-level-cache = <&L2>;
- };
- };
-
memory {
device_type = "memory";
};
localbus@ffe05000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
- reg = <0 0xffe05000 0 0x1000>;
- interrupts = <19 2>;
- interrupt-parent = <&mpic>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,88 +141,14 @@
};
soc@ffe00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "fsl,p1020-immr", "simple-bus";
- ranges = <0x0 0x0 0xffe00000 0x100000>;
- bus-frequency = <0>; // Filled out by uboot.
-
- ecm-law@0 {
- compatible = "fsl,ecm-law";
- reg = <0x0 0x1000>;
- fsl,num-laws = <12>;
- };
-
- ecm@1000 {
- compatible = "fsl,p1020-ecm", "fsl,ecm";
- reg = <0x1000 0x1000>;
- interrupts = <16 2>;
- interrupt-parent = <&mpic>;
- };
-
- memory-controller@2000 {
- compatible = "fsl,p1020-memory-controller";
- reg = <0x2000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
-
i2c@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
-
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
-
spi@7000 {
- cell-index = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,espi";
- reg = <0x7000 0x1000>;
- interrupts = <59 0x2>;
- interrupt-parent = <&mpic>;
- mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
@@ -294,66 +196,7 @@
};
};
- gpio: gpio-controller@f000 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8572-gpio";
- reg = <0xf000 0x100>;
- interrupts = <47 0x2>;
- interrupt-parent = <&mpic>;
- gpio-controller;
- };
-
- L2: l2-cache-controller@20000 {
- compatible = "fsl,p1020-l2-cache-controller";
- reg = <0x20000 0x1000>;
- cache-line-size = <32>; // 32 bytes
- cache-size = <0x40000>; // L2,256K
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
-
- dma@21300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,eloplus-dma";
- reg = <0x21300 0x4>;
- ranges = <0x0 0x21100 0x200>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x0 0x80>;
- cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <20 2>;
- };
- dma-channel@80 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x80 0x80>;
- cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <21 2>;
- };
- dma-channel@100 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x100 0x80>;
- cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <22 2>;
- };
- dma-channel@180 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x180 0x80>;
- cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <23 2>;
- };
- };
-
mdio@24000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-mdio";
- reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
@@ -369,10 +212,6 @@
};
mdio@25000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-tbi";
- reg = <0x25000 0x1000 0xb1030 0x4>;
tbi0: tbi-phy@11 {
reg = <0x11>;
@@ -381,97 +220,25 @@
};
enet0: ethernet@b0000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb0000 0x1000>;
- interrupts = <29 2 30 2 34 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb4000 0x1000>;
- interrupts = <17 2 18 2 24 2>;
- };
};
enet1: ethernet@b1000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb1000 0x1000>;
- interrupts = <35 2 36 2 40 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb5000 0x1000>;
- interrupts = <51 2 52 2 67 2>;
- };
};
enet2: ethernet@b2000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb2000 0x1000>;
- interrupts = <31 2 32 2 33 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb6000 0x1000>;
- interrupts = <25 2 26 2 27 2>;
- };
};
usb@22000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl-usb2-dr";
- reg = <0x22000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <28 0x2>;
phy_type = "ulpi";
};
@@ -481,82 +248,15 @@
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl-usb2-dr";
- reg = <0x23000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <46 0x2>;
phy_type = "ulpi";
};
*/
- sdhci@2e000 {
- compatible = "fsl,p1020-esdhc", "fsl,esdhc";
- reg = <0x2e000 0x1000>;
- interrupts = <72 0x2>;
- interrupt-parent = <&mpic>;
- /* Filled in by U-Boot */
- clock-frequency = <0>;
- };
-
- crypto@30000 {
- compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
- "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
- reg = <0x30000 0x10000>;
- interrupts = <45 2 58 2>;
- interrupt-parent = <&mpic>;
- fsl,num-channels = <4>;
- fsl,channel-fifo-len = <24>;
- fsl,exec-units-mask = <0xbfe>;
- fsl,descriptor-types-mask = <0x3ab0ebf>;
- };
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x40000 0x40000>;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- };
-
- msi@41600 {
- compatible = "fsl,p1020-msi", "fsl,mpic-msi";
- reg = <0x41600 0x80>;
- msi-available-ranges = <0 0x100>;
- interrupts = <
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0>;
- interrupt-parent = <&mpic>;
- };
-
- global-utilities@e0000 { //global utilities block
- compatible = "fsl,p1020-guts";
- reg = <0xe0000 0x1000>;
- fsl,has-rstcr;
- };
};
pci0: pcie@ffe09000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0 0xffe09000 0 0x1000>;
- bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
@@ -573,18 +273,8 @@
};
pci1: pcie@ffe0a000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0 0xffe0a000 0 0x1000>;
- bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
new file mode 100644
index 0000000..f6f1100
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020si.dtsi
@@ -0,0 +1,377 @@
+/*
+ * P1020si Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ compatible = "fsl,P1020";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P1020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P1020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ localbus@ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p1020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <16 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p1020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p1020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2,256K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ mdio@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x24000 0x1000 0xb0030 0x4>;
+
+ };
+
+ mdio@25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x25000 0x1000 0xb1030 0x4>;
+
+ };
+
+ enet0: ethernet@b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb0000 0x1000>;
+ interrupts = <29 2 30 2 34 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb4000 0x1000>;
+ interrupts = <17 2 18 2 24 2>;
+ };
+ };
+
+ enet1: ethernet@b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb1000 0x1000>;
+ interrupts = <35 2 36 2 40 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb5000 0x1000>;
+ interrupts = <51 2 52 2 67 2>;
+ };
+ };
+
+ enet2: ethernet@b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb2000 0x1000>;
+ interrupts = <31 2 32 2 33 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb6000 0x1000>;
+ interrupts = <25 2 26 2 27 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ };
+
+ /* USB2 is shared with localbus, so it must be disabled
+ by default. We can't put 'status = "disabled";' here
+ since U-Boot doesn't clear the status property when
+ it enables USB2. OTOH, U-Boot does create a new node
+ when there isn't any. So, just comment it out.
+ usb@23000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <46 0x2>;
+ phy_type = "ulpi";
+ };
+ */
+
+ sdhci@2e000 {
+ compatible = "fsl,p1020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi@41600 {
+ compatible = "fsl,p1020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,p1020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ pci1: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+};
--
1.7.3
^ permalink raw reply related
* Re: known working sata_sil24.c setup on powerpc platforms?
From: Martyn Welch @ 2011-04-07 8:27 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <BANLkTimXgi26RHHxyBLoN8YqaDy_PL-hGQ@mail.gmail.com>
On 06/04/11 18:00, Leon Woestenberg wrote:
> Hello,
>
> after investigating problems with sata_sil24.c on a freescale p2020
> soc, I wonder if this driver works on powerpc at all?
>
> Does anyone know of a working setup of sata_sil24 on a big endian
> powerpc system?
>
Yes, I think we even use it on a p2020 board, though I think our current
kernel on that product is 2.6.34.
Martyn
--
Martyn Welch (Principal Software Engineer) | Registered in England and
GE Intelligent Platforms | Wales (3828642) at 100
T +44(0)127322748 | Barbirolli Square, Manchester,
E martyn.welch@ge.com | M2 3AB VAT:GB 927559189
^ permalink raw reply
* Re: [PATCH] powerpc: Free up some CPU feature bits by moving out MMU-related features
From: Matt Evans @ 2011-04-07 8:17 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <D5DE7F16-B3E0-4F5C-9A2C-0052C6B6D2D1@kernel.crashing.org>
On 07/04/11 17:06, Kumar Gala wrote:
>
> On Apr 7, 2011, at 12:48 AM, Matt Evans wrote:
>
>> diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
>> index be3cdf9..7b0fe7c 100644
>> --- a/arch/powerpc/include/asm/cputable.h
>> +++ b/arch/powerpc/include/asm/cputable.h
>> @@ -178,22 +178,15 @@ extern const char *powerpc_base_platform;
>> #define LONG_ASM_CONST(x) 0
>> #endif
>>
>> -#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
>> -#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
>> -#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
>> #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
>> #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
>> #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
>> #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
>> -#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
>> -#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
>> #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
>> #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
>> #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
>> #define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
>> #define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
>> -#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
>> -#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
>> #define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
>> #define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
>> #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
>> @@ -205,9 +198,10 @@ extern const char *powerpc_base_platform;
>
> Seems like SAO should move into MMU features
I would argue it's the core/nest that orders/disorders things rather than the MMU.
Cheers,
Matt
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: P1020 DTS : re-organize dts files
From: Grant Likely @ 2011-04-07 8:09 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: meet2prabhu, devicetree-discuss, linuxppc-dev, B11780
In-Reply-To: <1302157534-16746-1-git-send-email-prabhakar@freescale.com>
On Thu, Apr 07, 2011 at 11:55:34AM +0530, Prabhakar Kushwaha wrote:
> Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
> files for P1020 based systems to use dtsi file.
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Acked-by: Kumar Gala <kumar.gala@freescale.com>
> ---
> Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master)
>
> Please see mpc5200b.dtsi for reference.
>
> Tested on P1020RDB
Minor comments below, but I think this looks good.
g.
>
> arch/powerpc/boot/dts/p1020rdb.dts | 315 +-----------------------------
> arch/powerpc/boot/dts/p1020si.dtsi | 378 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 380 insertions(+), 313 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
>
> diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
> index e0668f8..8ae5ddf 100644
> --- a/arch/powerpc/boot/dts/p1020rdb.dts
> +++ b/arch/powerpc/boot/dts/p1020rdb.dts
> @@ -9,12 +9,10 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "p1020si.dtsi"
> +
> / {
> - model = "fsl,P1020";
Model here should actually reflect the name of the board, not the soc.
I don't think you want to remove it from here, but it definitely looks
like it needs to be fixed.
> compatible = "fsl,P1020RDB";
> - #address-cells = <2>;
> - #size-cells = <2>;
>
> aliases {
> serial0 = &serial0;
> @@ -26,34 +24,11 @@
> pci1 = &pci1;
> };
>
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,P1020@0 {
> - device_type = "cpu";
> - reg = <0x0>;
> - next-level-cache = <&L2>;
> - };
> -
> - PowerPC,P1020@1 {
> - device_type = "cpu";
> - reg = <0x1>;
> - next-level-cache = <&L2>;
> - };
> - };
> -
> memory {
> device_type = "memory";
> };
>
> localbus@ffe05000 {
> - #address-cells = <2>;
> - #size-cells = <1>;
> - compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
> - reg = <0 0xffe05000 0 0x1000>;
> - interrupts = <19 2>;
> - interrupt-parent = <&mpic>;
>
> /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
> ranges = <0x0 0x0 0x0 0xef000000 0x01000000
> @@ -165,88 +140,14 @@
> };
>
> soc@ffe00000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "soc";
> - compatible = "fsl,p1020-immr", "simple-bus";
> - ranges = <0x0 0x0 0xffe00000 0x100000>;
> - bus-frequency = <0>; // Filled out by uboot.
> -
> - ecm-law@0 {
> - compatible = "fsl,ecm-law";
> - reg = <0x0 0x1000>;
> - fsl,num-laws = <12>;
> - };
> -
> - ecm@1000 {
> - compatible = "fsl,p1020-ecm", "fsl,ecm";
> - reg = <0x1000 0x1000>;
> - interrupts = <16 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - memory-controller@2000 {
> - compatible = "fsl,p1020-memory-controller";
> - reg = <0x2000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> - };
> -
> i2c@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - cell-index = <0>;
> - compatible = "fsl-i2c";
> - reg = <0x3000 0x100>;
> - interrupts = <43 2>;
> - interrupt-parent = <&mpic>;
> - dfsrr;
> rtc@68 {
> compatible = "dallas,ds1339";
> reg = <0x68>;
> };
> };
>
> - i2c@3100 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - cell-index = <1>;
> - compatible = "fsl-i2c";
> - reg = <0x3100 0x100>;
> - interrupts = <43 2>;
> - interrupt-parent = <&mpic>;
> - dfsrr;
> - };
> -
> - serial0: serial@4500 {
> - cell-index = <0>;
> - device_type = "serial";
> - compatible = "ns16550";
> - reg = <0x4500 0x100>;
> - clock-frequency = <0>;
> - interrupts = <42 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - serial1: serial@4600 {
> - cell-index = <1>;
> - device_type = "serial";
> - compatible = "ns16550";
> - reg = <0x4600 0x100>;
> - clock-frequency = <0>;
> - interrupts = <42 2>;
> - interrupt-parent = <&mpic>;
> - };
> -
> spi@7000 {
> - cell-index = <0>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,espi";
> - reg = <0x7000 0x1000>;
> - interrupts = <59 0x2>;
> - interrupt-parent = <&mpic>;
> - mode = "cpu";
>
> fsl_m25p80@0 {
> #address-cells = <1>;
> @@ -294,66 +195,7 @@
> };
> };
>
> - gpio: gpio-controller@f000 {
> - #gpio-cells = <2>;
> - compatible = "fsl,mpc8572-gpio";
> - reg = <0xf000 0x100>;
> - interrupts = <47 0x2>;
> - interrupt-parent = <&mpic>;
> - gpio-controller;
> - };
> -
> - L2: l2-cache-controller@20000 {
> - compatible = "fsl,p1020-l2-cache-controller";
> - reg = <0x20000 0x1000>;
> - cache-line-size = <32>; // 32 bytes
> - cache-size = <0x40000>; // L2,256K
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> - };
> -
> - dma@21300 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,eloplus-dma";
> - reg = <0x21300 0x4>;
> - ranges = <0x0 0x21100 0x200>;
> - cell-index = <0>;
> - dma-channel@0 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x0 0x80>;
> - cell-index = <0>;
> - interrupt-parent = <&mpic>;
> - interrupts = <20 2>;
> - };
> - dma-channel@80 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x80 0x80>;
> - cell-index = <1>;
> - interrupt-parent = <&mpic>;
> - interrupts = <21 2>;
> - };
> - dma-channel@100 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x100 0x80>;
> - cell-index = <2>;
> - interrupt-parent = <&mpic>;
> - interrupts = <22 2>;
> - };
> - dma-channel@180 {
> - compatible = "fsl,eloplus-dma-channel";
> - reg = <0x180 0x80>;
> - cell-index = <3>;
> - interrupt-parent = <&mpic>;
> - interrupts = <23 2>;
> - };
> - };
> -
> mdio@24000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,etsec2-mdio";
> - reg = <0x24000 0x1000 0xb0030 0x4>;
>
> phy0: ethernet-phy@0 {
> interrupt-parent = <&mpic>;
> @@ -369,10 +211,6 @@
> };
>
> mdio@25000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,etsec2-tbi";
> - reg = <0x25000 0x1000 0xb1030 0x4>;
>
> tbi0: tbi-phy@11 {
> reg = <0x11>;
> @@ -381,97 +219,25 @@
> };
>
> enet0: ethernet@b0000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> fixed-link = <1 1 1000 0 0>;
> phy-connection-type = "rgmii-id";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb0000 0x1000>;
> - interrupts = <29 2 30 2 34 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb4000 0x1000>;
> - interrupts = <17 2 18 2 24 2>;
> - };
> };
>
> enet1: ethernet@b1000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> phy-handle = <&phy0>;
> tbi-handle = <&tbi0>;
> phy-connection-type = "sgmii";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb1000 0x1000>;
> - interrupts = <35 2 36 2 40 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb5000 0x1000>;
> - interrupts = <51 2 52 2 67 2>;
> - };
> };
>
> enet2: ethernet@b2000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - device_type = "network";
> - model = "eTSEC";
> - compatible = "fsl,etsec2";
> - fsl,num_rx_queues = <0x8>;
> - fsl,num_tx_queues = <0x8>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupt-parent = <&mpic>;
> phy-handle = <&phy1>;
> phy-connection-type = "rgmii-id";
>
> - queue-group@0 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb2000 0x1000>;
> - interrupts = <31 2 32 2 33 2>;
> - };
> -
> - queue-group@1 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - reg = <0xb6000 0x1000>;
> - interrupts = <25 2 26 2 27 2>;
> - };
> };
>
> usb@22000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl-usb2-dr";
> - reg = <0x22000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <28 0x2>;
> phy_type = "ulpi";
> };
>
> @@ -481,82 +247,15 @@
> it enables USB2. OTOH, U-Boot does create a new node
> when there isn't any. So, just comment it out.
> usb@23000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl-usb2-dr";
> - reg = <0x23000 0x1000>;
> - interrupt-parent = <&mpic>;
> - interrupts = <46 0x2>;
> phy_type = "ulpi";
> };
> */
>
> - sdhci@2e000 {
> - compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> - reg = <0x2e000 0x1000>;
> - interrupts = <72 0x2>;
> - interrupt-parent = <&mpic>;
> - /* Filled in by U-Boot */
> - clock-frequency = <0>;
> - };
> -
> - crypto@30000 {
> - compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> - "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> - reg = <0x30000 0x10000>;
> - interrupts = <45 2 58 2>;
> - interrupt-parent = <&mpic>;
> - fsl,num-channels = <4>;
> - fsl,channel-fifo-len = <24>;
> - fsl,exec-units-mask = <0xbfe>;
> - fsl,descriptor-types-mask = <0x3ab0ebf>;
> - };
> -
> - mpic: pic@40000 {
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <2>;
> - reg = <0x40000 0x40000>;
> - compatible = "chrp,open-pic";
> - device_type = "open-pic";
> - };
> -
> - msi@41600 {
> - compatible = "fsl,p1020-msi", "fsl,mpic-msi";
> - reg = <0x41600 0x80>;
> - msi-available-ranges = <0 0x100>;
> - interrupts = <
> - 0xe0 0
> - 0xe1 0
> - 0xe2 0
> - 0xe3 0
> - 0xe4 0
> - 0xe5 0
> - 0xe6 0
> - 0xe7 0>;
> - interrupt-parent = <&mpic>;
> - };
> -
> - global-utilities@e0000 { //global utilities block
> - compatible = "fsl,p1020-guts";
> - reg = <0xe0000 0x1000>;
> - fsl,has-rstcr;
> - };
> };
>
> pci0: pcie@ffe09000 {
> - compatible = "fsl,mpc8548-pcie";
> - device_type = "pci";
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - reg = <0 0xffe09000 0 0x1000>;
> - bus-range = <0 255>;
> ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
> 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
> - clock-frequency = <33333333>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> pcie@0 {
> reg = <0x0 0x0 0x0 0x0 0x0>;
> #size-cells = <2>;
> @@ -573,18 +272,8 @@
> };
>
> pci1: pcie@ffe0a000 {
> - compatible = "fsl,mpc8548-pcie";
> - device_type = "pci";
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - reg = <0 0xffe0a000 0 0x1000>;
> - bus-range = <0 255>;
> ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
> 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
> - clock-frequency = <33333333>;
> - interrupt-parent = <&mpic>;
> - interrupts = <16 2>;
> pcie@0 {
> reg = <0x0 0x0 0x0 0x0 0x0>;
> #size-cells = <2>;
> diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
> new file mode 100644
> index 0000000..7b87d00
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p1020si.dtsi
> @@ -0,0 +1,378 @@
> +/*
> + * P1020si Device Tree Source
> + *
> + * Copyright 2011 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/ {
> + model = "fsl,P1020";
> + compatible = "fsl,P1020";
I think you should drop both of these properties from the include
file. Leave it to the board to actually define them.
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,P1020@0 {
> + device_type = "cpu";
> + reg = <0x0>;
> + next-level-cache = <&L2>;
> + };
> +
> + PowerPC,P1020@1 {
> + device_type = "cpu";
> + reg = <0x1>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + localbus@ffe05000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
> + reg = <0 0xffe05000 0 0x1000>;
> + interrupts = <19 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + soc@ffe00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + compatible = "fsl,p1020-immr", "simple-bus";
> + ranges = <0x0 0x0 0xffe00000 0x100000>;
> + bus-frequency = <0>; // Filled out by uboot.
> +
> + ecm-law@0 {
> + compatible = "fsl,ecm-law";
> + reg = <0x0 0x1000>;
> + fsl,num-laws = <12>;
> + };
> +
> + ecm@1000 {
> + compatible = "fsl,p1020-ecm", "fsl,ecm";
> + reg = <0x1000 0x1000>;
> + interrupts = <16 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + memory-controller@2000 {
> + compatible = "fsl,p1020-memory-controller";
> + reg = <0x2000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + i2c@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <0>;
> + compatible = "fsl-i2c";
> + reg = <0x3000 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + i2c@3100 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <1>;
> + compatible = "fsl-i2c";
> + reg = <0x3100 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + serial0: serial@4500 {
> + cell-index = <0>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4500 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + serial1: serial@4600 {
> + cell-index = <1>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4600 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + spi@7000 {
> + cell-index = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,espi";
> + reg = <0x7000 0x1000>;
> + interrupts = <59 0x2>;
> + interrupt-parent = <&mpic>;
> + mode = "cpu";
> + };
> +
> + gpio: gpio-controller@f000 {
> + #gpio-cells = <2>;
> + compatible = "fsl,mpc8572-gpio";
> + reg = <0xf000 0x100>;
> + interrupts = <47 0x2>;
> + interrupt-parent = <&mpic>;
> + gpio-controller;
> + };
> +
> + L2: l2-cache-controller@20000 {
> + compatible = "fsl,p1020-l2-cache-controller";
> + reg = <0x20000 0x1000>;
> + cache-line-size = <32>; // 32 bytes
> + cache-size = <0x40000>; // L2,256K
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + dma@21300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0x21300 0x4>;
> + ranges = <0x0 0x21100 0x200>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <20 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <21 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <22 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <23 2>;
> + };
> + };
> +
> + mdio@24000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,etsec2-mdio";
> + reg = <0x24000 0x1000 0xb0030 0x4>;
> +
> + };
> +
> + mdio@25000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,etsec2-tbi";
> + reg = <0x25000 0x1000 0xb1030 0x4>;
> +
> + };
> +
> + enet0: ethernet@b0000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb0000 0x1000>;
> + interrupts = <29 2 30 2 34 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb4000 0x1000>;
> + interrupts = <17 2 18 2 24 2>;
> + };
> + };
> +
> + enet1: ethernet@b1000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb1000 0x1000>;
> + interrupts = <35 2 36 2 40 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb5000 0x1000>;
> + interrupts = <51 2 52 2 67 2>;
> + };
> + };
> +
> + enet2: ethernet@b2000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "fsl,etsec2";
> + fsl,num_rx_queues = <0x8>;
> + fsl,num_tx_queues = <0x8>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupt-parent = <&mpic>;
> +
> + queue-group@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb2000 0x1000>;
> + interrupts = <31 2 32 2 33 2>;
> + };
> +
> + queue-group@1 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0xb6000 0x1000>;
> + interrupts = <25 2 26 2 27 2>;
> + };
> + };
> +
> + usb@22000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x22000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <28 0x2>;
> + };
> +
> + /* USB2 is shared with localbus, so it must be disabled
> + by default. We can't put 'status = "disabled";' here
> + since U-Boot doesn't clear the status property when
> + it enables USB2. OTOH, U-Boot does create a new node
> + when there isn't any. So, just comment it out.
> + usb@23000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x23000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <46 0x2>;
> + phy_type = "ulpi";
> + };
> + */
> +
> + sdhci@2e000 {
> + compatible = "fsl,p1020-esdhc", "fsl,esdhc";
> + reg = <0x2e000 0x1000>;
> + interrupts = <72 0x2>;
> + interrupt-parent = <&mpic>;
> + /* Filled in by U-Boot */
> + clock-frequency = <0>;
> + };
> +
> + crypto@30000 {
> + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> + reg = <0x30000 0x10000>;
> + interrupts = <45 2 58 2>;
> + interrupt-parent = <&mpic>;
> + fsl,num-channels = <4>;
> + fsl,channel-fifo-len = <24>;
> + fsl,exec-units-mask = <0xbfe>;
> + fsl,descriptor-types-mask = <0x3ab0ebf>;
> + };
> +
> + mpic: pic@40000 {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + reg = <0x40000 0x40000>;
> + compatible = "chrp,open-pic";
> + device_type = "open-pic";
> + };
> +
> + msi@41600 {
> + compatible = "fsl,p1020-msi", "fsl,mpic-msi";
> + reg = <0x41600 0x80>;
> + msi-available-ranges = <0 0x100>;
> + interrupts = <
> + 0xe0 0
> + 0xe1 0
> + 0xe2 0
> + 0xe3 0
> + 0xe4 0
> + 0xe5 0
> + 0xe6 0
> + 0xe7 0>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + global-utilities@e0000 { //global utilities block
> + compatible = "fsl,p1020-guts";
> + reg = <0xe0000 0x1000>;
> + fsl,has-rstcr;
> + };
> + };
> +
> + pci0: pcie@ffe09000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe09000 0 0x1000>;
> + bus-range = <0 255>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + pci1: pcie@ffe0a000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe0a000 0 0x1000>;
> + bus-range = <0 255>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +};
> --
> 1.7.3
>
>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply
* Re: halt/reset on assert?
From: Benjamin Herrenschmidt @ 2011-04-07 7:55 UTC (permalink / raw)
To: Evan Lavelle; +Cc: linuxppc-dev, Andreas Schwab
In-Reply-To: <4D9C6413.8030103@cyconix.com>
On Wed, 2011-04-06 at 14:01 +0100, Evan Lavelle wrote:
> #define MY_ASSERT(expr) if(!(expr)) BUG()
Make it
#define MY_ASSERT(expr) do { if .... } while(0)
To ensure it has proper single statement semantics in C.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Free up some CPU feature bits by moving out MMU-related features
From: Kumar Gala @ 2011-04-07 7:06 UTC (permalink / raw)
To: Matt Evans; +Cc: linuxppc-dev
In-Reply-To: <4D9D5042.6080500@ozlabs.org>
On Apr 7, 2011, at 12:48 AM, Matt Evans wrote:
> diff --git a/arch/powerpc/include/asm/cputable.h =
b/arch/powerpc/include/asm/cputable.h
> index be3cdf9..7b0fe7c 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -178,22 +178,15 @@ extern const char *powerpc_base_platform;
> #define LONG_ASM_CONST(x) 0
> #endif
>=20
> -#define CPU_FTR_SLB =
LONG_ASM_CONST(0x0000000100000000)
> -#define CPU_FTR_16M_PAGE =
LONG_ASM_CONST(0x0000000200000000)
> -#define CPU_FTR_TLBIEL =
LONG_ASM_CONST(0x0000000400000000)
> #define CPU_FTR_IABR =
LONG_ASM_CONST(0x0000002000000000)
> #define CPU_FTR_MMCRA =
LONG_ASM_CONST(0x0000004000000000)
> #define CPU_FTR_CTRL =
LONG_ASM_CONST(0x0000008000000000)
> #define CPU_FTR_SMT =
LONG_ASM_CONST(0x0000010000000000)
> -#define CPU_FTR_LOCKLESS_TLBIE =
LONG_ASM_CONST(0x0000040000000000)
> -#define CPU_FTR_CI_LARGE_PAGE =
LONG_ASM_CONST(0x0000100000000000)
> #define CPU_FTR_PAUSE_ZERO =
LONG_ASM_CONST(0x0000200000000000)
> #define CPU_FTR_PURR =
LONG_ASM_CONST(0x0000400000000000)
> #define CPU_FTR_CELL_TB_BUG =
LONG_ASM_CONST(0x0000800000000000)
> #define CPU_FTR_SPURR =
LONG_ASM_CONST(0x0001000000000000)
> #define CPU_FTR_DSCR =
LONG_ASM_CONST(0x0002000000000000)
> -#define CPU_FTR_1T_SEGMENT =
LONG_ASM_CONST(0x0004000000000000)
> -#define CPU_FTR_NO_SLBIE_B =
LONG_ASM_CONST(0x0008000000000000)
> #define CPU_FTR_VSX =
LONG_ASM_CONST(0x0010000000000000)
> #define CPU_FTR_SAO =
LONG_ASM_CONST(0x0020000000000000)
> #define CPU_FTR_CP_USE_DCBTZ =
LONG_ASM_CONST(0x0040000000000000)
> @@ -205,9 +198,10 @@ extern const char *powerpc_base_platform;
Seems like SAO should move into MMU features
- k=
^ permalink raw reply
* [PATCH] powerpc/85xx: P1020 DTS : re-organize dts files
From: Prabhakar Kushwaha @ 2011-04-07 6:25 UTC (permalink / raw)
To: linuxppc-dev, devicetree-discuss; +Cc: meet2prabhu, B11780, Prabhakar Kushwaha
Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts
files for P1020 based systems to use dtsi file.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Kumar Gala <kumar.gala@freescale.com>
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branch master)
Please see mpc5200b.dtsi for reference.
Tested on P1020RDB
arch/powerpc/boot/dts/p1020rdb.dts | 315 +-----------------------------
arch/powerpc/boot/dts/p1020si.dtsi | 378 ++++++++++++++++++++++++++++++++++++
2 files changed, 380 insertions(+), 313 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1020si.dtsi
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index e0668f8..8ae5ddf 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,12 +9,10 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "p1020si.dtsi"
+
/ {
- model = "fsl,P1020";
compatible = "fsl,P1020RDB";
- #address-cells = <2>;
- #size-cells = <2>;
aliases {
serial0 = &serial0;
@@ -26,34 +24,11 @@
pci1 = &pci1;
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,P1020@0 {
- device_type = "cpu";
- reg = <0x0>;
- next-level-cache = <&L2>;
- };
-
- PowerPC,P1020@1 {
- device_type = "cpu";
- reg = <0x1>;
- next-level-cache = <&L2>;
- };
- };
-
memory {
device_type = "memory";
};
localbus@ffe05000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
- reg = <0 0xffe05000 0 0x1000>;
- interrupts = <19 2>;
- interrupt-parent = <&mpic>;
/* NOR, NAND Flashes and Vitesse 5 port L2 switch */
ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,88 +140,14 @@
};
soc@ffe00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "fsl,p1020-immr", "simple-bus";
- ranges = <0x0 0x0 0xffe00000 0x100000>;
- bus-frequency = <0>; // Filled out by uboot.
-
- ecm-law@0 {
- compatible = "fsl,ecm-law";
- reg = <0x0 0x1000>;
- fsl,num-laws = <12>;
- };
-
- ecm@1000 {
- compatible = "fsl,p1020-ecm", "fsl,ecm";
- reg = <0x1000 0x1000>;
- interrupts = <16 2>;
- interrupt-parent = <&mpic>;
- };
-
- memory-controller@2000 {
- compatible = "fsl,p1020-memory-controller";
- reg = <0x2000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
-
i2c@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
-
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <0>;
- interrupts = <42 2>;
- interrupt-parent = <&mpic>;
- };
-
spi@7000 {
- cell-index = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,espi";
- reg = <0x7000 0x1000>;
- interrupts = <59 0x2>;
- interrupt-parent = <&mpic>;
- mode = "cpu";
fsl_m25p80@0 {
#address-cells = <1>;
@@ -294,66 +195,7 @@
};
};
- gpio: gpio-controller@f000 {
- #gpio-cells = <2>;
- compatible = "fsl,mpc8572-gpio";
- reg = <0xf000 0x100>;
- interrupts = <47 0x2>;
- interrupt-parent = <&mpic>;
- gpio-controller;
- };
-
- L2: l2-cache-controller@20000 {
- compatible = "fsl,p1020-l2-cache-controller";
- reg = <0x20000 0x1000>;
- cache-line-size = <32>; // 32 bytes
- cache-size = <0x40000>; // L2,256K
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
- };
-
- dma@21300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,eloplus-dma";
- reg = <0x21300 0x4>;
- ranges = <0x0 0x21100 0x200>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x0 0x80>;
- cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <20 2>;
- };
- dma-channel@80 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x80 0x80>;
- cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <21 2>;
- };
- dma-channel@100 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x100 0x80>;
- cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <22 2>;
- };
- dma-channel@180 {
- compatible = "fsl,eloplus-dma-channel";
- reg = <0x180 0x80>;
- cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <23 2>;
- };
- };
-
mdio@24000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-mdio";
- reg = <0x24000 0x1000 0xb0030 0x4>;
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
@@ -369,10 +211,6 @@
};
mdio@25000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,etsec2-tbi";
- reg = <0x25000 0x1000 0xb1030 0x4>;
tbi0: tbi-phy@11 {
reg = <0x11>;
@@ -381,97 +219,25 @@
};
enet0: ethernet@b0000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb0000 0x1000>;
- interrupts = <29 2 30 2 34 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb4000 0x1000>;
- interrupts = <17 2 18 2 24 2>;
- };
};
enet1: ethernet@b1000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb1000 0x1000>;
- interrupts = <35 2 36 2 40 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb5000 0x1000>;
- interrupts = <51 2 52 2 67 2>;
- };
};
enet2: ethernet@b2000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "fsl,etsec2";
- fsl,num_rx_queues = <0x8>;
- fsl,num_tx_queues = <0x8>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb2000 0x1000>;
- interrupts = <31 2 32 2 33 2>;
- };
-
- queue-group@1 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0xb6000 0x1000>;
- interrupts = <25 2 26 2 27 2>;
- };
};
usb@22000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl-usb2-dr";
- reg = <0x22000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <28 0x2>;
phy_type = "ulpi";
};
@@ -481,82 +247,15 @@
it enables USB2. OTOH, U-Boot does create a new node
when there isn't any. So, just comment it out.
usb@23000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl-usb2-dr";
- reg = <0x23000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <46 0x2>;
phy_type = "ulpi";
};
*/
- sdhci@2e000 {
- compatible = "fsl,p1020-esdhc", "fsl,esdhc";
- reg = <0x2e000 0x1000>;
- interrupts = <72 0x2>;
- interrupt-parent = <&mpic>;
- /* Filled in by U-Boot */
- clock-frequency = <0>;
- };
-
- crypto@30000 {
- compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
- "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
- reg = <0x30000 0x10000>;
- interrupts = <45 2 58 2>;
- interrupt-parent = <&mpic>;
- fsl,num-channels = <4>;
- fsl,channel-fifo-len = <24>;
- fsl,exec-units-mask = <0xbfe>;
- fsl,descriptor-types-mask = <0x3ab0ebf>;
- };
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x40000 0x40000>;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- };
-
- msi@41600 {
- compatible = "fsl,p1020-msi", "fsl,mpic-msi";
- reg = <0x41600 0x80>;
- msi-available-ranges = <0 0x100>;
- interrupts = <
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0>;
- interrupt-parent = <&mpic>;
- };
-
- global-utilities@e0000 { //global utilities block
- compatible = "fsl,p1020-guts";
- reg = <0xe0000 0x1000>;
- fsl,has-rstcr;
- };
};
pci0: pcie@ffe09000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0 0xffe09000 0 0x1000>;
- bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
@@ -573,18 +272,8 @@
};
pci1: pcie@ffe0a000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0 0xffe0a000 0 0x1000>;
- bus-range = <0 255>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
new file mode 100644
index 0000000..7b87d00
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020si.dtsi
@@ -0,0 +1,378 @@
+/*
+ * P1020si Device Tree Source
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P1020";
+ compatible = "fsl,P1020";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P1020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P1020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ localbus@ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p1020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p1020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <16 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p1020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p1020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2,256K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ mdio@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-mdio";
+ reg = <0x24000 0x1000 0xb0030 0x4>;
+
+ };
+
+ mdio@25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,etsec2-tbi";
+ reg = <0x25000 0x1000 0xb1030 0x4>;
+
+ };
+
+ enet0: ethernet@b0000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb0000 0x1000>;
+ interrupts = <29 2 30 2 34 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb4000 0x1000>;
+ interrupts = <17 2 18 2 24 2>;
+ };
+ };
+
+ enet1: ethernet@b1000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb1000 0x1000>;
+ interrupts = <35 2 36 2 40 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb5000 0x1000>;
+ interrupts = <51 2 52 2 67 2>;
+ };
+ };
+
+ enet2: ethernet@b2000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "fsl,etsec2";
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupt-parent = <&mpic>;
+
+ queue-group@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb2000 0x1000>;
+ interrupts = <31 2 32 2 33 2>;
+ };
+
+ queue-group@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb6000 0x1000>;
+ interrupts = <25 2 26 2 27 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ };
+
+ /* USB2 is shared with localbus, so it must be disabled
+ by default. We can't put 'status = "disabled";' here
+ since U-Boot doesn't clear the status property when
+ it enables USB2. OTOH, U-Boot does create a new node
+ when there isn't any. So, just comment it out.
+ usb@23000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x23000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <46 0x2>;
+ phy_type = "ulpi";
+ };
+ */
+
+ sdhci@2e000 {
+ compatible = "fsl,p1020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi@41600 {
+ compatible = "fsl,p1020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,p1020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ pci1: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+};
--
1.7.3
^ permalink raw reply related
* [PATCH] powerpc: Free up some CPU feature bits by moving out MMU-related features
From: Matt Evans @ 2011-04-07 5:48 UTC (permalink / raw)
To: linuxppc-dev
Some of the 64bit PPC CPU features are MMU-related, so this patch moves
them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to
mmu_has_feature(), and seven feature bits are freed as a result.
Signed-off-by: Matt Evans <matt@ozlabs.org>
---
Boot-tested on pseries and G5.
arch/powerpc/include/asm/cputable.h | 52 ++++++++++++++-------------
arch/powerpc/include/asm/mmu.h | 28 +++++++++++++++
arch/powerpc/include/asm/mmu_context.h | 2 +-
arch/powerpc/kernel/cputable.c | 39 ++++++++++-----------
arch/powerpc/kernel/entry_64.S | 8 ++--
arch/powerpc/kernel/exceptions-64s.S | 4 +-
arch/powerpc/kernel/process.c | 4 +-
arch/powerpc/kernel/prom.c | 17 +++++----
arch/powerpc/kernel/setup_64.c | 2 +-
arch/powerpc/mm/hash_low_64.S | 8 ++--
arch/powerpc/mm/hash_native_64.c | 8 ++--
arch/powerpc/mm/hash_utils_64.c | 18 +++++-----
arch/powerpc/mm/hugetlbpage.c | 2 +-
arch/powerpc/mm/slb.c | 4 +-
arch/powerpc/mm/slb_low.S | 8 ++--
arch/powerpc/mm/stab.c | 2 +-
arch/powerpc/platforms/iseries/exception.S | 2 +-
arch/powerpc/platforms/iseries/setup.c | 4 +-
arch/powerpc/platforms/pseries/lpar.c | 2 +-
arch/powerpc/xmon/xmon.c | 2 +-
20 files changed, 123 insertions(+), 93 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index be3cdf9..7b0fe7c 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -178,22 +178,15 @@ extern const char *powerpc_base_platform;
#define LONG_ASM_CONST(x) 0
#endif
-#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
-#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
-#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
-#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
@@ -205,9 +198,10 @@ extern const char *powerpc_base_platform;
#ifndef __ASSEMBLY__
-#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
- CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
- CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
+#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+
+#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
+ MMU_FTR_16M_PAGE)
/* We only set the altivec features if the kernel was compiled with altivec
* support
@@ -405,41 +399,49 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
- CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
- CPU_FTR_POPCNTB)
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
+ CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
- CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
- CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | CPU_FTR_SPURR | \
+ CPU_FTR_REAL_LE | CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
- CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
- CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | CPU_FTR_SPURR | \
+ CPU_FTR_REAL_LE | CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
- CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
- CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
+ CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
CPU_FTR_UNALIGNED_LD_STD)
#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | \
- CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
- CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
+ CPU_FTR_ALTIVEC_COMP | CPU_FTR_PURR | CPU_FTR_REAL_LE)
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
+/* MMU feature bit sets for various CPUs */
+#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
+ MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
+#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
+#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
+#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
+#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | \
+ MMU_FTR_TLBIE_206
+#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+ MMU_FTR_CI_LARGE_PAGE
+#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
+ MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
+
#ifdef __powerpc64__
#define CPU_FTRS_POSSIBLE \
(CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
- CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
- CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
+ CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_VSX)
#else
enum {
CPU_FTRS_POSSIBLE =
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index bb40a06..388189e 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -70,6 +70,34 @@
*/
#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
+/* MMU is SLB-based
+ */
+#define MMU_FTR_SLB ASM_CONST(0x02000000)
+
+/* Support 16M large pages
+ */
+#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
+
+/* Supports TLBIEL variant
+ */
+#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
+
+/* Supports tlbies w/o locking
+ */
+#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
+
+/* Large pages can be marked CI
+ */
+#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
+
+/* 1T segments available
+ */
+#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
+
+/* Doesn't support the B bit (1T segment) in SLBIE
+ */
+#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
+
#ifndef __ASSEMBLY__
#include <asm/cputable.h>
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index 81fb412..8e13f65 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -67,7 +67,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* sub architectures.
*/
#ifdef CONFIG_PPC_STD_MMU_64
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
switch_slb(tsk, next);
else
switch_stab(tsk, next);
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index c9b68d0..387c549 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -199,7 +199,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER4 (gp)",
.cpu_features = CPU_FTRS_POWER4,
.cpu_user_features = COMMON_USER_POWER4,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER4,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -214,7 +214,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER4+ (gq)",
.cpu_features = CPU_FTRS_POWER4,
.cpu_user_features = COMMON_USER_POWER4,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER4,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -230,7 +230,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_PPC970,
.cpu_user_features = COMMON_USER_POWER4 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PPC970,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -248,7 +248,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_PPC970,
.cpu_user_features = COMMON_USER_POWER4 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PPC970,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -284,7 +284,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_PPC970,
.cpu_user_features = COMMON_USER_POWER4 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PPC970,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -302,7 +302,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_PPC970,
.cpu_user_features = COMMON_USER_POWER4 |
PPC_FEATURE_HAS_ALTIVEC_COMP,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PPC970,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 8,
@@ -318,7 +318,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER5 (gr)",
.cpu_features = CPU_FTRS_POWER5,
.cpu_user_features = COMMON_USER_POWER5,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER5,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -338,7 +338,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER5+ (gs)",
.cpu_features = CPU_FTRS_POWER5,
.cpu_user_features = COMMON_USER_POWER5_PLUS,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER5,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -354,7 +354,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER5+ (gs)",
.cpu_features = CPU_FTRS_POWER5,
.cpu_user_features = COMMON_USER_POWER5_PLUS,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER5,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -371,7 +371,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER5+",
.cpu_features = CPU_FTRS_POWER5,
.cpu_user_features = COMMON_USER_POWER5_PLUS,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER5,
.icache_bsize = 128,
.dcache_bsize = 128,
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
@@ -385,7 +385,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_features = CPU_FTRS_POWER6,
.cpu_user_features = COMMON_USER_POWER6 |
PPC_FEATURE_POWER6_EXT,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER6,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -404,7 +404,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER6 (architected)",
.cpu_features = CPU_FTRS_POWER6,
.cpu_user_features = COMMON_USER_POWER6,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_POWER6,
.icache_bsize = 128,
.dcache_bsize = 128,
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
@@ -417,8 +417,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7 (architected)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
.oprofile_type = PPC_OPROFILE_POWER4,
@@ -431,8 +430,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7 (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -447,8 +445,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER7+ (raw)",
.cpu_features = CPU_FTRS_POWER7,
.cpu_user_features = COMMON_USER_POWER7,
- .mmu_features = MMU_FTR_HPTE_TABLE |
- MMU_FTR_TLBIE_206,
+ .mmu_features = MMU_FTRS_POWER7,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
@@ -465,7 +462,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_user_features = COMMON_USER_PPC64 |
PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
PPC_FEATURE_SMT,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_CELL,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 4,
@@ -480,7 +477,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "PA6T",
.cpu_features = CPU_FTRS_PA6T,
.cpu_user_features = COMMON_USER_PA6T,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_PA6T,
.icache_bsize = 64,
.dcache_bsize = 64,
.num_pmcs = 6,
@@ -497,7 +494,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = "POWER4 (compatible)",
.cpu_features = CPU_FTRS_COMPATIBLE,
.cpu_user_features = COMMON_USER_PPC64,
- .mmu_features = MMU_FTR_HPTE_TABLE,
+ .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
.icache_bsize = 128,
.dcache_bsize = 128,
.num_pmcs = 6,
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index d82878c..32c2605 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -462,10 +462,10 @@ BEGIN_FTR_SECTION
FTR_SECTION_ELSE_NESTED(95)
clrrdi r6,r8,40 /* get its 1T ESID */
clrrdi r9,r1,40 /* get current sp 1T ESID */
- ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95)
+ ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
FTR_SECTION_ELSE
b 2f
-ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
clrldi. r0,r6,2 /* is new ESID c00000000? */
cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
cror eq,4*cr1+eq,eq
@@ -479,7 +479,7 @@ BEGIN_FTR_SECTION
li r9,MMU_SEGSIZE_1T /* insert B field */
oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
/* Update the last bolted SLB. No write barriers are needed
* here, provided we only update the current CPU's SLB shadow
@@ -491,7 +491,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
- /* No need to check for CPU_FTR_NO_SLBIE_B here, since when
+ /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
* we have 1TB segments, the only CPUs known to have the errata
* only support less than 1TB of system memory and we'll never
* actually hit this code path.
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index c532cb2..2279294 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -74,7 +74,7 @@ BEGIN_FTR_SECTION
EXCEPTION_PROLOG_PSERIES_1(data_access_common)
FTR_SECTION_ELSE
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
-ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
. = 0x380
.globl data_access_slb_pSeries
@@ -750,7 +750,7 @@ _STATIC(do_hash_page)
BEGIN_FTR_SECTION
andis. r0,r4,0x0020 /* Is it a segment table fault? */
bne- do_ste_alloc /* If so handle it */
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
clrrdi r11,r1,THREAD_SHIFT
lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index f74f355..65c3802 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -755,11 +755,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
_ALIGN_UP(sizeof(struct thread_info), 16);
#ifdef CONFIG_PPC_STD_MMU_64
- if (cpu_has_feature(CPU_FTR_SLB)) {
+ if (mmu_has_feature(MMU_FTR_SLB)) {
unsigned long sp_vsid;
unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
- if (cpu_has_feature(CPU_FTR_1T_SEGMENT))
+ if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
<< SLB_VSID_SHIFT_1T;
else
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 05b7139..b48b04f 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -123,18 +123,19 @@ static void __init move_device_tree(void)
*/
static struct ibm_pa_feature {
unsigned long cpu_features; /* CPU_FTR_xxx bit */
+ unsigned long mmu_features; /* MMU_FTR_xxx bit */
unsigned int cpu_user_ftrs; /* PPC_FEATURE_xxx bit */
unsigned char pabyte; /* byte number in ibm,pa-features */
unsigned char pabit; /* bit number (big-endian) */
unsigned char invert; /* if 1, pa bit set => clear feature */
} ibm_pa_features[] __initdata = {
- {0, PPC_FEATURE_HAS_MMU, 0, 0, 0},
- {0, PPC_FEATURE_HAS_FPU, 0, 1, 0},
- {CPU_FTR_SLB, 0, 0, 2, 0},
- {CPU_FTR_CTRL, 0, 0, 3, 0},
- {CPU_FTR_NOEXECUTE, 0, 0, 6, 0},
- {CPU_FTR_NODSISRALIGN, 0, 1, 1, 1},
- {CPU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0},
+ {0, 0, PPC_FEATURE_HAS_MMU, 0, 0, 0},
+ {0, 0, PPC_FEATURE_HAS_FPU, 0, 1, 0},
+ {0, MMU_FTR_SLB, 0, 0, 2, 0},
+ {CPU_FTR_CTRL, 0, 0, 0, 3, 0},
+ {CPU_FTR_NOEXECUTE, 0, 0, 0, 6, 0},
+ {CPU_FTR_NODSISRALIGN, 0, 0, 1, 1, 1},
+ {0, MMU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0},
{CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0},
};
@@ -166,9 +167,11 @@ static void __init scan_features(unsigned long node, unsigned char *ftrs,
if (bit ^ fp->invert) {
cur_cpu_spec->cpu_features |= fp->cpu_features;
cur_cpu_spec->cpu_user_features |= fp->cpu_user_ftrs;
+ cur_cpu_spec->mmu_features |= fp->mmu_features;
} else {
cur_cpu_spec->cpu_features &= ~fp->cpu_features;
cur_cpu_spec->cpu_user_features &= ~fp->cpu_user_ftrs;
+ cur_cpu_spec->mmu_features &= ~fp->mmu_features;
}
}
}
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 5a0401f..2902f48 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -425,7 +425,7 @@ void __init setup_system(void)
static u64 slb0_limit(void)
{
- if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
+ if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
return 1UL << SID_SHIFT_1T;
}
return 1UL << SID_SHIFT;
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 3079f6b..36def97 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -118,7 +118,7 @@ _GLOBAL(__hash_page_4K)
BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
/* Calc va and put it in r29 */
rldicr r29,r5,28,63-28
rldicl r3,r3,0,36
@@ -401,7 +401,7 @@ _GLOBAL(__hash_page_4K)
BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
/* Calc va and put it in r29 */
rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */
rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */
@@ -715,7 +715,7 @@ BEGIN_FTR_SECTION
andi. r0,r31,_PAGE_NO_CACHE
/* If so, bail out and refault as a 4k page */
bne- ht64_bail_ok
-END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_CI_LARGE_PAGE)
/* Prepare new PTE value (turn access RW into DIRTY, then
* add BUSY and ACCESSED)
*/
@@ -736,7 +736,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
BEGIN_FTR_SECTION
cmpdi r9,0 /* check segment size */
bne 3f
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
/* Calc va and put it in r29 */
rldicr r29,r5,28,63-28
rldicl r3,r3,0,36
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 784a400..c23eef2 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -98,8 +98,8 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize)
static inline void tlbie(unsigned long va, int psize, int ssize, int local)
{
- unsigned int use_local = local && cpu_has_feature(CPU_FTR_TLBIEL);
- int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+ unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
+ int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
if (use_local)
use_local = mmu_psize_defs[psize].tlbiel;
@@ -503,7 +503,7 @@ static void native_flush_hash_range(unsigned long number, int local)
} pte_iterate_hashed_end();
}
- if (cpu_has_feature(CPU_FTR_TLBIEL) &&
+ if (mmu_has_feature(MMU_FTR_TLBIEL) &&
mmu_psize_defs[psize].tlbiel && local) {
asm volatile("ptesync":::"memory");
for (i = 0; i < number; i++) {
@@ -517,7 +517,7 @@ static void native_flush_hash_range(unsigned long number, int local)
}
asm volatile("ptesync":::"memory");
} else {
- int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+ int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
if (lock_tlbie)
raw_spin_lock(&native_tlbie_lock);
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index a5991fa..2f0b834 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -258,11 +258,11 @@ static int __init htab_dt_scan_seg_sizes(unsigned long node,
for (; size >= 4; size -= 4, ++prop) {
if (prop[0] == 40) {
DBG("1T segment support detected\n");
- cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
+ cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
return 1;
}
}
- cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
+ cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
return 0;
}
@@ -288,7 +288,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
if (prop != NULL) {
DBG("Page sizes from device-tree:\n");
size /= 4;
- cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
+ cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
while(size > 0) {
unsigned int shift = prop[0];
unsigned int slbenc = prop[1];
@@ -316,7 +316,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
break;
case 0x18:
idx = MMU_PAGE_16M;
- cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
+ cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
break;
case 0x22:
idx = MMU_PAGE_16G;
@@ -411,7 +411,7 @@ static void __init htab_init_page_sizes(void)
* Not in the device-tree, let's fallback on known size
* list for 16M capable GP & GR
*/
- if (cpu_has_feature(CPU_FTR_16M_PAGE))
+ if (mmu_has_feature(MMU_FTR_16M_PAGE))
memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
sizeof(mmu_psize_defaults_gp));
found:
@@ -441,7 +441,7 @@ static void __init htab_init_page_sizes(void)
mmu_vmalloc_psize = MMU_PAGE_64K;
if (mmu_linear_psize == MMU_PAGE_4K)
mmu_linear_psize = MMU_PAGE_64K;
- if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
+ if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
/*
* Don't use 64k pages for ioremap on pSeries, since
* that would stop us accessing the HEA ethernet.
@@ -598,7 +598,7 @@ static void __init htab_initialize(void)
/* Initialize page sizes */
htab_init_page_sizes();
- if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
+ if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
mmu_kernel_ssize = MMU_SEGSIZE_1T;
mmu_highuser_ssize = MMU_SEGSIZE_1T;
printk(KERN_INFO "Using 1TB segments\n");
@@ -739,7 +739,7 @@ void __init early_init_mmu(void)
/* Initialize stab / SLB management except on iSeries
*/
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
slb_initialize();
else if (!firmware_has_feature(FW_FEATURE_ISERIES))
stab_initialize(get_paca()->stab_real);
@@ -756,7 +756,7 @@ void __cpuinit early_init_mmu_secondary(void)
* in real mode on pSeries and we want a virutal address on
* iSeries anyway
*/
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
slb_initialize();
else
stab_initialize(get_paca()->stab_addr);
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 9bb249c..0b9a5c1 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -529,7 +529,7 @@ static int __init hugetlbpage_init(void)
{
int psize;
- if (!cpu_has_feature(CPU_FTR_16M_PAGE))
+ if (!mmu_has_feature(MMU_FTR_16M_PAGE))
return -ENODEV;
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 1d98ecc..3657531 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -166,7 +166,7 @@ static inline int esids_match(unsigned long addr1, unsigned long addr2)
int esid_1t_count;
/* System is not 1T segment size capable. */
- if (!cpu_has_feature(CPU_FTR_1T_SEGMENT))
+ if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
return (GET_ESID(addr1) == GET_ESID(addr2));
esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
@@ -201,7 +201,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
*/
hard_irq_disable();
offset = get_paca()->slb_cache_ptr;
- if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) &&
+ if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
offset <= SLB_CACHE_ENTRIES) {
int i;
asm volatile("isync" : : : "memory");
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 95ce355..ef653dc 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -58,7 +58,7 @@ _GLOBAL(slb_miss_kernel_load_linear)
li r11,0
BEGIN_FTR_SECTION
b slb_finish_load
-END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
b slb_finish_load_1T
1:
@@ -87,7 +87,7 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
6:
BEGIN_FTR_SECTION
b slb_finish_load
-END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -138,11 +138,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
ld r9,PACACONTEXTID(r13)
BEGIN_FTR_SECTION
cmpldi r10,0x1000
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
rldimi r10,r9,USER_ESID_BITS,0
BEGIN_FTR_SECTION
bge slb_finish_load_1T
-END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
b slb_finish_load
8: /* invalid EA */
diff --git a/arch/powerpc/mm/stab.c b/arch/powerpc/mm/stab.c
index 446a018..41e3164 100644
--- a/arch/powerpc/mm/stab.c
+++ b/arch/powerpc/mm/stab.c
@@ -243,7 +243,7 @@ void __init stabs_alloc(void)
{
int cpu;
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
return;
for_each_possible_cpu(cpu) {
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index 32a56c6..703b1c9 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -157,7 +157,7 @@ BEGIN_FTR_SECTION
FTR_SECTION_ELSE
EXCEPTION_PROLOG_1(PACA_EXGEN)
EXCEPTION_PROLOG_ISERIES_1
-ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
+ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
b data_access_common
.do_stab_bolted_iSeries:
diff --git a/arch/powerpc/platforms/iseries/setup.c b/arch/powerpc/platforms/iseries/setup.c
index 2946ae1..81cb8d2 100644
--- a/arch/powerpc/platforms/iseries/setup.c
+++ b/arch/powerpc/platforms/iseries/setup.c
@@ -249,7 +249,7 @@ static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
unsigned long i;
unsigned long mem_blocks = 0;
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
max_entries);
else
@@ -634,7 +634,7 @@ static int __init iseries_probe(void)
hpte_init_iSeries();
/* iSeries does not support 16M pages */
- cur_cpu_spec->cpu_features &= ~CPU_FTR_16M_PAGE;
+ cur_cpu_spec->mmu_features &= ~MMU_FTR_16M_PAGE;
return 1;
}
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index ca5d589..6f0ed3a 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -573,7 +573,7 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
unsigned long i, pix, rc;
unsigned long flags = 0;
struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
- int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
+ int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
unsigned long param[9];
unsigned long va;
unsigned long hash, index, shift, hidx, slot;
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 33794c1..57500eb 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2663,7 +2663,7 @@ static void dump_stab(void)
void dump_segments(void)
{
- if (cpu_has_feature(CPU_FTR_SLB))
+ if (mmu_has_feature(MMU_FTR_SLB))
dump_slb();
else
dump_stab();
--
1.7.0.4
^ permalink raw reply related
* RE: known working sata_sil24.c setup on powerpc platforms?
From: Kushwaha Prabhakar-B32579 @ 2011-04-07 4:48 UTC (permalink / raw)
To: Leon Woestenberg
Cc: Linux PPC, Tejun Heo, Jeff Garzik, Moffett, Kyle D,
linux-ide@vger.kernel.org
In-Reply-To: <BANLkTinjn5nt4-0cSo6nUfG8Vt1UrL2Q0g@mail.gmail.com>
Hi Leon,
Can you please check p2020rdb.dts for IDSEL entries for pci0/1 node?
In order to work in legacy mode, IDSEL entries are required.=20
--Prabhakar
> -----Original Message-----
> From: linux-ide-owner@vger.kernel.org [mailto:linux-ide-
> owner@vger.kernel.org] On Behalf Of Leon Woestenberg
> Sent: Thursday, April 07, 2011 12:20 AM
> To: Jeff Garzik
> Cc: Moffett, Kyle D; Linux PPC; linux-ide@vger.kernel.org; Tejun Heo
> Subject: Re: known working sata_sil24.c setup on powerpc platforms?
>=20
> Hello Jeff, all,
>=20
> On Wed, Apr 6, 2011 at 8:12 PM, Jeff Garzik <jeff@garzik.org> wrote:
> > On 04/06/2011 01:48 PM, Moffett, Kyle D wrote:
> >> On Apr 06, 2011, at 13:00, Leon Woestenberg wrote:
> >>> after investigating problems with sata_sil24.c on a freescale p2020
> >>> soc, I wonder if this driver works on powerpc at all?
> >>>
> >>> Does anyone know of a working setup of sata_sil24 on a big endian
> >>> powerpc system?
> >>
> >> Our P2020 boards work fine with legacy PCI interrupts (I think it's a
> >> sil3124 over PCI-E); the only deficiency is that MSI does not seem to
> work.
> >>
> >
> > We've definitely had issues with sata_sil24 + MSI, also...
> >
> > sata_sil24 does work on big endian in general.
> >
>=20
> On my system, I have the contrary to Kyle's experience (thanks for
> sharing).
>=20
> PowerPC P2020RDB
> vanilla 2.6.38
> Sil3132 on mini-PCI Express card
>=20
>=20
> Enabling msi gets me further than disabling it (default).
>=20
> modprobe sata_sil
>=20
> [ 8.834613] sata_sil24 0001:03:00.0: version 1.1
> [ 8.885581] scsi0 : sata_sil24
> [ 8.901420] scsi1 : sata_sil24
> [ 8.904642] ata1: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0004000 irq 16
> [ 8.911961] ata2: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0006000 irq 16
> [ 11.095127] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
> [ 14.906986] eth0: no IPv6 routers present
> [ 16.099016] ata1.00: qc timeout (cmd 0xec)
> [ 16.103128] ata1.00: failed to IDENTIFY (I/O error, err_mask=3D0x4)
> [ 18.299050] ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
> [ 28.303026] ata1.00: qc timeout (cmd 0xec)
> [ 28.307139] ata1.00: failed to IDENTIFY (I/O error, err_mask=3D0x4)
> [ 28.313233] ata1: limiting SATA link speed to 1.5 Gbps
> [ 30.523059] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 10)
>=20
>=20
> modprobe sata_sil msi=3D1
>=20
> [ 92.984120] sata_sil24 0001:03:00.0: version 1.1
> [ 92.988897] irq: irq 0 on host /soc@ffe00000/msi@41600 mapped to
> virtual irq 41
> [ 92.996229] sata_sil24 0001:03:00.0: Using MSI
> [ 93.000675] sata_sil24 0001:03:00.0: enabling bus mastering
> [ 93.011628] scsi2 : sata_sil24
> [ 93.022463] scsi3 : sata_sil24
> [ 93.025695] ata3: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0004000 irq 41
> [ 93.033023] ata4: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0006000 irq 41
> [ 95.203029] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
> [ 95.209045] ata3: spurious interrupt (slot_stat 0x0 active_tag
> -84148995 sactive 0x0)
> [ 95.217171] ata3.00: ATA-7: INTEL SSDSA2M080G2GN, 2CV102HD, max
> UDMA/133
> [ 95.223882] ata3.00: 156301488 sectors, multi 1: LBA48 NCQ (depth
> 31/32)
> [ 95.230905] ata3.00: configured for UDMA/100
> [ 95.235399] scsi 2:0:0:0: Direct-Access ATA INTEL
> SSDSA2M080 2CV1 PQ: 0 ANSI: 5
> [ 95.244002] sd 2:0:0:0: Attached scsi generic sg0 type 0
> [ 95.252041] sd 2:0:0:0: [sda] 156301488 512-byte logical blocks:
> (80.0 GB/74.5 GiB)
> [ 95.260219] sd 2:0:0:0: [sda] Write Protect is off
> [ 95.265063] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00
> [ 95.270500] sd 2:0:0:0: [sda] Write cache: enabled, read cache:
> enabled, doesn't support DPO or FUA
> [ 95.283779] sda: sda1 sda2 sda3 sda4
> [ 95.289482] sd 2:0:0:0: [sda] Attached SCSI disk
> [ 95.965897] EXT3-fs: barriers not enabled
> [ 95.977279] kjournald starting. Commit interval 5 seconds
> [ 95.983296] EXT3-fs (sda2): using internal journal
> [ 95.988143] EXT3-fs (sda2): recovery complete
> [ 95.992504] EXT3-fs (sda2): mounted filesystem with writeback data
> mode
> [ 96.111587] NTFS volume version 3.1.
> [ 97.331005] ata4: SATA link down (SStatus 0 SControl 0)
>=20
> root@p1020rdb:~# dd if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D1000
> 1000+0 records in
> 1000+0 records out
> 4096000 bytes (4.1 MB) copied, 0.0315629 s, 130 MB/s root@p1020rdb:~# dd
> if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D10000
> 10000+0 records in
> 10000+0 records out
> 40960000 bytes (41 MB) copied, 0.471802 s, 86.8 MB/s
>=20
> root@p1020rdb:~# dd if=3D/dev/sda of=3D/dev/null bs=3D4k count=3D100000
>=20
> That stalls, I see the controller fail. See dmesg below:
>=20
> ^C^Cdd: reading `/dev/sda': Input/output error
> 51804+0 records in
> 51804+0 records out
> 212189184 bytes (212 MB) copied, 85.6537 s, 2.5 MB/s
> dd: closing input file `/dev/sda': Bad file descriptor
>=20
>=20
> [ 92.984120] sata_sil24 0001:03:00.0: version 1.1
> [ 92.988897] irq: irq 0 on host /soc@ffe00000/msi@41600 mapped to
> virtual irq 41
> [ 92.996229] sata_sil24 0001:03:00.0: Using MSI
> [ 93.000675] sata_sil24 0001:03:00.0: enabling bus mastering
> [ 93.011628] scsi2 : sata_sil24
> [ 93.022463] scsi3 : sata_sil24
> [ 93.025695] ata3: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0004000 irq 41
> [ 93.033023] ata4: SATA max UDMA/100 host m128@0xc0000000 port
> 0xc0006000 irq 41
> [ 95.203029] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 0)
> [ 95.209045] ata3: spurious interrupt (slot_stat 0x0 active_tag
> -84148995 sactive 0x0)
> [ 95.217171] ata3.00: ATA-7: INTEL SSDSA2M080G2GN, 2CV102HD, max
> UDMA/133
> [ 95.223882] ata3.00: 156301488 sectors, multi 1: LBA48 NCQ (depth
> 31/32)
> [ 95.230905] ata3.00: configured for UDMA/100
> [ 95.235399] scsi 2:0:0:0: Direct-Access ATA INTEL
> SSDSA2M080 2CV1 PQ: 0 ANSI: 5
> [ 95.244002] sd 2:0:0:0: Attached scsi generic sg0 type 0
> [ 95.252041] sd 2:0:0:0: [sda] 156301488 512-byte logical blocks:
> (80.0 GB/74.5 GiB)
> [ 95.260219] sd 2:0:0:0: [sda] Write Protect is off
> [ 95.265063] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00
> [ 95.270500] sd 2:0:0:0: [sda] Write cache: enabled, read cache:
> enabled, doesn't support DPO or FUA
> [ 95.283779] sda: sda1 sda2 sda3 sda4
> [ 95.289482] sd 2:0:0:0: [sda] Attached SCSI disk
> [ 95.965897] EXT3-fs: barriers not enabled
> [ 95.977279] kjournald starting. Commit interval 5 seconds
> [ 95.983296] EXT3-fs (sda2): using internal journal
> [ 95.988143] EXT3-fs (sda2): recovery complete
> [ 95.992504] EXT3-fs (sda2): mounted filesystem with writeback data
> mode
> [ 96.111587] NTFS volume version 3.1.
> [ 97.331005] ata4: SATA link down (SStatus 0 SControl 0)
> [ 285.891036] ata3.00: exception Emask 0x0 SAct 0x3 SErr 0x0 action 0x6
> frozen [ 285.898099] ata3.00: failed command: READ FPDMA QUEUED [
> 285.903250] ata3.00: cmd 60/00:00:e0:53:06/01:00:00:00:00/40 tag 0 ncq
> 131072 in
> [ 285.903255] res 40/00:00:00:00:00/00:00:00:00:00/00 Emask
> 0x4 (timeout)
> [ 285.918028] ata3.00: status: { DRDY } [ 285.921689] ata3.00: failed
> command: READ FPDMA QUEUED [ 285.926836] ata3.00: cmd
> 60/00:08:e0:52:06/01:00:00:00:00/40 tag 1 ncq 131072 in
> [ 285.926841] res 40/00:00:00:00:00/00:00:00:00:00/00 Emask
> 0x4 (timeout)
> [ 285.941615] ata3.00: status: { DRDY } [ 285.945281] ata3: hard
> resetting link [ 288.055034] ata3: SATA link up 3.0 Gbps (SStatus 123
> SControl 0) [ 293.058999] ata3.00: qc timeout (cmd 0xec) [ 293.063106]
> ata3.00: failed to IDENTIFY (I/O error, err_mask=3D0x4) [ 293.069198]
> ata3.00: revalidation failed (errno=3D-5) [ 293.074077] ata3: hard
> resetting link [ 295.259018] ata3: SATA link up 3.0 Gbps (SStatus 123
> SControl 0)
>=20
> What can I do next to investigate and help fix this issue?
>=20
>=20
> Regards,
> --
> Leon
> --
> To unsubscribe from this list: send the line "unsubscribe linux-ide" in
> the body of a message to majordomo@vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
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