* Re: [PATCH] powerpc/85xx: add host-pci(e) bridge only for RC
From: Kumar Gala @ 2011-05-19 6:25 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: meet2prabhu, linuxppc-dev, Vivek Mahajan
In-Reply-To: <1303882532-25615-1-git-send-email-prabhakar@freescale.com>
On Apr 27, 2011, at 12:35 AM, Prabhakar Kushwaha wrote:
> FSL PCIe controller can act as agent(EP) or host(RC).
> Under Agent(EP) mode they are configured via Host. So it is not =
required to add
> with the PCI(e) sub-system.
>=20
> Add and configure PCIe controller only for RC mode.
>=20
> Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Based upon =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branc=
h master)
>=20
> arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++
> 1 files changed, 14 insertions(+), 0 deletions(-)
>=20
> diff --git a/arch/powerpc/sysdev/fsl_pci.c =
b/arch/powerpc/sysdev/fsl_pci.c
> index 68ca929..87ac11b 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -323,6 +323,7 @@ int __init fsl_add_bridge(struct device_node *dev, =
int is_primary)
> struct pci_controller *hose;
> struct resource rsrc;
> const int *bus_range;
> + u8 is_agent;
>=20
> if (!of_device_is_available(dev)) {
> pr_warning("%s: disabled\n", dev->full_name);
> @@ -353,6 +354,19 @@ int __init fsl_add_bridge(struct device_node =
*dev, int is_primary)
>=20
> setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> PPC_INDIRECT_TYPE_BIG_ENDIAN);
> +
> + early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &is_agent);
Why are we looking at PCI_HEADER_TYPE? We should look at =
PCI_CLASS_PROG.
> + if ((is_agent & 0x7f) =3D=3D PCI_HEADER_TYPE_NORMAL) {
> + u32 temp;
> +
> + temp =3D (u32)hose->cfg_data & ~PAGE_MASK;
> + if (((u32)hose->cfg_data & PAGE_MASK) !=3D =
(u32)hose->cfg_addr)
> + iounmap(hose->cfg_data - temp);
> + iounmap(hose->cfg_addr);
> + pcibios_free_controller(hose);
> + return 0;
> + }
> +
> setup_pci_cmd(hose);
>=20
> /* check PCI express link status */
> --=20
> 1.7.3
>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for PM
From: Kumar Gala @ 2011-05-19 6:30 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: meet2prabhu, linuxppc-dev, Jiang Yutang
In-Reply-To: <1303972729-32242-1-git-send-email-prabhakar@freescale.com>
On Apr 28, 2011, at 1:38 AM, Prabhakar Kushwaha wrote:
> D3-cold state indicates removal of the clock and power. however =
auxiliary (AUX)
> Power may remain available even after the main power rails are powered =
down.
>=20
> wakeup from D3-cold state requires full context restore. Other things =
are taken
> care in pci-driver except ATMUs.
> ATMU windows needs to be saved and restored during suspend and resume.
>=20
> Signed-off-by: Jiang Yutang <b14898@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Based upon =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branc=
h master)
>=20
> arch/powerpc/sysdev/fsl_pci.c | 116 =
+++++++++++++++++++++++++++++++++++++++++
> arch/powerpc/sysdev/fsl_pci.h | 7 ++-
> 2 files changed, 121 insertions(+), 2 deletions(-)
Is this patch for when we are a host or agent?
- k=
^ permalink raw reply
* Re: [PATCH] powerpc/85xx:Create dts of each core in CAMP mode for P1020RDB
From: Kumar Gala @ 2011-05-19 6:33 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: meet2prabhu, devicetree-discuss, linuxppc-dev
In-Reply-To: <1303974000-2943-1-git-send-email-prabhakar@freescale.com>
On Apr 28, 2011, at 2:00 AM, Prabhakar Kushwaha wrote:
> Create the dts files for each core and splits the devices between the =
two cores
> for P1020RDB.
>=20
> Core0 has core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb, =
eth1, eth2,
> sdhc, crypto, global-util, message, pci0, pci1, msi.
> Core1 has l2, eth0, crypto.
>=20
> MPIC is shared between two cores but each core will protect its =
interrupts from
> other core by using "protected-sources" of mpic.
>=20
> Fix compatible property for global-util node of P1020si.dtsi.
>=20
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Based upon =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(branc=
h master)
>=20
> This patch depends on following patch
> "powerpc/85xx: P1020 DTS : re-organize dts files"
>=20
> arch/powerpc/boot/dts/p1020rdb_camp_core0.dts | 213 =
+++++++++++++++++++++++++
> arch/powerpc/boot/dts/p1020rdb_camp_core1.dts | 148 +++++++++++++++++
> arch/powerpc/boot/dts/p1020si.dtsi | 2 +-
> 3 files changed, 362 insertions(+), 1 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
> create mode 100644 arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
applied to next
- k=
^ permalink raw reply
* Re: [PATCH] powerpc/qoriq: Add default mode for P1020RDB USB
From: Kumar Gala @ 2011-05-19 6:37 UTC (permalink / raw)
To: Ramneek Mehresh; +Cc: paulus, linuxppc-dev
In-Reply-To: <1304515616-3413-1-git-send-email-ramneek.mehresh@freescale.com>
On May 4, 2011, at 8:26 AM, Ramneek Mehresh wrote:
> Add P1020 USB controller default value for "dr_mode" property
>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> ---
> Applies on git://git.am.freescale.net/mirrors/linux-2.6.git
> (branch master)
> arch/powerpc/boot/dts/p1020rdb.dts | 10 ++++------
> 1 files changed, 4 insertions(+), 6 deletions(-)
Can you update the patch. Also make sure to update the p1020rdb_camp* .dts
Against git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
thanks
- k
^ permalink raw reply
* [PATCH][upstream] powerpc:Integrated Flash controller device tree bindings
From: Dipen Dudhat @ 2011-05-19 6:38 UTC (permalink / raw)
To: devicetree-discuss, linuxppc-dev; +Cc: linuxppc-dev
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-By: Scott Wood <scottwood@freescale.com>
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git (branch -> master)
.../devicetree/bindings/powerpc/fsl/ifc.txt | 76 ++++++++++++++++++++
1 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
new file mode 100644
index 0000000..939a26d
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
@@ -0,0 +1,76 @@
+Integrated Flash Controller
+
+Properties:
+- name : Should be ifc
+- compatible : should contain "fsl,ifc". The version of the integrated
+ flash controller can be found in the IFC_REV register at
+ offset zero.
+
+- #address-cells : Should be either two or three. The first cell is the
+ chipselect number, and the remaining cells are the
+ offset into the chipselect.
+- #size-cells : Either one or two, depending on how large each chipselect
+ can be.
+- reg : Offset and length of the register set for the device
+- interrupts : IFC has two interrupts. The first one is the "common"
+ interrupt(CM_EVTER_STAT), and second is the NAND interrupt
+ (NAND_EVTER_STAT).
+
+- ranges : Each range corresponds to a single chipselect, and covers
+ the entire access window as configured.
+
+Child device nodes describe the devices connected to IFC such as NOR (e.g.
+cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
+like FPGAs, CPLDs, etc.
+
+Example:
+
+ ifc@ffe1e000 {
+ compatible = "fsl,ifc", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ reg = <0x0 0xffe1e000 0 0x2000>;
+ interrupts = <16 2 19 2>;
+
+ /* NOR, NAND Flashes and CPLD on board */
+ ranges = <0x0 0x0 0x0 0xee000000 0x02000000
+ 0x1 0x0 0x0 0xffa00000 0x00010000
+ 0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+ flash@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x2000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ /* 32MB for user data */
+ reg = <0x0 0x02000000>;
+ label = "NOR Data";
+ };
+ };
+
+ flash@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x1 0x0 0x10000>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND U-Boot Image";
+ read-only;
+ };
+ };
+
+ cpld@3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p1010rdb-cpld";
+ reg = <0x3 0x0 0x000001f>;
+ };
+ };
--
1.5.6.5
^ permalink raw reply related
* Re: [linuxppc-dev] [PATCH][upstream] powerpc:Integrated Flash controller device tree bindings
From: Kumar Gala @ 2011-05-19 6:41 UTC (permalink / raw)
To: Dipen Dudhat; +Cc: linuxppc-dev, devicetree-discuss, linuxppc-dev
In-Reply-To: <1305787103-25105-1-git-send-email-Dipen.Dudhat@freescale.com>
On May 19, 2011, at 1:38 AM, Dipen Dudhat wrote:
> Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
> Acked-By: Scott Wood <scottwood@freescale.com>
> ---
> Based upon =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git =
(branch -> master)
> .../devicetree/bindings/powerpc/fsl/ifc.txt | 76 =
++++++++++++++++++++
> 1 files changed, 76 insertions(+), 0 deletions(-)
> create mode 100644 =
Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 19/37] powerpc: consolidate ipi message mux and demux
From: Benjamin Herrenschmidt @ 2011-05-19 6:57 UTC (permalink / raw)
To: Milton Miller; +Cc: linuxppc-dev
In-Reply-To: <b9e2ff2d16e4647af0047ddbf6146b6c7433ce6c.1305092637.git.miltonm@bga.com>
On Wed, 2011-05-11 at 00:29 -0500, Milton Miller wrote:
> Consolidate the mux and demux of ipi messages into smp.c and call
> a new smp_ops callback to actually trigger the ipi.
.../...
I'm merging the whole series. I had to do some fixups to this one and
the one adding the CONFIG option, missing cell & wsp bits among others,
but mostly trivial.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 19/37] powerpc: consolidate ipi message mux and demux
From: Benjamin Herrenschmidt @ 2011-05-19 6:58 UTC (permalink / raw)
To: Milton Miller; +Cc: linuxppc-dev
In-Reply-To: <1305788222.7481.46.camel@pasglop>
On Thu, 2011-05-19 at 16:57 +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2011-05-11 at 00:29 -0500, Milton Miller wrote:
> > Consolidate the mux and demux of ipi messages into smp.c and call
> > a new smp_ops callback to actually trigger the ipi.
>
> .../...
>
> I'm merging the whole series. I had to do some fixups to this one and
> the one adding the CONFIG option, missing cell & wsp bits among others,
> but mostly trivial.
I forgot to mention... I dropped the change to include/linux/smp.h to
remove the unused MSG_ flags for now. It will not have been in -next
long enough to hit Linus via my tree, just in case somebody started
using the flags while we were not looking :-)
I suggest you send it to Linus directly after he pulls my tree during
the merge window.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 5/8] powerpc: override dma_get_required_mask by platform hook and ops
From: Benjamin Herrenschmidt @ 2011-05-19 7:43 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: cbe-oss-dev, FUJITA Tomonori, Arnd Bergmann, Sonny Rao,
devicetree-discuss, linux-kernel, Milton Miller, Paul Mackerras,
Anton Blanchard, Will Schmidt, Andrew Morton, linuxppc-dev
In-Reply-To: <1305152704-4864-6-git-send-email-nacc@us.ibm.com>
On Wed, 2011-05-11 at 15:25 -0700, Nishanth Aravamudan wrote:
> From: Milton Miller <miltonm@bga.com>
>
> The hook dma_get_required_mask is supposed to return the mask required
> by the platform to operate efficently. The generic version of
> dma_get_required_mask in driver/base/platform.c returns a mask based
> only on max_pfn. However, this is likely too big for iommu systems
> and could be too small for platforms that require a dma offset or have
> a secondary window at a high offset.
The result of those 3 patches doesn't build on top of my current tree,
the generic dma_ops lacks the dma_get_required_mask hook. I'll have a
look again after the merge window.
Cheers,
Ben.
^ permalink raw reply
* RE: [PATCH 1/3] mpt2sas: remove the use of writeq, since writeq isnot atomic
From: David Laight @ 2011-05-19 8:35 UTC (permalink / raw)
To: James Bottomley, Hitoshi Mitake
Cc: linux-arch, Prakash, Sathya, Roland Dreier, Desai, Kashyap,
linux scsi dev, Matthew Wilcox, linux pci, linux powerpc dev,
Milton Miller, linux kernel, Sam Ravnborg, Ingo Molnar, paulus,
Ingo Molnar, Moore, Eric
In-Reply-To: <1305780360.2576.20.camel@mulgrave.site>
=20
> The specific mpt2sas problem is that if we write a 64 bit register non
> atomically, we can't allow any interleaving writes for any other
region
> on the chip, otherwise the HW will take the write as complete in the
64
> bit register and latch the wrong value. The only way to achieve that
> given the semantics of writeq is a global static spinlock.
That sounds like very specific and slightly dodgy hardware.
You don't say what the scope of 'region on the chip' is, but
it looks like you need to disable ALL writes to the memory
area between the first and second writes of the 64bit value
and not just those coming from writeq().
I don't see how this can possibly be done by normal mutexing
around the writeq() sequence, surely you need to lock the bus
between the two transfers.
Even dma writes would be a problem.
The only way I can think to stop other cpus doing writes
is to use IPIs for force them into a busy wait loop.
All rather reminds me of a PCI slave that got things
horribly wrong when a read was done while a write was
still 'posted', or a 2nd master did a cycle did a read
while a read rerun sequence was still in progress.
(required a mutex and dummy cycles).
At least than one wqs confined to one driver.
David
^ permalink raw reply
* Re: [PATCH 01/13] powerpc/e500: Save SPEFCSR in flush_spe_to_thread()
From: Alexander Graf @ 2011-05-19 9:38 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev, kvm-ppc
In-Reply-To: <DC207279-54AC-41CC-BF21-25181D16A6AB@kernel.crashing.org>
On 05/19/2011 08:04 AM, Kumar Gala wrote:
> On May 17, 2011, at 6:35 PM, Scott Wood wrote:
>
>> From: yu liu<yu.liu@freescale.com>
>>
>> giveup_spe() saves the SPE state which is protected by MSR[SPE].
>> However, modifying SPEFSCR does not trap when MSR[SPE]=0.
>> And since SPEFSCR is already saved/restored in _switch(),
>> not all the callers want to save SPEFSCR again.
>> Thus, saving SPEFSCR should not belong to giveup_spe().
>>
>> This patch moves SPEFSCR saving to flush_spe_to_thread(),
>> and cleans up the caller that needs to save SPEFSCR accordingly.
>>
>> Signed-off-by: Liu Yu<yu.liu@freescale.com>
>> Signed-off-by: Scott Wood<scottwood@freescale.com>
>> ---
>> This is a resending of http://patchwork.ozlabs.org/patch/88677/
>>
>> Kumar, please ack to go via kvm. This is holding up the rest of the SPE
>> patches, which in turn are holding up the MMU patches due to both
>> touching the MSR update code.
>>
>> arch/powerpc/kernel/head_fsl_booke.S | 2 --
>> arch/powerpc/kernel/process.c | 1 +
>> arch/powerpc/kernel/traps.c | 5 +----
>> 3 files changed, 2 insertions(+), 6 deletions(-)
> Acked-by: Kumar Gala<galak@kernel.crashing.org>
>
> [ Alex, let me know if you want this via my powerpc.git tree or your kvm tree ]
I'll take them :). Thanks!
Alex
^ permalink raw reply
* Re: [PATCH v2 0/7] Consolidate sdhci pltfm & OF drivers and get them self registered
From: Wolfram Sang @ 2011-05-19 9:40 UTC (permalink / raw)
To: Shawn Guo
Cc: Chris Ball, sameo, Arnd Bergmann, patches, devicetree-discuss,
linux-mmc, Saeed Bishara, Xiaobo Xie, kernel, Mike Rapoport,
Olof Johansson, Anton Vorontsov, linuxppc-dev, Albert Herranz,
linux-arm-kernel
In-Reply-To: <1304601778-13837-1-git-send-email-shawn.guo@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 1083 bytes --]
Hi Shawn,
> Changes since v1:
> * Rebase on cjb's mmc-next tree
Is it maybe possible that you get access to
http://opensource.freescale.com/git or another machine? A branch to pull
from would be more convenient, because the series does not apply to
mmc-next anymore, so an extra step to go "back in time" is needed.
(minor) When applying I got:
Applying: mmc: sdhci: make sdhci-pltfm device drivers self registered
/home/wsa/Kernel/linux-2.6/.git/rebase-apply/patch:384: trailing whitespace.
/home/wsa/Kernel/linux-2.6/.git/rebase-apply/patch:817: space before tab in indent.
struct tegra_sdhci_platform_data *plat;
/home/wsa/Kernel/linux-2.6/.git/rebase-apply/patch:867: trailing whitespace.
Applying: sdhci: rename sdhci-esdhc-imx.c to sdhci-esdhc.c
/home/wsa/Kernel/linux-2.6/.git/rebase-apply/patch:780: trailing whitespace.
See later comments for further issues.
Thanks,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* Re: [PATCH v2 5/7] mmc: sdhci: consolidate sdhci-of-esdhc and sdhci-esdhc-imx
From: Wolfram Sang @ 2011-05-19 9:48 UTC (permalink / raw)
To: Shawn Guo
Cc: Chris Ball, sameo, Arnd Bergmann, patches, devicetree-discuss,
linux-mmc, Saeed Bishara, Xiaobo Xie, kernel, Mike Rapoport,
Olof Johansson, Anton Vorontsov, linuxppc-dev, Albert Herranz,
linux-arm-kernel
In-Reply-To: <1304601778-13837-6-git-send-email-shawn.guo@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 949 bytes --]
> +config MMC_SDHCI_ESDHC
> + bool
> + depends on MMC_SDHCI
> + select MMC_SDHCI_PLTFM
> + help
> + This selects SDHCI driver for Freescale eSDHC controller.
bool is not a good choice here, because if ESDHC_IMX is selected as a
module (-m), it will get converted here to built-in (-y). Same goes for
MMC_SDHCI_PLTFM. If I change both into tristate and then compile, I get
a build error:
ERROR: "sdhci_pltfm_suspend" [drivers/mmc/host/sdhci-esdhc.ko] undefined!
ERROR: "sdhci_get_of_property" [drivers/mmc/host/sdhci-esdhc.ko] undefined!
ERROR: "sdhci_pltfm_init" [drivers/mmc/host/sdhci-esdhc.ko] undefined!
ERROR: "sdhci_pltfm_free" [drivers/mmc/host/sdhci-esdhc.ko] undefined!
So, the module-support seems to be missing for the library.
Regards,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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^ permalink raw reply
* Re: [PATCH 4/7] [RFC] enable L1_WRITETHROUGH mode for BG/P
From: Josh Boyer @ 2011-05-19 10:43 UTC (permalink / raw)
To: Eric Van Hensbergen; +Cc: linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <1305753895-24845-4-git-send-email-ericvh@gmail.com>
On Wed, May 18, 2011 at 04:24:52PM -0500, Eric Van Hensbergen wrote:
>BG/P nodes need to be configured for writethrough to work in SMP
>configurations. This patch adds the right hooks in the MMU code
>to make sure L1_WRITETHROUGH configurations are setup for BG/P.
>
>Signed-off-by: Eric Van Hensbergen <ericvh@gmail.com>
>---
> arch/powerpc/include/asm/mmu-44x.h | 2 ++
> arch/powerpc/kernel/head_44x.S | 24 ++++++++++++++++++++++--
> arch/powerpc/kernel/misc_32.S | 15 +++++++++++++++
> arch/powerpc/lib/copy_32.S | 10 ++++++++++
> arch/powerpc/mm/44x_mmu.c | 7 +++++--
> arch/powerpc/platforms/Kconfig | 5 +++++
> arch/powerpc/platforms/Kconfig.cputype | 4 ++++
> 7 files changed, 63 insertions(+), 4 deletions(-)
>
>diff --git a/arch/powerpc/include/asm/mmu-44x.h b/arch/powerpc/include/asm/mmu-44x.h
>index bf52d70..ca1b90c 100644
>--- a/arch/powerpc/include/asm/mmu-44x.h
>+++ b/arch/powerpc/include/asm/mmu-44x.h
>@@ -8,6 +8,7 @@
>
> #define PPC44x_MMUCR_TID 0x000000ff
> #define PPC44x_MMUCR_STS 0x00010000
>+#define PPC44x_MMUCR_U2 0x00200000
>
> #define PPC44x_TLB_PAGEID 0
> #define PPC44x_TLB_XLAT 1
>@@ -32,6 +33,7 @@
>
> /* Storage attribute and access control fields */
> #define PPC44x_TLB_ATTR_MASK 0x0000ff80
>+#define PPC44x_TLB_WL1 0x00100000 /* Write-through L1 */
> #define PPC44x_TLB_U0 0x00008000 /* User 0 */
> #define PPC44x_TLB_U1 0x00004000 /* User 1 */
> #define PPC44x_TLB_U2 0x00002000 /* User 2 */
>diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
>index 5e12b74..1f7ae60 100644
>--- a/arch/powerpc/kernel/head_44x.S
>+++ b/arch/powerpc/kernel/head_44x.S
>@@ -429,7 +429,16 @@ finish_tlb_load_44x:
> andi. r10,r12,_PAGE_USER /* User page ? */
> beq 1f /* nope, leave U bits empty */
> rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */
>-1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */
>+1:
>+#ifdef CONFIG_L1_WRITETHROUGH
>+ andi. r10, r11, PPC44x_TLB_I
>+ bne 2f
>+ oris r11,r11,PPC44x_TLB_WL1@h /* Add coherency for */
>+ /* non-inhibited */
>+ ori r11,r11,PPC44x_TLB_U2|PPC44x_TLB_M
>+2:
>+#endif /* CONFIG_L1_WRITETHROUGH */
>+ tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */
>
> /* Done...restore registers and get out of here.
> */
>@@ -799,7 +808,11 @@ skpinv: addi r4,r4,1 /* Increment */
> sync
>
> /* Initialize MMUCR */
>+#ifdef CONFIG_L1_WRITETHROUGH
>+ lis r5, PPC44x_MMUCR_U2@h
>+#else
> li r5,0
>+#endif /* CONFIG_L1_WRITETHROUGH */
> mtspr SPRN_MMUCR,r5
> sync
>
>@@ -814,7 +827,14 @@ skpinv: addi r4,r4,1 /* Increment */
> /* attrib fields */
> /* Added guarded bit to protect against speculative loads/stores */
> li r5,0
>- ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
>+#ifdef CONFIG_L1_WRITETHROUGH
>+ ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | \
>+ PPC44x_TLB_G | PPC44x_TLB_U2)
>+ oris r5,r5,PPC44x_TLB_WL1@h
>+#else
>+ ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | \
>+ PPC44x_TLB_G)
>+#endif /* CONFIG_L1_WRITETHROUGH
>
> li r0,63 /* TLB slot 63 */
>
>diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
>index 094bd98..d88369b 100644
>--- a/arch/powerpc/kernel/misc_32.S
>+++ b/arch/powerpc/kernel/misc_32.S
>@@ -506,7 +506,20 @@ _GLOBAL(clear_pages)
> li r0,PAGE_SIZE/L1_CACHE_BYTES
> slw r0,r0,r4
> mtctr r0
>+#ifdef CONFIG_L1_WRITETHROUGH
>+ /* assuming 32 byte cacheline */
>+ li r4, 0
>+1: stw r4, 0(r3)
>+ stw r4, 4(r3)
>+ stw r4, 8(r3)
>+ stw r4, 12(r3)
>+ stw r4, 16(r3)
>+ stw r4, 20(r3)
>+ stw r4, 24(r3)
>+ stw r4, 28(r3)
>+#else
> 1: dcbz 0,r3
>+#endif /* CONFIG_L1_WRITETHROUGH */
> addi r3,r3,L1_CACHE_BYTES
> bdnz 1b
> blr
>@@ -550,7 +563,9 @@ _GLOBAL(copy_page)
> mtctr r0
> 1:
> dcbt r11,r4
>+#ifndef CONFIG_L1_WRITETHROUGH
> dcbz r5,r3
>+#endif
> COPY_16_BYTES
> #if L1_CACHE_BYTES >= 32
> COPY_16_BYTES
>diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
>index 55f19f9..98a07e3 100644
>--- a/arch/powerpc/lib/copy_32.S
>+++ b/arch/powerpc/lib/copy_32.S
>@@ -98,7 +98,11 @@ _GLOBAL(cacheable_memzero)
> bdnz 4b
> 3: mtctr r9
> li r7,4
>+#ifdef CONFIG_L1_WRITETHROUGH
>+10:
>+#else
> 10: dcbz r7,r6
>+#endif /* CONFIG_L1_WRITETHROUGH */
> addi r6,r6,CACHELINE_BYTES
> bdnz 10b
> clrlwi r5,r8,32-LG_CACHELINE_BYTES
>@@ -187,7 +191,9 @@ _GLOBAL(cacheable_memcpy)
> mtctr r0
> beq 63f
> 53:
>+#ifndef CONFIG_L1_WRITETHROUGH
> dcbz r11,r6
>+#endif /* CONFIG_L1_WRITETHROUGH */
> COPY_16_BYTES
> #if L1_CACHE_BYTES >= 32
> COPY_16_BYTES
>@@ -368,7 +374,11 @@ _GLOBAL(__copy_tofrom_user)
> mtctr r8
>
> 53: dcbt r3,r4
>+#ifdef CONFIG_L1_WRITETHROUGH
>+54:
>+#else
> 54: dcbz r11,r6
>+#endif
> .section __ex_table,"a"
> .align 2
> .long 54b,105f
>diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
>index 024acab..b684c8a 100644
>--- a/arch/powerpc/mm/44x_mmu.c
>+++ b/arch/powerpc/mm/44x_mmu.c
>@@ -80,9 +80,12 @@ static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
> :
> #ifdef CONFIG_PPC47x
> : "r" (PPC47x_TLB2_S_RWX),
>-#else
>+#elseif CONFIG_L1_WRITETHROUGH
>+ : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_WL1 \
>+ | PPC44x_TLB_U2 | PPC44x_TLB_M),
>+#else /* neither CONFIG_PPC47x or CONFIG_L1_WRITETHROUGH */
> : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
>-#endif
>+#endif /* CONFIG_PPC47x */
> "r" (phys),
> "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
> "r" (entry),
>diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
>index f7b0772..684a281 100644
>--- a/arch/powerpc/platforms/Kconfig
>+++ b/arch/powerpc/platforms/Kconfig
>@@ -348,4 +348,9 @@ config XILINX_PCI
> bool "Xilinx PCI host bridge support"
> depends on PCI && XILINX_VIRTEX
>
>+config L1_WRITETHROUGH
>+ bool "Blue Gene/P enabled writethrough mode"
>+ depends on BGP
>+ default y
You add this config option here, named generically, but then make it
depend on BGP. It sees it should be named BGP_L1_WRITETHROUGH, and then
just selected by the BGP platform. But then....
> endmenu
>diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
>index 111138c..3a3c711 100644
>--- a/arch/powerpc/platforms/Kconfig.cputype
>+++ b/arch/powerpc/platforms/Kconfig.cputype
>@@ -329,9 +329,13 @@ config NOT_COHERENT_CACHE
> bool
> depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON
> default n if PPC_47x
>+ default n if BGP
> default y
>
> config CHECK_CACHE_COHERENCY
> bool
>
>+config L1_WRITETHROUGH
>+ bool
You add an identical option down here. Confused.
josh
^ permalink raw reply
* Re: [PATCH 1/7] [RFC] Mainline BG/P platform support
From: Josh Boyer @ 2011-05-19 11:01 UTC (permalink / raw)
To: Eric Van Hensbergen; +Cc: linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <1305753895-24845-1-git-send-email-ericvh@gmail.com>
On Wed, May 18, 2011 at 04:24:49PM -0500, Eric Van Hensbergen wrote:
>The Linux kernel patches for the IBM BlueGene/P have been open-sourced
>for quite some time, but haven't been integrated into the mainline Linux
>kernel source tree. This is the first patch series of several where I
>will attempt to cleanup and mainline the already public patches. I
>welcome feedback as well as any help I can get. I'm drawing on
>the patches available for the IBM Compute Node kernel, the ZeptoOS project
>and the Kittyhawk project.
>(all available from http://wiki.bg.anl-external.org)
>
>I'll be prioritizing core patches which are harder to keep current with
>mainline due to merge conflicts and then slowly incorporating the drivers
>and other extensions (if acceptable after community review).
>
>I'll be maintaining the patchset in my kernel.org repository
>(/pub/scm/linux/kernel/git/ericvh/bluegene.git) under the bluegene
>branch with the source repos (zepto, kittyhawk, ibmcn) available in
>respective branches. Ben - if you would prefer me to send pull requests
>once we get rolling, I can switch to that -- otherwise I'll stick to
>just submitting patches to the list assuming you'll pull them when they
>become acceptable. Thanks for your attention reviewing these patches.
This is going to get slightly messy if there are lots of changes in
platforms/44x and/or head_44x.S. Most 4xx changes go through my tree,
and I'm happy to pull from your tree once things get off the ground. We
just need to make sure and coordinate as we go.
My tree is fairly low-churn (as is all of 4xx) so hopefully I'm worried
for nothing.
>Signed-off-by: Eric Van Hensbergen <ericvh@gmail.com>
>---
> MAINTAINERS | 8 ++++++++
> 1 files changed, 8 insertions(+), 0 deletions(-)
>
>diff --git a/MAINTAINERS b/MAINTAINERS
>index 69f19f1..3ffca88 100644
>--- a/MAINTAINERS
>+++ b/MAINTAINERS
>@@ -3863,6 +3863,14 @@ S: Maintained
> F: arch/powerpc/platforms/40x/
> F: arch/powerpc/platforms/44x/
>
>+LINUX FOR POWERPC BLUEGENE/P
>+M: Eric Van Hensbergen <ericvh@gmail.com>
>+W: http://bg-linux.anl-external.org/wiki/index.php/Main_Page
>+L: bg-linux@lists.anl-external.org
>+T: git git://git.kernel.org/pub/scm/linux/kernel/git/ericvh/bluegene.git
>+S: Maintained
>+F: arch/powerpc/platforms/44x/bgp*
This should probably be the last patch in the series. You have a file
pattern listed for files that don't exist at all in any of the other
patches you submitted :).
josh
^ permalink raw reply
* [PATCH] Powerpc/fsl_lbc: Add workaround for ELBC-A001 erratum
From: Shengzhou Liu @ 2011-05-19 10:48 UTC (permalink / raw)
To: linuxppc-dev; +Cc: scottwood, kumar.gala, Shengzhou Liu
Simultaneous FCM and GPCM or UPM operation may erroneously trigger
bus monitor timeout.
Set the local bus monitor timeout value to the maximum by setting
LBCR[BMT] = 0 and LBCR[BMTPS] = 0xF.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Gala Kumar <kumar.gala@freescale.com>
---
arch/powerpc/include/asm/fsl_lbc.h | 2 ++
arch/powerpc/sysdev/fsl_lbc.c | 9 +++++++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 5c1bf34..8a0b5ec 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -157,6 +157,8 @@ struct fsl_lbc_regs {
#define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8
+#define LBCR_BMTPS 0x0000000F
+#define LBCR_BMTPS_SHIFT 0
#define LBCR_INIT 0x00040000
__be32 lcrr; /**< Clock Ratio Register */
#define LCRR_DBYP 0x80000000
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 4fcb5a4..19a4ecd 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -184,7 +184,8 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
}
EXPORT_SYMBOL(fsl_upm_run_pattern);
-static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
+static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
+ struct device_node *node)
{
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
@@ -198,6 +199,10 @@ static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
/* Enable interrupts for any detected events */
out_be32(&lbc->lteir, LTEIR_ENABLE);
+ /* Set the monitor timeout value to the maximum for erratum A001 */
+ if (of_device_is_compatible(node, "fsl,elbc"))
+ clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
+
return 0;
}
@@ -304,7 +309,7 @@ static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
fsl_lbc_ctrl_dev->dev = &dev->dev;
- ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
+ ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, ofdev->node);
if (ret < 0)
goto err;
--
1.6.4
^ permalink raw reply related
* Re: [PATCH] [klibc] ppc64: Fix build failure with stricter as
From: maximilian attems @ 2011-05-19 11:20 UTC (permalink / raw)
To: Matthias Klose; +Cc: klibc, linuxppc-dev, Paul Mackerras
In-Reply-To: <1305726080-27589-1-git-send-email-max@stro.at>
On Wed, 18 May 2011, maximilian attems wrote:
> From: Matthias Klose <doko@ubuntu.com>
>
> Landed in Ubuntu klibc version 1.5.20-1ubuntu3.
>
>
> Signed-off-by: maximilian attems <max@stro.at>
> ---
> usr/klibc/arch/ppc64/crt0.S | 17 +++++++++--------
> 1 files changed, 9 insertions(+), 8 deletions(-)
>
thank you, merged in klibc git, will be in next 1.5.23.
--
maks
^ permalink raw reply
* RE: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for PM
From: Kushwaha Prabhakar-B32579 @ 2011-05-19 11:22 UTC (permalink / raw)
To: Kumar Gala
Cc: meet2prabhu@gmail.com, linuxppc-dev@lists.ozlabs.org,
Jiang Yutang-B14898
In-Reply-To: <3A8FAEED-7BD9-4776-85A9-560D07417BA8@kernel.crashing.org>
Hi Kumar,
Please find my answer in-lined
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Thursday, May 19, 2011 12:00 PM
> To: Kushwaha Prabhakar-B32579
> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Jiang Yutang-
> B14898
> Subject: Re: [PATCH] powerpc/85xx: Save and restore pcie ATMU windows for
> PM
>=20
>=20
> On Apr 28, 2011, at 1:38 AM, Prabhakar Kushwaha wrote:
>=20
> > D3-cold state indicates removal of the clock and power. however
> > auxiliary (AUX) Power may remain available even after the main power
> rails are powered down.
> >
> > wakeup from D3-cold state requires full context restore. Other things
> > are taken care in pci-driver except ATMUs.
> > ATMU windows needs to be saved and restored during suspend and resume.
> >
> > Signed-off-by: Jiang Yutang <b14898@freescale.com>
> > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> > ---
> > Based upon
> > git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(b
> > ranch master)
> >
> > arch/powerpc/sysdev/fsl_pci.c | 116
> +++++++++++++++++++++++++++++++++++++++++
> > arch/powerpc/sysdev/fsl_pci.h | 7 ++-
> > 2 files changed, 121 insertions(+), 2 deletions(-)
>=20
> Is this patch for when we are a host or agent?
This patch is independent of host or agent. It is for supporting D3 cold st=
ate for P1022.
These functions are called during System level suspend and resume.=20
--Prabhakar
^ permalink raw reply
* RE: [PATCH] powerpc/85xx: add host-pci(e) bridge only for RC
From: Kushwaha Prabhakar-B32579 @ 2011-05-19 11:25 UTC (permalink / raw)
To: Kumar Gala
Cc: meet2prabhu@gmail.com, linuxppc-dev@lists.ozlabs.org,
Vivek Mahajan
In-Reply-To: <7E57A9FF-9BB3-4C5A-9965-E56A4E35B1B8@kernel.crashing.org>
Hello Kumar,
Please find my answer in-lined
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Thursday, May 19, 2011 11:55 AM
> To: Kushwaha Prabhakar-B32579
> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Vivek Mahajan
> Subject: Re: [PATCH] powerpc/85xx: add host-pci(e) bridge only for RC
>=20
>=20
> On Apr 27, 2011, at 12:35 AM, Prabhakar Kushwaha wrote:
>=20
> > FSL PCIe controller can act as agent(EP) or host(RC).
> > Under Agent(EP) mode they are configured via Host. So it is not
> > required to add with the PCI(e) sub-system.
> >
> > Add and configure PCIe controller only for RC mode.
> >
> > Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
> > Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> > ---
> > Based upon
> > git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(b
> > ranch master)
> >
> > arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++
> > 1 files changed, 14 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/powerpc/sysdev/fsl_pci.c
> > b/arch/powerpc/sysdev/fsl_pci.c index 68ca929..87ac11b 100644
> > --- a/arch/powerpc/sysdev/fsl_pci.c
> > +++ b/arch/powerpc/sysdev/fsl_pci.c
> > @@ -323,6 +323,7 @@ int __init fsl_add_bridge(struct device_node *dev,
> int is_primary)
> > struct pci_controller *hose;
> > struct resource rsrc;
> > const int *bus_range;
> > + u8 is_agent;
> >
> > if (!of_device_is_available(dev)) {
> > pr_warning("%s: disabled\n", dev->full_name); @@ -353,6
> +354,19 @@
> > int __init fsl_add_bridge(struct device_node *dev, int is_primary)
> >
> > setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> > PPC_INDIRECT_TYPE_BIG_ENDIAN);
> > +
> > + early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &is_agent);
>=20
> Why are we looking at PCI_HEADER_TYPE? We should look at PCI_CLASS_PROG.
I think both are OK. We can check for any one.=20
Is there any problem with PCI_HEADER_TYPE?
> > + if ((is_agent & 0x7f) =3D=3D PCI_HEADER_TYPE_NORMAL) {
> > + u32 temp;
> > +
> > + temp =3D (u32)hose->cfg_data & ~PAGE_MASK;
> > + if (((u32)hose->cfg_data & PAGE_MASK) !=3D (u32)hose->cfg_addr)
> > + iounmap(hose->cfg_data - temp);
> > + iounmap(hose->cfg_addr);
> > + pcibios_free_controller(hose);
> > + return 0;
> > + }
> > +
> > setup_pci_cmd(hose);
> >
> > /* check PCI express link status */
> > --
> > 1.7.3
> >
> >
> > _______________________________________________
> > Linuxppc-dev mailing list
> > Linuxppc-dev@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/linuxppc-dev
>=20
^ permalink raw reply
* Re: [PATCH 3/5] v2 seccomp_filters: Enable ftrace-based system call filtering
From: Steven Rostedt @ 2011-05-19 12:22 UTC (permalink / raw)
To: Will Drewry
Cc: linux-mips, linux-sh, Peter Zijlstra, Frederic Weisbecker,
Heiko Carstens, Oleg Nesterov, David Howells, Paul Mackerras,
Ralf Baechle, H. Peter Anvin, sparclinux, Jiri Slaby, linux-s390,
Russell King, x86, James Morris, Linus Torvalds, Ingo Molnar,
linux-arm-kernel, Ingo Molnar, Serge E. Hallyn,
Martin Schwidefsky, Thomas Gleixner, kees.cook, Roland McGrath,
Michal Marek, Michal Simek, linuxppc-dev, linux-kernel,
Eric Paris, Paul Mundt, Tejun Heo, linux390, Andrew Morton, agl,
David S. Miller
In-Reply-To: <BANLkTikBK3-KZ10eErQ6Eex_L6Qe2aZang@mail.gmail.com>
On Wed, 2011-05-18 at 21:07 -0700, Will Drewry wrote:
> Do event_* that return non-void exist in the tree at all now? I've
> looked at the various tracepoint macros as well as some of the other
> handlers (trace_function, perf_tp_event, etc) and I'm not seeing any
> places where a return value is honored nor could be. At best, the
> perf_tp_event can be short-circuited it in the hlist_for_each, but
> it'd still need a way to bubble up a failure and result in not calling
> the trace/event that the hook precedes.
No, none of the current trace hooks have return values. That was what I
was talking about how to implement in my previous emails.
-- Steve
^ permalink raw reply
* Re: [PATCH 1/7] [RFC] Mainline BG/P platform support
From: Eric Van Hensbergen @ 2011-05-19 12:35 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <20110519110105.GB25179@zod.rchland.ibm.com>
On Thu, May 19, 2011 at 6:01 AM, Josh Boyer <jwboyer@linux.vnet.ibm.com> wr=
ote:
> On Wed, May 18, 2011 at 04:24:49PM -0500, Eric Van Hensbergen wrote:
>>
>>I'll be maintaining the patchset in my kernel.org repository
>>(/pub/scm/linux/kernel/git/ericvh/bluegene.git) under the bluegene
>>branch with the source repos (zepto, kittyhawk, ibmcn) available in
>>respective branches. =A0Ben - if you would prefer me to send pull request=
s
>>once we get rolling, I can switch to that -- otherwise I'll stick to
>>just submitting patches to the list assuming you'll pull them when they
>>become acceptable. =A0Thanks for your attention reviewing these patches.
>
> This is going to get slightly messy if there are lots of changes in
> platforms/44x and/or head_44x.S. =A0Most 4xx changes go through my tree,
> and I'm happy to pull from your tree once things get off the ground. =A0W=
e
> just need to make sure and coordinate as we go.
>
I'm fine with processing the changes through your tree. Most of the items
with conflicts are in this series, so hopefully it won't be too messy (outs=
ide
of some Makefile and Kconfig changes which are much easier to merge)
after this. So, should I base changes on:
http://git.kernel.org/?p=3Dlinux/kernel/git/jwboyer/powerpc-4xx.git;a=3Dsho=
rtlog;h=3Drefs/heads/next
or:
http://git.kernel.org/?p=3Dlinux/kernel/git/benh/powerpc.git;a=3Dshortlog;h=
=3Drefs/heads/next
There are some important questions on code organization which it would
probably be a good idea to discuss at some point -- in particular what I
should do about the device drivers. Pretty much every driver except for
the ethernet is particular to this platform. IIRC some of the embedded
platforms have the SOC drivers in the platforms directory -- but it doesn't
seem like you've done this with 4xx so I was gonna just place them in
the appropriate drivers/* directory. The other question is that there are
a number of patches which involve communication which a somewhat
substantial firmware layer. You can get an idea of the existing patch's
code organization by looking at:
http://git.kernel.org/?p=3Dlinux/kernel/git/ericvh/bluegene.git;a=3Dcommit;=
h=3Dbee9f329eeef6c8eb95c35de4c5d22a0c05a1b3e
Its important to point out that I am going through and cleaning up as I
go, so not everything from that patch will make the cut as is (or perhaps
even at all) -- but that should help identify where potential conflicts are
as well as potentially out of place code.
>>
>>+LINUX FOR POWERPC BLUEGENE/P
>>+M: =A0 =A0Eric Van Hensbergen <ericvh@gmail.com>
>>+W: =A0 =A0http://bg-linux.anl-external.org/wiki/index.php/Main_Page
>>+L: =A0 =A0bg-linux@lists.anl-external.org
>>+T: =A0 =A0git git://git.kernel.org/pub/scm/linux/kernel/git/ericvh/blueg=
ene.git
>>+S: =A0 =A0Maintained
>>+F: =A0 =A0arch/powerpc/platforms/44x/bgp*
>
> This should probably be the last patch in the series. =A0You have a file
> pattern listed for files that don't exist at all in any of the other
> patches you submitted :).
>
Yeah, I wondered about that, its just I hate patch series intro messages wi=
th
no patch, and I figured this was a good way out of it. It also adds
the relevant
info as far as mailing lists and wiki pages where folks can go for more inf=
o --
but if folks have a problem with it I'll kill it until we get
everything else in.
-eric
^ permalink raw reply
* Re: Kernel cannot see PCI device
From: Prashant Bhole @ 2011-05-19 12:41 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: linux-pci, linuxppc-dev
In-Reply-To: <BANLkTim22Lm=TG9vP+XH25k04ncX=kqy8g@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1919 bytes --]
Hi,
On Wed, May 18, 2011 at 7:44 PM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> On Wed, May 18, 2011 at 4:02 AM, Prashant Bhole
> <prashantsmailcenter@gmail.com> wrote:
>> On Mon, May 2, 2011 at 10:21 AM, Prashant Bhole
>> <prashantsmailcenter@gmail.com> wrote:
>>>
>>> Hi,
>>> I have a custom made powerpc 460EX board. On that board u-boot
>>> can see a PCI device but Linux kernel cannot see it. What could be the problem?
>>>
>>> On u-boot "pci 2" commands displays following device:
>>> Scanning PCI devices on bus 2
>>> BusDevFun VendorId DeviceId Device Class Sub-Class
>>> _____________________________________________________________
>>> 02.00.00 0x1000 0x0072 Mass storage controller 0x00
>>>
>>> And when the kernel is booted, there is only one pci device (bridge):
>>> #ls /sys/bus/pci/devices
>>> 0000:80:00.0
>>>
>>
>> I am still facing in this problem.
>>
>> a call to pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l) returns
>> positive value in the function pci_scan_device(), which means VENDOR_ID reading
>> failed. I could not find the reason. Any hints?
>
> Hmm... probably powerpc-related, so I added linuxppc-dev.
>
> My guess would be that Linux didn't find the host bridge to the
> hierarchy containing bus 2. I would guess the host bridge info is
> supposed to come from OF. More information, like the complete u-boot
> PCI scan and the kernel dmesg log, would be useful. And maybe u-boot
> has a way to dump the OF device tree?
>
I am not using OF for booting u-boot. OF is being used for booting the kernel.
Not sure whether the host bridge info is coming from OF.
Device tree has two pciex nodes with following property:
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"
I think that node represents a pciex bus not the bridge.
I have attached u-boot, dmesg logs and device tree source
-Prashant
[-- Attachment #2: dmesg.txt --]
[-- Type: text/plain, Size: 11488 bytes --]
460ex #dmesg
<6>Using PowerPC 44x Platform machine description
<4>Only using first contiguous memory region
<5>Linux version 2.6.38.4 (root@stripe) (gcc version 4.3.4 (Buildroot 2010.02) ) #12 Thu May 19 16:51:17 IST 2011
<4>Found initrd at 0xefdff000:0xeffffc24
<7>Found legacy serial port 0 for /plb/opb/serial@ef600300
<7> mem=4ef600300, taddr=4ef600300, irq=0, clk=7407407, speed=0
<7>Found legacy serial port 1 for /plb/opb/serial@ef600400
<7> mem=4ef600400, taddr=4ef600400, irq=0, clk=7407407, speed=0
<7>Found legacy serial port 2 for /plb/opb/serial@ef600500
<7> mem=4ef600500, taddr=4ef600500, irq=0, clk=7407407, speed=0
<7>Found legacy serial port 3 for /plb/opb/serial@ef600600
<7> mem=4ef600600, taddr=4ef600600, irq=0, clk=7407407, speed=0
<7>Top of RAM: 0x30000000, Total RAM: 0x30000000
<7>Memory hole size: 0MB
<4>Zone PFN ranges:
<4> DMA 0x00000000 -> 0x00030000
<4> Normal empty
<4>Movable zone start PFN for each node
<4>early_node_map[1] active PFN ranges
<4> 0: 0x00000000 -> 0x00030000
<7>On node 0 totalpages: 196608
<7>free_area_init_node: node 0, pgdat c033b628, node_mem_map c045e000
<7> DMA zone: 1536 pages used for memmap
<7> DMA zone: 0 pages reserved
<7> DMA zone: 195072 pages, LIFO batch:31
<6>MMU: Allocated 1088 bytes of context maps for 255 contexts
<7>pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
<7>pcpu-alloc: [0] 0
<4>Built 1 zonelists in Zone order, mobility grouping on. Total pages: 195072
<5>Kernel command line: root=/dev/ram rw console=ttyS0,115200
<6>PID hash table entries: 4096 (order: 2, 16384 bytes)
<6>Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
<6>Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
<6>Memory: 772860k/786432k available (3240k kernel code, 13572k reserved, 100k data, 1127k bss, 160k init)
<6>Kernel virtual memory layout:
<6> * 0xfffdf000..0xfffff000 : fixmap
<6> * 0xfde00000..0xfe000000 : consistent mem
<6> * 0xfde00000..0xfde00000 : early ioremap
<6> * 0xf1000000..0xfde00000 : vmalloc & ioremap
<6>SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
<6>NR_IRQS:512 nr_irqs:512 16
<4>UIC0 (32 IRQ sources) at DCR 0xc0
<4>UIC1 (32 IRQ sources) at DCR 0xd0
<7>irq: irq 30 on host /interrupt-controller0 mapped to virtual irq 30
<4>UIC2 (32 IRQ sources) at DCR 0xe0
<7>irq: irq 10 on host /interrupt-controller0 mapped to virtual irq 16
<4>UIC3 (32 IRQ sources) at DCR 0xf0
<7>irq: irq 16 on host /interrupt-controller0 mapped to virtual irq 17
<7>time_init: decrementer frequency = 1000.000012 MHz
<7>time_init: processor frequency = 1000.000012 MHz
<6>clocksource: timebase mult[400000] shift[22] registered
<7>clockevent: decrementer mult[80000019] shift[31] cpu[0]
<6>pid_max: default: 32768 minimum: 301
<4>Mount-cache hash table entries: 512
<6>NET: Registered protocol family 16
<7>irq: irq 11 on host /interrupt-controller1 mapped to virtual irq 18
<6>256k L2-cache enabled
<6>PCIE0: Port disabled via device-tree
<6>PCIE1: Checking link...
<6>PCIE1: Device detected, waiting for link...
<6>PCIE1: link is up !
<6>PCI host bridge /plb/pciex@d20000000 (primary) ranges:
<6> MEM 0x0000000e80000000..0x0000000effffffff -> 0x0000000080000000
<6> MEM 0x0000000f00100000..0x0000000f001fffff -> 0x0000000000000000
<6> IO 0x0000000f80010000..0x0000000f8001ffff -> 0x0000000000000000
<6> Removing ISA hole at 0x0000000f00100000
<6>4xx PCI DMA offset set to 0x00000000
<6>/plb/pciex@d20000000: Legacy ISA memory support enabled
<6>PCIE1: successfully set as root-complex
<6>PCI host bridge /plb/pci@c0ec00000 (primary) ranges:
<6> MEM 0x0000000d80000000..0x0000000dffffffff -> 0x0000000080000000
<6> MEM 0x0000000c0ee00000..0x0000000c0eefffff -> 0x0000000000000000
<6> IO 0x0000000c08000000..0x0000000c0800ffff -> 0x0000000000000000
<6> Removing ISA hole at 0x0000000c0ee00000
<6>4xx PCI DMA offset set to 0x00000000
<6>/plb/pci@c0ec00000: Legacy ISA memory support enabled
<6>PCI: Probing PCI hardware
<7>pci_bus 0000:80: scanning bus
<7>pci 0000:80:00.0: [aaa1:bed1] type 1 class 0x000604
<7>pci 0000:80:00.0: calling quirk_mmio_always_on+0x0/0x24
<7>pci 0000:80:00.0: reg 10: [mem 0x00000000-0x7fffffff pref]
<7>pci 0000:80:00.0: calling pcibios_fixup_resources+0x0/0x174
<7>pci 0000:80:00.0: calling fixup_ppc4xx_pci_bridge+0x0/0x134
<6>PCI: Hiding 4xx host bridge resources 0000:80:00.0
<7>pci 0000:80:00.0: calling quirk_resource_alignment+0x0/0x1e0
<7>pci_bus 0000:80: fixups for bus
<7>pci 0000:80:00.0: scanning [bus 81-bf] behind bridge, pass 0
<7>pci_bus 0000:81: scanning bus
<7>pci_bus 0000:81: fixups for bus
<6>pci 0000:80:00.0: PCI bridge to [bus 81-bf]
<7>pci 0000:80:00.0: bridge window [io 0x0000-0x0000] (disabled)
<7>pci 0000:80:00.0: bridge window [mem 0xb8000000-0xb80fffff]
<7>pci 0000:80:00.0: bridge window [mem 0x10000000-0x000fffff pref] (disabled)
<7>pci_bus 0000:81: bus scan returning with max=81
<7>pci 0000:80:00.0: scanning [bus 81-bf] behind bridge, pass 1
<7>pci_bus 0000:80: bus scan returning with max=bf
<7>pci_bus 0001:00: scanning bus
<7>pci_bus 0001:00: fixups for bus
<7>pci_bus 0001:00: bus scan returning with max=00
<6>pci 0000:80:00.0: PCI bridge to [bus 81-bf]
<6>pci 0000:80:00.0: bridge window [io disabled]
<6>pci 0000:80:00.0: bridge window [mem disabled]
<6>pci 0000:80:00.0: bridge window [mem pref disabled]
<7>pci_bus 0000:80: resource 0 [io 0xfffe0000-0xfffeffff]
<7>pci_bus 0000:80: resource 1 [mem 0xe80000000-0xeffffffff]
<7>pci_bus 0001:00: resource 0 [io 0x0000-0xffff]
<7>pci_bus 0001:00: resource 1 [mem 0xd80000000-0xdffffffff]
<4>bio: create slab <bio-0> at 0
<6>vgaarb: loaded
<5>SCSI subsystem initialized
<6>Switching to clocksource timebase
<6>NET: Registered protocol family 2
<6>IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
<6>TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
<6>Switched to NOHz mode on CPU #0
<6>TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
<6>TCP: Hash tables configured (established 131072 bind 65536)
<6>TCP reno registered
<6>UDP hash table entries: 512 (order: 1, 8192 bytes)
<6>UDP-Lite hash table entries: 512 (order: 1, 8192 bytes)
<6>NET: Registered protocol family 1
<6>RPC: Registered udp transport module.
<6>RPC: Registered tcp transport module.
<6>RPC: Registered tcp NFSv4.1 backchannel transport module.
<7>pci 0000:80:00.0: calling quirk_cardbus_legacy+0x0/0x50
<7>pci 0000:80:00.0: calling quirk_usb_early_handoff+0x0/0x714
<7>PCI: CLS 32 bytes, default 32
<6>Trying to unpack rootfs image as initramfs...
<6>rootfs image is not initramfs (no cpio magic); looks like an initrd
<4>Freeing initrd memory: 2051k freed
<7>irq: irq 1 on host /interrupt-controller1 mapped to virtual irq 19
<7>irq: irq 1 on host /interrupt-controller0 mapped to virtual irq 20
<7>irq: irq 29 on host /interrupt-controller1 mapped to virtual irq 29
<7>irq: irq 30 on host /interrupt-controller1 mapped to virtual irq 21
<7>irq: irq 29 on host /interrupt-controller0 mapped to virtual irq 22
<7>irq: irq 6 on host /interrupt-controller2 mapped to virtual irq 23
<7>irq: irq 7 on host /interrupt-controller2 mapped to virtual irq 24
<7>irq: irq 3 on host /interrupt-controller2 mapped to virtual irq 25
<7>irq: irq 4 on host /interrupt-controller2 mapped to virtual irq 26
<7>irq: irq 5 on host /interrupt-controller2 mapped to virtual irq 27
<7>irq: irq 22 on host /interrupt-controller0 mapped to virtual irq 28
<7>irq: irq 21 on host /interrupt-controller0 mapped to virtual irq 31
<7>irq: irq 22 on host /interrupt-controller1 mapped to virtual irq 32
<7>irq: irq 6 on host /interrupt-controller1 mapped to virtual irq 33
<7>irq: irq 0 on host /interrupt-controller1 mapped to virtual irq 34
<7>irq: irq 18 on host /interrupt-controller0 mapped to virtual irq 35
<7>irq: irq 9 on host /interrupt-controller0 mapped to virtual irq 36
<7>irq: irq 20 on host /interrupt-controller3 mapped to virtual irq 37
<7>irq: irq 21 on host /interrupt-controller3 mapped to virtual irq 38
<7>irq: irq 21 on host /interrupt-controller1 mapped to virtual irq 39
<7>irq: irq 20 on host /interrupt-controller1 mapped to virtual irq 40
<7>irq: irq 2 on host /interrupt-controller2 mapped to virtual irq 41
<7>irq: irq 2 on host /interrupt-controller0 mapped to virtual irq 42
<7>irq: irq 3 on host /interrupt-controller0 mapped to virtual irq 43
<7>irq: irq 16 on host /interrupt-controller2 mapped to virtual irq 44
<7>irq: irq 20 on host /interrupt-controller2 mapped to virtual irq 45
<7>irq: irq 17 on host /interrupt-controller2 mapped to virtual irq 46
<7>irq: irq 21 on host /interrupt-controller2 mapped to virtual irq 47
<7>irq: irq 0 on host /interrupt-controller0 mapped to virtual irq 48
<3>setting trigger mode 3 for irq 42 failed (compat_irq_set_type+0x0/0x30)
<3>setting trigger mode 3 for irq 42 failed (compat_irq_set_type+0x0/0x30)
<6>ROMFS MTD (C) 2007 Red Hat, Inc.
<6>msgmni has been set to 1515
<6>Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
<6>io scheduler noop registered
<6>io scheduler deadline registered
<6>io scheduler cfq registered (default)
<6>pci_hotplug: PCI Hot Plug PCI Core version: 0.5
<6>Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
<6>serial8250.0: ttyS0 at MMIO 0x4ef600300 (irq = 19) is a U6_16550A
<6>console [ttyS0] enabled
<6>serial8250.0: ttyS1 at MMIO 0x4ef600400 (irq = 20) is a U6_16550A
<6>serial8250.0: ttyS2 at MMIO 0x4ef600500 (irq = 29) is a U6_16550A
<6>serial8250.0: ttyS3 at MMIO 0x4ef600600 (irq = 21) is a U6_16550A
<6>4ef600300.serial: ttyS0 at MMIO 0x4ef600300 (irq = 19) is a 16550
<6>4ef600400.serial: ttyS1 at MMIO 0x4ef600400 (irq = 20) is a 16550
<6>4ef600500.serial: ttyS2 at MMIO 0x4ef600500 (irq = 29) is a 16550
<6>4ef600600.serial: ttyS3 at MMIO 0x4ef600600 (irq = 21) is a 16550
<6>brd: module loaded
<6>mpt2sas version 07.100.00.00 loaded
<6>PPC 4xx OCP EMAC driver, version 3.54
<6>MAL v2 /plb/mcmal, 2 TX channels, 16 RX channels
<6>ZMII /plb/opb/emac-zmii@ef600d00 initialized
<6>RGMII /plb/opb/emac-rgmii@ef601500 initialized with MDIO support
<6>TAH /plb/opb/emac-tah@ef601350 initialized
<6>TAH /plb/opb/emac-tah@ef601450 initialized
<5>/plb/opb/emac-rgmii@ef601500: input 0 in RGMII mode
<6>eth0: EMAC-0 /plb/opb/ethernet@ef600e00, MAC 12:34:56:78:cc:dd
<4>eth0: found Generic MII PHY (0x00)
<5>/plb/opb/emac-rgmii@ef601500: input 1 in RGMII mode
<6>eth1: EMAC-1 /plb/opb/ethernet@ef600f00, MAC 12:34:56:78:dc:dd
<4>eth1: found Generic MII PHY (0x01)
<6>i2c /dev entries driver
<6>of:ibm-iic 4ef600700.i2c: using standard (100 kHz) mode
<7>irq: irq 25 on host /interrupt-controller2 mapped to virtual irq 49
<6>rtc-m41t80 0-0068: chip found, driver version 0.05
<6>rtc-m41t80 0-0068: rtc core: registered m41t80 as rtc0
<6>of:ibm-iic 4ef600800.i2c: using standard (100 kHz) mode
<6>ad7414 0-0048: chip found
<4>ad7414 0-0048: ad7414_probe unable to read config register.
<6>TCP cubic registered
<6>NET: Registered protocol family 17
<6>rtc-m41t80 0-0068: setting system clock to 2071-09-15 11:14:52 UTC (3209541292)
<5>RAMDISK: gzip image found at block 0
<4>VFS: Mounted root (romfs filesystem) readonly on device 1:0.
<4>Freeing unused kernel memory: 160k init
<6>eth0: link is down
<6>eth1: link is down
<6>eth0: link is up, 100 FDX, pause enabled
460ex #
[-- Attachment #3: uboot_log.txt --]
[-- Type: text/plain, Size: 833 bytes --]
U-Boot 2009.08 (Apr 08 2011 - 18:08:03)
CPU: AMCC PowerPC 460EX Rev. B at 1000 MHz (PLB=200, OPB=100, EBC=100 MHz)
Security/Kasumi support
Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
Internal PCI arbiter disabled
32 kB I-Cache 32 kB D-Cache
Board: Canyonlands - AMCC PPC460EX Evaluation Board, 1*PCIe/1*SATA, Rev. 0
I2C: ready
DRAM: 1 GB (ECC not enabled, 400 MHz, CL3)
I2C channel 1 test:
SDRAM channel: OK
AT24C02 channel: OK
RTC channel: OK
W83793 channel: OK
FLASH: 8 MB
NAND: 256 MiB
PCI: Bus Dev VenId DevId Class Int
PCIE1: successfully set as root-complex
02 00 1000 0072 0100 00
DTT: 1 FAILED INIT
Net: ppc_4xx_eth0, ppc_4xx_eth1
Type run flash_nfs to mount root filesystem over NFS
Hit any key to stop autoboot: 5
[-- Attachment #4: canyonlands.dts --]
[-- Type: application/octet-stream, Size: 17676 bytes --]
/*
* Device Tree Source for AMCC Canyonlands (460EX)
*
* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <1>;
model = "amcc,canyonlands";
compatible = "amcc,canyonlands";
dcr-parent = <&{/cpus/cpu@0}>;
aliases {
ethernet0 = &EMAC0;
ethernet1 = &EMAC1;
serial0 = &UART0;
serial1 = &UART1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
model = "PowerPC,460EX";
reg = <0x00000000>;
clock-frequency = <0>; /* Filled in by U-Boot */
timebase-frequency = <0>; /* Filled in by U-Boot */
i-cache-line-size = <32>;
d-cache-line-size = <32>;
i-cache-size = <32768>;
d-cache-size = <32768>;
dcr-controller;
dcr-access-method = "native";
next-level-cache = <&L2C0>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
};
nvram@4e4000000 {
compatible = "nvram";
device_type = "memory";
reg = <4 0xE4000000 0x20000>;
};
UIC0: interrupt-controller0 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <0>;
dcr-reg = <0x0c0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
};
UIC1: interrupt-controller1 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <1>;
dcr-reg = <0x0d0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
UIC2: interrupt-controller2 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <2>;
dcr-reg = <0x0e0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
UIC3: interrupt-controller3 {
compatible = "ibm,uic-460ex","ibm,uic";
interrupt-controller;
cell-index = <3>;
dcr-reg = <0x0f0 0x009>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <2>;
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
interrupt-parent = <&UIC0>;
};
OCM1: ocm@400040000 {
compatible = "ibm,ocm";
status = "enabled";
cell-index = <1>;
/* configured in U-Boot */
reg = <4 0x00040000 0x10000>; /* 64K */
};
SDR0: sdr {
compatible = "ibm,sdr-460ex";
dcr-reg = <0x00e 0x002>;
};
CPR0: cpr {
compatible = "ibm,cpr-460ex";
dcr-reg = <0x00c 0x002>;
};
L2C0: l2c {
compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
0x030 0x008>; /* L2 cache DCR's */
cache-line-size = <32>; /* 32 bytes */
cache-size = <262144>; /* L2, 256K */
interrupt-parent = <&UIC1>;
interrupts = <11 1>;
};
plb {
compatible = "ibm,plb-460ex", "ibm,plb4";
#address-cells = <2>;
#size-cells = <1>;
ranges;
clock-frequency = <0>; /* Filled in by U-Boot */
SDRAM0: sdram {
compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
dcr-reg = <0x010 0x002>;
};
CRYPTO: crypto@180000 {
compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
reg = <4 0x00180000 0x80400>;
interrupt-parent = <&UIC0>;
interrupts = <0x1d 0x4>;
};
MAL0: mcmal {
compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
dcr-reg = <0x180 0x062>;
num-tx-chans = <2>;
num-rx-chans = <16>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-parent = <&UIC2>;
interrupts = < /*TXEOB*/ 0x6 0x4
/*RXEOB*/ 0x7 0x4
/*SERR*/ 0x3 0x4
/*TXDE*/ 0x4 0x4
/*RXDE*/ 0x5 0x4>;
};
ADMA: adma {
compatible = "amcc,adma";
device_type = "dma";
reg = <4 00100200 80>;
interrupt-parent = <&ADMA>;
interrupts =<0 1 2>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*FIFO need service */ 0 &UIC0 0x16 4
/*FIFO FULL */ 1 &UIC0 0x15 4
/*FIFO HSDMA err */ 2 &UIC1 0x16 4>;
};
POB0: opb {
compatible = "ibm,opb-460ex", "ibm,opb";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
clock-frequency = <0>; /* Filled in by U-Boot */
EBC0: ebc {
compatible = "ibm,ebc-460ex", "ibm,ebc";
dcr-reg = <0x012 0x002>;
#address-cells = <2>;
#size-cells = <1>;
clock-frequency = <0>; /* Filled in by U-Boot */
/* ranges property is supplied by U-Boot */
ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
interrupts = <0x6 0x4>;
interrupt-parent = <&UIC1>;
nor_flash@0,0 {
compatible = "amd,s29gl512n", "cfi-flash";
bank-width = <2>;
reg = <0x00000000 0x00000000 0x00800000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x00280000>;
};
partition@280000 {
label = "romfs";
reg = <0x00280000 0x00480000>;
};
partition@700000 {
label = "dtb";
reg = <0x00700000 0x00010000>;
};
partition@703000 {
label = "Reserved";
reg = <0x00710000 0x00070000>;
};
partition@770000 {
label = "env";
reg = <0x00780000 0x00020000>;
};
partition@790000 {
label = "u-boot";
reg = <0x007A0000 0x00060000>;
};
};
ndfc@1,0 {
compatible = "ibm,ndfc";
reg = <00000003 00000000 00002000>;
ccr = <0x00001000>;
bank-settings = <0x80002222>;
#address-cells = <1>;
#size-cells = <1>;
nand {
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Free space";
reg = <0 0x10000000>;
};
};
};
};
EXT_INT0: ext_int0 {
compatible = "amcc,ext_int-460ex";
interrupt-parent = <&EXT_INT0>;
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
reg = < 0xef600b00 0x80 /* GPIO 0 */
0xef600c00 0x80>; /* GPIO 1 */
interrupt-map = <0x0 &UIC1 0x00 0x2
0x1 &UIC0 0x12 0x2
0x2 &UIC0 0x9 0x2
0x3 &UIC3 0x14 0x2
0x4 &UIC3 0x15 0x2
0x5 &UIC1 0x1E 0x2
0x6 &UIC1 0x15 0x2
0x7 &UIC1 0x14 0x2
0x8 &UIC2 0x2 0x2>;
};
mute {
compatible = "mute";
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-parent = <&UIC3>;
interrupts = <0x14 0x2>;
};
UART0: serial@ef600300 {
device_type = "serial";
compatible = "ns16550";
reg = <0xef600300 0x00000008>;
virtual-reg = <0xef600300>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
interrupts = <0x1 0x4>;
};
UART1: serial@ef600400 {
device_type = "serial";
compatible = "ns16550";
reg = <0xef600400 0x00000008>;
virtual-reg = <0xef600400>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC0>;
interrupts = <0x1 0x4>;
};
UART2: serial@ef600500 {
device_type = "serial";
compatible = "ns16550";
reg = <0xef600500 0x00000008>;
virtual-reg = <0xef600500>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
interrupts = <0x1d 0x4>;
};
UART3: serial@ef600600 {
device_type = "serial";
compatible = "ns16550";
reg = <0xef600600 0x00000008>;
virtual-reg = <0xef600600>;
clock-frequency = <0>; /* Filled in by U-Boot */
current-speed = <0>; /* Filled in by U-Boot */
interrupt-parent = <&UIC1>;
interrupts = <0x1e 0x4>;
};
IIC0: i2c@ef600700 {
compatible = "ibm,iic-460ex", "ibm,iic";
reg = <0xef600700 0x00000014>;
interrupt-parent = <&UIC0>;
interrupts = <0x2 0x4>;
#address-cells = <1>;
#size-cells = <0>;
rtc@68 {
compatible = "stm,m41t80";
reg = <0x68>;
interrupt-parent = <&UIC2>;
interrupts = <0x19 0x8>;
};
sttm@48 {
compatible = "ad,ad7414";
reg = <0x48>;
interrupt-parent = <&UIC1>;
interrupts = <0x14 0x8>;
};
};
IIC1: i2c@ef600800 {
compatible = "ibm,iic-460ex", "ibm,iic";
reg = <0xef600800 0x00000014>;
interrupt-parent = <&UIC0>;
interrupts = <0x3 0x4>;
#address-cells = <1>;
#size-cells = <0>;
hwmonitor@2D {
compatible = "wb,w83793";
reg = <0x2D>;
/*interrupt-parent = <&UIC1>;*/
/*interrupts = <0x14 0x8>;*/
};
};
ZMII0: emac-zmii@ef600d00 {
compatible = "ibm,zmii-460ex", "ibm,zmii";
reg = <0xef600d00 0x0000000c>;
};
RGMII0: emac-rgmii@ef601500 {
compatible = "ibm,rgmii-460ex", "ibm,rgmii";
reg = <0xef601500 0x00000008>;
has-mdio;
};
TAH0: emac-tah@ef601350 {
compatible = "ibm,tah-460ex", "ibm,tah";
reg = <0xef601350 0x00000030>;
};
TAH1: emac-tah@ef601450 {
compatible = "ibm,tah-460ex", "ibm,tah";
reg = <0xef601450 0x00000030>;
};
EMAC0: ethernet@ef600e00 {
device_type = "network";
compatible = "ibm,emac-460ex", "ibm,emac4sync";
interrupt-parent = <&EMAC0>;
interrupts = <0x0 0x1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
reg = <0xef600e00 0x000000c4>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <0>;
mal-rx-channel = <0>;
cell-index = <0>;
max-frame-size = <9000>;
rx-fifo-size = <4096>;
tx-fifo-size = <2048>;
phy-mode = "rgmii";
phy-map = <0x00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <0>;
tah-device = <&TAH0>;
tah-channel = <0>;
has-inverted-stacr-oc;
has-new-stacr-staopc;
};
EMAC1: ethernet@ef600f00 {
device_type = "network";
compatible = "ibm,emac-460ex", "ibm,emac4sync";
interrupt-parent = <&EMAC1>;
interrupts = <0x0 0x1>;
#interrupt-cells = <1>;
#address-cells = <0>;
#size-cells = <0>;
interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
/*Wake*/ 0x1 &UIC2 0x15 0x4>;
reg = <0xef600f00 0x000000c4>;
local-mac-address = [000000000000]; /* Filled in by U-Boot */
mal-device = <&MAL0>;
mal-tx-channel = <1>;
mal-rx-channel = <8>;
cell-index = <1>;
max-frame-size = <9000>;
rx-fifo-size = <4096>;
tx-fifo-size = <2048>;
phy-mode = "rgmii";
phy-map = <0x00000000>;
rgmii-device = <&RGMII0>;
rgmii-channel = <1>;
tah-device = <&TAH1>;
tah-channel = <1>;
has-inverted-stacr-oc;
has-new-stacr-staopc;
mdio-device = <&EMAC0>;
};
};
DMA: plb_dma@400300200 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "amcc,dma";
cell-index = <0>;
reg = <4 00300200 200>;
dcr-reg = <0x100 0x13f>;
interrupt-parent = <&UIC0>;
interrupts = <0 1 2 3>;
interrupt-map = < /*chan 0*/ 0 &UIC0 12 4
/* chan1*/ 1 &UIC0 13 4
/* chan2*/ 2 &UIC0 14 4
/* chan3*/ 3 &UIC0 15 4>;
dma-4channel@0{
compatible = "amcc,dma-4channel";
cell-index = <0>;
label = "channel0";
reg = <0x100 0x107>;
};
dma-4channel@1 {
compatible = "amcc,dma-4channel";
cell-index = <1>;
label = "channel1";
reg = <0x108 0x10f>;
};
dma-4channel@2 {
compatible = "amcc,dma-4channel";
cell-index = <2>;
label = "channel2";
reg = <0x110 0x117>;
};
dma-4channel@3 {
compatible = "amcc,dma-4channel";
cell-index = <3>;
label = "channel3";
reg = <0x118 0x11f>;
};
};
PCIX0: pci@c0ec00000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
primary;
large-inbound-windows;
enable-msi-hole;
reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
0x00000000 0x00000000 0x00000000 /* no IACK cycles */
0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
/* Outbound ranges, one memory and one IO,
* later cannot be changed
*/
ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
/* This drives busses 0 to 0x3f */
bus-range = <0x0 0x3f>;
/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
};
PCIE0: pciex@d00000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
primary;
port = <0x0>; /* port number */
reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
0x0000000c 0x08010000 0x00001000>; /* Registers */
dcr-reg = <0x100 0x020>;
sdr-base = <0x300>;
/* Outbound ranges, one memory and one IO,
* later cannot be changed
*/
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
/* This drives busses 40 to 0x7f */
bus-range = <0x40 0x7f>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* We are de-swizzling here because the numbers are actually for
* port of the root complex virtual P2P bridge. But I want
* to avoid putting a node for it in the tree, so the numbers
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
};
PCIE1: pciex@d20000000 {
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
primary;
port = <0x1>; /* port number */
reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
0x0000000c 0x08011000 0x00001000>; /* Registers */
dcr-reg = <0x120 0x020>;
sdr-base = <0x340>;
/* Outbound ranges, one memory and one IO,
* later cannot be changed
*/
ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
/* This drives busses 80 to 0xbf */
bus-range = <0x80 0xbf>;
/* Legacy interrupts (note the weird polarity, the bridge seems
* to invert PCIe legacy interrupts).
* We are de-swizzling here because the numbers are actually for
* port of the root complex virtual P2P bridge. But I want
* to avoid putting a node for it in the tree, so the numbers
* below are basically de-swizzled numbers.
* The real slot is on idsel 0, so the swizzling is 1:1
*/
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <
0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
};
};
};
^ permalink raw reply
* Re: [PATCH v4]PPC4xx: Adding PCI(E) MSI support
From: Josh Boyer @ 2011-05-19 12:53 UTC (permalink / raw)
To: Rupjyoti Sarmah; +Cc: linuxppc-dev, rsarmah, linux-kernel
In-Reply-To: <201103300910.p2U9AO8t024353@amcc.com>
On Wed, Mar 30, 2011 at 02:40:24PM +0530, Rupjyoti Sarmah wrote:
>This patch adds MSI support for 440SPe, 460Ex, 460Sx and 405Ex.
>
>Signed-off-by: Rupjyoti Sarmah <rsarmah@apm.com>
>Signed-off-by: Tirumala R Marri <tmarri@apm.com>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
>---
>v4:
> * Updated the coding style as per recommendation by Philipp
> * The goto style code removed as per suggestion
>v3:
> * Rebased to Josh next tree
> * Cleanup and remove some unwanted log msg.
> * Remove list member and its references.
> * Keep msi_data local reference.
>v2:
> * Remove or add blank lines at appropriate places.
> * Added BITMAP as it is easy to request and free the MSIs
> * Removed UPPER_4BITS_OF36BIT & LOWER_32BITS_OF36BIT;
> * Remove unused feature variable.
> * Remove initialization of "virq".
> * remove static int_no varaible and replace with bitmap.
> * Eliminated reading count from DTS tree and added a macro.
> * Remove printK.
> * Remove else in setup_irqs.
> * Free interrupts in teardown_msi_interrupts().
> * Print contraints in check_device().
> * Replace ioremap with of_iomap().
> * Use msi_data in setup_pcieh_hw().
> * Don't unmap in the setup_pcieh_hw().
> * don't use WARN_ON.
> * Remove ppc4xx_msi_ids[].
>---
> arch/powerpc/boot/dts/canyonlands.dts | 18 ++
> arch/powerpc/boot/dts/katmai.dts | 18 ++
> arch/powerpc/boot/dts/kilauea.dts | 28 ++++
> arch/powerpc/boot/dts/redwood.dts | 20 +++
> arch/powerpc/platforms/40x/Kconfig | 2 +
> arch/powerpc/platforms/44x/Kconfig | 6 +
> arch/powerpc/sysdev/Kconfig | 7 +
> arch/powerpc/sysdev/Makefile | 1 +
> arch/powerpc/sysdev/ppc4xx_msi.c | 277 +++++++++++++++++++++++++++++++++
> 9 files changed, 377 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/sysdev/ppc4xx_msi.c
>
>diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
>index 2779f08..22dd6ae 100644
>--- a/arch/powerpc/boot/dts/canyonlands.dts
>+++ b/arch/powerpc/boot/dts/canyonlands.dts
>@@ -530,5 +530,23 @@
> 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
> 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
> };
>+
>+ MSI: ppc4xx-msi@C10000000 {
>+ compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
>+ reg = < 0xC 0x10000000 0x100>;
>+ sdr-base = <0x36C>;
>+ msi-data = <0x00000000>;
>+ msi-mask = <0x44440000>;
>+ interrupt-count = <3>;
>+ interrupts = <0 1 2 3>;
>+ interrupt-parent = <&UIC3>;
>+ #interrupt-cells = <1>;
>+ #address-cells = <0>;
>+ #size-cells = <0>;
>+ interrupt-map = <0 &UIC3 0x18 1
>+ 1 &UIC3 0x19 1
>+ 2 &UIC3 0x1A 1
>+ 3 &UIC3 0x1B 1>;
>+ };
> };
> };
>diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
>index 7c3be5e..f913dbe 100644
>--- a/arch/powerpc/boot/dts/katmai.dts
>+++ b/arch/powerpc/boot/dts/katmai.dts
>@@ -442,6 +442,24 @@
> 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
> };
>
>+ MSI: ppc4xx-msi@400300000 {
>+ compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
>+ reg = < 0x4 0x00300000 0x100>;
>+ sdr-base = <0x3B0>;
>+ msi-data = <0x00000000>;
>+ msi-mask = <0x44440000>;
>+ interrupt-count = <3>;
>+ interrupts =<0 1 2 3>;
>+ interrupt-parent = <&UIC0>;
>+ #interrupt-cells = <1>;
>+ #address-cells = <0>;
>+ #size-cells = <0>;
>+ interrupt-map = <0 &UIC0 0xC 1
>+ 1 &UIC0 0x0D 1
>+ 2 &UIC0 0x0E 1
>+ 3 &UIC0 0x0F 1>;
>+ };
>+
> I2O: i2o@400100000 {
> compatible = "ibm,i2o-440spe";
> reg = <0x00000004 0x00100000 0x100>;
>diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
>index 89edb16..1613d6e 100644
>--- a/arch/powerpc/boot/dts/kilauea.dts
>+++ b/arch/powerpc/boot/dts/kilauea.dts
>@@ -403,5 +403,33 @@
> 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
> 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
> };
>+
>+ MSI: ppc4xx-msi@C10000000 {
>+ compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
>+ reg = < 0x0 0xEF620000 0x100>;
>+ sdr-base = <0x4B0>;
>+ msi-data = <0x00000000>;
>+ msi-mask = <0x44440000>;
>+ interrupt-count = <12>;
>+ interrupts = <0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD>;
>+ interrupt-parent = <&UIC2>;
>+ #interrupt-cells = <1>;
>+ #address-cells = <0>;
>+ #size-cells = <0>;
>+ interrupt-map = <0 &UIC2 0x10 1
>+ 1 &UIC2 0x11 1
>+ 2 &UIC2 0x12 1
>+ 2 &UIC2 0x13 1
>+ 2 &UIC2 0x14 1
>+ 2 &UIC2 0x15 1
>+ 2 &UIC2 0x16 1
>+ 2 &UIC2 0x17 1
>+ 2 &UIC2 0x18 1
>+ 2 &UIC2 0x19 1
>+ 2 &UIC2 0x1A 1
>+ 2 &UIC2 0x1B 1
>+ 2 &UIC2 0x1C 1
>+ 3 &UIC2 0x1D 1>;
>+ };
> };
> };
>diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
>index 81636c0..d86a3a4 100644
>--- a/arch/powerpc/boot/dts/redwood.dts
>+++ b/arch/powerpc/boot/dts/redwood.dts
>@@ -358,8 +358,28 @@
> 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
> };
>
>+ MSI: ppc4xx-msi@400300000 {
>+ compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
>+ reg = < 0x4 0x00300000 0x100
>+ 0x4 0x00300000 0x100>;
>+ sdr-base = <0x3B0>;
>+ msi-data = <0x00000000>;
>+ msi-mask = <0x44440000>;
>+ interrupt-count = <3>;
>+ interrupts =<0 1 2 3>;
>+ interrupt-parent = <&UIC0>;
>+ #interrupt-cells = <1>;
>+ #address-cells = <0>;
>+ #size-cells = <0>;
>+ interrupt-map = <0 &UIC0 0xC 1
>+ 1 &UIC0 0x0D 1
>+ 2 &UIC0 0x0E 1
>+ 3 &UIC0 0x0F 1>;
>+ };
>+
> };
>
>+
> chosen {
> linux,stdout-path = "/plb/opb/serial@ef600200";
> };
>diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
>index b721764..92aeee6 100644
>--- a/arch/powerpc/platforms/40x/Kconfig
>+++ b/arch/powerpc/platforms/40x/Kconfig
>@@ -57,6 +57,8 @@ config KILAUEA
> select 405EX
> select PPC40x_SIMPLE
> select PPC4xx_PCI_EXPRESS
>+ select PCI_MSI
>+ select 4xx_MSI
> help
> This option enables support for the AMCC PPC405EX evaluation board.
>
>diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
>index f485fc5..f10cc7f 100644
>--- a/arch/powerpc/platforms/44x/Kconfig
>+++ b/arch/powerpc/platforms/44x/Kconfig
>@@ -74,6 +74,8 @@ config KATMAI
> select 440SPe
> select PCI
> select PPC4xx_PCI_EXPRESS
>+ select PCI_MSI
>+ select 4xx_MSI
> help
> This option enables support for the AMCC PPC440SPe evaluation board.
>
>@@ -118,6 +120,8 @@ config CANYONLANDS
> select 460EX
> select PCI
> select PPC4xx_PCI_EXPRESS
>+ select PCI_MSI
>+ select 4xx_MSI
> select IBM_NEW_EMAC_RGMII
> select IBM_NEW_EMAC_ZMII
> help
>@@ -144,6 +148,8 @@ config REDWOOD
> select 460SX
> select PCI
> select PPC4xx_PCI_EXPRESS
>+ select PCI_MSI
>+ select 4xx_MSI
> help
> This option enables support for the AMCC PPC460SX Redwood board.
>
>diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
>index 3965828..32f5a40 100644
>--- a/arch/powerpc/sysdev/Kconfig
>+++ b/arch/powerpc/sysdev/Kconfig
>@@ -7,8 +7,15 @@ config PPC4xx_PCI_EXPRESS
> depends on PCI && 4xx
> default n
>
>+config 4xx_MSI
>+ bool
>+ depends on PCI_MSI
>+ depends on PCI && 4xx
>+ default n
>+
> config PPC_MSI_BITMAP
> bool
> depends on PCI_MSI
> default y if MPIC
> default y if FSL_PCI
>+ default y if 4xx_MSI
>diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
>index 1e0c933..5d92e29 100644
>--- a/arch/powerpc/sysdev/Makefile
>+++ b/arch/powerpc/sysdev/Makefile
>@@ -41,6 +41,7 @@ obj-$(CONFIG_OF_RTC) += of_rtc.o
> ifeq ($(CONFIG_PCI),y)
> obj-$(CONFIG_4xx) += ppc4xx_pci.o
> endif
>+obj-$(CONFIG_4xx_MSI) += ppc4xx_msi.o
> obj-$(CONFIG_PPC4xx_CPM) += ppc4xx_cpm.o
> obj-$(CONFIG_PPC4xx_GPIO) += ppc4xx_gpio.o
>
>diff --git a/arch/powerpc/sysdev/ppc4xx_msi.c b/arch/powerpc/sysdev/ppc4xx_msi.c
>new file mode 100644
>index 0000000..ab69edb
>--- /dev/null
>+++ b/arch/powerpc/sysdev/ppc4xx_msi.c
>@@ -0,0 +1,277 @@
>+/*
>+ * Adding PCI-E MSI support for PPC4XX SoCs.
>+ *
>+ * Copyright (c) 2010, Applied Micro Circuits Corporation
>+ * Authors: Tirumala R Marri <tmarri@apm.com>
>+ * Feng Kan <fkan@apm.com>
>+ *
>+ * This program is free software; you can redistribute it and/or
>+ * modify it under the terms of the GNU General Public License as
>+ * published by the Free Software Foundation; either version 2 of
>+ * the License, or (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ *
>+ * You should have received a copy of the GNU General Public License
>+ * along with this program; if not, write to the Free Software
>+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>+ * MA 02111-1307 USA
>+ */
>+
>+#include <linux/irq.h>
>+#include <linux/bootmem.h>
>+#include <linux/pci.h>
>+#include <linux/msi.h>
>+#include <linux/of_platform.h>
>+#include <linux/interrupt.h>
>+#include <asm/prom.h>
>+#include <asm/hw_irq.h>
>+#include <asm/ppc-pci.h>
>+#include <boot/dcr.h>
>+#include <asm/dcr-regs.h>
>+#include <asm/msi_bitmap.h>
>+
>+#define PEIH_TERMADH 0x00
>+#define PEIH_TERMADL 0x08
>+#define PEIH_MSIED 0x10
>+#define PEIH_MSIMK 0x18
>+#define PEIH_MSIASS 0x20
>+#define PEIH_FLUSH0 0x30
>+#define PEIH_FLUSH1 0x38
>+#define PEIH_CNTRST 0x48
>+#define NR_MSI_IRQS 4
>+
>+struct ppc4xx_msi {
>+ u32 msi_addr_lo;
>+ u32 msi_addr_hi;
>+ void __iomem *msi_regs;
>+ int msi_virqs[NR_MSI_IRQS];
>+ struct msi_bitmap bitmap;
>+ struct device_node *msi_dev;
>+};
>+
>+static struct ppc4xx_msi ppc4xx_msi;
>+
>+static int ppc4xx_msi_init_allocator(struct platform_device *dev,
>+ struct ppc4xx_msi *msi_data)
>+{
>+ int err;
>+
>+ err = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
>+ dev->dev.of_node);
>+ if (err)
>+ return err;
>+
>+ err = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
>+ if (err < 0) {
>+ msi_bitmap_free(&msi_data->bitmap);
>+ return err;
>+ }
>+
>+ return 0;
>+}
>+
>+static int ppc4xx_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
>+{
>+ int int_no = -ENOMEM;
>+ unsigned int virq;
>+ struct msi_msg msg;
>+ struct msi_desc *entry;
>+ struct ppc4xx_msi *msi_data = &ppc4xx_msi;
>+
>+ list_for_each_entry(entry, &dev->msi_list, list) {
>+ int_no = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
>+ if (int_no >= 0)
>+ break;
>+ if (int_no < 0) {
>+ pr_debug("%s: fail allocating msi interrupt\n",
>+ __func__);
>+ }
>+ virq = irq_of_parse_and_map(msi_data->msi_dev, int_no);
>+ if (virq == NO_IRQ) {
>+ dev_err(&dev->dev, "%s: fail mapping irq\n", __func__);
>+ msi_bitmap_free_hwirqs(&msi_data->bitmap, int_no, 1);
>+ return -ENOSPC;
>+ }
>+ set_irq_data(virq, (void *)int_no);
>+ dev_dbg(&dev->dev, "%s: virq = %d\n", __func__, virq);
>+
>+ /* Setup msi address space */
>+ msg.address_hi = msi_data->msi_addr_hi;
>+ msg.address_lo = msi_data->msi_addr_lo;
>+
>+ set_irq_msi(virq, entry);
>+ msg.data = int_no;
>+ write_msi_msg(virq, &msg);
>+ }
>+ return 0;
>+}
>+
>+void ppc4xx_teardown_msi_irqs(struct pci_dev *dev)
>+{
>+ struct msi_desc *entry;
>+ struct ppc4xx_msi *msi_data = &ppc4xx_msi;
>+
>+ dev_dbg(&dev->dev, "PCIE-MSI: tearing down msi irqs\n");
>+
>+ list_for_each_entry(entry, &dev->msi_list, list) {
>+ if (entry->irq == NO_IRQ)
>+ continue;
>+ set_irq_msi(entry->irq, NULL);
>+ msi_bitmap_free_hwirqs(&msi_data->bitmap,
>+ virq_to_hw(entry->irq), 1);
>+ irq_dispose_mapping(entry->irq);
>+ }
>+}
>+
>+static int ppc4xx_msi_check_device(struct pci_dev *pdev, int nvec, int type)
>+{
>+ dev_dbg(&pdev->dev, "PCIE-MSI:%s called. vec %x type %d\n",
>+ __func__, nvec, type);
>+ if (type == PCI_CAP_ID_MSIX)
>+ pr_debug("ppc4xx msi: MSI-X untested, trying anyway.\n");
>+
>+ return 0;
>+}
>+
>+static int ppc4xx_setup_pcieh_hw(struct platform_device *dev,
>+ struct resource res, struct ppc4xx_msi *msi)
>+{
>+ const u32 *msi_data;
>+ const u32 *msi_mask;
>+ const u32 *sdr_addr;
>+ dma_addr_t msi_phys;
>+ void *msi_virt;
>+
>+ sdr_addr = of_get_property(dev->dev.of_node, "sdr-base", NULL);
>+ if (!sdr_addr)
>+ return -1;
>+
>+ SDR0_WRITE(sdr_addr, (u64)res.start >> 32); /*HIGH addr */
>+ SDR0_WRITE(sdr_addr + 1, res.start & 0xFFFFFFFF); /* Low addr */
>+
>+
>+ msi->msi_dev = of_find_node_by_name(NULL, "ppc4xx-msi");
>+ if (msi->msi_dev)
>+ return -ENODEV;
>+
>+ msi->msi_regs = of_iomap(msi->msi_dev, 0);
>+ if (!msi->msi_regs) {
>+ dev_err(&dev->dev, "of_iomap problem failed\n");
>+ return -ENOMEM;
>+ }
>+ dev_dbg(&dev->dev, "PCIE-MSI: msi register mapped 0x%x 0x%x\n",
>+ (u32) (msi->msi_regs + PEIH_TERMADH), (u32) (msi->msi_regs));
>+
>+ msi_virt = dma_alloc_coherent(&dev->dev, 64, &msi_phys, GFP_KERNEL);
>+ msi->msi_addr_hi = 0x0;
>+ msi->msi_addr_lo = (u32) msi_phys;
>+ dev_dbg(&dev->dev, "PCIE-MSI: msi address 0x%x\n", msi->msi_addr_lo);
>+
>+ /* Progam the Interrupt handler Termination addr registers */
>+ out_be32(msi->msi_regs + PEIH_TERMADH, msi->msi_addr_hi);
>+ out_be32(msi->msi_regs + PEIH_TERMADL, msi->msi_addr_lo);
>+
>+ msi_data = of_get_property(dev->dev.of_node, "msi-data", NULL);
>+ if (!msi_data)
>+ return -1;
>+ msi_mask = of_get_property(dev->dev.of_node, "msi-mask", NULL);
>+ if (!msi_mask)
>+ return -1;
>+ /* Program MSI Expected data and Mask bits */
>+ out_be32(msi->msi_regs + PEIH_MSIED, *msi_data);
>+ out_be32(msi->msi_regs + PEIH_MSIMK, *msi_mask);
>+
>+ return 0;
>+}
>+
>+static int ppc4xx_of_msi_remove(struct platform_device *dev)
>+{
>+ struct ppc4xx_msi *msi = dev->dev.platform_data;
>+ int i;
>+ int virq;
>+
>+ for (i = 0; i < NR_MSI_IRQS; i++) {
>+ virq = msi->msi_virqs[i];
>+ if (virq != NO_IRQ)
>+ irq_dispose_mapping(virq);
>+ }
>+
>+ if (msi->bitmap.bitmap)
>+ msi_bitmap_free(&msi->bitmap);
>+ iounmap(msi->msi_regs);
>+ of_node_put(msi->msi_dev);
>+ kfree(msi);
>+
>+ return 0;
>+}
>+
>+static int __devinit ppc4xx_msi_probe(struct platform_device *dev)
>+{
>+ struct ppc4xx_msi *msi;
>+ struct resource res;
>+ int err = 0;
>+
>+ msi = &ppc4xx_msi;/*keep the msi data for further use*/
>+
>+ dev_dbg(&dev->dev, "PCIE-MSI: Setting up MSI support...\n");
>+
>+ msi = kzalloc(sizeof(struct ppc4xx_msi), GFP_KERNEL);
>+ if (!msi) {
>+ dev_err(&dev->dev, "No memory for MSI structure\n");
>+ return -ENOMEM;
>+ }
>+ dev->dev.platform_data = msi;
>+
>+ /* Get MSI ranges */
>+ err = of_address_to_resource(dev->dev.of_node, 0, &res);
>+ if (err) {
>+ dev_err(&dev->dev, "%s resource error!\n",
>+ dev->dev.of_node->full_name);
>+ goto error_out;
>+ }
>+
>+ if (ppc4xx_setup_pcieh_hw(dev, res, msi))
>+ goto error_out;
>+
>+ err = ppc4xx_msi_init_allocator(dev, msi);
>+ if (err) {
>+ dev_err(&dev->dev, "Error allocating MSI bitmap\n");
>+ goto error_out;
>+ }
>+
>+ ppc_md.setup_msi_irqs = ppc4xx_setup_msi_irqs;
>+ ppc_md.teardown_msi_irqs = ppc4xx_teardown_msi_irqs;
>+ ppc_md.msi_check_device = ppc4xx_msi_check_device;
>+ return err;
>+
>+error_out:
>+ ppc4xx_of_msi_remove(dev);
>+ return err;
>+}
>+static const struct of_device_id ppc4xx_msi_ids[] = {
>+ {
>+ .compatible = "amcc,ppc4xx-msi",
>+ },
>+ {}
>+};
>+static struct platform_driver ppc4xx_msi_driver = {
>+ .probe = ppc4xx_msi_probe,
>+ .remove = ppc4xx_of_msi_remove,
>+ .driver = {
>+ .name = "ppc4xx-msi",
>+ .owner = THIS_MODULE,
>+ .of_match_table = ppc4xx_msi_ids,
>+ },
>+
>+};
>+
>+static __init int ppc4xx_msi_init(void)
>+{
>+ return platform_driver_register(&ppc4xx_msi_driver);
>+}
>+
>+subsys_initcall(ppc4xx_msi_init);
>--
>1.5.6.3
>
>_______________________________________________
>Linuxppc-dev mailing list
>Linuxppc-dev@lists.ozlabs.org
>https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 4/7] [RFC] enable L1_WRITETHROUGH mode for BG/P
From: Eric Van Hensbergen @ 2011-05-19 12:53 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, linux-kernel, bg-linux
In-Reply-To: <20110519104330.GA25179@zod.rchland.ibm.com>
On Thu, May 19, 2011 at 5:43 AM, Josh Boyer <jwboyer@linux.vnet.ibm.com> wr=
ote:
> On Wed, May 18, 2011 at 04:24:52PM -0500, Eric Van Hensbergen wrote:
>>
>>+config L1_WRITETHROUGH
>>+ =A0 =A0 =A0bool "Blue Gene/P enabled writethrough mode"
>>+ =A0 =A0 =A0depends on BGP
>>+ =A0 =A0 =A0default y
>
> You add this config option here, named generically, but then make it
> depend on BGP. =A0It sees it should be named BGP_L1_WRITETHROUGH, and the=
n
> just selected by the BGP platform. =A0But then....
>
>> endmenu
>>diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platfo=
rms/Kconfig.cputype
>>index 111138c..3a3c711 100644
>>--- a/arch/powerpc/platforms/Kconfig.cputype
>>+++ b/arch/powerpc/platforms/Kconfig.cputype
>>@@ -329,9 +329,13 @@ config NOT_COHERENT_CACHE
>> =A0 =A0 =A0 bool
>> =A0 =A0 =A0 depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COM=
MON
>> =A0 =A0 =A0 default n if PPC_47x
>>+ =A0 =A0 =A0default n if BGP
>> =A0 =A0 =A0 default y
>>
>> config CHECK_CACHE_COHERENCY
>> =A0 =A0 =A0 bool
>>
>>+config L1_WRITETHROUGH
>>+ =A0 =A0 =A0bool
>
> You add an identical option down here. =A0Confused.
>
Yeah, this was copied from the original patches and it confused me as
well, but I had never
modified Kconfig.cputype before so I wasn't sure if there were some
weird rules. I'm happy
to remove the vestigial one and make the changes you suggest to make
the naming BGP
specific.
-eric
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: add host-pci(e) bridge only for RC
From: Kumar Gala @ 2011-05-19 13:22 UTC (permalink / raw)
To: Kushwaha Prabhakar-B32579
Cc: meet2prabhu@gmail.com, linuxppc-dev@lists.ozlabs.org,
Vivek Mahajan
In-Reply-To: <071A08F2C6A57E4E94D980ECA553F8741D5C9C@039-SN1MPN1-005.039d.mgd.msft.net>
On May 19, 2011, at 6:25 AM, Kushwaha Prabhakar-B32579 wrote:
> Hello Kumar,
> Please find my answer in-lined
>=20
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Thursday, May 19, 2011 11:55 AM
>> To: Kushwaha Prabhakar-B32579
>> Cc: linuxppc-dev@lists.ozlabs.org; meet2prabhu@gmail.com; Vivek =
Mahajan
>> Subject: Re: [PATCH] powerpc/85xx: add host-pci(e) bridge only for RC
>>=20
>>=20
>> On Apr 27, 2011, at 12:35 AM, Prabhakar Kushwaha wrote:
>>=20
>>> FSL PCIe controller can act as agent(EP) or host(RC).
>>> Under Agent(EP) mode they are configured via Host. So it is not
>>> required to add with the PCI(e) sub-system.
>>>=20
>>> Add and configure PCIe controller only for RC mode.
>>>=20
>>> Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
>>> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
>>> ---
>>> Based upon
>>> =
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git(b
>>> ranch master)
>>>=20
>>> arch/powerpc/sysdev/fsl_pci.c | 14 ++++++++++++++
>>> 1 files changed, 14 insertions(+), 0 deletions(-)
>>>=20
>>> diff --git a/arch/powerpc/sysdev/fsl_pci.c
>>> b/arch/powerpc/sysdev/fsl_pci.c index 68ca929..87ac11b 100644
>>> --- a/arch/powerpc/sysdev/fsl_pci.c
>>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>>> @@ -323,6 +323,7 @@ int __init fsl_add_bridge(struct device_node =
*dev,
>> int is_primary)
>>> struct pci_controller *hose;
>>> struct resource rsrc;
>>> const int *bus_range;
>>> + u8 is_agent;
>>>=20
>>> if (!of_device_is_available(dev)) {
>>> pr_warning("%s: disabled\n", dev->full_name); @@ -353,6
>> +354,19 @@
>>> int __init fsl_add_bridge(struct device_node *dev, int is_primary)
>>>=20
>>> setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>>> PPC_INDIRECT_TYPE_BIG_ENDIAN);
>>> +
>>> + early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &is_agent);
>>=20
>> Why are we looking at PCI_HEADER_TYPE? We should look at =
PCI_CLASS_PROG.
>=20
> I think both are OK. We can check for any one.=20
> Is there any problem with PCI_HEADER_TYPE?
Let use PCI_CLASS_PROG as its explicit for this purpose of determining =
agent/host across PCI, PCI-X, PCIe
>=20
>=20
>>> + if ((is_agent & 0x7f) =3D=3D PCI_HEADER_TYPE_NORMAL) {
>>> + u32 temp;
>>> +
>>> + temp =3D (u32)hose->cfg_data & ~PAGE_MASK;
>>> + if (((u32)hose->cfg_data & PAGE_MASK) !=3D =
(u32)hose->cfg_addr)
>>> + iounmap(hose->cfg_data - temp);
>>> + iounmap(hose->cfg_addr);
>>> + pcibios_free_controller(hose);
>>> + return 0;
>>> + }
>>> +
>>> setup_pci_cmd(hose);
>>>=20
>>> /* check PCI express link status */
>>> --
>>> 1.7.3
>>>=20
>>>=20
>>> _______________________________________________
>>> Linuxppc-dev mailing list
>>> Linuxppc-dev@lists.ozlabs.org
>>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>>=20
>=20
^ permalink raw reply
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