* [PATCH 13/15] 8xx: Use symbolic constants in TLB asm
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Use the PTE #defines where possible instead of
hardcoded constants.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 12 ++++++------
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index d701542..a4290b5 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -442,11 +442,11 @@ DataStoreTLBMiss:
* this into the Linux pgd/pmd and load it in the operation
* above.
*/
- rlwimi r21, r20, 0, 27, 27
+ rlwimi r21, r20, 0, _PAGE_GUARDED
/* Insert the WriteThru flag into the TWC from the Linux PTE.
* It is bit 25 in the Linux PTE and bit 30 in the TWC
*/
- rlwimi r21, r20, 32-5, 30, 30
+ rlwimi r21, r20, 32-5, _PAGE_WRITETHRU>>5
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
@@ -460,9 +460,9 @@ DataStoreTLBMiss:
/* Honour kernel RO, User NA */
/* 0x200 == Extended encoding, bit 22 */
/* r20 |= (r20 & _PAGE_USER) >> 2 */
- rlwimi r20, r20, 32-2, 0x200
+ rlwimi r20, r20, 32-2, _PAGE_USER>>2 /* Copy USER to Encoding */
/* r21 = (r20 & _PAGE_RW) >> 1 */
- rlwinm r21, r20, 32-1, 0x200
+ rlwinm r21, r20, 32-1, _PAGE_RW>>1
or r20, r21, r20
/* invert RW and 0x200 bits */
xori r20, r20, _PAGE_RW | 0x200
@@ -582,11 +582,11 @@ DARFixed:
/* Insert the Guarded flag into the TWC from the Linux PTE.
* It is bit 27 of both the Linux PTE and the TWC
*/
- rlwimi r21, r20, 0, 27, 27
+ rlwimi r21, r20, 0, _PAGE_GUARDED
/* Insert the WriteThru flag into the TWC from the Linux PTE.
* It is bit 25 in the Linux PTE and bit 30 in the TWC
*/
- rlwimi r21, r20, 32-5, 30, 30
+ rlwimi r21, r20, 32-5, _PAGE_WRITETHRU>>5
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
mfspr r21, MD_TWC /* get the pte address again */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 14/15] 8xx: Optimize ITLBMiss handler.
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Don't check for kernel space if no modules.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index a4290b5..7f9e647 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -355,12 +355,17 @@ InstructionTLBMiss:
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
+#ifdef CONFIG_MODULES
+ /* Since we PIN the first 8MB text, we only get ITLB misses
+ * for modules
+ */
andi. r21, r20, 0x0800 /* Address >= 0x80000000 */
beq 3f
lis r21, swapper_pg_dir@h
ori r21, r21, swapper_pg_dir@l
rlwimi r20, r21, 0, 2, 19
3:
+#endif
lwz r21, 0(r20) /* Get the level 1 entry */
rlwinm. r20, r21,0,0,19 /* Extract page descriptor page address */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 08/15] 8xx: CPU6 errata make DTLB error too big to fit.
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
branch to common code in DTLB Miss instead.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 23 ++---------------------
1 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index f4c3f41..44e79b3 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -469,6 +469,7 @@ DataStoreTLBMiss:
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
+finish_DTLB:
2: li r21, 0x00f0
mtspr DAR, r21 /* Tag DAR */
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
@@ -578,27 +579,7 @@ DARFixed:
ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
stw r20, 0(r21) /* and update pte in table */
xori r20, r20, _PAGE_RW /* RW bit is inverted */
-
- /* The Linux PTE won't go exactly into the MMU TLB.
- * Software indicator bits 22 and 28 must be clear.
- * Software indicator bits 24, 25, 26, and 27 must be
- * set. All other Linux PTE bits control the behavior
- * of the MMU.
- */
- li r21, 0x00f0
- mtspr DAR, r21 /* Tag DAR */
- rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
- DO_8xx_CPU6(0x3d80, r3)
- mtspr MD_RPN, r20 /* Update TLB entry */
-
- mfspr r20, M_TW /* Restore registers */
- lwz r21, 0(r0)
- mtcr r21
- lwz r21, 4(r0)
-#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0)
-#endif
- rfi
+ b finish_DTLB
2:
mfspr r20, M_TW /* Restore registers */
lwz r21, 0(r0)
--
1.7.3.4
^ permalink raw reply related
* [PATCH 00/15] Backport 8xx TLB to 2.4
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
This is a backport from 2.6 which I did to overcome 8xx CPU
bugs. 8xx does not update the DAR register when taking a TLB
error caused by dcbX and icbi insns which makes it very
tricky to use these insns. Also the dcbst wrongly sets the
the store bit when faulting into DTLB error.
A few more bugs very found during development.
I know 2.4 is in strict maintenance mode and 8xx is obsolete
but as it is still in use I wanted 8xx to age with grace.
Addendum:
I have now ported our 8xx custom board to 2.4.37.11 and
tested these patches there.
Joakim Tjernlund (15):
8xx: Use a macro to simpliy CPU6 errata code.
8xx: Tag DAR with 0x00f0 to catch buggy instructions.
8xx: invalidate non present TLBs
8xx: Fix CONFIG_PIN_TLB
8xx: Update TLB asm so it behaves as linux mm expects.
8xx: Always pin kernel instruction TLB
8xx: Fixup DAR from buggy dcbX instructions.
8xx: CPU6 errata make DTLB error too big to fit.
8xx: Add missing Guarded setting in DTLB Error.
8xx: Restore _PAGE_WRITETHRU
8xx: Set correct HW pte flags in DTLB Error too
8xx: start using dcbX instructions in various copy routines
8xx: Use symbolic constants in TLB asm
8xx: Optimize ITLBMiss handler.
8xx: Optimize TLB Miss handlers
arch/ppc/kernel/head_8xx.S | 381 ++++++++++++++++++++++++++++++-------------
arch/ppc/kernel/misc.S | 18 --
arch/ppc/lib/string.S | 17 --
include/asm-ppc/pgtable.h | 16 +-
4 files changed, 274 insertions(+), 158 deletions(-)
--
1.7.3.4
^ permalink raw reply
* [PATCH 03/15] 8xx: invalidate non present TLBs
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separately as 8xx MMU don't.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 12 ++++++++++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 57858ce..b3aff21 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -221,7 +221,11 @@ DataAccess:
mr r5,r20
mfspr r4,DAR
stw r4,_DAR(r21)
- li r20,0x00f0
+ /* invalidate ~PRESENT TLBs, 8xx MMU don't do this */
+ andis. r20,r5,0x4000
+ beq+ 1f
+ tlbie r4
+1: li r20,0x00f0
mtspr DAR,r20 /* Tag DAR */
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
@@ -238,7 +242,11 @@ InstructionAccess:
addi r3,r1,STACK_FRAME_OVERHEAD
mr r4,r22
mr r5,r23
- li r20,MSR_KERNEL
+ /* invalidate ~PRESENT TLBs, 8xx MMU don't do this */
+ andis. r20,r5,0x4000
+ beq+ 1f
+ tlbie r4
+1: li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
FINISH_EXCEPTION(do_page_fault)
--
1.7.3.4
^ permalink raw reply related
* [PATCH 15/15] 8xx: Optimize TLB Miss handlers
From: Joakim Tjernlund @ 2011-06-14 13:55 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Only update pte w.r.t ACCESSED if it isn't already set
Wrap ACCESSED with #ifndef NO_SWAP for too ease optimization.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 11 +++++++++--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 7f9e647..8f50ffb 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -382,10 +382,14 @@ InstructionTLBMiss:
mfspr r21, MD_TWC /* ....and get the pte address */
lwz r20, 0(r21) /* Get the pte */
-#if 1
+#ifndef NO_SWAP
/* if !swap, you can delete this */
+ andi. r21, r20, _PAGE_ACCESSED /* test ACCESSED bit */
+ bne+ 4f /* Branch if set */
+ mfspr r21, MD_TWC /* get the pte address */
rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */
stw r20, 0(r21) /* Update pte */
+4:
#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 21 and 28 must be clear.
@@ -455,11 +459,14 @@ DataStoreTLBMiss:
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
-#if 1
+#ifndef NO_SWAP
/* if !swap, you can delete this */
+ andi. r21, r20, _PAGE_ACCESSED /* test ACCESSED bit */
+ bne+ 4f /* Branch if set */
mfspr r21, MD_TWC /* get the pte address */
rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */
stw r20, 0(r21) /* Update pte */
+4:
#endif
/* Honour kernel RO, User NA */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 09/15] 8xx: Add missing Guarded setting in DTLB Error.
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 12 +++++++++---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 44e79b3..199ede5 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -573,9 +573,15 @@ DARFixed:
ori r21, r21, 1 /* Set valid bit in physical L2 page */
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21 /* Load pte table base address */
- mfspr r21, MD_TWC /* ....and get the pte address */
- lwz r20, 0(r21) /* Get the pte */
-
+ mfspr r20, MD_TWC /* ....and get the pte address */
+ lwz r20, 0(r20) /* Get the pte */
+ /* Insert the Guarded flag into the TWC from the Linux PTE.
+ * It is bit 27 of both the Linux PTE and the TWC
+ */
+ rlwimi r21, r20, 0, 27, 27
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr MD_TWC, r21
+ mfspr r21, MD_TWC /* get the pte address again */
ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
stw r20, 0(r21) /* and update pte in table */
xori r20, r20, _PAGE_RW /* RW bit is inverted */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 05/15] 8xx: Update TLB asm so it behaves as linux mm expects.
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Update the TLB asm to make proper use of _PAGE_DIRTY and _PAGE_ACCESSED.
Get rid of _PAGE_HWWRITE too.
Pros:
- PRESENT is copied to ACCESSED, fixing accounting
- DIRTY is mapped to 0x100, the changed bit, and is set directly
when a page has been made dirty.
- Proper RO/RW mapping of user space.
- Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?)
- kernel RO/user NA support. Not sure this is really needed, would save
a few insn if not required.
Cons:
- A few more instructions in the DTLB Miss routine.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 53 ++++++++++++++++++++++++++-----------------
include/asm-ppc/pgtable.h | 15 +++++------
2 files changed, 39 insertions(+), 29 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 9d8a1b5..c9770b6 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -369,25 +369,27 @@ InstructionTLBMiss:
*/
tophys(r21,r21)
ori r21,r21,1 /* Set valid bit */
- beq- 2f /* If zero, don't try to find a pte */
DO_8xx_CPU6(0x2b80, r3)
mtspr MI_TWC, r21 /* Set segment attributes */
+ beq- 2f /* If zero, don't try to find a pte */
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21 /* Load pte table base address */
mfspr r21, MD_TWC /* ....and get the pte address */
lwz r20, 0(r21) /* Get the pte */
- ori r20, r20, _PAGE_ACCESSED
- stw r20, 0(r21)
-
+#if 1
+ /* if !swap, you can delete this */
+ rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */
+ stw r20, 0(r21) /* Update pte */
+#endif
/* The Linux PTE won't go exactly into the MMU TLB.
- * Software indicator bits 21, 22 and 28 must be clear.
+ * Software indicator bits 21 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
2: li r21, 0x00f0
- rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
+ rlwimi r20, r21, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
DO_8xx_CPU6(0x2d80, r3)
mtspr MI_RPN, r20 /* Update TLB entry */
@@ -444,12 +446,25 @@ DataStoreTLBMiss:
DO_8xx_CPU6(0x3b80, r3)
mtspr MD_TWC, r21
- mfspr r21, MD_TWC /* get the pte address again */
- ori r20, r20, _PAGE_ACCESSED
- stw r20, 0(r21)
+#if 1
+ /* if !swap, you can delete this */
+ mfspr r21, MD_TWC /* get the pte address */
+ rlwimi r20, r20, 5, _PAGE_PRESENT<<5 /* Copy PRESENT to ACCESSED */
+ stw r20, 0(r21) /* Update pte */
+#endif
+
+ /* Honour kernel RO, User NA */
+ /* 0x200 == Extended encoding, bit 22 */
+ /* r20 |= (r20 & _PAGE_USER) >> 2 */
+ rlwimi r20, r20, 32-2, 0x200
+ /* r21 = (r20 & _PAGE_RW) >> 1 */
+ rlwinm r21, r20, 32-1, 0x200
+ or r20, r21, r20
+ /* invert RW and 0x200 bits */
+ xori r20, r20, _PAGE_RW | 0x200
/* The Linux PTE won't go exactly into the MMU TLB.
- * Software indicator bits 21, 22 and 28 must be clear.
+ * Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
* of the MMU.
@@ -496,11 +511,12 @@ DataTLBError:
stw r20, 0(r0)
stw r21, 4(r0)
- /* First, make sure this was a store operation.
- */
mfspr r20, DSISR
- andis. r21, r20, 0x0200 /* If set, indicates store op */
- beq 2f
+ andis. r21, r20, 0x4800 /* !translation or protection */
+ bne- 2f
+ /* Only Change bit left now, do it here as it is faster
+ * than trapping to the C fault handler.
+ */
/* The EA of a data TLB miss is automatically stored in the MD_EPN
* register. The EA of a data TLB error is automatically stored in
@@ -550,17 +566,12 @@ DataTLBError:
mfspr r21, MD_TWC /* ....and get the pte address */
lwz r20, 0(r21) /* Get the pte */
- andi. r21, r20, _PAGE_RW /* Is it writeable? */
- beq 2f /* Bail out if not */
-
- /* Update 'changed', among others.
- */
ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
- mfspr r21, MD_TWC /* Get pte address again */
stw r20, 0(r21) /* and update pte in table */
+ xori r20, r20, _PAGE_RW /* RW bit is inverted */
/* The Linux PTE won't go exactly into the MMU TLB.
- * Software indicator bits 21, 22 and 28 must be clear.
+ * Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
* of the MMU.
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 71b2165..2ba37d3 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -298,21 +298,20 @@ extern unsigned long vmalloc_start;
#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
-/* These five software bits must be masked out when the entry is loaded
- * into the TLB.
+/* These three software bits must be masked out when the entry is loaded
+ * into the TLB, 2 SW bits free.
*/
#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
#define _PAGE_GUARDED 0x0010 /* software: guarded access */
-#define _PAGE_DIRTY 0x0020 /* software: page changed */
-#define _PAGE_RW 0x0040 /* software: user write access allowed */
-#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
+#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
/* Setting any bits in the nibble with the follow two controls will
* require a TLB exception handler change. It is assumed unused bits
- * are always zero.
+ * are always zero, encoding(bit 22).
*/
-#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
-#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
+#define _PAGE_DIRTY 0x0100 /* Changed: page changed */
+#define _PAGE_RW 0x0400 /* PP lsb(bit 21), user write access allowed */
+#define _PAGE_USER 0x0800 /* PP msb(bit 20), user access allowed */
#define _PMD_PRESENT PAGE_MASK
#define _PMD_PAGE_MASK 0x000c
--
1.7.3.4
^ permalink raw reply related
* [PATCH 02/15] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
This also fixes MachineCheck to pass DAR and DSISR as well.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 18 +++++++++++++++++-
1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index ba05a57..57858ce 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -197,7 +197,17 @@ label: \
STD_EXCEPTION(0x100, Reset, UnknownException)
/* Machine check */
- STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+ . = 0x200
+MachineCheck:
+ EXCEPTION_PROLOG
+ mfspr r20,DSISR
+ stw r20,_DSISR(r21)
+ mfspr r20,DAR
+ stw r20,_DAR(r21)
+ li r20,0x00f0
+ mtspr DAR,r20 /* Tag DAR */
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ FINISH_EXCEPTION(MachineCheckException)
/* Data access exception.
* This is "never generated" by the MPC8xx. We jump to it for other
@@ -211,6 +221,8 @@ DataAccess:
mr r5,r20
mfspr r4,DAR
stw r4,_DAR(r21)
+ li r20,0x00f0
+ mtspr DAR,r20 /* Tag DAR */
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
@@ -249,6 +261,8 @@ Alignment:
EXCEPTION_PROLOG
mfspr r4,DAR
stw r4,_DAR(r21)
+ li r20,0x00f0
+ mtspr DAR,r20 /* Tag DAR */
mfspr r5,DSISR
stw r5,_DSISR(r21)
addi r3,r1,STACK_FRAME_OVERHEAD
@@ -433,6 +447,7 @@ DataStoreTLBMiss:
* of the MMU.
*/
2: li r21, 0x00f0
+ mtspr DAR, r21 /* Tag DAR */
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr MD_RPN, r20 /* Update TLB entry */
@@ -543,6 +558,7 @@ DataTLBError:
* of the MMU.
*/
li r21, 0x00f0
+ mtspr DAR, r21 /* Tag DAR */
rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr MD_RPN, r20 /* Update TLB entry */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 07/15] 8xx: Fixup DAR from buggy dcbX instructions.
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 149 +++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 146 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 48e9dde..f4c3f41 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -511,8 +511,17 @@ DataTLBError:
stw r20, 0(r0)
stw r21, 4(r0)
- mfspr r20, DSISR
- andis. r21, r20, 0x4800 /* !translation or protection */
+ mfspr r20, DAR
+ cmpwi cr0, r20, 0x00f0
+ beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
+DARFixed:
+ /* As the DAR fixup may clear store we may have all 3 states zero.
+ * Make sure only 0x0200(store) falls down into DIRTY handling
+ */
+ mfspr r21, DSISR
+ andis. r21, r21, 0x4a00 /* !translation, protection or store */
+ srwi r21, r21, 16
+ cmpwi cr0, r21, 0x0200 /* just store ? */
bne- 2f
/* Only Change bit left now, do it here as it is faster
* than trapping to the C fault handler.
@@ -534,7 +543,7 @@ DataTLBError:
* are initialized in mapin_ram(). This will avoid the problem,
* assuming we only use the dcbi instruction on kernel addresses.
*/
- mfspr r20, DAR
+ /* DAR is in r20 already */
rlwinm r21, r20, 0, 0, 19
ori r21, r21, MD_EVALID
mfspr r20, M_CASID
@@ -618,6 +627,140 @@ DataTLBError:
STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
. = 0x2000
+/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
+ * by decoding the registers used by the dcbx instruction and adding them.
+ * DAR is set to the calculated address and r10 also holds the EA on exit.
+ */
+ /* define if you don't want to use self modifying code */
+#define NO_SELF_MODIFYING_CODE
+FixupDAR:/* Entry point for dcbx workaround. */
+ /* fetch instruction from memory. */
+ mfspr r20, SRR0
+ andis. r21, r20, 0x8000 /* Address >= 0x80000000 */
+ DO_8xx_CPU6(0x3780, r3)
+ mtspr MD_EPN, r20
+ mfspr r21, M_TWB /* Get level 1 table entry address */
+ beq- 3f /* Branch if user space */
+ lis r21, (swapper_pg_dir-PAGE_OFFSET)@h
+ ori r21, r21, (swapper_pg_dir-PAGE_OFFSET)@l
+ rlwimi r21, r20, 32-20, 0xffc /* r21 = r21&~0xffc|(r20>>20)&0xffc */
+3: lwz r21, 0(r21) /* Get the level 1 entry */
+ tophys (r21, r21)
+ DO_8xx_CPU6(0x3b80, r3)
+ mtspr MD_TWC, r21 /* Load pte table base address */
+ mfspr r21, MD_TWC /* ....and get the pte address */
+ lwz r21, 0(r21) /* Get the pte */
+ /* concat physical page address(r21) and page offset(r20) */
+ rlwimi r21, r20, 0, 20, 31
+ lwz r21,0(r21)
+/* Check if it really is a dcbx instruction. */
+/* dcbt and dcbtst does not generate DTLB Misses/Errors,
+ * no need to include them here */
+ srwi r20, r21, 26 /* check if major OP code is 31 */
+ cmpwi cr0, r20, 31
+ bne- 141f
+ rlwinm r20, r21, 0, 21, 30
+ cmpwi cr0, r20, 2028 /* Is dcbz? */
+ beq+ 142f
+ cmpwi cr0, r20, 940 /* Is dcbi? */
+ beq+ 142f
+ cmpwi cr0, r20, 108 /* Is dcbst? */
+ beq+ 144f /* Fix up store bit! */
+ cmpwi cr0, r20, 172 /* Is dcbf? */
+ beq+ 142f
+ cmpwi cr0, r20, 1964 /* Is icbi? */
+ beq+ 142f
+141: mfspr r20, DAR /* r20 must hold DAR at exit */
+ b DARFixed /* Nope, go back to normal TLB processing */
+
+144: mfspr r20, DSISR
+ rlwinm r20, r20,0,7,5 /* Clear store bit for buggy dcbst insn */
+ mtspr DSISR, r20
+142: /* continue, it was a dcbx, dcbi instruction. */
+#ifdef CONFIG_8xx_CPU6
+ lwz r3, 8(r0) /* restore r3 from memory */
+#endif
+#ifndef NO_SELF_MODIFYING_CODE
+ andis. r20,r21,0x1f /* test if reg RA is r0 */
+ li r20,modified_instr@l
+ dcbtst r0,r20 /* touch for store */
+ rlwinm r21,r21,0,0,20 /* Zero lower 10 bits */
+ oris r21,r21,640 /* Transform instr. to a "add r20,RA,RB" */
+ ori r21,r21,532
+ stw r21,0(r20) /* store add/and instruction */
+ dcbf 0,r20 /* flush new instr. to memory. */
+ icbi 0,r20 /* invalidate instr. cache line */
+ lwz r21, 4(r0) /* restore r21 from memory */
+ mfspr r20, M_TW /* restore r20 from M_TW */
+ isync /* Wait until new instr is loaded from memory */
+modified_instr:
+ .space 4 /* this is where the add instr. is stored */
+ bne+ 143f
+ subf r20,r0,r20 /* r20=r20-r0, only if reg RA is r0 */
+143: mtdar r20 /* store faulting EA in DAR */
+ b DARFixed /* Go back to normal TLB handling */
+#else
+ mfctr r20
+ mtdar r20 /* save ctr reg in DAR */
+ rlwinm r20, r21, 24, 24, 28 /* offset into jump table for reg RB */
+ addi r20, r20, 150f@l /* add start of table */
+ mtctr r20 /* load ctr with jump address */
+ xor r20, r20, r20 /* sum starts at zero */
+ bctr /* jump into table */
+150:
+ add r20, r20, r0 ;b 151f
+ add r20, r20, r1 ;b 151f
+ add r20, r20, r2 ;b 151f
+ add r20, r20, r3 ;b 151f
+ add r20, r20, r4 ;b 151f
+ add r20, r20, r5 ;b 151f
+ add r20, r20, r6 ;b 151f
+ add r20, r20, r7 ;b 151f
+ add r20, r20, r8 ;b 151f
+ add r20, r20, r9 ;b 151f
+ add r20, r20, r10 ;b 151f
+ add r20, r20, r11 ;b 151f
+ add r20, r20, r12 ;b 151f
+ add r20, r20, r13 ;b 151f
+ add r20, r20, r14 ;b 151f
+ add r20, r20, r15 ;b 151f
+ add r20, r20, r16 ;b 151f
+ add r20, r20, r17 ;b 151f
+ add r20, r20, r18 ;b 151f
+ add r20, r20, r19 ;b 151f
+ mtctr r21 ;b 154f /* r20 needs special handling */
+ mtctr r21 ;b 153f /* r21 needs special handling */
+ add r20, r20, r22 ;b 151f
+ add r20, r20, r23 ;b 151f
+ add r20, r20, r24 ;b 151f
+ add r20, r20, r25 ;b 151f
+ add r20, r20, r26 ;b 151f
+ add r20, r20, r27 ;b 151f
+ add r20, r20, r28 ;b 151f
+ add r20, r20, r29 ;b 151f
+ add r20, r20, r30 ;b 151f
+ add r20, r20, r31
+151:
+ rlwinm. r21,r21,19,24,28 /* offset into jump table for reg RA */
+ beq 152f /* if reg RA is zero, don't add it */
+ addi r21, r21, 150b@l /* add start of table */
+ mtctr r21 /* load ctr with jump address */
+ rlwinm r21,r21,0,16,10 /* make sure we don't execute this more than once */
+ bctr /* jump into table */
+152:
+ mfdar r21
+ mtctr r21 /* restore ctr reg from DAR */
+ mtdar r20 /* save fault EA to DAR */
+ b DARFixed /* Go back to normal TLB handling */
+
+ /* special handling for r20,r21 since these are modified already */
+153: lwz r21, 4(r0) /* load r21 from memory */
+ b 155f
+154: mfspr r21, M_TW /* load r20 from M_TW */
+155: add r20, r20, r21 /* add it */
+ mfctr r21 /* restore r21 */
+ b 151b
+#endif
/*
* This code finishes saving the registers to the exception frame
--
1.7.3.4
^ permalink raw reply related
* [PATCH 06/15] 8xx: Always pin kernel instruction TLB
From: Joakim Tjernlund @ 2011-06-14 13:54 UTC (permalink / raw)
To: Willy Tarreau, Scott Wood, linuxppc-dev
In-Reply-To: <1308059700-10839-1-git-send-email-Joakim.Tjernlund@transmode.se>
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
arch/ppc/kernel/head_8xx.S | 9 +++++----
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index c9770b6..48e9dde 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -785,12 +785,13 @@ start_here:
*/
initial_mmu:
tlbia /* Invalidate all TLB entries */
-#ifdef CONFIG_PIN_TLB
+
+/* Always pin the first 8 MB ITLB to prevent ITLB
+ misses while mucking around with SRR0/SRR1 in asm
+*/
lis r8, MI_RSV4I@h
ori r8, r8, 0x1c00
-#else
- li r8, 0
-#endif
+
mtspr MI_CTR, r8 /* Set instruction MMU control */
#ifdef CONFIG_PIN_TLB
--
1.7.3.4
^ permalink raw reply related
* Re: [PATCH] slub: fix kernel BUG at mm/slub.c:1950!
From: Hugh Dickins @ 2011-06-14 12:18 UTC (permalink / raw)
To: Pekka Enberg
Cc: Christoph Lameter, linuxppc-dev@lists.ozlabs.org, linux-kernel,
linux-mm
In-Reply-To: <1308027078.2874.1005.camel@pasglop>
On Tue, 14 Jun 2011, Benjamin Herrenschmidt wrote:
> On Mon, 2011-06-13 at 14:00 -0700, Hugh Dickins wrote:
> > On Mon, Jun 13, 2011 at 1:34 PM, Pekka Enberg <penberg@kernel.org> wrote:
> > > On Mon, Jun 13, 2011 at 10:29 PM, Christoph Lameter <cl@linux.com> wrote:
> > >> On Mon, 13 Jun 2011, Pekka Enberg wrote:
> > >>
> > >>> > Hmmm.. The allocpercpu in alloc_kmem_cache_cpus should take care of the
> > >>> > alignment. Uhh.. I see that a patch that removes the #ifdef CMPXCHG_LOCAL
> > >>> > was not applied? Pekka?
> > >>>
> > >>> This patch?
> > >>>
> > >>> http://git.kernel.org/?p=linux/kernel/git/penberg/slab-2.6.git;a=commitdiff;h=d4d84fef6d0366b585b7de13527a0faeca84d9ce
> > >>>
> > >>> It's queued and will be sent to Linus soon.
> > >>
> > >> Ok it will also fix Hugh's problem then.
> > >
> > > It's in Linus' tree now. Hugh, can you please confirm it fixes your machine too?
> >
> > I expect it to, thanks: I'll confirm tonight.
>
> From report to resolution before I got to read the thread, that's how I
> like them ! Thanks guys :-)
Confirmed: fixed in 3.0-rc3 - thank you!
Hugh
^ permalink raw reply
* Re: Relocatable kernel for ppc44x
From: Josh Boyer @ 2011-06-14 12:16 UTC (permalink / raw)
To: Michal Simek; +Cc: linuxppc-dev, Suzuki Poulose, John Williams
In-Reply-To: <4DF74E5D.9020908@monstr.eu>
On Tue, Jun 14, 2011 at 02:04:45PM +0200, Michal Simek wrote:
>Hi,
>
>have someone tried to support RELOCATABLE kernel on ppc44x?
Suzuki will be working on this eventually as part of getting kexec/kdump
working for 44x. I've CC'd him.
josh
^ permalink raw reply
* Relocatable kernel for ppc44x
From: Michal Simek @ 2011-06-14 12:04 UTC (permalink / raw)
To: linuxppc-dev; +Cc: John Williams
Hi,
have someone tried to support RELOCATABLE kernel on ppc44x?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
^ permalink raw reply
* Re: Mapping an executable page
From: Thomas De Schampheleire @ 2011-06-14 8:56 UTC (permalink / raw)
To: Tabi Timur-B04825; +Cc: linuxppc-dev
In-Reply-To: <BANLkTinOxqF=TcBxQOsfJSot-1XH3iErXA@mail.gmail.com>
Hi,
On Sun, May 29, 2011 at 4:53 PM, Tabi Timur-B04825 <B04825@freescale.com> w=
rote:
> On Fri, May 27, 2011 at 8:25 AM, Thomas De Schampheleire
> <patrickdepinguin+linuxppc@gmail.com> wrote:
>
>> Although I realize that what I need to achieve is unconventional, what
>> is the correct way of mapping a certain address range into memory, and
>> be able to execute from it?
>
> Have you tried looking at the actual TLB entry for this page to see if
> it's correct? =A0Also, you might need to do some kind of instruction
> cache flushing before you jump to that page.
Sorry to have delayed this so long.
I had to do quite some experimentation to get it finally working. Here
are my findings:
* to map a page as executable, the following does indeed work:
void __iomem *vaddr =3D __ioremap(map_start, map_size, (_PAGE_BASE |
_PAGE_KERNEL_RWX));
* However, if you jump to an address in that page, you'll have to make
sure that the entire code that executes is mapped (make map_size large
enough).
* When that range spanned multiple pages, I faced the issue of only
one page being actually mapped in the TLBs. My assumption is that the
call to __ioremap not necessarily updates the TLBs, but mainly some
kernel-internal tables. The actual TLB mapping presumably happens when
a data exception occurs.
Unfortunately, since I left the Linux kernel and jumped to other
(boot) code that reassigns the exception vectors, the kernel-internal
tables are not used anymore, and the exception handler cannot update
the TLBs correctly.
* Therefore, to make sure that the mapping I intended with __ioremap()
is actually reflected in the TLB tables, I added dummy reads of each
page in the TLB, prior to jumping to the boot code, as follows:
/* make sure memory is read, once every 4Kbyte is enough */
for (p =3D vaddr; p < vaddr + map_size; p +=3D 0x1000) {
unsigned long dummy =3D *(volatile unsigned long *)=
p;
(void)dummy;
}
* After these changes (make sure all code is mapped + make sure to
read all pages so that the TLBs are updated), my scenario works fine.
Best regards,
Thomas
^ permalink raw reply
* Re: [PATCH 1/1] Big endian swap for Marvell 6440 SAS driver
From: Benjamin Herrenschmidt @ 2011-06-14 7:05 UTC (permalink / raw)
To: Cédric Cano; +Cc: linuxppc-dev, linux-scsi
In-Reply-To: <4DF702F3.704@interfaceconcept.com>
On Tue, 2011-06-14 at 08:42 +0200, Cédric Cano wrote:
> Hi Ben,
>
> You're alright! I hadn't thought to use le32_to_cpu.
> Do you want I make a new patch?
Well, I'm not the maintainer of the subsystem or of the driver, so I'm
not going to be the one accepting/merging it :-)
I'm just reviewing the patch, but yes, I think you should, and you
should send it to the right people, ie, I think at least linux-scsi and
possibly the author/maintainer of the driver itself.
Cheers,
Ben.
> Cedric
>
> Le 12/06/2011 00:45, Benjamin Herrenschmidt a écrit :
> > On Fri, 2011-06-10 at 15:56 +0200, Cédric Cano wrote:
> >> Hi,
> >>
> >> Marvell SAS driver doesn't work on powerpc architecture due to big
> >> endian swap. I've tested it with the MV6440 chip.
> >> Here you can find the patch for Linux 2.6.39.1.
> >>
> >> Cedric Cano
> >>
> >> Signed-off-by: Cedric Cano<ccano@interfaceconcept.com>
> >> ---
> >> --- drivers/scsi/mvsas/mv_sas.c 2011-06-10 15:50:04.000000000 +0200
> >> +++ drivers/scsi/mvsas/mv_sas.c 2011-06-10 15:50:12.000000000 +0200
> >> @@ -1143,6 +1143,14 @@
> >> MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
> >> s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
> >>
> >> + /* swap for big endian devices because of use of these data in bytes */
> >> +#ifdef __BIG_ENDIAN
> >> + s[0] = swab32(s[0]);
> >> + s[1] = swab32(s[1]);
> >> + s[2] = swab32(s[2]);
> >> + s[3] = swab32(s[3]);
> >> +#endif /* __BIG_ENDIAN */
> > Hi Cedric !
> >
> > Thanks for this. CC'ing linux-scsi.
> >
> > Note that it would probably have been better to use le32_to_cpu, which
> > avoids the ifdef completely.
> >
> > Cheers,
> > Ben.
> >
> >> /* Workaround: take some ATAPI devices for ATA */
> >> if (((s[1]& 0x00FFFFFF) == 0x00EB1401)&& (*(u8 *)&s[3] == 0x01))
> >> s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3)& 0x10);
> >>
> >> ---
> >> _______________________________________________
> >> Linuxppc-dev mailing list
> >> Linuxppc-dev@lists.ozlabs.org
> >> https://lists.ozlabs.org/listinfo/linuxppc-dev
> >
> >
^ permalink raw reply
* Re: [PATCH 1/1] Big endian swap for Marvell 6440 SAS driver
From: Cédric Cano @ 2011-06-14 6:42 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, linux-scsi
In-Reply-To: <1307832356.2874.312.camel@pasglop>
Hi Ben,
You're alright! I hadn't thought to use le32_to_cpu.
Do you want I make a new patch?
Cedric
Le 12/06/2011 00:45, Benjamin Herrenschmidt a écrit :
> On Fri, 2011-06-10 at 15:56 +0200, Cédric Cano wrote:
>> Hi,
>>
>> Marvell SAS driver doesn't work on powerpc architecture due to big
>> endian swap. I've tested it with the MV6440 chip.
>> Here you can find the patch for Linux 2.6.39.1.
>>
>> Cedric Cano
>>
>> Signed-off-by: Cedric Cano<ccano@interfaceconcept.com>
>> ---
>> --- drivers/scsi/mvsas/mv_sas.c 2011-06-10 15:50:04.000000000 +0200
>> +++ drivers/scsi/mvsas/mv_sas.c 2011-06-10 15:50:12.000000000 +0200
>> @@ -1143,6 +1143,14 @@
>> MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
>> s[0] = MVS_CHIP_DISP->read_port_cfg_data(mvi, i);
>>
>> + /* swap for big endian devices because of use of these data in bytes */
>> +#ifdef __BIG_ENDIAN
>> + s[0] = swab32(s[0]);
>> + s[1] = swab32(s[1]);
>> + s[2] = swab32(s[2]);
>> + s[3] = swab32(s[3]);
>> +#endif /* __BIG_ENDIAN */
> Hi Cedric !
>
> Thanks for this. CC'ing linux-scsi.
>
> Note that it would probably have been better to use le32_to_cpu, which
> avoids the ifdef completely.
>
> Cheers,
> Ben.
>
>> /* Workaround: take some ATAPI devices for ATA */
>> if (((s[1]& 0x00FFFFFF) == 0x00EB1401)&& (*(u8 *)&s[3] == 0x01))
>> s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3)& 0x10);
>>
>> ---
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@lists.ozlabs.org
>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
>
^ permalink raw reply
* [PATCH] tqm8540: add description for onboard flash
From: Dmitry Eremin-Solenikov @ 2011-06-14 5:22 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Paul Mackerras
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
arch/powerpc/boot/dts/tqm8540.dts | 40 +++++++++++++++++++++++++++++++++++++
1 files changed, 40 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index b5c0940..987c862 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -278,6 +278,46 @@
};
};
+ localbus@e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus",
+ "simple-bus";
+ reg = <0xe0005000 0x1000>;
+
+ ranges = <0x0 0x0 0xfe000000 0x02000000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x02000000>;
+ bank-width = <4>;
+ device-width = <2>;
+ partition@0 {
+ label = "kernel";
+ reg = <0x00000000 0x00180000>;
+ };
+ partition@180000 {
+ label = "root";
+ reg = <0x00180000 0x01dc0000>;
+ };
+ partition@1f40000 {
+ label = "env1";
+ reg = <0x01f40000 0x00040000>;
+ };
+ partition@1f80000 {
+ label = "env2";
+ reg = <0x01f80000 0x00040000>;
+ };
+ partition@1fc0000 {
+ label = "u-boot";
+ reg = <0x01fc0000 0x00040000>;
+ read-only;
+ };
+ };
+ };
+
pci0: pci@e0008000 {
#interrupt-cells = <1>;
#size-cells = <2>;
--
1.7.5.3
^ permalink raw reply related
* Re: [PATCH] slub: fix kernel BUG at mm/slub.c:1950!
From: Benjamin Herrenschmidt @ 2011-06-14 4:51 UTC (permalink / raw)
To: Hugh Dickins
Cc: Pekka Enberg, linux-mm, Christoph Lameter,
linuxppc-dev@lists.ozlabs.org, linux-kernel
In-Reply-To: <BANLkTik-KGtuoVFKvy_rk7voBRAxSsR9FRg0fhb0k3NCSg-fWQ@mail.gmail.com>
On Mon, 2011-06-13 at 14:00 -0700, Hugh Dickins wrote:
> On Mon, Jun 13, 2011 at 1:34 PM, Pekka Enberg <penberg@kernel.org> wrote:
> > On Mon, Jun 13, 2011 at 10:29 PM, Christoph Lameter <cl@linux.com> wrote:
> >> On Mon, 13 Jun 2011, Pekka Enberg wrote:
> >>
> >>> > Hmmm.. The allocpercpu in alloc_kmem_cache_cpus should take care of the
> >>> > alignment. Uhh.. I see that a patch that removes the #ifdef CMPXCHG_LOCAL
> >>> > was not applied? Pekka?
> >>>
> >>> This patch?
> >>>
> >>> http://git.kernel.org/?p=linux/kernel/git/penberg/slab-2.6.git;a=commitdiff;h=d4d84fef6d0366b585b7de13527a0faeca84d9ce
> >>>
> >>> It's queued and will be sent to Linus soon.
> >>
> >> Ok it will also fix Hugh's problem then.
> >
> > It's in Linus' tree now. Hugh, can you please confirm it fixes your machine too?
>
> I expect it to, thanks: I'll confirm tonight.
>From report to resolution before I got to read the thread, that's how I
like them ! Thanks guys :-)
Cheers,
Ben.
^ permalink raw reply
* [PATCH 2/2] powerpc/mm: Fix memory_block_size_bytes() for non-pseries
From: Benjamin Herrenschmidt @ 2011-06-14 0:57 UTC (permalink / raw)
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org, Ingo Molnar, linuxppc-dev, Thomas Gleixner
Just compiling pseries in the kernel causes it to override
memory_block_size_bytes() regardless of what is the runtime
platform.
This cleans up the implementation of that function, fixing
a bug or two while at it, so that it's harmless (and potentially
useful) for other platforms. Without this, bugs in that code
would trigger a WARN_ON() in drivers/base/memory.c when
booting some different platforms.
If/when we have another platform supporting memory hotplug we
might want to either move that out to a generic place or
make it a ppc_md. callback.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 33867ec..9d6a8ef 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -12,6 +12,8 @@
#include <linux/of.h>
#include <linux/memblock.h>
#include <linux/vmalloc.h>
+#include <linux/memory.h>
+
#include <asm/firmware.h>
#include <asm/machdep.h>
#include <asm/pSeries_reconfig.h>
@@ -20,24 +22,25 @@
static unsigned long get_memblock_size(void)
{
struct device_node *np;
- unsigned int memblock_size = 0;
+ unsigned int memblock_size = MIN_MEMORY_BLOCK_SIZE;
+ struct resource r;
np = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
if (np) {
- const unsigned long *size;
+ const __be64 *size;
size = of_get_property(np, "ibm,lmb-size", NULL);
- memblock_size = size ? *size : 0;
-
+ if (size)
+ memblock_size = be64_to_cpup(size);
of_node_put(np);
- } else {
+ } else if (machine_is(pseries)) {
+ /* This fallback really only applies to pseries */
unsigned int memzero_size = 0;
- const unsigned int *regs;
np = of_find_node_by_path("/memory@0");
if (np) {
- regs = of_get_property(np, "reg", NULL);
- memzero_size = regs ? regs[3] : 0;
+ if (!of_address_to_resource(np, 0, &r))
+ memzero_size = resource_size(&r);
of_node_put(np);
}
@@ -50,16 +53,21 @@ static unsigned long get_memblock_size(void)
sprintf(buf, "/memory@%x", memzero_size);
np = of_find_node_by_path(buf);
if (np) {
- regs = of_get_property(np, "reg", NULL);
- memblock_size = regs ? regs[3] : 0;
+ if (!of_address_to_resource(np, 0, &r))
+ memblock_size = resource_size(&r);
of_node_put(np);
}
}
}
-
return memblock_size;
}
+/* WARNING: This is going to override the generic definition whenever
+ * pseries is built-in regardless of what platform is active at boot
+ * time. This is fine for now as this is the only "option" and it
+ * should work everywhere. If not, we'll have to turn this into a
+ * ppc_md. callback
+ */
unsigned long memory_block_size_bytes(void)
{
return get_memblock_size();
^ permalink raw reply related
* [PATCH 1/2] mm: Move definition of MIN_MEMORY_BLOCK_SIZE to a header
From: Benjamin Herrenschmidt @ 2011-06-14 0:57 UTC (permalink / raw)
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org, Ingo Molnar, linuxppc-dev, Thomas Gleixner
The macro MIN_MEMORY_BLOCK_SIZE is currently defined twice in two .c
files, and I need it in a third one to fix a powerpc bug, so let's
first move it into a header
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Ingo, Thomas: Who needs to ack the x86 bit ? I'd like to send that
to Linus asap with the powerpc fix.
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index d865c4a..bbaaa00 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -28,6 +28,7 @@
#include <linux/poison.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
+#include <linux/memory.h>
#include <linux/memory_hotplug.h>
#include <linux/nmi.h>
#include <linux/gfp.h>
@@ -895,8 +896,6 @@ const char *arch_vma_name(struct vm_area_struct *vma)
}
#ifdef CONFIG_X86_UV
-#define MIN_MEMORY_BLOCK_SIZE (1 << SECTION_SIZE_BITS)
-
unsigned long memory_block_size_bytes(void)
{
if (is_uv_system()) {
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 9f9b235..45d7c8f 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -30,7 +30,6 @@
static DEFINE_MUTEX(mem_sysfs_mutex);
#define MEMORY_CLASS_NAME "memory"
-#define MIN_MEMORY_BLOCK_SIZE (1 << SECTION_SIZE_BITS)
static int sections_per_block;
diff --git a/include/linux/memory.h b/include/linux/memory.h
index e1e3b2b..935699b 100644
--- a/include/linux/memory.h
+++ b/include/linux/memory.h
@@ -20,6 +20,8 @@
#include <linux/compiler.h>
#include <linux/mutex.h>
+#define MIN_MEMORY_BLOCK_SIZE (1 << SECTION_SIZE_BITS)
+
struct memory_block {
unsigned long start_section_nr;
unsigned long end_section_nr;
^ permalink raw reply related
* Re: [PATCH] slub: fix kernel BUG at mm/slub.c:1950!
From: Hugh Dickins @ 2011-06-13 21:00 UTC (permalink / raw)
To: Pekka Enberg
Cc: linux-mm, Christoph Lameter, linuxppc-dev@lists.ozlabs.org,
linux-kernel
In-Reply-To: <BANLkTi=RYq0Dd210VC+NeTXWWuFbz7cxeg@mail.gmail.com>
On Mon, Jun 13, 2011 at 1:34 PM, Pekka Enberg <penberg@kernel.org> wrote:
> On Mon, Jun 13, 2011 at 10:29 PM, Christoph Lameter <cl@linux.com> wrote:
>> On Mon, 13 Jun 2011, Pekka Enberg wrote:
>>
>>> > Hmmm.. The allocpercpu in alloc_kmem_cache_cpus should take care of the
>>> > alignment. Uhh.. I see that a patch that removes the #ifdef CMPXCHG_LOCAL
>>> > was not applied? Pekka?
>>>
>>> This patch?
>>>
>>> http://git.kernel.org/?p=linux/kernel/git/penberg/slab-2.6.git;a=commitdiff;h=d4d84fef6d0366b585b7de13527a0faeca84d9ce
>>>
>>> It's queued and will be sent to Linus soon.
>>
>> Ok it will also fix Hugh's problem then.
>
> It's in Linus' tree now. Hugh, can you please confirm it fixes your machine too?
I expect it to, thanks: I'll confirm tonight.
Hugh
^ permalink raw reply
* Re: [PATCH] slub: fix kernel BUG at mm/slub.c:1950!
From: Pekka Enberg @ 2011-06-13 20:34 UTC (permalink / raw)
To: Christoph Lameter; +Cc: linux-mm, linuxppc-dev, Hugh Dickins, linux-kernel
In-Reply-To: <alpine.DEB.2.00.1106131428560.5601@router.home>
On Mon, Jun 13, 2011 at 10:29 PM, Christoph Lameter <cl@linux.com> wrote:
> On Mon, 13 Jun 2011, Pekka Enberg wrote:
>
>> > Hmmm.. The allocpercpu in alloc_kmem_cache_cpus should take care of the
>> > alignment. Uhh.. I see that a patch that removes the #ifdef CMPXCHG_LOCAL
>> > was not applied? Pekka?
>>
>> This patch?
>>
>> http://git.kernel.org/?p=linux/kernel/git/penberg/slab-2.6.git;a=commitdiff;h=d4d84fef6d0366b585b7de13527a0faeca84d9ce
>>
>> It's queued and will be sent to Linus soon.
>
> Ok it will also fix Hugh's problem then.
It's in Linus' tree now. Hugh, can you please confirm it fixes your machine too?
^ permalink raw reply
* Re: [PATCH] slub: fix kernel BUG at mm/slub.c:1950!
From: Christoph Lameter @ 2011-06-13 19:29 UTC (permalink / raw)
To: Pekka Enberg; +Cc: linux-mm, linuxppc-dev, Hugh Dickins, linux-kernel
In-Reply-To: <1307990048.11288.3.camel@jaguar>
On Mon, 13 Jun 2011, Pekka Enberg wrote:
> > Hmmm.. The allocpercpu in alloc_kmem_cache_cpus should take care of the
> > alignment. Uhh.. I see that a patch that removes the #ifdef CMPXCHG_LOCAL
> > was not applied? Pekka?
>
> This patch?
>
> http://git.kernel.org/?p=linux/kernel/git/penberg/slab-2.6.git;a=commitdiff;h=d4d84fef6d0366b585b7de13527a0faeca84d9ce
>
> It's queued and will be sent to Linus soon.
Ok it will also fix Hugh's problem then.
^ permalink raw reply
* Re: [PATCH] usb:gadget: use min_t() macro instead of min()
From: Felipe Balbi @ 2011-06-13 19:09 UTC (permalink / raw)
To: Alan Stern
Cc: 'open list:FREESCALE USB PER...', Tanya Brokhman, greg,
linux-usb, 'open list', balbi, linux-arm-msm,
'open list:OMAP USB SUPPORT', ablay
In-Reply-To: <Pine.LNX.4.44L0.1106131503040.1983-100000@iolanthe.rowland.org>
[-- Attachment #1: Type: text/plain, Size: 1120 bytes --]
Hi,
On Mon, Jun 13, 2011 at 03:03:44PM -0400, Alan Stern wrote:
> > > The change I suggested involved replacing two typecasts with a single
> > > min_t. All (or almost all) the places this patch touches currently
> > > contain only one typecast, so the motivation for changing them is a lot
> > > weaker.
> > >
> > You're right. So what's the final call on this one? Do you think it can be
> > merged or you prefer not change anything? I personally think the code looks
> > nicer using min_t instead of min with casting but that's just my opinion and
> > of course there are arguments against this patch.
>
> I don't care either way. It's up to you and Felipe.
I guess it's better to have a more critical look at the arguments first.
Looking into dummy_hcd for instance, it doesn't appear like we need to
be int, it could be unsigned int. I just skimmed through the code, but
it looks like we will always hold >= 0 values on that variable.
So go through that exercise first, then we look at the others. Blindly
changing to min_t() might not give us any improvements at all ;-)
--
balbi
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^ permalink raw reply
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