* Re: [RFC 4/4] [powerpc] Add flexcan device support for p1010rdb.
From: Robin Holt @ 2011-08-09 12:04 UTC (permalink / raw)
To: Wolfgang Grandegger
Cc: netdev, U Bhaskar-B22300, socketcan-core, Robin Holt, PPC list
In-Reply-To: <4E40DDA5.1050004@grandegger.com>
On Tue, Aug 09, 2011 at 09:11:33AM +0200, Wolfgang Grandegger wrote:
> On 08/09/2011 08:33 AM, Robin Holt wrote:
> > Argh. I sent an earlier (non-working) version of this patch. Here is
> > the correct one.
>
> Please always resend the complete series of patches with an incremented
> version number. Furthermore, this is not an RFC any more. A prefix
> similar to [PATCH nfsl_get_sys_freq() et-next-2.6 v2] would be perfect.
>
> > I added a clock source for the p1010rdb so the flexcan driver
> > could find its clock frequency.
> >
> > Signed-off-by: Robin Holt <holt@sgi.com>
> > To: Marc Kleine-Budde <mkl@pengutronix.de>,
> > To: Wolfgang Grandegger <wg@grandegger.com>,
> > To: U Bhaskar-B22300 <B22300@freescale.com>
> > Cc: socketcan-core@lists.berlios.de,
> > Cc: netdev@vger.kernel.org,
> > Cc: PPC list <linuxppc-dev@lists.ozlabs.org>
> > ---
> > arch/powerpc/platforms/85xx/Kconfig | 6 +++
> > arch/powerpc/platforms/85xx/Makefile | 1 +
> > arch/powerpc/platforms/85xx/clock.c | 59 ++++++++++++++++++++++++++++++++
> > arch/powerpc/platforms/85xx/p1010rdb.c | 10 +++++
> > 4 files changed, 76 insertions(+), 0 deletions(-)
> > create mode 100644 arch/powerpc/platforms/85xx/clock.c
> >
> > diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
> > index 498534c..ed4cf92 100644
> > --- a/arch/powerpc/platforms/85xx/Kconfig
> > +++ b/arch/powerpc/platforms/85xx/Kconfig
> > @@ -26,6 +26,10 @@ config MPC8560_ADS
> > help
> > This option enables support for the MPC 8560 ADS board
> >
> > +config 85xx_HAVE_CAN_FLEXCAN
> > + bool
> > + select HAVE_CAN_FLEXCAN if NET && CAN
> > +
>
> Why do you need that? More below...
Happily removed.
> > config MPC85xx_CDS
> > bool "Freescale MPC85xx CDS"
> > select DEFAULT_UIMAGE
> > @@ -70,6 +74,8 @@ config MPC85xx_RDB
> > config P1010_RDB
> > bool "Freescale P1010RDB"
> > select DEFAULT_UIMAGE
> > + select 85xx_HAVE_CAN_FLEXCAN
> > + select PPC_CLOCK if CAN_FLEXCAN
>
> select HAVE_CAN_FLEXCAN
> select PPC_CLOCK
>
> Should just be fine, or have I missed something.
If I don't have the if NET && CAN, then 'make savedefconfig' will
complain. Otherwise, removed 85xx_HAVE_CAN_FLEXCAN.
> > help
> > This option enables support for the MPC85xx RDB (P1010 RDB) board
> >
> > diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
> > index a971b32..64ad7a4 100644
> > --- a/arch/powerpc/platforms/85xx/Makefile
> > +++ b/arch/powerpc/platforms/85xx/Makefile
> > @@ -11,6 +11,7 @@ obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
> > obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
> > obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
> > obj-$(CONFIG_P1010_RDB) += p1010rdb.o
> > +obj-$(CONFIG_PPC_CLOCK) += clock.o
>
> I would put that to the beginning or before the board settings.
Done.
> > obj-$(CONFIG_P1022_DS) += p1022_ds.o
> > obj-$(CONFIG_P1023_RDS) += p1023_rds.o
> > obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
> > diff --git a/arch/powerpc/platforms/85xx/clock.c b/arch/powerpc/platforms/85xx/clock.c
> > new file mode 100644
> > index 0000000..a25cbf3
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/85xx/clock.c
> > @@ -0,0 +1,59 @@
> > +
> > +#include <linux/device.h>
> > +#include <linux/err.h>
> > +
> > +#include <asm/clk_interface.h>
> > +
> > +#include <sysdev/fsl_soc.h>
> > +
> > +/*
> > + * p1010rdb needs to provide a clock source for the flexcan driver.
> > + */
> > +struct clk {
> > + unsigned long rate;
> > +} p1010_rdb_system_clock;
> > +
> > +static struct clk *p1010_rdb_clk_get(struct device *dev, const char *id)
> > +{
> > + const char *dev_init_name;
> > +
> > + if (!dev)
> > + return ERR_PTR(-ENOENT);
> > +
> > + /*
> > + * The can devices are named ffe1c000.can0 and ffe1d000.can1 on
> > + * the p1010rdb. Check for the "can" portion of that name before
> > + * returning a clock source.
> > + */
> > + dev_init_name = dev_name(dev);
> > + if (strlen(dev_init_name) != 13)
> > + return ERR_PTR(-ENOENT);
> > + dev_init_name += 9;
> > + if (strncmp(dev_init_name, "can", 3))
> > + return ERR_PTR(-ENOENT);
>
> What's that good for? Also it's wrong to rely on the special name of the
> node. I think it can be removed.
Removed.
>
> > + return &p1010_rdb_system_clock;
>
> Just returning fsl_get_sys_freq() here would already be fine. I'm also
> missing the factor of two here:
>
> return fsl_get_sys_freq() / 2; ????
If we were going that route, I would return NULL here and do that
return on the clk_get_rate() call, correct? I just tested with that
and it worked.
> > +}
> > +
> > +static void p1010_rdb_clk_put(struct clk *clk)
> > +{
> > + return;
> > +}
> > +
> > +static unsigned long p1010_rdb_clk_get_rate(struct clk *clk)
> > +{
> > + return clk->rate;
> > +}
> > +
> > +static struct clk_interface p1010_rdb_clk_functions = {
> > + .clk_get = p1010_rdb_clk_get,
> > + .clk_get_rate = p1010_rdb_clk_get_rate,
> > + .clk_put = p1010_rdb_clk_put,
> > +};
> > +
> > +void __init p1010_rdb_clk_init(void)
> > +{
> > + p1010_rdb_system_clock.rate = fsl_get_sys_freq();
>
> > + clk_functions = p1010_rdb_clk_functions;
> > +}
>
> The name is too specific. The idea is that the interface could be used
> for other 85xx processors as well, not only the p1010. The prefix
> "mpc85xx_" instead of "p1010_rdb" seems more appropriate to me.
Done.
>
> > diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
> > index d7387fa..d0afbf9 100644
> > --- a/arch/powerpc/platforms/85xx/p1010rdb.c
> > +++ b/arch/powerpc/platforms/85xx/p1010rdb.c
> > @@ -81,6 +81,15 @@ static void __init p1010_rdb_setup_arch(void)
> > printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
> > }
> >
> > +extern void p1010_rdb_clk_init(void);
> > +
> > +static void __init p1010_rdb_init(void)
> > +{
> > +#ifdef CONFIG_PPC_CLOCK
> > + p1010_rdb_clk_init();
> > +#endif
> > +}
>
> The #ifdef's are not needed if CONFIG_PPC_CLOCK is selected in the Kconfig.
Done.
>
> > static struct of_device_id __initdata p1010rdb_ids[] = {
> > { .type = "soc", },
> > { .compatible = "soc", },
> > @@ -111,6 +120,7 @@ define_machine(p1010_rdb) {
> > .name = "P1010 RDB",
> > .probe = p1010_rdb_probe,
> > .setup_arch = p1010_rdb_setup_arch,
> > + .init = p1010_rdb_init,
> > .init_IRQ = p1010_rdb_pic_init,
> > #ifdef CONFIG_PCI
> > .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
Thank you very much for your patience with me,
Robin
^ permalink raw reply
* Re: [RFC 4/4] [powerpc] Add flexcan device support for p1010rdb.
From: Marc Kleine-Budde @ 2011-08-09 12:04 UTC (permalink / raw)
To: Robin Holt; +Cc: socketcan-core, netdev, U Bhaskar-B22300, PPC list
In-Reply-To: <20110809114043.GN4926@sgi.com>
[-- Attachment #1: Type: text/plain, Size: 1400 bytes --]
On 08/09/2011 01:40 PM, Robin Holt wrote:
> On Tue, Aug 09, 2011 at 09:11:33AM +0200, Wolfgang Grandegger wrote:
>>> + return &p1010_rdb_system_clock;
>>
>> Just returning fsl_get_sys_freq() here would already be fine. I'm also
>> missing the factor of two here:
>>
>> return fsl_get_sys_freq() / 2; ????
>
> I am working on the other comments right now as well, but this one
> brought up a good question. The old algorithm in the original freescale
> patches I started with actually did, essentially:
>
> ...clock.freq = DIV_ROUND_CLOSEST(fsl_get_sys_freq() / 2, 1000) * 1000
>
> The end result was before:
> ...clock.freq=0x0bebc200
That's exactly 200 MHz
> After:
> ...clock.freq=0x0bebc1fe
this is 199 999 998 Hz
> Is that rounding relavent?
_If_ 200 MHz is correct, this would be an error of 0.000001%. But the
fsl code rounds to closest KHz. Rounding introduces errors in most of
the cases. IMHO it's better not to round here.
For example the usual at91can is clocked with 99.532800 MHz, this is a
least the value the arm clock framework reports.
Cheers, Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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^ permalink raw reply
* Re: [PATCH] powerpc: Make KVM_GUEST default to n
From: Alexander Graf @ 2011-08-09 11:58 UTC (permalink / raw)
To: Anton Blanchard; +Cc: paulus, linuxppc-dev
In-Reply-To: <20110805132358.086648e5@kryten>
On 08/05/2011 05:23 AM, Anton Blanchard wrote:
> KVM_GUEST adds a 1 MB array to the kernel (kvm_tmp) which grew
> my kernel enough to cause it to fail to boot.
>
> Dynamically allocating or reducing the size of this array is a
> good idea, but in the meantime I think it makes sense to make
> KVM_GUEST default to n in order to minimise surprises.
>
> Signed-off-by: Anton Blanchard<anton@samba.org>
Hrm - the idea was that the code is so little intrusive that it could
simply always be enabled. But yeah, maybe this should be default n.
Ben, could you please pull this into your ppc tree for now? I don't
think I'll manage to clean up my tree and send out a pull request before
KVM Forum.
Alex
> ---
>
> Index: linux-powerpc/arch/powerpc/platforms/Kconfig
> ===================================================================
> --- linux-powerpc.orig/arch/powerpc/platforms/Kconfig 2011-08-01 17:33:46.120121554 +1000
> +++ linux-powerpc/arch/powerpc/platforms/Kconfig 2011-08-01 17:35:06.921772044 +1000
> @@ -24,7 +24,7 @@ source "arch/powerpc/platforms/wsp/Kconf
>
> config KVM_GUEST
> bool "KVM Guest support"
> - default y
> + default n
> ---help---
> This option enables various optimizations for running under the KVM
> hypervisor. Overhead for the kernel when not running inside KVM should
^ permalink raw reply
* Re: [RFC 4/4] [powerpc] Add flexcan device support for p1010rdb.
From: Robin Holt @ 2011-08-09 11:40 UTC (permalink / raw)
To: Wolfgang Grandegger
Cc: netdev, U Bhaskar-B22300, socketcan-core, Robin Holt, PPC list
In-Reply-To: <4E40DDA5.1050004@grandegger.com>
On Tue, Aug 09, 2011 at 09:11:33AM +0200, Wolfgang Grandegger wrote:
> > + return &p1010_rdb_system_clock;
>
> Just returning fsl_get_sys_freq() here would already be fine. I'm also
> missing the factor of two here:
>
> return fsl_get_sys_freq() / 2; ????
I am working on the other comments right now as well, but this one
brought up a good question. The old algorithm in the original freescale
patches I started with actually did, essentially:
...clock.freq = DIV_ROUND_CLOSEST(fsl_get_sys_freq() / 2, 1000) * 1000
The end result was before:
...clock.freq=0x0bebc200
After:
...clock.freq=0x0bebc1fe
Is that rounding relavent?
Thanks,
Robin
^ permalink raw reply
* GPIO IRQ dts bindings for MPC85xx and QorIQ
From: Felix Radensky @ 2011-08-09 8:14 UTC (permalink / raw)
To: linuxppc-dev@ozlabs.org, jacmet@sunsite.dk, grant.likely
Hi,
DTS bindings document for mpc8xxx GPIOs implies that to use GPIO as IRQ
one should specify GPIO controller node and GPIO number in device tree
node,
like this:
funkyfpga@0 {
compatible = "funky-fpga";
...
interrupts = <9 2>;
interrupt-parent = <&gpio2>;
};
I suppose the intention here is to do the following in driver code:
int irq;
struct device node *np;
np = of_find_compatible_node((NULL, NULL, "funky-fpga");
irq = irq_of_parse_and_map(np, 0);
request_irq(irq, ...);
However this doesn't work as expected. The resulting virq
is connected to real interrupt controller, mpic, and not to
GPIO controller. As a result, interrupt handler is never invoked.
This is what /proc/interrupts shows:
20: 0 OpenPIC Edge funky-fpga
On the other hand, when using
#define FPGA_IRQ_GPIO 169
request_gpio(FPGA_IRQ_GPIO);
gpio_direction_input(FPGA_IRQ_GPIO);
irq = gpio_to_irq(FPGA_IRQ_GPIO);
request_irq(irq, ...);
the connection to GPIO controller is created properly,
/proc/interrupts shows
20: 0 mpc8xxx_gpio Edge funky-fpga
The drawback of this approach is that GPIO IRQ cannot
be naturally specified in device tree by GPIO controller number
and GPIO pin number.
So what is the correct way to refer to 85XX GPIO IRQs in driver
code ?
Thanks.
Felix.
^ permalink raw reply
* Re: [RFC 4/4] [powerpc] Add flexcan device support for p1010rdb.
From: Wolfgang Grandegger @ 2011-08-09 7:11 UTC (permalink / raw)
To: Robin Holt; +Cc: socketcan-core, U Bhaskar-B22300, PPC list, netdev
In-Reply-To: <20110809063319.GK4926@sgi.com>
On 08/09/2011 08:33 AM, Robin Holt wrote:
> Argh. I sent an earlier (non-working) version of this patch. Here is
> the correct one.
Please always resend the complete series of patches with an incremented
version number. Furthermore, this is not an RFC any more. A prefix
similar to [PATCH nfsl_get_sys_freq() et-next-2.6 v2] would be perfect.
> I added a clock source for the p1010rdb so the flexcan driver
> could find its clock frequency.
>
> Signed-off-by: Robin Holt <holt@sgi.com>
> To: Marc Kleine-Budde <mkl@pengutronix.de>,
> To: Wolfgang Grandegger <wg@grandegger.com>,
> To: U Bhaskar-B22300 <B22300@freescale.com>
> Cc: socketcan-core@lists.berlios.de,
> Cc: netdev@vger.kernel.org,
> Cc: PPC list <linuxppc-dev@lists.ozlabs.org>
> ---
> arch/powerpc/platforms/85xx/Kconfig | 6 +++
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/clock.c | 59 ++++++++++++++++++++++++++++++++
> arch/powerpc/platforms/85xx/p1010rdb.c | 10 +++++
> 4 files changed, 76 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/platforms/85xx/clock.c
>
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
> index 498534c..ed4cf92 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -26,6 +26,10 @@ config MPC8560_ADS
> help
> This option enables support for the MPC 8560 ADS board
>
> +config 85xx_HAVE_CAN_FLEXCAN
> + bool
> + select HAVE_CAN_FLEXCAN if NET && CAN
> +
Why do you need that? More below...
> config MPC85xx_CDS
> bool "Freescale MPC85xx CDS"
> select DEFAULT_UIMAGE
> @@ -70,6 +74,8 @@ config MPC85xx_RDB
> config P1010_RDB
> bool "Freescale P1010RDB"
> select DEFAULT_UIMAGE
> + select 85xx_HAVE_CAN_FLEXCAN
> + select PPC_CLOCK if CAN_FLEXCAN
select HAVE_CAN_FLEXCAN
select PPC_CLOCK
Should just be fine, or have I missed something.
> help
> This option enables support for the MPC85xx RDB (P1010 RDB) board
>
> diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
> index a971b32..64ad7a4 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
> obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
> obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
> obj-$(CONFIG_P1010_RDB) += p1010rdb.o
> +obj-$(CONFIG_PPC_CLOCK) += clock.o
I would put that to the beginning or before the board settings.
> obj-$(CONFIG_P1022_DS) += p1022_ds.o
> obj-$(CONFIG_P1023_RDS) += p1023_rds.o
> obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
> diff --git a/arch/powerpc/platforms/85xx/clock.c b/arch/powerpc/platforms/85xx/clock.c
> new file mode 100644
> index 0000000..a25cbf3
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/clock.c
> @@ -0,0 +1,59 @@
> +
> +#include <linux/device.h>
> +#include <linux/err.h>
> +
> +#include <asm/clk_interface.h>
> +
> +#include <sysdev/fsl_soc.h>
> +
> +/*
> + * p1010rdb needs to provide a clock source for the flexcan driver.
> + */
> +struct clk {
> + unsigned long rate;
> +} p1010_rdb_system_clock;
> +
> +static struct clk *p1010_rdb_clk_get(struct device *dev, const char *id)
> +{
> + const char *dev_init_name;
> +
> + if (!dev)
> + return ERR_PTR(-ENOENT);
> +
> + /*
> + * The can devices are named ffe1c000.can0 and ffe1d000.can1 on
> + * the p1010rdb. Check for the "can" portion of that name before
> + * returning a clock source.
> + */
> + dev_init_name = dev_name(dev);
> + if (strlen(dev_init_name) != 13)
> + return ERR_PTR(-ENOENT);
> + dev_init_name += 9;
> + if (strncmp(dev_init_name, "can", 3))
> + return ERR_PTR(-ENOENT);
What's that good for? Also it's wrong to rely on the special name of the
node. I think it can be removed.
> + return &p1010_rdb_system_clock;
Just returning fsl_get_sys_freq() here would already be fine. I'm also
missing the factor of two here:
return fsl_get_sys_freq() / 2; ????
> +}
> +
> +static void p1010_rdb_clk_put(struct clk *clk)
> +{
> + return;
> +}
> +
> +static unsigned long p1010_rdb_clk_get_rate(struct clk *clk)
> +{
> + return clk->rate;
> +}
> +
> +static struct clk_interface p1010_rdb_clk_functions = {
> + .clk_get = p1010_rdb_clk_get,
> + .clk_get_rate = p1010_rdb_clk_get_rate,
> + .clk_put = p1010_rdb_clk_put,
> +};
> +
> +void __init p1010_rdb_clk_init(void)
> +{
> + p1010_rdb_system_clock.rate = fsl_get_sys_freq();
> + clk_functions = p1010_rdb_clk_functions;
> +}
The name is too specific. The idea is that the interface could be used
for other 85xx processors as well, not only the p1010. The prefix
"mpc85xx_" instead of "p1010_rdb" seems more appropriate to me.
> diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
> index d7387fa..d0afbf9 100644
> --- a/arch/powerpc/platforms/85xx/p1010rdb.c
> +++ b/arch/powerpc/platforms/85xx/p1010rdb.c
> @@ -81,6 +81,15 @@ static void __init p1010_rdb_setup_arch(void)
> printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
> }
>
> +extern void p1010_rdb_clk_init(void);
> +
> +static void __init p1010_rdb_init(void)
> +{
> +#ifdef CONFIG_PPC_CLOCK
> + p1010_rdb_clk_init();
> +#endif
> +}
The #ifdef's are not needed if CONFIG_PPC_CLOCK is selected in the Kconfig.
> static struct of_device_id __initdata p1010rdb_ids[] = {
> { .type = "soc", },
> { .compatible = "soc", },
> @@ -111,6 +120,7 @@ define_machine(p1010_rdb) {
> .name = "P1010 RDB",
> .probe = p1010_rdb_probe,
> .setup_arch = p1010_rdb_setup_arch,
> + .init = p1010_rdb_init,
> .init_IRQ = p1010_rdb_pic_init,
> #ifdef CONFIG_PCI
> .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
We also need cleanup patches for the Freescale stuff.
Thanks,
Wolfgang.
^ permalink raw reply
* Re: [RFC 4/4] [powerpc] Add flexcan device support for p1010rdb.
From: Robin Holt @ 2011-08-09 6:33 UTC (permalink / raw)
To: Robin Holt, Marc Kleine-Budde, Wolfgang Grandegger,
U Bhaskar-B22300
Cc: socketcan-core, netdev, PPC list
In-Reply-To: <1312869313-22434-5-git-send-email-holt@sgi.com>
Argh. I sent an earlier (non-working) version of this patch. Here is
the correct one.
I added a clock source for the p1010rdb so the flexcan driver
could find its clock frequency.
Signed-off-by: Robin Holt <holt@sgi.com>
To: Marc Kleine-Budde <mkl@pengutronix.de>,
To: Wolfgang Grandegger <wg@grandegger.com>,
To: U Bhaskar-B22300 <B22300@freescale.com>
Cc: socketcan-core@lists.berlios.de,
Cc: netdev@vger.kernel.org,
Cc: PPC list <linuxppc-dev@lists.ozlabs.org>
---
arch/powerpc/platforms/85xx/Kconfig | 6 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/clock.c | 59 ++++++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/p1010rdb.c | 10 +++++
4 files changed, 76 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/85xx/clock.c
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 498534c..ed4cf92 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -26,6 +26,10 @@ config MPC8560_ADS
help
This option enables support for the MPC 8560 ADS board
+config 85xx_HAVE_CAN_FLEXCAN
+ bool
+ select HAVE_CAN_FLEXCAN if NET && CAN
+
config MPC85xx_CDS
bool "Freescale MPC85xx CDS"
select DEFAULT_UIMAGE
@@ -70,6 +74,8 @@ config MPC85xx_RDB
config P1010_RDB
bool "Freescale P1010RDB"
select DEFAULT_UIMAGE
+ select 85xx_HAVE_CAN_FLEXCAN
+ select PPC_CLOCK if CAN_FLEXCAN
help
This option enables support for the MPC85xx RDB (P1010 RDB) board
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index a971b32..64ad7a4 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
obj-$(CONFIG_P1010_RDB) += p1010rdb.o
+obj-$(CONFIG_PPC_CLOCK) += clock.o
obj-$(CONFIG_P1022_DS) += p1022_ds.o
obj-$(CONFIG_P1023_RDS) += p1023_rds.o
obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
diff --git a/arch/powerpc/platforms/85xx/clock.c b/arch/powerpc/platforms/85xx/clock.c
new file mode 100644
index 0000000..a25cbf3
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/clock.c
@@ -0,0 +1,59 @@
+
+#include <linux/device.h>
+#include <linux/err.h>
+
+#include <asm/clk_interface.h>
+
+#include <sysdev/fsl_soc.h>
+
+/*
+ * p1010rdb needs to provide a clock source for the flexcan driver.
+ */
+struct clk {
+ unsigned long rate;
+} p1010_rdb_system_clock;
+
+static struct clk *p1010_rdb_clk_get(struct device *dev, const char *id)
+{
+ const char *dev_init_name;
+
+ if (!dev)
+ return ERR_PTR(-ENOENT);
+
+ /*
+ * The can devices are named ffe1c000.can0 and ffe1d000.can1 on
+ * the p1010rdb. Check for the "can" portion of that name before
+ * returning a clock source.
+ */
+ dev_init_name = dev_name(dev);
+ if (strlen(dev_init_name) != 13)
+ return ERR_PTR(-ENOENT);
+ dev_init_name += 9;
+ if (strncmp(dev_init_name, "can", 3))
+ return ERR_PTR(-ENOENT);
+
+ return &p1010_rdb_system_clock;
+}
+
+static void p1010_rdb_clk_put(struct clk *clk)
+{
+ return;
+}
+
+static unsigned long p1010_rdb_clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+static struct clk_interface p1010_rdb_clk_functions = {
+ .clk_get = p1010_rdb_clk_get,
+ .clk_get_rate = p1010_rdb_clk_get_rate,
+ .clk_put = p1010_rdb_clk_put,
+};
+
+void __init p1010_rdb_clk_init(void)
+{
+ p1010_rdb_system_clock.rate = fsl_get_sys_freq();
+ clk_functions = p1010_rdb_clk_functions;
+}
+
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index d7387fa..d0afbf9 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -81,6 +81,15 @@ static void __init p1010_rdb_setup_arch(void)
printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
}
+extern void p1010_rdb_clk_init(void);
+
+static void __init p1010_rdb_init(void)
+{
+#ifdef CONFIG_PPC_CLOCK
+ p1010_rdb_clk_init();
+#endif
+}
+
static struct of_device_id __initdata p1010rdb_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
@@ -111,6 +120,7 @@ define_machine(p1010_rdb) {
.name = "P1010 RDB",
.probe = p1010_rdb_probe,
.setup_arch = p1010_rdb_setup_arch,
+ .init = p1010_rdb_init,
.init_IRQ = p1010_rdb_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
--
1.7.2.1
^ permalink raw reply related
* [RFC 2/4] [flexcan] Abstract off read/write for big/little endian.
From: Robin Holt @ 2011-08-09 5:55 UTC (permalink / raw)
To: Robin Holt, Marc Kleine-Budde, Wolfgang Grandegger,
U Bhaskar-B22300
Cc: socketcan-core, netdev, PPC list, Robin Holt
In-Reply-To: <1312869313-22434-1-git-send-email-holt@sgi.com>
Make flexcan driver handle register reads in the appropriate endianess.
This was a basic search and replace and then define some inlines.
Signed-off-by: Robin Holt <holt@sgi.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
To: Wolfgang Grandegger <wg@grandegger.com>
To: U Bhaskar-B22300 <B22300@freescale.com>
Cc: socketcan-core@lists.berlios.de
Cc: netdev@vger.kernel.org
Cc: PPC list <linuxppc-dev@lists.ozlabs.org>
---
drivers/net/can/flexcan.c | 140 ++++++++++++++++++++++++++------------------
1 files changed, 83 insertions(+), 57 deletions(-)
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 586b2cd..68cbe52 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -190,6 +190,31 @@ static struct can_bittiming_const flexcan_bittiming_const = {
};
/*
+ * Abstract off the read/write for arm versus ppc.
+ */
+#if defined(__BIG_ENDIAN)
+static inline u32 flexcan_read(void __iomem *addr)
+{
+ return in_be32(addr);
+}
+
+static inline void flexcan_write(u32 val, void __iomem *addr)
+{
+ out_be32(addr, val);
+}
+#else
+static inline u32 flexcan_read(void __iomem *addr)
+{
+ return readl(addr);
+}
+
+static inline void flexcan_write(u32 val, void __iomem *addr)
+{
+ writel(val, addr);
+}
+#endif
+
+/*
* Swtich transceiver on or off
*/
static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
@@ -210,9 +235,9 @@ static inline void flexcan_chip_enable(struct flexcan_priv *priv)
struct flexcan_regs __iomem *regs = priv->base;
u32 reg;
- reg = readl(®s->mcr);
+ reg = flexcan_read(®s->mcr);
reg &= ~FLEXCAN_MCR_MDIS;
- writel(reg, ®s->mcr);
+ flexcan_write(reg, ®s->mcr);
udelay(10);
}
@@ -222,9 +247,9 @@ static inline void flexcan_chip_disable(struct flexcan_priv *priv)
struct flexcan_regs __iomem *regs = priv->base;
u32 reg;
- reg = readl(®s->mcr);
+ reg = flexcan_read(®s->mcr);
reg |= FLEXCAN_MCR_MDIS;
- writel(reg, ®s->mcr);
+ flexcan_write(reg, ®s->mcr);
}
static int flexcan_get_berr_counter(const struct net_device *dev,
@@ -232,7 +257,7 @@ static int flexcan_get_berr_counter(const struct net_device *dev,
{
const struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->base;
- u32 reg = readl(®s->ecr);
+ u32 reg = flexcan_read(®s->ecr);
bec->txerr = (reg >> 0) & 0xff;
bec->rxerr = (reg >> 8) & 0xff;
@@ -266,15 +291,15 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
if (cf->can_dlc > 0) {
u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
- writel(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
+ flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
}
if (cf->can_dlc > 3) {
u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
- writel(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
+ flexcan_write(data, ®s->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
}
- writel(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
- writel(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+ flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
+ flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
kfree_skb(skb);
@@ -462,8 +487,8 @@ static void flexcan_read_fifo(const struct net_device *dev,
struct flexcan_mb __iomem *mb = ®s->cantxfg[0];
u32 reg_ctrl, reg_id;
- reg_ctrl = readl(&mb->can_ctrl);
- reg_id = readl(&mb->can_id);
+ reg_ctrl = flexcan_read(&mb->can_ctrl);
+ reg_id = flexcan_read(&mb->can_id);
if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
else
@@ -473,12 +498,12 @@ static void flexcan_read_fifo(const struct net_device *dev,
cf->can_id |= CAN_RTR_FLAG;
cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
- *(__be32 *)(cf->data + 0) = cpu_to_be32(readl(&mb->data[0]));
- *(__be32 *)(cf->data + 4) = cpu_to_be32(readl(&mb->data[1]));
+ *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
+ *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
/* mark as read */
- writel(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
- readl(®s->timer);
+ flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
+ flexcan_read(®s->timer);
}
static int flexcan_read_frame(struct net_device *dev)
@@ -514,17 +539,17 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
* The error bits are cleared on read,
* use saved value from irq handler.
*/
- reg_esr = readl(®s->esr) | priv->reg_esr;
+ reg_esr = flexcan_read(®s->esr) | priv->reg_esr;
/* handle state changes */
work_done += flexcan_poll_state(dev, reg_esr);
/* handle RX-FIFO */
- reg_iflag1 = readl(®s->iflag1);
+ reg_iflag1 = flexcan_read(®s->iflag1);
while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
work_done < quota) {
work_done += flexcan_read_frame(dev);
- reg_iflag1 = readl(®s->iflag1);
+ reg_iflag1 = flexcan_read(®s->iflag1);
}
/* report bus errors */
@@ -534,8 +559,8 @@ static int flexcan_poll(struct napi_struct *napi, int quota)
if (work_done < quota) {
napi_complete(napi);
/* enable IRQs */
- writel(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
- writel(priv->reg_ctrl_default, ®s->ctrl);
+ flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
+ flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
}
return work_done;
@@ -549,9 +574,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
struct flexcan_regs __iomem *regs = priv->base;
u32 reg_iflag1, reg_esr;
- reg_iflag1 = readl(®s->iflag1);
- reg_esr = readl(®s->esr);
- writel(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */
+ reg_iflag1 = flexcan_read(®s->iflag1);
+ reg_esr = flexcan_read(®s->esr);
+ flexcan_write(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */
/*
* schedule NAPI in case of:
@@ -567,16 +592,16 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
* save them for later use.
*/
priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
- writel(FLEXCAN_IFLAG_DEFAULT & ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE,
- ®s->imask1);
- writel(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
+ flexcan_write(FLEXCAN_IFLAG_DEFAULT &
+ ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->imask1);
+ flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
®s->ctrl);
napi_schedule(&priv->napi);
}
/* FIFO overflow */
if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
- writel(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
+ flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
dev->stats.rx_over_errors++;
dev->stats.rx_errors++;
}
@@ -585,7 +610,7 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
/* tx_bytes is incremented in flexcan_start_xmit */
stats->tx_packets++;
- writel((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
+ flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
netif_wake_queue(dev);
}
@@ -599,7 +624,7 @@ static void flexcan_set_bittiming(struct net_device *dev)
struct flexcan_regs __iomem *regs = priv->base;
u32 reg;
- reg = readl(®s->ctrl);
+ reg = flexcan_read(®s->ctrl);
reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
FLEXCAN_CTRL_RJW(0x3) |
FLEXCAN_CTRL_PSEG1(0x7) |
@@ -623,11 +648,11 @@ static void flexcan_set_bittiming(struct net_device *dev)
reg |= FLEXCAN_CTRL_SMP;
dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg);
- writel(reg, ®s->ctrl);
+ flexcan_write(reg, ®s->ctrl);
/* print chip status */
dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
- readl(®s->mcr), readl(®s->ctrl));
+ flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
}
/*
@@ -648,10 +673,10 @@ static int flexcan_chip_start(struct net_device *dev)
flexcan_chip_enable(priv);
/* soft reset */
- writel(FLEXCAN_MCR_SOFTRST, ®s->mcr);
+ flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
udelay(10);
- reg_mcr = readl(®s->mcr);
+ reg_mcr = flexcan_read(®s->mcr);
if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
dev_err(dev->dev.parent,
"Failed to softreset can module (mcr=0x%08x)\n",
@@ -673,12 +698,12 @@ static int flexcan_chip_start(struct net_device *dev)
* choose format C
*
*/
- reg_mcr = readl(®s->mcr);
+ reg_mcr = flexcan_read(®s->mcr);
reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
FLEXCAN_MCR_IDAM_C;
dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr);
- writel(reg_mcr, ®s->mcr);
+ flexcan_write(reg_mcr, ®s->mcr);
/*
* CTRL
@@ -696,7 +721,7 @@ static int flexcan_chip_start(struct net_device *dev)
* (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any
* warning or bus passive interrupts.
*/
- reg_ctrl = readl(®s->ctrl);
+ reg_ctrl = flexcan_read(®s->ctrl);
reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK;
@@ -704,38 +729,39 @@ static int flexcan_chip_start(struct net_device *dev)
/* save for later use */
priv->reg_ctrl_default = reg_ctrl;
dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
- writel(reg_ctrl, ®s->ctrl);
+ flexcan_write(reg_ctrl, ®s->ctrl);
for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
- writel(0, ®s->cantxfg[i].can_ctrl);
- writel(0, ®s->cantxfg[i].can_id);
- writel(0, ®s->cantxfg[i].data[0]);
- writel(0, ®s->cantxfg[i].data[1]);
+ flexcan_write(0, ®s->cantxfg[i].can_ctrl);
+ flexcan_write(0, ®s->cantxfg[i].can_id);
+ flexcan_write(0, ®s->cantxfg[i].data[0]);
+ flexcan_write(0, ®s->cantxfg[i].data[1]);
/* put MB into rx queue */
- writel(FLEXCAN_MB_CNT_CODE(0x4), ®s->cantxfg[i].can_ctrl);
+ flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
+ ®s->cantxfg[i].can_ctrl);
}
/* acceptance mask/acceptance code (accept everything) */
- writel(0x0, ®s->rxgmask);
- writel(0x0, ®s->rx14mask);
- writel(0x0, ®s->rx15mask);
+ flexcan_write(0x0, ®s->rxgmask);
+ flexcan_write(0x0, ®s->rx14mask);
+ flexcan_write(0x0, ®s->rx15mask);
flexcan_transceiver_switch(priv, 1);
/* synchronize with the can bus */
- reg_mcr = readl(®s->mcr);
+ reg_mcr = flexcan_read(®s->mcr);
reg_mcr &= ~FLEXCAN_MCR_HALT;
- writel(reg_mcr, ®s->mcr);
+ flexcan_write(reg_mcr, ®s->mcr);
priv->can.state = CAN_STATE_ERROR_ACTIVE;
/* enable FIFO interrupts */
- writel(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
+ flexcan_write(FLEXCAN_IFLAG_DEFAULT, ®s->imask1);
/* print chip status */
dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n",
- __func__, readl(®s->mcr), readl(®s->ctrl));
+ __func__, flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
return 0;
@@ -757,12 +783,12 @@ static void flexcan_chip_stop(struct net_device *dev)
u32 reg;
/* Disable all interrupts */
- writel(0, ®s->imask1);
+ flexcan_write(0, ®s->imask1);
/* Disable + halt module */
- reg = readl(®s->mcr);
+ reg = flexcan_read(®s->mcr);
reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
- writel(reg, ®s->mcr);
+ flexcan_write(reg, ®s->mcr);
flexcan_transceiver_switch(priv, 0);
priv->can.state = CAN_STATE_STOPPED;
@@ -854,24 +880,24 @@ static int __devinit register_flexcandev(struct net_device *dev)
/* select "bus clock", chip must be disabled */
flexcan_chip_disable(priv);
- reg = readl(®s->ctrl);
+ reg = flexcan_read(®s->ctrl);
reg |= FLEXCAN_CTRL_CLK_SRC;
- writel(reg, ®s->ctrl);
+ flexcan_write(reg, ®s->ctrl);
flexcan_chip_enable(priv);
/* set freeze, halt and activate FIFO, restrict register access */
- reg = readl(®s->mcr);
+ reg = flexcan_read(®s->mcr);
reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
- writel(reg, ®s->mcr);
+ flexcan_write(reg, ®s->mcr);
/*
* Currently we only support newer versions of this core
* featuring a RX FIFO. Older cores found on some Coldfire
* derivates are not yet supported.
*/
- reg = readl(®s->mcr);
+ reg = flexcan_read(®s->mcr);
if (!(reg & FLEXCAN_MCR_FEN)) {
dev_err(dev->dev.parent,
"Could not enable RX FIFO, unsupported core\n");
--
1.7.2.1
^ permalink raw reply related
* [RFC 3/4] [flexcan] Add of_match to platform_device definition.
From: Robin Holt @ 2011-08-09 5:55 UTC (permalink / raw)
To: Robin Holt, Marc Kleine-Budde, Wolfgang Grandegger,
U Bhaskar-B22300
Cc: socketcan-core, netdev, PPC list, Robin Holt
In-Reply-To: <1312869313-22434-1-git-send-email-holt@sgi.com>
On powerpc, the OpenFirmware devices are not matched without specifying
an of_match array. Introduce that array as that is used for matching
on the Freescale P1010 processor.
Signed-off-by: Robin Holt <holt@sgi.com>
To: Marc Kleine-Budde <mkl@pengutronix.de>
To: Wolfgang Grandegger <wg@grandegger.com>
To: U Bhaskar-B22300 <B22300@freescale.com>
Cc: socketcan-core@lists.berlios.de
Cc: netdev@vger.kernel.org
Cc: PPC list <linuxppc-dev@lists.ozlabs.org>
---
drivers/net/can/flexcan.c | 13 ++++++++++++-
1 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 68cbe52..662f832 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -1027,8 +1027,19 @@ static int __devexit flexcan_remove(struct platform_device *pdev)
return 0;
}
+static struct of_device_id flexcan_of_match[] = {
+ {
+ .compatible = "fsl,flexcan",
+ },
+ {},
+};
+
static struct platform_driver flexcan_driver = {
- .driver.name = DRV_NAME,
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = flexcan_of_match,
+ },
.probe = flexcan_probe,
.remove = __devexit_p(flexcan_remove),
};
--
1.7.2.1
^ permalink raw reply related
* [RFC 0/4] [flexcan/powerpc] Add support for powerpc flexcan (freescale p1010) -V7
From: Robin Holt @ 2011-08-09 5:55 UTC (permalink / raw)
To: Robin Holt, Marc Kleine-Budde, Wolfgang Grandegger,
U Bhaskar-B22300
Cc: socketcan-core, netdev, PPC list, Robin Holt
Marc, Wolfgang or U Bhaskar,
This patch set should have all your comments included. It is based on
the David S. Miller net-next-2.6 tree commit 19fd617.
I have compiled each patch in the series individually for both arm and
powerpc (cheated on ppc and reordered them with the last patch first so
I could select CAN_FLEXCAN.
With all the patches applied, my p1010rdb works for communicating between
its two can ports and also can communicate with an external PSOC. I have
done no testing beyond compile testing on an arm system as I have no
access to an arm based system.
For the first three patches in the series, I believe they are all ready
for submission to David S. Miller for the netdev tree. This is the
first submission of patch 4 which, I believe, will end up going through
the linuxppc-dev list and can go at any time after the flexcan patches
are submitted. As long the first and last patches are both applied,
the tree will compile for either ppc or arm, but will not work without
all patches. If the ppc patch (4/4) gets applied before 1/4, we could
have a random config tester detect a compile failure on ppc if they
select NET, CAN, and CAN_FLEXCAN.
Thanks,
Robin Holt
^ permalink raw reply
* [RFC 4/4] [powerpc] Add flexcan device support for p1010rdb.
From: Robin Holt @ 2011-08-09 5:55 UTC (permalink / raw)
To: Robin Holt, Marc Kleine-Budde, Wolfgang Grandegger,
U Bhaskar-B22300
Cc: socketcan-core, , PPC list, Robin Holt, netdev
In-Reply-To: <1312869313-22434-1-git-send-email-holt@sgi.com>
I added a clock source for the p1010rdb so the flexcan driver
could find its clock frequency.
Signed-off-by: Robin Holt <holt@sgi.com>
To: Marc Kleine-Budde <mkl@pengutronix.de>,
To: Wolfgang Grandegger <wg@grandegger.com>,
To: U Bhaskar-B22300 <B22300@freescale.com>
Cc: socketcan-core@lists.berlios.de,
Cc: netdev@vger.kernel.org,
Cc: PPC list <linuxppc-dev@lists.ozlabs.org>
---
Could I also get a ruling on the Kconfig language. I could do it either
with the 85xx_HAVE_CAN_FLEXCAN in or out of the Kconfig file. It felt
like the right thing to do was without, but the arm Kconfig files do
it this way and a patch from freescale had something similar so I went
this route.
arch/powerpc/platforms/85xx/Kconfig | 6 +++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/clock.c | 59 ++++++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/p1010rdb.c | 8 ++++
4 files changed, 74 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/85xx/clock.c
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 498534c..ed4cf92 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -26,6 +26,10 @@ config MPC8560_ADS
help
This option enables support for the MPC 8560 ADS board
+config 85xx_HAVE_CAN_FLEXCAN
+ bool
+ select HAVE_CAN_FLEXCAN if NET && CAN
+
config MPC85xx_CDS
bool "Freescale MPC85xx CDS"
select DEFAULT_UIMAGE
@@ -70,6 +74,8 @@ config MPC85xx_RDB
config P1010_RDB
bool "Freescale P1010RDB"
select DEFAULT_UIMAGE
+ select 85xx_HAVE_CAN_FLEXCAN
+ select PPC_CLOCK if CAN_FLEXCAN
help
This option enables support for the MPC85xx RDB (P1010 RDB) board
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index a971b32..64ad7a4 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
obj-$(CONFIG_P1010_RDB) += p1010rdb.o
+obj-$(CONFIG_PPC_CLOCK) += clock.o
obj-$(CONFIG_P1022_DS) += p1022_ds.o
obj-$(CONFIG_P1023_RDS) += p1023_rds.o
obj-$(CONFIG_P2040_RDB) += p2040_rdb.o corenet_ds.o
diff --git a/arch/powerpc/platforms/85xx/clock.c b/arch/powerpc/platforms/85xx/clock.c
new file mode 100644
index 0000000..a25cbf3
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/clock.c
@@ -0,0 +1,59 @@
+
+#include <linux/device.h>
+#include <linux/err.h>
+
+#include <asm/clk_interface.h>
+
+#include <sysdev/fsl_soc.h>
+
+/*
+ * p1010rdb needs to provide a clock source for the flexcan driver.
+ */
+struct clk {
+ unsigned long rate;
+} p1010_rdb_system_clock;
+
+static struct clk *p1010_rdb_clk_get(struct device *dev, const char *id)
+{
+ const char *dev_init_name;
+
+ if (!dev)
+ return ERR_PTR(-ENOENT);
+
+ /*
+ * The can devices are named ffe1c000.can0 and ffe1d000.can1 on
+ * the p1010rdb. Check for the "can" portion of that name before
+ * returning a clock source.
+ */
+ dev_init_name = dev_name(dev);
+ if (strlen(dev_init_name) != 13)
+ return ERR_PTR(-ENOENT);
+ dev_init_name += 9;
+ if (strncmp(dev_init_name, "can", 3))
+ return ERR_PTR(-ENOENT);
+
+ return &p1010_rdb_system_clock;
+}
+
+static void p1010_rdb_clk_put(struct clk *clk)
+{
+ return;
+}
+
+static unsigned long p1010_rdb_clk_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+static struct clk_interface p1010_rdb_clk_functions = {
+ .clk_get = p1010_rdb_clk_get,
+ .clk_get_rate = p1010_rdb_clk_get_rate,
+ .clk_put = p1010_rdb_clk_put,
+};
+
+void __init p1010_rdb_clk_init(void)
+{
+ p1010_rdb_system_clock.rate = fsl_get_sys_freq();
+ clk_functions = p1010_rdb_clk_functions;
+}
+
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index d7387fa..29e04d6 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -81,6 +81,13 @@ static void __init p1010_rdb_setup_arch(void)
printk(KERN_INFO "P1010 RDB board from Freescale Semiconductor\n");
}
+static void __init p1010_rdb_init(void)
+{
+#ifdef PPC_CLOCK
+ p1010_rdb_clk_init();
+#endif
+}
+
static struct of_device_id __initdata p1010rdb_ids[] = {
{ .type = "soc", },
{ .compatible = "soc", },
@@ -111,6 +118,7 @@ define_machine(p1010_rdb) {
.name = "P1010 RDB",
.probe = p1010_rdb_probe,
.setup_arch = p1010_rdb_setup_arch,
+ .init = p1010_rdb_init,
.init_IRQ = p1010_rdb_pic_init,
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
--
1.7.2.1
^ permalink raw reply related
* [RFC 1/4] [flexcan] Remove #include <mach/clock.h>
From: Robin Holt @ 2011-08-09 5:55 UTC (permalink / raw)
To: Robin Holt, Marc Kleine-Budde, Wolfgang Grandegger,
U Bhaskar-B22300
Cc: socketcan-core, netdev, PPC list, Robin Holt
In-Reply-To: <1312869313-22434-1-git-send-email-holt@sgi.com>
powerpc does not have a mach-####/clock.h. When testing, I found neither
arm nor powerpc needed the mach/clock.h at all so I removed it.
Signed-off-by: Robin Holt <holt@sgi.com>
To: Marc Kleine-Budde <mkl@pengutronix.de>
To: Wolfgang Grandegger <wg@grandegger.com>
To: U Bhaskar-B22300 <B22300@freescale.com>
Cc: socketcan-core@lists.berlios.de
Cc: netdev@vger.kernel.org
Cc: PPC list <linuxppc-dev@lists.ozlabs.org>
---
drivers/net/can/flexcan.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 1767811..586b2cd 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -35,8 +35,6 @@
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <mach/clock.h>
-
#define DRV_NAME "flexcan"
/* 8 for RX fifo and 2 error handling */
--
1.7.2.1
^ permalink raw reply related
* RE: FW: Ethernet driver WR linux
From: smitha.vanga @ 2011-08-09 5:46 UTC (permalink / raw)
To: scottwood; +Cc: linuxppc-dev
In-Reply-To: <4E404D1F.6020503@freescale.com>
Thank Scott. I am working on a legacy project Which is using 2.6.21
linux kernel so the device tree is based on that.
Can you let me why the probe error of the driver happens. So that I can
keep a patch in the code.Or What exacly in the device tree it is
missing. That would be of great help.
Thanks & Regards,
Smitha
-----Original Message-----
From: Scott Wood [mailto:scottwood@freescale.com]
Sent: Tuesday, August 09, 2011 2:25 AM
To: Smitha Vanga (WT01 - GMT-Telecom Equipment)
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: FW: Ethernet driver WR linux
On 08/08/2011 12:53 AM, smitha.vanga@wipro.com wrote:
>
> Hi Scott,
>
> Below is the .dts file. My board is based on mpc8247. Currently using
> FCC1.
This device tree is based on something very short-lived when 82xx
support was first being worked on for 82xx, around 2.6.24 or so. Please
redo it from scratch based on what is in the current kernel.
-Scott
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^ permalink raw reply
* Re: [PATCH 3/3] powerpc: icswx: Simple ACOP fault handler for both book3e and book3s parts.
From: Kumar Gala @ 2011-08-09 5:26 UTC (permalink / raw)
To: Jimi Xenidis; +Cc: linuxppc-dev, Ian Munsie, Anton Blanchard
In-Reply-To: <1312842408-21482-4-git-send-email-jimix@pobox.com>
On Aug 8, 2011, at 5:26 PM, Jimi Xenidis wrote:
> This patch adds a fault handler that responds to illegal Coprocessor
> types. Currently all CTs are treated and illegal. There are two ways
> to report the fault back to the application. If the application used
> the record form ("icswx.") then the architected "reject" is emulated.
> If the application did not used the record form ("icswx") then it is
> selectable by config whether the failure is silent (as architected) or
> a SIGILL is generated.
>=20
> In all cases pr_warn() is used to log the bad CT.
>=20
> Signed-off-by: Jimi Xenidis <jimix@pobox.com>
> ---
> arch/powerpc/mm/fault.c | 16 +++++
> arch/powerpc/mm/icswx.c | 114 =
++++++++++++++++++++++++++++++++
> arch/powerpc/mm/icswx.h | 34 ++++++++++
> arch/powerpc/platforms/Kconfig.cputype | 11 +++
> 4 files changed, 175 insertions(+), 0 deletions(-)
>=20
> diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
> index 5efe8c9..88abe70 100644
> --- a/arch/powerpc/mm/fault.c
> +++ b/arch/powerpc/mm/fault.c
> @@ -43,6 +43,7 @@
> #include <asm/tlbflush.h>
> #include <asm/siginfo.h>
> #include <mm/mmu_decl.h>
> +#include <mm/icswx.h>
>=20
> #ifdef CONFIG_KPROBES
> static inline int notify_page_fault(struct pt_regs *regs)
> @@ -143,6 +144,21 @@ int __kprobes do_page_fault(struct pt_regs *regs, =
unsigned long address,
> is_write =3D error_code & ESR_DST;
> #endif /* CONFIG_4xx || CONFIG_BOOKE */
>=20
> +#ifdef CONFIG_PPC_ICSWX
> + /*
> + * we need to do this early because this "data storage
> + * interrupt" does not update the DAR/DEAR so we don't want to
> + * look at it
> + */
> + if (error_code & ICSWX_DSI_UCT) {
> + int ret;
> +
> + ret =3D acop_handle_fault(regs, address, error_code);
> + if (ret)
> + return ret;
> + }
> +#endif
> +
> if (notify_page_fault(regs))
> return 0;
>=20
> diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
> index 667330e..fbf71b4 100644
> --- a/arch/powerpc/mm/icswx.c
> +++ b/arch/powerpc/mm/icswx.c
> @@ -17,6 +17,9 @@
> #include <linux/mm.h>
> #include <linux/spinlock.h>
> #include <linux/module.h>
> +
> +#include <asm/uaccess.h>
> +
> #include "icswx.h"
>=20
>=20
> @@ -161,3 +164,114 @@ void drop_cop(unsigned long acop, struct =
mm_struct *mm)
> up_read(&mm->mmap_sem);
> }
> EXPORT_SYMBOL_GPL(drop_cop);
> +
> +static int acop_use_cop(int ct)
> +{
> + /* todo */
> + return -1;
> +}
> +
> +/*
> + * Get the instruction word at the NIP
> + */
> +static u32 acop_get_inst(struct pt_regs *regs)
> +{
> + u32 inst;
> + u32 __user *p;
> +
> + p =3D (u32 __user *)regs->nip;
> + if (!access_ok(VERIFY_READ, p, sizeof(*p)))
> + return 0;
> +
> + if (__get_user(inst, p))
> + return 0;
> +
> + return inst;
> +}
> +
> +/**
> + * @regs: regsiters at time of interrupt
> + * @address: storage address
> + * @error_code: Fault code, usually the DSISR or ESR depending on
> + * processor type
> + *
> + * Return 0 if we are able to resolve the data storage fault that
> + * results from a CT miss in the ACOP register.
> + */
> +int acop_handle_fault(struct pt_regs *regs, unsigned long address,
> + unsigned long error_code)
> +{
> + int ct;
> + u32 inst =3D 0;
> +
> + if (!cpu_has_feature(CPU_FTR_ICSWX)) {
> + pr_info("No coprocessors available");
> + _exception(SIGILL, regs, ILL_ILLOPN, address);
> + }
> +
> + if (!user_mode(regs)) {
> + /* this could happen if the HV denies the
> + * kernel access, for now we just die */
> + die("ICSWX from kernel failed", regs, SIGSEGV);
> + }
> +
> + /* Some implementations leave us a hint for the CT */
> + ct =3D ICSWX_GET_CT_HINT(error_code);
> + if (ct < 0) {
> + /* we have to peek at the instruction work to figure out =
CT */
> + union cop_ccw ccw;
don't use a union, we don't do this for any other place we decode =
instructions (just use shift/mask). Utilize ppc-opcode.h
> + u32 rs;
> +
> + inst =3D acop_get_inst(regs);
> + if (inst =3D=3D 0)
> + return -1;
> +
> + rs =3D (inst >> (31 - 10)) & 0x1f;
> + ccw._val =3D regs->gpr[rs];
> + ct =3D ccw.ct;
> + }
> +
> + if (!acop_use_cop(ct))
> + return 0;
> +
> + /* at this point the CT is unknown to the system */
> + pr_warn("%s[%d]: Coprocessor %d is unavailable",
> + current->comm, current->pid, ct);
> +
> + /* get inst if we don't already have it */
> + if (inst =3D=3D 0) {
> + inst =3D acop_get_inst(regs);
> + if (inst =3D=3D 0)
> + return -1;
> + }
> +
> + /* Check if the instruction is the "record form" */
> + if (inst & 1) {
> + /*=20
> + * the instruction is "record" form so we can reject
> + * using CR0
> + */
> + regs->ccr &=3D ~(0xful << 28);
> + regs->ccr |=3D ICSWX_RC_NOT_FOUND << 28;
> +
> + /* Move on to the next instruction */
> + regs->nip +=3D 4;
> + } else {
> + /*
> + * There is no architected mechanism to report a bad
> + * CT so we could either SIGILL or report nothing.
> + * Since the non-record version should only bu used
> + * for "hints" or "don't care" we should probably do
> + * nothing. However, I could see how some people
> + * might want an SIGILL so it here if you want it.
> + */
> +#ifdef CONFIG_ICSWX_USE_SIGILL
> + _exception(SIGILL, regs, ILL_ILLOPN, address);
Where is CONFIG_ICSWX_USE_SIGILL defined? You have PPC_ICSWX_USE_SIGILL
> +#else
> + regs->nip +=3D 4;
> +#endif
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(acop_handle_fault);
> diff --git a/arch/powerpc/mm/icswx.h b/arch/powerpc/mm/icswx.h
> index 5121ddd..920d9f3 100644
> --- a/arch/powerpc/mm/icswx.h
> +++ b/arch/powerpc/mm/icswx.h
> @@ -32,3 +32,37 @@ extern void free_cop_pid(int free_pid);
> #define disable_cop_pid(m) (COP_PID_NONE)
> #define free_cop_pid(p)
> #endif
> +
> +/*
> + * These are implementation bits for architected registers. If this
> + * ever becomes architecture the should be moved to reg.h et. al.
> + */
> +/* UCT is the same bit for Server and Embedded */
> +#define ICSWX_DSI_UCT 0x00004000 /* Unavailable =
Coprocessor Type */
> +
> +#ifdef CONFIG_BOOKE
> +/* Embedded implementation gives us no hits as to what the CT is */
> +#define ICSWX_GET_CT_HINT(x) (-1)
> +#else
> +/* Server implementation contains the CT value in the DSISR */
> +#define ICSWX_DSISR_CTMASK 0x00003f00
> +#define ICSWX_GET_CT_HINT(x) (((x) & ICSWX_DSISR_CTMASK) >> 8)
> +#endif
> +
> +union cop_ccw {
> + u32 _val;
> + struct {
> + u32 msb:8;
> + u32 reserved:2;
> + u32 ct:6;
> + u32 cd:16;
> + };
> +};
kill the union, move some of the opcode stuff into ppc-opcode.h
> +
> +#define ICSWX_RC_STARTED 0x8 /* The request has been started =
*/
> +#define ICSWX_RC_NOT_IDLE 0x4 /* No coprocessor found idle */
> +#define ICSWX_RC_NOT_FOUND 0x2 /* No coprocessor found */
> +#define ICSWX_RC_UNDEFINED 0x1 /* Reserved */
> +
> +extern int acop_handle_fault(struct pt_regs *regs, unsigned long =
address,
> + unsigned long error_code);
> diff --git a/arch/powerpc/platforms/Kconfig.cputype =
b/arch/powerpc/platforms/Kconfig.cputype
> index 3cd22e5..817d723 100644
> --- a/arch/powerpc/platforms/Kconfig.cputype
> +++ b/arch/powerpc/platforms/Kconfig.cputype
> @@ -258,6 +258,17 @@ config PPC_ICSWX_PID
> PID register in server is used explicitly for ICSWX. In
> embedded systems PID managment is done by the system.
>=20
> +config PPC_ICSWX_USE_SIGILL
> + bool "Should a bad CT cause a SIGILL?"
Is there some reason to even have this cfg option?
> + depends on PPC_ICSWX
> + default n
> + ---help---
> + Should a bad CT used for "non-record form ICSWX" cause an
> + illegal intruction signal or should it be silent as
> + architected.
> +
> + If in doubt, say N here.
> +
> config SPE
> bool "SPE Support"
> depends on E200 || (E500 && !PPC_E500MC)
> --=20
> 1.7.0.4
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 2/3] powerpc: book3e: Add ICSWX/ACOP support to Book3e cores like A2
From: Kumar Gala @ 2011-08-09 5:22 UTC (permalink / raw)
To: Jimi Xenidis; +Cc: linuxppc-dev, Ian Munsie, Anton Blanchard
In-Reply-To: <1312842408-21482-3-git-send-email-jimix@pobox.com>
On Aug 8, 2011, at 5:26 PM, Jimi Xenidis wrote:
> ICSWX is also used by the A2 processor to access coprocessors,
> although not all "chips" that contain A2s have coprocessors.
>=20
> Signed-off-by: Jimi Xenidis <jimix@pobox.com>
> ---
> arch/powerpc/include/asm/cputable.h | 2 +-
> arch/powerpc/include/asm/mmu-book3e.h | 4 ++++
> arch/powerpc/include/asm/reg_booke.h | 4 ++++
> arch/powerpc/kernel/cpu_setup_a2.S | 10 ++++++++--
> arch/powerpc/platforms/wsp/Kconfig | 1 +
> 5 files changed, 18 insertions(+), 3 deletions(-)
>=20
> diff --git a/arch/powerpc/include/asm/cputable.h =
b/arch/powerpc/include/asm/cputable.h
> index e30442c..7044233 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -437,7 +437,7 @@ extern const char *powerpc_base_platform;
> #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
>=20
> #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
> - CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
> + CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | =
CPU_FTR_ICSWX)
>=20
> #ifdef __powerpc64__
> #ifdef CONFIG_PPC_BOOK3E
> diff --git a/arch/powerpc/include/asm/mmu-book3e.h =
b/arch/powerpc/include/asm/mmu-book3e.h
> index 3ea0f9a..06d7f91 100644
> --- a/arch/powerpc/include/asm/mmu-book3e.h
> +++ b/arch/powerpc/include/asm/mmu-book3e.h
> @@ -212,6 +212,10 @@ typedef struct {
> unsigned int id;
> unsigned int active;
> unsigned long vdso_base;
> +#ifdef CONFIG_PPC_ICSWX
> + struct spinlock *cop_lockp; /* guard acop and cop_pid */
> + unsigned long acop; /* mask of enabled coprocessor types */
> +#endif /* CONFIG_PPC_ICSWX */
match whitespace (tab) formatting.
> } mm_context_t;
>=20
> /* Page size definitions, common between 32 and 64-bit
- k=
^ permalink raw reply
* Re: [PATCH 1/3] powerpc: Split ICSWX ACOP and PID processing
From: Kumar Gala @ 2011-08-09 5:20 UTC (permalink / raw)
To: Jimi Xenidis; +Cc: linuxppc-dev, Ian Munsie, Anton Blanchard
In-Reply-To: <1312842408-21482-2-git-send-email-jimix@pobox.com>
On Aug 8, 2011, at 5:26 PM, Jimi Xenidis wrote:
> Some processors, like embedded, that already have a PID register that
> is managed by the system. This patch separates the ACOP and PID
> processing into separate files so that the ACOP code can be shared.
>=20
> Signed-off-by: Jimi Xenidis <jimix@pobox.com>
> ---
> arch/powerpc/mm/Makefile | 4 +-
> arch/powerpc/mm/icswx.c | 163 =
++++++++++++++++++++++++++
> arch/powerpc/mm/icswx.h | 34 ++++++
> arch/powerpc/mm/icswx_pid.c | 87 ++++++++++++++
> arch/powerpc/mm/mmu_context_hash64.c | 195 =
--------------------------------
> arch/powerpc/platforms/Kconfig.cputype | 10 ++-
> 6 files changed, 296 insertions(+), 197 deletions(-)
> create mode 100644 arch/powerpc/mm/icswx.c
> create mode 100644 arch/powerpc/mm/icswx.h
> create mode 100644 arch/powerpc/mm/icswx_pid.c
>=20
> diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
> index bdca46e..ba51190 100644
> --- a/arch/powerpc/mm/Makefile
> +++ b/arch/powerpc/mm/Makefile
> @@ -21,7 +21,9 @@ obj-$(CONFIG_PPC_STD_MMU_32) +=3D =
ppc_mmu_32.o
> obj-$(CONFIG_PPC_STD_MMU) +=3D hash_low_$(CONFIG_WORD_SIZE).o \
> tlb_hash$(CONFIG_WORD_SIZE).o \
> mmu_context_hash$(CONFIG_WORD_SIZE).o
> -obj-$(CONFIG_40x) +=3D 40x_mmu.o
> +obj-$(CONFIG_PPC_ICSWX) +=3D icswx.o
> +obj-$(CONFIG_PPC_ICSWX_PID) +=3D icswx_pid.o
> +obj-$(CONFIG_40x) +=3D 40x_mmu.o?
? seems like a typo
> obj-$(CONFIG_44x) +=3D 44x_mmu.o
> obj-$(CONFIG_PPC_FSL_BOOK3E) +=3D fsl_booke_mmu.o
> obj-$(CONFIG_NEED_MULTIPLE_NODES) +=3D numa.o
^ permalink raw reply
* [PATCH] rio: Use discovered bit to test if enumeration is complete
From: Liu Gang @ 2011-08-09 2:17 UTC (permalink / raw)
To: linux-kernel
Cc: r58472, Liu Gang, r61911, linuxppc-dev, Liu Gang, akpm, B11780
The discovered bit in PGCCSR register indicates if the device has
been discovered by system host. In Rapidio system, some agent devices
can also be master devices. They can issue requests into the system.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---
drivers/rapidio/rio-scan.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/rapidio/rio-scan.c b/drivers/rapidio/rio-scan.c
index ee89358..2dac1f0 100644
--- a/drivers/rapidio/rio-scan.c
+++ b/drivers/rapidio/rio-scan.c
@@ -924,7 +924,7 @@ static int __devinit rio_enum_peer(struct rio_net *net, struct rio_mport *port,
* rio_enum_complete- Tests if enumeration of a network is complete
* @port: Master port to send transaction
*
- * Tests the Component Tag CSR for non-zero value (enumeration
+ * Tests the PGCCSR discovered bit for non-zero value (enumeration
* complete flag). Return %1 if enumeration is complete or %0 if
* enumeration is incomplete.
*/
@@ -934,7 +934,7 @@ static int rio_enum_complete(struct rio_mport *port)
rio_local_read_config_32(port, port->phys_efptr + RIO_PORT_GEN_CTL_CSR,
®val);
- return (regval & RIO_PORT_GEN_MASTER) ? 1 : 0;
+ return (regval & RIO_PORT_GEN_DISCOVERED) ? 1 : 0;
}
/**
--
1.7.3.1
^ permalink raw reply related
* [PATCH 2/2] powerpc: poweren: pci-msi: Add MSI support for PCI on PowerEN
From: Jimi Xenidis @ 2011-08-08 22:30 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Michael Ellerman, Ian Munsie
In-Reply-To: <1312842655-21526-1-git-send-email-jimix@pobox.com>
From: Michael Ellerman <michael@ellerman.id.au>
Based on a patch by Michael Ellerman <michael@ellerman.id.au>
Patch was simply forward ported upstream.
Jimi Xenidis <jimix@pobox.com>
---
arch/powerpc/platforms/wsp/Makefile | 1 +
arch/powerpc/platforms/wsp/ics.c | 48 ++++++++++++++++
arch/powerpc/platforms/wsp/ics.h | 5 ++
arch/powerpc/platforms/wsp/msi.c | 102 +++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/wsp/msi.h | 19 +++++++
5 files changed, 175 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/wsp/msi.c
create mode 100644 arch/powerpc/platforms/wsp/msi.h
diff --git a/arch/powerpc/platforms/wsp/Makefile b/arch/powerpc/platforms/wsp/Makefile
index 84519f8..a1486b4 100644
--- a/arch/powerpc/platforms/wsp/Makefile
+++ b/arch/powerpc/platforms/wsp/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PPC_PSR2) += psr2.o opb_pic.o
obj-$(CONFIG_PPC_WSP) += scom_wsp.o
obj-$(CONFIG_SMP) += smp.o scom_smp.o
obj-$(CONFIG_PCI) += wsp_pci.o
+obj-$(CONFIG_PCI_MSI) += msi.o
\ No newline at end of file
diff --git a/arch/powerpc/platforms/wsp/ics.c b/arch/powerpc/platforms/wsp/ics.c
index e53bd9e..5768743 100644
--- a/arch/powerpc/platforms/wsp/ics.c
+++ b/arch/powerpc/platforms/wsp/ics.c
@@ -710,3 +710,51 @@ void __init wsp_init_irq(void)
/* We need to patch our irq chip's EOI to point to the right ICP */
wsp_irq_chip.irq_eoi = icp_ops->eoi;
}
+
+#ifdef CONFIG_PCI_MSI
+static void wsp_ics_msi_unmask_irq(struct irq_data *d)
+{
+ wsp_chip_unmask_irq(d);
+ unmask_msi_irq(d);
+}
+
+static unsigned int wsp_ics_msi_startup(struct irq_data *d)
+{
+ wsp_ics_msi_unmask_irq(d);
+ return 0;
+}
+
+static void wsp_ics_msi_mask_irq(struct irq_data *d)
+{
+ mask_msi_irq(d);
+ wsp_chip_mask_irq(d);
+}
+
+/*
+ * we do it this way because we reassinge default EOI handling in
+ * irq_init() above
+ */
+static void wsp_ics_eoi(struct irq_data *data)
+{
+ wsp_irq_chip.irq_eoi(data);
+}
+
+static struct irq_chip wsp_ics_msi = {
+ .name = "WSP ICS MSI",
+ .irq_startup = wsp_ics_msi_startup,
+ .irq_mask = wsp_ics_msi_mask_irq,
+ .irq_unmask = wsp_ics_msi_unmask_irq,
+ .irq_eoi = wsp_ics_eoi,
+ .irq_set_affinity = wsp_chip_set_affinity
+};
+
+void wsp_ics_set_msi_chip(unsigned int irq)
+{
+ irq_set_chip(irq, &wsp_ics_msi);
+}
+
+void wsp_ics_set_std_chip(unsigned int irq)
+{
+ irq_set_chip(irq, &wsp_irq_chip);
+}
+#endif /* CONFIG_PCI_MSI */
diff --git a/arch/powerpc/platforms/wsp/ics.h b/arch/powerpc/platforms/wsp/ics.h
index e34d531..07b644e 100644
--- a/arch/powerpc/platforms/wsp/ics.h
+++ b/arch/powerpc/platforms/wsp/ics.h
@@ -17,4 +17,9 @@ extern void wsp_init_irq(void);
extern int wsp_ics_alloc_irq(struct device_node *dn, int num);
extern void wsp_ics_free_irq(struct device_node *dn, unsigned int irq);
+#ifdef CONFIG_PCI_MSI
+extern void wsp_ics_set_msi_chip(unsigned int irq);
+extern void wsp_ics_set_std_chip(unsigned int irq);
+#endif /* CONFIG_PCI_MSI */
+
#endif /* __ICS_H */
diff --git a/arch/powerpc/platforms/wsp/msi.c b/arch/powerpc/platforms/wsp/msi.c
new file mode 100644
index 0000000..380882f
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/msi.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2011 Michael Ellerman, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/msi.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include "msi.h"
+#include "ics.h"
+#include "wsp_pci.h"
+
+/* Magic addresses for 32 & 64-bit MSIs with hardcoded MVE 0 */
+#define MSI_ADDR_32 0xFFFF0000ul
+#define MSI_ADDR_64 0x1000000000000000ul
+
+int wsp_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+ struct pci_controller *phb;
+ struct msi_desc *entry;
+ struct msi_msg msg;
+ unsigned int virq;
+ int hwirq;
+
+ phb = pci_bus_to_host(dev->bus);
+ if (!phb)
+ return -ENOENT;
+
+ entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
+ if (entry->msi_attrib.is_64) {
+ msg.address_lo = 0;
+ msg.address_hi = MSI_ADDR_64 >> 32;
+ } else {
+ msg.address_lo = MSI_ADDR_32;
+ msg.address_hi = 0;
+ }
+
+ list_for_each_entry(entry, &dev->msi_list, list) {
+ hwirq = wsp_ics_alloc_irq(phb->dn, 1);
+ if (hwirq < 0) {
+ dev_warn(&dev->dev, "wsp_msi: hwirq alloc failed!\n");
+ return hwirq;
+ }
+
+ virq = irq_create_mapping(NULL, hwirq);
+ if (virq == NO_IRQ) {
+ dev_warn(&dev->dev, "wsp_msi: virq alloc failed!\n");
+ return -1;
+ }
+
+ dev_dbg(&dev->dev, "wsp_msi: allocated irq %#x/%#x\n",
+ hwirq, virq);
+
+ wsp_ics_set_msi_chip(virq);
+ irq_set_msi_desc(virq, entry);
+ msg.data = hwirq & XIVE_ADDR_MASK;
+ write_msi_msg(virq, &msg);
+ }
+
+ return 0;
+}
+
+void wsp_teardown_msi_irqs(struct pci_dev *dev)
+{
+ struct pci_controller *phb;
+ struct msi_desc *entry;
+ int hwirq;
+
+ phb = pci_bus_to_host(dev->bus);
+
+ dev_dbg(&dev->dev, "wsp_msi: tearing down msi irqs\n");
+
+ list_for_each_entry(entry, &dev->msi_list, list) {
+ if (entry->irq == NO_IRQ)
+ continue;
+
+ irq_set_msi_desc(entry->irq, NULL);
+ wsp_ics_set_std_chip(entry->irq);
+
+ hwirq = virq_to_hw(entry->irq);
+ /* In this order to avoid racing with irq_create_mapping() */
+ irq_dispose_mapping(entry->irq);
+ wsp_ics_free_irq(phb->dn, hwirq);
+ }
+}
+
+void wsp_setup_phb_msi(struct pci_controller *phb)
+{
+ /* Create a single MVE at offset 0 that matches everything */
+ out_be64(phb->cfg_data + PCIE_REG_IODA_ADDR, PCIE_REG_IODA_AD_TBL_MVT);
+ out_be64(phb->cfg_data + PCIE_REG_IODA_DATA0, 1ull << 63);
+
+ ppc_md.setup_msi_irqs = wsp_setup_msi_irqs;
+ ppc_md.teardown_msi_irqs = wsp_teardown_msi_irqs;
+}
diff --git a/arch/powerpc/platforms/wsp/msi.h b/arch/powerpc/platforms/wsp/msi.h
new file mode 100644
index 0000000..0ab27b7
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/msi.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2011 Michael Ellerman, IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __WSP_MSI_H
+#define __WSP_MSI_H
+
+#ifdef CONFIG_PCI_MSI
+extern void wsp_setup_phb_msi(struct pci_controller *phb);
+#else
+static inline void wsp_setup_phb_msi(struct pci_controller *phb) { }
+#endif
+
+#endif /* __WSP_MSI_H */
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/2] powerpc: poweren: pci: Add PCIe Root support to PowerEN
From: Jimi Xenidis @ 2011-08-08 22:30 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Michael Ellerman, Ian Munsie
In-Reply-To: <1312842655-21526-1-git-send-email-jimix@pobox.com>
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Based on a patch by Benjamin Herrenschmidt <benh@kernel.crashing.org>
Modernized and slightly modified to not record erros into the nvram
log since we do not have that device driver just yet.
Jimi Xenidis <jimix@pobox.com>
---
arch/powerpc/platforms/wsp/Kconfig | 3 +
arch/powerpc/platforms/wsp/Makefile | 1 +
arch/powerpc/platforms/wsp/psr2.c | 4 +
arch/powerpc/platforms/wsp/wsp.h | 3 +
arch/powerpc/platforms/wsp/wsp_pci.c | 1133 ++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/wsp/wsp_pci.h | 268 ++++++++
6 files changed, 1412 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/wsp/wsp_pci.c
create mode 100644 arch/powerpc/platforms/wsp/wsp_pci.h
diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig
index 3540293..ea2811c 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -5,6 +5,9 @@ config PPC_WSP
select PPC_SCOM
select PPC_XICS
select PPC_ICP_NATIVE
+ select PCI
+ select PPC_IO_WORKAROUNDS if PCI
+ select PPC_INDIRECT_PIO if PCI
default n
menu "WSP platform selection"
diff --git a/arch/powerpc/platforms/wsp/Makefile b/arch/powerpc/platforms/wsp/Makefile
index 095be73..84519f8 100644
--- a/arch/powerpc/platforms/wsp/Makefile
+++ b/arch/powerpc/platforms/wsp/Makefile
@@ -4,3 +4,4 @@ obj-y += setup.o ics.o
obj-$(CONFIG_PPC_PSR2) += psr2.o opb_pic.o
obj-$(CONFIG_PPC_WSP) += scom_wsp.o
obj-$(CONFIG_SMP) += smp.o scom_smp.o
+obj-$(CONFIG_PCI) += wsp_pci.o
diff --git a/arch/powerpc/platforms/wsp/psr2.c b/arch/powerpc/platforms/wsp/psr2.c
index 40f2891..166f2e4 100644
--- a/arch/powerpc/platforms/wsp/psr2.c
+++ b/arch/powerpc/platforms/wsp/psr2.c
@@ -63,6 +63,10 @@ static void __init psr2_setup_arch(void)
#ifdef CONFIG_SMP
a2_setup_smp();
#endif
+#ifdef CONFIG_PCI
+ wsp_setup_pci();
+#endif
+
}
static int __init psr2_probe(void)
diff --git a/arch/powerpc/platforms/wsp/wsp.h b/arch/powerpc/platforms/wsp/wsp.h
index 7c3e087..3347981 100644
--- a/arch/powerpc/platforms/wsp/wsp.h
+++ b/arch/powerpc/platforms/wsp/wsp.h
@@ -3,6 +3,9 @@
#include <asm/wsp.h>
+/* Devtree compatible strings for major devices */
+#define PCIE_COMPATIBLE "ibm,wsp-pciex"
+
extern void wsp_setup_pci(void);
extern void scom_init_wsp(void);
diff --git a/arch/powerpc/platforms/wsp/wsp_pci.c b/arch/powerpc/platforms/wsp/wsp_pci.c
new file mode 100644
index 0000000..e0262cd
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/wsp_pci.c
@@ -0,0 +1,1133 @@
+/*
+ * Copyright 2010 Ben Herrenschmidt, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#define DEBUG
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/debugfs.h>
+
+#include <asm/sections.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#include <asm/machdep.h>
+#include <asm/ppc-pci.h>
+#include <asm/iommu.h>
+#include <asm/io-workarounds.h>
+
+#include "wsp.h"
+#include "wsp_pci.h"
+#include "msi.h"
+
+
+/* Max number of TVTs for one table. Only 32-bit tables can use
+ * multiple TVTs and so the max currently supported is thus 8
+ * since only 2G of DMA space is supported
+ */
+#define MAX_TABLE_TVT_COUNT 8
+
+struct wsp_dma_table {
+ struct list_head link;
+ struct iommu_table table;
+ struct wsp_phb *phb;
+ struct page *tces[MAX_TABLE_TVT_COUNT];
+};
+
+/* We support DMA regions from 0...2G in 32bit space (no support for
+ * 64-bit DMA just yet). Each device gets a separate TCE table (TVT
+ * entry) with validation enabled (though not supported by SimiCS
+ * just yet).
+ *
+ * To simplify things, we divide this 2G space into N regions based
+ * on the constant below which could be turned into a tunable eventually
+ *
+ * We then assign dynamically those regions to devices as they show up.
+ *
+ * We use a bitmap as an allocator for these.
+ *
+ * Tables are allocated/created dynamically as devices are discovered,
+ * multiple TVT entries are used if needed
+ *
+ * When 64-bit DMA support is added we should simply use a separate set
+ * of larger regions (the HW supports 64 TVT entries). We can
+ * additionally create a bypass region in 64-bit space for performances
+ * though that would have a cost in term of security.
+ *
+ * If you set NUM_DMA32_REGIONS to 1, then a single table is shared
+ * for all devices and bus/dev/fn validation is disabled
+ *
+ * Note that a DMA32 region cannot be smaller than 256M so the max
+ * supported here for now is 8. We don't yet support sharing regions
+ * between multiple devices so the max number of devices supported
+ * is MAX_TABLE_TVT_COUNT.
+ */
+#define NUM_DMA32_REGIONS 1
+
+struct wsp_phb {
+ struct pci_controller *hose;
+
+ /* Lock controlling access to the list of dma tables.
+ * It does -not- protect against dma_* operations on
+ * those tables, those should be stopped before an entry
+ * is removed from the list.
+ *
+ * The lock is also used for error handling operations
+ */
+ spinlock_t lock;
+ struct list_head dma_tables;
+ unsigned long dma32_map;
+ unsigned long dma32_base;
+ unsigned int dma32_num_regions;
+ unsigned long dma32_region_size;
+
+ /* Debugfs stuff */
+ struct dentry *ddir;
+
+ struct list_head all;
+};
+static LIST_HEAD(wsp_phbs);
+
+//#define cfg_debug(fmt...) pr_debug(fmt)
+#define cfg_debug(fmt...)
+
+
+static int wsp_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 *val)
+{
+ struct pci_controller *hose;
+ int suboff;
+ u64 addr;
+
+ hose = pci_bus_to_host(bus);
+ if (hose == NULL)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (offset >= 0x1000)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ addr = PCIE_REG_CA_ENABLE |
+ ((u64)bus->number) << PCIE_REG_CA_BUS_SHIFT |
+ ((u64)devfn) << PCIE_REG_CA_FUNC_SHIFT |
+ ((u64)offset & ~3) << PCIE_REG_CA_REG_SHIFT;
+ suboff = offset & 3;
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+
+ switch (len) {
+ case 1:
+ addr |= (0x8ul >> suboff) << PCIE_REG_CA_BE_SHIFT;
+ out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
+ *val = (in_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA)
+ >> (suboff << 3)) & 0xff;
+ cfg_debug("read 1 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%02x\n",
+ bus->number, devfn >> 3, devfn & 7,
+ offset, suboff, addr, *val);
+ break;
+ case 2:
+ addr |= (0xcul >> suboff) << PCIE_REG_CA_BE_SHIFT;
+ out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
+ *val = (in_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA)
+ >> (suboff << 3)) & 0xffff;
+ cfg_debug("read 2 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%04x\n",
+ bus->number, devfn >> 3, devfn & 7,
+ offset, suboff, addr, *val);
+ break;
+ default:
+ addr |= 0xful << PCIE_REG_CA_BE_SHIFT;
+ out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
+ *val = in_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA);
+ cfg_debug("read 4 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%08x\n",
+ bus->number, devfn >> 3, devfn & 7,
+ offset, suboff, addr, *val);
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int wsp_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
+ int offset, int len, u32 val)
+{
+ struct pci_controller *hose;
+ int suboff;
+ u64 addr;
+
+ hose = pci_bus_to_host(bus);
+ if (hose == NULL)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (offset >= 0x1000)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ addr = PCIE_REG_CA_ENABLE |
+ ((u64)bus->number) << PCIE_REG_CA_BUS_SHIFT |
+ ((u64)devfn) << PCIE_REG_CA_FUNC_SHIFT |
+ ((u64)offset & ~3) << PCIE_REG_CA_REG_SHIFT;
+ suboff = offset & 3;
+
+ /*
+ * Note: the caller has already checked that offset is
+ * suitably aligned and that len is 1, 2 or 4.
+ */
+ switch (len) {
+ case 1:
+ addr |= (0x8ul >> suboff) << PCIE_REG_CA_BE_SHIFT;
+ val <<= suboff << 3;
+ out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
+ out_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA, val);
+ cfg_debug("write 1 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%02x\n",
+ bus->number, devfn >> 3, devfn & 7,
+ offset, suboff, addr, val);
+ break;
+ case 2:
+ addr |= (0xcul >> suboff) << PCIE_REG_CA_BE_SHIFT;
+ val <<= suboff << 3;
+ out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
+ out_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA, val);
+ cfg_debug("write 2 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%04x\n",
+ bus->number, devfn >> 3, devfn & 7,
+ offset, suboff, addr, val);
+ break;
+ default:
+ addr |= 0xful << PCIE_REG_CA_BE_SHIFT;
+ out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
+ out_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA, val);
+ cfg_debug("write 4 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%08x\n",
+ bus->number, devfn >> 3, devfn & 7,
+ offset, suboff, addr, val);
+ break;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops wsp_pcie_pci_ops =
+{
+ .read = wsp_pcie_read_config,
+ .write = wsp_pcie_write_config,
+};
+
+#define TCE_SHIFT 12
+#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
+#define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
+#define TCE_PCI_READ 0x1 /* read from PCI allowed */
+#define TCE_RPN_MASK 0x3fffffffffful /* 42-bit RPN (4K pages) */
+#define TCE_RPN_SHIFT 12
+
+//#define dma_debug(fmt...) pr_debug(fmt)
+#define dma_debug(fmt...)
+
+static int tce_build_wsp(struct iommu_table *tbl, long index, long npages,
+ unsigned long uaddr, enum dma_data_direction direction,
+ struct dma_attrs *attrs)
+{
+ struct wsp_dma_table *ptbl = container_of(tbl,
+ struct wsp_dma_table,
+ table);
+ u64 proto_tce;
+ u64 *tcep;
+ u64 rpn;
+
+ proto_tce = TCE_PCI_READ;
+#ifdef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
+ proto_tce |= TCE_PCI_WRITE;
+#else
+ if (direction != DMA_TO_DEVICE)
+ proto_tce |= TCE_PCI_WRITE;
+#endif
+
+ /* XXX Make this faster by factoring out the page address for
+ * within a TCE table
+ */
+ while (npages--) {
+ /* We don't use it->base as the table can be scattered */
+ tcep = (u64 *)page_address(ptbl->tces[index >> 16]);
+ tcep += (index & 0xffff);
+
+ /* can't move this out since we might cross LMB boundary */
+ rpn = __pa(uaddr) >> TCE_SHIFT;
+ *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
+
+ dma_debug("[DMA] TCE %p set to 0x%016llx (dma addr: 0x%lx)\n",
+ tcep, *tcep, (tbl->it_offset + index) << IOMMU_PAGE_SHIFT);
+
+ uaddr += TCE_PAGE_SIZE;
+ index++;
+ }
+ return 0;
+}
+
+static void tce_free_wsp(struct iommu_table *tbl, long index, long npages)
+{
+ struct wsp_dma_table *ptbl = container_of(tbl,
+ struct wsp_dma_table,
+ table);
+#ifndef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
+ struct pci_controller *hose = ptbl->phb->hose;
+#endif
+ u64 *tcep;
+
+ /* XXX Make this faster by factoring out the page address for
+ * within a TCE table. Also use line-kill option to kill multiple
+ * TCEs at once
+ */
+ while (npages--) {
+ /* We don't use it->base as the table can be scattered */
+ tcep = (u64 *)page_address(ptbl->tces[index >> 16]);
+ tcep += (index & 0xffff);
+ dma_debug("[DMA] TCE %p cleared\n", tcep);
+ *tcep = 0;
+#ifndef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
+ /* Don't write there since it would pollute other MMIO accesses */
+ out_be64(hose->cfg_data + PCIE_REG_TCE_KILL,
+ PCIE_REG_TCEKILL_SINGLE | PCIE_REG_TCEKILL_PS_4K |
+ (__pa(tcep) & PCIE_REG_TCEKILL_ADDR_MASK));
+#endif
+ index++;
+ }
+}
+
+static struct wsp_dma_table *wsp_pci_create_dma32_table(struct wsp_phb *phb,
+ unsigned int region,
+ struct pci_dev *validate)
+{
+ struct pci_controller *hose = phb->hose;
+ unsigned long size = phb->dma32_region_size;
+ unsigned long addr = phb->dma32_region_size * region + phb->dma32_base;
+ struct wsp_dma_table *tbl;
+ int tvts_per_table, i, tvt, nid;
+ unsigned long flags;
+
+ nid = of_node_to_nid(phb->hose->dn);
+
+ /* Calculate how many TVTs are needed */
+ tvts_per_table = size / 0x10000000;
+ if (tvts_per_table == 0)
+ tvts_per_table = 1;
+
+ /* Calculate the base TVT index. We know all tables have the same
+ * size so we just do a simple multiply here
+ */
+ tvt = region * tvts_per_table;
+
+ pr_debug(" Region : %d\n", region);
+ pr_debug(" DMA range : 0x%08lx..0x%08lx\n", addr, addr + size - 1);
+ pr_debug(" Number of TVTs : %d\n", tvts_per_table);
+ pr_debug(" Base TVT : %d\n", tvt);
+ pr_debug(" Node : %d\n", nid);
+
+ tbl = kzalloc_node(sizeof(struct wsp_dma_table), GFP_KERNEL, nid);
+ if (!tbl)
+ return ERR_PTR(-ENOMEM);
+ tbl->phb = phb;
+
+ /* Create as many TVTs as needed, each represents 256M at most */
+ for (i = 0; i < tvts_per_table; i++) {
+ u64 tvt_data1, tvt_data0;
+
+ /* Allocate table. We use a 4K TCE size for now always so
+ * one table is always 8 * (258M / 4K) == 512K
+ */
+ tbl->tces[i] = alloc_pages_node(nid, GFP_KERNEL, get_order(0x80000));
+ if (tbl->tces[i] == NULL)
+ goto fail;
+ memset(page_address(tbl->tces[i]), 0, 0x80000);
+
+ pr_debug(" TCE table %d at : %p\n", i, page_address(tbl->tces[i]));
+
+ /* Table size. We currently set it to be the whole 256M region */
+ tvt_data0 = 2ull << IODA_TVT0_TCE_TABLE_SIZE_SHIFT;
+ /* IO page size set to 4K */
+ tvt_data1 = 1ull << IODA_TVT1_IO_PAGE_SIZE_SHIFT;
+ /* Shift in the address */
+ tvt_data0 |= __pa(page_address(tbl->tces[i])) << IODA_TVT0_TTA_SHIFT;
+
+ /* Validation stuff. We only validate fully bus/dev/fn for now
+ * one day maybe we can group devices but that isn't the case
+ * at the moment
+ */
+ if (validate) {
+ tvt_data0 |= IODA_TVT0_BUSNUM_VALID_MASK;
+ tvt_data0 |= validate->bus->number;
+ tvt_data1 |= IODA_TVT1_DEVNUM_VALID;
+ tvt_data1 |= ((u64)PCI_SLOT(validate->devfn))
+ << IODA_TVT1_DEVNUM_VALUE_SHIFT;
+ tvt_data1 |= IODA_TVT1_FUNCNUM_VALID;
+ tvt_data1 |= ((u64)PCI_FUNC(validate->devfn))
+ << IODA_TVT1_FUNCNUM_VALUE_SHIFT;
+ }
+
+ /* XX PE number is always 0 for now */
+
+ /* Program the values using the PHB lock */
+ spin_lock_irqsave(&phb->lock, flags);
+ out_be64(hose->cfg_data + PCIE_REG_IODA_ADDR,
+ (tvt + i) | PCIE_REG_IODA_AD_TBL_TVT);
+ out_be64(hose->cfg_data + PCIE_REG_IODA_DATA1, tvt_data1);
+ out_be64(hose->cfg_data + PCIE_REG_IODA_DATA0, tvt_data0);
+ spin_unlock_irqrestore(&phb->lock, flags);
+ }
+
+ /* Init bits and pieces */
+ tbl->table.it_blocksize = 16;
+ tbl->table.it_offset = addr >> IOMMU_PAGE_SHIFT;
+ tbl->table.it_size = size >> IOMMU_PAGE_SHIFT;
+
+ /*
+ * It's already blank but we clear it anyway.
+ * Consider an aditiona interface that makes cleaing optional
+ */
+ iommu_init_table(&tbl->table, nid);
+
+ list_add(&tbl->link, &phb->dma_tables);
+ return tbl;
+
+ fail:
+ pr_debug(" Failed to allocate a 256M TCE table !\n");
+ for (i = 0; i < tvts_per_table; i++)
+ if (tbl->tces[i])
+ __free_pages(tbl->tces[i], get_order(0x80000));
+ kfree(tbl);
+ return ERR_PTR(-ENOMEM);
+}
+
+static void __devinit wsp_pci_dma_dev_setup(struct pci_dev *pdev)
+{
+ struct dev_archdata *archdata = &pdev->dev.archdata;
+ struct pci_controller *hose = pci_bus_to_host(pdev->bus);
+ struct wsp_phb *phb = hose->private_data;
+ struct wsp_dma_table *table = NULL;
+ unsigned long flags;
+ int i;
+
+ /* Don't assign an iommu table to a bridge */
+ if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
+ return;
+
+ pr_debug("%s: Setting up DMA...\n", pci_name(pdev));
+
+ spin_lock_irqsave(&phb->lock, flags);
+
+ /* If only one region, check if it already exist */
+ if (phb->dma32_num_regions == 1) {
+ spin_unlock_irqrestore(&phb->lock, flags);
+ if (list_empty(&phb->dma_tables))
+ table = wsp_pci_create_dma32_table(phb, 0, NULL);
+ else
+ table = list_first_entry(&phb->dma_tables,
+ struct wsp_dma_table,
+ link);
+ } else {
+ /* else find a free region */
+ for (i = 0; i < phb->dma32_num_regions && !table; i++) {
+ if (__test_and_set_bit(i, &phb->dma32_map))
+ continue;
+ spin_unlock_irqrestore(&phb->lock, flags);
+ table = wsp_pci_create_dma32_table(phb, i, pdev);
+ }
+ }
+
+ /* Check if we got an error */
+ if (IS_ERR(table)) {
+ pr_err("%s: Failed to create DMA table, err %ld !\n",
+ pci_name(pdev), PTR_ERR(table));
+ return;
+ }
+
+ /* Or a valid table */
+ if (table) {
+ pr_info("%s: Setup iommu: 32-bit DMA region 0x%08lx..0x%08lx\n",
+ pci_name(pdev),
+ table->table.it_offset << IOMMU_PAGE_SHIFT,
+ (table->table.it_offset << IOMMU_PAGE_SHIFT)
+ + phb->dma32_region_size - 1);
+ archdata->dma_data.iommu_table_base = &table->table;
+ return;
+ }
+
+ /* Or no room */
+ spin_unlock_irqrestore(&phb->lock, flags);
+ pr_err("%s: Out of DMA space !\n", pci_name(pdev));
+}
+
+static void __init wsp_pcie_configure_hw(struct pci_controller *hose)
+{
+ u64 val;
+ int i;
+
+#define DUMP_REG(x) \
+ pr_debug("%-30s : 0x%016llx\n", #x, in_be64(hose->cfg_data + x))
+
+#ifdef CONFIG_WSP_DD1_WORKAROUND_BAD_PCIE_CLASS
+ /* WSP DD1 has a bogus class code by default in the PCI-E
+ * root complex's built-in P2P bridge */
+ val = in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1);
+ pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", val);
+ out_be64(hose->cfg_data + PCIE_REG_SYS_CFG1,
+ (val & ~PCIE_REG_SYS_CFG1_CLASS_CODE) | (PCI_CLASS_BRIDGE_PCI << 8));
+ pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1));
+#endif /* CONFIG_WSP_DD1_WORKAROUND_BAD_PCIE_CLASS */
+
+#ifdef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
+ /* XXX Disable TCE caching, it doesn't work on DD1 */
+ out_be64(hose->cfg_data + 0xe50,
+ in_be64(hose->cfg_data + 0xe50) | (3ull << 62));
+ printk("PCI-E DEBUG CONTROL 5 = 0x%llx\n", in_be64(hose->cfg_data + 0xe50));
+#endif
+
+ /* Configure M32A and IO. IO is hard wired to be 1M for now */
+ out_be64(hose->cfg_data + PCIE_REG_IO_BASE_ADDR, hose->io_base_phys);
+ out_be64(hose->cfg_data + PCIE_REG_IO_BASE_MASK,
+ (~(hose->io_resource.end - hose->io_resource.start)) &
+ 0x3fffffff000ul);
+ out_be64(hose->cfg_data + PCIE_REG_IO_START_ADDR, 0 | 1);
+
+ out_be64(hose->cfg_data + PCIE_REG_M32A_BASE_ADDR,
+ hose->mem_resources[0].start);
+ printk("Want to write to M32A_BASE_MASK : 0x%llx\n",
+ (~(hose->mem_resources[0].end -
+ hose->mem_resources[0].start)) & 0x3ffffff0000ul);
+ out_be64(hose->cfg_data + PCIE_REG_M32A_BASE_MASK,
+ (~(hose->mem_resources[0].end -
+ hose->mem_resources[0].start)) & 0x3ffffff0000ul);
+ out_be64(hose->cfg_data + PCIE_REG_M32A_START_ADDR,
+ (hose->mem_resources[0].start - hose->pci_mem_offset) | 1);
+
+ /* Clear all TVT entries
+ *
+ * XX Might get TVT count from device-tree
+ */
+ for (i = 0; i < IODA_TVT_COUNT; i++) {
+ out_be64(hose->cfg_data + PCIE_REG_IODA_ADDR,
+ PCIE_REG_IODA_AD_TBL_TVT | i);
+ out_be64(hose->cfg_data + PCIE_REG_IODA_DATA1, 0);
+ out_be64(hose->cfg_data + PCIE_REG_IODA_DATA0, 0);
+ }
+
+ /* Kill the TCE cache */
+ out_be64(hose->cfg_data + PCIE_REG_PHB_CONFIG,
+ in_be64(hose->cfg_data + PCIE_REG_PHB_CONFIG) |
+ PCIE_REG_PHBC_64B_TCE_EN);
+
+ /* Enable 32 & 64-bit MSIs, IO space and M32A */
+ val = PCIE_REG_PHBC_32BIT_MSI_EN |
+ PCIE_REG_PHBC_IO_EN |
+ PCIE_REG_PHBC_64BIT_MSI_EN |
+ PCIE_REG_PHBC_M32A_EN;
+ if (iommu_is_off)
+ val |= PCIE_REG_PHBC_DMA_XLATE_BYPASS;
+ pr_debug("Will write config: 0x%llx\n", val);
+ out_be64(hose->cfg_data + PCIE_REG_PHB_CONFIG, val);
+
+ /* Enable error reporting */
+ out_be64(hose->cfg_data + 0xe00,
+ in_be64(hose->cfg_data + 0xe00) | 0x0008000000000000ull);
+
+ /* Mask an error that's generated when doing config space probe
+ *
+ * XXX Maybe we should only mask it around config space cycles... that or
+ * ignore it when we know we had a config space cycle recently ?
+ */
+ out_be64(hose->cfg_data + PCIE_REG_DMA_ERR_STATUS_MASK, 0x8000000000000000ull);
+ out_be64(hose->cfg_data + PCIE_REG_DMA_ERR1_STATUS_MASK, 0x8000000000000000ull);
+
+ /* Enable UTL errors, for now, all of them got to UTL irq 1
+ *
+ * We similarily mask one UTL error caused apparently during normal
+ * probing. We also mask the link up error
+ */
+ out_be64(hose->cfg_data + PCIE_UTL_SYS_BUS_AGENT_ERR_SEV, 0);
+ out_be64(hose->cfg_data + PCIE_UTL_RC_ERR_SEVERITY, 0);
+ out_be64(hose->cfg_data + PCIE_UTL_PCIE_PORT_ERROR_SEV, 0);
+ out_be64(hose->cfg_data + PCIE_UTL_SYS_BUS_AGENT_IRQ_EN, 0xffffffff00000000ull);
+ out_be64(hose->cfg_data + PCIE_UTL_PCIE_PORT_IRQ_EN, 0xff5fffff00000000ull);
+ out_be64(hose->cfg_data + PCIE_UTL_EP_ERR_IRQ_EN, 0xffffffff00000000ull);
+
+ DUMP_REG(PCIE_REG_IO_BASE_ADDR);
+ DUMP_REG(PCIE_REG_IO_BASE_MASK);
+ DUMP_REG(PCIE_REG_IO_START_ADDR);
+ DUMP_REG(PCIE_REG_M32A_BASE_ADDR);
+ DUMP_REG(PCIE_REG_M32A_BASE_MASK);
+ DUMP_REG(PCIE_REG_M32A_START_ADDR);
+ DUMP_REG(PCIE_REG_M32B_BASE_ADDR);
+ DUMP_REG(PCIE_REG_M32B_BASE_MASK);
+ DUMP_REG(PCIE_REG_M32B_START_ADDR);
+ DUMP_REG(PCIE_REG_M64_BASE_ADDR);
+ DUMP_REG(PCIE_REG_M64_BASE_MASK);
+ DUMP_REG(PCIE_REG_M64_START_ADDR);
+ DUMP_REG(PCIE_REG_PHB_CONFIG);
+}
+
+static void wsp_pci_wait_io_idle(struct wsp_phb *phb, unsigned long port)
+{
+ u64 val;
+ int i;
+
+ for (i = 0; i < 10000; i++) {
+ val = in_be64(phb->hose->cfg_data + 0xe08);
+ if ((val & 0x1900000000000000ull) == 0x0100000000000000ull)
+ return;
+ udelay(1);
+ }
+ pr_warning("PCI IO timeout on domain %d port 0x%lx\n",
+ phb->hose->global_number, port);
+}
+
+#define DEF_PCI_AC_RET_pio(name, ret, at, al, aa) \
+static ret wsp_pci_##name at \
+{ \
+ struct iowa_bus *bus; \
+ struct wsp_phb *phb; \
+ unsigned long flags; \
+ ret rval; \
+ bus = iowa_pio_find_bus(aa); \
+ WARN_ON(!bus); \
+ phb = bus->private; \
+ spin_lock_irqsave(&phb->lock, flags); \
+ wsp_pci_wait_io_idle(phb, aa); \
+ rval = __do_##name al; \
+ spin_unlock_irqrestore(&phb->lock, flags); \
+ return rval; \
+}
+
+#define DEF_PCI_AC_NORET_pio(name, at, al, aa) \
+static void wsp_pci_##name at \
+{ \
+ struct iowa_bus *bus; \
+ struct wsp_phb *phb; \
+ unsigned long flags; \
+ bus = iowa_pio_find_bus(aa); \
+ WARN_ON(!bus); \
+ phb = bus->private; \
+ spin_lock_irqsave(&phb->lock, flags); \
+ wsp_pci_wait_io_idle(phb, aa); \
+ __do_##name al; \
+ spin_unlock_irqrestore(&phb->lock, flags); \
+}
+
+#define DEF_PCI_AC_RET_mem(name, ret, at, al, aa)
+#define DEF_PCI_AC_NORET_mem(name, at, al, aa)
+
+#define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
+ DEF_PCI_AC_RET_##space(name, ret, at, al, aa)
+
+#define DEF_PCI_AC_NORET(name, at, al, space, aa) \
+ DEF_PCI_AC_NORET_##space(name, at, al, aa) \
+
+
+#include <asm/io-defs.h>
+
+#undef DEF_PCI_AC_RET
+#undef DEF_PCI_AC_NORET
+
+static struct ppc_pci_io wsp_pci_iops = {
+ .inb = wsp_pci_inb,
+ .inw = wsp_pci_inw,
+ .inl = wsp_pci_inl,
+ .outb = wsp_pci_outb,
+ .outw = wsp_pci_outw,
+ .outl = wsp_pci_outl,
+ .insb = wsp_pci_insb,
+ .insw = wsp_pci_insw,
+ .insl = wsp_pci_insl,
+ .outsb = wsp_pci_outsb,
+ .outsw = wsp_pci_outsw,
+ .outsl = wsp_pci_outsl,
+};
+
+static int __init wsp_setup_one_phb(struct device_node *np)
+{
+ struct pci_controller *hose;
+ struct wsp_phb *phb;
+
+ pr_info("PCI: Setting up PCIe host bridge 0x%s\n", np->full_name);
+
+ phb = zalloc_maybe_bootmem(sizeof(struct wsp_phb), GFP_KERNEL);
+ if (!phb)
+ return -ENOMEM;
+ hose = pcibios_alloc_controller(np);
+ if (!hose) {
+ /* Can't really free the phb */
+ return -ENOMEM;
+ }
+ hose->private_data = phb;
+ phb->hose = hose;
+
+ INIT_LIST_HEAD(&phb->dma_tables);
+ spin_lock_init(&phb->lock);
+
+ /* XXX Use bus-range property ? */
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* We use cfg_data as the address for the whole bridge MMIO space
+ */
+ hose->cfg_data = of_iomap(hose->dn, 0);
+
+ pr_debug("PCIe registers mapped at 0x%p\n", hose->cfg_data);
+
+ /* Get the ranges of the device-tree */
+ pci_process_bridge_OF_ranges(hose, np, 0);
+
+ /* XXX Force re-assigning of everything for now */
+ pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC |
+ PCI_ENABLE_PROC_DOMAINS);
+ pci_probe_only = 0;
+
+ /* Calculate how the TCE space is divided */
+ phb->dma32_base = 0;
+ phb->dma32_num_regions = NUM_DMA32_REGIONS;
+ if (phb->dma32_num_regions > MAX_TABLE_TVT_COUNT) {
+ pr_warning("IOMMU: Clamped to %d DMA32 regions\n",
+ MAX_TABLE_TVT_COUNT);
+ phb->dma32_num_regions = MAX_TABLE_TVT_COUNT;
+ }
+ phb->dma32_region_size = 0x80000000 / phb->dma32_num_regions;
+
+ BUG_ON(!is_power_of_2(phb->dma32_region_size));
+
+ /* Setup config ops */
+ hose->ops = &wsp_pcie_pci_ops;
+
+ /* Configure the HW */
+ wsp_pcie_configure_hw(hose);
+
+ /* Instanciate IO workarounds */
+ iowa_register_bus(hose, &wsp_pci_iops, NULL, phb);
+#ifdef CONFIG_PCI_MSI
+ wsp_setup_phb_msi(hose);
+#endif
+
+ /* Add to global list */
+ list_add(&phb->all, &wsp_phbs);
+
+ return 0;
+}
+
+void __init wsp_setup_pci(void)
+{
+ struct device_node *np;
+ int rc;
+
+ /* Find host bridges */
+ for_each_compatible_node(np, "pciex", PCIE_COMPATIBLE) {
+ rc = wsp_setup_one_phb(np);
+ if (rc)
+ pr_err("Failed to setup PCIe bridge %s, rc=%d\n",
+ np->full_name, rc);
+ }
+
+ /* Establish device-tree linkage */
+ pci_devs_phb_init();
+
+ /* Set DMA ops to use TCEs */
+ if (iommu_is_off) {
+ pr_info("PCI-E: Disabled TCEs, using direct DMA\n");
+ set_pci_dma_ops(&dma_direct_ops);
+ } else {
+ ppc_md.pci_dma_dev_setup = wsp_pci_dma_dev_setup;
+ ppc_md.tce_build = tce_build_wsp;
+ ppc_md.tce_free = tce_free_wsp;
+ set_pci_dma_ops(&dma_iommu_ops);
+ }
+}
+
+#define err_debug(fmt...) pr_debug(fmt)
+//#define err_debug(fmt...)
+
+static int __init wsp_pci_get_err_irq_no_dt(struct device_node *np)
+{
+ const u32 *prop;
+ int hw_irq;
+
+ /* Ok, no interrupts property, let's try to find our child P2P */
+ np = of_get_next_child(np, NULL);
+ if (np == NULL)
+ return 0;
+
+ /* Grab it's interrupt map */
+ prop = of_get_property(np, "interrupt-map", NULL);
+ if (prop == NULL)
+ return 0;
+
+ /* Grab one of the interrupts in there, keep the low 4 bits */
+ hw_irq = prop[5] & 0xf;
+
+ /* 0..4 for PHB 0 and 5..9 for PHB 1 */
+ if (hw_irq < 5)
+ hw_irq = 4;
+ else
+ hw_irq = 9;
+ hw_irq |= prop[5] & ~0xf;
+
+ err_debug("PCI: Using 0x%x as error IRQ for %s\n",
+ hw_irq, np->parent->full_name);
+ return irq_create_mapping(NULL, hw_irq);
+}
+
+static const struct {
+ u32 offset;
+ const char *name;
+} wsp_pci_regs[] = {
+#define DREG(x) { PCIE_REG_##x, #x }
+#define DUTL(x) { PCIE_UTL_##x, "UTL_" #x }
+ /* Architected registers except CONFIG_ and IODA
+ * to avoid side effects
+ */
+ DREG(DMA_CHAN_STATUS),
+ DREG(CPU_LOADSTORE_STATUS),
+ DREG(LOCK0),
+ DREG(LOCK1),
+ DREG(PHB_CONFIG),
+ DREG(IO_BASE_ADDR),
+ DREG(IO_BASE_MASK),
+ DREG(IO_START_ADDR),
+ DREG(M32A_BASE_ADDR),
+ DREG(M32A_BASE_MASK),
+ DREG(M32A_START_ADDR),
+ DREG(M32B_BASE_ADDR),
+ DREG(M32B_BASE_MASK),
+ DREG(M32B_START_ADDR),
+ DREG(M64_BASE_ADDR),
+ DREG(M64_BASE_MASK),
+ DREG(M64_START_ADDR),
+ DREG(TCE_KILL),
+ DREG(LOCK2),
+ DREG(PHB_GEN_CAP),
+ DREG(PHB_TCE_CAP),
+ DREG(PHB_IRQ_CAP),
+ DREG(PHB_EEH_CAP),
+ DREG(PAPR_ERR_INJ_CONTROL),
+ DREG(PAPR_ERR_INJ_ADDR),
+ DREG(PAPR_ERR_INJ_MASK),
+
+ /* UTL core regs */
+ DUTL(SYS_BUS_CONTROL),
+ DUTL(STATUS),
+ DUTL(SYS_BUS_AGENT_STATUS),
+ DUTL(SYS_BUS_AGENT_ERR_SEV),
+ DUTL(SYS_BUS_AGENT_IRQ_EN),
+ DUTL(SYS_BUS_BURST_SZ_CONF),
+ DUTL(REVISION_ID),
+ DUTL(OUT_POST_HDR_BUF_ALLOC),
+ DUTL(OUT_POST_DAT_BUF_ALLOC),
+ DUTL(IN_POST_HDR_BUF_ALLOC),
+ DUTL(IN_POST_DAT_BUF_ALLOC),
+ DUTL(OUT_NP_BUF_ALLOC),
+ DUTL(IN_NP_BUF_ALLOC),
+ DUTL(PCIE_TAGS_ALLOC),
+ DUTL(GBIF_READ_TAGS_ALLOC),
+
+ DUTL(PCIE_PORT_CONTROL),
+ DUTL(PCIE_PORT_STATUS),
+ DUTL(PCIE_PORT_ERROR_SEV),
+ DUTL(PCIE_PORT_IRQ_EN),
+ DUTL(RC_STATUS),
+ DUTL(RC_ERR_SEVERITY),
+ DUTL(RC_IRQ_EN),
+ DUTL(EP_STATUS),
+ DUTL(EP_ERR_SEVERITY),
+ DUTL(EP_ERR_IRQ_EN),
+ DUTL(PCI_PM_CTRL1),
+ DUTL(PCI_PM_CTRL2),
+
+ /* PCIe stack regs */
+ DREG(SYSTEM_CONFIG1),
+ DREG(SYSTEM_CONFIG2),
+ DREG(EP_SYSTEM_CONFIG),
+ DREG(EP_FLR),
+ DREG(EP_BAR_CONFIG),
+ DREG(LINK_CONFIG),
+ DREG(PM_CONFIG),
+ DREG(DLP_CONTROL),
+ DREG(DLP_STATUS),
+ DREG(ERR_REPORT_CONTROL),
+ DREG(SLOT_CONTROL1),
+ DREG(SLOT_CONTROL2),
+ DREG(UTL_CONFIG),
+ DREG(BUFFERS_CONFIG),
+ DREG(ERROR_INJECT),
+ DREG(SRIOV_CONFIG),
+ DREG(PF0_SRIOV_STATUS),
+ DREG(PF1_SRIOV_STATUS),
+ DREG(PORT_NUMBER),
+ DREG(POR_SYSTEM_CONFIG),
+
+ /* Internal logic regs */
+ DREG(PHB_VERSION),
+ DREG(RESET),
+ DREG(PHB_CONTROL),
+ DREG(PHB_TIMEOUT_CONTROL1),
+ DREG(PHB_QUIESCE_DMA),
+ DREG(PHB_DMA_READ_TAG_ACTV),
+ DREG(PHB_TCE_READ_TAG_ACTV),
+
+ /* FIR registers */
+ DREG(LEM_FIR_ACCUM),
+ DREG(LEM_FIR_AND_MASK),
+ DREG(LEM_FIR_OR_MASK),
+ DREG(LEM_ACTION0),
+ DREG(LEM_ACTION1),
+ DREG(LEM_ERROR_MASK),
+ DREG(LEM_ERROR_AND_MASK),
+ DREG(LEM_ERROR_OR_MASK),
+
+ /* Error traps registers */
+ DREG(PHB_ERR_STATUS),
+ DREG(PHB_ERR_STATUS),
+ DREG(PHB_ERR1_STATUS),
+ DREG(PHB_ERR_INJECT),
+ DREG(PHB_ERR_LEM_ENABLE),
+ DREG(PHB_ERR_IRQ_ENABLE),
+ DREG(PHB_ERR_FREEZE_ENABLE),
+ DREG(PHB_ERR_SIDE_ENABLE),
+ DREG(PHB_ERR_LOG_0),
+ DREG(PHB_ERR_LOG_1),
+ DREG(PHB_ERR_STATUS_MASK),
+ DREG(PHB_ERR1_STATUS_MASK),
+ DREG(MMIO_ERR_STATUS),
+ DREG(MMIO_ERR1_STATUS),
+ DREG(MMIO_ERR_INJECT),
+ DREG(MMIO_ERR_LEM_ENABLE),
+ DREG(MMIO_ERR_IRQ_ENABLE),
+ DREG(MMIO_ERR_FREEZE_ENABLE),
+ DREG(MMIO_ERR_SIDE_ENABLE),
+ DREG(MMIO_ERR_LOG_0),
+ DREG(MMIO_ERR_LOG_1),
+ DREG(MMIO_ERR_STATUS_MASK),
+ DREG(MMIO_ERR1_STATUS_MASK),
+ DREG(DMA_ERR_STATUS),
+ DREG(DMA_ERR1_STATUS),
+ DREG(DMA_ERR_INJECT),
+ DREG(DMA_ERR_LEM_ENABLE),
+ DREG(DMA_ERR_IRQ_ENABLE),
+ DREG(DMA_ERR_FREEZE_ENABLE),
+ DREG(DMA_ERR_SIDE_ENABLE),
+ DREG(DMA_ERR_LOG_0),
+ DREG(DMA_ERR_LOG_1),
+ DREG(DMA_ERR_STATUS_MASK),
+ DREG(DMA_ERR1_STATUS_MASK),
+
+ /* Debug and Trace registers */
+ DREG(PHB_DEBUG_CONTROL0),
+ DREG(PHB_DEBUG_STATUS0),
+ DREG(PHB_DEBUG_CONTROL1),
+ DREG(PHB_DEBUG_STATUS1),
+ DREG(PHB_DEBUG_CONTROL2),
+ DREG(PHB_DEBUG_STATUS2),
+ DREG(PHB_DEBUG_CONTROL3),
+ DREG(PHB_DEBUG_STATUS3),
+ DREG(PHB_DEBUG_CONTROL4),
+ DREG(PHB_DEBUG_STATUS4),
+ DREG(PHB_DEBUG_CONTROL5),
+ DREG(PHB_DEBUG_STATUS5),
+
+ /* Don't seem to exist ...
+ DREG(PHB_DEBUG_CONTROL6),
+ DREG(PHB_DEBUG_STATUS6),
+ */
+};
+
+static int wsp_pci_regs_show(struct seq_file *m, void *private)
+{
+ struct wsp_phb *phb = m->private;
+ struct pci_controller *hose = phb->hose;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(wsp_pci_regs); i++) {
+ /* Skip write-only regs */
+ if (wsp_pci_regs[i].offset == 0xc08 ||
+ wsp_pci_regs[i].offset == 0xc10 ||
+ wsp_pci_regs[i].offset == 0xc38 ||
+ wsp_pci_regs[i].offset == 0xc40)
+ continue;
+ seq_printf(m, "0x%03x: 0x%016llx %s\n",
+ wsp_pci_regs[i].offset,
+ in_be64(hose->cfg_data + wsp_pci_regs[i].offset),
+ wsp_pci_regs[i].name);
+ }
+ return 0;
+}
+
+static int wsp_pci_regs_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, wsp_pci_regs_show, inode->i_private);
+}
+
+static const struct file_operations wsp_pci_regs_fops = {
+ .open = wsp_pci_regs_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int wsp_pci_reg_set(void *data, u64 val)
+{
+ out_be64((void __iomem *)data, val);
+ return 0;
+}
+
+static int wsp_pci_reg_get(void *data, u64 *val)
+{
+ *val = in_be64((void __iomem *)data);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(wsp_pci_reg_fops, wsp_pci_reg_get, wsp_pci_reg_set, "0x%llx\n");
+
+static irqreturn_t wsp_pci_err_irq(int irq, void *dev_id)
+{
+ struct wsp_phb *phb = dev_id;
+ struct pci_controller *hose = phb->hose;
+ irqreturn_t handled = IRQ_NONE;
+ struct wsp_pcie_err_log_data ed;
+
+ pr_err("PCI: Error interrupt on %s (PHB %d)\n",
+ hose->dn->full_name, hose->global_number);
+ again:
+ memset(&ed, 0, sizeof(ed));
+
+ /* Read and clear UTL errors */
+ ed.utl_sys_err = in_be64(hose->cfg_data + PCIE_UTL_SYS_BUS_AGENT_STATUS);
+ if (ed.utl_sys_err)
+ out_be64(hose->cfg_data + PCIE_UTL_SYS_BUS_AGENT_STATUS, ed.utl_sys_err);
+ ed.utl_port_err = in_be64(hose->cfg_data + PCIE_UTL_PCIE_PORT_STATUS);
+ if (ed.utl_port_err)
+ out_be64(hose->cfg_data + PCIE_UTL_PCIE_PORT_STATUS, ed.utl_port_err);
+ ed.utl_rc_err = in_be64(hose->cfg_data + PCIE_UTL_RC_STATUS);
+ if (ed.utl_rc_err)
+ out_be64(hose->cfg_data + PCIE_UTL_RC_STATUS, ed.utl_rc_err);
+
+ /* Read and clear main trap errors */
+ ed.phb_err = in_be64(hose->cfg_data + PCIE_REG_PHB_ERR_STATUS);
+ if (ed.phb_err) {
+ ed.phb_err1 = in_be64(hose->cfg_data + PCIE_REG_PHB_ERR1_STATUS);
+ ed.phb_log0 = in_be64(hose->cfg_data + PCIE_REG_PHB_ERR_LOG_0);
+ ed.phb_log1 = in_be64(hose->cfg_data + PCIE_REG_PHB_ERR_LOG_1);
+ out_be64(hose->cfg_data + PCIE_REG_PHB_ERR1_STATUS, 0);
+ out_be64(hose->cfg_data + PCIE_REG_PHB_ERR_STATUS, 0);
+ }
+ ed.mmio_err = in_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_STATUS);
+ if (ed.mmio_err) {
+ ed.mmio_err1 = in_be64(hose->cfg_data + PCIE_REG_MMIO_ERR1_STATUS);
+ ed.mmio_log0 = in_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_LOG_0);
+ ed.mmio_log1 = in_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_LOG_1);
+ out_be64(hose->cfg_data + PCIE_REG_MMIO_ERR1_STATUS, 0);
+ out_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_STATUS, 0);
+ }
+ ed.dma_err = in_be64(hose->cfg_data + PCIE_REG_DMA_ERR_STATUS);
+ if (ed.dma_err) {
+ ed.dma_err1 = in_be64(hose->cfg_data + PCIE_REG_DMA_ERR1_STATUS);
+ ed.dma_log0 = in_be64(hose->cfg_data + PCIE_REG_DMA_ERR_LOG_0);
+ ed.dma_log1 = in_be64(hose->cfg_data + PCIE_REG_DMA_ERR_LOG_1);
+ out_be64(hose->cfg_data + PCIE_REG_DMA_ERR1_STATUS, 0);
+ out_be64(hose->cfg_data + PCIE_REG_DMA_ERR_STATUS, 0);
+ }
+
+ /* Now print things out */
+ if (ed.phb_err) {
+ pr_err(" PHB Error Status : 0x%016llx\n", ed.phb_err);
+ pr_err(" PHB First Error Status: 0x%016llx\n", ed.phb_err1);
+ pr_err(" PHB Error Log 0 : 0x%016llx\n", ed.phb_log0);
+ pr_err(" PHB Error Log 1 : 0x%016llx\n", ed.phb_log1);
+ }
+ if (ed.mmio_err) {
+ pr_err(" MMIO Error Status : 0x%016llx\n", ed.mmio_err);
+ pr_err(" MMIO First Error Status: 0x%016llx\n", ed.mmio_err1);
+ pr_err(" MMIO Error Log 0 : 0x%016llx\n", ed.mmio_log0);
+ pr_err(" MMIO Error Log 1 : 0x%016llx\n", ed.mmio_log1);
+ }
+ if (ed.dma_err) {
+ pr_err(" DMA Error Status : 0x%016llx\n", ed.dma_err);
+ pr_err(" DMA First Error Status: 0x%016llx\n", ed.dma_err1);
+ pr_err(" DMA Error Log 0 : 0x%016llx\n", ed.dma_log0);
+ pr_err(" DMA Error Log 1 : 0x%016llx\n", ed.dma_log1);
+ }
+ if (ed.utl_sys_err)
+ pr_err(" UTL Sys Error Status : 0x%016llx\n", ed.utl_sys_err);
+ if (ed.utl_port_err)
+ pr_err(" UTL Port Error Status : 0x%016llx\n", ed.utl_port_err);
+ if (ed.utl_rc_err)
+ pr_err(" UTL RC Error Status : 0x%016llx\n", ed.utl_rc_err);
+
+ /* Interrupts are caused by the error traps. If we had any error there
+ * we loop again in case the UTL buffered some new stuff between
+ * going there and going to the traps
+ */
+ if (ed.dma_err || ed.mmio_err || ed.phb_err) {
+ handled = IRQ_HANDLED;
+ goto again;
+ }
+ return handled;
+}
+
+static void __init wsp_setup_pci_err_reporting(struct wsp_phb *phb)
+{
+ struct pci_controller *hose = phb->hose;
+ int err_irq, i, rc;
+ char fname[16];
+
+ /* Create a debugfs file for that PHB */
+ sprintf(fname, "phb%d", phb->hose->global_number);
+ phb->ddir = debugfs_create_dir(fname, powerpc_debugfs_root);
+
+ /* Some useful debug output */
+ if (phb->ddir) {
+ struct dentry *d = debugfs_create_dir("regs", phb->ddir);
+ char tmp[64];
+
+ for (i = 0; i < ARRAY_SIZE(wsp_pci_regs); i++) {
+ sprintf(tmp, "%03x_%s", wsp_pci_regs[i].offset,
+ wsp_pci_regs[i].name);
+ debugfs_create_file(tmp, 0600, d,
+ hose->cfg_data + wsp_pci_regs[i].offset,
+ &wsp_pci_reg_fops);
+ }
+ debugfs_create_file("all_regs", 0600, phb->ddir, phb, &wsp_pci_regs_fops);
+ }
+
+ /* Find the IRQ number for that PHB */
+ err_irq = irq_of_parse_and_map(hose->dn, 0);
+ if (err_irq == 0)
+ /* XXX Error IRQ lacking from device-tree */
+ err_irq = wsp_pci_get_err_irq_no_dt(hose->dn);
+ if (err_irq == 0) {
+ pr_err("PCI: Failed to fetch error interrupt for %s\n",
+ hose->dn->full_name);
+ return;
+ }
+ /* Request it */
+ rc = request_irq(err_irq, wsp_pci_err_irq, 0, "wsp_pci error", phb);
+ if (rc) {
+ pr_err("PCI: Failed to request interrupt for %s\n",
+ hose->dn->full_name);
+ }
+ /* Enable interrupts for all errors for now */
+ out_be64(hose->cfg_data + PCIE_REG_PHB_ERR_IRQ_ENABLE, 0xffffffffffffffffull);
+ out_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_IRQ_ENABLE, 0xffffffffffffffffull);
+ out_be64(hose->cfg_data + PCIE_REG_DMA_ERR_IRQ_ENABLE, 0xffffffffffffffffull);
+}
+
+/*
+ * This is called later to hookup with the error interrupt
+ */
+static int __init wsp_setup_pci_late(void)
+{
+ struct wsp_phb *phb;
+
+ list_for_each_entry(phb, &wsp_phbs, all)
+ wsp_setup_pci_err_reporting(phb);
+
+ return 0;
+}
+arch_initcall(wsp_setup_pci_late);
diff --git a/arch/powerpc/platforms/wsp/wsp_pci.h b/arch/powerpc/platforms/wsp/wsp_pci.h
new file mode 100644
index 0000000..52e9bd9
--- /dev/null
+++ b/arch/powerpc/platforms/wsp/wsp_pci.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright 2010 Ben Herrenschmidt, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef __WSP_PCI_H
+#define __WSP_PCI_H
+
+/* Architected registers */
+#define PCIE_REG_DMA_CHAN_STATUS 0x110
+#define PCIE_REG_CPU_LOADSTORE_STATUS 0x120
+
+#define PCIE_REG_CONFIG_DATA 0x130
+#define PCIE_REG_LOCK0 0x138
+#define PCIE_REG_CONFIG_ADDRESS 0x140
+#define PCIE_REG_CA_ENABLE 0x8000000000000000ull
+#define PCIE_REG_CA_BUS_MASK 0x0ff0000000000000ull
+#define PCIE_REG_CA_BUS_SHIFT (20+32)
+#define PCIE_REG_CA_DEV_MASK 0x000f800000000000ull
+#define PCIE_REG_CA_DEV_SHIFT (15+32)
+#define PCIE_REG_CA_FUNC_MASK 0x0000700000000000ull
+#define PCIE_REG_CA_FUNC_SHIFT (12+32)
+#define PCIE_REG_CA_REG_MASK 0x00000fff00000000ull
+#define PCIE_REG_CA_REG_SHIFT ( 0+32)
+#define PCIE_REG_CA_BE_MASK 0x00000000f0000000ull
+#define PCIE_REG_CA_BE_SHIFT ( 28)
+#define PCIE_REG_LOCK1 0x148
+
+#define PCIE_REG_PHB_CONFIG 0x160
+#define PCIE_REG_PHBC_64B_TCE_EN 0x2000000000000000ull
+#define PCIE_REG_PHBC_MMIO_DMA_FREEZE_EN 0x1000000000000000ull
+#define PCIE_REG_PHBC_32BIT_MSI_EN 0x0080000000000000ull
+#define PCIE_REG_PHBC_M64_EN 0x0040000000000000ull
+#define PCIE_REG_PHBC_IO_EN 0x0008000000000000ull
+#define PCIE_REG_PHBC_64BIT_MSI_EN 0x0002000000000000ull
+#define PCIE_REG_PHBC_M32A_EN 0x0000800000000000ull
+#define PCIE_REG_PHBC_M32B_EN 0x0000400000000000ull
+#define PCIE_REG_PHBC_MSI_PE_VALIDATE 0x0000200000000000ull
+#define PCIE_REG_PHBC_DMA_XLATE_BYPASS 0x0000100000000000ull
+
+#define PCIE_REG_IO_BASE_ADDR 0x170
+#define PCIE_REG_IO_BASE_MASK 0x178
+#define PCIE_REG_IO_START_ADDR 0x180
+
+#define PCIE_REG_M32A_BASE_ADDR 0x190
+#define PCIE_REG_M32A_BASE_MASK 0x198
+#define PCIE_REG_M32A_START_ADDR 0x1a0
+
+#define PCIE_REG_M32B_BASE_ADDR 0x1b0
+#define PCIE_REG_M32B_BASE_MASK 0x1b8
+#define PCIE_REG_M32B_START_ADDR 0x1c0
+
+#define PCIE_REG_M64_BASE_ADDR 0x1e0
+#define PCIE_REG_M64_BASE_MASK 0x1e8
+#define PCIE_REG_M64_START_ADDR 0x1f0
+
+#define PCIE_REG_TCE_KILL 0x210
+#define PCIE_REG_TCEKILL_SINGLE 0x8000000000000000ull
+#define PCIE_REG_TCEKILL_ADDR_MASK 0x000003fffffffff8ull
+#define PCIE_REG_TCEKILL_PS_4K 0
+#define PCIE_REG_TCEKILL_PS_64K 1
+#define PCIE_REG_TCEKILL_PS_16M 2
+#define PCIE_REG_TCEKILL_PS_16G 3
+
+#define PCIE_REG_IODA_ADDR 0x220
+#define PCIE_REG_IODA_AD_AUTOINC 0x8000000000000000ull
+#define PCIE_REG_IODA_AD_TBL_MVT 0x0005000000000000ull
+#define PCIE_REG_IODA_AD_TBL_PELT 0x0006000000000000ull
+#define PCIE_REG_IODA_AD_TBL_PESTA 0x0007000000000000ull
+#define PCIE_REG_IODA_AD_TBL_PESTB 0x0008000000000000ull
+#define PCIE_REG_IODA_AD_TBL_TVT 0x0009000000000000ull
+#define PCIE_REG_IODA_AD_TBL_TCE 0x000a000000000000ull
+#define PCIE_REG_IODA_DATA0 0x228
+#define PCIE_REG_IODA_DATA1 0x230
+
+#define PCIE_REG_LOCK2 0x240
+
+#define PCIE_REG_PHB_GEN_CAP 0x250
+#define PCIE_REG_PHB_TCE_CAP 0x258
+#define PCIE_REG_PHB_IRQ_CAP 0x260
+#define PCIE_REG_PHB_EEH_CAP 0x268
+
+#define PCIE_REG_PAPR_ERR_INJ_CONTROL 0x2b0
+#define PCIE_REG_PAPR_ERR_INJ_ADDR 0x2b8
+#define PCIE_REG_PAPR_ERR_INJ_MASK 0x2c0
+
+
+#define PCIE_REG_SYS_CFG1 0x600
+#define PCIE_REG_SYS_CFG1_CLASS_CODE 0x0000000000ffffffull
+
+#define IODA_TVT0_TTA_MASK 0x000fffffffff0000ull
+#define IODA_TVT0_TTA_SHIFT 4
+#define IODA_TVT0_BUSNUM_VALID_MASK 0x000000000000e000ull
+#define IODA_TVT0_TCE_TABLE_SIZE_MASK 0x0000000000001f00ull
+#define IODA_TVT0_TCE_TABLE_SIZE_SHIFT 8
+#define IODA_TVT0_BUSNUM_VALUE_MASK 0x00000000000000ffull
+#define IODA_TVT0_BUSNUM_VALID_SHIFT 0
+#define IODA_TVT1_DEVNUM_VALID 0x2000000000000000ull
+#define IODA_TVT1_DEVNUM_VALUE_MASK 0x1f00000000000000ull
+#define IODA_TVT1_DEVNUM_VALUE_SHIFT 56
+#define IODA_TVT1_FUNCNUM_VALID 0x0008000000000000ull
+#define IODA_TVT1_FUNCNUM_VALUE_MASK 0x0007000000000000ull
+#define IODA_TVT1_FUNCNUM_VALUE_SHIFT 48
+#define IODA_TVT1_IO_PAGE_SIZE_MASK 0x00001f0000000000ull
+#define IODA_TVT1_IO_PAGE_SIZE_SHIFT 40
+#define IODA_TVT1_PE_NUMBER_MASK 0x000000000000003full
+#define IODA_TVT1_PE_NUMBER_SHIFT 0
+
+#define IODA_TVT_COUNT 64
+
+/* UTL Core registers */
+#define PCIE_UTL_SYS_BUS_CONTROL 0x400
+#define PCIE_UTL_STATUS 0x408
+#define PCIE_UTL_SYS_BUS_AGENT_STATUS 0x410
+#define PCIE_UTL_SYS_BUS_AGENT_ERR_SEV 0x418
+#define PCIE_UTL_SYS_BUS_AGENT_IRQ_EN 0x420
+#define PCIE_UTL_SYS_BUS_BURST_SZ_CONF 0x440
+#define PCIE_UTL_REVISION_ID 0x448
+
+#define PCIE_UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0
+#define PCIE_UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0
+#define PCIE_UTL_IN_POST_HDR_BUF_ALLOC 0x4e0
+#define PCIE_UTL_IN_POST_DAT_BUF_ALLOC 0x4f0
+#define PCIE_UTL_OUT_NP_BUF_ALLOC 0x500
+#define PCIE_UTL_IN_NP_BUF_ALLOC 0x510
+#define PCIE_UTL_PCIE_TAGS_ALLOC 0x520
+#define PCIE_UTL_GBIF_READ_TAGS_ALLOC 0x530
+
+#define PCIE_UTL_PCIE_PORT_CONTROL 0x540
+#define PCIE_UTL_PCIE_PORT_STATUS 0x548
+#define PCIE_UTL_PCIE_PORT_ERROR_SEV 0x550
+#define PCIE_UTL_PCIE_PORT_IRQ_EN 0x558
+#define PCIE_UTL_RC_STATUS 0x560
+#define PCIE_UTL_RC_ERR_SEVERITY 0x568
+#define PCIE_UTL_RC_IRQ_EN 0x570
+#define PCIE_UTL_EP_STATUS 0x578
+#define PCIE_UTL_EP_ERR_SEVERITY 0x580
+#define PCIE_UTL_EP_ERR_IRQ_EN 0x588
+
+#define PCIE_UTL_PCI_PM_CTRL1 0x590
+#define PCIE_UTL_PCI_PM_CTRL2 0x598
+
+/* PCIe stack registers */
+#define PCIE_REG_SYSTEM_CONFIG1 0x600
+#define PCIE_REG_SYSTEM_CONFIG2 0x608
+#define PCIE_REG_EP_SYSTEM_CONFIG 0x618
+#define PCIE_REG_EP_FLR 0x620
+#define PCIE_REG_EP_BAR_CONFIG 0x628
+#define PCIE_REG_LINK_CONFIG 0x630
+#define PCIE_REG_PM_CONFIG 0x640
+#define PCIE_REG_DLP_CONTROL 0x650
+#define PCIE_REG_DLP_STATUS 0x658
+#define PCIE_REG_ERR_REPORT_CONTROL 0x660
+#define PCIE_REG_SLOT_CONTROL1 0x670
+#define PCIE_REG_SLOT_CONTROL2 0x678
+#define PCIE_REG_UTL_CONFIG 0x680
+#define PCIE_REG_BUFFERS_CONFIG 0x690
+#define PCIE_REG_ERROR_INJECT 0x698
+#define PCIE_REG_SRIOV_CONFIG 0x6a0
+#define PCIE_REG_PF0_SRIOV_STATUS 0x6a8
+#define PCIE_REG_PF1_SRIOV_STATUS 0x6b0
+#define PCIE_REG_PORT_NUMBER 0x700
+#define PCIE_REG_POR_SYSTEM_CONFIG 0x708
+
+/* PHB internal logic registers */
+#define PCIE_REG_PHB_VERSION 0x800
+#define PCIE_REG_RESET 0x808
+#define PCIE_REG_PHB_CONTROL 0x810
+#define PCIE_REG_PHB_TIMEOUT_CONTROL1 0x878
+#define PCIE_REG_PHB_QUIESCE_DMA 0x888
+#define PCIE_REG_PHB_DMA_READ_TAG_ACTV 0x900
+#define PCIE_REG_PHB_TCE_READ_TAG_ACTV 0x908
+
+/* FIR registers */
+#define PCIE_REG_LEM_FIR_ACCUM 0xc00
+#define PCIE_REG_LEM_FIR_AND_MASK 0xc08
+#define PCIE_REG_LEM_FIR_OR_MASK 0xc10
+#define PCIE_REG_LEM_ACTION0 0xc18
+#define PCIE_REG_LEM_ACTION1 0xc20
+#define PCIE_REG_LEM_ERROR_MASK 0xc30
+#define PCIE_REG_LEM_ERROR_AND_MASK 0xc38
+#define PCIE_REG_LEM_ERROR_OR_MASK 0xc40
+
+/* PHB Error registers */
+#define PCIE_REG_PHB_ERR_STATUS 0xc80
+#define PCIE_REG_PHB_ERR1_STATUS 0xc88
+#define PCIE_REG_PHB_ERR_INJECT 0xc90
+#define PCIE_REG_PHB_ERR_LEM_ENABLE 0xc98
+#define PCIE_REG_PHB_ERR_IRQ_ENABLE 0xca0
+#define PCIE_REG_PHB_ERR_FREEZE_ENABLE 0xca8
+#define PCIE_REG_PHB_ERR_SIDE_ENABLE 0xcb8
+#define PCIE_REG_PHB_ERR_LOG_0 0xcc0
+#define PCIE_REG_PHB_ERR_LOG_1 0xcc8
+#define PCIE_REG_PHB_ERR_STATUS_MASK 0xcd0
+#define PCIE_REG_PHB_ERR1_STATUS_MASK 0xcd8
+
+#define PCIE_REG_MMIO_ERR_STATUS 0xd00
+#define PCIE_REG_MMIO_ERR1_STATUS 0xd08
+#define PCIE_REG_MMIO_ERR_INJECT 0xd10
+#define PCIE_REG_MMIO_ERR_LEM_ENABLE 0xd18
+#define PCIE_REG_MMIO_ERR_IRQ_ENABLE 0xd20
+#define PCIE_REG_MMIO_ERR_FREEZE_ENABLE 0xd28
+#define PCIE_REG_MMIO_ERR_SIDE_ENABLE 0xd38
+#define PCIE_REG_MMIO_ERR_LOG_0 0xd40
+#define PCIE_REG_MMIO_ERR_LOG_1 0xd48
+#define PCIE_REG_MMIO_ERR_STATUS_MASK 0xd50
+#define PCIE_REG_MMIO_ERR1_STATUS_MASK 0xd58
+
+#define PCIE_REG_DMA_ERR_STATUS 0xd80
+#define PCIE_REG_DMA_ERR1_STATUS 0xd88
+#define PCIE_REG_DMA_ERR_INJECT 0xd90
+#define PCIE_REG_DMA_ERR_LEM_ENABLE 0xd98
+#define PCIE_REG_DMA_ERR_IRQ_ENABLE 0xda0
+#define PCIE_REG_DMA_ERR_FREEZE_ENABLE 0xda8
+#define PCIE_REG_DMA_ERR_SIDE_ENABLE 0xdb8
+#define PCIE_REG_DMA_ERR_LOG_0 0xdc0
+#define PCIE_REG_DMA_ERR_LOG_1 0xdc8
+#define PCIE_REG_DMA_ERR_STATUS_MASK 0xdd0
+#define PCIE_REG_DMA_ERR1_STATUS_MASK 0xdd8
+
+/* Shortcuts for access to the above using the PHB definitions
+ * with an offset
+ */
+#define PCIE_REG_ERR_PHB_OFFSET 0x0
+#define PCIE_REG_ERR_MMIO_OFFSET 0x80
+#define PCIE_REG_ERR_DMA_OFFSET 0x100
+
+/* Debug and Trace registers */
+#define PCIE_REG_PHB_DEBUG_CONTROL0 0xe00
+#define PCIE_REG_PHB_DEBUG_STATUS0 0xe08
+#define PCIE_REG_PHB_DEBUG_CONTROL1 0xe10
+#define PCIE_REG_PHB_DEBUG_STATUS1 0xe18
+#define PCIE_REG_PHB_DEBUG_CONTROL2 0xe20
+#define PCIE_REG_PHB_DEBUG_STATUS2 0xe28
+#define PCIE_REG_PHB_DEBUG_CONTROL3 0xe30
+#define PCIE_REG_PHB_DEBUG_STATUS3 0xe38
+#define PCIE_REG_PHB_DEBUG_CONTROL4 0xe40
+#define PCIE_REG_PHB_DEBUG_STATUS4 0xe48
+#define PCIE_REG_PHB_DEBUG_CONTROL5 0xe50
+#define PCIE_REG_PHB_DEBUG_STATUS5 0xe58
+#define PCIE_REG_PHB_DEBUG_CONTROL6 0xe60
+#define PCIE_REG_PHB_DEBUG_STATUS6 0xe68
+
+/* Definition for PCIe errors */
+struct wsp_pcie_err_log_data {
+ __u64 phb_err;
+ __u64 phb_err1;
+ __u64 phb_log0;
+ __u64 phb_log1;
+ __u64 mmio_err;
+ __u64 mmio_err1;
+ __u64 mmio_log0;
+ __u64 mmio_log1;
+ __u64 dma_err;
+ __u64 dma_err1;
+ __u64 dma_log0;
+ __u64 dma_log1;
+ __u64 utl_sys_err;
+ __u64 utl_port_err;
+ __u64 utl_rc_err;
+ __u64 unused;
+};
+
+#endif /* __WSP_PCI_H */
--
1.7.0.4
^ permalink raw reply related
* powerpc: poweren: Add PCIe Root and MSI support the PowerEN
From: Jimi Xenidis @ 2011-08-08 22:30 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Michael Ellerman, Ian Munsie
Based on patchs from:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Michael Ellerman <michael@ellerman.id.au>
I just brought them up to date
-JX
^ permalink raw reply
* [PATCH 3/3] powerpc: icswx: Simple ACOP fault handler for both book3e and book3s parts.
From: Jimi Xenidis @ 2011-08-08 22:26 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Ian Munsie, Anton Blanchard
In-Reply-To: <1312842408-21482-1-git-send-email-jimix@pobox.com>
This patch adds a fault handler that responds to illegal Coprocessor
types. Currently all CTs are treated and illegal. There are two ways
to report the fault back to the application. If the application used
the record form ("icswx.") then the architected "reject" is emulated.
If the application did not used the record form ("icswx") then it is
selectable by config whether the failure is silent (as architected) or
a SIGILL is generated.
In all cases pr_warn() is used to log the bad CT.
Signed-off-by: Jimi Xenidis <jimix@pobox.com>
---
arch/powerpc/mm/fault.c | 16 +++++
arch/powerpc/mm/icswx.c | 114 ++++++++++++++++++++++++++++++++
arch/powerpc/mm/icswx.h | 34 ++++++++++
arch/powerpc/platforms/Kconfig.cputype | 11 +++
4 files changed, 175 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 5efe8c9..88abe70 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -43,6 +43,7 @@
#include <asm/tlbflush.h>
#include <asm/siginfo.h>
#include <mm/mmu_decl.h>
+#include <mm/icswx.h>
#ifdef CONFIG_KPROBES
static inline int notify_page_fault(struct pt_regs *regs)
@@ -143,6 +144,21 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
is_write = error_code & ESR_DST;
#endif /* CONFIG_4xx || CONFIG_BOOKE */
+#ifdef CONFIG_PPC_ICSWX
+ /*
+ * we need to do this early because this "data storage
+ * interrupt" does not update the DAR/DEAR so we don't want to
+ * look at it
+ */
+ if (error_code & ICSWX_DSI_UCT) {
+ int ret;
+
+ ret = acop_handle_fault(regs, address, error_code);
+ if (ret)
+ return ret;
+ }
+#endif
+
if (notify_page_fault(regs))
return 0;
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
index 667330e..fbf71b4 100644
--- a/arch/powerpc/mm/icswx.c
+++ b/arch/powerpc/mm/icswx.c
@@ -17,6 +17,9 @@
#include <linux/mm.h>
#include <linux/spinlock.h>
#include <linux/module.h>
+
+#include <asm/uaccess.h>
+
#include "icswx.h"
@@ -161,3 +164,114 @@ void drop_cop(unsigned long acop, struct mm_struct *mm)
up_read(&mm->mmap_sem);
}
EXPORT_SYMBOL_GPL(drop_cop);
+
+static int acop_use_cop(int ct)
+{
+ /* todo */
+ return -1;
+}
+
+/*
+ * Get the instruction word at the NIP
+ */
+static u32 acop_get_inst(struct pt_regs *regs)
+{
+ u32 inst;
+ u32 __user *p;
+
+ p = (u32 __user *)regs->nip;
+ if (!access_ok(VERIFY_READ, p, sizeof(*p)))
+ return 0;
+
+ if (__get_user(inst, p))
+ return 0;
+
+ return inst;
+}
+
+/**
+ * @regs: regsiters at time of interrupt
+ * @address: storage address
+ * @error_code: Fault code, usually the DSISR or ESR depending on
+ * processor type
+ *
+ * Return 0 if we are able to resolve the data storage fault that
+ * results from a CT miss in the ACOP register.
+ */
+int acop_handle_fault(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code)
+{
+ int ct;
+ u32 inst = 0;
+
+ if (!cpu_has_feature(CPU_FTR_ICSWX)) {
+ pr_info("No coprocessors available");
+ _exception(SIGILL, regs, ILL_ILLOPN, address);
+ }
+
+ if (!user_mode(regs)) {
+ /* this could happen if the HV denies the
+ * kernel access, for now we just die */
+ die("ICSWX from kernel failed", regs, SIGSEGV);
+ }
+
+ /* Some implementations leave us a hint for the CT */
+ ct = ICSWX_GET_CT_HINT(error_code);
+ if (ct < 0) {
+ /* we have to peek at the instruction work to figure out CT */
+ union cop_ccw ccw;
+ u32 rs;
+
+ inst = acop_get_inst(regs);
+ if (inst == 0)
+ return -1;
+
+ rs = (inst >> (31 - 10)) & 0x1f;
+ ccw._val = regs->gpr[rs];
+ ct = ccw.ct;
+ }
+
+ if (!acop_use_cop(ct))
+ return 0;
+
+ /* at this point the CT is unknown to the system */
+ pr_warn("%s[%d]: Coprocessor %d is unavailable",
+ current->comm, current->pid, ct);
+
+ /* get inst if we don't already have it */
+ if (inst == 0) {
+ inst = acop_get_inst(regs);
+ if (inst == 0)
+ return -1;
+ }
+
+ /* Check if the instruction is the "record form" */
+ if (inst & 1) {
+ /*
+ * the instruction is "record" form so we can reject
+ * using CR0
+ */
+ regs->ccr &= ~(0xful << 28);
+ regs->ccr |= ICSWX_RC_NOT_FOUND << 28;
+
+ /* Move on to the next instruction */
+ regs->nip += 4;
+ } else {
+ /*
+ * There is no architected mechanism to report a bad
+ * CT so we could either SIGILL or report nothing.
+ * Since the non-record version should only bu used
+ * for "hints" or "don't care" we should probably do
+ * nothing. However, I could see how some people
+ * might want an SIGILL so it here if you want it.
+ */
+#ifdef CONFIG_ICSWX_USE_SIGILL
+ _exception(SIGILL, regs, ILL_ILLOPN, address);
+#else
+ regs->nip += 4;
+#endif
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(acop_handle_fault);
diff --git a/arch/powerpc/mm/icswx.h b/arch/powerpc/mm/icswx.h
index 5121ddd..920d9f3 100644
--- a/arch/powerpc/mm/icswx.h
+++ b/arch/powerpc/mm/icswx.h
@@ -32,3 +32,37 @@ extern void free_cop_pid(int free_pid);
#define disable_cop_pid(m) (COP_PID_NONE)
#define free_cop_pid(p)
#endif
+
+/*
+ * These are implementation bits for architected registers. If this
+ * ever becomes architecture the should be moved to reg.h et. al.
+ */
+/* UCT is the same bit for Server and Embedded */
+#define ICSWX_DSI_UCT 0x00004000 /* Unavailable Coprocessor Type */
+
+#ifdef CONFIG_BOOKE
+/* Embedded implementation gives us no hits as to what the CT is */
+#define ICSWX_GET_CT_HINT(x) (-1)
+#else
+/* Server implementation contains the CT value in the DSISR */
+#define ICSWX_DSISR_CTMASK 0x00003f00
+#define ICSWX_GET_CT_HINT(x) (((x) & ICSWX_DSISR_CTMASK) >> 8)
+#endif
+
+union cop_ccw {
+ u32 _val;
+ struct {
+ u32 msb:8;
+ u32 reserved:2;
+ u32 ct:6;
+ u32 cd:16;
+ };
+};
+
+#define ICSWX_RC_STARTED 0x8 /* The request has been started */
+#define ICSWX_RC_NOT_IDLE 0x4 /* No coprocessor found idle */
+#define ICSWX_RC_NOT_FOUND 0x2 /* No coprocessor found */
+#define ICSWX_RC_UNDEFINED 0x1 /* Reserved */
+
+extern int acop_handle_fault(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code);
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 3cd22e5..817d723 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -258,6 +258,17 @@ config PPC_ICSWX_PID
PID register in server is used explicitly for ICSWX. In
embedded systems PID managment is done by the system.
+config PPC_ICSWX_USE_SIGILL
+ bool "Should a bad CT cause a SIGILL?"
+ depends on PPC_ICSWX
+ default n
+ ---help---
+ Should a bad CT used for "non-record form ICSWX" cause an
+ illegal intruction signal or should it be silent as
+ architected.
+
+ If in doubt, say N here.
+
config SPE
bool "SPE Support"
depends on E200 || (E500 && !PPC_E500MC)
--
1.7.0.4
^ permalink raw reply related
* [PATCH 2/3] powerpc: book3e: Add ICSWX/ACOP support to Book3e cores like A2
From: Jimi Xenidis @ 2011-08-08 22:26 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Ian Munsie, Anton Blanchard
In-Reply-To: <1312842408-21482-1-git-send-email-jimix@pobox.com>
ICSWX is also used by the A2 processor to access coprocessors,
although not all "chips" that contain A2s have coprocessors.
Signed-off-by: Jimi Xenidis <jimix@pobox.com>
---
arch/powerpc/include/asm/cputable.h | 2 +-
arch/powerpc/include/asm/mmu-book3e.h | 4 ++++
arch/powerpc/include/asm/reg_booke.h | 4 ++++
arch/powerpc/kernel/cpu_setup_a2.S | 10 ++++++++--
arch/powerpc/platforms/wsp/Kconfig | 1 +
5 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index e30442c..7044233 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -437,7 +437,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
- CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+ CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
#ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 3ea0f9a..06d7f91 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -212,6 +212,10 @@ typedef struct {
unsigned int id;
unsigned int active;
unsigned long vdso_base;
+#ifdef CONFIG_PPC_ICSWX
+ struct spinlock *cop_lockp; /* guard acop and cop_pid */
+ unsigned long acop; /* mask of enabled coprocessor types */
+#endif /* CONFIG_PPC_ICSWX */
} mm_context_t;
/* Page size definitions, common between 32 and 64-bit
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 9ec0b39..e927049 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -187,6 +187,10 @@
#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
#endif
+#ifdef CONFIG_PPC_ICSWX
+#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
+#endif
+
/* Bit definitions for CCR1. */
#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
#define CCR1_TCS 0x00000080 /* Timer Clock Select */
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S b/arch/powerpc/kernel/cpu_setup_a2.S
index 7f818fe..ebc62f4 100644
--- a/arch/powerpc/kernel/cpu_setup_a2.S
+++ b/arch/powerpc/kernel/cpu_setup_a2.S
@@ -41,11 +41,16 @@ _GLOBAL(__setup_cpu_a2)
* core local but doing it always won't hurt
*/
-#ifdef CONFIG_PPC_WSP_COPRO
+#ifdef CONFIG_PPC_ICSWX
/* Make sure ACOP starts out as zero */
li r3,0
mtspr SPRN_ACOP,r3
+ /* Skip the following if we are in Guest mode */
+ mfmsr r3
+ andis. r0,r3,MSR_GS@h
+ bne _icswx_skip_guest
+
/* Enable icswx instruction */
mfspr r3,SPRN_A2_CCR2
ori r3,r3,A2_CCR2_ENABLE_ICSWX
@@ -54,7 +59,8 @@ _GLOBAL(__setup_cpu_a2)
/* Unmask all CTs in HACOP */
li r3,-1
mtspr SPRN_HACOP,r3
-#endif /* CONFIG_PPC_WSP_COPRO */
+_icswx_skip_guest:
+#endif /* CONFIG_PPC_ICSWX */
/* Enable doorbell */
mfspr r3,SPRN_A2_CCR2
diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig
index d051581..3540293 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -1,6 +1,7 @@
config PPC_WSP
bool
select PPC_A2
+ select PPC_ICSWX
select PPC_SCOM
select PPC_XICS
select PPC_ICP_NATIVE
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/3] powerpc: Split ICSWX ACOP and PID processing
From: Jimi Xenidis @ 2011-08-08 22:26 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Ian Munsie, Anton Blanchard
In-Reply-To: <1312842408-21482-1-git-send-email-jimix@pobox.com>
Some processors, like embedded, that already have a PID register that
is managed by the system. This patch separates the ACOP and PID
processing into separate files so that the ACOP code can be shared.
Signed-off-by: Jimi Xenidis <jimix@pobox.com>
---
arch/powerpc/mm/Makefile | 4 +-
arch/powerpc/mm/icswx.c | 163 ++++++++++++++++++++++++++
arch/powerpc/mm/icswx.h | 34 ++++++
arch/powerpc/mm/icswx_pid.c | 87 ++++++++++++++
arch/powerpc/mm/mmu_context_hash64.c | 195 --------------------------------
arch/powerpc/platforms/Kconfig.cputype | 10 ++-
6 files changed, 296 insertions(+), 197 deletions(-)
create mode 100644 arch/powerpc/mm/icswx.c
create mode 100644 arch/powerpc/mm/icswx.h
create mode 100644 arch/powerpc/mm/icswx_pid.c
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index bdca46e..ba51190 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -21,7 +21,9 @@ obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
tlb_hash$(CONFIG_WORD_SIZE).o \
mmu_context_hash$(CONFIG_WORD_SIZE).o
-obj-$(CONFIG_40x) += 40x_mmu.o
+obj-$(CONFIG_PPC_ICSWX) += icswx.o
+obj-$(CONFIG_PPC_ICSWX_PID) += icswx_pid.o
+obj-$(CONFIG_40x) += 40x_mmu.o?
obj-$(CONFIG_44x) += 44x_mmu.o
obj-$(CONFIG_PPC_FSL_BOOK3E) += fsl_booke_mmu.o
obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
diff --git a/arch/powerpc/mm/icswx.c b/arch/powerpc/mm/icswx.c
new file mode 100644
index 0000000..667330e
--- /dev/null
+++ b/arch/powerpc/mm/icswx.c
@@ -0,0 +1,163 @@
+/*
+ * ICSWX and ACOP Management
+ *
+ * Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include "icswx.h"
+
+
+/*
+ * The processor and its L2 cache cause the icswx instruction to
+ * generate a COP_REQ transaction on PowerBus. The transaction has no
+ * address, and the processor does not perform an MMU access to
+ * authenticate the transaction. The command portion of the PowerBus
+ * COP_REQ transaction includes the LPAR_ID (LPID) and the coprocessor
+ * Process ID (PID), which the coprocessor compares to the authorized
+ * LPID and PID held in the coprocessor, to determine if the process
+ * is authorized to generate the transaction. The data of the COP_REQ
+ * transaction is cache block or less, typically 64 or 128 bytes in
+ * size, and is placed in cacheable memory on a 128-byte boundary
+ * _always_.
+ *
+ * The task to use a coprocessor should use use_cop() mark the use of
+ * the coprocessor type (CT) and context swithing. On a server
+ * processor the PID register is used only for coprocessor management
+ * and so a coprocessor PID is allocated before executing icswx
+ * instruction. Drop_cop() is used to free the resources created by
+ * use_cop().
+ *
+ * Example:
+ * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
+ * Each HFI have multiple windows. Each HFI window serves as a
+ * network device sending to and receiving from HFI network.
+ * HFI immediate send function uses icswx instruction. The immediate
+ * send function allows small (single cache-line) packets be sent
+ * without using the regular HFI send FIFO and doorbell, which are
+ * much slower than immediate send.
+ *
+ * For each task intending to use HFI immediate send, the HFI driver
+ * calls use_cop() to obtain a coprocessor PID for the task.
+ * The HFI driver then allocate a free HFI window and save the
+ * coprocessor PID to the HFI window to allow the task to use the
+ * HFI window.
+ *
+ * The HFI driver repeatedly creates immediate send packets and
+ * issues icswx instruction to send data through the HFI window.
+ * The HFI compares the coprocessor PID in the CPU PID register
+ * to the PID held in the HFI window to determine if the transaction
+ * is allowed.
+ *
+ * When the task to release the HFI window, the HFI driver calls
+ * drop_cop() to release the coprocessor PID.
+ */
+
+void switch_cop(struct mm_struct *next)
+{
+#ifdef CONFIG_ICSWX_PID
+ mtspr(SPRN_PID, next->context.cop_pid);
+#endif
+ mtspr(SPRN_ACOP, next->context.acop);
+}
+
+/**
+ * Start using a coprocessor.
+ * @acop: mask of coprocessor to be used.
+ * @mm: The mm the coprocessor to associate with. Most likely current mm.
+ *
+ * Return a positive PID if successful. Negative errno otherwise.
+ * The returned PID will be fed to the coprocessor to determine if an
+ * icswx transaction is authenticated.
+ */
+int use_cop(unsigned long acop, struct mm_struct *mm)
+{
+ int ret;
+
+ if (!cpu_has_feature(CPU_FTR_ICSWX))
+ return -ENODEV;
+
+ if (!mm || !acop)
+ return -EINVAL;
+
+ /* We need to make sure mm_users doesn't change */
+ down_read(&mm->mmap_sem);
+ spin_lock(mm->context.cop_lockp);
+
+ ret = get_cop_pid(mm);
+ if (ret < 0)
+ goto out;
+
+ /* update acop */
+ mm->context.acop |= acop;
+
+ sync_cop(mm);
+
+ /*
+ * If this is a threaded process then there might be other threads
+ * running. We need to send an IPI to force them to pick up any
+ * change in PID and ACOP.
+ */
+ /* -JX why would we do this */
+ if (atomic_read(&mm->mm_users) > 1)
+ smp_call_function(sync_cop, mm, 1);
+
+out:
+ spin_unlock(mm->context.cop_lockp);
+ up_read(&mm->mmap_sem);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(use_cop);
+
+/**
+ * Stop using a coprocessor.
+ * @acop: mask of coprocessor to be stopped.
+ * @mm: The mm the coprocessor associated with.
+ */
+void drop_cop(unsigned long acop, struct mm_struct *mm)
+{
+ int free_pid;
+
+ if (!cpu_has_feature(CPU_FTR_ICSWX))
+ return;
+
+ if (WARN_ON_ONCE(!mm))
+ return;
+
+ /* We need to make sure mm_users doesn't change */
+ down_read(&mm->mmap_sem);
+ spin_lock(mm->context.cop_lockp);
+
+ mm->context.acop &= ~acop;
+
+ free_pid = disable_cop_pid(mm);
+ sync_cop(mm);
+
+ /*
+ * If this is a threaded process then there might be other threads
+ * running. We need to send an IPI to force them to pick up any
+ * change in PID and ACOP.
+ */
+ if (atomic_read(&mm->mm_users) > 1)
+ smp_call_function(sync_cop, mm, 1);
+
+ if (free_pid != COP_PID_NONE)
+ free_cop_pid(free_pid);
+
+ spin_unlock(mm->context.cop_lockp);
+ up_read(&mm->mmap_sem);
+}
+EXPORT_SYMBOL_GPL(drop_cop);
diff --git a/arch/powerpc/mm/icswx.h b/arch/powerpc/mm/icswx.h
new file mode 100644
index 0000000..5121ddd
--- /dev/null
+++ b/arch/powerpc/mm/icswx.h
@@ -0,0 +1,34 @@
+/*
+ * ICSWX and ACOP Management
+ *
+ * Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <asm/mmu_context.h>
+
+/* also used to denote that PIDs are not used */
+#define COP_PID_NONE 0
+
+static inline void sync_cop(void *arg)
+{
+ struct mm_struct *mm = arg;
+
+ if (mm == current->active_mm)
+ switch_cop(current->active_mm);
+}
+
+#ifdef CONFIG_PPC_ICSWX_PID
+extern int get_cop_pid(struct mm_struct *mm);
+extern int disable_cop_pid(struct mm_struct *mm);
+extern void free_cop_pid(int free_pid);
+#else
+#define get_cop_pid(m) (COP_PID_NONE)
+#define disable_cop_pid(m) (COP_PID_NONE)
+#define free_cop_pid(p)
+#endif
diff --git a/arch/powerpc/mm/icswx_pid.c b/arch/powerpc/mm/icswx_pid.c
new file mode 100644
index 0000000..91e30eb
--- /dev/null
+++ b/arch/powerpc/mm/icswx_pid.c
@@ -0,0 +1,87 @@
+/*
+ * ICSWX and ACOP/PID Management
+ *
+ * Copyright (C) 2011 Anton Blanchard, IBM Corp. <anton@samba.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/idr.h>
+#include <linux/module.h>
+#include "icswx.h"
+
+#define COP_PID_MIN (COP_PID_NONE + 1)
+#define COP_PID_MAX (0xFFFF)
+
+static DEFINE_SPINLOCK(mmu_context_acop_lock);
+static DEFINE_IDA(cop_ida);
+
+static int new_cop_pid(struct ida *ida, int min_id, int max_id,
+ spinlock_t *lock)
+{
+ int index;
+ int err;
+
+again:
+ if (!ida_pre_get(ida, GFP_KERNEL))
+ return -ENOMEM;
+
+ spin_lock(lock);
+ err = ida_get_new_above(ida, min_id, &index);
+ spin_unlock(lock);
+
+ if (err == -EAGAIN)
+ goto again;
+ else if (err)
+ return err;
+
+ if (index > max_id) {
+ spin_lock(lock);
+ ida_remove(ida, index);
+ spin_unlock(lock);
+ return -ENOMEM;
+ }
+
+ return index;
+}
+
+int get_cop_pid(struct mm_struct *mm)
+{
+ int pid;
+
+ if (mm->context.cop_pid == COP_PID_NONE) {
+ pid = new_cop_pid(&cop_ida, COP_PID_MIN, COP_PID_MAX,
+ &mmu_context_acop_lock);
+ if (pid >= 0)
+ mm->context.cop_pid = pid;
+ }
+ return mm->context.cop_pid;
+}
+
+int disable_cop_pid(struct mm_struct *mm)
+{
+ int free_pid = COP_PID_NONE;
+
+ if ((!mm->context.acop) && (mm->context.cop_pid != COP_PID_NONE)) {
+ free_pid = mm->context.cop_pid;
+ mm->context.cop_pid = COP_PID_NONE;
+ }
+ return free_pid;
+}
+
+void free_cop_pid(int free_pid)
+{
+ spin_lock(&mmu_context_acop_lock);
+ ida_remove(&cop_ida, free_pid);
+ spin_unlock(&mmu_context_acop_lock);
+}
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index 3bafc3d..a75832c 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -24,201 +24,6 @@
#include <asm/mmu_context.h>
-#ifdef CONFIG_PPC_ICSWX
-/*
- * The processor and its L2 cache cause the icswx instruction to
- * generate a COP_REQ transaction on PowerBus. The transaction has
- * no address, and the processor does not perform an MMU access
- * to authenticate the transaction. The command portion of the
- * PowerBus COP_REQ transaction includes the LPAR_ID (LPID) and
- * the coprocessor Process ID (PID), which the coprocessor compares
- * to the authorized LPID and PID held in the coprocessor, to determine
- * if the process is authorized to generate the transaction.
- * The data of the COP_REQ transaction is 128-byte or less and is
- * placed in cacheable memory on a 128-byte cache line boundary.
- *
- * The task to use a coprocessor should use use_cop() to allocate
- * a coprocessor PID before executing icswx instruction. use_cop()
- * also enables the coprocessor context switching. Drop_cop() is
- * used to free the coprocessor PID.
- *
- * Example:
- * Host Fabric Interface (HFI) is a PowerPC network coprocessor.
- * Each HFI have multiple windows. Each HFI window serves as a
- * network device sending to and receiving from HFI network.
- * HFI immediate send function uses icswx instruction. The immediate
- * send function allows small (single cache-line) packets be sent
- * without using the regular HFI send FIFO and doorbell, which are
- * much slower than immediate send.
- *
- * For each task intending to use HFI immediate send, the HFI driver
- * calls use_cop() to obtain a coprocessor PID for the task.
- * The HFI driver then allocate a free HFI window and save the
- * coprocessor PID to the HFI window to allow the task to use the
- * HFI window.
- *
- * The HFI driver repeatedly creates immediate send packets and
- * issues icswx instruction to send data through the HFI window.
- * The HFI compares the coprocessor PID in the CPU PID register
- * to the PID held in the HFI window to determine if the transaction
- * is allowed.
- *
- * When the task to release the HFI window, the HFI driver calls
- * drop_cop() to release the coprocessor PID.
- */
-
-#define COP_PID_NONE 0
-#define COP_PID_MIN (COP_PID_NONE + 1)
-#define COP_PID_MAX (0xFFFF)
-
-static DEFINE_SPINLOCK(mmu_context_acop_lock);
-static DEFINE_IDA(cop_ida);
-
-void switch_cop(struct mm_struct *next)
-{
- mtspr(SPRN_PID, next->context.cop_pid);
- mtspr(SPRN_ACOP, next->context.acop);
-}
-
-static int new_cop_pid(struct ida *ida, int min_id, int max_id,
- spinlock_t *lock)
-{
- int index;
- int err;
-
-again:
- if (!ida_pre_get(ida, GFP_KERNEL))
- return -ENOMEM;
-
- spin_lock(lock);
- err = ida_get_new_above(ida, min_id, &index);
- spin_unlock(lock);
-
- if (err == -EAGAIN)
- goto again;
- else if (err)
- return err;
-
- if (index > max_id) {
- spin_lock(lock);
- ida_remove(ida, index);
- spin_unlock(lock);
- return -ENOMEM;
- }
-
- return index;
-}
-
-static void sync_cop(void *arg)
-{
- struct mm_struct *mm = arg;
-
- if (mm == current->active_mm)
- switch_cop(current->active_mm);
-}
-
-/**
- * Start using a coprocessor.
- * @acop: mask of coprocessor to be used.
- * @mm: The mm the coprocessor to associate with. Most likely current mm.
- *
- * Return a positive PID if successful. Negative errno otherwise.
- * The returned PID will be fed to the coprocessor to determine if an
- * icswx transaction is authenticated.
- */
-int use_cop(unsigned long acop, struct mm_struct *mm)
-{
- int ret;
-
- if (!cpu_has_feature(CPU_FTR_ICSWX))
- return -ENODEV;
-
- if (!mm || !acop)
- return -EINVAL;
-
- /* We need to make sure mm_users doesn't change */
- down_read(&mm->mmap_sem);
- spin_lock(mm->context.cop_lockp);
-
- if (mm->context.cop_pid == COP_PID_NONE) {
- ret = new_cop_pid(&cop_ida, COP_PID_MIN, COP_PID_MAX,
- &mmu_context_acop_lock);
- if (ret < 0)
- goto out;
-
- mm->context.cop_pid = ret;
- }
- mm->context.acop |= acop;
-
- sync_cop(mm);
-
- /*
- * If this is a threaded process then there might be other threads
- * running. We need to send an IPI to force them to pick up any
- * change in PID and ACOP.
- */
- if (atomic_read(&mm->mm_users) > 1)
- smp_call_function(sync_cop, mm, 1);
-
- ret = mm->context.cop_pid;
-
-out:
- spin_unlock(mm->context.cop_lockp);
- up_read(&mm->mmap_sem);
-
- return ret;
-}
-EXPORT_SYMBOL_GPL(use_cop);
-
-/**
- * Stop using a coprocessor.
- * @acop: mask of coprocessor to be stopped.
- * @mm: The mm the coprocessor associated with.
- */
-void drop_cop(unsigned long acop, struct mm_struct *mm)
-{
- int free_pid = COP_PID_NONE;
-
- if (!cpu_has_feature(CPU_FTR_ICSWX))
- return;
-
- if (WARN_ON_ONCE(!mm))
- return;
-
- /* We need to make sure mm_users doesn't change */
- down_read(&mm->mmap_sem);
- spin_lock(mm->context.cop_lockp);
-
- mm->context.acop &= ~acop;
-
- if ((!mm->context.acop) && (mm->context.cop_pid != COP_PID_NONE)) {
- free_pid = mm->context.cop_pid;
- mm->context.cop_pid = COP_PID_NONE;
- }
-
- sync_cop(mm);
-
- /*
- * If this is a threaded process then there might be other threads
- * running. We need to send an IPI to force them to pick up any
- * change in PID and ACOP.
- */
- if (atomic_read(&mm->mm_users) > 1)
- smp_call_function(sync_cop, mm, 1);
-
- if (free_pid != COP_PID_NONE) {
- spin_lock(&mmu_context_acop_lock);
- ida_remove(&cop_ida, free_pid);
- spin_unlock(&mmu_context_acop_lock);
- }
-
- spin_unlock(mm->context.cop_lockp);
- up_read(&mm->mmap_sem);
-}
-EXPORT_SYMBOL_GPL(drop_cop);
-
-#endif /* CONFIG_PPC_ICSWX */
-
static DEFINE_SPINLOCK(mmu_context_lock);
static DEFINE_IDA(mmu_context_ida);
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index e06e395..3cd22e5 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -234,7 +234,7 @@ config VSX
config PPC_ICSWX
bool "Support for PowerPC icswx coprocessor instruction"
- depends on POWER4
+ depends on POWER4 || PPC_A2
default n
---help---
@@ -250,6 +250,14 @@ config PPC_ICSWX
If in doubt, say N here.
+config PPC_ICSWX_PID
+ bool "icswx requires direct PID management"
+ depends on PPC_ICSWX && POWER4
+ default y
+ ---help---
+ PID register in server is used explicitly for ICSWX. In
+ embedded systems PID managment is done by the system.
+
config SPE
bool "SPE Support"
depends on E200 || (E500 && !PPC_E500MC)
--
1.7.0.4
^ permalink raw reply related
* powerpc: Get icswx to work on both Book3s and Book3e platforms
From: Jimi Xenidis @ 2011-08-08 22:26 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Ian Munsie, Anton Blanchard
The following patches deal with the fact that Book3e parts already
have a PID register that is managed by the system. Currently an ICSWX
not in the ACOP will get rejected as specified by both architectures.
-JX
^ permalink raw reply
* [PATCH] powerpc: wsp: Fix Wire Speed Processor platform configs
From: Jimi Xenidis @ 2011-08-08 21:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Ian Munsie
Some config selections were applied to the platform (reference board)
when they actuall apply to the chip.
Signed-off-by: Jimi Xenidis <jimix@pobox.com>
---
arch/powerpc/platforms/wsp/Kconfig | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig
index c3c48eb..d051581 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -1,5 +1,9 @@
config PPC_WSP
bool
+ select PPC_A2
+ select PPC_SCOM
+ select PPC_XICS
+ select PPC_ICP_NATIVE
default n
menu "WSP platform selection"
@@ -7,13 +11,9 @@ menu "WSP platform selection"
config PPC_PSR2
bool "PSR-2 platform"
- select PPC_A2
select GENERIC_TBSYNC
- select PPC_SCOM
select EPAPR_BOOT
select PPC_WSP
- select PPC_XICS
- select PPC_ICP_NATIVE
default y
endmenu
--
1.7.0.4
^ permalink raw reply related
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