* Re: [PATCH 4/7] powerpc/85xx: add support to JOG feature using cpufreq interface
From: Zhao Chenhui @ 2011-11-07 10:27 UTC (permalink / raw)
To: Scott Wood; +Cc: Jerry Huang, linuxppc-dev
In-Reply-To: <4EB4403E.3040700@freescale.com>
On Fri, Nov 04, 2011 at 02:42:54PM -0500, Scott Wood wrote:
> On 11/04/2011 07:36 AM, Zhao Chenhui wrote:
> > From: Li Yang <leoli@freescale.com>
> >
> > Some 85xx silicons like MPC8536 and P1022 has the JOG PM feature.
> >
> > The patch adds the support to change CPU frequency using the standard
> > cpufreq interface. Add the all PLL ratio core support. The ratio CORE
> > to CCB can 1:1, 1.5, 2:1, 2.5:1, 3:1, 3.5:1 and 4:1
> >
> > Signed-off-by: Dave Liu <daveliu@freescale.com>
> > Signed-off-by: Li Yang <leoli@freescale.com>
> > Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
> > Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> > ---
> > arch/powerpc/platforms/85xx/Makefile | 1 +
> > arch/powerpc/platforms/85xx/cpufreq.c | 255 +++++++++++++++++++++++++++++++++
> > arch/powerpc/platforms/Kconfig | 8 +
> > 3 files changed, 264 insertions(+), 0 deletions(-)
> > create mode 100644 arch/powerpc/platforms/85xx/cpufreq.c
>
> Please name this something more specific, such as 85xx/cpufreq-jog.c
>
> Other 85xx/qoriq chips, such as p4080, have different mechanisms for
> updating CPU frequency.
>
> > +static struct cpufreq_frequency_table mpc85xx_freqs[] = {
> > + {2, 0},
> > + {3, 0},
> > + {4, 0},
> > + {5, 0},
> > + {6, 0},
> > + {7, 0},
> > + {8, 0},
> > + {0, CPUFREQ_TABLE_END},
> > +};
>
> Only p1022 can handle 1:1 (index 2).
>
> > +static void set_pll(unsigned int pll, int cpu)
> > +{
> > + int shift;
> > + u32 busfreq, corefreq, val;
> > + u32 core_spd, mask, tmp;
> > +
> > + tmp = in_be32(guts + PMJCR);
> > + shift = (cpu == 1) ? CORE1_RATIO_SHIFT : CORE0_RATIO_SHIFT;
> > + busfreq = fsl_get_sys_freq();
> > + val = (pll & CORE_RATIO_MASK) << shift;
> > +
> > + corefreq = ((busfreq * pll) >> 1);
>
> Use "/ 2", not ">> 1". Same asm code, more readable.
>
> > + /* must set the bit[18/19] if the requested core freq > 533 MHz */
> > + core_spd = (cpu == 1) ? PMJCR_CORE1_SPD_MASK : PMJCR_CORE0_SPD_MASK;
> > + if (corefreq > FREQ_533MHz)
> > + val |= core_spd;
>
> this is the cutoff for p1022 -- on mpc8536 the manual says the cutoff is
> 800 MHz.
>
> > + mask = (cpu == 1) ? (PMJCR_CORE1_RATIO_MASK | PMJCR_CORE1_SPD_MASK) :
> > + (PMJCR_CORE0_RATIO_MASK | PMJCR_CORE0_SPD_MASK);
> > + tmp &= ~mask;
> > + tmp |= val;
> > + out_be32(guts + PMJCR, tmp);
>
> clrsetbits_be32()
>
> > + val = in_be32(guts + PMJCR);
> > + out_be32(guts + POWMGTCSR,
> > + POWMGTCSR_LOSSLESS_MASK | POWMGTCSR_JOG_MASK);
>
> setbits32()
>
> > + pr_debug("PMJCR request %08x at CPU %d\n", tmp, cpu);
> > +}
> > +
> > +static void verify_pll(int cpu)
> > +{
> > + int shift;
> > + u32 busfreq, pll, corefreq;
> > +
> > + shift = (cpu == 1) ? CORE1_RATIO_SHIFT : CORE0_RATIO_SHIFT;
> > + busfreq = fsl_get_sys_freq();
> > + pll = (in_be32(guts + PORPLLSR) >> shift) & CORE_RATIO_MASK;
> > +
> > + corefreq = (busfreq * pll) >> 1;
> > + corefreq /= 1000000;
> > + pr_debug("PORPLLSR core freq %dMHz at CPU %d\n", corefreq, cpu);
> > +}
>
> It looks like the entire point of this function is to make a debug
> print... #ifdef DEBUG the contents? Or if we mark fsl_get_sys_freq()
> as __pure (or better, read this once at init, since it involves
> searching the device tree), will it all get optimized away?
>
>
> > + /* initialize frequency table */
> > + pr_info("core %d frequency table:\n", policy->cpu);
> > + for (i = 0; mpc85xx_freqs[i].frequency != CPUFREQ_TABLE_END; i++) {
> > + mpc85xx_freqs[i].frequency =
> > + (busfreq * mpc85xx_freqs[i].index) >> 1;
> > + pr_info("%d: %dkHz\n", i, mpc85xx_freqs[i].frequency);
> > + }
>
> This should be pr_debug.
>
> > + /* the latency of a transition, the unit is ns */
> > + policy->cpuinfo.transition_latency = 2000;
> > +
> > + cur_pll = get_pll(policy->cpu);
> > + pr_debug("current pll is at %d\n", cur_pll);
> > +
> > + for (i = 0; mpc85xx_freqs[i].frequency != CPUFREQ_TABLE_END; i++) {
> > + if (mpc85xx_freqs[i].index == cur_pll)
> > + policy->cur = mpc85xx_freqs[i].frequency;
> > + }
>
> You could combine these loops.
>
> > + /* this ensures that policy->cpuinfo_min
> > + * and policy->cpuinfo_max are set correctly */
>
> comment style
>
> > +static int mpc85xx_cpufreq_target(struct cpufreq_policy *policy,
> > + unsigned int target_freq,
> > + unsigned int relation)
> > +{
> > + struct cpufreq_freqs freqs;
> > + unsigned int new;
> > +
> > + cpufreq_frequency_table_target(policy,
> > + mpc85xx_freqs,
> > + target_freq,
> > + relation,
> > + &new);
> > +
> > + freqs.old = policy->cur;
> > + freqs.new = mpc85xx_freqs[new].frequency;
> > + freqs.cpu = policy->cpu;
> > +
> > + mutex_lock(&mpc85xx_switch_mutex);
> > + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> > +
> > + pr_info("Setting frequency for core %d to %d kHz, " \
> > + "PLL ratio is %d/2\n",
> > + policy->cpu,
> > + mpc85xx_freqs[new].frequency,
> > + mpc85xx_freqs[new].index);
> > +
> > + set_pll(mpc85xx_freqs[new].index, policy->cpu);
> > +
> > + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
> > + mutex_unlock(&mpc85xx_switch_mutex);
> > +
> > + ppc_proc_freq = freqs.new * 1000ul;
>
> ppc_proc_freq is global -- can CPUs not have their frequencies adjusted
> separately?
>
> It should be under the lock, if the lock is needed at all.
>
There is only one ppc_proc_freq. no lock.
> > +/*
> > + * module init and destoy
> > + */
> > +static struct of_device_id mpc85xx_jog_ids[] __initdata = {
> > + { .compatible = "fsl,mpc8536-guts", },
> > + { .compatible = "fsl,p1022-guts", },
> > + {}
> > +};
> > +
> > +static int __init mpc85xx_cpufreq_init(void)
> > +{
> > + struct device_node *np;
> > +
> > + pr_info("Freescale MPC85xx CPU frequency switching driver\n");
>
> If you're going to print something here, print it after you find a node
> you can work with -- not on all 85xx/qoriq that have this driver enabled.
>
> -Scott
Thanks. I will fix them all.
-chenhui
^ permalink raw reply
* [RFC PATCH v4 00/10] fadump: Firmware-assisted dump support for Powerpc.
From: Mahesh J Salgaonkar @ 2011-11-07 9:55 UTC (permalink / raw)
To: linuxppc-dev, Linux Kernel, Benjamin Herrenschmidt
Cc: Amerigo Wang, Milton Miller, Eric W. Biederman, Anton Blanchard
Hi All,
Please find the version 4 of the patchset that implements firmware-assisted
dump mechanism to capture kernel crash dump for Powerpc architecture. The
firmware-assisted dump is a robust mechanism to get reliable kernel crash
dump with assistance from firmware. This approach does not use kexec, instead
firmware assists in booting the kdump kernel while preserving memory contents.
Changes in v4:
--------------
patch 04/10:
- Move the init_elfcore_header() function and 'memblock_num_regions' macro
from generic code to power specific code as these are used only by
firmware assisted dump implementation which is power specific feature.
patch 05/10:
- Fixes a issue where memblock_free() is invoked from build_cpu_notes()
function during error_out path. Invoke cpu_notes_buf_free() in error_out
path instead of memblock_free().
Changes in v3:
-------------
- Re-factored the implementation to work with kdump service start/stop.
Introduce fadump_registered sysfs control file which will be used by
kdump init scripts to start/stop firmware assisted dump. echo 1 to
/sys/kernel/fadump_registered file for fadump registration and
echo 0 to /sys/kernel/fadump_registered file for fadump un-registration.
- Introduced the locking mechanism to handle simultaneous writes to
sysfs control files fadump_registered and fadump_release_mem
Affected patches are: 01/10, 03/10, 08/10.
Changes in v2:
-------------
patch 01/10:
- Modified the documentation to reflect the change of fadump_region
file under debugfs filesystem.
patch 02/10:
- Modified to use standard pr_debug() macro.
- Modified early_init_dt_scan_fw_dump() to get the size of
"ibm,configure-kernel-dump-sizes" property and use it to iterate through
an array of dump sections.
- Introduced boot option 'fadump_reserve_mem=' to let user specify the
fadump boot memory to be reserved.
patch 03/10:
- Removed few debug print statements.
- Moved the setup_fadump() call from setup_system() and now calling it
subsys_initcall.
- Moved fadump_region attribute under debugfs.
- Clear the TCE entries if firmware assisted dump is active.
patch 05/10:
- Moved the crash_fadump() invocation from generic code to panic notifier.
- Introduced cpu_notes_buf_alloc() function to allocate cpu notes buffer
using get_free_pages().
patch 08/10:
- Introduced cpu_notes_buf_free() function to free memory allocated for
cpu notes buffer.
The most of the code implementation has been adapted from phyp assisted dump
implementation written by Linas Vepstas and Manish Ahuja.
The first patch is a documentation that talks about firmware-assisted dump
mechanism, implementation details and TODO list.
I have tested the patches on following system configuration:
1. LPAR on Power6 with 4GB RAM and 8 CPUs
2. LPAR on Power7 with 2GB RAM and 20 CPUs
3. LPAR on Power7 with 1TB RAM and 896 CPUs
These patches cleanly apply on commit c3b92c878 in linux-2.6 git tree.
Please review the patchset and let me know your comments.
Thanks,
-Mahesh.
---
Mahesh Salgaonkar (10):
fadump: Add documentation for firmware-assisted dump.
fadump: Reserve the memory for firmware assisted dump.
fadump: Register for firmware assisted dump.
fadump: Initialize elfcore header and add PT_LOAD program headers.
fadump: Convert firmware-assisted cpu state dump data into elf notes.
fadump: Add PT_NOTE program header for vmcoreinfo
fadump: Introduce cleanup routine to invalidate /proc/vmcore.
fadump: Invalidate registration and release reserved memory for general use.
fadump: Invalidate the fadump registration during machine shutdown.
fadump: Introduce config option for firmware assisted dump feature
Documentation/powerpc/firmware-assisted-dump.txt | 262 ++++
arch/powerpc/Kconfig | 13
arch/powerpc/include/asm/fadump.h | 211 ++++
arch/powerpc/kernel/Makefile | 1
arch/powerpc/kernel/fadump.c | 1313 ++++++++++++++++++++++
arch/powerpc/kernel/iommu.c | 8
arch/powerpc/kernel/prom.c | 15
arch/powerpc/kernel/setup-common.c | 16
arch/powerpc/kernel/traps.c | 5
arch/powerpc/mm/hash_utils_64.c | 11
fs/proc/vmcore.c | 23
11 files changed, 1876 insertions(+), 2 deletions(-)
create mode 100644 Documentation/powerpc/firmware-assisted-dump.txt
create mode 100644 arch/powerpc/include/asm/fadump.h
create mode 100644 arch/powerpc/kernel/fadump.c
--
Signature
^ permalink raw reply
* suspecting ibm_newemac driver problem.
From: suggest @ 2011-11-07 10:33 UTC (permalink / raw)
To: linuxppc-dev
Hello All,
I am using ppc460ex based custom board.
using linux 2.6.30.2 kernel on this board it has ibm_newemac driver in it.
I am using this board as a iSCSI target which has RAID system behind it.
||
|| ||
||
n/w driver (ibm_newemac) || n/w layer || iSCSI Target ||
RAID
|| ||
||
The problem i am facing is when i start iometer based i/o.
I am doing i/o with following specifications.
Workload type : All in one.
no of outstanding i/o : 32.
no of worker threads : 8.
With this kind of workload n/w stucks in between. and board becomes
unresponsive.
If i try to ping to the board then ping fails with 100% packet loss.
While debugging the issue i found out that
sock->sk_state_change callback is called from the TCP layer and state of the
socket is not TCP_ESTABLISHED in the iSCSI target driver.
So i am assuming that this is a problem related to n/w driver.
Did anyone faced similar kind of issue before? Please point me in right
direction.
Thanks and Regards,
Harshal Shete.
--
View this message in context: http://old.nabble.com/suspecting-ibm_newemac-driver-problem.-tp32788715p32788715.html
Sent from the linuxppc-dev mailing list archive at Nabble.com.
^ permalink raw reply
* Re: [PATCH 6/7] fsl_pmc: Add API to enable device as wakeup event source
From: Zhao Chenhui @ 2011-11-07 11:24 UTC (permalink / raw)
To: Tabi Timur-B04825
Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
Li Yang-R58472, Zhao Chenhui-B35336
In-Reply-To: <CAOZdJXXB9zJWqC+kPq7ZDdzePtp8XNBnWcf5UmE8Ye50U-G7Dg@mail.gmail.com>
On Fri, Nov 04, 2011 at 07:08:24PM -0500, Tabi Timur-B04825 wrote:
> On Fri, Nov 4, 2011 at 7:39 AM, Zhao Chenhui <chenhui.zhao@freescale.co=
m> wrote:
>=20
> > + =A0 =A0 =A0 if (!pmc_regs) {
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_WARNING "PMC is unavailable=
\n");
>=20
> Use pr_warn() and the other pr_xxx functions.
>=20
> > + =A0 =A0 =A0 pmcdr_mask =3D (u32 *)of_get_property(clk_np, "fsl,pmcd=
r-mask", NULL);
>=20
> The typecast is unnecessary here.
>=20
> > + =A0 =A0 =A0 /* clear to enable clock in low power mode */
> > + =A0 =A0 =A0 if (enable)
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 clrbits32(&pmc_regs->pmcdr, *pmcdr_mask=
);
> > + =A0 =A0 =A0 else
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 setbits32(&pmc_regs->pmcdr, *pmcdr_mask=
);
>=20
> You need to use be32_to_cpup() when dereferencing a pointer to a
> device tree property.
>=20
> --=20
> Timur Tabi
> Linux kernel developer at Freescale
Thanks. I will fix them all.
-chenhui
^ permalink raw reply
* Re: [PATCH 6/7] fsl_pmc: Add API to enable device as wakeup event source
From: Zhao Chenhui @ 2011-11-07 11:22 UTC (permalink / raw)
To: Scott Wood; +Cc: netdev, linuxppc-dev
In-Reply-To: <4EB455B1.8030009@freescale.com>
On Fri, Nov 04, 2011 at 04:14:25PM -0500, Scott Wood wrote:
> On 11/04/2011 07:39 AM, Zhao Chenhui wrote:
> > @@ -45,6 +46,72 @@ static int has_lossless;
> > * code can be compatible with both 32-bit & 36-bit */
> > extern void mpc85xx_enter_deep_sleep(u64 ccsrbar, u32 powmgtreq);
> >
> > +#ifdef CONFIG_FSL_PMC
> > +/**
> > + * pmc_enable_wake - enable OF device as wakeup event source
> > + * @pdev: platform device affected
> > + * @state: PM state from which device will issue wakeup events
> > + * @enable: True to enable event generation; false to disable
> > + *
> > + * This enables the device as a wakeup event source, or disables it.
> > + *
> > + * RETURN VALUE:
> > + * 0 is returned on success
> > + * -EINVAL is returned if device is not supposed to wake up the system
> > + * Error code depending on the platform is returned if both the platform and
> > + * the native mechanism fail to enable the generation of wake-up events
> > + */
> > +int pmc_enable_wake(struct platform_device *pdev,
> > + suspend_state_t state, bool enable)
>
> "pmc" is too generic for a global function. If this can be either
> enable or disable, perhaps it should be something like
> mpc85xx_pmc_set_wake().
>
> > +{
> > + int ret = 0;
> > + struct device_node *clk_np;
> > + u32 *pmcdr_mask;
> > +
> > + if (!pmc_regs) {
> > + printk(KERN_WARNING "PMC is unavailable\n");
> > + return -ENOMEM;
> > + }
>
> -ENOMEM is not appropriate here, maybe -ENODEV?
>
> Should print __func__ so the user knows what's complaining.
>
> > + if (enable && !device_may_wakeup(&pdev->dev))
> > + return -EINVAL;
> > +
> > + clk_np = of_parse_phandle(pdev->dev.of_node, "clk-handle", 0);
> > + if (!clk_np)
> > + return -EINVAL;
> > +
> > + pmcdr_mask = (u32 *)of_get_property(clk_np, "fsl,pmcdr-mask", NULL);
> > + if (!pmcdr_mask) {
> > + ret = -EINVAL;
> > + goto out;
> > + }
> > +
> > + /* clear to enable clock in low power mode */
> > + if (enable)
> > + clrbits32(&pmc_regs->pmcdr, *pmcdr_mask);
> > + else
> > + setbits32(&pmc_regs->pmcdr, *pmcdr_mask);
>
> We should probably initialize PMCDR to all bits set (or at least all
> ones we know are valid) -- the default should be "not a wakeup source".
I think it should be initialized in u-boot.
>
> > +/**
> > + * pmc_enable_lossless - enable lossless ethernet in low power mode
> > + * @enable: True to enable event generation; false to disable
> > + */
> > +void pmc_enable_lossless(int enable)
> > +{
> > + if (enable && has_lossless)
> > + setbits32(&pmc_regs->pmcsr, PMCSR_LOSSLESS);
> > + else
> > + clrbits32(&pmc_regs->pmcsr, PMCSR_LOSSLESS);
> > +}
> > +EXPORT_SYMBOL_GPL(pmc_enable_lossless);
> > +#endif
>
> Won't we overwrite this later?
>
> -Scott
Do you have any idea?
-chenhui
^ permalink raw reply
* [PATCH] gpio: mpc8xxx: don't allow input-only pins to be output for MPC5121
From: Wolfram Sang @ 2011-11-07 13:21 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Anatolij Gustschin
Add a 5121-custom reject if an input-only pin is requested to be output
(see 18.3.1.1 in the refman). Also, rewrite mach-specific quirk setup to
consume less lines.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
---
drivers/gpio/gpio-mpc8xxx.c | 17 ++++++++++++-----
1 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index ec3fcf0..25dc736 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -115,6 +115,14 @@ static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
return 0;
}
+static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ /* GPIO 28..31 are input only on MPC5121 */
+ if (gpio >= 28)
+ return -EINVAL;
+
+ return mpc8xxx_gpio_dir_out(gc, gpio, val);
+}
static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
@@ -340,11 +348,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
mm_gc->save_regs = mpc8xxx_gpio_save_regs;
gc->ngpio = MPC8XXX_GPIO_PINS;
gc->direction_input = mpc8xxx_gpio_dir_in;
- gc->direction_output = mpc8xxx_gpio_dir_out;
- if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
- gc->get = mpc8572_gpio_get;
- else
- gc->get = mpc8xxx_gpio_get;
+ gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
+ mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
+ gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
+ mpc8572_gpio_get : mpc8xxx_gpio_get;
gc->set = mpc8xxx_gpio_set;
gc->to_irq = mpc8xxx_gpio_to_irq;
--
1.7.7.1
^ permalink raw reply related
* Re: [PATCH v2 1/5] [ppc] Process dynamic relocations for kernel
From: Josh Poimboeuf @ 2011-11-07 15:13 UTC (permalink / raw)
To: Suzuki Poulose
Cc: Nathan Miller, Josh Poimboeuf, Dave Hansen, Alan Modra,
Scott Wood, Paul Mackerras, linuxppc-dev
In-Reply-To: <4EB3A40C.1070802@in.ibm.com>
On Fri, 2011-11-04 at 14:06 +0530, Suzuki Poulose wrote:
> On 11/03/11 05:06, Josh Poimboeuf wrote:
> > On Tue, 2011-10-25 at 17:23 +0530, Suzuki K. Poulose wrote:
> > @@ -137,6 +137,9 @@ get_type:
> > lwz r0, 8(r9) /* r_addend */
> > add r0, r0, r3 /* final addend */
> > stwx r0, r4, r7 /* memory[r4+r7]) = (u32)r0 */
> > + dcbst r4,r7 /* flush dcache line to memory */
> > + sync /* wait for flush to complete */
> > + icbi r4,r7 /* invalidate icache line */
>
> Doing it this way has two drawbacks :
>
> 1) Placing it here in relocate would do the flushing for each and every update.
I agree. My kernel had around 80,000 relocations, which means 80,000
d-cache line flushes (for a 32k d-cache) and 80,000 i-cache line
invalidates (for a 32k i-cache). Which is obviously a little overkill.
Although I didn't notice a performance hit during boot.
> 2) I would like to keep this code as generic as possible for the PPC32 code.
>
> Could we move this to the place from relocate is called and flush the d-cache and
> i-cache entirely ?
Why not put the cache flushing code at the end of relocate? Would some
of the other PPC32 platforms not require the cache flushing?
My PPC32 knowledge is 4xx-centric, so please feel free to rewrite the
patch as needed to accommodate other PPC32 cores.
Thanks,
Josh
^ permalink raw reply
* RE: [PATCH v2 1/5] [ppc] Process dynamic relocations for kernel
From: David Laight @ 2011-11-07 15:26 UTC (permalink / raw)
To: Josh Poimboeuf, Suzuki Poulose
Cc: Nathan Miller, Josh Poimboeuf, Dave Hansen, Alan Modra,
Scott Wood, Paul Mackerras, linuxppc-dev
In-Reply-To: <1320678819.2750.15.camel@treble>
=20
> On Fri, 2011-11-04 at 14:06 +0530, Suzuki Poulose wrote:
> > On 11/03/11 05:06, Josh Poimboeuf wrote:
> > > On Tue, 2011-10-25 at 17:23 +0530, Suzuki K. Poulose wrote:
> > > @@ -137,6 +137,9 @@ get_type:
> > > lwz r0, 8(r9) /* r_addend */
> > > add r0, r0, r3 /* final addend */
> > > stwx r0, r4, r7 /* memory[r4+r7]) =3D (u32)r0 */
> > > + dcbst r4,r7 /* flush dcache line to memory */
> > > + sync /* wait for flush to complete */
> > > + icbi r4,r7 /* invalidate icache line */
> >=20
> > Doing it this way has two drawbacks :
> >=20
> > 1) Placing it here in relocate would do the flushing for=20
> each and every update.
>=20
> I agree. My kernel had around 80,000 relocations, which means 80,000
> d-cache line flushes (for a 32k d-cache) and 80,000 i-cache line
> invalidates (for a 32k i-cache). Which is obviously a little=20
> overkill.
> Although I didn't notice a performance hit during boot.
The I-cache invalidates shouldn't be needed, the un-relocated
code can't be in the I-cache (on the grounds that executing
it would crash the system).
A single sync at the end is probably enough as well.
I guess it is possible for the cpu to prefetch/preload
into the i-cache through the jump into the relocated code?
So maybe a full i-cache invalidate right at the end? (or
a jump indirect? - which is probably there anyway)
The d-cache will need some kind of flush, since the modified
lines have to be written out, the only time it generates
additional memeory cycles are if there are two (or more)
reloations in the same d-cache line. Otherwise the early
write-back might help!
David
^ permalink raw reply
* Re: [PATCH 6/7] fsl_pmc: Add API to enable device as wakeup event source
From: Scott Wood @ 2011-11-07 15:49 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: netdev, linuxppc-dev
In-Reply-To: <20111107112236.GB16470@localhost.localdomain>
On 11/07/2011 05:22 AM, Zhao Chenhui wrote:
> On Fri, Nov 04, 2011 at 04:14:25PM -0500, Scott Wood wrote:
>> On 11/04/2011 07:39 AM, Zhao Chenhui wrote:
>>> + if (enable && !device_may_wakeup(&pdev->dev))
>>> + return -EINVAL;
>>> +
>>> + clk_np = of_parse_phandle(pdev->dev.of_node, "clk-handle", 0);
>>> + if (!clk_np)
>>> + return -EINVAL;
>>> +
>>> + pmcdr_mask = (u32 *)of_get_property(clk_np, "fsl,pmcdr-mask", NULL);
>>> + if (!pmcdr_mask) {
>>> + ret = -EINVAL;
>>> + goto out;
>>> + }
>>> +
>>> + /* clear to enable clock in low power mode */
>>> + if (enable)
>>> + clrbits32(&pmc_regs->pmcdr, *pmcdr_mask);
>>> + else
>>> + setbits32(&pmc_regs->pmcdr, *pmcdr_mask);
>>
>> We should probably initialize PMCDR to all bits set (or at least all
>> ones we know are valid) -- the default should be "not a wakeup source".
>
> I think it should be initialized in u-boot.
I don't see it. If you mean you think this should be added to U-Boot, I
disagree. U-Boot does not use this, and we should not add gratuitous
U-Boot dependencies to Linux -- especially in cases where there are
existing U-Boots in use for relevant boards, that do not have this.
>>> +/**
>>> + * pmc_enable_lossless - enable lossless ethernet in low power mode
>>> + * @enable: True to enable event generation; false to disable
>>> + */
>>> +void pmc_enable_lossless(int enable)
>>> +{
>>> + if (enable && has_lossless)
>>> + setbits32(&pmc_regs->pmcsr, PMCSR_LOSSLESS);
>>> + else
>>> + clrbits32(&pmc_regs->pmcsr, PMCSR_LOSSLESS);
>>> +}
>>> +EXPORT_SYMBOL_GPL(pmc_enable_lossless);
>>> +#endif
>>
>> Won't we overwrite this later?
>>
>> -Scott
>
> Do you have any idea?
Set a flag that the code that enters (deep) sleep can use.
Also, rename function to mpc85xx_pmc_set_lossless_ethernet().
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc: Export PIR data through sysfs
From: Scott Wood @ 2011-11-07 17:18 UTC (permalink / raw)
To: ananth; +Cc: linuxppc-dev, Anton Blanchard, mahesh
In-Reply-To: <20111107044750.GB4361@in.ibm.com>
On 11/06/2011 10:47 PM, Ananth N Mavinakayanahalli wrote:
> The Processor Identification Register (PIR) on powerpc provides
> information to decode the processor identification tag. Decoding
> this information platform specfic.
>
> Export PIR data via sysfs.
>
> (Powerpc manuals state this register is 'optional'. I am not sure
> though if there are any Linux supported powerpc platforms that
> don't have it. Code in the kernel referencing PIR isn't under
> a platform ifdef).
Those references are in platform-specific files, under #ifdef
CONFIG_SMP, often in areas that would only be executed in the presence
of multiple CPUs (e.g. secondary release). The reference in misc_32.S
is inside #ifdef CONFIG_KEXEC and is fairly recent -- it may not have
been tested on these systems.
I don't see PIR (other than in the acronym definition section) in
manuals for UP-only cores such as e300, 8xx, and 750.
What use does userspace have for this? If you want to return the
currently executing CPU (which unless you're pinned could change as soon
as the value is read...), why not just return smp_processor_id() or
hard_smp_processor_id()?
-Scott
^ permalink raw reply
* Re: [PATCH 2/4] powerpc/time: Use clocksource_register_hz
From: john stultz @ 2011-11-07 18:26 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Anton Blanchard
In-Reply-To: <20111105005551.GB31510@bloggs.ozlabs.ibm.com>
On Sat, 2011-11-05 at 11:55 +1100, Paul Mackerras wrote:
> On Thu, Nov 03, 2011 at 09:14:44AM -0400, John Stultz wrote:
> > On Thu, 2011-11-03 at 11:59 +1100, Anton Blanchard wrote:
> > > plain text document attachment (clock3)
> > > Use clocksource_register_hz which calculates the shift/mult
> > > factors for us.
> > >
> > > Signed-off-by: Anton Blanchard <anton@samba.org>
> > > ---
> > >
> > > Index: linux-build/arch/powerpc/kernel/time.c
> > > ===================================================================
> > > --- linux-build.orig/arch/powerpc/kernel/time.c 2011-11-03 10:19:59.493679032 +1100
> > > +++ linux-build/arch/powerpc/kernel/time.c 2011-11-03 10:20:00.965704053 +1100
> > > @@ -86,8 +86,6 @@ static struct clocksource clocksource_rt
> > > .rating = 400,
> > > .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> > > .mask = CLOCKSOURCE_MASK(64),
> > > - .shift = 22,
> > > - .mult = 0, /* To be filled in */
> > > .read = rtc_read,
> > > };
> > >
> > > @@ -97,8 +95,6 @@ static struct clocksource clocksource_ti
> > > .rating = 400,
> > > .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> > > .mask = CLOCKSOURCE_MASK(64),
> > > - .shift = 22,
> > > - .mult = 0, /* To be filled in */
> > > .read = timebase_read,
> > > };
> >
> > So I've held off on ppc conversion to clocksource_register_hz due to the
> > fact that the ppc vdso gettimeofday at least used to make assumptions
> > that shift was 22.
> >
> > Is that no longer the case?
>
> It is still the case; specifically, update_vsyscall() in
> arch/powerpc/kernel/time.c converts a multiplier value to a 'tb_to_xs'
> multiplier (timebase to xsec conversion factor, where 1 xsec = 2^-20
> seconds) using a factor which assumes a shift of 22. The factor needs
> to be 2^(20 + 64 - shift) / 1e9, so we could accommodate other shift
> values by changing the line that computes new_tb_to_xs to do
>
> new_tb_to_xs = (u64) mult * (19342813113834067ULL >> shift);
>
> assuming the shift value is easily available to update_vsyscall
> (I assume it would be clock->shift).
Ok. That sounds reasonable. clock->shift should be correct there.
thanks
-john
^ permalink raw reply
* Re: [PATCH 6/7] fsl_pmc: Add API to enable device as wakeup event source
From: Scott Wood @ 2011-11-07 18:41 UTC (permalink / raw)
To: Tabi Timur-B04825
Cc: netdev@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
Li Yang-R58472, Zhao Chenhui-B35336
In-Reply-To: <CAOZdJXXB9zJWqC+kPq7ZDdzePtp8XNBnWcf5UmE8Ye50U-G7Dg@mail.gmail.com>
On 11/04/2011 07:08 PM, Tabi Timur-B04825 wrote:
> On Fri, Nov 4, 2011 at 7:39 AM, Zhao Chenhui <chenhui.zhao@freescale.com> wrote:
>> + /* clear to enable clock in low power mode */
>> + if (enable)
>> + clrbits32(&pmc_regs->pmcdr, *pmcdr_mask);
>> + else
>> + setbits32(&pmc_regs->pmcdr, *pmcdr_mask);
>
> You need to use be32_to_cpup() when dereferencing a pointer to a
> device tree property.
Or just use of_property_read_u32().
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe
From: Scott Wood @ 2011-11-07 18:44 UTC (permalink / raw)
To: Roy Zang; +Cc: linuxppc-dev
In-Reply-To: <1320654778-3294-1-git-send-email-tie-fei.zang@freescale.com>
On 11/07/2011 02:32 AM, Roy Zang wrote:
> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.
Some extra commentary on why this works would be nice.
The manual says:
> If a PCI Express INTx interrupt is being used, then the PIC must be configured so that external interrupts
> are level-sensitive (EIVPRn[S] = 1).
and
> In general, these signals should be considered mutually exclusive. If a PCI Express INTx signal is being
> used, the PIC must be configured so that external interrupts are level sensitive (EIVPRn[S] = 1). If an IRQn
> signal is being used as edge-triggered (EIVPRn[S] = 0), the system must not allow inbound PCI Express
> INTx transactions.
>
> Note that it is possible to share IRQn and INTx if the external interrupt is level sensitive; however, if an
> interrupt occurs, the interrupt service routine must poll both the external sources connected to the IRQn
> input and the PCI Express INTx sources to determine from which path the external interrupt came. In any
> case, IRQn should be pulled to the negated state as determined by the associated polarity setting in
> EIVPRn[P].
So it looks like there's some magic whereby the configuration of the
MPIC affects how the PCIe feeds the interrupt in.
Is there (or will there be) an erratum, or anything in the manual
besides not being documented as external interrupts, about these
specific interrupts being tied low in silicon or needing to be active high?
-Scott
^ permalink raw reply
* RE: fpga driver on custom PPC target platform (P4080) ...
From: Robert Sciuk @ 2011-11-07 18:48 UTC (permalink / raw)
To: David Gibson; +Cc: linuxppc-dev, devicetree-discuss, Tabi Timur-B04825
In-Reply-To: <20111105004050.GA1384@truffala.fritz.box>
> > Ah, my compatible attribute was wrong:
> >
> > Compatible =3D "nxp,pca9539";
> >
> > Should have been:
> >
> > Compatible =3D "nxp,pca953x";
> >
> > The tree now seems to bind the i2c gpio drivers properly ... on to
> > the localbus mappings!
>=20
> Ah. In that case the drivers should probably be extended to recognize
> the first compatible. "wildcard" compatible strings are a bad idea,
> unfortunately there are some already in the wild, as you've seen. We
> should try to phase them out though.
>=20
> --
> David Gibson | I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_
> _other_
> | _way_ _around_!
> http://www.ozlabs.org/~dgibson
Thanks, David
It did occur that a specific binding should be preferred over a generic =
one=20
Rob.
^ permalink raw reply
* Re: [PATCH 4/7] powerpc/85xx: add support to JOG feature using cpufreq interface
From: Scott Wood @ 2011-11-07 18:50 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: Jerry Huang, linuxppc-dev
In-Reply-To: <20111107102724.GA16470@localhost.localdomain>
On 11/07/2011 04:27 AM, Zhao Chenhui wrote:
> On Fri, Nov 04, 2011 at 02:42:54PM -0500, Scott Wood wrote:
>> On 11/04/2011 07:36 AM, Zhao Chenhui wrote:
>>> + cpufreq_frequency_table_target(policy,
>>> + mpc85xx_freqs,
>>> + target_freq,
>>> + relation,
>>> + &new);
>>> +
>>> + freqs.old = policy->cur;
>>> + freqs.new = mpc85xx_freqs[new].frequency;
>>> + freqs.cpu = policy->cpu;
>>> +
>>> + mutex_lock(&mpc85xx_switch_mutex);
>>> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
>>> +
>>> + pr_info("Setting frequency for core %d to %d kHz, " \
>>> + "PLL ratio is %d/2\n",
>>> + policy->cpu,
>>> + mpc85xx_freqs[new].frequency,
>>> + mpc85xx_freqs[new].index);
>>> +
>>> + set_pll(mpc85xx_freqs[new].index, policy->cpu);
>>> +
>>> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
>>> + mutex_unlock(&mpc85xx_switch_mutex);
>>> +
>>> + ppc_proc_freq = freqs.new * 1000ul;
>>
>> ppc_proc_freq is global -- can CPUs not have their frequencies adjusted
>> separately?
>>
>> It should be under the lock, if the lock is needed at all.
>>
>
> There is only one ppc_proc_freq. no lock.
I realize there's only one.
I'm asking whether CPUs can have their frequencies set indpendently --
if the answer is no, and this function is not specific to a CPU, my only
concern is the lock. Either this function can be called multiple times
in parallel, in which case the ppc_proc_freq update should be inside the
lock, or it can't, in which case why do we need the lock at all?
-Scott
^ permalink raw reply
* RE: fpga driver on custom PPC target platform (P4080) ...
From: Robert Sciuk @ 2011-11-07 20:09 UTC (permalink / raw)
To: linuxppc-dev, devicetree-discuss
In-Reply-To: <20111105004050.GA1384@truffala.fritz.box>
In my continuing saga of dev/tree driver development, I have a problem =
which might be obvious to those who have more experience in such =
matters.
I'm a bit perplexed on the tree nodes for the localbus/simplebus nodes =
for my FPGA. CS0 is reserved for booting (from NOR flash as required by =
our design), CS1 is tied to an FPGA which will always be present. CS2 =
actually is tied to both of two (optional) fpga's, which have been =
previously mapped by U-Boot (BRn/ORn configuration). Should I specify a =
ranges command as follows? This seems somehow wrong, to me, and I'm =
wondering if there is an alternative representation which would work =
better in this case. If you recall, the programming control lines are =
handled on the I2C bus, via a gpio controller. In an ideal world, the =
optional FPE1 and FPE2 fpgas will have the identical .bts stream, and =
should support the option to program both simultaneously, or each =
individually, but I'm at a loss as how to best represent this in the =
tree.
localbus@ffe124000 {
compatible =3D "fsl,p4080-elbc", "fsl,elbc", =
"simple-bus";
reg =3D <0xf 0xfe124000 0 0x1000>;
interrupts =3D <25 2 0 0>;
interrupt-parent =3D <&mpic>;
#address-cells =3D <2>;
#size-cells =3D <1>;
/* Local bus region mappings */
ranges =3D <0 0 0xf 0xe8000000 0x08000000 /* =
CS0: Boot flash */
1 0 0xf 0xd0000000 0x7fff /* CS1: =
FPGA0 - LIM */
2 0 0xf 0xd1000000 0x7fff /* CS2: =
FPGA1 - FPE1 */
2 0 0xf 0xd2000000 0x7fff >; /* CS2: =
FPGA2 - FPE2 */
flash@0,0 {
compatible =3D "cfi-flash";
reg =3D <0 0 0x08000000>;
bank-width =3D <2>;
device-width =3D <2>;
#size-cells =3D <1>;
#address-cells =3D <1>;
partition@0 {
label =3D "rcw";
reg =3D <0x0 0x20000>;
read-only;
};
partition@40000 {
label =3D "saveenv";
reg =3D <0x40000 0x20000>;
};
partition@7000000 {
label =3D "fman-firmware";
reg =3D <0x7000000 0x20000>;
read-only;
};
partition@7f80000 {
label =3D "u-boot";
reg =3D <0x7f80000 0x80000>;
read-only;
};
};
lim: fpga@1, {
}
fpe1: fpga@2, {
}
fpe2: fpga@2, {
}
Again, any pointers here would be greatly appreciated ...
Cheers,
Rob Sciuk
^ permalink raw reply
* Re: Regression: patch " hvc_console: display printk messages on console." causing infinite loop with 3.2-rc0 + Xen.
From: Greg KH @ 2011-11-07 20:24 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Rusty Russell, xen-devel, Konrad Rzeszutek Wilk, ppc-dev, miche,
linux-kernel, virtualization, Anton Blanchard, Amit Shah, Linus
In-Reply-To: <20111107171942.fe21429583491475f245aa08@canb.auug.org.au>
On Mon, Nov 07, 2011 at 05:19:42PM +1100, Stephen Rothwell wrote:
> Hi Greg,
>
> On Wed, 2 Nov 2011 18:30:12 -0700 Greg KH <gregkh@suse.de> wrote:
> >
> > On Wed, Nov 02, 2011 at 12:13:09PM +1100, Stephen Rothwell wrote:
> > >
> > > On Thu, 27 Oct 2011 07:48:06 +0200 Greg KH <gregkh@suse.de> wrote:
> > > >
> > > > On Thu, Oct 27, 2011 at 01:30:08AM -0400, Konrad Rzeszutek Wilk wrote:
> > > > > Hey Miche.
> > > > >
> > > > > The git commit 361162459f62dc0826b82c9690a741a940f457f0:
> > > > >
> > > > > hvc_console: display printk messages on console.
> > > > >
> > > > > is causing an infinite loop when booting Linux under Xen, as so:
> > > >
> > > > Ick, not good, thanks for letting us know.
> > >
> > > Indeed. I am wondering why it was put in a tree and sent to Linus without
> > > any Acks or even being replied to by anyone. It appeared in the tty tree
> > > between Oct 14 and Oct 25 (while I was unfortunately on vacation). If
> > > anyone had tried to boot this on any PowerPC server, it would have been
> > > immediately obvious (as it was when I booted Linus' tree last night).
> > >
> > > And the original author expressed doubts as to his understanding of how
> > > it should all work anyway.
> > >
> > > Just a little more care, please.
> > >
> > > I would vote for reverting the original and having it resubmitted with
> > > corrections at some later date.
> >
> > You are right, I will go do that, sorry for the problems.
>
> Ping ...
>
> Linus can you please just revert 361162459f62dc0826b82c9690a741a940f457f0
> "hvc_console: display printk messages on console" as it breaks consoles
> for all PowerPC server machines.
Thanks for doing this, I was going to include it in my next pull request
after 3.2-rc1 was out, but you are right, it should have gone in sooner.
greg k-h
^ permalink raw reply
* Re: fpga driver on custom PPC target platform (P4080) ...
From: Mitch Bradley @ 2011-11-07 21:31 UTC (permalink / raw)
To: Robert Sciuk; +Cc: devicetree-discuss, linuxppc-dev
In-Reply-To: <2DD52030B5146141BEB762A11AE97C4C0100CB3D@SPQCEXC05.exfo.com>
On 11/7/2011 10:09 AM, Robert Sciuk wrote:
> In my continuing saga of dev/tree driver development, I have a problem which might be obvious to those who have more experience in such matters.
>
> I'm a bit perplexed on the tree nodes for the localbus/simplebus nodes for my FPGA. CS0 is reserved for booting (from NOR flash as required by our design), CS1 is tied to an FPGA which will always be present. CS2 actually is tied to both of two (optional) fpga's, which have been previously mapped by U-Boot (BRn/ORn configuration). Should I specify a ranges command as follows? This seems somehow wrong, to me, and I'm wondering if there is an alternative representation which would work better in this case. If you recall, the programming control lines are handled on the I2C bus, via a gpio controller. In an ideal world, the optional FPE1 and FPE2 fpgas will have the identical .bts stream, and should support the option to program both simultaneously, or each individually, but I'm at a loss as how to best represent this in the tree.
I would be tempted to add another level of hierarchy as a container for
the two FPEs on CS2.
>
> localbus@ffe124000 {
> compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
> reg =<0xf 0xfe124000 0 0x1000>;
> interrupts =<25 2 0 0>;
> interrupt-parent =<&mpic>;
> #address-cells =<2>;
> #size-cells =<1>;
>
> /* Local bus region mappings */
> ranges =<0 0 0xf 0xe8000000 0x08000000 /* CS0: Boot flash */
> 1 0 0xf 0xd0000000 0x7fff /* CS1: FPGA0 - LIM */
> 2 0 0xf 0xd1000000 0x7fff /* CS2: FPGA1 - FPE1 */
> 2 0 0xf 0xd2000000 0x7fff>; /* CS2: FPGA2 - FPE2 */
>
> flash@0,0 {
> compatible = "cfi-flash";
> reg =<0 0 0x08000000>;
> bank-width =<2>;
> device-width =<2>;
> #size-cells =<1>;
> #address-cells =<1>;
>
> partition@0 {
> label = "rcw";
> reg =<0x0 0x20000>;
> read-only;
> };
> partition@40000 {
> label = "saveenv";
> reg =<0x40000 0x20000>;
> };
> partition@7000000 {
> label = "fman-firmware";
> reg =<0x7000000 0x20000>;
> read-only;
> };
> partition@7f80000 {
> label = "u-boot";
> reg =<0x7f80000 0x80000>;
> read-only;
> };
> };
>
> lim: fpga@1, {
> }
>
> fpe1: fpga@2, {
> }
>
> fpe2: fpga@2, {
> }
>
> Again, any pointers here would be greatly appreciated ...
>
> Cheers,
> Rob Sciuk
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>
^ permalink raw reply
* RE: fpga driver on custom PPC target platform (P4080) ...
From: Robert Sciuk @ 2011-11-07 21:50 UTC (permalink / raw)
To: Mitch Bradley; +Cc: devicetree-discuss, linuxppc-dev
In-Reply-To: <4EB84E24.9000000@firmworks.com>
> -----Original Message-----
> From: Mitch Bradley [mailto:wmb@firmworks.com]
>=20
> I would be tempted to add another level of hierarchy as a container =
for
> the two FPEs on CS2.
>=20
Hi, Mitch.
As a long time Forth(er), I'm somewhat honoured to have this exchange =
with you 8-)
Do you mean something like this????
localbus@ffe124000 {
compatible =3D "fsl,p4080-elbc", "fsl,elbc", =
"simple-bus";
reg =3D <0xf 0xfe124000 0 0x1000>;
interrupts =3D <25 2 0 0>;
interrupt-parent =3D <&mpic>;
#address-cells =3D <2>;
#size-cells =3D <1>;
/* Local bus region mappings */
ranges =3D <0 0 0xf 0xe8000000 0x08000000 /* =
CS0: Boot flash */
1 0 0xf 0xd0000000 0x7fff /* CS1: =
FPGA0 - LIM */
2 0 0xf 0xd1000000 0x7fff /* CS2: =
FPGA1 - FPE1 */
2 1 0xf 0xd2000000 0x7fff >; /* CS2: =
FPGA2 - FPE2 */
flash@0,0 {
compatible =3D "cfi-flash";
reg =3D <0 0 0x08000000>;
bank-width =3D <2>;
device-width =3D <2>;
#size-cells =3D <1>;
#address-cells =3D <1>;
partition@0 {
label =3D "rcw";
reg =3D <0x0 0x20000>;
read-only;
};
partition@40000 {
label =3D "saveenv";
reg =3D <0x40000 0x20000>;
};
partition@7000000 {
label =3D "fman-firmware";
reg =3D <0x7000000 0x20000>;
read-only;
};
partition@7f80000 {
label =3D "u-boot";
reg =3D <0x7f80000 0x80000>;
read-only;
};
};
lim: fpga@1, {
}
nitro: daughtercard@2 {
fpe1: fpga@2,0 {
}
fpe2: fpga@2,1 {
}
}
}
^ permalink raw reply
* Re: fpga driver on custom PPC target platform (P4080) ...
From: Scott Wood @ 2011-11-07 22:14 UTC (permalink / raw)
To: Robert Sciuk; +Cc: devicetree-discuss, linuxppc-dev
In-Reply-To: <2DD52030B5146141BEB762A11AE97C4C0100CB3D@SPQCEXC05.exfo.com>
On 11/07/2011 02:09 PM, Robert Sciuk wrote:
> In my continuing saga of dev/tree driver development, I have a problem which might be obvious to those who have more experience in such matters.
>
> I'm a bit perplexed on the tree nodes for the localbus/simplebus
> nodes for my FPGA. CS0 is reserved for booting (from NOR flash as
> required by our design), CS1 is tied to an FPGA which will always be
> present. CS2 actually is tied to both of two (optional) fpga's,
> which have been previously mapped by U-Boot (BRn/ORn configuration).
> Should I specify a ranges command as follows? This seems somehow
> wrong, to me, and I'm wondering if there is an alternative
> representation which would work better in this case. If you recall,
> the programming control lines are handled on the I2C bus, via a gpio
> controller. In an ideal world, the optional FPE1 and FPE2 fpgas will
> have the identical .bts stream, and should support the option to
> program both simultaneously, or each individually, but I'm at a loss
> as how to best represent this in the tree.
If you need to poke an i2c bus to switch access between certain localbus
children, you should remove "simple-bus" from the compatible -- or
perhaps do something like:
localbus@ffe124000 {
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
...
flash@0,0 {
...
};
switched-bank@2,0 {
// no simple-bus here
compatible = "something specific to your board's setup";
ranges = <0 0 2 0 0x8000>;
// reg is here just to make the unit-addres valid
reg = <2 0 0>;
#address-cells = <2>;
#size-cells = <1>;
// specify a phandle to the i2c device and any other
// relevant details for identifying which knob of the
// switch needs to be turned...
// replace x/y with appropriate switch ID, and 0 0x8000
// with appropriate portion of the window being used by
// each device
fpga@x,0 {
compatible = ...
reg = <x 0 0x8000>;
...
};
fpga@y,0 {
compatible = ...
reg = <y 0 0x8000>;
...
};
};
};
>
> localbus@ffe124000 {
> compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
> reg = <0xf 0xfe124000 0 0x1000>;
> interrupts = <25 2 0 0>;
> interrupt-parent = <&mpic>;
> #address-cells = <2>;
> #size-cells = <1>;
>
> /* Local bus region mappings */
> ranges = <0 0 0xf 0xe8000000 0x08000000 /* CS0: Boot flash */
> 1 0 0xf 0xd0000000 0x7fff /* CS1: FPGA0 - LIM */
> 2 0 0xf 0xd1000000 0x7fff /* CS2: FPGA1 - FPE1 */
> 2 0 0xf 0xd2000000 0x7fff >; /* CS2: FPGA2 - FPE2 */
The binding for FSL localbus nodes
(Documentation/devicetree/bindings/powerpc/fsl/lbc.txt) says that there
is a one-to-one correspondence between "ranges" entries and chipselects,
based on how the eLBC is actually programmed. The details of what is
attached come in the subnodes.
I don't see how the above mapping is possible with eLBC -- you're
splitting CS2 among 0xd1000000..0xd1007fff and 0xd2000000..0xd2007fff.
Since you have CS1 at 0xd0000000, alignment restrictions prevent CS2
from covering both of those regions -- unless you've got overlapping
mappings, with CS2 being at least 0xd0000000..0xd3ffffff, and are
relying on CS1 taking priority due to being lower-numbered.
I hope you're not doing that, and that these aren't the real addresses
(or they can be changed) -- but if you must do this, that breaks the
one-to-one model, so you'd need both ranges entries.
Also note that the final cell in each ranges entry should be the size,
not the size minus one.
> fpe1: fpga@2, {
> }
>
> fpe2: fpga@2, {
This would be fine for a case where the devices are not switched, but
rather decode different addresses within the chipselect.
E.g. CS3 of arch/powerpc/boot/dts/socrates.dts
-Scott
^ permalink raw reply
* RE: fpga driver on custom PPC target platform (P4080) ...
From: Robert Sciuk @ 2011-11-07 23:07 UTC (permalink / raw)
To: Scott Wood; +Cc: devicetree-discuss, linuxppc-dev
In-Reply-To: <4EB8582A.3070303@freescale.com>
...
>=20
> switched-bank@2,0 {
> // no simple-bus here
> compatible =3D "something specific to your board's setup";
> ranges =3D <0 0 2 0 0x8000>;
>=20
> // reg is here just to make the unit-addres valid
> reg =3D <2 0 0>;
>=20
> #address-cells =3D <2>;
> #size-cells =3D <1>;
>=20
> // specify a phandle to the i2c device and any other
> // relevant details for identifying which knob of the
> // switch needs to be turned...
>=20
> // replace x/y with appropriate switch ID, and 0 0x8000
> // with appropriate portion of the window being used by
> // each device
> fpga@x,0 {
> compatible =3D ...
> reg =3D <x 0 0x8000>;
> ...
> };
>=20
> fpga@y,0 {
> compatible =3D ...
> reg =3D <y 0 0x8000>;
> ...
> };
> };
> };
>=20
> >
> > localbus@ffe124000 {
> > compatible =3D "fsl,p4080-elbc", "fsl,elbc", =
"simple-
> bus";
> > reg =3D <0xf 0xfe124000 0 0x1000>;
> > interrupts =3D <25 2 0 0>;
> > interrupt-parent =3D <&mpic>;
> > #address-cells =3D <2>;
> > #size-cells =3D <1>;
> >
> > /* Local bus region mappings */
> > ranges =3D <0 0 0xf 0xe8000000 0x08000000 /*
> CS0: Boot flash */
> > 1 0 0xf 0xd0000000 0x7fff /*
> CS1: FPGA0 - LIM */
> > 2 0 0xf 0xd1000000 0x7fff /*
> CS2: FPGA1 - FPE1 */
> > 2 0 0xf 0xd2000000 0x7fff >; /*
> CS2: FPGA2 - FPE2 */
>=20
> The binding for FSL localbus nodes
> (Documentation/devicetree/bindings/powerpc/fsl/lbc.txt) says that =
there
> is a one-to-one correspondence between "ranges" entries and
> chipselects,
> based on how the eLBC is actually programmed. The details of what is
> attached come in the subnodes.
>=20
> I don't see how the above mapping is possible with eLBC -- you're
> splitting CS2 among 0xd1000000..0xd1007fff and 0xd2000000..0xd2007fff.
> Since you have CS1 at 0xd0000000, alignment restrictions prevent CS2
> from covering both of those regions -- unless you've got overlapping
> mappings, with CS2 being at least 0xd0000000..0xd3ffffff, and are
> relying on CS1 taking priority due to being lower-numbered.
>=20
> I hope you're not doing that, and that these aren't the real addresses
> (or they can be changed) -- but if you must do this, that breaks the
> one-to-one model, so you'd need both ranges entries.
>=20
> Also note that the final cell in each ranges entry should be the size,
> not the size minus one.
>=20
> > fpe1: fpga@2, {
> > }
> >
> > fpe2: fpga@2, {
>=20
> This would be fine for a case where the devices are not switched, but
> rather decode different addresses within the chipselect.
>=20
> E.g. CS3 of arch/powerpc/boot/dts/socrates.dts
>=20
> -Scott
Thanks, Scott ... I'm looking both at the localbus docs and the Socrates =
... I will stare at both for the requisite time, and re-emerge when I =
understand the issues.
Rob.
^ permalink raw reply
* RE: fpga driver on custom PPC target platform (P4080) ...
From: Robert Sciuk @ 2011-11-07 23:29 UTC (permalink / raw)
To: Scott Wood; +Cc: devicetree-discuss, linuxppc-dev
In-Reply-To: <4EB8582A.3070303@freescale.com>
> -----Original Message-----
> From: Scott Wood [mailto:scottwood@freescale.com]
> Sent: Monday, November 07, 2011 5:14 PM
> To: Robert Sciuk
> Cc: linuxppc-dev@lists.ozlabs.org; devicetree-discuss@lists.ozlabs.org
> Subject: Re: fpga driver on custom PPC target platform (P4080) ...
>=20
...=20
> If you need to poke an i2c bus to switch access between certain
> localbus children, you should remove "simple-bus" from the compatible =
-- or
> perhaps do something like:
>=20
Actually, the gpio expander on the I2C bus don't select the localbus =
children, but the programming pins are driven by the i2c bus, and each =
FPGA has its own gpio expander (PCA9539). ... Ultimately, I will link =
the i2c address and localbus (8 bit programming port) via phandles, but =
both of the optional fpga's have their databus tied to the same chip =
select on the localbus. The intent was to perform simultaneous =
programming, but I would like the option to do both simultaneous and =
individual programming ... eg: set either one or both of the FPGAs to =
programming mode, and then mmap the localbus port from user land (uio =
driver), and transmit the bit stream. The DONE (success/fail) bit would =
be returned by the device close ... or at least that's how I dreamed it =
might work ... again, I will stare at the fsl elbc device tree doc, and =
I can certainly re-map the addressing (36bit ... it=92s a P4080 target).
> localbus@ffe124000 {
> compatible =3D "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
> ...
>=20
> flash@0,0 {
> ...
> };
>=20
> switched-bank@2,0 {
> // no simple-bus here
> compatible =3D "something specific to your board's setup";
> ranges =3D <0 0 2 0 0x8000>;
>=20
> // reg is here just to make the unit-addres valid
> reg =3D <2 0 0>;
>=20
> #address-cells =3D <2>;
> #size-cells =3D <1>;
>=20
> // specify a phandle to the i2c device and any other
> // relevant details for identifying which knob of the
> // switch needs to be turned...
>=20
> // replace x/y with appropriate switch ID, and 0 0x8000
> // with appropriate portion of the window being used by
> // each device
> fpga@x,0 {
> compatible =3D ...
> reg =3D <x 0 0x8000>;
> ...
> };
>=20
> fpga@y,0 {
> compatible =3D ...
> reg =3D <y 0 0x8000>;
> ...
> };
> };
> };
>=20
> >
> > localbus@ffe124000 {
> > compatible =3D "fsl,p4080-elbc", "fsl,elbc", =
"simple-
> bus";
> > reg =3D <0xf 0xfe124000 0 0x1000>;
> > interrupts =3D <25 2 0 0>;
> > interrupt-parent =3D <&mpic>;
> > #address-cells =3D <2>;
> > #size-cells =3D <1>;
> >
> > /* Local bus region mappings */
> > ranges =3D <0 0 0xf 0xe8000000 0x08000000 /*
> CS0: Boot flash */
> > 1 0 0xf 0xd0000000 0x7fff /*
> CS1: FPGA0 - LIM */
> > 2 0 0xf 0xd1000000 0x7fff /*
> CS2: FPGA1 - FPE1 */
> > 2 0 0xf 0xd2000000 0x7fff >; /*
> CS2: FPGA2 - FPE2 */
>=20
> The binding for FSL localbus nodes
> (Documentation/devicetree/bindings/powerpc/fsl/lbc.txt) says that =
there
> is a one-to-one correspondence between "ranges" entries and
> chipselects,
> based on how the eLBC is actually programmed. The details of what is
> attached come in the subnodes.
>=20
> I don't see how the above mapping is possible with eLBC -- you're
> splitting CS2 among 0xd1000000..0xd1007fff and 0xd2000000..0xd2007fff.
> Since you have CS1 at 0xd0000000, alignment restrictions prevent CS2
> from covering both of those regions -- unless you've got overlapping
> mappings, with CS2 being at least 0xd0000000..0xd3ffffff, and are
> relying on CS1 taking priority due to being lower-numbered.
>=20
> I hope you're not doing that, and that these aren't the real addresses
> (or they can be changed) -- but if you must do this, that breaks the
> one-to-one model, so you'd need both ranges entries.
>=20
> Also note that the final cell in each ranges entry should be the size,
> not the size minus one.
>=20
> > fpe1: fpga@2, {
> > }
> >
> > fpe2: fpga@2, {
>=20
> This would be fine for a case where the devices are not switched, but
> rather decode different addresses within the chipselect.
>=20
> E.g. CS3 of arch/powerpc/boot/dts/socrates.dts
>=20
> -Scott
^ permalink raw reply
* [PATCH] powerpc/kvm: annotate kvm_rma_init as __init
From: Nishanth Aravamudan @ 2011-11-07 23:29 UTC (permalink / raw)
To: Alexander Graf; +Cc: Paul Mackerras, linuxppc-dev, kvm-ppc
kvm_rma_init() is only called at boot-time, by setup_arch, which is also __init.
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index d431203..73fdcc1 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -85,7 +85,7 @@ static inline int lpcr_rmls(unsigned long rma_size)
* to allocate contiguous physical memory for the real memory
* areas for guests.
*/
-void kvm_rma_init(void)
+void __init kvm_rma_init(void)
{
unsigned long i;
unsigned long j, npages;
--
Nishanth Aravamudan <nacc@us.ibm.com>
IBM Linux Technology Center
^ permalink raw reply related
* [PATCH] powerpc: Remove buggy 9-year-old test for binutils < 2.12.1
From: Kyle Moffett @ 2011-11-07 23:30 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev; +Cc: Paul Mackerras, Kyle Moffett
Recent binutils refuses to assemble AltiVec opcodes when in e500/SPE
mode, as some of those opcodes alias the "SPE" instructions. This
triggers an ancient binutils version check even when building a kernel
with CONFIG_ALTIVEC disabled.
In theory, the check could be conditionalized on CONFIG_ALTIVEC, but in
practice it has long outlived its utility. It is virtually impossible
to find binutils older than 2.12.1 (released 2002) in the wild anymore.
Even ancient RedHat Enterprise Linux 4 has binutils-2.14.
To fix the kernel build when done natively on e500 systems with this new
binutils, the test is simply removed.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
---
arch/powerpc/Makefile | 6 ------
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 57af16e..70ba0c0 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -255,12 +255,6 @@ checkbin:
echo 'disable kernel modules' ; \
false ; \
fi
- @if ! /bin/echo dssall | $(AS) -many -o $(TOUT) >/dev/null 2>&1 ; then \
- echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build ' ; \
- echo 'correctly with old versions of binutils.' ; \
- echo '*** Please upgrade your binutils to 2.12.1 or newer' ; \
- false ; \
- fi
CLEAN_FILES += $(TOUT)
--
1.7.2.5
^ permalink raw reply related
* [PATCH] powerpc/kvm: fix build with older toolchains
From: Nishanth Aravamudan @ 2011-11-07 23:36 UTC (permalink / raw)
To: Alexander Graf; +Cc: Paul Mackerras, linuxppc-dev, kvm-ppc
Fix KVM build for older toolchains (found with .powerpc64-unknown-linux-gnu-gcc
(crosstool-NG-1.8.1) 4.3.2):
AS arch/powerpc/kvm/book3s_hv_rmhandlers.o
arch/powerpc/kvm/book3s_hv_rmhandlers.S: Assembler messages:
arch/powerpc/kvm/book3s_hv_rmhandlers.S:1388: Error: Unrecognized opcode: `popcntw'
make[1]: *** [arch/powerpc/kvm/book3s_hv_rmhandlers.o] Error 1
make: *** [_module_arch/powerpc/kvm] Error 2
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 0607909..a053db1 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -1385,7 +1385,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
addi r6,r5,VCORE_NAPPING_THREADS
31: lwarx r4,0,r6
or r4,r4,r0
- popcntw r7,r4
+ PPC_POPCNTW(r7,r4)
cmpw r7,r8
bge 2f
stwcx. r4,0,r6
--
Nishanth Aravamudan <nacc@us.ibm.com>
IBM Linux Technology Center
^ permalink raw reply related
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