* [PATCH] powerpc/fsl: add MSI support for the Freescale hypervisor
From: Timur Tabi @ 2011-12-12 23:37 UTC (permalink / raw)
To: kumar.gala, scottwood, linuxppc-dev
Add support for MSIs under the Freescale hypervisor. This involves updating
the fsl_pci driver to support vmpic-msi nodes, and updating the fsl_pci
driver to create an ATMU for the rerouted MSIIR register.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/sysdev/fsl_msi.c | 68 +++++++++++++++++++++++++++++------------
arch/powerpc/sysdev/fsl_msi.h | 7 ++--
arch/powerpc/sysdev/fsl_pci.c | 25 +++++++++++++++
3 files changed, 77 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 89548e0..7dc473f 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -23,6 +23,8 @@
#include <asm/hw_irq.h>
#include <asm/ppc-pci.h>
#include <asm/mpic.h>
+#include <asm/fsl_hcalls.h>
+
#include "fsl_msi.h"
#include "fsl_pci.h"
@@ -163,11 +165,13 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
*/
np = of_parse_phandle(hose->dn, "fsl,msi", 0);
if (np) {
- if (of_device_is_compatible(np, "fsl,mpic-msi"))
+ if (of_device_is_compatible(np, "fsl,mpic-msi") ||
+ of_device_is_compatible(np, "fsl,vmpic-msi"))
phandle = np->phandle;
else {
- dev_err(&pdev->dev, "node %s has an invalid fsl,msi"
- " phandle\n", hose->dn->full_name);
+ dev_err(&pdev->dev,
+ "node %s has an invalid fsl,msi phandle %u\n",
+ hose->dn->full_name, np->phandle);
return -EINVAL;
}
}
@@ -196,16 +200,14 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
if (hwirq < 0) {
rc = hwirq;
- pr_debug("%s: fail allocating msi interrupt\n",
- __func__);
+ dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
goto out_free;
}
virq = irq_create_mapping(msi_data->irqhost, hwirq);
if (virq == NO_IRQ) {
- pr_debug("%s: fail mapping hwirq 0x%x\n",
- __func__, hwirq);
+ dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
rc = -ENOSPC;
goto out_free;
@@ -234,6 +236,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
u32 intr_index;
u32 have_shift = 0;
struct fsl_msi_cascade_data *cascade_data;
+ unsigned int ret;
cascade_data = irq_get_handler_data(irq);
msi_data = cascade_data->msi_data;
@@ -265,6 +268,14 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
case FSL_PIC_IP_IPIC:
msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
break;
+ case FSL_PIC_IP_VMPIC:
+ ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
+ if (ret) {
+ pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
+ "irq %u (ret=%u)\n", irq, ret);
+ msir_value = 0;
+ }
+ break;
}
while (msir_value) {
@@ -282,6 +293,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
switch (msi_data->feature & FSL_PIC_IP_MASK) {
case FSL_PIC_IP_MPIC:
+ case FSL_PIC_IP_VMPIC:
chip->irq_eoi(idata);
break;
case FSL_PIC_IP_IPIC:
@@ -311,7 +323,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
}
if (msi->bitmap.bitmap)
msi_bitmap_free(&msi->bitmap);
- iounmap(msi->msi_regs);
+ if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
+ iounmap(msi->msi_regs);
kfree(msi);
return 0;
@@ -383,26 +396,32 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
goto error_out;
}
- /* Get the MSI reg base */
- err = of_address_to_resource(dev->dev.of_node, 0, &res);
- if (err) {
- dev_err(&dev->dev, "%s resource error!\n",
+ /*
+ * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
+ * property. Instead, we use hypercalls to access the MSI.
+ */
+ if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
+ err = of_address_to_resource(dev->dev.of_node, 0, &res);
+ if (err) {
+ dev_err(&dev->dev, "invalid resource for node %s\n",
dev->dev.of_node->full_name);
- goto error_out;
- }
+ goto error_out;
+ }
- msi->msi_regs = ioremap(res.start, resource_size(&res));
- if (!msi->msi_regs) {
- dev_err(&dev->dev, "ioremap problem failed\n");
- goto error_out;
+ msi->msi_regs = ioremap(res.start, resource_size(&res));
+ if (!msi->msi_regs) {
+ dev_err(&dev->dev, "could not map node %s\n",
+ dev->dev.of_node->full_name);
+ goto error_out;
+ }
+ msi->msiir_offset =
+ features->msiir_offset + (res.start & 0xfffff);
}
msi->feature = features->fsl_pic_ip;
msi->irqhost->host_data = msi;
- msi->msiir_offset = features->msiir_offset + (res.start & 0xfffff);
-
/*
* Remember the phandle, so that we can match with any PCI nodes
* that have an "fsl,msi" property.
@@ -476,6 +495,11 @@ static const struct fsl_msi_feature ipic_msi_feature = {
.msiir_offset = 0x38,
};
+static const struct fsl_msi_feature vmpic_msi_feature = {
+ .fsl_pic_ip = FSL_PIC_IP_VMPIC,
+ .msiir_offset = 0,
+};
+
static const struct of_device_id fsl_of_msi_ids[] = {
{
.compatible = "fsl,mpic-msi",
@@ -485,6 +509,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
.compatible = "fsl,ipic-msi",
.data = (void *)&ipic_msi_feature,
},
+ {
+ .compatible = "fsl,vmpic-msi",
+ .data = (void *)&vmpic_msi_feature,
+ },
{}
};
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index b5d25ba..f6c646a 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -20,9 +20,10 @@
#define IRQS_PER_MSI_REG 32
#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG)
-#define FSL_PIC_IP_MASK 0x0000000F
-#define FSL_PIC_IP_MPIC 0x00000001
-#define FSL_PIC_IP_IPIC 0x00000002
+#define FSL_PIC_IP_MASK 0x0000000F
+#define FSL_PIC_IP_MPIC 0x00000001
+#define FSL_PIC_IP_IPIC 0x00000002
+#define FSL_PIC_IP_VMPIC 0x00000003
struct fsl_msi {
struct irq_host *irqhost;
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4ce547e..819987c 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -113,6 +113,8 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
char *name = hose->dn->full_name;
+ const u64 *reg;
+ int len;
pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
(u64)rsrc->start, (u64)resource_size(rsrc));
@@ -205,6 +207,29 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
/* Setup inbound mem window */
mem = memblock_end_of_DRAM();
+
+ /*
+ * The msi-address-64 property, if it exists, indicates the physical
+ * address of the MSIIR register. Normally, this register is located
+ * inside CCSR, so the ATMU that covers all of CCSR is used for MSIs.
+ * But if this property exists, then we'll normally need to create a
+ * new ATMU for it. For now, however, we cheat. The only entity that
+ * creates this property is the Freescale hypervisor, and it
+ * always locates MSIIR in the page immediately after the end of DDR.
+ * So we can avoid allocating a new ATMU by just extending the DDR
+ * ATMU by one page.
+ */
+ reg = of_get_property(hose->dn, "msi-address-64", &len);
+ if (reg && (len == sizeof(u64))) {
+ u64 address = be64_to_cpup(reg);
+
+ if ((address >= mem) && (address < (mem + PAGE_SIZE)))
+ mem += PAGE_SIZE;
+ else
+ pr_warn("msi-address-64 address of %llx in node %s is "
+ "unsupported\n", address, hose->dn->full_name);
+ }
+
sz = min(mem, paddr_lo);
mem_log = __ilog2_u64(sz);
--
1.7.3.4
^ permalink raw reply related
* Re: [PATCH] powerpc/fsl: add MSI support for the Freescale hypervisor
From: Scott Wood @ 2011-12-12 23:52 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev, kumar.gala
In-Reply-To: <1323733052-21495-1-git-send-email-timur@freescale.com>
On 12/12/2011 05:37 PM, Timur Tabi wrote:
> @@ -205,6 +207,29 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
>
> /* Setup inbound mem window */
> mem = memblock_end_of_DRAM();
> +
> + /*
> + * The msi-address-64 property, if it exists, indicates the physical
> + * address of the MSIIR register. Normally, this register is located
> + * inside CCSR, so the ATMU that covers all of CCSR is used for MSIs.
> + * But if this property exists, then we'll normally need to create a
> + * new ATMU for it. For now, however, we cheat. The only entity that
> + * creates this property is the Freescale hypervisor, and it
> + * always locates MSIIR in the page immediately after the end of DDR.
> + * So we can avoid allocating a new ATMU by just extending the DDR
> + * ATMU by one page.
> + */
Technically, it's up to the hv config file where MSIIR gets mapped.
After main memory is just a common way of configuring it, but won't work
if we're limiting the partition's memory to end at an unusual address.
Might also want to comment that the reason for this weird remapping is
hardware limitations in the IOMMU.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/fsl: add MSI support for the Freescale hypervisor
From: Tabi Timur-B04825 @ 2011-12-13 0:27 UTC (permalink / raw)
To: Wood Scott-B07421; +Cc: linuxppc-dev@ozlabs.org, Gala Kumar-B11780
In-Reply-To: <4EE693C9.3080009@freescale.com>
Scott Wood wrote:
> Technically, it's up to the hv config file where MSIIR gets mapped.
> After main memory is just a common way of configuring it, but won't work
> if we're limiting the partition's memory to end at an unusual address.
I'll change the comment to reflect this.
Why can't we have the hypervisor always put MSIIR at the end of DDR, and=20
not make it configurable?
--=20
Timur Tabi
Linux kernel developer at Freescale=
^ permalink raw reply
* Re: [PATCH] powerpc/fsl: add MSI support for the Freescale hypervisor
From: Scott Wood @ 2011-12-13 0:39 UTC (permalink / raw)
To: Tabi Timur-B04825
Cc: Wood Scott-B07421, Gala Kumar-B11780, linuxppc-dev@ozlabs.org
In-Reply-To: <4EE69BEB.8020208@freescale.com>
On 12/12/2011 06:27 PM, Tabi Timur-B04825 wrote:
> Scott Wood wrote:
>> Technically, it's up to the hv config file where MSIIR gets mapped.
>> After main memory is just a common way of configuring it, but won't work
>> if we're limiting the partition's memory to end at an unusual address.
>
> I'll change the comment to reflect this.
>
> Why can't we have the hypervisor always put MSIIR at the end of DDR, and
> not make it configurable?
"...but won't work if we're limiting the partition's memory to end at an
unusual address." We have to live with PAMU's iova limitations. PAMU
setup is user-controlled in general under Topaz.
How's the hypervisor even going to know if the mem= kernel command line
argument is used to change the end of main memory (assuming that's been
taken into account by this point in the boot sequence)?
What if the user put a shared memory region immediately after the main
partition memory?
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/fsl: add MSI support for the Freescale hypervisor
From: Tabi Timur-B04825 @ 2011-12-13 0:43 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: Wood Scott-B07421, Gala Kumar-B11780, linuxppc-dev@ozlabs.org
In-Reply-To: <4EE69ED1.6040302@freescale.com>
Scott Wood wrote:
> How's the hypervisor even going to know if the mem=3D kernel command line
> argument is used to change the end of main memory (assuming that's been
> taken into account by this point in the boot sequence)?
>
> What if the user put a shared memory region immediately after the main
> partition memory?
Alright, I'll need to add support for detached MSIIR addresses, but for=20
now I think this patch is okay. It's the same level of functionality that=
=20
we provide on the SDK.
--=20
Timur Tabi
Linux kernel developer at Freescale=
^ permalink raw reply
* Re: [PATCH 01/16 v3] pmac_zilog: fix unexpected irq
From: Finn Thain @ 2011-12-13 1:24 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, linux-m68k, Geert Uytterhoeven, linux-serial
In-Reply-To: <1323720383.19891.21.camel@pasglop>
On Tue, 13 Dec 2011, Benjamin Herrenschmidt wrote:
> On Tue, 2011-12-13 at 00:34 +1100, Finn Thain wrote:
> > On Mon, 12 Dec 2011, Benjamin Herrenschmidt wrote:
> >
> > > Any chance you can test this patch ? I would not be surprised if it
> > > broke m68k since I had to do some of the changes in there "blind",
> > > so let me know... with this, I can again suspend/resume properly on
> > > a Pismo while using the internal modem among other things.
> >
> > The patch works on a PowerBook 520 given a few changes (below). This
> > PowerBook only has one serial port that I can test (the internal modem
> > is not supported on 68k Macs).
>
> Interesting. The modem is a soft-modem "geoport" or a hw serial modem ?
It's the latter.
> In the later case it's probably just a matter of finding the right GPIO
> bit in Apple ASIC to turn the power on :-)
Surely feasible, but not high on the list of missing hardware support.
>
> > Can you test a machine with two ports? The rest of my Mac hardware is
> > in storage since I moved house last week.
>
> I tried on 2 port powermacs, but I only have one adapter, so I've
> basically been running with one serial port open and shooting irda frame
> on the other (with nothing to check wether I got the frames on the other
> hand), oh well ...
>
> I'll apply your patch and commit via my tree.
I forgot to include this fix for your logging change.
Finn
Index: linux-git/drivers/tty/serial/pmac_zilog.c
===================================================================
--- linux-git.orig/drivers/tty/serial/pmac_zilog.c 2011-12-13 12:12:05.000000000 +1100
+++ linux-git/drivers/tty/serial/pmac_zilog.c 2011-12-13 12:13:29.000000000 +1100
@@ -99,6 +99,10 @@ MODULE_LICENSE("GPL");
#define PMACZILOG_NAME "ttyPZ"
#endif
+#define pmz_debug(fmt, arg...) pr_debug(PMACZILOG_NAME "%d: " fmt, uap->port.line, ## arg)
+#define pmz_error(fmt, arg...) pr_err(PMACZILOG_NAME "%d: " fmt, uap->port.line, ## arg)
+#define pmz_info(fmt, arg...) pr_info(PMACZILOG_NAME "%d: " fmt, uap->port.line, ## arg)
+
/*
* For the sake of early serial console, we can do a pre-probe
Index: linux-git/drivers/tty/serial/pmac_zilog.h
===================================================================
--- linux-git.orig/drivers/tty/serial/pmac_zilog.h 2011-12-13 12:12:05.000000000 +1100
+++ linux-git/drivers/tty/serial/pmac_zilog.h 2011-12-13 12:12:28.000000000 +1100
@@ -1,10 +1,6 @@
#ifndef __PMAC_ZILOG_H__
#define __PMAC_ZILOG_H__
-#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
-#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
-#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
-
/*
* At most 2 ESCCs with 2 ports each
*/
^ permalink raw reply
* Re: [UPDATED] [PATCH v4 3/7] [ppc] Process dynamic relocations for kernel
From: Suzuki Poulose @ 2011-12-13 2:24 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Scott Wood, Josh Poimboeuf, linux ppc dev
In-Reply-To: <485863B3-91BC-4488-9CA8-4F902D85D8F6@kernel.crashing.org>
On 12/11/11 01:32, Segher Boessenkool wrote:
> Hi Suzuki,
>
> Looks quite good, a few comments...
>
>> +get_type:
>> + /* r4 holds the relocation type */
>> + extrwi r4, r4, 8, 24 /* r4 = ((char*)r4)[3] */
>
> This comment is confusing (only makes sense together with the
> lwz a long way up).
Agree, will fix them.
>
>> +nxtrela:
>> + /*
>> + * We have to flush the modified instructions to the
>> + * main storage from the d-cache. And also, invalidate the
>> + * cached instructions in i-cache which has been modified.
>> + *
>> + * We delay the msync / isync operation till the end, since
>> + * we won't be executing the modified instructions until
>> + * we return from here.
>> + */
>> + dcbst r4,r7
>> + icbi r4,r7
>
> You still need a sync between these two. Without it, the icbi can
> complete before the dcbst for the same address does, which leaves
> room for an instruction fetch from that address to get old data.
>
Ok.
>> + cmpwi r8, 0 /* relasz = 0 ? */
>> + ble done
>> + add r9, r9, r6 /* move to next entry in the .rela table */
>> + subf r8, r6, r8 /* relasz -= relaent */
>> + b applyrela
>> +
>> +done:
>> + msync /* Wait for the flush to finish */
>
> The instruction is called "sync". msync is a BookE thing.
>
>> next if (/R_PPC64_RELATIVE/ or /R_PPC64_NONE/ or
>> /R_PPC64_ADDR64\s+mach_/);
>> + next if (/R_PPC_ADDR16_LO/ or /R_PPC_ADDR16_HI/ or
>> + /R_PPC_ADDR16_HA/ or /R_PPC_RELATIVE/);
>
> Nothing new, but these should probably have \b or \s or just
> a space on each side.
Will fix this too. Also will include the R_PPC_NONE to the list
of valid relocations.
Thanks
Suzuki
>
>
> Segher
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH 3/3] mtd/nand : workaround for Freescale FCM to support large-page Nand chip
From: LiuShuo @ 2011-12-13 2:46 UTC (permalink / raw)
To: Scott Wood
Cc: Artem.Bityutskiy, dedekind1, linuxppc-dev, linux-kernel, shuo.liu,
linux-mtd, akpm, dwmw2
In-Reply-To: <4EE6725C.3050706@freescale.com>
=E4=BA=8E 2011=E5=B9=B412=E6=9C=8813=E6=97=A5 05:30, Scott Wood =E5=86=99=
=E9=81=93:
> On 12/12/2011 03:19 PM, Artem Bityutskiy wrote:
>> On Mon, 2011-12-12 at 15:15 -0600, Scott Wood wrote:
>>> NAND chips come from the factory with bad blocks marked at a certain
>>> offset into each page. This offset is normally in the OOB area, but
>>> since we change the layout from "4k data, 128 byte oob" to "2k data, =
64
>>> byte oob, 2k data, 64 byte oob" the marker is no longer in the oob. =
On
>>> first use we need to migrate the markers so that they are still in th=
e oob.
>> Ah, I see, thanks. Are you planning to implement in-kernel migration o=
r
>> use a user-space tool?
> That's the kind of answer I was hoping to get from Shuo. :-)
OK, I try to do this. Wait for a couple of days.
-LiuShuo
> Most likely is a firmware-based tool, but I'd like there to be some way
> for the tool to mark that this has happened, so that the Linux driver
> can refuse to do non-raw accesses to a chip that isn't marked as having
> been migrated (or at least yell loudly in the log).
>
> Speaking of raw accesses, these are currently broken in the eLBC
> driver... we need some way for the generic layer to tell us what kind o=
f
> access it is before the transaction starts, not once it wants to read
> out the buffer (unless we add more hacks to delay the start of a read
> transaction until first buffer access...). We'd be better off with a
> high-level "read page/write page" function that does the whole thing
> (not just buffer access, but command issuance as well).
>
> -Scott
^ permalink raw reply
* Re: [PATCH] powerpc: Fix swiotlb ops for ppc64
From: Becky Bruce @ 2011-12-13 3:55 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev list
In-Reply-To: <F8F675D7-B3F9-45B8-92D3-A3D1F0BF7746@kernel.crashing.org>
On Dec 7, 2011, at 11:46 PM, Kumar Gala wrote:
>=20
> On Dec 7, 2011, at 9:23 PM, Benjamin Herrenschmidt wrote:
>=20
>> On Wed, 2011-12-07 at 11:19 -0600, Kumar Gala wrote:
>>=20
>>> struct dma_map_ops swiotlb_dma_ops =3D {
>>> +#ifdef CONFIG_PPC64
>>> + .alloc_coherent =3D swiotlb_alloc_coherent,
>>> + .free_coherent =3D swiotlb_free_coherent,
>>> +#else
>>> .alloc_coherent =3D dma_direct_alloc_coherent,
>>> .free_coherent =3D dma_direct_free_coherent,
>>> +#endif
>>> .map_sg =3D swiotlb_map_sg_attrs,
>>> .unmap_sg =3D swiotlb_unmap_sg_attrs,
>>> .dma_supported =3D swiotlb_dma_supported,
>>=20
>> Do we really need the ifdef ? What happens if we use
>> swiotlb_alloc_coherent() on ppc32 ? Won't it allocate lowmem, realize
>> that it doesn't need bouncing and be happy ?
>>=20
>> Cheers,
>> Ben.
>=20
> Becky any comment?
>=20
> I know its been a while, but wondering if you had any reason to not do =
what Ben's suggesting ?
Well, as you say, it's been a while, and but I think:
1) dma_direct_alloc_coherent strips GFP_HIGHMEM out of the flags field =
when calling the actual allocator and the iotlb version does not. I =
don't know how much this matters - I did a quick grep and I don't see =
any users that specify that, but somebody went through the trouble of =
putting it in there in the first place and without knowing why I wasn't =
willing to get rid of it. Now, since my patch it looks like someone =
added a VM_BUG_ON into __get_free_pages() if GFP_HIGHMEM so this would =
get caught. However, I don't know if we really want to throw a bug =
there.
2) The iotlb code doesn't deal with the !coherent parts like 8xx. We =
can work around that by setting up the dma_ops differently for that case =
instead.
-Becky
^ permalink raw reply
* Re: [PATCH] powerpc: Fix swiotlb ops for ppc64
From: Benjamin Herrenschmidt @ 2011-12-13 4:27 UTC (permalink / raw)
To: Becky Bruce; +Cc: linuxppc-dev list
In-Reply-To: <4BCA9D4A-4284-4DE8-95B9-D5DBA9254CC1@kernel.crashing.org>
On Mon, 2011-12-12 at 21:55 -0600, Becky Bruce wrote:
> 1) dma_direct_alloc_coherent strips GFP_HIGHMEM out of the flags field
> when calling the actual allocator and the iotlb version does not. I
> don't know how much this matters - I did a quick grep and I don't see
> any users that specify that, but somebody went through the trouble of
> putting it in there in the first place and without knowing why I
> wasn't willing to get rid of it. Now, since my patch it looks like
> someone added a VM_BUG_ON into __get_free_pages() if GFP_HIGHMEM so
> this would get caught. However, I don't know if we really want to
> throw a bug there.
>
> 2) The iotlb code doesn't deal with the !coherent parts like 8xx. We
> can work around that by setting up the dma_ops differently for that
> case instead.
Does the rest of it handle them ? I mean swiotlb_map_sg_attrs etc...
If not then it's broken anyway so may as well not care for now.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 3/4] ppc32/kprobe: complete kprobe and migrate exception frame
From: tiejun.chen @ 2011-12-13 4:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1323731987.19891.40.camel@pasglop>
Benjamin Herrenschmidt wrote:
> On Mon, 2011-12-12 at 16:50 +0800, Tiejun Chen wrote:
>> We can't emulate stwu since that may corrupt current exception stack.
>> So we will have to do real store operation in the exception return code.
>>
>> Firstly we'll allocate a trampoline exception frame below the kprobed
>> function stack and copy the current exception frame to the trampoline.
>> Then we can do this real store operation to implement 'stwu', and reroute
>> the trampoline frame to r1 to complete this exception migration.
>>
>> Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
>> ---
>> arch/powerpc/kernel/entry_32.S | 26 ++++++++++++++++++++++++++
>> 1 files changed, 26 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
>> index 56212bc..d56e311 100644
>> --- a/arch/powerpc/kernel/entry_32.S
>> +++ b/arch/powerpc/kernel/entry_32.S
>> @@ -1185,6 +1185,8 @@ recheck:
>> bne- do_resched
>> andi. r0,r9,_TIF_USER_WORK_MASK
>> beq restore_user
>> + andis. r0,r9,_TIF_DELAYED_KPROBE@h
>> + bne- restore_kprobe
>
> Same comment as earlier about name. Note that you're not hooking in the
> right place. "recheck" is only reached if you -already- went out of the
> normal exit path and only when going back to user space unless I'm
> missing something (which is really the case you don't care about).
>
> You need to hook into "resume_kernel" instead.
Maybe I'm misunderstanding what you mean since as I recall you suggestion we
should do this at the end of do_work.
>
> Also, we may want to simplify the whole thing, instead of checking user
> vs. kernel first etc... we could instead have a single _TIF_WORK_MASK
> which includes both the bits for user work and the new bit for kernel
> work. With preempt, the kernel work bits would also include
> _TIF_NEED_RESCHED.
>
> Then you have in the common exit path, a single test for that, with a
> fast path that skips everything and just goes to "restore" for both
> kernel and user.
>
> The only possible issue is the setting of dbcr0 for BookE and 44x and we
> can keep that as a special case keyed of MSR_PR in the resume path under
> ifdef BOOKE (we'll probably sanitize that later with some different
> rework anyway).
>
> So the exit path because something like:
>
> ret_from_except:
> .. hard disable interrupts (unchanged) ...
> read TIF flags
> andi with _TIF_WORK_MASK
> nothing set -> restore
> check PR
> set -> do_work_user
> no set -> do_work_kernel (kprobes & preempt)
> (both loop until relevant _TIF flags are all clear)
> restore:
> #ifdef BOOKE & 44x test PR & do dbcr0 stuff if needed
> ... nornal restore ...
Do you mean we should reorganize current ret_from_except for ppc32 as well?
>
>> do_user_signal: /* r10 contains MSR_KERNEL here */
>> ori r10,r10,MSR_EE
>> SYNC
>> @@ -1202,6 +1204,30 @@ do_user_signal: /* r10 contains MSR_KERNEL here */
>> REST_NVGPRS(r1)
>> b recheck
>>
>> +restore_kprobe:
>> + lwz r3,GPR1(r1)
>> + subi r3,r3,INT_FRAME_SIZE; /* Allocate a trampoline exception frame */
>> + mr r4,r1
>> + bl copy_exc_stack /* Copy from the original to the trampoline */
>> +
>> + /* Do real stw operation to complete stwu */
>> + mr r4,r1
>> + addi r4,r4,INT_FRAME_SIZE /* Get kprobed entry */
>> + lwz r5,GPR1(r1) /* Backup r1 */
>> + stw r4,GPR1(r1) /* Now store that safely */
>
> The above confuses me. Shouldn't you do instead something like
>
> lwz r4,GPR1(r1)
> subi r3,r4,INT_FRAME_SIZE
> li r5,INT_FRAME_SIZE
> bl memcpy
>
Anyway I'll try this if you think memcpy is fine/safe in exception return codes.
> To start with, then you need to know the "old" r1 value which may or may
> not be related to your current r1. The emulation code should stash it
If the old r1 is not related to our current r1, it shouldn't be possible to go
restore_kprob since we set that new flag only for the current.
If I'm wrong please correct me :)
Thanks
Tiejun
> into the int frame in an unused slot such as "orig_gpr3" (since that
> only pertains to restarting syscalls which we aren't doing here).
>
> Then you adjust your r1 and do something like
>
> lwz r3,GPR1(r1)
> lwz r0,ORIG_GPR3(r1)
> stw r0,0(r3)
>
> To perform the store, before doing the rest:
>
>> + /* Reroute the trampoline frame to r1 */
>> + subi r5,r5,INT_FRAME_SIZE
>> + mr r1,r5
>> +
>> + /* Clear _TIF_DELAYED_KPROBE flag */
>> + rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
>> + lwz r0,TI_FLAGS(r9)
>> + rlwinm r0,r0,0,_TIF_DELAYED_KPROBE
>> + stw r0,TI_FLAGS(r9)
>> +
>> + b restore
>> +
>> /*
>> * We come here when we are at the end of handling an exception
>> * that occurred at a place where taking an exception will lose
^ permalink raw reply
* Re: [PATCH 1/4] powerpc/kprobe: introduce a new thread flag
From: tiejun.chen @ 2011-12-13 4:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1323730739.19891.23.camel@pasglop>
Benjamin Herrenschmidt wrote:
> On Mon, 2011-12-12 at 16:50 +0800, Tiejun Chen wrote:
>> We need to add a new thread flag, TIF_KPROBE/_TIF_DELAYED_KPROBE,
>> for handling kprobe operation while exiting exception.
>
> The basic idea is sane, however the instruction emulation isn't per-se
> kprobe specific. It could be used by xmon too for example. I'd rather
> use a different name, something like TIF_EMULATE_STACK_STORE or
Its good term so I'll use this directly :)
Thanks
Tiejun
> something like that.
>
> Cheers,
> Ben.
>
>> Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
>> ---
>> arch/powerpc/include/asm/thread_info.h | 2 ++
>> 1 files changed, 2 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
>> index 836f231..3378734 100644
>> --- a/arch/powerpc/include/asm/thread_info.h
>> +++ b/arch/powerpc/include/asm/thread_info.h
>> @@ -112,6 +112,7 @@ static inline struct thread_info *current_thread_info(void)
>> #define TIF_FREEZE 14 /* Freezing for suspend */
>> #define TIF_SYSCALL_TRACEPOINT 15 /* syscall tracepoint instrumentation */
>> #define TIF_RUNLATCH 16 /* Is the runlatch enabled? */
>> +#define TIF_KPROBE 17 /* Is the delayed kprobe operation? */
>>
>> /* as above, but as bit values */
>> #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
>> @@ -130,6 +131,7 @@ static inline struct thread_info *current_thread_info(void)
>> #define _TIF_FREEZE (1<<TIF_FREEZE)
>> #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
>> #define _TIF_RUNLATCH (1<<TIF_RUNLATCH)
>> +#define _TIF_DELAYED_KPROBE (1<<TIF_KPROBE)
>> #define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
>> _TIF_SECCOMP | _TIF_SYSCALL_TRACEPOINT)
>>
>
>
>
^ permalink raw reply
* Re: [PATCH 2/4] ppc32/kprobe: introduce copy_exc_stack
From: tiejun.chen @ 2011-12-13 4:58 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1323730871.19891.25.camel@pasglop>
Benjamin Herrenschmidt wrote:
> On Mon, 2011-12-12 at 16:50 +0800, Tiejun Chen wrote:
>> We need a copy mechanism to migrate exception stack. But looks copy_page()
>> already implement this well so we can complete copy_exc_stack() based on
>> that directly.
>
> I'd rather you don't hijack copy_page which is quite sensitive. The
> emulation isn't performance critical so a "dumber" routine would work
Yes, I just think we should introduce good performance so I 'steal' the original
copy_page().
> fine.
>
> Why not use memcpy ? You can call it from assembly.
I'd like to switch to memcpy.
Thanks
Tiejun
^ permalink raw reply
* Re: [PATCH 1/1] ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
From: tiejun.chen @ 2011-12-13 5:01 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1323681035-19350-1-git-send-email-tiejun.chen@windriver.com>
Tiejun Chen wrote:
> In entry_64.S version of ret_from_except_lite, you'll notice that
> in the !preempt case, after we've checked MSR_PR we test for any
> TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
> or not. However, in the preempt case, we do a convoluted trick to
> test SIGPENDING only if PR was set and always test NEED_RESCHED ...
> but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
> that means that with preempt, we completely fail to test for things
> like single step, syscall tracing, etc...
>
> This should be fixed as the following path:
>
> - Test PR. If set, go to test_work_user, else continue.
>
> - In test_work_user, always test for _TIF_USER_WORK_MASK to decide to
> go to do_work, maybe call it do_user_work
>
> - In test_work_kernel, test for _TIF_KERNEL_WORK_MASK which is set to
> our new flag along with NEED_RESCHED if preempt is enabled and branch to
> do_kernel_work.
Ben,
Any comment for this?
Tiejun
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
> ---
> arch/powerpc/kernel/entry_64.S | 33 +++++++++++++++------------------
> 1 files changed, 15 insertions(+), 18 deletions(-)
>
> diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
> index d834425..9e70b9a 100644
> --- a/arch/powerpc/kernel/entry_64.S
> +++ b/arch/powerpc/kernel/entry_64.S
> @@ -571,27 +571,26 @@ _GLOBAL(ret_from_except_lite)
> mtmsrd r9,1 /* Update machine state */
> #endif /* CONFIG_PPC_BOOK3E */
>
> -#ifdef CONFIG_PREEMPT
> - clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
> - li r0,_TIF_NEED_RESCHED /* bits to check */
> - ld r3,_MSR(r1)
> - ld r4,TI_FLAGS(r9)
> - /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
> - rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
> - and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
> - bne do_work
> -
> -#else /* !CONFIG_PREEMPT */
> ld r3,_MSR(r1) /* Returning to user mode? */
> andi. r3,r3,MSR_PR
> - beq restore /* if not, just restore regs and return */
> + bne test_work_user
>
> + clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
> + li r0,_TIF_USER_WORK_MASK
> +#ifdef CONFIG_PREEMPT
> + ori r0,r0,_TIF_NEED_RESCHED
> +#endif
> + ld r4,TI_FLAGS(r9)
> + and. r0,r4,r0 /* check NEED_RESCHED and maybe _TIF_USER_WORK_MASK */
> + bne do_kernel_work
> + b restore /* if so, just restore regs and return */
> +
> +test_work_user:
> /* Check current_thread_info()->flags */
> clrrdi r9,r1,THREAD_SHIFT
> ld r4,TI_FLAGS(r9)
> andi. r0,r4,_TIF_USER_WORK_MASK
> - bne do_work
> -#endif
> + bne do_user_work
>
> restore:
> BEGIN_FW_FTR_SECTION
> @@ -693,10 +692,8 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
> b .ret_from_except_lite /* loop back and handle more */
> #endif
>
> -do_work:
> +do_kernel_work:
> #ifdef CONFIG_PREEMPT
> - andi. r0,r3,MSR_PR /* Returning to user mode? */
> - bne user_work
> /* Check that preempt_count() == 0 and interrupts are enabled */
> lwz r8,TI_PREEMPT(r9)
> cmpwi cr1,r8,0
> @@ -738,9 +735,9 @@ do_work:
> bne 1b
> b restore
>
> -user_work:
> #endif /* CONFIG_PREEMPT */
>
> +do_user_work:
> /* Enable interrupts */
> #ifdef CONFIG_PPC_BOOK3E
> wrteei 1
^ permalink raw reply
* Linux port availability for p5010 processor
From: Vineeth @ 2011-12-13 5:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: rajarama.b, Senthil CGC
[-- Attachment #1: Type: text/plain, Size: 297 bytes --]
Do we have a linux port available for freescale P5010 processor (with
single E5500 core) ?
*(found arch/powerpc/platforms/pseries ; and a some details on
kernel/cputable.c *)
Is there any reference board which uses this processor ? any reference in
DTS file also will be helpful.
Thanks
Vineeth
[-- Attachment #2: Type: text/html, Size: 1076 bytes --]
^ permalink raw reply
* Re: [PATCH 1/1] ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
From: Benjamin Herrenschmidt @ 2011-12-13 5:55 UTC (permalink / raw)
To: tiejun.chen; +Cc: linuxppc-dev
In-Reply-To: <4EE6DC33.6090409@windriver.com>
On Tue, 2011-12-13 at 13:01 +0800, tiejun.chen wrote:
> Tiejun Chen wrote:
> > In entry_64.S version of ret_from_except_lite, you'll notice that
> > in the !preempt case, after we've checked MSR_PR we test for any
> > TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
> > or not. However, in the preempt case, we do a convoluted trick to
> > test SIGPENDING only if PR was set and always test NEED_RESCHED ...
> > but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
> > that means that with preempt, we completely fail to test for things
> > like single step, syscall tracing, etc...
> >
> > This should be fixed as the following path:
> >
> > - Test PR. If set, go to test_work_user, else continue.
> >
> > - In test_work_user, always test for _TIF_USER_WORK_MASK to decide to
> > go to do_work, maybe call it do_user_work
> >
> > - In test_work_kernel, test for _TIF_KERNEL_WORK_MASK which is set to
> > our new flag along with NEED_RESCHED if preempt is enabled and branch to
> > do_kernel_work.
>
> Ben,
>
> Any comment for this?
Sorry, I didn't get to review that one yet (nor reply to your newer
responses), I have very sore eyes and basically had to get off the
computer. Hopefully I'll be better tomorrow.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 1/1] ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
From: tiejun.chen @ 2011-12-13 6:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1323755709.19891.60.camel@pasglop>
Benjamin Herrenschmidt wrote:
> On Tue, 2011-12-13 at 13:01 +0800, tiejun.chen wrote:
>> Tiejun Chen wrote:
>>> In entry_64.S version of ret_from_except_lite, you'll notice that
>>> in the !preempt case, after we've checked MSR_PR we test for any
>>> TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
>>> or not. However, in the preempt case, we do a convoluted trick to
>>> test SIGPENDING only if PR was set and always test NEED_RESCHED ...
>>> but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
>>> that means that with preempt, we completely fail to test for things
>>> like single step, syscall tracing, etc...
>>>
>>> This should be fixed as the following path:
>>>
>>> - Test PR. If set, go to test_work_user, else continue.
>>>
>>> - In test_work_user, always test for _TIF_USER_WORK_MASK to decide to
>>> go to do_work, maybe call it do_user_work
>>>
>>> - In test_work_kernel, test for _TIF_KERNEL_WORK_MASK which is set to
>>> our new flag along with NEED_RESCHED if preempt is enabled and branch to
>>> do_kernel_work.
>> Ben,
>>
>> Any comment for this?
>
> Sorry, I didn't get to review that one yet (nor reply to your newer
I'm nothing, please do this when you're fine completely.
Thanks
Tiejun
> responses), I have very sore eyes and basically had to get off the
> computer. Hopefully I'll be better tomorrow.
>
> Cheers,
> Ben.
^ permalink raw reply
* [PATCH] powerpc: Fix comment explaining our VSID layout
From: Anton Blanchard @ 2011-12-13 6:16 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
We support 16TB of user address space and half a million contexts
so update the comment to reflect this.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: linux-powerpc/arch/powerpc/include/asm/mmu-hash64.h
===================================================================
--- linux-powerpc.orig/arch/powerpc/include/asm/mmu-hash64.h 2011-12-13 14:47:14.498301148 +1100
+++ linux-powerpc/arch/powerpc/include/asm/mmu-hash64.h 2011-12-13 14:58:01.085510915 +1100
@@ -312,10 +312,9 @@ extern void slb_set_size(u16 size);
* (i.e. everything above 0xC000000000000000), except the very top
* segment, which simplifies several things.
*
- * - We allow for 15 significant bits of ESID and 20 bits of
- * context for user addresses. i.e. 8T (43 bits) of address space for
- * up to 1M contexts (although the page table structure and context
- * allocation will need changes to take advantage of this).
+ * - We allow for 16 significant bits of ESID and 19 bits of
+ * context for user addresses. i.e. 16T (44 bits) of address space for
+ * up to half a million contexts.
*
* - The scramble function gives robust scattering in the hash
* table (at least based on some initial results). The previous
^ permalink raw reply
* [PATCH 01/19] mxc_udc: add workaround for ENGcm09152 for i.MX25
From: Eric Bénard @ 2011-12-13 6:31 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Greg Kroah-Hartman, open list:FREESCALE USB PER..., open list,
Felipe Balbi, Sascha Hauer, open list:FREESCALE USB PER...
this patch gives the possibility to workaround bug ENGcm09152
on i.MX25 when the hardware workaround is also implemented on
the board.
It covers the workaround described on page 42 of the following Errata :
http://cache.freescale.com/files/dsp/doc/errata/IMX25CE.pdf
Signed-off-by: Eric Bénard <eric@eukrea.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Cc: Li Yang <leoli@freescale.com>
---
drivers/usb/gadget/fsl_mxc_udc.c | 22 +++++++++++++---------
1 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index dcbc0a2..4aff05d 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -23,7 +23,7 @@
static struct clk *mxc_ahb_clk;
static struct clk *mxc_usb_clk;
-/* workaround ENGcm09152 for i.MX35 */
+/* workaround ENGcm09152 for i.MX25/35 */
#define USBPHYCTRL_OTGBASE_OFFSET 0x608
#define USBPHYCTRL_EVDO (1 << 23)
@@ -89,16 +89,20 @@ eenahb:
void fsl_udc_clk_finalize(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
- if (cpu_is_mx35()) {
+ if (cpu_is_mx25() || cpu_is_mx35()) {
unsigned int v;
-
- /* workaround ENGcm09152 for i.MX35 */
+ void __iomem *otgbase;
+ if (cpu_is_mx25())
+ otgbase = MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
+ USBPHYCTRL_OTGBASE_OFFSET);
+ else if (cpu_is_mx35())
+ otgbase = MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
+ USBPHYCTRL_OTGBASE_OFFSET);
+
+ /* workaround ENGcm09152 for i.MX25/35 */
if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
- v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
- USBPHYCTRL_OTGBASE_OFFSET));
- writel(v | USBPHYCTRL_EVDO,
- MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
- USBPHYCTRL_OTGBASE_OFFSET));
+ v = readl(otgbase);
+ writel(v | USBPHYCTRL_EVDO, otgbase);
}
}
--
1.7.6.4
^ permalink raw reply related
* RE: [PATCH] mmc: sdhci-pltfm: Added sdhci-adjust-timeout quirk
From: Huang Changming-R66093 @ 2011-12-13 8:00 UTC (permalink / raw)
To: Xie Xiaobo-R63061, linuxppc-dev@lists.ozlabs.org
Cc: avorontsov@ru.mvista.com, linux-mmc@vger.kernel.org,
Xie Xiaobo-R63061
In-Reply-To: <1323075320-9138-1-git-send-email-X.Xie@freescale.com>
Xiaobo, I have one other similar patch, but the property is 'sdhci,adjust-t=
imeout'.
Maybe I can repost it with add your signed-off-by?
> -----Original Message-----
> From: linuxppc-dev-bounces+r66093=3Dfreescale.com@lists.ozlabs.org
> [mailto:linuxppc-dev-bounces+r66093=3Dfreescale.com@lists.ozlabs.org] On
> Behalf Of Xie Xiaobo
> Sent: Monday, December 05, 2011 4:55 PM
> To: linuxppc-dev@lists.ozlabs.org
> Cc: avorontsov@ru.mvista.com; linux-mmc@vger.kernel.org; Xie Xiaobo-
> R63061
> Subject: [PATCH] mmc: sdhci-pltfm: Added sdhci-adjust-timeout quirk
>=20
> Some controller provides an incorrect timeout value for transfers,
> So it need the quirk to adjust timeout value to 0xE.
> E.g. eSDHC of MPC8536, P1010, and P2020.
>=20
> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
> ---
> drivers/mmc/host/sdhci-pltfm.c | 5 ++++-
> 1 files changed, 4 insertions(+), 1 deletions(-)
>=20
> diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-
> pltfm.c
> index a9e12ea..b5d6b3f 100644
> --- a/drivers/mmc/host/sdhci-pltfm.c
> +++ b/drivers/mmc/host/sdhci-pltfm.c
> @@ -2,7 +2,7 @@
> * sdhci-pltfm.c Support for SDHCI platform devices
> * Copyright (c) 2009 Intel Corporation
> *
> - * Copyright (c) 2007 Freescale Semiconductor, Inc.
> + * Copyright (c) 2007, 2011 Freescale Semiconductor, Inc.
> * Copyright (c) 2009 MontaVista Software, Inc.
> *
> * Authors: Xiaobo Xie <X.Xie@freescale.com>
> @@ -68,6 +68,9 @@ void sdhci_get_of_property(struct platform_device *pdev=
)
> if (of_get_property(np, "sdhci,1-bit-only", NULL))
> host->quirks |=3D SDHCI_QUIRK_FORCE_1_BIT_DATA;
>=20
> + if (of_get_property(np, "sdhci,sdhci-adjust-timeout", NULL))
> + host->quirks |=3D SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
> +
> if (sdhci_of_wp_inverted(np))
> host->quirks |=3D SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
>=20
> --
> 1.6.4
>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 3/4] ppc32/kprobe: complete kprobe and migrate exception frame
From: tiejun.chen @ 2011-12-13 8:21 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <4EE6DA8C.8090107@windriver.com>
>>
>> You need to hook into "resume_kernel" instead.
>
> Maybe I'm misunderstanding what you mean since as I recall you suggestion we
> should do this at the end of do_work.
>
I regenerate this with hooking into resume_kernel in below.
>> Also, we may want to simplify the whole thing, instead of checking user
>> vs. kernel first etc... we could instead have a single _TIF_WORK_MASK
>> which includes both the bits for user work and the new bit for kernel
>> work. With preempt, the kernel work bits would also include
>> _TIF_NEED_RESCHED.
>>
>> Then you have in the common exit path, a single test for that, with a
>> fast path that skips everything and just goes to "restore" for both
>> kernel and user.
>>
>> The only possible issue is the setting of dbcr0 for BookE and 44x and we
>> can keep that as a special case keyed of MSR_PR in the resume path under
>> ifdef BOOKE (we'll probably sanitize that later with some different
>> rework anyway).
>>
>> So the exit path because something like:
>>
>> ret_from_except:
>> .. hard disable interrupts (unchanged) ...
>> read TIF flags
>> andi with _TIF_WORK_MASK
>> nothing set -> restore
>> check PR
>> set -> do_work_user
>> no set -> do_work_kernel (kprobes & preempt)
>> (both loop until relevant _TIF flags are all clear)
>> restore:
>> #ifdef BOOKE & 44x test PR & do dbcr0 stuff if needed
>> ... nornal restore ...
>
> Do you mean we should reorganize current ret_from_except for ppc32 as well?
I assume it may not necessary to reorganize ret_from_except for *ppc32*.
>
>>> do_user_signal: /* r10 contains MSR_KERNEL here */
>>> ori r10,r10,MSR_EE
>>> SYNC
>>> @@ -1202,6 +1204,30 @@ do_user_signal: /* r10 contains MSR_KERNEL here */
>>> REST_NVGPRS(r1)
>>> b recheck
>>>
>>> +restore_kprobe:
>>> + lwz r3,GPR1(r1)
>>> + subi r3,r3,INT_FRAME_SIZE; /* Allocate a trampoline exception frame */
>>> + mr r4,r1
>>> + bl copy_exc_stack /* Copy from the original to the trampoline */
>>> +
>>> + /* Do real stw operation to complete stwu */
>>> + mr r4,r1
>>> + addi r4,r4,INT_FRAME_SIZE /* Get kprobed entry */
>>> + lwz r5,GPR1(r1) /* Backup r1 */
>>> + stw r4,GPR1(r1) /* Now store that safely */
>> The above confuses me. Shouldn't you do instead something like
>>
>> lwz r4,GPR1(r1)
Now GPR1(r1) is already pointed with new r1 in emulate_step().
>> subi r3,r4,INT_FRAME_SIZE
Here we need this, 'mr r4,r1', since r1 holds current exception stack.
>> li r5,INT_FRAME_SIZE
>> bl memcpy
Then the current exception stack is migrated below the kprobed function stack.
stack flow:
-------------------------- -> old r1 when hit 'stwu r1, -AA(r1)' in our
^ ^ kprobed function entry.
| |
| |------------> AA allocated for the kprobed function
| |
| v
--------|----------------- -> new r1, also GPR1(r1). It holds the kprobed
^ | function stack , -AA(r1).
| |
| |--------------------> INT_FRAME_SIZE for program exception
| |
| v
---|--------------------- -> r1 is updated to hold program exception stack.
|
|
|------------------------> migrate the exception stack (r1) below the
| kprobed after memcpy with INT_FRAME_SIZE.
v
------------------------- -> reroute this as r1 for program exception stack.
>>
>
> Anyway I'll try this if you think memcpy is fine/safe in exception return codes.
>
>> To start with, then you need to know the "old" r1 value which may or may
>> not be related to your current r1. The emulation code should stash it
>
> If the old r1 is not related to our current r1, it shouldn't be possible to go
> restore_kprob since we set that new flag only for the current.
If you agree what I say above, please check the follow:
======
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 56212bc..b6554c1 100644
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 56212bc..b6554c1 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -813,12 +813,40 @@ restore_user:
#ifdef CONFIG_PREEMPT
b restore
+#endif
-/* N.B. the only way to get here is from the beq following ret_from_except. */
resume_kernel:
/* check current_thread_info->preempt_count */
rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
lwz r0,TI_PREEMPT(r9)
+ andis. r0,r0,_TIF_EMULATE_STACK_STORE@h
+ beq+ restore
+
+ lwz r3,GPR1(r1)
+ subi r3,r3,INT_FRAME_SIZE /* Allocate a trampoline exception frame */
+ mr r4,r1
+ li r5,INT_FRAME_SIZE
+ bl memcpy /* Copy from the original to the
trampoline */
+
+ /* Do real store operation to complete stwu */
+ addi r4,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
+ lwz r5,GPR1(r1)
+ stw r4,0(r5) /* Now store that safely */
+
+ /* Reroute the trampoline frame to r1 */
+ subi r1,r5,INT_FRAME_SIZE
+
+ /* Clear _TIF_EMULATE_STACK_STORE flag */
+ rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
+ lwz r0,TI_FLAGS(r9)
+ rlwinm r0,r0,0,_TIF_EMULATE_STACK_STORE
+ stw r0,TI_FLAGS(r9)
+
+#ifdef CONFIG_PREEMPT
+/* N.B. the only way to get here is from the beq following ret_from_except. */
+ /* check current_thread_info->preempt_count */
+ rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
+ lwz r0,TI_PREEMPT(r9)
cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
bne restore
lwz r0,TI_FLAGS(r9)
@@ -844,8 +872,6 @@ resume_kernel:
*/
bl trace_hardirqs_on
#endif
-#else
-resume_kernel:
#endif /* CONFIG_PREEMPT */
/* interrupts are hard-disabled at this point */
Tiejun
^ permalink raw reply related
* [PATCH RESEND] gpio: mpc8xxx: don't allow input-only pins to be output for MPC5121
From: Wolfram Sang @ 2011-12-13 9:12 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Anatolij Gustschin, linux-kernel, Linus Walleij
Add a 5121-custom reject if an input-only pin is requested to be output
(see 18.3.1.1 in the refman). Also, rewrite mach-specific quirk setup to
consume less lines which scales better.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
---
drivers/gpio/gpio-mpc8xxx.c | 17 ++++++++++++-----
1 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
index ec3fcf0..25dc736 100644
--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
@@ -115,6 +115,14 @@ static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
return 0;
}
+static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ /* GPIO 28..31 are input only on MPC5121 */
+ if (gpio >= 28)
+ return -EINVAL;
+
+ return mpc8xxx_gpio_dir_out(gc, gpio, val);
+}
static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
@@ -340,11 +348,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
mm_gc->save_regs = mpc8xxx_gpio_save_regs;
gc->ngpio = MPC8XXX_GPIO_PINS;
gc->direction_input = mpc8xxx_gpio_dir_in;
- gc->direction_output = mpc8xxx_gpio_dir_out;
- if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
- gc->get = mpc8572_gpio_get;
- else
- gc->get = mpc8xxx_gpio_get;
+ gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
+ mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
+ gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
+ mpc8572_gpio_get : mpc8xxx_gpio_get;
gc->set = mpc8xxx_gpio_set;
gc->to_irq = mpc8xxx_gpio_to_irq;
--
1.7.7.1
^ permalink raw reply related
* Re: [PATCH RESEND] gpio: mpc8xxx: don't allow input-only pins to be output for MPC5121
From: Anatolij Gustschin @ 2011-12-13 9:52 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linuxppc-dev, linux-kernel, Linus Walleij
In-Reply-To: <1323767568-9565-1-git-send-email-w.sang@pengutronix.de>
Hi Wolfram,
Looks mostly good to me. Please see minor comments below.
On Tue, 13 Dec 2011 10:12:48 +0100
Wolfram Sang <w.sang@pengutronix.de> wrote:
...
> diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
> index ec3fcf0..25dc736 100644
> --- a/drivers/gpio/gpio-mpc8xxx.c
> +++ b/drivers/gpio/gpio-mpc8xxx.c
> @@ -115,6 +115,14 @@ static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
> return 0;
> }
>
> +static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
Line over 80 chars.
> +{
> + /* GPIO 28..31 are input only on MPC5121 */
> + if (gpio >= 28)
> + return -EINVAL;
> +
> + return mpc8xxx_gpio_dir_out(gc, gpio, val);
> +}
> static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
Please separate by an empty line. Thanks.
Anatolij
^ permalink raw reply
* Re: [PATCH RESEND] gpio: mpc8xxx: don't allow input-only pins to be output for MPC5121
From: Wolfram Sang @ 2011-12-13 10:03 UTC (permalink / raw)
To: Anatolij Gustschin; +Cc: linuxppc-dev, linux-kernel, Linus Walleij
In-Reply-To: <20111213105243.101ced70@wker>
[-- Attachment #1: Type: text/plain, Size: 1256 bytes --]
On Tue, Dec 13, 2011 at 10:52:43AM +0100, Anatolij Gustschin wrote:
> Hi Wolfram,
>
> Looks mostly good to me. Please see minor comments below.
>
> On Tue, 13 Dec 2011 10:12:48 +0100
> Wolfram Sang <w.sang@pengutronix.de> wrote:
> ...
> > diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c
> > index ec3fcf0..25dc736 100644
> > --- a/drivers/gpio/gpio-mpc8xxx.c
> > +++ b/drivers/gpio/gpio-mpc8xxx.c
> > @@ -115,6 +115,14 @@ static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
> > return 0;
> > }
> >
> > +static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
>
> Line over 80 chars.
In this case, I think the alternative would be far less readable.
> > +{
> > + /* GPIO 28..31 are input only on MPC5121 */
> > + if (gpio >= 28)
> > + return -EINVAL;
> > +
> > + return mpc8xxx_gpio_dir_out(gc, gpio, val);
> > +}
> > static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
>
> Please separate by an empty line. Thanks.
Ups, yes.
Thanks,
Wolfram
--
Pengutronix e.K. | Wolfram Sang |
Industrial Linux Solutions | http://www.pengutronix.de/ |
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply
* Re: [PATCH 3/4] ppc32/kprobe: complete kprobe and migrate exception frame
From: tiejun.chen @ 2011-12-13 10:11 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <4EE70B13.7000102@windriver.com>
Sorry please ignore this email since I'm missing something here :(
Tiejun
tiejun.chen wrote:
>>> You need to hook into "resume_kernel" instead.
>> Maybe I'm misunderstanding what you mean since as I recall you suggestion we
>> should do this at the end of do_work.
>>
>
> I regenerate this with hooking into resume_kernel in below.
>
>>> Also, we may want to simplify the whole thing, instead of checking user
>>> vs. kernel first etc... we could instead have a single _TIF_WORK_MASK
>>> which includes both the bits for user work and the new bit for kernel
>>> work. With preempt, the kernel work bits would also include
>>> _TIF_NEED_RESCHED.
>>>
>>> Then you have in the common exit path, a single test for that, with a
>>> fast path that skips everything and just goes to "restore" for both
>>> kernel and user.
>>>
>>> The only possible issue is the setting of dbcr0 for BookE and 44x and we
>>> can keep that as a special case keyed of MSR_PR in the resume path under
>>> ifdef BOOKE (we'll probably sanitize that later with some different
>>> rework anyway).
>>>
>>> So the exit path because something like:
>>>
>>> ret_from_except:
>>> .. hard disable interrupts (unchanged) ...
>>> read TIF flags
>>> andi with _TIF_WORK_MASK
>>> nothing set -> restore
>>> check PR
>>> set -> do_work_user
>>> no set -> do_work_kernel (kprobes & preempt)
>>> (both loop until relevant _TIF flags are all clear)
>>> restore:
>>> #ifdef BOOKE & 44x test PR & do dbcr0 stuff if needed
>>> ... nornal restore ...
>> Do you mean we should reorganize current ret_from_except for ppc32 as well?
>
> I assume it may not necessary to reorganize ret_from_except for *ppc32*.
>
>>>> do_user_signal: /* r10 contains MSR_KERNEL here */
>>>> ori r10,r10,MSR_EE
>>>> SYNC
>>>> @@ -1202,6 +1204,30 @@ do_user_signal: /* r10 contains MSR_KERNEL here */
>>>> REST_NVGPRS(r1)
>>>> b recheck
>>>>
>>>> +restore_kprobe:
>>>> + lwz r3,GPR1(r1)
>>>> + subi r3,r3,INT_FRAME_SIZE; /* Allocate a trampoline exception frame */
>>>> + mr r4,r1
>>>> + bl copy_exc_stack /* Copy from the original to the trampoline */
>>>> +
>>>> + /* Do real stw operation to complete stwu */
>>>> + mr r4,r1
>>>> + addi r4,r4,INT_FRAME_SIZE /* Get kprobed entry */
>>>> + lwz r5,GPR1(r1) /* Backup r1 */
>>>> + stw r4,GPR1(r1) /* Now store that safely */
>>> The above confuses me. Shouldn't you do instead something like
>>>
>>> lwz r4,GPR1(r1)
>
> Now GPR1(r1) is already pointed with new r1 in emulate_step().
>
>>> subi r3,r4,INT_FRAME_SIZE
>
> Here we need this, 'mr r4,r1', since r1 holds current exception stack.
>
>>> li r5,INT_FRAME_SIZE
>>> bl memcpy
>
> Then the current exception stack is migrated below the kprobed function stack.
>
> stack flow:
>
> -------------------------- -> old r1 when hit 'stwu r1, -AA(r1)' in our
> ^ ^ kprobed function entry.
> | |
> | |------------> AA allocated for the kprobed function
> | |
> | v
> --------|----------------- -> new r1, also GPR1(r1). It holds the kprobed
> ^ | function stack , -AA(r1).
> | |
> | |--------------------> INT_FRAME_SIZE for program exception
> | |
> | v
> ---|--------------------- -> r1 is updated to hold program exception stack.
> |
> |
> |------------------------> migrate the exception stack (r1) below the
> | kprobed after memcpy with INT_FRAME_SIZE.
> v
> ------------------------- -> reroute this as r1 for program exception stack.
>
>> Anyway I'll try this if you think memcpy is fine/safe in exception return codes.
>>
>>> To start with, then you need to know the "old" r1 value which may or may
>>> not be related to your current r1. The emulation code should stash it
>> If the old r1 is not related to our current r1, it shouldn't be possible to go
>> restore_kprob since we set that new flag only for the current.
>
> If you agree what I say above, please check the follow:
> ======
> diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
> index 56212bc..b6554c1 100644
> diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
> index 56212bc..b6554c1 100644
> --- a/arch/powerpc/kernel/entry_32.S
> +++ b/arch/powerpc/kernel/entry_32.S
> @@ -813,12 +813,40 @@ restore_user:
>
> #ifdef CONFIG_PREEMPT
> b restore
> +#endif
>
> -/* N.B. the only way to get here is from the beq following ret_from_except. */
> resume_kernel:
> /* check current_thread_info->preempt_count */
> rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
> lwz r0,TI_PREEMPT(r9)
> + andis. r0,r0,_TIF_EMULATE_STACK_STORE@h
> + beq+ restore
> +
> + lwz r3,GPR1(r1)
> + subi r3,r3,INT_FRAME_SIZE /* Allocate a trampoline exception frame */
> + mr r4,r1
> + li r5,INT_FRAME_SIZE
> + bl memcpy /* Copy from the original to the
> trampoline */
> +
> + /* Do real store operation to complete stwu */
> + addi r4,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
> + lwz r5,GPR1(r1)
> + stw r4,0(r5) /* Now store that safely */
> +
> + /* Reroute the trampoline frame to r1 */
> + subi r1,r5,INT_FRAME_SIZE
> +
> + /* Clear _TIF_EMULATE_STACK_STORE flag */
> + rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
> + lwz r0,TI_FLAGS(r9)
> + rlwinm r0,r0,0,_TIF_EMULATE_STACK_STORE
> + stw r0,TI_FLAGS(r9)
> +
> +#ifdef CONFIG_PREEMPT
> +/* N.B. the only way to get here is from the beq following ret_from_except. */
> + /* check current_thread_info->preempt_count */
> + rlwinm r9,r1,0,0,(31-THREAD_SHIFT)
> + lwz r0,TI_PREEMPT(r9)
> cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
> bne restore
> lwz r0,TI_FLAGS(r9)
> @@ -844,8 +872,6 @@ resume_kernel:
> */
> bl trace_hardirqs_on
> #endif
> -#else
> -resume_kernel:
> #endif /* CONFIG_PREEMPT */
>
> /* interrupts are hard-disabled at this point */
>
> Tiejun
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox