* RE: [PATCH 00/14] DMA-mapping framework redesign preparation
From: Marek Szyprowski @ 2011-12-28 12:52 UTC (permalink / raw)
To: 'James Bottomley'
Cc: linux-mips, linux-ia64, linux-sh, linux-mm, sparclinux,
linux-arch, 'Stephen Rothwell', 'Jonathan Corbet',
x86, 'Arnd Bergmann', 'Matthew Wilcox',
microblaze-uclinux, linaro-mm-sig, Andrzej Pietrasiewicz,
'Thomas Gleixner', linux-arm-kernel, discuss,
linux-kernel, 'Kyungmin Park', linux-alpha,
'Andrew Morton', linuxppc-dev
In-Reply-To: <1325008393.14252.5.camel@dabdike>
Hello,
On Tuesday, December 27, 2011 6:53 PM James Bottomley wrote:
> On Tue, 2011-12-27 at 09:25 +0100, Marek Szyprowski wrote:
> [...]
> > > > Usually these drivers don't touch the buffer data at all, so the mapping
> > > > in kernel virtual address space is not needed. We can introduce
> > > > DMA_ATTRIB_NO_KERNEL_MAPPING attribute which lets kernel to skip/ignore
> > > > creation of kernel virtual mapping. This way we can save previous
> > > > vmalloc area and simply some mapping operation on a few architectures.
> > >
> > > I really think this wants to be a separate function. dma_alloc_coherent
> > > is for allocating memory to be shared between the kernel and a driver;
> > > we already have dma_map_sg for mapping userspace I/O as an alternative
> > > interface. This feels like it's something different again rather than
> > > an option to dma_alloc_coherent.
> >
> > That is just a starting point for the discussion.
> >
> > I thought about this API a bit and came to conclusion that there is no much
> > difference between a dma_alloc_coherent which creates a mapping in kernel
> > virtual space and the one that does not. It is just a hint from the driver
> > that it will not use that mapping at all. Of course this attribute makes sense
> > only together with adding a dma_mmap_attrs() call, because otherwise drivers
> > won't be able to get access to the buffer data.
>
> This depends. On Virtually indexed systems like PA-RISC, there are two
> ways of making a DMA range coherent. One is to make the range uncached.
> This is incredibly slow and not what we do by default, but it can be
> used to make multiple mappings coherent. The other is to load the
> virtual address up as a coherence index into the IOMMU. This makes it a
> full peer in the coherence process, but means we can only designate a
> single virtual range to be coherent (not multiple mappings unless they
> happen to be congruent). Perhaps it doesn't matter that much, since I
> don't see a use for this on PA, but if any other architecture works the
> same, you'd have to designate a single mapping as the coherent one and
> essentially promise not to use the other mapping if we followed our
> normal coherence protocols.
>
> Obviously, the usual range we currently make coherent is the kernel
> mapping (that's actually the only virtual address we have by the time
> we're deep in the iommu code), so designating a different virtual
> address would need some surgery to the guts of the iommu code.
I see, in this case not much can be achieved by dropping the kernel
mapping for the allocated buffer. I'm also not sure how to mmap the buffer
into userspace meet the cpu requirements? Is it possible to use non-cached
mapping in userspace together with coherent mapping in kernel virtual
space?
However on some other architectures this attribute allows using HIGH_MEM
for the allocated coherent buffer. The other possibility is to allocate it
in chunks and map them contiguously into dma address space. With
NO_KERNEL_MAPPING attribute we avoid consuming vmalloc range for the newly
allocated buffer for which we cannot use the linear mapping (because it is
scattered).
Of course this attribute will be implemented by the architectures where it
gives some benefits. All other can simply ignore it and return plain
coherent buffer with ordinary kernel virtual mapping. The driver will just
ignore it.
Best regards
--
Marek Szyprowski
Samsung Poland R&D Center
^ permalink raw reply
* Re: [PATCH 1/2][v2] Integrated Flash Controller support
From: dmitry pervushin @ 2011-12-28 13:30 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: Scott Wood, Dipen Dudhat, linuxppc-dev, Liu Shuo
In-Reply-To: <1324987753-30318-1-git-send-email-prabhakar@freescale.com>
On Tue, 2011-12-27 at 17:39 +0530, Prabhakar Kushwaha wrote:
[...]
> +/*
> + * IFC Controller NAND Machine registers
> + */
> +struct fsl_ifc_nand {
> + __be32 ncfgr;
> + u32 res1[0x4];
> + __be32 nand_fcr0;
> + __be32 nand_fcr1;
> + u32 res2[0x8];
> + __be32 row0;
> + u32 res3;
> + __be32 col0;
> + u32 res4;
> + __be32 row1;
> + u32 res5;
> + __be32 col1;
> + u32 res6;
> + __be32 row2;
> + u32 res7;
> + __be32 col2;
> + u32 res8;
> + __be32 row3;
> + u32 res9;
> + __be32 col3;
> + u32 res10[0x24];
> + __be32 nand_fbcr;
> + u32 res11;
> + __be32 nand_fir0;
> + __be32 nand_fir1;
> + __be32 nand_fir2;
> + u32 res12[0x10];
> + __be32 nand_csel;
> + u32 res13;
> + __be32 nandseq_strt;
> + u32 res14;
> + __be32 nand_evter_stat;
> + u32 res15;
> + __be32 pgrdcmpl_evt_stat;
> + u32 res16[0x2];
> + __be32 nand_evter_en;
> + u32 res17[0x2];
> + __be32 nand_evter_intr_en;
> + u32 res18[0x2];
> + __be32 nand_erattr0;
> + __be32 nand_erattr1;
> + u32 res19[0x10];
> + __be32 nand_fsr;
> + u32 res20;
> + __be32 nand_eccstat[4];
> + u32 res21[0x20];
> + __be32 nanndcr;
> + u32 res22[0x2];
> + __be32 nand_autoboot_trgr;
> + u32 res23;
> + __be32 nand_mdr;
> + u32 res24[0x5C];
> +};
If you're using memory-mapped structure, shouldn't it be announced with
__attribute__(packed) ?
> +
> +/*
> + * IFC controller NOR Machine registers
> + */
> +struct fsl_ifc_nor {
> + __be32 nor_evter_stat;
> + u32 res1[0x2];
> + __be32 nor_evter_en;
> + u32 res2[0x2];
> + __be32 nor_evter_intr_en;
> + u32 res3[0x2];
> + __be32 nor_erattr0;
> + __be32 nor_erattr1;
> + __be32 nor_erattr2;
> + u32 res4[0x4];
> + __be32 norcr;
> + u32 res5[0xEF];
> +};
> +
> +/*
> + * IFC controller GPCM Machine registers
> + */
> +struct fsl_ifc_gpcm {
> + __be32 gpcm_evter_stat;
> + u32 res1[0x2];
> + __be32 gpcm_evter_en;
> + u32 res2[0x2];
> + __be32 gpcm_evter_intr_en;
> + u32 res3[0x2];
> + __be32 gpcm_erattr0;
> + __be32 gpcm_erattr1;
> + __be32 gpcm_erattr2;
> + __be32 gpcm_stat;
> + u32 res4[0x1F3];
> +};
...here too...
> +
> +/*
> + * IFC Controller Registers
> + */
> +struct fsl_ifc_regs {
> + __be32 ifc_rev;
> + u32 res1[0x3];
> + struct {
> + __be32 cspr;
> + u32 res2[0x2];
> + } cspr_cs[FSL_IFC_BANK_COUNT];
> + u32 res3[0x18];
> + struct {
> + __be32 amask;
> + u32 res4[0x2];
> + } amask_cs[FSL_IFC_BANK_COUNT];
> + u32 res5[0x18];
> + struct {
> + __be32 csor;
> + u32 res6[0x2];
> + } csor_cs[FSL_IFC_BANK_COUNT];
> + u32 res7[0x18];
> + struct {
> + __be32 ftim[4];
> + u32 res8[0x8];
> + } ftim_cs[FSL_IFC_BANK_COUNT];
> + u32 res9[0x60];
> + __be32 rb_stat;
> + u32 res10[0x2];
> + __be32 ifc_gcr;
> + u32 res11[0x2];
> + __be32 cm_evter_stat;
> + u32 res12[0x2];
> + __be32 cm_evter_en;
> + u32 res13[0x2];
> + __be32 cm_evter_intr_en;
> + u32 res14[0x2];
> + __be32 cm_erattr0;
> + __be32 cm_erattr1;
> + u32 res15[0x2];
> + __be32 ifc_ccr;
> + __be32 ifc_csr;
> + u32 res16[0x2EB];
> + struct fsl_ifc_nand ifc_nand;
> + struct fsl_ifc_nor ifc_nor;
> + struct fsl_ifc_gpcm ifc_gpcm;
> +};
...and here.
> +
> +extern unsigned int convert_ifc_address(phys_addr_t addr_base);
> +extern int fsl_ifc_find(phys_addr_t addr_base);
> +
> +/* overview of the fsl ifc controller */
> +
> +struct fsl_ifc_ctrl {
> + /* device info */
> + struct device *dev;
> + struct fsl_ifc_regs __iomem *regs;
> + int irq;
> + int nand_irq;
> + spinlock_t lock;
> + void *nand;
> +
> + u32 nand_stat;
> + wait_queue_head_t nand_wait;
> +};
> +
> +extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
> +
> +
> +#endif /* __ASM_FSL_IFC_H */
^ permalink raw reply
* mtd/NAND:Fix issues with freescale IFC to support NAND 2K
From: Prabhakar Kushwaha @ 2011-12-29 4:59 UTC (permalink / raw)
To: linuxppc-dev, linux-mtd; +Cc: scottwood
This Patch series takes care issues with Freescale IFC driver for supporting 2K
page size NAND with ECC enabled.
[PATCH 1/2] mtd/nand:Fix wrong address read in is_blank()
Fix driver issue when ECC enabled.
[PATCH 2/2] mtd/nand: Fix IFC driver to support 2K NAND page
Fix driver during OOB updation
^ permalink raw reply
* [PATCH 1/2] mtd/nand:Fix wrong address read in is_blank()
From: Prabhakar Kushwaha @ 2011-12-29 4:59 UTC (permalink / raw)
To: linuxppc-dev, linux-mtd; +Cc: scottwood, Poonam Aggrwal, Prabhakar Kushwaha
In-Reply-To: <1325134779-3571-1-git-send-email-prabhakar@freescale.com>
IFC NAND Machine calculates ECC on 512byte sector. Same is taken care in
fsl_ifc_run_command() while ECC status verification. Here buffer number is
calculated assuming 512byte sector and same is passed to is_blank.
However in is_blank() buffer address is calculated using mdt->writesize which is
wrong. It should be calculated on basis of ecc sector size.
Also, in fsl_ifc_run_command() bufferpage is calculated on the basis of ecc sector
size instead of hard coded value.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)
Tested on P1010RDB
drivers/mtd/nand/fsl_ifc_nand.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 8475b88..2df7206 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -191,7 +191,9 @@ static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
{
struct nand_chip *chip = mtd->priv;
struct fsl_ifc_mtd *priv = chip->priv;
- u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
+ int bufperpage = mtd->writesize / chip->ecc.size;
+ u8 __iomem *addr = priv->vbase + bufnum / bufperpage
+ * (mtd->writesize * 2);
u32 __iomem *mainarea = (u32 *)addr;
u8 __iomem *oob = addr + mtd->writesize;
int i;
@@ -273,7 +275,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
dev_err(priv->dev, "NAND Flash Write Protect Error\n");
if (nctrl->eccread) {
- int bufperpage = mtd->writesize / 512;
+ int bufperpage = mtd->writesize / chip->ecc.size;
int bufnum = (nctrl->page & priv->bufnum_mask) * bufperpage;
int bufnum_end = bufnum + bufperpage - 1;
--
1.7.5.4
^ permalink raw reply related
* [PATCH 2/2] mtd/nand: Fix IFC driver to support 2K NAND page
From: Prabhakar Kushwaha @ 2011-12-29 4:59 UTC (permalink / raw)
To: linuxppc-dev, linux-mtd; +Cc: scottwood, Poonam Aggrwal, Prabhakar Kushwaha
In-Reply-To: <1325134779-3571-1-git-send-email-prabhakar@freescale.com>
1) OOB area should be updated irrespective of NAND page size. Earlier it was
updated only for 512byte NAND page.
2) During OOB update fbcr should be equal to OOB size.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)
Tested on P1010RDB
drivers/mtd/nand/fsl_ifc_nand.c | 20 ++++++++------------
1 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 2df7206..2c02168 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -439,20 +439,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
out_be32(&ifc->ifc_nand.nand_fir1,
(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
- if (column >= mtd->writesize) {
- /* OOB area --> READOOB */
- column -= mtd->writesize;
- nand_fcr0 |= NAND_CMD_READOOB <<
- IFC_NAND_FCR0_CMD0_SHIFT;
- ifc_nand_ctrl->oob = 1;
- } else if (column < 256)
+ if (column < 256)
/* First 256 bytes --> READ0 */
nand_fcr0 |=
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
- else
- /* Second 256 bytes --> READ1 */
- nand_fcr0 |=
- NAND_CMD_READ1 << IFC_NAND_FCR0_CMD0_SHIFT;
+ }
+
+ if (column >= mtd->writesize) {
+ /* OOB area --> READOOB */
+ column -= mtd->writesize;
+ ifc_nand_ctrl->oob = 1;
}
out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
@@ -465,7 +461,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
int full_page;
if (ifc_nand_ctrl->oob) {
out_be32(&ifc->ifc_nand.nand_fbcr,
- ifc_nand_ctrl->index);
+ ifc_nand_ctrl->index - ifc_nand_ctrl->column);
full_page = 0;
} else {
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
--
1.7.5.4
^ permalink raw reply related
* [PATCH 1/2][v3] Integrated Flash Controller support
From: Prabhakar Kushwaha @ 2011-12-29 5:59 UTC (permalink / raw)
To: linuxppc-dev, linux-mtd
Cc: Scott Wood, Dipen Dudhat, Liu Shuo, Prabhakar Kushwaha
Integrated Flash Controller supports various flashes like NOR, NAND
and other devices using NOR, NAND and GPCM Machine available on it.
IFC supports four chip selects.
Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Liu Shuo <b35362@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)
Tested on P1010RDB
Changes for v2: Incorporated Artem Bityutskiy's comment
- Error handling in fsl_ifc_ctrl_probe
- Use module_platform_driver() insted of module_init and module_exit
Changes for v3: Incorporated Dmitry Pervushin's comments
- Memory mapped structures should be defined with packet attribute
arch/powerpc/Kconfig | 4 +
arch/powerpc/include/asm/fsl_ifc.h | 834 ++++++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/fsl_ifc.c | 310 +++++++++++++
4 files changed, 1149 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_ifc.h
create mode 100644 arch/powerpc/sysdev/fsl_ifc.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 7c93c7e..d78cb6e 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -688,6 +688,10 @@ config FSL_LBC
controller. Also contains some common code used by
drivers for specific local bus peripherals.
+config FSL_IFC
+ bool
+ depends on FSL_SOC
+
config FSL_GTM
bool
depends on PPC_83xx || QUICC_ENGINE || CPM2
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
new file mode 100644
index 0000000..85472e7
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -0,0 +1,834 @@
+/* Freescale Integrated Flash Controller
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_FSL_IFC_H
+#define __ASM_FSL_IFC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/io.h>
+
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+
+#define FSL_IFC_BANK_COUNT 4
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA 0xFFFF0000
+#define CSPR_BA_SHIFT 16
+#define CSPR_PORT_SIZE 0x00000180
+#define CSPR_PORT_SIZE_SHIFT 7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8 0x00000080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16 0x00000100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32 0x00000180
+/* Write Protect */
+#define CSPR_WP 0x00000040
+#define CSPR_WP_SHIFT 6
+/* Machine Select */
+#define CSPR_MSEL 0x00000006
+#define CSPR_MSEL_SHIFT 1
+/* NOR */
+#define CSPR_MSEL_NOR 0x00000000
+/* NAND */
+#define CSPR_MSEL_NAND 0x00000002
+/* GPCM */
+#define CSPR_MSEL_GPCM 0x00000004
+/* Bank Valid */
+#define CSPR_V 0x00000001
+#define CSPR_V_SHIFT 0
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK 0xFFFF0000
+#define IFC_AMASK_SHIFT 16
+#define IFC_AMASK(n) (IFC_AMASK_MASK << \
+ (__ilog2(n) - IFC_AMASK_SHIFT))
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN 0x80000000
+#define CSOR_NAND_ECC_MODE_MASK 0x30000000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4 0x00000000
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8 0x10000000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN 0x04000000
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK 0x01800000
+#define CSOR_NAND_RAL_SHIFT 20
+#define CSOR_NAND_RAL_1 0x00000000
+#define CSOR_NAND_RAL_2 0x00800000
+#define CSOR_NAND_RAL_3 0x01000000
+#define CSOR_NAND_RAL_4 0x01800000
+/* Page Size 512b, 2k, 4k */
+#define CSOR_NAND_PGS_MASK 0x00180000
+#define CSOR_NAND_PGS_SHIFT 16
+#define CSOR_NAND_PGS_512 0x00000000
+#define CSOR_NAND_PGS_2K 0x00080000
+#define CSOR_NAND_PGS_4K 0x00100000
+/* Spare region Size */
+#define CSOR_NAND_SPRZ_MASK 0x0000E000
+#define CSOR_NAND_SPRZ_SHIFT 13
+#define CSOR_NAND_SPRZ_16 0x00000000
+#define CSOR_NAND_SPRZ_64 0x00002000
+#define CSOR_NAND_SPRZ_128 0x00004000
+#define CSOR_NAND_SPRZ_210 0x00006000
+#define CSOR_NAND_SPRZ_218 0x00008000
+#define CSOR_NAND_SPRZ_224 0x0000A000
+/* Pages Per Block */
+#define CSOR_NAND_PB_MASK 0x00000700
+#define CSOR_NAND_PB_SHIFT 8
+#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NAND_TRHZ_MASK 0x0000001C
+#define CSOR_NAND_TRHZ_SHIFT 2
+#define CSOR_NAND_TRHZ_20 0x00000000
+#define CSOR_NAND_TRHZ_40 0x00000004
+#define CSOR_NAND_TRHZ_60 0x00000008
+#define CSOR_NAND_TRHZ_80 0x0000000C
+#define CSOR_NAND_TRHZ_100 0x00000010
+/* Buffer control disable */
+#define CSOR_NAND_BCTLD 0x00000001
+
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+/* Enable Address shift Mode */
+#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
+/* Page Read Enable from NOR device */
+#define CSOR_NOR_PGRD_EN 0x10000000
+/* AVD Toggle Enable during Burst Program */
+#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
+/* Address Data Multiplexing Shift */
+#define CSOR_NOR_ADM_MASK 0x0003E000
+#define CSOR_NOR_ADM_SHIFT_SHIFT 13
+#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
+/* Type of the NOR device hooked */
+#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
+#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NOR_TRHZ_MASK 0x0000001C
+#define CSOR_NOR_TRHZ_SHIFT 2
+#define CSOR_NOR_TRHZ_20 0x00000000
+#define CSOR_NOR_TRHZ_40 0x00000004
+#define CSOR_NOR_TRHZ_60 0x00000008
+#define CSOR_NOR_TRHZ_80 0x0000000C
+#define CSOR_NOR_TRHZ_100 0x00000010
+/* Buffer control disable */
+#define CSOR_NOR_BCTLD 0x00000001
+
+/*
+ * Chip Select Option Register - GPCM Mode
+ */
+/* GPCM Mode - Normal */
+#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
+/* GPCM Mode - GenericASIC */
+#define CSOR_GPCM_GPMODE_ASIC 0x80000000
+/* Parity Mode odd/even */
+#define CSOR_GPCM_PARITY_EVEN 0x40000000
+/* Parity Checking enable/disable */
+#define CSOR_GPCM_PAR_EN 0x20000000
+/* GPCM Timeout Count */
+#define CSOR_GPCM_GPTO_MASK 0x0F000000
+#define CSOR_GPCM_GPTO_SHIFT 24
+#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
+/* GPCM External Access Termination mode for read access */
+#define CSOR_GPCM_RGETA_EXT 0x00080000
+/* GPCM External Access Termination mode for write access */
+#define CSOR_GPCM_WGETA_EXT 0x00040000
+/* Address Data Multiplexing Shift */
+#define CSOR_GPCM_ADM_MASK 0x0003E000
+#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
+#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
+/* Generic ASIC Parity error indication delay */
+#define CSOR_GPCM_GAPERRD_MASK 0x00000180
+#define CSOR_GPCM_GAPERRD_SHIFT 7
+#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_GPCM_TRHZ_MASK 0x0000001C
+#define CSOR_GPCM_TRHZ_20 0x00000000
+#define CSOR_GPCM_TRHZ_40 0x00000004
+#define CSOR_GPCM_TRHZ_60 0x00000008
+#define CSOR_GPCM_TRHZ_80 0x0000000C
+#define CSOR_GPCM_TRHZ_100 0x00000010
+/* Buffer control disable */
+#define CSOR_GPCM_BCTLD 0x00000001
+
+/*
+ * Ready Busy Status Register (RB_STAT)
+ */
+/* CSn is READY */
+#define IFC_RB_STAT_READY_CS0 0x80000000
+#define IFC_RB_STAT_READY_CS1 0x40000000
+#define IFC_RB_STAT_READY_CS2 0x20000000
+#define IFC_RB_STAT_READY_CS3 0x10000000
+
+/*
+ * General Control Register (GCR)
+ */
+#define IFC_GCR_MASK 0x8000F800
+/* reset all IFC hardware */
+#define IFC_GCR_SOFT_RST_ALL 0x80000000
+/* Turnaroud Time of external buffer */
+#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
+#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
+
+/*
+ * Common Event and Error Status Register (CM_EVTER_STAT)
+ */
+/* Chip select error */
+#define IFC_CM_EVTER_STAT_CSER 0x80000000
+
+/*
+ * Common Event and Error Enable Register (CM_EVTER_EN)
+ */
+/* Chip select error checking enable */
+#define IFC_CM_EVTER_EN_CSEREN 0x80000000
+
+/*
+ * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
+ */
+/* Chip select error interrupt enable */
+#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
+
+/*
+ * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
+ */
+/* transaction type of error Read/Write */
+#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
+#define IFC_CM_ERATTR0_ERAID 0x0FF00000
+#define IFC_CM_ERATTR0_ERAID_SHIFT 20
+#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
+#define IFC_CM_ERATTR0_ESRCID_SHIFT 8
+
+/*
+ * Clock Control Register (CCR)
+ */
+#define IFC_CCR_MASK 0x0F0F8800
+/* Clock division ratio */
+#define IFC_CCR_CLK_DIV_MASK 0x0F000000
+#define IFC_CCR_CLK_DIV_SHIFT 24
+#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
+/* IFC Clock Delay */
+#define IFC_CCR_CLK_DLY_MASK 0x000F0000
+#define IFC_CCR_CLK_DLY_SHIFT 16
+#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
+/* Invert IFC clock before sending out */
+#define IFC_CCR_INV_CLK_EN 0x00008000
+/* Fedback IFC Clock */
+#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
+
+/*
+ * Clock Status Register (CSR)
+ */
+/* Clk is stable */
+#define IFC_CSR_CLK_STAT_STABLE 0x80000000
+
+/*
+ * IFC_NAND Machine Specific Registers
+ */
+/*
+ * NAND Configuration Register (NCFGR)
+ */
+/* Auto Boot Mode */
+#define IFC_NAND_NCFGR_BOOT 0x80000000
+/* Addressing Mode-ROW0+n/COL0 */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
+/* Addressing Mode-ROW0+n/COL0+n */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
+/* Number of loop iterations of FIR sequences for multi page operations */
+#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
+#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
+#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
+/* Number of wait cycles */
+#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
+#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
+
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0 0xFF000000
+#define IFC_NAND_FCR0_CMD0_SHIFT 24
+#define IFC_NAND_FCR0_CMD1 0x00FF0000
+#define IFC_NAND_FCR0_CMD1_SHIFT 16
+#define IFC_NAND_FCR0_CMD2 0x0000FF00
+#define IFC_NAND_FCR0_CMD2_SHIFT 8
+#define IFC_NAND_FCR0_CMD3 0x000000FF
+#define IFC_NAND_FCR0_CMD3_SHIFT 0
+#define IFC_NAND_FCR1_CMD4 0xFF000000
+#define IFC_NAND_FCR1_CMD4_SHIFT 24
+#define IFC_NAND_FCR1_CMD5 0x00FF0000
+#define IFC_NAND_FCR1_CMD5_SHIFT 16
+#define IFC_NAND_FCR1_CMD6 0x0000FF00
+#define IFC_NAND_FCR1_CMD6_SHIFT 8
+#define IFC_NAND_FCR1_CMD7 0x000000FF
+#define IFC_NAND_FCR1_CMD7_SHIFT 0
+
+/*
+ * Flash ROW and COL Address Register (ROWn, COLn)
+ */
+/* Main/spare region locator */
+#define IFC_NAND_COL_MS 0x80000000
+/* Column Address */
+#define IFC_NAND_COL_CA_MASK 0x00000FFF
+
+/*
+ * NAND Flash Byte Count Register (NAND_BC)
+ */
+/* Byte Count for read/Write */
+#define IFC_NAND_BC 0x000001FF
+
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0 0xFC000000
+#define IFC_NAND_FIR0_OP0_SHIFT 26
+#define IFC_NAND_FIR0_OP1 0x03F00000
+#define IFC_NAND_FIR0_OP1_SHIFT 20
+#define IFC_NAND_FIR0_OP2 0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT 14
+#define IFC_NAND_FIR0_OP3 0x00003F00
+#define IFC_NAND_FIR0_OP3_SHIFT 8
+#define IFC_NAND_FIR0_OP4 0x000000FC
+#define IFC_NAND_FIR0_OP4_SHIFT 2
+#define IFC_NAND_FIR1_OP5 0xFC000000
+#define IFC_NAND_FIR1_OP5_SHIFT 26
+#define IFC_NAND_FIR1_OP6 0x03F00000
+#define IFC_NAND_FIR1_OP6_SHIFT 20
+#define IFC_NAND_FIR1_OP7 0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT 14
+#define IFC_NAND_FIR1_OP8 0x00003F00
+#define IFC_NAND_FIR1_OP8_SHIFT 8
+#define IFC_NAND_FIR1_OP9 0x000000FC
+#define IFC_NAND_FIR1_OP9_SHIFT 2
+#define IFC_NAND_FIR2_OP10 0xFC000000
+#define IFC_NAND_FIR2_OP10_SHIFT 26
+#define IFC_NAND_FIR2_OP11 0x03F00000
+#define IFC_NAND_FIR2_OP11_SHIFT 20
+#define IFC_NAND_FIR2_OP12 0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT 14
+#define IFC_NAND_FIR2_OP13 0x00003F00
+#define IFC_NAND_FIR2_OP13_SHIFT 8
+#define IFC_NAND_FIR2_OP14 0x000000FC
+#define IFC_NAND_FIR2_OP14_SHIFT 2
+
+/*
+ * Instruction opcodes to be programmed
+ * in FIR registers- 6bits
+ */
+enum ifc_nand_fir_opcodes {
+ IFC_FIR_OP_NOP,
+ IFC_FIR_OP_CA0,
+ IFC_FIR_OP_CA1,
+ IFC_FIR_OP_CA2,
+ IFC_FIR_OP_CA3,
+ IFC_FIR_OP_RA0,
+ IFC_FIR_OP_RA1,
+ IFC_FIR_OP_RA2,
+ IFC_FIR_OP_RA3,
+ IFC_FIR_OP_CMD0,
+ IFC_FIR_OP_CMD1,
+ IFC_FIR_OP_CMD2,
+ IFC_FIR_OP_CMD3,
+ IFC_FIR_OP_CMD4,
+ IFC_FIR_OP_CMD5,
+ IFC_FIR_OP_CMD6,
+ IFC_FIR_OP_CMD7,
+ IFC_FIR_OP_CW0,
+ IFC_FIR_OP_CW1,
+ IFC_FIR_OP_CW2,
+ IFC_FIR_OP_CW3,
+ IFC_FIR_OP_CW4,
+ IFC_FIR_OP_CW5,
+ IFC_FIR_OP_CW6,
+ IFC_FIR_OP_CW7,
+ IFC_FIR_OP_WBCD,
+ IFC_FIR_OP_RBCD,
+ IFC_FIR_OP_BTRD,
+ IFC_FIR_OP_RDSTAT,
+ IFC_FIR_OP_NWAIT,
+ IFC_FIR_OP_WFR,
+ IFC_FIR_OP_SBRD,
+ IFC_FIR_OP_UA,
+ IFC_FIR_OP_RB,
+};
+
+/*
+ * NAND Chip Select Register (NAND_CSEL)
+ */
+#define IFC_NAND_CSEL 0x0C000000
+#define IFC_NAND_CSEL_SHIFT 26
+#define IFC_NAND_CSEL_CS0 0x00000000
+#define IFC_NAND_CSEL_CS1 0x04000000
+#define IFC_NAND_CSEL_CS2 0x08000000
+#define IFC_NAND_CSEL_CS3 0x0C000000
+
+/*
+ * NAND Operation Sequence Start (NANDSEQ_STRT)
+ */
+/* NAND Flash Operation Start */
+#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
+/* Automatic Erase */
+#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
+/* Automatic Program */
+#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
+/* Automatic Copyback */
+#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
+/* Automatic Read Operation */
+#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
+/* Automatic Status Read */
+#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
+
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC 0x80000000
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER 0x04000000
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
+/* RCW Load Done */
+#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
+/* Boot Loadr Done */
+#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
+/* Bad Block Indicator search select */
+#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
+
+/*
+ * NAND Flash Page Read Completion Event Status Register
+ * (PGRDCMPL_EVT_STAT)
+ */
+#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
+/* Small Page 0-15 Done */
+#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
+/* Large Page(2K) 0-3 Done */
+#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
+/* Large Page(4K) 0-1 Done */
+#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
+
+/*
+ * NAND Event and Error Enable Register (NAND_EVTER_EN)
+ */
+/* Operation complete event enable */
+#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
+/* Page read complete event enable */
+#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
+/* Flash Timeout error enable */
+#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
+/* Write Protect error enable */
+#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
+/* ECC error logging enable */
+#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
+
+/*
+ * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
+ */
+/* Enable interrupt for operation complete */
+#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
+/* Enable interrupt for Page read complete */
+#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
+/* Enable interrupt for Flash timeout error */
+#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
+/* Enable interrupt for Write protect error */
+#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
+/* Enable interrupt for ECC error*/
+#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
+
+/*
+ * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
+ */
+#define IFC_NAND_ERATTR0_MASK 0x0C080000
+/* Error on CS0-3 for NAND */
+#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
+#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
+#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
+#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
+/* Transaction type of error Read/Write */
+#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
+
+/*
+ * NAND Flash Status Register (NAND_FSR)
+ */
+/* First byte of data read from read status op */
+#define IFC_NAND_NFSR_RS0 0xFF000000
+/* Second byte of data read from read status op */
+#define IFC_NAND_NFSR_RS1 0x00FF0000
+
+/*
+ * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
+ */
+/* Number of ECC errors on sector n (n = 0-15) */
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
+
+/*
+ * NAND Control Register (NANDCR)
+ */
+#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
+#define IFC_NAND_NCR_FTOCNT_SHIFT 25
+#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
+
+/*
+ * NAND_AUTOBOOT_TRGR
+ */
+/* Trigger RCW load */
+#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
+/* Trigget Auto Boot */
+#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
+
+/*
+ * NAND_MDR
+ */
+/* 1st read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA0 0xFF000000
+/* 2nd read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA1 0x00FF0000
+
+/*
+ * NOR Machine Specific Registers
+ */
+/*
+ * NOR Event and Error Status Register (NOR_EVTER_STAT)
+ */
+/* NOR Command Sequence Operation Complete */
+#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
+/* Write Protect Error */
+#define IFC_NOR_EVTER_STAT_WPER 0x04000000
+/* Command Sequence Timeout Error */
+#define IFC_NOR_EVTER_STAT_STOER 0x01000000
+
+/*
+ * NOR Event and Error Enable Register (NOR_EVTER_EN)
+ */
+/* NOR Command Seq complete event enable */
+#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
+/* Write Protect Error Checking Enable */
+#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
+/* Timeout Error Enable */
+#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
+
+/*
+ * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
+ */
+/* Enable interrupt for OPC complete */
+#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
+/* Enable interrupt for write protect error */
+#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
+/* Enable interrupt for timeout error */
+#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
+
+/*
+ * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
+/* AXI ID for error transation */
+#define IFC_NOR_ERATTR0_ERAID 0x000FF000
+/* Chip select corresponds to NOR error */
+#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
+#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
+#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
+#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
+/* Type of transaction read/write */
+#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
+
+/*
+ * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
+ */
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
+
+/*
+ * NOR Control Register (NORCR)
+ */
+#define IFC_NORCR_MASK 0x0F0F0000
+/* No. of Address/Data Phase */
+#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
+#define IFC_NORCR_NUM_PHASE_SHIFT 24
+#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
+/* Sequence Timeout Count */
+#define IFC_NORCR_STOCNT_MASK 0x000F0000
+#define IFC_NORCR_STOCNT_SHIFT 16
+#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
+
+/*
+ * GPCM Machine specific registers
+ */
+/*
+ * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
+ */
+/* Timeout error */
+#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
+/* Parity error */
+#define IFC_GPCM_EVTER_STAT_PER 0x01000000
+
+/*
+ * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
+ */
+/* Timeout error enable */
+#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
+/* Parity error enable */
+#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
+
+/*
+ * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
+ */
+/* Enable Interrupt for timeout error */
+#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
+/* Enable Interrupt for Parity error */
+#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
+
+/*
+ * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
+/* AXI ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
+/* Chip select corresponds to GPCM error */
+#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
+#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
+#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
+#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
+/* Type of transaction read/Write */
+#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
+
+/*
+ * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
+ */
+/* On which beat of address/data parity error is observed */
+#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
+/* Parity Error on byte */
+#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
+/* Parity Error reported in addr or data phase */
+#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
+
+/*
+ * GPCM Status Register (GPCM_STAT)
+ */
+#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
+
+/*
+ * IFC Controller NAND Machine registers
+ */
+struct fsl_ifc_nand {
+ __be32 ncfgr;
+ u32 res1[0x4];
+ __be32 nand_fcr0;
+ __be32 nand_fcr1;
+ u32 res2[0x8];
+ __be32 row0;
+ u32 res3;
+ __be32 col0;
+ u32 res4;
+ __be32 row1;
+ u32 res5;
+ __be32 col1;
+ u32 res6;
+ __be32 row2;
+ u32 res7;
+ __be32 col2;
+ u32 res8;
+ __be32 row3;
+ u32 res9;
+ __be32 col3;
+ u32 res10[0x24];
+ __be32 nand_fbcr;
+ u32 res11;
+ __be32 nand_fir0;
+ __be32 nand_fir1;
+ __be32 nand_fir2;
+ u32 res12[0x10];
+ __be32 nand_csel;
+ u32 res13;
+ __be32 nandseq_strt;
+ u32 res14;
+ __be32 nand_evter_stat;
+ u32 res15;
+ __be32 pgrdcmpl_evt_stat;
+ u32 res16[0x2];
+ __be32 nand_evter_en;
+ u32 res17[0x2];
+ __be32 nand_evter_intr_en;
+ u32 res18[0x2];
+ __be32 nand_erattr0;
+ __be32 nand_erattr1;
+ u32 res19[0x10];
+ __be32 nand_fsr;
+ u32 res20;
+ __be32 nand_eccstat[4];
+ u32 res21[0x20];
+ __be32 nanndcr;
+ u32 res22[0x2];
+ __be32 nand_autoboot_trgr;
+ u32 res23;
+ __be32 nand_mdr;
+ u32 res24[0x5C];
+} __packed;
+
+/*
+ * IFC controller NOR Machine registers
+ */
+struct fsl_ifc_nor {
+ __be32 nor_evter_stat;
+ u32 res1[0x2];
+ __be32 nor_evter_en;
+ u32 res2[0x2];
+ __be32 nor_evter_intr_en;
+ u32 res3[0x2];
+ __be32 nor_erattr0;
+ __be32 nor_erattr1;
+ __be32 nor_erattr2;
+ u32 res4[0x4];
+ __be32 norcr;
+ u32 res5[0xEF];
+} __packed;
+
+/*
+ * IFC controller GPCM Machine registers
+ */
+struct fsl_ifc_gpcm {
+ __be32 gpcm_evter_stat;
+ u32 res1[0x2];
+ __be32 gpcm_evter_en;
+ u32 res2[0x2];
+ __be32 gpcm_evter_intr_en;
+ u32 res3[0x2];
+ __be32 gpcm_erattr0;
+ __be32 gpcm_erattr1;
+ __be32 gpcm_erattr2;
+ __be32 gpcm_stat;
+ u32 res4[0x1F3];
+} __packed;
+
+/*
+ * IFC Controller Registers
+ */
+struct fsl_ifc_regs {
+ __be32 ifc_rev;
+ u32 res1[0x3];
+ struct {
+ __be32 cspr;
+ u32 res2[0x2];
+ } cspr_cs[FSL_IFC_BANK_COUNT];
+ u32 res3[0x18];
+ struct {
+ __be32 amask;
+ u32 res4[0x2];
+ } amask_cs[FSL_IFC_BANK_COUNT];
+ u32 res5[0x18];
+ struct {
+ __be32 csor;
+ u32 res6[0x2];
+ } csor_cs[FSL_IFC_BANK_COUNT];
+ u32 res7[0x18];
+ struct {
+ __be32 ftim[4];
+ u32 res8[0x8];
+ } ftim_cs[FSL_IFC_BANK_COUNT];
+ u32 res9[0x60];
+ __be32 rb_stat;
+ u32 res10[0x2];
+ __be32 ifc_gcr;
+ u32 res11[0x2];
+ __be32 cm_evter_stat;
+ u32 res12[0x2];
+ __be32 cm_evter_en;
+ u32 res13[0x2];
+ __be32 cm_evter_intr_en;
+ u32 res14[0x2];
+ __be32 cm_erattr0;
+ __be32 cm_erattr1;
+ u32 res15[0x2];
+ __be32 ifc_ccr;
+ __be32 ifc_csr;
+ u32 res16[0x2EB];
+ struct fsl_ifc_nand ifc_nand;
+ struct fsl_ifc_nor ifc_nor;
+ struct fsl_ifc_gpcm ifc_gpcm;
+} __packed;
+
+extern unsigned int convert_ifc_address(phys_addr_t addr_base);
+extern int fsl_ifc_find(phys_addr_t addr_base);
+
+/* overview of the fsl ifc controller */
+
+struct fsl_ifc_ctrl {
+ /* device info */
+ struct device *dev;
+ struct fsl_ifc_regs __iomem *regs;
+ int irq;
+ int nand_irq;
+ spinlock_t lock;
+ void *nand;
+
+ u32 nand_stat;
+ wait_queue_head_t nand_wait;
+};
+
+extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+
+
+#endif /* __ASM_FSL_IFC_H */
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 8dea593..5e37b47 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o $(fsl-msi-obj-y)
obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
+obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
diff --git a/arch/powerpc/sysdev/fsl_ifc.c b/arch/powerpc/sysdev/fsl_ifc.c
new file mode 100644
index 0000000..b31f19f
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_ifc.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc
+ *
+ * Freescale Integrated Flash Controller
+ *
+ * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <asm/prom.h>
+#include <asm/fsl_ifc.h>
+
+struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
+
+/*
+ * convert_ifc_address - convert the base address
+ * @addr_base: base address of the memory bank
+ */
+unsigned int convert_ifc_address(phys_addr_t addr_base)
+{
+ return addr_base & CSPR_BA;
+}
+EXPORT_SYMBOL(convert_ifc_address);
+
+/*
+ * fsl_ifc_find - find IFC bank
+ * @addr_base: base address of the memory bank
+ *
+ * This function walks IFC banks comparing "Base address" field of the CSPR
+ * registers with the supplied addr_base argument. When bases match this
+ * function returns bank number (starting with 0), otherwise it returns
+ * appropriate errno value.
+ */
+int fsl_ifc_find(phys_addr_t addr_base)
+{
+ int i = 0;
+
+ if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
+ return -ENODEV;
+
+ for (i = 0; i < ARRAY_SIZE(fsl_ifc_ctrl_dev->regs->cspr_cs); i++) {
+ __be32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
+ if (cspr & CSPR_V && (cspr & CSPR_BA) ==
+ convert_ifc_address(addr_base))
+ return i;
+ }
+
+ return -ENOENT;
+}
+EXPORT_SYMBOL(fsl_ifc_find);
+
+static int __devinit fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
+{
+ struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+
+ /*
+ * Clear all the common status and event registers
+ */
+ if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
+ out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
+
+ /* enable all error and events */
+ out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN);
+
+ /* enable all error and event interrupts */
+ out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN);
+ out_be32(&ifc->cm_erattr0, 0x0);
+ out_be32(&ifc->cm_erattr1, 0x0);
+
+ return 0;
+}
+
+static int fsl_ifc_ctrl_remove(struct platform_device *dev)
+{
+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
+
+ free_irq(ctrl->nand_irq, ctrl);
+ free_irq(ctrl->irq, ctrl);
+
+ irq_dispose_mapping(ctrl->nand_irq);
+ irq_dispose_mapping(ctrl->irq);
+
+ iounmap(ctrl->regs);
+
+ dev_set_drvdata(&dev->dev, NULL);
+ kfree(ctrl);
+
+ return 0;
+}
+
+/*
+ * NAND events are split between an operational interrupt which only
+ * receives OPC, and an error interrupt that receives everything else,
+ * including non-NAND errors. Whichever interrupt gets to it first
+ * records the status and wakes the wait queue.
+ */
+static DEFINE_SPINLOCK(nand_irq_lock);
+
+static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
+{
+ struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+ unsigned long flags;
+ u32 stat;
+
+ spin_lock_irqsave(&nand_irq_lock, flags);
+
+ stat = in_be32(&ifc->ifc_nand.nand_evter_stat);
+ if (stat) {
+ out_be32(&ifc->ifc_nand.nand_evter_stat, stat);
+ ctrl->nand_stat = stat;
+ wake_up(&ctrl->nand_wait);
+ }
+
+ spin_unlock_irqrestore(&nand_irq_lock, flags);
+
+ return stat;
+}
+
+static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
+{
+ struct fsl_ifc_ctrl *ctrl = data;
+
+ if (check_nand_stat(ctrl))
+ return IRQ_HANDLED;
+
+ return IRQ_NONE;
+}
+
+/*
+ * NOTE: This interrupt is used to report ifc events of various kinds,
+ * such as transaction errors on the chipselects.
+ */
+static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
+{
+ struct fsl_ifc_ctrl *ctrl = data;
+ struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+ u32 err_axiid, err_srcid, status, cs_err, err_addr;
+ irqreturn_t ret = IRQ_NONE;
+
+ /* read for chip select error */
+ cs_err = in_be32(&ifc->cm_evter_stat);
+ if (cs_err) {
+ dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
+ "any memory bank 0x%08X\n", cs_err);
+ /* clear the chip select error */
+ out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER);
+
+ /* read error attribute registers print the error information */
+ status = in_be32(&ifc->cm_erattr0);
+ err_addr = in_be32(&ifc->cm_erattr1);
+
+ if (status & IFC_CM_ERATTR0_ERTYP_READ)
+ dev_err(ctrl->dev, "Read transaction error"
+ "CM_ERATTR0 0x%08X\n", status);
+ else
+ dev_err(ctrl->dev, "Write transaction error"
+ "CM_ERATTR0 0x%08X\n", status);
+
+ err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
+ IFC_CM_ERATTR0_ERAID_SHIFT;
+ dev_err(ctrl->dev, "AXI ID of the error"
+ "transaction 0x%08X\n", err_axiid);
+
+ err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
+ IFC_CM_ERATTR0_ESRCID_SHIFT;
+ dev_err(ctrl->dev, "SRC ID of the error"
+ "transaction 0x%08X\n", err_srcid);
+
+ dev_err(ctrl->dev, "Transaction Address corresponding to error"
+ "ERADDR 0x%08X\n", err_addr);
+
+ ret = IRQ_HANDLED;
+ }
+
+ if (check_nand_stat(ctrl))
+ ret = IRQ_HANDLED;
+
+ return ret;
+}
+
+/*
+ * fsl_ifc_ctrl_probe
+ *
+ * called by device layer when it finds a device matching
+ * one our driver can handled. This code allocates all of
+ * the resources needed for the controller only. The
+ * resources for the NAND banks themselves are allocated
+ * in the chip probe function.
+*/
+static int __devinit fsl_ifc_ctrl_probe(struct platform_device *dev)
+{
+ int ret = 0;
+
+
+ dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
+
+ fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
+ if (!fsl_ifc_ctrl_dev)
+ return -ENOMEM;
+
+ dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
+
+ /* IOMAP the entire IFC region */
+ fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
+ if (!fsl_ifc_ctrl_dev->regs) {
+ dev_err(&dev->dev, "failed to get memory region\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ /* get the Controller level irq */
+ fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
+ if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
+ dev_err(&dev->dev, "failed to get irq resource "
+ "for IFC\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ /* get the nand machine irq */
+ fsl_ifc_ctrl_dev->nand_irq =
+ irq_of_parse_and_map(dev->dev.of_node, 1);
+ if (fsl_ifc_ctrl_dev->nand_irq == NO_IRQ) {
+ dev_err(&dev->dev, "failed to get irq resource "
+ "for NAND Machine\n");
+ ret = -ENODEV;
+ goto err;
+ }
+
+ fsl_ifc_ctrl_dev->dev = &dev->dev;
+
+ ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
+ if (ret < 0)
+ goto err;
+
+ init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
+
+ ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
+ "fsl-ifc", fsl_ifc_ctrl_dev);
+ if (ret != 0) {
+ dev_err(&dev->dev, "failed to install irq (%d)\n",
+ fsl_ifc_ctrl_dev->irq);
+ goto err_irq;
+ }
+
+ ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq, 0,
+ "fsl-ifc-nand", fsl_ifc_ctrl_dev);
+ if (ret != 0) {
+ dev_err(&dev->dev, "failed to install irq (%d)\n",
+ fsl_ifc_ctrl_dev->nand_irq);
+ goto err_nandirq;
+ }
+
+ return 0;
+
+err_nandirq:
+ free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
+ irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
+err_irq:
+ free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
+ irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
+err:
+ return ret;
+}
+
+static const struct of_device_id fsl_ifc_match[] = {
+ {
+ .compatible = "fsl,ifc",
+ },
+ {},
+};
+
+static struct platform_driver fsl_ifc_ctrl_driver = {
+ .driver = {
+ .name = "fsl-ifc",
+ .of_match_table = fsl_ifc_match,
+ },
+ .probe = fsl_ifc_ctrl_probe,
+ .remove = fsl_ifc_ctrl_remove,
+};
+
+module_platform_driver(fsl_ifc_ctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
--
1.7.5.4
^ permalink raw reply related
* RE: [PATCH] mmc:sdhci: restore the enabled dma when do reset all
From: Xie Shaohui-B21989 @ 2011-12-29 9:05 UTC (permalink / raw)
To: Adrian Hunter; +Cc: linuxppc-dev@lists.ozlabs.org, linux-mmc@vger.kernel.org
In-Reply-To: <4EFB00AC.5070209@intel.com>
>-----Original Message-----
>From: Adrian Hunter [mailto:adrian.hunter@intel.com]
>Sent: Wednesday, December 28, 2011 7:43 PM
>To: Xie Shaohui-B21989
>Cc: linux-mmc@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
>Subject: Re: [PATCH] mmc:sdhci: restore the enabled dma when do reset all
>
>On 28/12/11 11:41, Shaohui Xie wrote:
>> If dma is enabled, it'll be cleared when reset all is performed, this
>> can be observed on some platforms, such as P2041 which has a version
>> 2.3 controller, but platform like P4080 which has a version 2.2
>> controller, does not suffer this, so we will check if the dma is
>> enabled, we should restore it after reset all.
>>
>> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
>> ---
>> based on http://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git,
>> branch 'for-linus'.
>>
>> drivers/mmc/host/sdhci.c | 7 +++++++
>> 1 files changed, 7 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index
>> 19ed580..22033c3 100644
>> --- a/drivers/mmc/host/sdhci.c
>> +++ b/drivers/mmc/host/sdhci.c
>> @@ -29,6 +29,7 @@
>> #include <linux/mmc/host.h>
>>
>> #include "sdhci.h"
>> +#include "sdhci-esdhc.h"
>>
>> #define DRIVER_NAME "sdhci"
>>
>> @@ -176,6 +177,7 @@ static void sdhci_reset(struct sdhci_host *host,
>> u8 mask) {
>> unsigned long timeout;
>> u32 uninitialized_var(ier);
>> + u32 uninitialized_var(dma);
>>
>> if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
>> if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & @@ -189,6
>+191,8 @@
>> static void sdhci_reset(struct sdhci_host *host, u8 mask)
>> if (host->ops->platform_reset_enter)
>> host->ops->platform_reset_enter(host, mask);
>>
>> + dma =3D sdhci_readl(host, ESDHC_DMA_SYSCTL);
>
>
>You must not access eSDHC-specific registers in generic SDHCI code
[Xie Shaohui] OK. Thank you, I'll call the wrapper API here.
Best Regards,=20
Shaohui Xie
^ permalink raw reply
* [PATCH][v2] mmc:sdhci: restore the enabled dma when do reset all
From: Shaohui Xie @ 2011-12-29 8:33 UTC (permalink / raw)
To: linux-mmc; +Cc: linuxppc-dev, Shaohui Xie
If dma is enabled, it'll be cleared when reset all is performed, this can
be observed on some platforms, such as P2041 which has a version 2.3
controller, but platform like P4080 which has a version 2.2 controller,
does not suffer this, so we will check if the dma is enabled, we should
restore it after reset all.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
based on http://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git,
branch 'for-linus'.
changes for v2:
call the wrapper API instead of access the register directly.
drivers/mmc/host/sdhci.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 19ed580..cf6a048 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -214,6 +214,11 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
+
+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
+ host->ops->enable_dma(host);
+ }
}
static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
--
1.6.4
^ permalink raw reply related
* Mac address in the DTS file
From: smitha.vanga @ 2011-12-30 12:51 UTC (permalink / raw)
To: scottwood; +Cc: linuxppc-dev
In-Reply-To: <4E57FD3D.6090809@freescale.com>
Hi Scott,
In my DTS file for mpc8247 I have defined the ether MAC in the node as below=
.
ethernet@24000 {
#address-cells =3D <1>;
#size-cells =3D <0>;
device_type =3D "network";
device-id =3D <1>;
compatible =3D "fs_enet";
model =3D "FCC";
reg =3D <11300 20 8400 100 11380 30>;
mac-address =3D [ 00 e0 ee 00 05 2e ];
interrupts =3D <20 2>;
interrupt-parent =3D <10c00>;
phy-handle =3D <2452000>;
rx-clock =3D <13>;
tx-clock =3D <12>;
};
The driver is working and everything is fine. But as I defined the mac-addre=
ss as 00:e0:ee:00:05:2e
Its constant. Am not able to change this mac -address in linux once the targ=
et is up with LINUX.
How do I change the MAC address. If different targets boards are connected o=
n the network then every board will have the same MAC address as the .dtb f=
ile is the same. How to go about this problem?
It would be a great help if you answer soon.
Regards,
Smitha
Please do not print this email unless it is absolutely necessary. =0A=
=0A=
The information contained in this electronic message and any attachments to=
this message are intended for the exclusive use of the addressee(s) and may=
contain proprietary, confidential or privileged information. If you are not=
the intended recipient, you should not disseminate, distribute or copy this=
e-mail. Please notify the sender immediately and destroy all copies of this=
message and any attachments. =0A=
=0A=
WARNING: Computer viruses can be transmitted via email. The recipient should=
check this email and any attachments for the presence of viruses. The compa=
ny accepts no liability for any damage caused by any virus transmitted by th=
is email. =0A=
=0A=
www.wipro.com
^ permalink raw reply
* Re: Mac address in the DTS file
From: Lorenz Kolb @ 2011-12-30 14:00 UTC (permalink / raw)
To: smitha.vanga; +Cc: scottwood, linuxppc-dev
In-Reply-To: <40631E9A2581F14BA60888C87A76A1FE01C6BB@HYD-MKD-MBX4.wipro.com>
Hi Smitha,
actually it should work as normal
On 12/30/2011 1:51 PM, smitha.vanga@wipro.com wrote:
> Its constant. Am not able to change this mac -address in linux once the target is up with LINUX.
> How do I change the MAC address.
actually it should work as normal:
ifconfig ethX down
ifconfig ethX hw ether 00:11:22:33:44:55
ifconfig ethX up
> If different targets boards are connected on the network then every board will have the same MAC address as the .dtb file is the same. How to go about this problem?
Depends on your setup: normally the real MAC is stored on some onboard
configuration space (eeprom or flash).
Afterwards there are multiple ways you could work aroun the problem:
most elegant: make your bootloader replace the fake MAC with the real
one within the dtb.
Most simple one: have a startup script that reads the real MAC and does
the ifconfig magic.
Regards,
Lorenz
^ permalink raw reply
* [PATCH 82/94] USB: ehci-fsl: Fix 'have_sysif_regs' detection
From: Jason Jin @ 2011-12-30 16:51 UTC (permalink / raw)
To: tiejun.chen, kexin.hao, Bo.Liu
Cc: b14898, David Brownell, Pan Jiafei, Anatolij Gustschin,
linuxppc-dev, b37022
In-Reply-To: <1325263910-14057-1-git-send-email-Jason.jin@freescale.com>
From: Pan Jiafei <Jiafei.Pan@freescale.com>
extract from vendor drop QorIQ-DPAA-SDK-20111026-systembuilder.iso
Previously a check was done on an ID register at the base of a CPU's
internal USB registers to determine if system interface regsiters were
present. The check looked for an ID register that had the format
ID[0:5] == ~ID[8:13] as described in the MPC5121 User's Manual to
determine if a MPC5121 or MPC83xx/85xx was being used.
There are two issues with this method:
- The ID register is not defined on the MPC83xx/85xx CPUs, so its
unclear what is being checked on them.
- Newer CPUs such as the P4080 also don't document the ID register, but
do share the same format as the MPC5121. Thus the previous code did
not set 'have_sysif_regs' properly which results in the P4080 not
properly initializing its USB ports.
Using the device tree 'compatible' node is a cleaner way to determine if
'have_sysif_regs' should be set and resolves the USB initialization issue
seen on the P4080.
Tested on a P4080-based system and compile tested on mpc512x_defconfig
with Freescale EHCI driver enabled.
Cc: Anatolij Gustschin <agust@denx.de>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Integrated-by: Pan Jiafei <Jiafei.Pan@freescale.com>
---
drivers/usb/host/ehci-fsl.c | 13 -------------
drivers/usb/host/ehci-fsl.h | 3 ---
drivers/usb/host/fsl-mph-dr-of.c | 11 ++++++++---
3 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index ac5f38d..22baaec 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -52,7 +52,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
struct resource *res;
int irq;
int retval;
- unsigned int temp;
pr_debug("initializing FSL-SOC USB Controller\n");
@@ -126,18 +125,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
goto err3;
}
- /*
- * Check if it is MPC5121 SoC, otherwise set pdata->have_sysif_regs
- * flag for 83xx or 8536 system interface registers.
- */
- if (pdata->big_endian_mmio)
- temp = in_be32(hcd->regs + FSL_SOC_USB_ID);
- else
- temp = in_le32(hcd->regs + FSL_SOC_USB_ID);
-
- if ((temp & ID_MSK) != (~((temp & NID_MSK) >> 8) & ID_MSK))
- pdata->have_sysif_regs = 1;
-
/* Enable USB controller, 83xx or 8536 */
if (pdata->have_sysif_regs)
setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 2c83537..3fabed3 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -19,9 +19,6 @@
#define _EHCI_FSL_H
/* offsets for the non-ehci registers in the FSL SOC USB controller */
-#define FSL_SOC_USB_ID 0x0
-#define ID_MSK 0x3f
-#define NID_MSK 0x3f00
#define FSL_SOC_USB_ULPIVP 0x170
#define FSL_SOC_USB_PORTSC1 0x184
#define PORT_PTS_MSK (3<<30)
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 574b99e..79a66d6 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -262,19 +262,24 @@ static void fsl_usb2_mpc5121_exit(struct platform_device *pdev)
}
}
-struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
+static struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
.big_endian_desc = 1,
.big_endian_mmio = 1,
.es = 1,
+ .have_sysif_regs = 0,
.le_setup_buf = 1,
.init = fsl_usb2_mpc5121_init,
.exit = fsl_usb2_mpc5121_exit,
};
#endif /* CONFIG_PPC_MPC512x */
+static struct fsl_usb2_platform_data fsl_usb2_mpc8xxx_pd = {
+ .have_sysif_regs = 1,
+};
+
static const struct of_device_id fsl_usb2_mph_dr_of_match[] = {
- { .compatible = "fsl-usb2-mph", },
- { .compatible = "fsl-usb2-dr", },
+ { .compatible = "fsl-usb2-mph", .data = &fsl_usb2_mpc8xxx_pd, },
+ { .compatible = "fsl-usb2-dr", .data = &fsl_usb2_mpc8xxx_pd, },
#ifdef CONFIG_PPC_MPC512x
{ .compatible = "fsl,mpc5121-usb2-dr", .data = &fsl_usb2_mpc5121_pd, },
#endif
--
1.7.5.1
^ permalink raw reply related
* Re: Mac address in the DTS file
From: Wolfgang Denk @ 2011-12-30 18:28 UTC (permalink / raw)
To: smitha.vanga; +Cc: scottwood, linuxppc-dev
In-Reply-To: <40631E9A2581F14BA60888C87A76A1FE01C6BB@HYD-MKD-MBX4.wipro.com>
Dear smitha.vanga@wipro.com,
In message <40631E9A2581F14BA60888C87A76A1FE01C6BB@HYD-MKD-MBX4.wipro.com> you wrote:
>
> In my DTS file for mpc8247 I have defined the ether MAC in the node as below.
On a MPC82xx there is a chance that you are using U-Boot as boot
loader...
> How do I change the MAC address. If different targets boards are
U-Boot can store (it the environment variables) MAC addresses and
update the DT with this information.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"Beware of bugs in the above code; I have only proved it correct, not
tried it." - Donald Knuth
^ permalink raw reply
* Re: [PATCH 4/5] KVM: PPC: Book3s HV: Implement get_dirty_log using hardware changed bit
From: Paul Mackerras @ 2011-12-31 0:44 UTC (permalink / raw)
To: Takuya Yoshikawa
Cc: linuxppc-dev, Takuya Yoshikawa, Alexander Graf, kvm-ppc, KVM list
In-Reply-To: <4EF80090.7050008@oss.ntt.co.jp>
On Mon, Dec 26, 2011 at 02:05:20PM +0900, Takuya Yoshikawa wrote:
> From my x86 dirty logging experience I have some concern about your code:
> your code looks slow even when there is no/few dirty pages in the slot.
>
> + for (i = 0; i < memslot->npages; ++i) {
> + if (kvm_test_clear_dirty(kvm, rmapp))
> + __set_bit_le(i, map);
> + ++rmapp;
> + }
>
> The check is being done for each page and this can be very expensive because
> the number of pages is not small.
>
> When we scan the dirty_bitmap 64 pages are checked at once and
> the problem is not so significant.
>
> Though I do not know well what kvm-ppc's dirty logging is aiming at, I guess
> reporting cleanliness without noticeable delay to the user-space is important.
>
> E.g. for VGA most of the cases are clean. For live migration, the
> chance of seeing complete clean slot is small but almost all cases
> are sparse.
The alternative approach is not to use the hardware changed bit but
instead to install read-only HPTEs when the guest requests a
read/write mapping, and then when the guest writes to the page we
intercept the protection fault, mark the page dirty and change the
HPTE to allow writing. Then when harvesting the dirty bits we have to
change any dirty page back to a read-only HPTE.
That is all quite doable, but I was worried about the performance
impact of the extra faults. We intend to do some performance studies
to see whether the alternative approach would give better performance.
There is a trade-off in that the alternative approach would slow down
normal operation a little in order to speed up the harvesting of the
dirty log. That may in fact be worthwhile.
For now, the patch I posted at least gets the dirty page tracking
working, so we can use VGA emulation.
Paul.
^ permalink raw reply
* Ask a technical problem happened on PPC board
From: Wang, Junhua H. (NSN - CN/Hangzhou) @ 2011-12-31 4:15 UTC (permalink / raw)
To: Linuxppc-dev
[-- Attachment #1.1: Type: text/plain, Size: 1865 bytes --]
HI, all:
Sorry to disturb all of you in the linuxppc-dev mail group. I am a new
member from linuxppc-dev from China, and I have a very weird problem, it
have been bothering me for a long time. I will be very grateful if you
can help me to analyse it.
1) Problem description:
a) FRIU(a circuit board) unit is a ppc(powerpc) unit, 256 M bytes Ram,
bootloader is uboot, kernel linux-2.6.21 filesystem: initramfs
The main problem is that when kernel start up and mount initramfs, run
the init process(pid 1), when the process(init) write file(20 M bytes)
to filesystem(initramfs),
sometimes it will find some data modified when check the file's contents
by read it.
b) I have write a test init process which will write 20 Mbytes
data(0xFF) to "/TEST0.IMG" and check it's contents. Sometimes, the
contents will by modified.
c) Here is the test procedure:
Uboot download linux kernel and initramfs --> cmd "bootm" to start linux
--> after kernel start complete, mount initramfs, run init process(pid
1)
--> It will write 20 Mbytes data(0XFF) to 'TEST0.IMG' and check it's
contents, If there is error, the error data will be printed.
2) Error data:
a) Every time the error happened, a pair of data modified:
first place: 1C 00 FF FF FF FF FF FF 00 00 00 040 80 ...
Second place: FF FF FF FF FF FF 00 A0 ....
Sometimes, there will be 2 pair of data modified.
b) The error happens not very often, but it happens sometime.
3)
Could you give me some advice on how to investigate it or which part you
think will have problem?
Thanks very much!
Used kernel: linux-2.6.21 <<init process write_read file(20Mbytes)
error2.txt>> <<init process write_read file(20Mbytes) error.txt>>
Br,
Wang Junhua
Wang Junhua (Jonny)
-----------------------------------------
LINDX
DX 200 R&D HZ Area E
MP: +8615967154143
Seat:4076
[-- Attachment #1.2: Type: text/html, Size: 6240 bytes --]
[-- Attachment #2: init process write_read file(20Mbytes) error2.txt --]
[-- Type: text/plain, Size: 13024 bytes --]
*$
U-Boot @(inph)BSP_VERSION_INFO=R2.0.3 SX01827-X06 V2.0.3 (Sep 30 2011 - 16:13:34)
?## Interphase 3632 FR
FPGA: Build(0) ver 2.0.2
BMC Watchdog Enabled...
DRAM: 256 MB
/-Now running in RAM - U-Boot at: 0ff6a000
FLASH: 128 MB
NETCONSOLE: (dev='nc')
In: serial
Out: serial
Err: serial
MMC: Initializing
?
POST: Disable
?
BEDBUG:ready
Hit any key to stop autoboot: 3 2 1 0
Setting bootm wdog disable flag.
command success!
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
Retry count exceeded; starting again [Try #1]
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
Retry count exceeded; starting again [Try #2]
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
Retry count exceeded; starting again [Try #3]
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
Retry count exceeded; starting again [Try #4]
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
?BOOTP broadcast 4
BOOTP broadcast 5
Retry count exceeded; starting again [Try #5]
*$
U-Boot @(inph)BSP_VERSION_INFO=R2.0.3 SX01827-X06 V2.0.3 (Sep 30 2011 - 16:13:34)
?## Interphase 3632 FR
FPGA: Build(0) ver 2.0.2
BMC Watchdog Enabled...
DRAM: 256 MB
/-Now running in RAM - U-Boot at: 0ff6a000
FLASH: 128 MB
NETCONSOLE: (dev='nc')
In: serial
Out: serial
Err: serial
MMC: Initializing
?
POST: Disable
?
BEDBUG:ready
Hit any key to stop autoboot: 3 2 1 0
Setting bootm wdog disable flag.
command success!
BOOTP broadcast 1
DHCP client bound to address 10.150.151.100
TFTP from server 10.150.151.1; our IP address is 10.150.151.100
Filename '/BLCODE/LNXSCR06.IMG'.(uboot script)
Load address: 0x400000
Loading: *#
done
Bytes transferred = 1020 (3fc hex)
## Executing script at 00400078
TFTP from server 10.150.151.1; our IP address is 10.150.151.100
Filename 'BLCODE/LNXUBO06.IMG'.(kernel)
Load address: 0x3fff88
Loading: *#################################################################
#################################################################
#################################################################
#################################################################
########################################
done
Bytes transferred = 1531530 (175e8a hex)
TFTP from server 10.150.151.1; our IP address is 10.150.151.100
Filename 'BLCODE/LNXIFSG3.IMG'.(initramfs)
Load address: 0x7fff88
Loading: *####################################################
done
Bytes transferred = 262650 (401fa hex)
## Booting image at 00400000 ...
Image Name: Linux-2.6.21.7-hrt1-cfs-v22-grse
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1531128 Bytes = 1.5 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
## Loading RAMDisk Image at 00800000 ...
Image Name: SCNMA-C Linux initramfs 2011.11.
Image Type: PowerPC Linux RAMDisk Image (uncompressed)
Data Size: 262327 Bytes = 256.2 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Loading Ramdisk to 0f709000, end 0f7490b7 ... OK
## Transferring control to Linux (at address 00000000) ...
Linux version 2.6.21.7-hrt1-cfs-v22-grsec-WR2.0bl_cgl (tdaigneault@gizmo) (gcc version 4.1.2 (Wind River Linux Sourcery G++ 4.1-84)) #1 Fri Sep 30 16:12:23 CDT 2011
Zone PFN ranges:
DMA 0 -> 65536
Normal 65536 -> 65536
early_node_map[1] active PFN ranges
0: 0 -> 65536
Built 1 zonelists. Total pages: 65024
Kernel command line: dmx_bsp=06 dmx_architecture=3 console=ttyUL0,38400 root=/dev/ram0 rw mtdparts=physmap-flash.0:5M,2M,48M,8M,128K,128K,768K,5M,2M,48M,8M,128K,128K,768K ip=10.150.151.100:10.150.151.1:10.150.151.1:255.255.255.0:iph3632:eth0:on envbase=0xfff00000 server_ip=10.150.151.1
Xilinx INTC #0 at 0x50000000 mapped to 0xFDFFF000
PID hash table entries: 1024 (order: 10, 4096 bytes)
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 256000k available (2400k kernel code, 924k data, 116k init, 0k highmem)
Security Framework v1.0.0 initialized
Capability LSM initialized
Mount-cache hash table entries: 512
NET: Registered protocol family 16
Generic PHY: Registered new driver
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP reno registered
checking if image is initramfs... it is
Freeing initrd memory: 256k freed
Registering GDB sysrq handler
JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
LTT : ltt-facilities init
LTT : ltt-relay init
xilinx_spi 0: at 0x40200000 mapped to 0xD1060000, irq=5
uartlite.0: ttyUL0 at MMIO map 0x40600000 mem 0xd105c000 (irq = 2) is a uartlite
uartlite.1: ttyUL1 at MMIO map 0x40620000 mem 0xd105e000 (irq = 0) is a uartlite
uartlite.2: ttyUL2 at MMIO map 0x40640000 mem 0xd1072000 (irq = 1) is a uartlite
RAMDISK driver initialized: 8 RAM disks of 32768K size 1024 blocksize
temac_probe: - temac[0] [v1.0.6]
temac_probe: - temac[0] iobase reg 0x70000000 -> 0xd1080000
temac_probe: - temac[0] SDMA reg 0x2c000000 -> 0xd1074000
temac_probe: - temac[0] DMA irqs tx = 11, rx = 12
temac_probe: - temac[0] MAC address = 00 00 77 b3 f6 7c
temac_probe: - temac[0] driver loaded
temac_probe: - temac[1] [v1.0.6]
temac_probe: - temac[1] iobase reg 0x80000000 -> 0xd1180000
temac_probe: - temac[1] SDMA reg 0x2c010000 -> 0xd1076000
temac_probe: - temac[1] DMA irqs tx = 9, rx = 10
temac_probe: - temac[1] MAC address = 00 00 77 b3 f6 7d
temac_probe: - temac[1] driver loaded
temac_probe: - temac[2] [v1.0.6]
temac_probe: - temac[2] iobase reg 0x80000040 -> 0xd1280040
temac_probe: - temac[2] SDMA reg 0x2c020000 -> 0xd1078000
temac_probe: - temac[2] DMA irqs tx = 7, rx = 8
temac_probe: - temac[2] MAC address = 00 00 77 b3 f6 7e
temac_probe: - temac[2] driver loaded
netconsole: not configured, aborting
i2c /dev entries driver
physmap platform flash device: 08000000 at f8000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
physmap-flash.0: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
14 cmdlinepart partitions found on MTD device physmap-flash.0
Creating 14 MTD partitions on "physmap-flash.0":
0x00000000-0x00500000 : "Partition_000"
0x00500000-0x00700000 : "Partition_001"
0x00700000-0x03700000 : "Partition_002"
0x03700000-0x03f00000 : "Partition_003"
0x03f00000-0x03f20000 : "Partition_004"
0x03f20000-0x03f40000 : "Partition_005"
0x03f40000-0x04000000 : "Partition_006"
0x04000000-0x04500000 : "Partition_007"
0x04500000-0x04700000 : "Partition_008"
0x04700000-0x07700000 : "Partition_009"
0x07700000-0x07f00000 : "Partition_010"
0x07f00000-0x07f20000 : "Partition_011"
0x07f20000-0x07f40000 : "Partition_012"
0x07f40000-0x08000000 : "Partition_013"
TCP cubic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
eth0: Promiscuous mode disabled.
eth0: initialized.
eth0: DOWN
IP-Config: Complete:
device=eth0, addr=10.150.151.100, mask=255.255.255.0, gw=10.150.151.1,
host=iph3632, domain=, nis-domain=(none),
bootserver=10.150.151.1, rootserver=10.150.151.1, rootpath=
Freeing unused kernel memoryotest start!
test: 0, file length: 125 M name: /TEST0.IMG
eth0: UP
read: 0, name: /TEST0.IMG
error found at offset: 0x549400
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 1c 0 ff ff
ff ff ff ff 0 0 0 4 8 0 fd be 45 0 2 52
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
error pos: 5543308
error found at offset: 0x54A000
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 1c 0 ff ff
ff ff ff ff 0 0 0 4 8 0 fd be 45 0 2 52
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
?
error pos: 5546444
test: 1, file length: 125 M name: /TEST0.IMG
read: 1, name: /TEST0.IMG
test: 2, file length: 125 M name: /TEST0.IMG
read: 2, name: /TEST0.IMG
test: 3, file length: 125 M name: /TEST0.IMG
read: 3, name: /TEST0.IMG
test: 4, file length: 125 M name: /TEST0.IMG
read: 4, name: /TEST0.IMG
test: 5, file length: 125 M name: /TEST0.IMG
read: 5, name: /TEST0.IMG
test: 6, file length: 125 M name: /TEST0.IMG
read: 6, name: /TEST0.IMG
test: 7, file length: 125 M name: /TEST0.IMG
read: 7, name: /TEST0.IMG
test: 8, file length: 125 M name: /TEST0.IMG
read: 8, name: /TEST0.IMG
[-- Attachment #3: init process write_read file(20Mbytes) error.txt --]
[-- Type: text/plain, Size: 20426 bytes --]
*$
U-Boot @(inph)BSP_VERSION_INFO=R2.0.4 SX01827-A02 V2.0.4 (Nov 3 2011 - 13:43:51)
?## Interphase 3632 FR
FPGA: Build(0) ver 2.0.3
BMC Watchdog Enabled...
DRAM: 256 MB
\b/\b-\bNow running in RAM - U-Boot at: 0ff69000
FLASH: 128 MB
NETCONSOLE: (dev='nc')
In: serial
Out: serial
Err: serial
MMC: Initializing
POST: Disable
BEDBUG:ready
Hit any key to stop autoboot: 3 \b\b\b 2 \b\b\b 1 \b\b\b 0
Setting bootm wdog disable flag.
command success!
BOOTP broadcast 1
DHCP client bound to address 10.150.151.104
TFTP from server 10.150.151.1; our IP address is 10.150.151.104
Filename '/BLCODE/LNXSCR06.IMG'.
Load address: 0x400000
Loading: *\b#
done
Bytes transferred = 510 (1fe hex)
## Executing script at 00400078
TFTP from server 10.150.151.1; our IP address is 10.150.151.104
Filename 'BLCODE/LNXUBO06.IMG'.
Load address: 0x3fff88
Loading: *\b#################################################################
#################################################################
#################################################################
#################################################################
##################################
done
Bytes transferred = 1504500 (16f4f4 hex)
TFTP from server 10.150.151.1; our IP address is 10.150.151.104
Filename 'BLCODE/LNXIFSG3.IMG'.
Load address: 0x7fff88
Loading: *\b#####################################################
done
Bytes transferred = 266730 (411ea hex)
## Booting image at 00400000 ...
Image Name: Linux-2.6.21.7-hrt1-cfs-v22-grse
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 1504191 Bytes = 1.4 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
## Loading RAMDisk Image at 00800000 ...
Image Name: Making U-Boot Head
Image Type: PowerPC Linux RAMDisk Image (uncompressed)
Data Size: 266155 Bytes = 259.9 kB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Loading Ramdisk to 0f707000, end 0f747fab ... OK
## Transferring control to Linux (at address 00000000) ...
Initializing container subsys cpu
Linux version 2.6.21.7-hrt1-cfs-v22-grsec-WR2.0aq_cgl (junhuawa@hzling08.china.nsn-net.net) (gcc version 4.1.2 (Wind River Linux Sourcery G++ 4.1-182)) #1 PREEMPT Wed Dec 28 16:16:55 CST 2011
Zone PFN ranges:
DMA 0 -> 65536
Normal 65536 -> 65536
early_node_map[1] active PFN ranges
0: 0 -> 65536
Built 1 zonelists. Total pages: 65024
Kernel command line: dmx_bsp=06 dmx_architecture=3 console=ttyUL0,38400 root=/dev/ram0 rw
Xilinx INTC #0 at 0x50000000 mapped to 0xFDFFF000
PID hash table entries: 1024 (order: 10, 4096 bytes)
Console: colour dummy device 80x25
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 256000k available (2448k kernel code, 852k data, 108k init, 0k highmem)
Security Framework v1.0.0 initialized
Mount-cache hash table entries: 512
Initializing container subsys debug
NET: Registered protocol family 16
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP reno registered
checking if image is initramfs... it is
Freeing initrd memory: 259k freed
Registering GDB sysrq handler
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered (default)
LTT : ltt-facilities init
LTT : ltt-relay init
xilinx_spi 0: at 0x40200000 mapped to 0xD1000000, irq=5
uartlite.0: ttyUL0 at MMIO map 0x40600000 mem 0xd1012000 (irq = 2) is a uartlite
uartlite.1: ttyUL1 at MMIO map 0x40620000 mem 0xd1014000 (irq = 0) is a uartlite
uartlite.2: ttyUL2 at MMIO map 0x40640000 mem 0xd1016000 (irq = 1) is a uartlite
RAMDISK driver initialized: 8 RAM disks of 32768K size 1024 blocksize
i2c /dev entries driver
physmap platform flash device: 08000000 at f8000000
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
physmap-flash.0: CFI does not contain boot bank location. Assuming top.
number of CFI chips: 1
cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.
TCP cubic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
Freeing unused kernel memory
test 0 start:/TEST0.IMG
test: 0, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 0, name: /TEST0.IMG
test 1 start:/TEST0.IMG
test: 1, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 1, name: /TEST0.IMG
test 2 start:/TEST0.IMG
test: 2, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 2, name: /TEST0.IMG
test 3 start:/TEST0.IMG
test: 3, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 3, name: /TEST0.IMG
test 4 start:/TEST0.IMG
test: 4, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 4, name: /TEST0.IMG
test 5 start:/TEST0.IMG
test: 5, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 5, name: /TEST0.IMG
test 6 start:/TEST0.IMG
test: 6, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 6, name: /TEST0.IMG
test 7 start:/TEST0.IMG
test: 7, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 7, name: /TEST0.IMG
test 8 start:/TEST0.IMG
test: 8, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 8, name: /TEST0.IMG
test 9 start:/TEST0.IMG
test: 9, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 9, name: /TEST0.IMG
test 10 start:/TEST0.IMG
test: 10, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 10, name: /TEST0.IMG
test 11 start:/TEST0.IMG
test: 11, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 11, name: /TEST0.IMG
test 12 start:/TEST0.IMG
test: 12, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 12, name: /TEST0.IMG
test 13 start:/TEST0.IMG
test: 13, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 13, name: /TEST0.IMG
test 14 start:/TEST0.IMG
test: 14, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 14, name: /TEST0.IMG
test 15 start:/TEST0.IMG
test: 15, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 15, name: /TEST0.IMG
test 16 start:/TEST0.IMG
test: 16, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 16, name: /TEST0.IMG
test 17 start:/TEST0.IMG
test: 17, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 17, name: /TEST0.IMG
test 18 start:/TEST0.IMG
test: 18, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 18, name: /TEST0.IMG
test 19 start:/TEST0.IMG
test: 19, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 19, name: /TEST0.IMG
test 20 start:/TEST0.IMG
test: 20, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 20, name: /TEST0.IMG
test 21 start:/TEST0.IMG
test: 21, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 21, name: /TEST0.IMG
test 22 start:/TEST0.IMG
test: 22, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 22, name: /TEST0.IMG
test 23 start:/TEST0.IMG
test: 23, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 23, name: /TEST0.IMG
test 24 start:/TEST0.IMG
test: 24, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 24, name: /TEST0.IMG
test 25 start:/TEST0.IMG
test: 25, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 25, name: /TEST0.IMG
test 26 start:/TEST0.IMG
test: 26, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 26, name: /TEST0.IMG
test 27 start:/TEST0.IMG
test: 27, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 27, name: /TEST0.IMG
test 28 start:/TEST0.IMG
test: 28, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 28, name: /TEST0.IMG
test 29 start:/TEST0.IMG
test: 29, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 29, name: /TEST0.IMG
test 30 start:/TEST0.IMG
test: 30, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 30, name: /TEST0.IMG
test 31 start:/TEST0.IMG
test: 31, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 31, name: /TEST0.IMG
test 32 start:/TEST0.IMG
test: 32, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 32, name: /TEST0.IMG
test 33 start:/TEST0.IMG
test: 33, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 33, name: /TEST0.IMG
test 34 start:/TEST0.IMG
test: 34, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 34, name: /TEST0.IMG
test 35 start:/TEST0.IMG
test: 35, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 35, name: /TEST0.IMG
test 36 start:/TEST0.IMG
test: 36, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 36, name: /TEST0.IMG
test 37 start:/TEST0.IMG
test: 37, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 37, name: /TEST0.IMG
test 38 start:/TEST0.IMG
test: 38, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 38, name: /TEST0.IMG
error found at offset: 0xBED800 bytes
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff 1c 0 ff ff
ff ff ff ff 0 0 0 4 8 6 df 99 0 1 0 3c
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
error found at offset: 0xBEDE00 bytes
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff 0 a0 a5 65 3 78 8 6 0 1
8 0 6 4 0 1 0 a0 a5 65 3 78 a a a 1
0 0 0 0 0 0 a a a 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
error found at offset: 0xBEE400 bytes
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff 1c 0 ff ff
ff ff ff ff 0 0 0 4 8 6 df 99 0 1 0 3c
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
error found at offset: 0xBEEA00 bytes
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff 0 a0 a5 65 3 78 8 6 0 1
8 0 6 4 0 1 0 a0 a5 65 3 78 a a a 1
error found at offset: 0xBEEC00 bytes
0 0 0 0 0 0 a a a 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
found error
test 0 start:/TEST0.IMG
test: 0, file length: 20 M name: /TEST0.IMG
file size: 0x1400000
read: 0, name: /TEST0.IMG
found error
Kernel panic - not syncing: Attempted to kill init!
Rebooting in 180 seconds..*$
^ permalink raw reply
* Re: [PATCH 82/94] USB: ehci-fsl: Fix 'have_sysif_regs' detection
From: Jason Jin @ 2011-12-31 6:43 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1325263910-14057-83-git-send-email-Jason.jin@freescale.com>
[-- Attachment #1: Type: text/plain, Size: 4997 bytes --]
Please ignore this mail, It's wrongly sent out. Thanks.
On Sat, Dec 31, 2011 at 12:51 AM, Jason Jin <Jason.jin@freescale.com> wrote:
> From: Pan Jiafei <Jiafei.Pan@freescale.com>
>
> extract from vendor drop QorIQ-DPAA-SDK-20111026-systembuilder.iso
>
> Previously a check was done on an ID register at the base of a CPU's
> internal USB registers to determine if system interface regsiters were
> present. The check looked for an ID register that had the format
> ID[0:5] == ~ID[8:13] as described in the MPC5121 User's Manual to
> determine if a MPC5121 or MPC83xx/85xx was being used.
>
> There are two issues with this method:
> - The ID register is not defined on the MPC83xx/85xx CPUs, so its
> unclear what is being checked on them.
> - Newer CPUs such as the P4080 also don't document the ID register, but
> do share the same format as the MPC5121. Thus the previous code did
> not set 'have_sysif_regs' properly which results in the P4080 not
> properly initializing its USB ports.
>
> Using the device tree 'compatible' node is a cleaner way to determine if
> 'have_sysif_regs' should be set and resolves the USB initialization issue
> seen on the P4080.
>
> Tested on a P4080-based system and compile tested on mpc512x_defconfig
> with Freescale EHCI driver enabled.
>
> Cc: Anatolij Gustschin <agust@denx.de>
> Cc: David Brownell <dbrownell@users.sourceforge.net>
> Cc: Kumar Gala <galak@kernel.crashing.org>
> Cc: linuxppc-dev@lists.ozlabs.org
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
> Integrated-by: Pan Jiafei <Jiafei.Pan@freescale.com>
> ---
> drivers/usb/host/ehci-fsl.c | 13 -------------
> drivers/usb/host/ehci-fsl.h | 3 ---
> drivers/usb/host/fsl-mph-dr-of.c | 11 ++++++++---
> 3 files changed, 8 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
> index ac5f38d..22baaec 100644
> --- a/drivers/usb/host/ehci-fsl.c
> +++ b/drivers/usb/host/ehci-fsl.c
> @@ -52,7 +52,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver
> *driver,
> struct resource *res;
> int irq;
> int retval;
> - unsigned int temp;
>
> pr_debug("initializing FSL-SOC USB Controller\n");
>
> @@ -126,18 +125,6 @@ static int usb_hcd_fsl_probe(const struct hc_driver
> *driver,
> goto err3;
> }
>
> - /*
> - * Check if it is MPC5121 SoC, otherwise set pdata->have_sysif_regs
> - * flag for 83xx or 8536 system interface registers.
> - */
> - if (pdata->big_endian_mmio)
> - temp = in_be32(hcd->regs + FSL_SOC_USB_ID);
> - else
> - temp = in_le32(hcd->regs + FSL_SOC_USB_ID);
> -
> - if ((temp & ID_MSK) != (~((temp & NID_MSK) >> 8) & ID_MSK))
> - pdata->have_sysif_regs = 1;
> -
> /* Enable USB controller, 83xx or 8536 */
> if (pdata->have_sysif_regs)
> setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
> diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
> index 2c83537..3fabed3 100644
> --- a/drivers/usb/host/ehci-fsl.h
> +++ b/drivers/usb/host/ehci-fsl.h
> @@ -19,9 +19,6 @@
> #define _EHCI_FSL_H
>
> /* offsets for the non-ehci registers in the FSL SOC USB controller */
> -#define FSL_SOC_USB_ID 0x0
> -#define ID_MSK 0x3f
> -#define NID_MSK 0x3f00
> #define FSL_SOC_USB_ULPIVP 0x170
> #define FSL_SOC_USB_PORTSC1 0x184
> #define PORT_PTS_MSK (3<<30)
> diff --git a/drivers/usb/host/fsl-mph-dr-of.c
> b/drivers/usb/host/fsl-mph-dr-of.c
> index 574b99e..79a66d6 100644
> --- a/drivers/usb/host/fsl-mph-dr-of.c
> +++ b/drivers/usb/host/fsl-mph-dr-of.c
> @@ -262,19 +262,24 @@ static void fsl_usb2_mpc5121_exit(struct
> platform_device *pdev)
> }
> }
>
> -struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
> +static struct fsl_usb2_platform_data fsl_usb2_mpc5121_pd = {
> .big_endian_desc = 1,
> .big_endian_mmio = 1,
> .es = 1,
> + .have_sysif_regs = 0,
> .le_setup_buf = 1,
> .init = fsl_usb2_mpc5121_init,
> .exit = fsl_usb2_mpc5121_exit,
> };
> #endif /* CONFIG_PPC_MPC512x */
>
> +static struct fsl_usb2_platform_data fsl_usb2_mpc8xxx_pd = {
> + .have_sysif_regs = 1,
> +};
> +
> static const struct of_device_id fsl_usb2_mph_dr_of_match[] = {
> - { .compatible = "fsl-usb2-mph", },
> - { .compatible = "fsl-usb2-dr", },
> + { .compatible = "fsl-usb2-mph", .data = &fsl_usb2_mpc8xxx_pd, },
> + { .compatible = "fsl-usb2-dr", .data = &fsl_usb2_mpc8xxx_pd, },
> #ifdef CONFIG_PPC_MPC512x
> { .compatible = "fsl,mpc5121-usb2-dr", .data =
> &fsl_usb2_mpc5121_pd, },
> #endif
> --
> 1.7.5.1
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
--
Best Regards,
Zhengxiong Jin
[-- Attachment #2: Type: text/html, Size: 6374 bytes --]
^ permalink raw reply
* Re: Ask a technical problem happened on PPC board
From: manu @ 2011-12-31 9:01 UTC (permalink / raw)
Cc: Linuxppc-dev
In-Reply-To: <E2D908A47720CD488BC2AFD11DB6A1B540E9A1@CNBEEXC007.nsn-intra.net>
[-- Attachment #1: Type: text/plain, Size: 2833 bytes --]
Hi,
it looks like a memory interface problem. This is a typical issue with
FPGA-based PPC systems.
You should check/monitor carefully the hardware :
- power supplies
- memory controller configuration (RAS, CAS, banks...)
- timing of pins connected to external memory
Prior to boot a linux kernel, you should test your board with an
exhaustive standalone test program running from internal BRAM. In
particular, you should run an intensive test of your external memory
with cache enabled. Cache must be configured in copy back mode and test
code must be written so that it causes a lot of cache misses.
Hope this helps.
Manu
Le 31/12/2011 05:15, Wang, Junhua H. (NSN - CN/Hangzhou) a écrit :
>
> HI, all:
>
> Sorry to disturb all of you in the linuxppc-dev mail group. I am a new
> member from linuxppc-dev from China, and I have a very weird problem,
> it have been bothering me for a long time. I will be very grateful if
> you can help me to analyse it.
>
> 1) Problem description:
>
> a) FRIU(a circuit board) unit is a ppc(powerpc) unit, 256 M bytes Ram,
> bootloader is uboot, kernel linux-2.6.21 filesystem: initramfs
>
> The main problem is that when kernel start up and mount initramfs, run
> the init process(pid 1), when the process(init) write file(20 M bytes)
> to filesystem(initramfs),
>
> sometimes it will find some data modified when check the file's
> contents by read it.
>
> b) I have write a test init process which will write 20 Mbytes
> data(0xFF) to "/TEST0.IMG" and check it's contents. Sometimes, the
> contents will by modified.
>
> c) Here is the test procedure:
>
> Uboot download linux kernel and initramfs --> cmd "bootm" to start
> linux -->after kernel start complete, mount initramfs, run init
> process(pid 1)
>
> --> It will write 20 Mbytes data(0XFF) to 'TEST0.IMG' and check it's
> contents, If there is error, the error data will be printed.
>
> 2) Error data:
>
> a) Every time the error happened, a pair of data modified:
>
> first place: 1C 00 FF FF FF FF FF FF 00 00 00 040 80 ...
>
> Second place:FF FF FF FF FF FF 00 A0 ....
>
> Sometimes, there will be 2 pair of data modified.
>
> b) The error happens not very often, but it happens sometime.
>
> 3)
>
> Could you give me some advice on how to investigate it or which part
> you think will have problem?
>
> Thanks very much!
>
> Usedkernel: linux-2.6.21<<init process write_read file(20Mbytes)
> error2.txt>> <<init process write_read file(20Mbytes) error.txt>>
>
> Br,
>
> Wang Junhua
>
> *Wang Junhua (Jonny)*//
>
> /-----------------------------------------/
>
> /LINDX/
>
> /DX 200 R&D HZ Area E /
>
> /MP: +8615967154143/
>
> /Seat:4076/
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
[-- Attachment #2: Type: text/html, Size: 8816 bytes --]
^ permalink raw reply
* Re: Ask a technical problem happened on PPC board
From: Lorenz Kolb @ 2011-12-31 11:16 UTC (permalink / raw)
To: Wang, Junhua H. (NSN - CN/Hangzhou); +Cc: Linuxppc-dev
In-Reply-To: <E2D908A47720CD488BC2AFD11DB6A1B540E9A1@CNBEEXC007.nsn-intra.net>
[-- Attachment #1: Type: text/plain, Size: 2743 bytes --]
Hi,
first of all: have you tried doing a standalone memory test application?
From what I see you are using either a Virtex-4FX or Virtex-5FXT
device, correct?
So I'd highly recommend doing a standalone test prior to booting Linux
to verify the memory controller timings of the FPGA based SoC.
Apart from this: your Linux-Kernel and gcc seem to be pretty outdated.
Using a more recent Linux and toolchain often solves a lot of issues (my
experience, esp. with PowerPC Linux for Xilinx FPGAs).
Regards,
Lorenz
Missing Link Electronics
On 12/31/2011 5:15 AM, Wang, Junhua H. (NSN - CN/Hangzhou) wrote:
>
> HI, all:
>
> Sorry to disturb all of you in the linuxppc-dev mail group. I am a new
> member from linuxppc-dev from China, and I have a very weird problem,
> it have been bothering me for a long time. I will be very grateful if
> you can help me to analyse it.
>
> 1) Problem description:
>
> a) FRIU(a circuit board) unit is a ppc(powerpc) unit, 256 M bytes Ram,
> bootloader is uboot, kernel linux-2.6.21 filesystem: initramfs
>
> The main problem is that when kernel start up and mount initramfs, run
> the init process(pid 1), when the process(init) write file(20 M bytes)
> to filesystem(initramfs),
>
> sometimes it will find some data modified when check the file's
> contents by read it.
>
> b) I have write a test init process which will write 20 Mbytes
> data(0xFF) to "/TEST0.IMG" and check it's contents. Sometimes, the
> contents will by modified.
>
> c) Here is the test procedure:
>
> Uboot download linux kernel and initramfs --> cmd "bootm" to start
> linux -->after kernel start complete, mount initramfs, run init
> process(pid 1)
>
> --> It will write 20 Mbytes data(0XFF) to 'TEST0.IMG' and check it's
> contents, If there is error, the error data will be printed.
>
> 2) Error data:
>
> a) Every time the error happened, a pair of data modified:
>
> first place: 1C 00 FF FF FF FF FF FF 00 00 00 040 80 ...
>
> Second place:FF FF FF FF FF FF 00 A0 ....
>
> Sometimes, there will be 2 pair of data modified.
>
> b) The error happens not very often, but it happens sometime.
>
> 3)
>
> Could you give me some advice on how to investigate it or which part
> you think will have problem?
>
> Thanks very much!
>
> Usedkernel: linux-2.6.21<<init process write_read file(20Mbytes)
> error2.txt>> <<init process write_read file(20Mbytes) error.txt>>
>
> Br,
>
> Wang Junhua
>
> *Wang Junhua (Jonny)*//
>
> /-----------------------------------------/
>
> /LINDX/
>
> /DX 200 R&D HZ Area E /
>
> /MP: +8615967154143/
>
> /Seat:4076/
>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
[-- Attachment #2: Type: text/html, Size: 8685 bytes --]
^ permalink raw reply
* Re: linux-next: build failure after merge of the final tree (powerpc related)
From: Grant Likely @ 2012-01-02 8:25 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Stephen Rothwell, linux-kernel, linux-next, Paul Mackerras,
Thomas Gleixner, linuxppc-dev
In-Reply-To: <1325068334.6632.43.camel@pasglop>
On Wed, Dec 28, 2011 at 09:32:14PM +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2011-12-28 at 19:49 +1100, Stephen Rothwell wrote:
> > Hi ,
> >
> > After merging the final tree, today's linux-next build (powerpc
> > allyesconfig) failed like this:
> >
> > kernel/built-in.o: In function `irq_dispose_mapping':
> > (.opd+0x159f0): multiple definition of `irq_dispose_mapping'
> > arch/powerpc/kernel/built-in.o:(.opd+0x960): first defined here
> > kernel/built-in.o: In function `irq_create_of_mapping':
> > (.opd+0x15a20): multiple definition of `irq_create_of_mapping'
> > arch/powerpc/kernel/built-in.o:(.opd+0x9a8): first defined here
> > kernel/built-in.o: In function `.irq_create_of_mapping':
> > (.text+0x147030): multiple definition of `.irq_create_of_mapping'
> > arch/powerpc/kernel/built-in.o:(.text+0x9de0): first defined here
> > kernel/built-in.o: In function `.irq_dispose_mapping':
> > (.text+0x146f4c): multiple definition of `.irq_dispose_mapping'
> > arch/powerpc/kernel/built-in.o:(.text+0x9684): first defined here
> >
> > I am not sure what caused this. And have just left it broken.
>
> Grant, is your irq remapper misbehaving ?
Hmmmm, that's odd. I've not touched it. I'll investigate.
^ permalink raw reply
* Re: linux-next: build failure after merge of the final tree (powerpc related)
From: Grant Likely @ 2012-01-02 8:39 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Stephen Rothwell, Benoit Cousson, linux-kernel, linux-next,
Paul Mackerras, Thomas Gleixner, linuxppc-dev, Samuel Ortiz
In-Reply-To: <20120102082514.GG18381@ponder.secretlab.ca>
On Mon, Jan 2, 2012 at 1:25 AM, Grant Likely <grant.likely@secretlab.ca> wr=
ote:
> On Wed, Dec 28, 2011 at 09:32:14PM +1100, Benjamin Herrenschmidt wrote:
>> On Wed, 2011-12-28 at 19:49 +1100, Stephen Rothwell wrote:
>> > Hi ,
>> >
>> > After merging the final tree, today's linux-next build (powerpc
>> > allyesconfig) failed like this:
>> >
>> > kernel/built-in.o: In function `irq_dispose_mapping':
>> > (.opd+0x159f0): multiple definition of `irq_dispose_mapping'
>> > arch/powerpc/kernel/built-in.o:(.opd+0x960): first defined here
>> > kernel/built-in.o: In function `irq_create_of_mapping':
>> > (.opd+0x15a20): multiple definition of `irq_create_of_mapping'
>> > arch/powerpc/kernel/built-in.o:(.opd+0x9a8): first defined here
>> > kernel/built-in.o: In function `.irq_create_of_mapping':
>> > (.text+0x147030): multiple definition of `.irq_create_of_mapping'
>> > arch/powerpc/kernel/built-in.o:(.text+0x9de0): first defined here
>> > kernel/built-in.o: In function `.irq_dispose_mapping':
>> > (.text+0x146f4c): multiple definition of `.irq_dispose_mapping'
>> > arch/powerpc/kernel/built-in.o:(.text+0x9684): first defined here
>> >
>> > I am not sure what caused this. And have just left it broken.
>>
>> Grant, is your irq remapper misbehaving ?
>
> Hmmmm, that's odd. =A0I've not touched it. =A0I'll investigate.
It looks like CONFIG_IRQ_DOMAIN is getting selected by TWL4030_CORE.
Drivers must not select that config symbol. It looks like commit
da28adbd (mfd: twl-core: Add initial DT support for twl4030/twl6030)
is the culprit.
The following patch should solve the problem:
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 13c468e..e43a570 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -200,8 +200,7 @@ config MENELAUS
config TWL4030_CORE
bool "Texas Instruments TWL4030/TWL5030/TWL6030/TPS659x0 Support"
- depends on I2C=3Dy && GENERIC_HARDIRQS
- select IRQ_DOMAIN
+ depends on I2C=3Dy && GENERIC_HARDIRQS && IRQ_DOMAIN
help
Say yes here if you have TWL4030 / TWL6030 family chip on your board.
This core driver provides register access and IRQ handling
^ permalink raw reply related
* Mac address change in linux
From: smitha.vanga @ 2012-01-02 11:24 UTC (permalink / raw)
To: scottwood; +Cc: linuxppc-dev
Hi Scott,
When I execute below statements in linux to change the mac address I get the=
error Host name look up error.
Below are the commands I execute to change the mac address and the console o=
utput.
1. ifconfig eth0.246 down
2. ifconfig eth0.246 hw ether 00:11:22:33:44:55
ifconfig: hw: Host name lookup failure
sh-3.1# ifconfig
eth0 Link encap:Ethernet HWaddr 00:E0:EE:00:05:2E
inet addr:172.16.52.20 Bcast:172.16.53.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:999 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:93661 (91.4 KiB) TX bytes:0 (0.0 B)
eth0.246 Link encap:Ethernet HWaddr 00:E0:EE:00:05:2E
inet addr:172.16.52.20 Bcast:172.16.53.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:4 errors:0 dropped:0 overruns:0 frame:0
TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:248 (248.0 B) TX bytes:248 (248.0 B)
sh-3.1# ifconfig eth0.246 down
sh-3.1# ifconfig
eth0 Link encap:Ethernet HWaddr 00:E0:EE:00:05:2E
inet addr:172.16.52.20 Bcast:172.16.53.255 Mask:255.255.254.0
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:1005 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:94205 (91.9 KiB) TX bytes:0 (0.0 B)
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:4 errors:0 dropped:0 overruns:0 frame:0
TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:248 (248.0 B) TX bytes:248 (248.0 B)
sh-3.1# ifconfig eth0.246 hw ether 00:11:22:33:44:55 ifconfig eth0.246 up
ifconfig: hw: Host name lookup failure
sh-3.1#
Regards,
Smitha
Please do not print this email unless it is absolutely necessary. =0A=
=0A=
The information contained in this electronic message and any attachments to=
this message are intended for the exclusive use of the addressee(s) and may=
contain proprietary, confidential or privileged information. If you are not=
the intended recipient, you should not disseminate, distribute or copy this=
e-mail. Please notify the sender immediately and destroy all copies of this=
message and any attachments. =0A=
=0A=
WARNING: Computer viruses can be transmitted via email. The recipient should=
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ny accepts no liability for any damage caused by any virus transmitted by th=
is email. =0A=
=0A=
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^ permalink raw reply
* Re: p1020 unstable with 3.2
From: Alexander Graf @ 2012-01-02 15:20 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Scott Wood, linuxppc-dev, Fleming Andy-AFLEMING
In-Reply-To: <1325048474.6632.33.camel@pasglop>
On 28.12.2011, at 06:01, Benjamin Herrenschmidt wrote:
> On Sun, 2011-12-25 at 11:48 +0100, Alexander Graf wrote:
>> On 24.12.2011, at 07:53, Benjamin Herrenschmidt wrote:
>>
>>> On Fri, 2011-12-23 at 17:54 +0100, Alexander Graf wrote:
>>>> Hi guys,
>>>>
>>>> While trying to test my latest patch queue for ppc kvm, I realized
>>>> that even though the device trees got updated, the p1020 box still is
>>>> unstable. The trace below is the one I've seen the most. It only
>>>> occurs during network I/O which happens a lot on that box, since I'm
>>>> running it using NFS root.
>>>>
>>>> As for configuration, I use kumar's "merge" branch from today and the
>>>> p1020rdb.dts device tree provided in that tree.
>>>>
>>>> The last known good configuration I'm aware of is 3.0.
>>>>
>>>> Any ideas what's going wrong here?
>>>
>>> Try SLAB instead of SLUB and let me know. It -could- be a bogon in SLUB
>>> that should be fixed upstream now but I think did hit 3.2
>>
>> Yup, things seem a lot more stable with SLAB now :).
>
> BTW. Fix for slub should be upstream:
>
> 42d623a8cd08eb93ab221d22cee5a62618895bbf
Yup, works like a charm now again. Thanks a lot!
Alex
^ permalink raw reply
* Re: [PATCH] KVM: Move gfn_to_memslot() to kvm_host.h
From: Alexander Graf @ 2012-01-02 15:23 UTC (permalink / raw)
To: Avi Kivity; +Cc: linuxppc-dev, Paul Mackerras, kvm, kvm-ppc
In-Reply-To: <4EF87528.8000305@redhat.com>
On 26.12.2011, at 14:22, Avi Kivity wrote:
> On 12/20/2011 11:21 AM, Paul Mackerras wrote:
>> This moves gfn_to_memslot(), and the functions it calls, that is,
>> search_memslots() and __gfn_to_memslot(), from kvm_main.c to kvm_host.h
>> so that gfn_to_memslot() can be called from non-modular code even
>> when KVM is a module. On powerpc, the Book3S HV style of KVM has
>> code that is called from real mode which needs to call gfn_to_memslot()
>> and thus needs this. (Module code is allocated in the vmalloc region,
>> which can't be accessed in real mode.)
>>
>> With this, we can remove builtin_gfn_to_memslot() from book3s_hv_rm_mmu.c
>> and thus eliminate a little bit of duplication.
>
> Those functions are too big to be inlined IMO. How about moving them to
> another C file, and making it builtin for ppc?
>
> The only issue is what to call it. virt/kvm/builtin-for-ppc seems silly.
Yeah - and it makes it pretty confusing to find the functions then.
> Or we could move the implementation into a header file, with an extra __
> prefix, and have the C stubs call those inlines, so we have exactly on
> instantiation. Your real mode code can then call the inlines.
I like this version. That way everyone should be happy :)
Alex
^ permalink raw reply
* Re: Mac address change in linux
From: Lorenz Kolb @ 2012-01-02 15:42 UTC (permalink / raw)
To: smitha.vanga; +Cc: scottwood, linuxppc-dev
In-Reply-To: <40631E9A2581F14BA60888C87A76A1FE01C96A@HYD-MKD-MBX4.wipro.com>
Hi Smitha,
first of: please try changing the MAC of the adapter, not of the virtual
interface (btw: are you sure, that you really intend to have a physical
and a virtual interface that have the same configurations and the same
metric?).
second: guess your copy+pasted log shows: that you concatenated
"ifconfig eth0.246 up" to the actual MAC address change command by
accident. Please try again, without these additional (surely non
working) parameters.
Regards,
lorenz
On 1/2/2012 12:24 PM, smitha.vanga@wipro.com wrote:
> Hi Scott,
>
> When I execute below statements in linux to change the mac address I get the error Host name look up error.
> Below are the commands I execute to change the mac address and the console output.
>
>
> 1. ifconfig eth0.246 down
> 2. ifconfig eth0.246 hw ether 00:11:22:33:44:55
> ifconfig: hw: Host name lookup failure
>
> sh-3.1# ifconfig
> eth0 Link encap:Ethernet HWaddr 00:E0:EE:00:05:2E
> inet addr:172.16.52.20 Bcast:172.16.53.255 Mask:255.255.254.0
> UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
> RX packets:999 errors:0 dropped:0 overruns:0 frame:0
> TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
> collisions:0 txqueuelen:1000
> RX bytes:93661 (91.4 KiB) TX bytes:0 (0.0 B)
>
> eth0.246 Link encap:Ethernet HWaddr 00:E0:EE:00:05:2E
> inet addr:172.16.52.20 Bcast:172.16.53.255 Mask:255.255.254.0
> UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
> RX packets:0 errors:0 dropped:0 overruns:0 frame:0
> TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
> collisions:0 txqueuelen:0
> RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)
>
> lo Link encap:Local Loopback
> inet addr:127.0.0.1 Mask:255.0.0.0
> UP LOOPBACK RUNNING MTU:16436 Metric:1
> RX packets:4 errors:0 dropped:0 overruns:0 frame:0
> TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
> collisions:0 txqueuelen:0
> RX bytes:248 (248.0 B) TX bytes:248 (248.0 B)
>
> sh-3.1# ifconfig eth0.246 down
> sh-3.1# ifconfig
> eth0 Link encap:Ethernet HWaddr 00:E0:EE:00:05:2E
> inet addr:172.16.52.20 Bcast:172.16.53.255 Mask:255.255.254.0
> UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
> RX packets:1005 errors:0 dropped:0 overruns:0 frame:0
> TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
> collisions:0 txqueuelen:1000
> RX bytes:94205 (91.9 KiB) TX bytes:0 (0.0 B)
>
> lo Link encap:Local Loopback
> inet addr:127.0.0.1 Mask:255.0.0.0
> UP LOOPBACK RUNNING MTU:16436 Metric:1
> RX packets:4 errors:0 dropped:0 overruns:0 frame:0
> TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
> collisions:0 txqueuelen:0
> RX bytes:248 (248.0 B) TX bytes:248 (248.0 B)
>
> sh-3.1# ifconfig eth0.246 hw ether 00:11:22:33:44:55 ifconfig eth0.246 up
> ifconfig: hw: Host name lookup failure
> sh-3.1#
>
>
> Regards,
> Smitha
> Please do not print this email unless it is absolutely necessary.
>
> The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments.
>
> WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email.
>
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> _______________________________________________
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* Re: [PATCH] KVM: Move gfn_to_memslot() to kvm_host.h
From: Avi Kivity @ 2012-01-02 16:13 UTC (permalink / raw)
To: Alexander Graf; +Cc: linuxppc-dev, Paul Mackerras, kvm, kvm-ppc
In-Reply-To: <6918CBBE-19AF-4323-BFE7-0F8739E32008@suse.de>
On 01/02/2012 05:23 PM, Alexander Graf wrote:
> > Or we could move the implementation into a header file, with an extra __
> > prefix, and have the C stubs call those inlines, so we have exactly on
> > instantiation. Your real mode code can then call the inlines.
>
> I like this version. That way everyone should be happy :)
Pretty much how everything is solved. Pile up another layer of
indirection (compile-time here), everyone's happy, and the code bloats.
(I'm not against this, just grumpy)
--
error compiling committee.c: too many arguments to function
^ permalink raw reply
* Re: [PATCH 1/2][v2] Integrated Flash Controller support
From: Scott Wood @ 2012-01-02 17:31 UTC (permalink / raw)
To: dpervushin; +Cc: Liu Shuo, linuxppc-dev, Prabhakar Kushwaha
In-Reply-To: <1325079052.12535.22.camel@mrki-medvjed.diimka.lan>
On 12/28/2011 07:30 AM, dmitry pervushin wrote:
> If you're using memory-mapped structure, shouldn't it be announced with
> __attribute__(packed) ?
Why? We know this isn't going to be compiled on some strange ABI where
a struct with nothing but u32 gets padding. __attribute__((packed))
also tells GCC the struct itself could be unaligned which is not true.
-Scott
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