* Re: [PATCH 2/2] Kbuild: Use dtc's -d (dependency) option
From: Shawn Guo @ 2012-01-10 3:12 UTC (permalink / raw)
To: Stephen Warren
Cc: Michal Marek, Jon Loeliger, Russell King, linux-c6x-dev,
Aurelien Jacquiot, microblaze-uclinux, Devicetree Discuss,
linux-kbuild, linux-kernel, Rob Herring, linux, linuxppc-dev,
linux-arm-kernel, David Gibson
In-Reply-To: <1326134295-15547-2-git-send-email-swarren@nvidia.com>
On Mon, Jan 09, 2012 at 11:38:15AM -0700, Stephen Warren wrote:
> This hooks dtc into Kbuild's dependency system.
>
> Thus, for example, "make dtbs" will rebuild tegra-harmony.dtb if only
> tegra20.dtsi has changed yet tegra-harmony.dts has not. The previous
> lack of this feature recently caused me to have very confusing "git
> bisect" results.
>
> For ARM, it's obvious what to add to $(targets). I'm not familiar enough
> with other architectures to know what to add there. Powerpc appears to
> already add various .dtb files into $(targets), but the other archs may
> need something added to $(targets) to work.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Though I did not look into the patches deeply, I know the problem very
well and it annoys me a lot. It's great that we have patches to fix
it, so
Acked-by: Shawn Guo <shawn.guo@linaro.org>
--
Regards,
Shawn
^ permalink raw reply
* Re: [RFC PATCH 14/16] KVM: PPC: booke: category E.HV (GS-mode) support
From: Alexander Graf @ 2012-01-10 3:11 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <4F0B8B7D.4@freescale.com>
On 10.01.2012, at 01:51, Scott Wood wrote:
> On 01/09/2012 11:46 AM, Alexander Graf wrote:
>>=20
>> On 21.12.2011, at 02:34, Scott Wood wrote:
>>=20
>>> Chips such as e500mc that implement category E.HV in Power ISA 2.06
>>> provide hardware virtualization features, including a new MSR mode =
for
>>> guest state. The guest OS can perform many operations without =
trapping
>>> into the hypervisor, including transitions to and from guest =
userspace.
>>>=20
>>> Since we can use SRR1[GS] to reliably tell whether an exception came =
from
>>> guest state, instead of messing around with IVPR, we use DO_KVM =
similarly
>>> to book3s.
>>=20
>> Is there any benefit of using DO_KVM? I would assume that messing =
with IVPR is faster.
>=20
> Using the GS bit to decide which handler to run means we won't get
> confused if a machine check or critical interrupt happens between
> entering/exiting the guest and updating IVPR (we could use the IS bit
> similarly in PR-mode).
>=20
> This could be supplemented with IVPR (though that will add a few =
cycles
> to guest entry/exit) or some sort of runtime patching (would be more
> coarse-grained, active when any KVM guest exists) to avoid adding
> overhead to traps when KVM is not used, but I'd like to quantify that
> overhead first. It should be much lower than what happens on book3s.
Hrm. Yeah, given that your DO_KVM handler is so much simpler, it might =
make sense to stick with that method. Benchmarks would be useful in the =
long run though.
>=20
>>> Current issues include:
>>> - Machine checks from guest state are not routed to the host =
handler.
>>> - The guest can cause a host oops by executing an emulated =
instruction
>>> in a page that lacks read permission. Existing e500/4xx support =
has
>>> the same problem.
>>=20
>> We solve that in book3s pr by doing
>>=20
>> LAST_INST =3D <known bad value>;
>> PACA->kvm_mode =3D <recover at next inst>;
>> lwz(guest pc);
>> do_more_stuff();
>>=20
>> That way when an exception occurs at lwz() the DO_KVM handler checks =
that we're in kvm mode "recover" which does basically srr0+=3D4; rfi;.
>=20
> I was thinking we'd check ESR[EPID] or SRR1[IS] as appropriate, and
> treat it as a kernel fault (search exception table) -- but this works
> too and is a bit cleaner (could be other uses of external pid), at the
> expense of a couple extra instructions in the emulation path (but
> probably a slightly faster host TLB handler).
>=20
> The check wouldn't go in DO_KVM, though, since on bookehv that only
> deals with diverting flow when xSRR1[GS] is set, which wouldn't be the
> case here.
Yup, not sure where you'd put the check, as it'd slow down normal =
operation too. Hrm.
>=20
>>> @@ -243,16 +324,20 @@ static int kvmppc_booke_irqprio_deliver(struct =
kvm_vcpu *vcpu,
>>> case BOOKE_IRQPRIO_AP_UNAVAIL:
>>> case BOOKE_IRQPRIO_ALIGNMENT:
>>> allowed =3D 1;
>>> - msr_mask =3D MSR_CE|MSR_ME|MSR_DE;
>>> + msr_mask =3D MSR_GS | MSR_CE | MSR_ME | MSR_DE;
>>=20
>> No need to do this. You already force MSR_GS in set_msr();
>=20
> OK. This was here since before set_msr() started doing that. :-)
>=20
>>> + if (!current->thread.kvm_vcpu) {
>>> + WARN(1, "no vcpu\n");
>>> + return -EPERM;
>>> + }
>>=20
>> Huh?
>=20
> Oops, leftover debugging.
>=20
>>> +static int emulation_exit(struct kvm_run *run, struct kvm_vcpu =
*vcpu)
>>> +{
>>> + enum emulation_result er;
>>> +
>>> + er =3D kvmppc_emulate_instruction(run, vcpu);
>>> + switch (er) {
>>> + case EMULATE_DONE:
>>> + /* don't overwrite subtypes, just account kvm_stats */
>>> + kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
>>> + /* Future optimization: only reload non-volatiles if
>>> + * they were actually modified by emulation. */
>>> + return RESUME_GUEST_NV;
>>> +
>>> + case EMULATE_DO_DCR:
>>> + run->exit_reason =3D KVM_EXIT_DCR;
>>> + return RESUME_HOST;
>>> +
>>> + case EMULATE_FAIL:
>>> + /* XXX Deliver Program interrupt to guest. */
>>> + printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
>>> + __func__, vcpu->arch.regs.nip, =
vcpu->arch.last_inst);
>>=20
>> This should be throttled, otherwise the guest can spam our logs.
>=20
> Yes it should, but I'm just moving the code here.
Yeah, only realized this later. Maybe next time (not for this patch set, =
next time you're sending something) just extract these mechanical parts, =
so it's easier to review the pieces where code actually changes :).
>=20
>>> + /* For debugging, encode the failing instruction and
>>> + * report it to userspace. */
>>> + run->hw.hardware_exit_reason =3D ~0ULL << 32;
>>> + run->hw.hardware_exit_reason |=3D vcpu->arch.last_inst;
>>=20
>>=20
>> I'm fairly sure you want to fix this :)
>=20
> Likewise, that's what booke.c already does. What should it do =
instead?
This is what book3s does:
case EMULATE_FAIL:
printk(KERN_CRIT "%s: emulation at %lx failed =
(%08x)\n",
__func__, kvmppc_get_pc(vcpu), =
kvmppc_get_last_inst(vcpu));
kvmppc_core_queue_program(vcpu, flags);
r =3D RESUME_GUEST;
which also doesn't throttle the printk, but I think injecting a program =
fault into the guest is the most sensible thing to do if we don't know =
what the instruction is supposed to do. Best case we get an oops inside =
the guest telling us what broke :).
>=20
>> /**
>>> * kvmppc_handle_exit
>>> *
>>> @@ -374,12 +530,39 @@ out:
>>> int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
>>> unsigned int exit_nr)
>>> {
>>> - enum emulation_result er;
>>> int r =3D RESUME_HOST;
>>>=20
>>> /* update before a new last_exit_type is rewritten */
>>> kvmppc_update_timing_stats(vcpu);
>>>=20
>>> + /*
>>> + * If we actually care, we could copy MSR, DEAR, and ESR to =
regs,
>>> + * insert an appropriate trap number, etc.
>>> + *
>>> + * Seems like a waste of cycles for something that should only =
matter
>>> + * to someone using sysrq-t/p or similar host kernel debug =
facility.
>>> + * We have other debug facilities to get that information from a
>>> + * guest through userspace.
>>> + */
>>> + switch (exit_nr) {
>>> + case BOOKE_INTERRUPT_EXTERNAL:
>>> + do_IRQ(&vcpu->arch.regs);
>>=20
>> Ah, so that's what you want to use regs for. So is having a pt_regs
>> struct that only contains useful register values in half its fields
>> any useful here? Or could we keep control of the registers ourselves,
>> enabling us to maybe one day optimize things more.
>=20
> I think it contains enough to be useful for debugging code such as =
sysrq
> and tracers, and as noted in the comment we could copy the rest if we
> care enough. MSR might be worth copying.
>=20
> It will eventually be used for machine checks as well, which I'd like =
to
> hand reasonable register state to, at least for GPRs, LR, and PC.
>=20
> If there's a good enough performance reason, we could just copy
> everything over for machine checks and pass NULL to do_IRQ (I think it
> can take this -- a dummy regs struct if not), but it seems premature =
at
> the moment unless the switch already causes measured performance loss
> (cache utilization?).
I'm definitely not concerned about performance, but complexity and =
uniqueness. With the pt_regs struct, we have a bunch of fields in the =
vcpu that are there, but unused. I find that situation pretty confusing.
So yes, I would definitely prefer to copy registers during MC and keep =
the registers where they are today - unless there are SPRs for them of =
course.
Imagine we'd one day want to share GPRs with user space through the =
kvm_run structure (see the s390 patches on the ML for this). I really =
wouldn't want to make pt_regs part of our userspace ABI.
>=20
>>> @@ -387,30 +570,56 @@ int kvmppc_handle_exit(struct kvm_run *run, =
struct kvm_vcpu *vcpu,
>>>=20
>>> switch (exit_nr) {
>>> case BOOKE_INTERRUPT_MACHINE_CHECK:
>>> - printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
>>> - kvmppc_dump_vcpu(vcpu);
>>> - r =3D RESUME_HOST;
>>> + kvm_resched(vcpu);
>>> + r =3D RESUME_GUEST;
>>=20
>> huh?
>=20
> Patch shuffling accident -- this belongs with a later patch that =
invokes
> the host machine check handler similar to what is done with do_IRQ().
> The host machine check handler needs some work first, though.
>=20
>>> break;
>>>=20
>>> case BOOKE_INTERRUPT_EXTERNAL:
>>> kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
>>> - if (need_resched())
>>> - cond_resched();
>>> + kvm_resched(vcpu);
>>=20
>> Why are we explicit about the resched? On book3s I just call =
kvm_resched(vcpu) before the switch().
>=20
> There are a few exit types where we don't currently do the resched -- =
if
> they're all bugs or don't-cares, we could move it out of the switch.
>=20
> We probably should defer the check until after we've disabled
> interrupts, similar to signals -- even if we didn't exit for an
> interrupt, we could have received one after enabling them.
Yup. I just don't think you can call resched() with interrupts disabled, =
so a bit cleverness is probably required here.
>=20
>>> + if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
>>> + /* The guest TLB had a mapping, but the shadow =
TLB
>>> + * didn't. This could be because:
>>> + * a) the entry is mapping the host kernel, or
>>> + * b) the guest used a large mapping which we're =
faking
>>> + * Either way, we need to satisfy the fault =
without
>>> + * invoking the guest. */
>>> + kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
>>> + } else {
>>> + /* Guest mapped and leaped at non-RAM! */
>>> + kvmppc_booke_queue_irqprio(vcpu,
>>> + =
BOOKE_IRQPRIO_MACHINE_CHECK);
>>=20
>> Are you sure? Couldn't this also be MMIO? That doesn't really improve =
the situation as executing from MMIO is tricky with the KVM model, but =
it's not necessarily bad. Oh well, I guess we'll have to do something =
and throwing an #MC isn't all that ugly.
>=20
> I think I asked you about executing from MMIO once, and you said it
> wasn't supported even in straight QEMU. Have things changed?
Yeah, I talked to Anthony about that part and apparently the QEMU design =
does support execution from MMIO. But don't worry about it for now. I =
don't think we'll really have guest OSs doing this. And if they do, we =
can worry about it then.
>=20
>>> diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
>>> index 05d1d99..d53bcf2 100644
>>> --- a/arch/powerpc/kvm/booke.h
>>> +++ b/arch/powerpc/kvm/booke.h
>>> @@ -48,7 +48,20 @@
>>> #define BOOKE_IRQPRIO_PERFORMANCE_MONITOR 19
>>> /* Internal pseudo-irqprio for level triggered externals */
>>> #define BOOKE_IRQPRIO_EXTERNAL_LEVEL 20
>>> -#define BOOKE_IRQPRIO_MAX 20
>>> +#define BOOKE_IRQPRIO_DBELL 21
>>> +#define BOOKE_IRQPRIO_DBELL_CRIT 22
>>> +#define BOOKE_IRQPRIO_MAX 23
>>=20
>> So was MAX wrong before or is it too big now?
>=20
> MAX is just a marker for how many IRQPRIOs we have, not any sort of
> external limit. This patch adds new IRQPRIOs, so MAX goes up.
>=20
> The actual limit is the number of bits in a long.
Yes, and before the highest value was 20 with MAX being 20, now the =
highest value is 22 with MAX being 23. Either MAX =3D=3D highest number =
or MAX =3D=3D highest number + 1, but you're changing the semantics of =
MAX here. Maybe it was wrong before, I don't know, hence I'm asking :).
>=20
>>> + .if \flags & NEED_EMU
>>> + lwz r9, VCPU_KVM(r4)
>>=20
>> writing r9
>>=20
>>> + .endif
>>> +
>>> +#ifdef CONFIG_KVM_EXIT_TIMING
>>> + /* save exit time */
>>> +1: mfspr r7, SPRN_TBRU
>>> + mfspr r8, SPRN_TBRL
>>> + mfspr r9, SPRN_TBRU
>>=20
>> overwriting r9 again?
>=20
> Oops. It's RFC for a reason. :-)
>=20
>>> +#ifndef CONFIG_64BIT
>>=20
>> Double negation is always hard to read. Please reverse the ifdef :)
>=20
> OK.
>=20
>>> +lightweight_exit:
>>> + PPC_STL r2, HOST_R2(r1)
>>> +
>>> + mfspr r3, SPRN_PID
>>> + stw r3, VCPU_HOST_PID(r4)
>>> + lwz r3, VCPU_GUEST_PID(r4)
>>> + mtspr SPRN_PID, r3
>>> +
>>> + /* Save vcpu pointer for the exception handlers
>>> + * must be done before loading guest r2.
>>> + */
>>> +// SET_VCPU(r4)
>>=20
>> hm?
>=20
> Can just be removed, it's handled in booke's vcpu load/put.
>=20
>>> + lwz r6, (VCPU_SHARED_MAS2 + 4)(r11)
>>> +#else
>>> + ld r6, (VCPU_SHARED_MAS2)(r11)
>>> +#endif
>>> + lwz r7, VCPU_SHARED_MAS7_3+4(r11)
>>> + lwz r8, VCPU_SHARED_MAS4(r11)
>>> + mtspr SPRN_MAS0, r3
>>> + mtspr SPRN_MAS1, r5
>>> + mtspr SPRN_MAS2, r6
>>> + mtspr SPRN_MAS3, r7
>>> + mtspr SPRN_MAS4, r8
>>> + lwz r3, VCPU_SHARED_MAS6(r11)
>>> + lwz r5, VCPU_SHARED_MAS7_3+0(r11)
>>> + mtspr SPRN_MAS6, r3
>>> + mtspr SPRN_MAS7, r5
>>> + /* Disable MAS register updates via exception */
>>> + mfspr r3, SPRN_EPCR
>>> + oris r3, r3, SPRN_EPCR_DMIUH@h
>>> + mtspr SPRN_EPCR, r3
>>=20
>> Shouldn't this happen before you set the MAS registers? :)
>=20
> Yes (though we really shouldn't be getting a TLB miss here, at least =
on
> e500mc).
Yeah, but the way it's now it gives you a false feeling of security :)
>=20
>>> + /* Load some guest volatiles. */
>>> + PPC_LL r3, VCPU_LR(r4)
>>> + PPC_LL r5, VCPU_XER(r4)
>>> + PPC_LL r6, VCPU_CTR(r4)
>>> + PPC_LL r7, VCPU_CR(r4)
>>> + PPC_LL r8, VCPU_PC(r4)
>>> +#ifndef CONFIG_64BIT
>>> + lwz r9, (VCPU_SHARED_MSR + 4)(r11)
>>> +#else
>>> + ld r9, (VCPU_SHARED_MSR)(r11)
>>> +#endif
>>> + PPC_LL r0, VCPU_GPR(r0)(r4)
>>> + PPC_LL r1, VCPU_GPR(r1)(r4)
>>> + PPC_LL r2, VCPU_GPR(r2)(r4)
>>> + PPC_LL r10, VCPU_GPR(r10)(r4)
>>> + PPC_LL r11, VCPU_GPR(r11)(r4)
>>> + PPC_LL r12, VCPU_GPR(r12)(r4)
>>> + PPC_LL r13, VCPU_GPR(r13)(r4)
>>> + mtlr r3
>>> + mtxer r5
>>> + mtctr r6
>>> + mtcr r7
>>> + mtsrr0 r8
>>> + mtsrr1 r9
>>=20
>> Are you sure this should be shared->msr, not shadow_msr?
>=20
> Yes, we don't use shadow_msr on bookehv. I'll add a comment in the
> struct definition as discussed in the other thread, as well as other
> areas where there are subtle differences between PR-mode and GS-mode.
Thanks!
Alex
^ permalink raw reply
* Re: [PATCH 2/2][v2] mtd/nand: Fix IFC driver to support 2K NAND page
From: Scott Wood @ 2012-01-10 1:10 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: linux-mtd, linuxppc-dev, Poonam Aggrwal
In-Reply-To: <1326111866-13120-1-git-send-email-prabhakar@freescale.com>
On 01/09/2012 06:24 AM, Prabhakar Kushwaha wrote:
> 1) OOB area should be updated irrespective of NAND page size. Earlier it was
> updated only for 512byte NAND page.
>
> 2) During OOB update fbcr should be equal to OOB size.
>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git (branch next)
>
> This patch is created on top of IFC driver patch (already floated in mailing
> list). Please find their link:
> http://patchwork.ozlabs.org/patch/133315/
> http://patchwork.ozlabs.org/patch/133316/
Looks good.
-Scott
^ permalink raw reply
* Re: [PATCH 1/2][v2] mtd/nand:Fix wrong address read in is_blank()
From: Scott Wood @ 2012-01-10 1:07 UTC (permalink / raw)
To: Prabhakar Kushwaha; +Cc: linux-mtd, linuxppc-dev, Poonam Aggrwal
In-Reply-To: <1326111847-13085-1-git-send-email-prabhakar@freescale.com>
On 01/09/2012 06:24 AM, Prabhakar Kushwaha wrote:
> @@ -215,12 +215,15 @@ static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
> static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
> u32 *eccstat, unsigned int bufnum)
> {
> + struct nand_chip *chip = mtd->priv;
> + int bufperpage = mtd->writesize / chip->ecc.size;
> + int eccbuf_num = bufnum + (bufnum / bufperpage) * bufperpage;
This is unnecessarily complicated (and introduces two more, dependent,
runtime divisions). I don't think there are any changes required in
this function. You're awkwardly compensating for the fact that the
caller hasn't been updated for the new definition of bufnum.
bufperpage used in fsl_ifc_run_command should be doubled to account for
the OOB buffers. We should probably rename it from "buf" to something
else (chunk? subpage?) to avoid confusion with bufnum_mask, which refers
to page-sized buffers.
> u32 reg = eccstat[bufnum / 4];
> int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
>
> if (errors == 15) { /* uncorrectable */
> /* Blank pages fail hw ECC checks */
> - if (is_blank(mtd, bufnum))
> + if (is_blank(mtd, eccbuf_num))
> return 1;
>
> /*
> @@ -273,7 +276,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
> dev_err(priv->dev, "NAND Flash Write Protect Error\n");
>
> if (nctrl->eccread) {
> - int bufperpage = mtd->writesize / 512;
> + int bufperpage = mtd->writesize / chip->ecc.size;
> int bufnum = (nctrl->page & priv->bufnum_mask) * bufperpage;
> int bufnum_end = bufnum + bufperpage - 1;
>
Again, please calculate bufperpage (chunksperpage? subsperpage? perbuf?)
at driver init, as is done with bufnum_mask.
-Scott
^ permalink raw reply
* Re: [RFC PATCH 14/16] KVM: PPC: booke: category E.HV (GS-mode) support
From: Scott Wood @ 2012-01-10 0:51 UTC (permalink / raw)
To: Alexander Graf; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <1A656B06-E290-4B75-8F98-F8FAB8B817F1@suse.de>
On 01/09/2012 11:46 AM, Alexander Graf wrote:
>
> On 21.12.2011, at 02:34, Scott Wood wrote:
>
>> Chips such as e500mc that implement category E.HV in Power ISA 2.06
>> provide hardware virtualization features, including a new MSR mode for
>> guest state. The guest OS can perform many operations without trapping
>> into the hypervisor, including transitions to and from guest userspace.
>>
>> Since we can use SRR1[GS] to reliably tell whether an exception came from
>> guest state, instead of messing around with IVPR, we use DO_KVM similarly
>> to book3s.
>
> Is there any benefit of using DO_KVM? I would assume that messing with IVPR is faster.
Using the GS bit to decide which handler to run means we won't get
confused if a machine check or critical interrupt happens between
entering/exiting the guest and updating IVPR (we could use the IS bit
similarly in PR-mode).
This could be supplemented with IVPR (though that will add a few cycles
to guest entry/exit) or some sort of runtime patching (would be more
coarse-grained, active when any KVM guest exists) to avoid adding
overhead to traps when KVM is not used, but I'd like to quantify that
overhead first. It should be much lower than what happens on book3s.
>> Current issues include:
>> - Machine checks from guest state are not routed to the host handler.
>> - The guest can cause a host oops by executing an emulated instruction
>> in a page that lacks read permission. Existing e500/4xx support has
>> the same problem.
>
> We solve that in book3s pr by doing
>
> LAST_INST = <known bad value>;
> PACA->kvm_mode = <recover at next inst>;
> lwz(guest pc);
> do_more_stuff();
>
> That way when an exception occurs at lwz() the DO_KVM handler checks that we're in kvm mode "recover" which does basically srr0+=4; rfi;.
I was thinking we'd check ESR[EPID] or SRR1[IS] as appropriate, and
treat it as a kernel fault (search exception table) -- but this works
too and is a bit cleaner (could be other uses of external pid), at the
expense of a couple extra instructions in the emulation path (but
probably a slightly faster host TLB handler).
The check wouldn't go in DO_KVM, though, since on bookehv that only
deals with diverting flow when xSRR1[GS] is set, which wouldn't be the
case here.
>> @@ -243,16 +324,20 @@ static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
>> case BOOKE_IRQPRIO_AP_UNAVAIL:
>> case BOOKE_IRQPRIO_ALIGNMENT:
>> allowed = 1;
>> - msr_mask = MSR_CE|MSR_ME|MSR_DE;
>> + msr_mask = MSR_GS | MSR_CE | MSR_ME | MSR_DE;
>
> No need to do this. You already force MSR_GS in set_msr();
OK. This was here since before set_msr() started doing that. :-)
>> + if (!current->thread.kvm_vcpu) {
>> + WARN(1, "no vcpu\n");
>> + return -EPERM;
>> + }
>
> Huh?
Oops, leftover debugging.
>> +static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
>> +{
>> + enum emulation_result er;
>> +
>> + er = kvmppc_emulate_instruction(run, vcpu);
>> + switch (er) {
>> + case EMULATE_DONE:
>> + /* don't overwrite subtypes, just account kvm_stats */
>> + kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
>> + /* Future optimization: only reload non-volatiles if
>> + * they were actually modified by emulation. */
>> + return RESUME_GUEST_NV;
>> +
>> + case EMULATE_DO_DCR:
>> + run->exit_reason = KVM_EXIT_DCR;
>> + return RESUME_HOST;
>> +
>> + case EMULATE_FAIL:
>> + /* XXX Deliver Program interrupt to guest. */
>> + printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
>> + __func__, vcpu->arch.regs.nip, vcpu->arch.last_inst);
>
> This should be throttled, otherwise the guest can spam our logs.
Yes it should, but I'm just moving the code here.
>> + /* For debugging, encode the failing instruction and
>> + * report it to userspace. */
>> + run->hw.hardware_exit_reason = ~0ULL << 32;
>> + run->hw.hardware_exit_reason |= vcpu->arch.last_inst;
>
>
> I'm fairly sure you want to fix this :)
Likewise, that's what booke.c already does. What should it do instead?
> /**
>> * kvmppc_handle_exit
>> *
>> @@ -374,12 +530,39 @@ out:
>> int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
>> unsigned int exit_nr)
>> {
>> - enum emulation_result er;
>> int r = RESUME_HOST;
>>
>> /* update before a new last_exit_type is rewritten */
>> kvmppc_update_timing_stats(vcpu);
>>
>> + /*
>> + * If we actually care, we could copy MSR, DEAR, and ESR to regs,
>> + * insert an appropriate trap number, etc.
>> + *
>> + * Seems like a waste of cycles for something that should only matter
>> + * to someone using sysrq-t/p or similar host kernel debug facility.
>> + * We have other debug facilities to get that information from a
>> + * guest through userspace.
>> + */
>> + switch (exit_nr) {
>> + case BOOKE_INTERRUPT_EXTERNAL:
>> + do_IRQ(&vcpu->arch.regs);
>
> Ah, so that's what you want to use regs for. So is having a pt_regs
> struct that only contains useful register values in half its fields
> any useful here? Or could we keep control of the registers ourselves,
> enabling us to maybe one day optimize things more.
I think it contains enough to be useful for debugging code such as sysrq
and tracers, and as noted in the comment we could copy the rest if we
care enough. MSR might be worth copying.
It will eventually be used for machine checks as well, which I'd like to
hand reasonable register state to, at least for GPRs, LR, and PC.
If there's a good enough performance reason, we could just copy
everything over for machine checks and pass NULL to do_IRQ (I think it
can take this -- a dummy regs struct if not), but it seems premature at
the moment unless the switch already causes measured performance loss
(cache utilization?).
>> @@ -387,30 +570,56 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
>>
>> switch (exit_nr) {
>> case BOOKE_INTERRUPT_MACHINE_CHECK:
>> - printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
>> - kvmppc_dump_vcpu(vcpu);
>> - r = RESUME_HOST;
>> + kvm_resched(vcpu);
>> + r = RESUME_GUEST;
>
> huh?
Patch shuffling accident -- this belongs with a later patch that invokes
the host machine check handler similar to what is done with do_IRQ().
The host machine check handler needs some work first, though.
>> break;
>>
>> case BOOKE_INTERRUPT_EXTERNAL:
>> kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
>> - if (need_resched())
>> - cond_resched();
>> + kvm_resched(vcpu);
>
> Why are we explicit about the resched? On book3s I just call kvm_resched(vcpu) before the switch().
There are a few exit types where we don't currently do the resched -- if
they're all bugs or don't-cares, we could move it out of the switch.
We probably should defer the check until after we've disabled
interrupts, similar to signals -- even if we didn't exit for an
interrupt, we could have received one after enabling them.
>> + if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
>> + /* The guest TLB had a mapping, but the shadow TLB
>> + * didn't. This could be because:
>> + * a) the entry is mapping the host kernel, or
>> + * b) the guest used a large mapping which we're faking
>> + * Either way, we need to satisfy the fault without
>> + * invoking the guest. */
>> + kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
>> + } else {
>> + /* Guest mapped and leaped at non-RAM! */
>> + kvmppc_booke_queue_irqprio(vcpu,
>> + BOOKE_IRQPRIO_MACHINE_CHECK);
>
> Are you sure? Couldn't this also be MMIO? That doesn't really improve the situation as executing from MMIO is tricky with the KVM model, but it's not necessarily bad. Oh well, I guess we'll have to do something and throwing an #MC isn't all that ugly.
I think I asked you about executing from MMIO once, and you said it
wasn't supported even in straight QEMU. Have things changed?
>> diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
>> index 05d1d99..d53bcf2 100644
>> --- a/arch/powerpc/kvm/booke.h
>> +++ b/arch/powerpc/kvm/booke.h
>> @@ -48,7 +48,20 @@
>> #define BOOKE_IRQPRIO_PERFORMANCE_MONITOR 19
>> /* Internal pseudo-irqprio for level triggered externals */
>> #define BOOKE_IRQPRIO_EXTERNAL_LEVEL 20
>> -#define BOOKE_IRQPRIO_MAX 20
>> +#define BOOKE_IRQPRIO_DBELL 21
>> +#define BOOKE_IRQPRIO_DBELL_CRIT 22
>> +#define BOOKE_IRQPRIO_MAX 23
>
> So was MAX wrong before or is it too big now?
MAX is just a marker for how many IRQPRIOs we have, not any sort of
external limit. This patch adds new IRQPRIOs, so MAX goes up.
The actual limit is the number of bits in a long.
>> + .if \flags & NEED_EMU
>> + lwz r9, VCPU_KVM(r4)
>
> writing r9
>
>> + .endif
>> +
>> +#ifdef CONFIG_KVM_EXIT_TIMING
>> + /* save exit time */
>> +1: mfspr r7, SPRN_TBRU
>> + mfspr r8, SPRN_TBRL
>> + mfspr r9, SPRN_TBRU
>
> overwriting r9 again?
Oops. It's RFC for a reason. :-)
>> +#ifndef CONFIG_64BIT
>
> Double negation is always hard to read. Please reverse the ifdef :)
OK.
>> +lightweight_exit:
>> + PPC_STL r2, HOST_R2(r1)
>> +
>> + mfspr r3, SPRN_PID
>> + stw r3, VCPU_HOST_PID(r4)
>> + lwz r3, VCPU_GUEST_PID(r4)
>> + mtspr SPRN_PID, r3
>> +
>> + /* Save vcpu pointer for the exception handlers
>> + * must be done before loading guest r2.
>> + */
>> +// SET_VCPU(r4)
>
> hm?
Can just be removed, it's handled in booke's vcpu load/put.
>> + lwz r6, (VCPU_SHARED_MAS2 + 4)(r11)
>> +#else
>> + ld r6, (VCPU_SHARED_MAS2)(r11)
>> +#endif
>> + lwz r7, VCPU_SHARED_MAS7_3+4(r11)
>> + lwz r8, VCPU_SHARED_MAS4(r11)
>> + mtspr SPRN_MAS0, r3
>> + mtspr SPRN_MAS1, r5
>> + mtspr SPRN_MAS2, r6
>> + mtspr SPRN_MAS3, r7
>> + mtspr SPRN_MAS4, r8
>> + lwz r3, VCPU_SHARED_MAS6(r11)
>> + lwz r5, VCPU_SHARED_MAS7_3+0(r11)
>> + mtspr SPRN_MAS6, r3
>> + mtspr SPRN_MAS7, r5
>> + /* Disable MAS register updates via exception */
>> + mfspr r3, SPRN_EPCR
>> + oris r3, r3, SPRN_EPCR_DMIUH@h
>> + mtspr SPRN_EPCR, r3
>
> Shouldn't this happen before you set the MAS registers? :)
Yes (though we really shouldn't be getting a TLB miss here, at least on
e500mc).
>> + /* Load some guest volatiles. */
>> + PPC_LL r3, VCPU_LR(r4)
>> + PPC_LL r5, VCPU_XER(r4)
>> + PPC_LL r6, VCPU_CTR(r4)
>> + PPC_LL r7, VCPU_CR(r4)
>> + PPC_LL r8, VCPU_PC(r4)
>> +#ifndef CONFIG_64BIT
>> + lwz r9, (VCPU_SHARED_MSR + 4)(r11)
>> +#else
>> + ld r9, (VCPU_SHARED_MSR)(r11)
>> +#endif
>> + PPC_LL r0, VCPU_GPR(r0)(r4)
>> + PPC_LL r1, VCPU_GPR(r1)(r4)
>> + PPC_LL r2, VCPU_GPR(r2)(r4)
>> + PPC_LL r10, VCPU_GPR(r10)(r4)
>> + PPC_LL r11, VCPU_GPR(r11)(r4)
>> + PPC_LL r12, VCPU_GPR(r12)(r4)
>> + PPC_LL r13, VCPU_GPR(r13)(r4)
>> + mtlr r3
>> + mtxer r5
>> + mtctr r6
>> + mtcr r7
>> + mtsrr0 r8
>> + mtsrr1 r9
>
> Are you sure this should be shared->msr, not shadow_msr?
Yes, we don't use shadow_msr on bookehv. I'll add a comment in the
struct definition as discussed in the other thread, as well as other
areas where there are subtle differences between PR-mode and GS-mode.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc: Fix RCU idle and hcall tracing
From: Paul E. McKenney @ 2012-01-10 0:43 UTC (permalink / raw)
To: Anton Blanchard; +Cc: paulus, linuxppc-dev
In-Reply-To: <20120110112915.387e8b1c@kryten>
On Tue, Jan 10, 2012 at 11:29:15AM +1100, Anton Blanchard wrote:
>
> Tracepoints should not be called inside an rcu_idle_enter/rcu_idle_exit
> region. Since pSeries calls H_CEDE in the idle loop, we were violating
> this rule.
>
> commit a7b152d5342c (powerpc: Tell RCU about idle after hcall tracing)
> tried to work around it by delaying the rcu_idle_enter until after we
> called the hcall tracepoint, but there are a number of issues with it.
>
> The hcall tracepoint trampoline code is called conditionally when the
> tracepoint is enabled. If the tracepoint is not enabled we never call
> rcu_idle_enter. The idle_uses_rcu check was also done at compile time
> which breaks multiplatform builds.
>
> The simple fix is to avoid tracing H_CEDE and rely on other tracepoints
> and the hypervisor dispatch trace log to work out if we called H_CEDE.
>
> This fixes a hang during boot on pSeries.
>
> Signed-off-by: Anton Blanchard <anton@samba.org>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> ---
>
> Index: linux-build/arch/powerpc/kernel/idle.c
> ===================================================================
> --- linux-build.orig/arch/powerpc/kernel/idle.c 2012-01-10 11:07:22.091615183 +1100
> +++ linux-build/arch/powerpc/kernel/idle.c 2012-01-10 11:07:57.172264229 +1100
> @@ -50,12 +50,6 @@ static int __init powersave_off(char *ar
> }
> __setup("powersave=off", powersave_off);
>
> -#if defined(CONFIG_PPC_PSERIES) && defined(CONFIG_TRACEPOINTS)
> -static const bool idle_uses_rcu = 1;
> -#else
> -static const bool idle_uses_rcu;
> -#endif
> -
> /*
> * The body of the idle task.
> */
> @@ -67,8 +61,7 @@ void cpu_idle(void)
> set_thread_flag(TIF_POLLING_NRFLAG);
> while (1) {
> tick_nohz_idle_enter();
> - if (!idle_uses_rcu)
> - rcu_idle_enter();
> + rcu_idle_enter();
>
> while (!need_resched() && !cpu_should_die()) {
> ppc64_runlatch_off();
> @@ -106,8 +99,7 @@ void cpu_idle(void)
>
> HMT_medium();
> ppc64_runlatch_on();
> - if (!idle_uses_rcu)
> - rcu_idle_exit();
> + rcu_idle_exit();
> tick_nohz_idle_exit();
> preempt_enable_no_resched();
> if (cpu_should_die())
> Index: linux-build/arch/powerpc/platforms/pseries/lpar.c
> ===================================================================
> --- linux-build.orig/arch/powerpc/platforms/pseries/lpar.c 2012-01-10 11:07:22.079614961 +1100
> +++ linux-build/arch/powerpc/platforms/pseries/lpar.c 2012-01-10 11:16:55.710226236 +1100
> @@ -546,6 +546,13 @@ void __trace_hcall_entry(unsigned long o
> unsigned long flags;
> unsigned int *depth;
>
> + /*
> + * We cannot call tracepoints inside RCU idle regions which
> + * means we must not trace H_CEDE.
> + */
> + if (opcode == H_CEDE)
> + return;
> +
> local_irq_save(flags);
>
> depth = &__get_cpu_var(hcall_trace_depth);
> @@ -556,8 +563,6 @@ void __trace_hcall_entry(unsigned long o
> (*depth)++;
> preempt_disable();
> trace_hcall_entry(opcode, args);
> - if (opcode == H_CEDE)
> - rcu_idle_enter();
> (*depth)--;
>
> out:
> @@ -570,6 +575,9 @@ void __trace_hcall_exit(long opcode, uns
> unsigned long flags;
> unsigned int *depth;
>
> + if (opcode == H_CEDE)
> + return;
> +
> local_irq_save(flags);
>
> depth = &__get_cpu_var(hcall_trace_depth);
> @@ -578,8 +586,6 @@ void __trace_hcall_exit(long opcode, uns
> goto out;
>
> (*depth)++;
> - if (opcode == H_CEDE)
> - rcu_idle_exit();
> trace_hcall_exit(opcode, retval, retbuf);
> preempt_enable();
> (*depth)--;
>
^ permalink raw reply
* [PATCH] powerpc: Fix RCU idle and hcall tracing
From: Anton Blanchard @ 2012-01-10 0:29 UTC (permalink / raw)
To: benh, paulus, paulmck; +Cc: linuxppc-dev
Tracepoints should not be called inside an rcu_idle_enter/rcu_idle_exit
region. Since pSeries calls H_CEDE in the idle loop, we were violating
this rule.
commit a7b152d5342c (powerpc: Tell RCU about idle after hcall tracing)
tried to work around it by delaying the rcu_idle_enter until after we
called the hcall tracepoint, but there are a number of issues with it.
The hcall tracepoint trampoline code is called conditionally when the
tracepoint is enabled. If the tracepoint is not enabled we never call
rcu_idle_enter. The idle_uses_rcu check was also done at compile time
which breaks multiplatform builds.
The simple fix is to avoid tracing H_CEDE and rely on other tracepoints
and the hypervisor dispatch trace log to work out if we called H_CEDE.
This fixes a hang during boot on pSeries.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: linux-build/arch/powerpc/kernel/idle.c
===================================================================
--- linux-build.orig/arch/powerpc/kernel/idle.c 2012-01-10 11:07:22.091615183 +1100
+++ linux-build/arch/powerpc/kernel/idle.c 2012-01-10 11:07:57.172264229 +1100
@@ -50,12 +50,6 @@ static int __init powersave_off(char *ar
}
__setup("powersave=off", powersave_off);
-#if defined(CONFIG_PPC_PSERIES) && defined(CONFIG_TRACEPOINTS)
-static const bool idle_uses_rcu = 1;
-#else
-static const bool idle_uses_rcu;
-#endif
-
/*
* The body of the idle task.
*/
@@ -67,8 +61,7 @@ void cpu_idle(void)
set_thread_flag(TIF_POLLING_NRFLAG);
while (1) {
tick_nohz_idle_enter();
- if (!idle_uses_rcu)
- rcu_idle_enter();
+ rcu_idle_enter();
while (!need_resched() && !cpu_should_die()) {
ppc64_runlatch_off();
@@ -106,8 +99,7 @@ void cpu_idle(void)
HMT_medium();
ppc64_runlatch_on();
- if (!idle_uses_rcu)
- rcu_idle_exit();
+ rcu_idle_exit();
tick_nohz_idle_exit();
preempt_enable_no_resched();
if (cpu_should_die())
Index: linux-build/arch/powerpc/platforms/pseries/lpar.c
===================================================================
--- linux-build.orig/arch/powerpc/platforms/pseries/lpar.c 2012-01-10 11:07:22.079614961 +1100
+++ linux-build/arch/powerpc/platforms/pseries/lpar.c 2012-01-10 11:16:55.710226236 +1100
@@ -546,6 +546,13 @@ void __trace_hcall_entry(unsigned long o
unsigned long flags;
unsigned int *depth;
+ /*
+ * We cannot call tracepoints inside RCU idle regions which
+ * means we must not trace H_CEDE.
+ */
+ if (opcode == H_CEDE)
+ return;
+
local_irq_save(flags);
depth = &__get_cpu_var(hcall_trace_depth);
@@ -556,8 +563,6 @@ void __trace_hcall_entry(unsigned long o
(*depth)++;
preempt_disable();
trace_hcall_entry(opcode, args);
- if (opcode == H_CEDE)
- rcu_idle_enter();
(*depth)--;
out:
@@ -570,6 +575,9 @@ void __trace_hcall_exit(long opcode, uns
unsigned long flags;
unsigned int *depth;
+ if (opcode == H_CEDE)
+ return;
+
local_irq_save(flags);
depth = &__get_cpu_var(hcall_trace_depth);
@@ -578,8 +586,6 @@ void __trace_hcall_exit(long opcode, uns
goto out;
(*depth)++;
- if (opcode == H_CEDE)
- rcu_idle_exit();
trace_hcall_exit(opcode, retval, retbuf);
preempt_enable();
(*depth)--;
^ permalink raw reply
* Re: [RFC PATCH 15/16] KVM: PPC: booke: standard PPC floating point support
From: Alexander Graf @ 2012-01-09 22:56 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <4F0B700B.7020006@freescale.com>
On 09.01.2012, at 23:54, Scott Wood wrote:
> On 01/09/2012 04:47 PM, Alexander Graf wrote:
>>=20
>> On 09.01.2012, at 23:39, Scott Wood wrote:
>>=20
>>> On 01/09/2012 04:17 PM, Alexander Graf wrote:
>>>>=20
>>>> On 09.01.2012, at 22:48, Scott Wood wrote:
>>>>=20
>>>>> On 01/09/2012 11:48 AM, Alexander Graf wrote:
>>>>>> I'm having a hard time to grasp when shared->msr, shadow_msr and =
regs->msr is used in your code :).
>>>>>=20
>>>>> shadow_msr is the real MSR.
>>>>>=20
>>>>> shared->msr is the guest's view of MSR.
>>>=20
>>> Correction -- this applies to PR-mode (e500v2).
>>>=20
>>> In GS-mode, shadow_msr is not used. The guest sees the real MSR (hw
>>> silently prevents it from modifying certain bits), which gets saved =
on
>>> exit into shared->msr.
>>=20
>> Hrm. Can we maybe #ifdef out shadow_msr on HV then? I'm really =
getting confused with having 3 potential msr variables in the vcpu =
struct.
>=20
> An ifdef would take us further down the road of not being able to
> support both in the same kernel image (not sure whether that's a
> long-term goal -- probably won't happen any time soon with =
e500v2+e500mc
> even disregarding KVM, but maybe it'll be relevant on some other =
chips),
> and in general increase the mess in the struct definition. How about =
a
> comment?
Well, I'd like to make sure we don't accidentally access the wrong =
field. But yes, a comment should be ok.
Alex
^ permalink raw reply
* Re: [RFC PATCH 15/16] KVM: PPC: booke: standard PPC floating point support
From: Scott Wood @ 2012-01-09 22:54 UTC (permalink / raw)
To: Alexander Graf; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <96605829-1BD3-4668-AEB8-7D27775C2868@suse.de>
On 01/09/2012 04:47 PM, Alexander Graf wrote:
>
> On 09.01.2012, at 23:39, Scott Wood wrote:
>
>> On 01/09/2012 04:17 PM, Alexander Graf wrote:
>>>
>>> On 09.01.2012, at 22:48, Scott Wood wrote:
>>>
>>>> On 01/09/2012 11:48 AM, Alexander Graf wrote:
>>>>> I'm having a hard time to grasp when shared->msr, shadow_msr and regs->msr is used in your code :).
>>>>
>>>> shadow_msr is the real MSR.
>>>>
>>>> shared->msr is the guest's view of MSR.
>>
>> Correction -- this applies to PR-mode (e500v2).
>>
>> In GS-mode, shadow_msr is not used. The guest sees the real MSR (hw
>> silently prevents it from modifying certain bits), which gets saved on
>> exit into shared->msr.
>
> Hrm. Can we maybe #ifdef out shadow_msr on HV then? I'm really getting confused with having 3 potential msr variables in the vcpu struct.
An ifdef would take us further down the road of not being able to
support both in the same kernel image (not sure whether that's a
long-term goal -- probably won't happen any time soon with e500v2+e500mc
even disregarding KVM, but maybe it'll be relevant on some other chips),
and in general increase the mess in the struct definition. How about a
comment?
-Scott
^ permalink raw reply
* Re: [RFC PATCH 15/16] KVM: PPC: booke: standard PPC floating point support
From: Alexander Graf @ 2012-01-09 22:47 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <4F0B6C91.1090102@freescale.com>
On 09.01.2012, at 23:39, Scott Wood wrote:
> On 01/09/2012 04:17 PM, Alexander Graf wrote:
>>=20
>> On 09.01.2012, at 22:48, Scott Wood wrote:
>>=20
>>> On 01/09/2012 11:48 AM, Alexander Graf wrote:
>>>>=20
>>>> Do you think it's possible to combine this with the book3s_pr code, =
so we don't duplicate too much here?
>>>=20
>>> book3s_pr is a bit different in that it can trap when the guest sets
>>> MSR[FP].
>>=20
>> Ah, there's no doorbell? So you always have to swap fpu registers? =
You still have to enable it manually when preempting in, right? IIRC =
ppc32 does lazy fpu activation.
>=20
> Right.
>=20
> Preempting in is handled by calling kvmppc_load_guest_fp() (which =
should
> be renamed to be booke-specific, since the semantics are tied to
> booke.c) from kvmppc_core_vcpu_load() in e500mc.c.
Ah, and that one's called on sched_in. All is well then :).
>=20
>>>> I'm having a hard time to grasp when shared->msr, shadow_msr and =
regs->msr is used in your code :).
>>>=20
>>> shadow_msr is the real MSR.
>>>=20
>>> shared->msr is the guest's view of MSR.
>=20
> Correction -- this applies to PR-mode (e500v2).
>=20
> In GS-mode, shadow_msr is not used. The guest sees the real MSR (hw
> silently prevents it from modifying certain bits), which gets saved on
> exit into shared->msr.
Hrm. Can we maybe #ifdef out shadow_msr on HV then? I'm really getting =
confused with having 3 potential msr variables in the vcpu struct.
Alex
^ permalink raw reply
* Re: Mac address in the DT
From: Wolfgang Denk @ 2012-01-09 22:40 UTC (permalink / raw)
To: smitha.vanga; +Cc: scottwood, linuxppc-dev
In-Reply-To: <40631E9A2581F14BA60888C87A76A1FE01D360@HYD-MKD-MBX4.wipro.com>
Dear smitha.vanga@wipro.com,
In message <40631E9A2581F14BA60888C87A76A1FE01D360@HYD-MKD-MBX4.wipro.com> you wrote:
>
> >Setenv set_mac 'cp 0xffec0000 0x100000 1024;fdt addr 0xc00000 8192;fdt set=
> /soc8272@f0000000/ethernet@24000 mac-address "[00 44 00 55 00 66]";erase 0x=
> ffec0000 0xffec4000;cp 0xc00000 0xffec0000 1024;bootm 0xfe060000 - 0xffec000=
> 0'
>
> > run set_mac
>
> For the above command I want to replace the mac address with the ethaddr> How
> do I do that. I tried $ethaddr but I get extra : characters.
Why would you do that at all? U-Boot will run fdt_fixup_ethernet()
for all (at least AFAICT) supported architectures, which will replace
"mac-address" and "local-mac-address" for all "ethernet?" interfaces
in the device tree for which a corresponding "ethadd" / "eth?addr"
environment variable is set.
No additional actions are needed.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"One day," said a dull voice from down below, "I'm going to be back
in form again and you're going to be very sorry you said that. For a
very long time. I might even go so far as to make even more Time just
for you to be sorry in." - Terry Pratchett, _Small Gods_
^ permalink raw reply
* Re: [RFC PATCH 15/16] KVM: PPC: booke: standard PPC floating point support
From: Scott Wood @ 2012-01-09 22:39 UTC (permalink / raw)
To: Alexander Graf; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <08DCCAC0-82FA-46FC-974C-E7CCA53474A3@suse.de>
On 01/09/2012 04:17 PM, Alexander Graf wrote:
>
> On 09.01.2012, at 22:48, Scott Wood wrote:
>
>> On 01/09/2012 11:48 AM, Alexander Graf wrote:
>>>
>>> Do you think it's possible to combine this with the book3s_pr code, so we don't duplicate too much here?
>>
>> book3s_pr is a bit different in that it can trap when the guest sets
>> MSR[FP].
>
> Ah, there's no doorbell? So you always have to swap fpu registers? You still have to enable it manually when preempting in, right? IIRC ppc32 does lazy fpu activation.
Right.
Preempting in is handled by calling kvmppc_load_guest_fp() (which should
be renamed to be booke-specific, since the semantics are tied to
booke.c) from kvmppc_core_vcpu_load() in e500mc.c.
>>> I'm having a hard time to grasp when shared->msr, shadow_msr and regs->msr is used in your code :).
>>
>> shadow_msr is the real MSR.
>>
>> shared->msr is the guest's view of MSR.
Correction -- this applies to PR-mode (e500v2).
In GS-mode, shadow_msr is not used. The guest sees the real MSR (hw
silently prevents it from modifying certain bits), which gets saved on
exit into shared->msr.
-Scott
^ permalink raw reply
* Re: [RFC PATCH 15/16] KVM: PPC: booke: standard PPC floating point support
From: Alexander Graf @ 2012-01-09 22:17 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <4F0B60A5.1040208@freescale.com>
On 09.01.2012, at 22:48, Scott Wood wrote:
> On 01/09/2012 11:48 AM, Alexander Graf wrote:
>>=20
>> On 21.12.2011, at 02:34, Scott Wood wrote:
>>> +#ifdef CONFIG_PPC_FPU
>>> + /* Save userspace FPU state in stack */
>>> + enable_kernel_fp();
>>> + memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr));
>>> + fpscr =3D current->thread.fpscr.val;
>>> + fpexc_mode =3D current->thread.fpexc_mode;
>>> +
>>> + /* Restore guest FPU state to thread */
>>> + memcpy(current->thread.fpr, vcpu->arch.fpr, =
sizeof(vcpu->arch.fpr));
>>> + current->thread.fpscr.val =3D vcpu->arch.fpscr;
>>> +
>>> + /*
>>> + * Since we can't trap on MSR_FP in GS-mode, we consider the =
guest
>>> + * as always using the FPU. Kernel usage of FP (via
>>> + * enable_kernel_fp()) in this thread must not occur while
>>> + * vcpu->fpu_active is set.
>>> + */
>>> + vcpu->fpu_active =3D 1;
>>> +
>>> + kvmppc_load_guest_fp(vcpu);
>>> +#endif
>>=20
>> Do you think it's possible to combine this with the book3s_pr code, =
so we don't duplicate too much here?
>=20
> book3s_pr is a bit different in that it can trap when the guest sets
> MSR[FP].
Ah, there's no doorbell? So you always have to swap fpu registers? You =
still have to enable it manually when preempting in, right? IIRC ppc32 =
does lazy fpu activation.
> Maybe a few lines could be factored out (the first memcpy, fpscr,
> fpexc_mode). I'm not sure that it makes sense given the lack of
> isolation between what it's doing and what the rest of the code is =
doing.
Yeah, looking at the code it does look pretty different. Too bad - I =
would've hoped to throw the vmx code in as well so we could get =
vmx/vsx/whatever for free later.
>=20
>>> +/*
>>> + * Load up guest vcpu FP state if it's needed.
>>> + * It also set the MSR_FP in thread so that host know
>>> + * we're holding FPU, and then host can help to save
>>> + * guest vcpu FP state if other threads require to use FPU.
>>> + * This simulates an FP unavailable fault.
>>> + *
>>> + * It requires to be called with preemption disabled.
>>> + */
>>> +static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
>>> +{
>>> +#ifdef CONFIG_PPC_FPU
>>> + if (vcpu->fpu_active && !(current->thread.regs->msr & MSR_FP)) {
>>> + load_up_fpu();
>>> + current->thread.regs->msr |=3D MSR_FP;
>>=20
>> I'm having a hard time to grasp when shared->msr, shadow_msr and =
regs->msr is used in your code :).
>=20
> shadow_msr is the real MSR.
>=20
> shared->msr is the guest's view of MSR.
>=20
> current->thread.regs->msr is nominally userspace's MSR. In this case =
we
> use it to tell host Linux that FP is in use and must be saved on =
context
> switch. The actual userspace MSR_FP is known to be clear at this =
point
> because we called enable_kernel_fp(). It will be clear again when we
> return to userspace because we'll call giveup_fpu().
Ah, this is thread.regs, not vcpu.regs. Sorry, I misread that part. This =
way it obviously makes a lot more sense.
Alex
^ permalink raw reply
* [git pull] Please pull powerpc.git merge branch
From: Kumar Gala @ 2012-01-09 21:47 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
The following changes since commit a0e86bd4252519321b0d102dc4ed90557aa7bee9:
audit: always follow va_copy() with va_end() (2012-01-08 14:15:21 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git merge
Michael Neuling (1):
powerpc: fix compile error with 85xx/p1022_ds.c
arch/powerpc/platforms/85xx/p1022_ds.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
^ permalink raw reply
* Re: [RFC PATCH 15/16] KVM: PPC: booke: standard PPC floating point support
From: Scott Wood @ 2012-01-09 21:48 UTC (permalink / raw)
To: Alexander Graf; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <F0432B7A-E742-48B0-8016-3F2D0A800553@suse.de>
On 01/09/2012 11:48 AM, Alexander Graf wrote:
>
> On 21.12.2011, at 02:34, Scott Wood wrote:
>> +#ifdef CONFIG_PPC_FPU
>> + /* Save userspace FPU state in stack */
>> + enable_kernel_fp();
>> + memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr));
>> + fpscr = current->thread.fpscr.val;
>> + fpexc_mode = current->thread.fpexc_mode;
>> +
>> + /* Restore guest FPU state to thread */
>> + memcpy(current->thread.fpr, vcpu->arch.fpr, sizeof(vcpu->arch.fpr));
>> + current->thread.fpscr.val = vcpu->arch.fpscr;
>> +
>> + /*
>> + * Since we can't trap on MSR_FP in GS-mode, we consider the guest
>> + * as always using the FPU. Kernel usage of FP (via
>> + * enable_kernel_fp()) in this thread must not occur while
>> + * vcpu->fpu_active is set.
>> + */
>> + vcpu->fpu_active = 1;
>> +
>> + kvmppc_load_guest_fp(vcpu);
>> +#endif
>
> Do you think it's possible to combine this with the book3s_pr code, so we don't duplicate too much here?
book3s_pr is a bit different in that it can trap when the guest sets
MSR[FP].
Maybe a few lines could be factored out (the first memcpy, fpscr,
fpexc_mode). I'm not sure that it makes sense given the lack of
isolation between what it's doing and what the rest of the code is doing.
>> +/*
>> + * Load up guest vcpu FP state if it's needed.
>> + * It also set the MSR_FP in thread so that host know
>> + * we're holding FPU, and then host can help to save
>> + * guest vcpu FP state if other threads require to use FPU.
>> + * This simulates an FP unavailable fault.
>> + *
>> + * It requires to be called with preemption disabled.
>> + */
>> +static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
>> +{
>> +#ifdef CONFIG_PPC_FPU
>> + if (vcpu->fpu_active && !(current->thread.regs->msr & MSR_FP)) {
>> + load_up_fpu();
>> + current->thread.regs->msr |= MSR_FP;
>
> I'm having a hard time to grasp when shared->msr, shadow_msr and regs->msr is used in your code :).
shadow_msr is the real MSR.
shared->msr is the guest's view of MSR.
current->thread.regs->msr is nominally userspace's MSR. In this case we
use it to tell host Linux that FP is in use and must be saved on context
switch. The actual userspace MSR_FP is known to be clear at this point
because we called enable_kernel_fp(). It will be clear again when we
return to userspace because we'll call giveup_fpu().
-Scott
^ permalink raw reply
* Re: [PATCH v2 3/3] KVM: PPC: epapr: install ev_idle hcall for e500 guest
From: Scott Wood @ 2012-01-09 21:15 UTC (permalink / raw)
To: Liu Yu; +Cc: kvm, kvm-ppc, agraf, linuxppc-dev, timur
In-Reply-To: <1325754412-29963-2-git-send-email-yu.liu@freescale.com>
On 01/05/2012 03:06 AM, Liu Yu wrote:
> diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S
> index 3e2b95c..6ea95f0 100644
> --- a/arch/powerpc/kernel/idle_e500.S
> +++ b/arch/powerpc/kernel/idle_e500.S
> @@ -85,6 +85,23 @@ END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
> 2: b 2b
> #endif /* !E500MC */
>
> +#ifdef CONFIG_KVM_GUEST
> +/*
> + * r3 contains the pointer to in[8]
> + * r4 contains the pointer to out[8]
> + * r5 contains the hcall vendor and nr
> + * r6 contains the handler which send hcall
> + */
> +_GLOBAL(e500_ev_idle)
> + rlwinm r7,r1,0,0,31-THREAD_SHIFT /* current thread_info */
> + lwz r8,TI_LOCAL_FLAGS(r7) /* set napping bit */
> + ori r8,r8,_TLF_NAPPING /* so when we take an exception */
> + stw r8,TI_LOCAL_FLAGS(r7) /* it will return to our caller */
> + wrteei 1
> + mtctr r6
> + bctr
> +#endif /* KVM_GUEST */
You'll need to branch back to the hcall invocation in an infinite loop
-- the only way we should leave is via an interrupt.
> +static void kvm_hcall_idle(void)
> +{
> +#ifdef CONFIG_KVM_E500
> + ulong in[8];
> + ulong out[8];
> +
> + e500_ev_idle(in, out, HC_VENDOR_EPAPR | HC_EV_IDLE, kvm_hypercall);
> +#endif
> +}
kvm_hypercall is C code. As stated before, you cannot use C code while
_TLF_NAPPING is set.
> +static bool kvm_para_has_idle(void)
> +{
> +#ifdef CONFIG_BOOKE
> + return epapr_hcall_has_idle;
> +#else
> + return false;
> +#endif
> +}
> +
> static int __init kvm_guest_init(void)
> {
> if (!kvm_para_available())
> @@ -594,6 +614,10 @@ static int __init kvm_guest_init(void)
> powersave_nap = 1;
> #endif
>
> + /* Install hcall based power_save for guest kernel */
> + if (kvm_para_has_idle())
> + ppc_md.power_save = kvm_hcall_idle;
Why did you only move it halfway out of KVM code? ePAPR features such
as idle hcall should work on any ePAPR hypervisor, even with all KVM
code disabled.
Plus everything Alex said. :-)
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Add P1024rdb dts support
From: Scott Wood @ 2012-01-09 21:03 UTC (permalink / raw)
To: b29983; +Cc: Tang Yuantian, linuxppc-dev
In-Reply-To: <1326098258-32097-1-git-send-email-b29983@freescale.com>
On 01/09/2012 02:37 AM, b29983@freescale.com wrote:
> +/include/ "p1024rdb.dtsi"
> +/include/ "fsl/p1020si-post.dtsi"
Is p1024 100% software-compatible with p1020?
They have different manuals...
-Scott
^ permalink raw reply
* Re: [SDK v1.2][PATCH 1/2 v3] powerpc/85xx: Add dts for P1021RDB-PC board
From: Scott Wood @ 2012-01-09 20:54 UTC (permalink / raw)
To: Xu Jiucheng; +Cc: Matthew McClintock, linuxppc-dev
In-Reply-To: <1326092022-10085-1-git-send-email-B37781@freescale.com>
On 01/09/2012 12:53 AM, Xu Jiucheng wrote:
> + nand@1,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,p1020-fcm-nand",
> + "fsl,elbc-fcm-nand";
s/p1020/p1021/
-Scott
^ permalink raw reply
* Re: [PATCH 1/2] dtc: Implement -d option to write out a dependency file
From: Jon Loeliger @ 2012-01-09 18:58 UTC (permalink / raw)
To: Stephen Warren
Cc: Michal Marek, Jonas Bonn, Michal Simek, Russell King,
linux-c6x-dev, Arnd Bergmann, Aurelien Jacquiot,
Devicetree Discuss, linux-kbuild, linux-kernel, Rob Herring,
Paul Mackerras, Mark Salter, microblaze-uclinux, linuxppc-dev,
linux, linux-arm-kernel, David Gibson
In-Reply-To: <1326134295-15547-1-git-send-email-swarren@nvidia.com>
> This will allow callers to rebuild .dtb files when any of the /include/d
> .dtsi files are modified, not just the top-level .dts file.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> This patch is against the Linux kernel's copy of dtc, but it applies to
> upstream dtc with a couple of trivial conflicts. I can post a version for
> upstream dtc as well if desired.
If it does go upstream into Linux proper, we should
definitely have it in the main DTC repository.
So if you would, please send me a path that applies there.
Thanks,
jdl
^ permalink raw reply
* Re: [RFC PATCH 16/16] KVM: PPC: e500mc support
From: Scott Wood @ 2012-01-09 19:29 UTC (permalink / raw)
To: Avi Kivity; +Cc: Liu Yu, kvm, agraf, kvm-ppc, Varun Sethi, linuxppc-dev
In-Reply-To: <4F0B16D7.2000709@redhat.com>
On 01/09/2012 10:33 AM, Avi Kivity wrote:
> On 12/21/2011 03:34 AM, Scott Wood wrote:
>> Add processor support for e500mc, using hardware virtualization support
>> (GS-mode).
>>
>> Current issues include:
>> - No support for external proxy (coreint) interrupt mode in the guest.
>>
>> Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>,
>> Varun Sethi <Varun.Sethi@freescale.com>, and
>> Liu Yu <yu.liu@freescale.com>.
>>
>
> Best to include their signoffs, if possible.
These patches are based in part on a bunch of different patches from
these people (for which I did receive signoffs). I was reluctant to put
their signoff directly on the new patches, since I didn't want to make
it look like they had submitted the patch in anything resembling its
current form. I wanted to give them credit for what they did, but not
blame for what I did with their code.
I've CCed Varun and Liu so they can sign off these versions of the
patches if they wish. Ashish no longer works at Freescale, so I don't
have a currently valid e-mail address for him.
-Scott
^ permalink raw reply
* Re: [RFC PATCH 01/16] powerpc/booke: Set CPU_FTR_DEBUG_LVL_EXC on 32-bit
From: Scott Wood @ 2012-01-09 19:14 UTC (permalink / raw)
To: Alexander Graf; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <C57ECE6B-1040-40BC-B7C7-5107533A2DC2@suse.de>
On 01/09/2012 09:21 AM, Alexander Graf wrote:
>
> On 21.12.2011, at 02:34, Scott Wood wrote:
>
>> Currently 32-bit only cares about this for choice of exception
>> vector, which is done in core-specific code. However, KVM will
>> want to distinguish as well.
>>
>> Signed-off-by: Scott Wood <scottwood@freescale.com>
>> ---
>> arch/powerpc/include/asm/cputable.h | 5 +++--
>> 1 files changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
>> index e30442c..033ad30 100644
>> --- a/arch/powerpc/include/asm/cputable.h
>> +++ b/arch/powerpc/include/asm/cputable.h
>> @@ -375,7 +375,8 @@ extern const char *powerpc_base_platform;
>> #define CPU_FTRS_47X (CPU_FTRS_440x6)
>> #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
>> CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
>> - CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
>> + CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
>> + CPU_FTR_DEBUG_LVL_EXC)
>
> KVM on E200?
This isn't a KVM patch, it's a patch to make CPU_FTR_DEBUG_LVL_EXC be
set properly on 32-bit chips. e200 has this CPU feature.
-Scott
^ permalink raw reply
* [PATCH 2/2] Kbuild: Use dtc's -d (dependency) option
From: Stephen Warren @ 2012-01-09 18:38 UTC (permalink / raw)
To: Michal Marek, Jon Loeliger, David Gibson
Cc: Jonas Bonn, Michal Simek, Russell King, linux-c6x-dev,
Arnd Bergmann, Aurelien Jacquiot, Devicetree Discuss,
microblaze-uclinux, linux-kbuild, linux-kernel, Rob Herring,
Paul Mackerras, Mark Salter, Stephen Warren, linuxppc-dev, linux,
linux-arm-kernel
In-Reply-To: <1326134295-15547-1-git-send-email-swarren@nvidia.com>
This hooks dtc into Kbuild's dependency system.
Thus, for example, "make dtbs" will rebuild tegra-harmony.dtb if only
tegra20.dtsi has changed yet tegra-harmony.dts has not. The previous
lack of this feature recently caused me to have very confusing "git
bisect" results.
For ARM, it's obvious what to add to $(targets). I'm not familiar enough
with other architectures to know what to add there. Powerpc appears to
already add various .dtb files into $(targets), but the other archs may
need something added to $(targets) to work.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
I have only tested this series for ARM.
arch/arm/boot/Makefile | 6 ++++--
arch/c6x/boot/Makefile | 2 +-
arch/microblaze/boot/Makefile | 2 +-
arch/openrisc/boot/Makefile | 4 ++--
arch/powerpc/boot/Makefile | 4 ++--
scripts/Makefile.lib | 2 +-
6 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 1338cf0..c72730d 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -62,9 +62,11 @@ $(obj)/zImage-dtb.%: $(obj)/%.dtb $(obj)/zImage
endif
+targets += $(dtb-y)
+
# Rule to build device tree blobs
-$(obj)/%.dtb: $(src)/dts/%.dts
- $(call cmd,dtc)
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
+ $(call if_changed_dep,dtc)
$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
diff --git a/arch/c6x/boot/Makefile b/arch/c6x/boot/Makefile
index ecca820..6891257 100644
--- a/arch/c6x/boot/Makefile
+++ b/arch/c6x/boot/Makefile
@@ -13,7 +13,7 @@ obj-y += linked_dtb.o
endif
$(obj)/%.dtb: $(src)/dts/%.dts FORCE
- $(call cmd,dtc)
+ $(call if_changed_dep,dtc)
quiet_cmd_cp = CP $< $@$2
cmd_cp = cat $< >$@$2 || (rm -f $@ && echo false)
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index 4c4e58e..0c796cf 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -53,6 +53,6 @@ $(obj)/simpleImage.%: vmlinux FORCE
DTC_FLAGS := -p 1024
$(obj)/%.dtb: $(src)/dts/%.dts FORCE
- $(call cmd,dtc)
+ $(call if_changed_dep,dtc)
clean-files += *.dtb simpleImage.*.unstrip linux.bin.ub
diff --git a/arch/openrisc/boot/Makefile b/arch/openrisc/boot/Makefile
index 98ca185..0995835 100644
--- a/arch/openrisc/boot/Makefile
+++ b/arch/openrisc/boot/Makefile
@@ -11,5 +11,5 @@ clean-files := *.dtb.S
#DTC_FLAGS ?= -p 1024
-$(obj)/%.dtb: $(src)/dts/%.dts
- $(call cmd,dtc)
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
+ $(call if_changed_dep,dtc)
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 15986e7..8844a17 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -345,8 +345,8 @@ $(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
$(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb)
# Rule to build device tree blobs
-$(obj)/%.dtb: $(src)/dts/%.dts
- $(call cmd,dtc)
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
+ $(call if_changed_dep,dtc)
# If there isn't a platform selected then just strip the vmlinux.
ifeq (,$(image-y))
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 5d986d9..7bae316 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -264,7 +264,7 @@ $(obj)/%.dtb.S: $(obj)/%.dtb
$(call cmd,dt_S_dtb)
quiet_cmd_dtc = DTC $@
-cmd_dtc = $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 $(DTC_FLAGS) $<
+cmd_dtc = $(objtree)/scripts/dtc/dtc -O dtb -o $@ -b 0 $(DTC_FLAGS) -d $(depfile) $<
# Bzip2
# ---------------------------------------------------------------------------
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/2] dtc: Implement -d option to write out a dependency file
From: Stephen Warren @ 2012-01-09 18:38 UTC (permalink / raw)
To: Michal Marek, Jon Loeliger, David Gibson
Cc: Jonas Bonn, Michal Simek, Russell King, linux-c6x-dev,
Arnd Bergmann, Aurelien Jacquiot, Devicetree Discuss,
microblaze-uclinux, linux-kbuild, linux-kernel, Rob Herring,
Paul Mackerras, Mark Salter, Stephen Warren, linuxppc-dev, linux,
linux-arm-kernel
This will allow callers to rebuild .dtb files when any of the /include/d
.dtsi files are modified, not just the top-level .dts file.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
This patch is against the Linux kernel's copy of dtc, but it applies to
upstream dtc with a couple of trivial conflicts. I can post a version for
upstream dtc as well if desired.
I have only tested this series for ARM.
scripts/dtc/dtc.c | 22 +++++++++++++++++++++-
scripts/dtc/srcpos.c | 6 ++++++
scripts/dtc/srcpos.h | 1 +
3 files changed, 28 insertions(+), 1 deletions(-)
diff --git a/scripts/dtc/dtc.c b/scripts/dtc/dtc.c
index cbc0193..27ecf06 100644
--- a/scripts/dtc/dtc.c
+++ b/scripts/dtc/dtc.c
@@ -71,6 +71,7 @@ static void __attribute__ ((noreturn)) usage(void)
fprintf(stderr, "\t\t\tasm - assembler source\n");
fprintf(stderr, "\t-V <output version>\n");
fprintf(stderr, "\t\tBlob version to produce, defaults to %d (relevant for dtb\n\t\tand asm output only)\n", DEFAULT_FDT_VERSION);
+ fprintf(stderr, "\t-d <output dependency file>\n");
fprintf(stderr, "\t-R <number>\n");
fprintf(stderr, "\t\tMake space for <number> reserve map entries (relevant for \n\t\tdtb and asm output only)\n");
fprintf(stderr, "\t-S <bytes>\n");
@@ -99,6 +100,7 @@ int main(int argc, char *argv[])
const char *inform = "dts";
const char *outform = "dts";
const char *outname = "-";
+ const char *depname = NULL;
int force = 0, check = 0, sort = 0;
const char *arg;
int opt;
@@ -111,7 +113,8 @@ int main(int argc, char *argv[])
minsize = 0;
padsize = 0;
- while ((opt = getopt(argc, argv, "hI:O:o:V:R:S:p:fcqb:vH:s")) != EOF) {
+ while ((opt = getopt(argc, argv, "hI:O:o:V:d:R:S:p:fcqb:vH:s"))
+ != EOF) {
switch (opt) {
case 'I':
inform = optarg;
@@ -125,6 +128,9 @@ int main(int argc, char *argv[])
case 'V':
outversion = strtol(optarg, NULL, 0);
break;
+ case 'd':
+ depname = optarg;
+ break;
case 'R':
reservenum = strtol(optarg, NULL, 0);
break;
@@ -188,6 +194,15 @@ int main(int argc, char *argv[])
fprintf(stderr, "DTC: %s->%s on file \"%s\"\n",
inform, outform, arg);
+ if (depname) {
+ depfile = fopen(depname, "w");
+ if (!depfile)
+ die("Couldn't open dependency file %s: %s\n", depname,
+ strerror(errno));
+ fputs(outname, depfile);
+ fputc(':', depfile);
+ }
+
if (streq(inform, "dts"))
bi = dt_from_source(arg);
else if (streq(inform, "fs"))
@@ -197,6 +212,11 @@ int main(int argc, char *argv[])
else
die("Unknown input format \"%s\"\n", inform);
+ if (depfile) {
+ fputc('\n', depfile);
+ fclose(depfile);
+ }
+
if (cmdline_boot_cpuid != -1)
bi->boot_cpuid_phys = cmdline_boot_cpuid;
diff --git a/scripts/dtc/srcpos.c b/scripts/dtc/srcpos.c
index 2dbc874..93b3533 100644
--- a/scripts/dtc/srcpos.c
+++ b/scripts/dtc/srcpos.c
@@ -40,6 +40,7 @@ static char *dirname(const char *path)
return NULL;
}
+FILE *depfile; /* = NULL */
struct srcfile_state *current_srcfile; /* = NULL */
/* Detect infinite include recursion. */
@@ -67,6 +68,11 @@ FILE *srcfile_relative_open(const char *fname, char **fullnamep)
strerror(errno));
}
+ if (depfile) {
+ fputc(' ', depfile);
+ fputs(fullname, depfile);
+ }
+
if (fullnamep)
*fullnamep = fullname;
else
diff --git a/scripts/dtc/srcpos.h b/scripts/dtc/srcpos.h
index bd7966e..ce980ca 100644
--- a/scripts/dtc/srcpos.h
+++ b/scripts/dtc/srcpos.h
@@ -30,6 +30,7 @@ struct srcfile_state {
struct srcfile_state *prev;
};
+extern FILE *depfile; /* = NULL */
extern struct srcfile_state *current_srcfile; /* = NULL */
FILE *srcfile_relative_open(const char *fname, char **fullnamep);
--
1.7.0.4
^ permalink raw reply related
* Re: [RFC PATCH 15/16] KVM: PPC: booke: standard PPC floating point support
From: Alexander Graf @ 2012-01-09 17:48 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <20111221013445.GO8378@schlenkerla.am.freescale.net>
On 21.12.2011, at 02:34, Scott Wood wrote:
> e500mc has a normal PPC FPU, rather than SPE which is found
> on e500v1/v2.
>=20
> Based on code from Liu Yu <yu.liu@freescale.com>.
>=20
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> arch/powerpc/include/asm/system.h | 1 +
> arch/powerpc/kvm/booke.c | 44 =
+++++++++++++++++++++++++++++++++++++
> arch/powerpc/kvm/booke.h | 30 +++++++++++++++++++++++++
> 3 files changed, 75 insertions(+), 0 deletions(-)
>=20
> diff --git a/arch/powerpc/include/asm/system.h =
b/arch/powerpc/include/asm/system.h
> index e30a13d..0561356 100644
> --- a/arch/powerpc/include/asm/system.h
> +++ b/arch/powerpc/include/asm/system.h
> @@ -140,6 +140,7 @@ extern void via_cuda_init(void);
> extern void read_rtc_time(void);
> extern void pmac_find_display(void);
> extern void giveup_fpu(struct task_struct *);
> +extern void load_up_fpu(void);
> extern void disable_kernel_fp(void);
> extern void enable_kernel_fp(void);
> extern void flush_fp_to_thread(struct task_struct *);
> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> index cf63b93..4bf43f9 100644
> --- a/arch/powerpc/kvm/booke.c
> +++ b/arch/powerpc/kvm/booke.c
> @@ -460,6 +460,11 @@ void kvmppc_core_prepare_to_enter(struct kvm_vcpu =
*vcpu)
> int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
> {
> int ret;
> +#ifdef CONFIG_PPC_FPU
> + unsigned int fpscr;
> + int fpexc_mode;
> + u64 fpr[32];
> +#endif
>=20
> if (!vcpu->arch.sane) {
> kvm_run->exit_reason =3D KVM_EXIT_INTERNAL_ERROR;
> @@ -482,7 +487,46 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, =
struct kvm_vcpu *vcpu)
> }
>=20
> kvm_guest_enter();
> +
> +#ifdef CONFIG_PPC_FPU
> + /* Save userspace FPU state in stack */
> + enable_kernel_fp();
> + memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr));
> + fpscr =3D current->thread.fpscr.val;
> + fpexc_mode =3D current->thread.fpexc_mode;
> +
> + /* Restore guest FPU state to thread */
> + memcpy(current->thread.fpr, vcpu->arch.fpr, =
sizeof(vcpu->arch.fpr));
> + current->thread.fpscr.val =3D vcpu->arch.fpscr;
> +
> + /*
> + * Since we can't trap on MSR_FP in GS-mode, we consider the =
guest
> + * as always using the FPU. Kernel usage of FP (via
> + * enable_kernel_fp()) in this thread must not occur while
> + * vcpu->fpu_active is set.
> + */
> + vcpu->fpu_active =3D 1;
> +
> + kvmppc_load_guest_fp(vcpu);
> +#endif
Do you think it's possible to combine this with the book3s_pr code, so =
we don't duplicate too much here?
> +
> ret =3D __kvmppc_vcpu_run(kvm_run, vcpu);
> +
> +#ifdef CONFIG_PPC_FPU
> + kvmppc_save_guest_fp(vcpu);
> +
> + vcpu->fpu_active =3D 0;
> +
> + /* Save guest FPU state from thread */
> + memcpy(vcpu->arch.fpr, current->thread.fpr, =
sizeof(vcpu->arch.fpr));
> + vcpu->arch.fpscr =3D current->thread.fpscr.val;
> +
> + /* Restore userspace FPU state from stack */
> + memcpy(current->thread.fpr, fpr, sizeof(current->thread.fpr));
> + current->thread.fpscr.val =3D fpscr;
> + current->thread.fpexc_mode =3D fpexc_mode;
> +#endif
> +
> kvm_guest_exit();
>=20
> out:
> diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
> index d53bcf2..3bf5eda 100644
> --- a/arch/powerpc/kvm/booke.h
> +++ b/arch/powerpc/kvm/booke.h
> @@ -96,4 +96,34 @@ enum int_class {
>=20
> void kvmppc_set_pending_interrupt(struct kvm_vcpu *vcpu, enum =
int_class type);
>=20
> +/*
> + * Load up guest vcpu FP state if it's needed.
> + * It also set the MSR_FP in thread so that host know
> + * we're holding FPU, and then host can help to save
> + * guest vcpu FP state if other threads require to use FPU.
> + * This simulates an FP unavailable fault.
> + *
> + * It requires to be called with preemption disabled.
> + */
> +static inline void kvmppc_load_guest_fp(struct kvm_vcpu *vcpu)
> +{
> +#ifdef CONFIG_PPC_FPU
> + if (vcpu->fpu_active && !(current->thread.regs->msr & MSR_FP)) {
> + load_up_fpu();
> + current->thread.regs->msr |=3D MSR_FP;
I'm having a hard time to grasp when shared->msr, shadow_msr and =
regs->msr is used in your code :).
Alex
^ permalink raw reply
* Re: [RFC PATCH 14/16] KVM: PPC: booke: category E.HV (GS-mode) support
From: Alexander Graf @ 2012-01-09 17:46 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <20111221013443.GN8378@schlenkerla.am.freescale.net>
On 21.12.2011, at 02:34, Scott Wood wrote:
> Chips such as e500mc that implement category E.HV in Power ISA 2.06
> provide hardware virtualization features, including a new MSR mode for
> guest state. The guest OS can perform many operations without =
trapping
> into the hypervisor, including transitions to and from guest =
userspace.
>=20
> Since we can use SRR1[GS] to reliably tell whether an exception came =
from
> guest state, instead of messing around with IVPR, we use DO_KVM =
similarly
> to book3s.
Is there any benefit of using DO_KVM? I would assume that messing with =
IVPR is faster.
>=20
> Current issues include:
> - Machine checks from guest state are not routed to the host handler.
> - The guest can cause a host oops by executing an emulated instruction
> in a page that lacks read permission. Existing e500/4xx support has
> the same problem.
We solve that in book3s pr by doing
LAST_INST =3D <known bad value>;
PACA->kvm_mode =3D <recover at next inst>;
lwz(guest pc);
do_more_stuff();
That way when an exception occurs at lwz() the DO_KVM handler checks =
that we're in kvm mode "recover" which does basically srr0+=3D4; rfi;.
>=20
> Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>,
> Varun Sethi <Varun.Sethi@freescale.com>, and
> Liu Yu <yu.liu@freescale.com>.
>=20
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> arch/powerpc/include/asm/dbell.h | 1 +
> arch/powerpc/include/asm/kvm_asm.h | 8 +
> arch/powerpc/include/asm/kvm_booke_hv_asm.h | 49 +++
> arch/powerpc/include/asm/kvm_host.h | 19 +-
> arch/powerpc/include/asm/kvm_ppc.h | 3 +
> arch/powerpc/include/asm/mmu-book3e.h | 6 +
> arch/powerpc/include/asm/processor.h | 3 +
> arch/powerpc/include/asm/reg.h | 2 +
> arch/powerpc/include/asm/reg_booke.h | 34 ++
> arch/powerpc/kernel/asm-offsets.c | 15 +-
> arch/powerpc/kernel/head_booke.h | 28 ++-
> arch/powerpc/kvm/Kconfig | 3 +
> arch/powerpc/kvm/booke.c | 398 ++++++++++++++-----
> arch/powerpc/kvm/booke.h | 24 +-
> arch/powerpc/kvm/booke_emulate.c | 23 +-
> arch/powerpc/kvm/bookehv_interrupts.S | 587 =
+++++++++++++++++++++++++++
> arch/powerpc/kvm/powerpc.c | 5 +
> arch/powerpc/kvm/timing.h | 6 +
> 18 files changed, 1107 insertions(+), 107 deletions(-)
> create mode 100644 arch/powerpc/include/asm/kvm_booke_hv_asm.h
> create mode 100644 arch/powerpc/kvm/bookehv_interrupts.S
>=20
> diff --git a/arch/powerpc/include/asm/dbell.h =
b/arch/powerpc/include/asm/dbell.h
> index efa74ac..d7365b0 100644
> --- a/arch/powerpc/include/asm/dbell.h
> +++ b/arch/powerpc/include/asm/dbell.h
> @@ -19,6 +19,7 @@
>=20
> #define PPC_DBELL_MSG_BRDCAST (0x04000000)
> #define PPC_DBELL_TYPE(x) (((x) & 0xf) << (63-36))
> +#define PPC_DBELL_LPID(x) ((x) << (63 - 49))
> enum ppc_dbell {
> PPC_DBELL =3D 0, /* doorbell */
> PPC_DBELL_CRIT =3D 1, /* critical doorbell */
> diff --git a/arch/powerpc/include/asm/kvm_asm.h =
b/arch/powerpc/include/asm/kvm_asm.h
> index 7b1f0e0..0978152 100644
> --- a/arch/powerpc/include/asm/kvm_asm.h
> +++ b/arch/powerpc/include/asm/kvm_asm.h
> @@ -48,6 +48,14 @@
> #define BOOKE_INTERRUPT_SPE_FP_DATA 33
> #define BOOKE_INTERRUPT_SPE_FP_ROUND 34
> #define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
> +#define BOOKE_INTERRUPT_DOORBELL 36
> +#define BOOKE_INTERRUPT_DOORBELL_CRITICAL 37
> +
> +/* booke_hv */
> +#define BOOKE_INTERRUPT_GUEST_DBELL 38
> +#define BOOKE_INTERRUPT_GUEST_DBELL_CRIT 39
> +#define BOOKE_INTERRUPT_HV_SYSCALL 40
> +#define BOOKE_INTERRUPT_HV_PRIV 41
>=20
> /* book3s */
>=20
> diff --git a/arch/powerpc/include/asm/kvm_booke_hv_asm.h =
b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> new file mode 100644
> index 0000000..30a600f
> --- /dev/null
> +++ b/arch/powerpc/include/asm/kvm_booke_hv_asm.h
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright 2010-2011 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or =
modify
> + * it under the terms of the GNU General Public License, version 2, =
as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef ASM_KVM_BOOKE_HV_ASM_H
> +#define ASM_KVM_BOOKE_HV_ASM_H
> +
> +#ifdef __ASSEMBLY__
> +
> +/*
> + * All exceptions from guest state must go through KVM
> + * (except for those which are delivered directly to the guest) --
> + * there are no exceptions for which we fall through directly to
> + * the normal host handler.
> + *
> + * Expected inputs (normal exceptions):
> + * SCRATCH0 =3D saved r10
> + * r10 =3D thread struct
> + * r11 =3D appropriate SRR1 variant (currently used as scratch)
> + * r13 =3D saved CR
> + * *(r10 + THREAD_NORMSAVE(0)) =3D saved r11
> + * *(r10 + THREAD_NORMSAVE(2)) =3D saved r13
> + *
> + * Expected inputs (crit/mcheck/debug exceptions):
> + * appropriate SCRATCH =3D saved r8
> + * r8 =3D exception level stack frame
> + * r9 =3D *(r8 + _CCR) =3D saved CR
> + * r11 =3D appropriate SRR1 variant (currently used as scratch)
> + * *(r8 + GPR9) =3D saved r9
> + * *(r8 + GPR10) =3D saved r10 (r10 not yet clobbered)
> + * *(r8 + GPR11) =3D saved r11
> + */
> +.macro DO_KVM intno srr1
> +#ifdef CONFIG_KVM_BOOKE_HV
> +BEGIN_FTR_SECTION
> + mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg =
*/
> + bf 3, kvmppc_resume_\intno\()_\srr1
> + b kvmppc_handler_\intno\()_\srr1
> +kvmppc_resume_\intno\()_\srr1:
> +END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
> +#endif
> +.endm
> +
> +#endif /*__ASSEMBLY__ */
> +#endif /* ASM_KVM_BOOKE_HV_ASM_H */
> diff --git a/arch/powerpc/include/asm/kvm_host.h =
b/arch/powerpc/include/asm/kvm_host.h
> index ad4d671..d603513 100644
> --- a/arch/powerpc/include/asm/kvm_host.h
> +++ b/arch/powerpc/include/asm/kvm_host.h
> @@ -107,6 +107,8 @@ struct kvm_vcpu_stat {
> u32 dec_exits;
> u32 ext_intr_exits;
> u32 halt_wakeup;
> + u32 dbell_exits;
> + u32 gdbell_exits;
> #ifdef CONFIG_PPC_BOOK3S
> u32 pf_storage;
> u32 pf_instruc;
> @@ -141,6 +143,7 @@ enum kvm_exit_types {
> EMULATED_TLBSX_EXITS,
> EMULATED_TLBWE_EXITS,
> EMULATED_RFI_EXITS,
> + EMULATED_RFCI_EXITS,
> DEC_EXITS,
> EXT_INTR_EXITS,
> HALT_WAKEUP,
> @@ -148,6 +151,8 @@ enum kvm_exit_types {
> FP_UNAVAIL,
> DEBUG_EXITS,
> TIMEINGUEST,
> + DBELL_EXITS,
> + GDBELL_EXITS,
> __NUMBER_OF_KVM_EXIT_TYPES
> };
>=20
> @@ -213,10 +218,10 @@ struct revmap_entry {
> #define KVMPPC_GOT_PAGE 0x80
>=20
> struct kvm_arch {
> + unsigned int lpid;
> #ifdef CONFIG_KVM_BOOK3S_64_HV
> unsigned long hpt_virt;
> struct revmap_entry *revmap;
> - unsigned int lpid;
> unsigned int host_lpid;
> unsigned long host_lpcr;
> unsigned long sdr1;
> @@ -346,6 +351,17 @@ struct kvm_vcpu_arch {
> u32 qpr[32];
> #endif
>=20
> +#ifdef CONFIG_KVM_BOOKE_HV
> + u32 host_mas4;
> + u32 host_mas6;
> + u32 shadow_epcr;
> + u32 epcr;
> + u32 shadow_msrp;
> + u32 eplc;
> + u32 epsc;
> + u32 oldpir;
> +#endif
> +
> #ifdef CONFIG_PPC_BOOK3S
> ulong hflags;
> ulong guest_owned_ext;
> @@ -417,6 +433,7 @@ struct kvm_vcpu_arch {
> ulong queued_esr;
> u32 tlbcfg[4];
> u32 mmucfg;
> + u32 epr;
> #endif
> gpa_t paddr_accessed;
>=20
> diff --git a/arch/powerpc/include/asm/kvm_ppc.h =
b/arch/powerpc/include/asm/kvm_ppc.h
> index 5524f88..247b920 100644
> --- a/arch/powerpc/include/asm/kvm_ppc.h
> +++ b/arch/powerpc/include/asm/kvm_ppc.h
> @@ -137,6 +137,9 @@ extern int =
kvmppc_core_prepare_memory_region(struct kvm *kvm,
> extern void kvmppc_core_commit_memory_region(struct kvm *kvm,
> struct kvm_userspace_memory_region =
*mem);
>=20
> +extern int kvmppc_bookehv_init(void);
> +extern void kvmppc_bookehv_exit(void);
> +
> /*
> * Cuts out inst bits with ordering according to spec.
> * That means the leftmost bit is zero. All given bits are included.
> diff --git a/arch/powerpc/include/asm/mmu-book3e.h =
b/arch/powerpc/include/asm/mmu-book3e.h
> index 36a6eaa..b8e303c 100644
> --- a/arch/powerpc/include/asm/mmu-book3e.h
> +++ b/arch/powerpc/include/asm/mmu-book3e.h
> @@ -104,6 +104,8 @@
> #define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */
> #define MAS4_TSIZED_SHIFT 7
>=20
> +#define MAS5_SGS 0x80000000
> +
> #define MAS6_SPID0 0x3FFF0000
> #define MAS6_SPID1 0x00007FFE
> #define MAS6_ISIZE(x) MAS1_TSIZE(x)
> @@ -118,6 +120,10 @@
>=20
> #define MAS7_RPN 0xFFFFFFFF
>=20
> +#define MAS8_TGS 0x80000000 /* Guest space */
> +#define MAS8_VF 0x40000000 /* Virtualization =
Fault */
> +#define MAS8_TLPID 0x000000ff
> +
> /* Bit definitions for MMUCFG */
> #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version =
Number */
> #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
> diff --git a/arch/powerpc/include/asm/processor.h =
b/arch/powerpc/include/asm/processor.h
> index eb11a44..032a984 100644
> --- a/arch/powerpc/include/asm/processor.h
> +++ b/arch/powerpc/include/asm/processor.h
> @@ -243,6 +243,9 @@ struct thread_struct {
> #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
> void* kvm_shadow_vcpu; /* KVM internal data */
> #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
> +#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
> + struct kvm_vcpu *kvm_vcpu;
> +#endif
> #ifdef CONFIG_PPC64
> unsigned long dscr;
> int dscr_inherit;
> diff --git a/arch/powerpc/include/asm/reg.h =
b/arch/powerpc/include/asm/reg.h
> index 209dc74..5993770 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -257,7 +257,9 @@
> #define LPCR_LPES_SH 2
> #define LPCR_RMI 0x00000002 /* real mode is cache inhibit =
*/
> #define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) =
*/
> +#ifndef SPRN_LPID
> #define SPRN_LPID 0x13F /* Logical Partition Identifier */
> +#endif
> #define LPID_RSVD 0x3ff /* Reserved LPID for partn =
switching */
> #define SPRN_HMER 0x150 /* Hardware m? error recovery */
> #define SPRN_HMEER 0x151 /* Hardware m? enable error =
recovery */
> diff --git a/arch/powerpc/include/asm/reg_booke.h =
b/arch/powerpc/include/asm/reg_booke.h
> index 03c48e8..bd80b8d 100644
> --- a/arch/powerpc/include/asm/reg_booke.h
> +++ b/arch/powerpc/include/asm/reg_booke.h
> @@ -56,17 +56,29 @@
> #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 =
Write */
> #define SPRN_EPCR 0x133 /* Embedded Processor Control Register =
*/
> #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
> +#define SPRN_MSRP 0x137 /* MSR Protect Register */
> #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
> #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
> #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
> #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
> +#define SPRN_LPID 0x152 /* Logical Partition ID */
> #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
> #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
> #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
> #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
> #define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */
> +#define SPRN_GSPRG0 0x170 /* Guest SPRG0 */
> +#define SPRN_GSPRG1 0x171 /* Guest SPRG1 */
> +#define SPRN_GSPRG2 0x172 /* Guest SPRG2 */
> +#define SPRN_GSPRG3 0x173 /* Guest SPRG3 */
> #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
> #define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */
> +#define SPRN_GSRR0 0x17A /* Guest SRR0 */
> +#define SPRN_GSRR1 0x17B /* Guest SRR1 */
> +#define SPRN_GEPR 0x17C /* Guest EPR */
> +#define SPRN_GDEAR 0x17D /* Guest DEAR */
> +#define SPRN_GPIR 0x17E /* Guest PIR */
> +#define SPRN_GESR 0x17F /* Guest Exception Syndrome Register */
> #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
> #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
> #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
> @@ -87,6 +99,13 @@
> #define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 =
*/
> #define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 =
*/
> #define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 =
*/
> +#define SPRN_GIVOR2 0x1B8 /* Guest IVOR2 */
> +#define SPRN_GIVOR3 0x1B9 /* Guest IVOR3 */
> +#define SPRN_GIVOR4 0x1BA /* Guest IVOR4 */
> +#define SPRN_GIVOR8 0x1BB /* Guest IVOR8 */
> +#define SPRN_GIVOR13 0x1BC /* Guest IVOR13 */
> +#define SPRN_GIVOR14 0x1BD /* Guest IVOR14 */
> +#define SPRN_GIVPR 0x1BF /* Guest IVPR */
> #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
> #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register =
*/
> #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register =
*/
> @@ -235,6 +254,10 @@
> #define MCSR_LDG 0x00002000UL /* Guarded Load */
> #define MCSR_TLBSYNC 0x00000002UL /* Multiple tlbsyncs detected */
> #define MCSR_BSL2_ERR 0x00000001UL /* Backside L2 cache error */
> +
> +#define MSRP_UCLEP 0x04000000 /* Protect MSR[UCLE] */
> +#define MSRP_DEP 0x00000200 /* Protect MSR[DE] */
> +#define MSRP_PMMP 0x00000004 /* Protect MSR[PMM] */
> #endif
>=20
> #ifdef CONFIG_E200
> @@ -589,6 +612,17 @@
> #define SPRN_EPCR_DMIUH 0x00400000 /* Disable MAS =
Interrupt updates
> * for hypervisor */
>=20
> +/* Bit definitions for EPLC/EPSC */
> +#define EPC_EPR 0x80000000 /* 1 =3D user, 0 =3D kernel =
*/
> +#define EPC_EPR_SHIFT 31
> +#define EPC_EAS 0x40000000 /* Address Space */
> +#define EPC_EAS_SHIFT 30
> +#define EPC_EGS 0x20000000 /* 1 =3D guest, 0 =3D =
hypervisor */
> +#define EPC_EGS_SHIFT 29
> +#define EPC_ELPID 0x00ff0000
> +#define EPC_ELPID_SHIFT 16
> +#define EPC_EPID 0x00003fff
> +#define EPC_EPID_SHIFT 0
>=20
> /*
> * The IBM-403 is an even more odd special case, as it is much
> diff --git a/arch/powerpc/kernel/asm-offsets.c =
b/arch/powerpc/kernel/asm-offsets.c
> index c80bdd1..e179f09 100644
> --- a/arch/powerpc/kernel/asm-offsets.c
> +++ b/arch/powerpc/kernel/asm-offsets.c
> @@ -119,6 +119,9 @@ int main(void)
> #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
> DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, =
kvm_shadow_vcpu));
> #endif
> +#ifdef CONFIG_KVM_BOOKE_HV
> + DEFINE(THREAD_KVM_VCPU, offsetof(struct thread_struct, =
kvm_vcpu));
> +#endif
>=20
> DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
> DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, =
local_flags));
> @@ -400,6 +403,7 @@ int main(void)
> #ifdef CONFIG_KVM
> DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, =
arch.host_stack));
> DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid));
> + DEFINE(VCPU_GUEST_PID, offsetof(struct kvm_vcpu, arch.pid));
> DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.regs.gpr));
> DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave));
> DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fpr));
> @@ -442,9 +446,11 @@ int main(void)
> DEFINE(VCPU_SHARED_MAS4, offsetof(struct kvm_vcpu_arch_shared, =
mas4));
> DEFINE(VCPU_SHARED_MAS6, offsetof(struct kvm_vcpu_arch_shared, =
mas6));
>=20
> + DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
> + DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid));
> +
> /* book3s */
> #ifdef CONFIG_KVM_BOOK3S_64_HV
> - DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid));
> DEFINE(KVM_SDR1, offsetof(struct kvm, arch.sdr1));
> DEFINE(KVM_HOST_LPID, offsetof(struct kvm, arch.host_lpid));
> DEFINE(KVM_HOST_LPCR, offsetof(struct kvm, arch.host_lpcr));
> @@ -459,7 +465,6 @@ int main(void)
> DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
> #endif
> #ifdef CONFIG_PPC_BOOK3S
> - DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
> DEFINE(VCPU_VCPUID, offsetof(struct kvm_vcpu, vcpu_id));
> DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr));
> DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr));
> @@ -605,6 +610,12 @@ int main(void)
> DEFINE(VCPU_HOST_SPEFSCR, offsetof(struct kvm_vcpu, =
arch.host_spefscr));
> #endif
>=20
> +#ifdef CONFIG_KVM_BOOKE_HV
> + DEFINE(VCPU_HOST_MAS4, offsetof(struct kvm_vcpu, =
arch.host_mas4));
> + DEFINE(VCPU_HOST_MAS6, offsetof(struct kvm_vcpu, =
arch.host_mas6));
> + DEFINE(VCPU_EPLC, offsetof(struct kvm_vcpu, arch.eplc));
> +#endif
> +
> #ifdef CONFIG_KVM_EXIT_TIMING
> DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
> =
arch.timing_exit.tv32.tbu));
> diff --git a/arch/powerpc/kernel/head_booke.h =
b/arch/powerpc/kernel/head_booke.h
> index 06ab353..b87c335 100644
> --- a/arch/powerpc/kernel/head_booke.h
> +++ b/arch/powerpc/kernel/head_booke.h
> @@ -3,6 +3,7 @@
>=20
> #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
> #include <asm/kvm_asm.h>
> +#include <asm/kvm_booke_hv_asm.h>
>=20
> /*
> * Macros used for common Book-e exception handling
> @@ -36,8 +37,9 @@
> stw r11, THREAD_NORMSAVE(0)(r10); =
\
> stw r13, THREAD_NORMSAVE(2)(r10); =
\
> mfcr r13; /* save CR in r13 for now =
*/\
> - mfspr r11,SPRN_SRR1; /* check whether user or kernel =
*/\
> - andi. r11,r11,MSR_PR; =
\
> + mfspr r11, SPRN_SRR1; =
\
> + DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; =
\
> + andi. r11, r11, MSR_PR; /* check whether user or kernel =
*/\
> mr r11, r1; =
\
> beq 1f; =
\
> /* if from user, start at top of this thread's kernel stack */ =
\
> @@ -123,8 +125,9 @@
> stw r10,GPR10(r8); =
\
> stw r11,GPR11(r8); =
\
> stw r9,_CCR(r8); /* save CR on stack =
*/\
> - mfspr r10,exc_level_srr1; /* check whether user or kernel =
*/\
> - andi. r10,r10,MSR_PR; =
\
> + mfspr r11,exc_level_srr1; /* check whether user or kernel =
*/\
> + DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; =
\
> + andi. r11,r11,MSR_PR; =
\
> mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of =
*/\
> lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel =
stack */\
> addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame =
*/\
> @@ -173,6 +176,23 @@
> SPRN_MCSRR0, SPRN_MCSRR1)
>=20
> /*
> + * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
> + * being delivered to the host. This exception can only happen
> + * inside a KVM guest -- so we just handle up to the DO_KVM rather
> + * than try to fit this into one of the existing prolog macros.
> + */
> +#define GUEST_DOORBELL_EXCEPTION \
> + START_EXCEPTION(GuestDoorbell); =
\
> + mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ =
\
> + mfspr r10, SPRN_SPRG_THREAD; =
\
> + stw r11, THREAD_NORMSAVE(0)(r10); =
\
> + mfspr r11, SPRN_SRR1; =
\
> + stw r13, THREAD_NORMSAVE(2)(r10); =
\
> + mfcr r13; /* save CR in r13 for now =
*/\
> + DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; =
\
> + trap
> +
> +/*
> * Exception vectors.
> */
> #define START_EXCEPTION(label) =
\
> diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
> index 8f64709..2c33cd3 100644
> --- a/arch/powerpc/kvm/Kconfig
> +++ b/arch/powerpc/kvm/Kconfig
> @@ -90,6 +90,9 @@ config KVM_BOOK3S_64_PR
> depends on KVM_BOOK3S_64 && !KVM_BOOK3S_64_HV
> select KVM_BOOK3S_PR
>=20
> +config KVM_BOOKE_HV
> + bool
> +
> config KVM_440
> bool "KVM support for PowerPC 440 processors"
> depends on EXPERIMENTAL && 44x
> diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
> index f66e741..cf63b93 100644
> --- a/arch/powerpc/kvm/booke.c
> +++ b/arch/powerpc/kvm/booke.c
> @@ -17,6 +17,8 @@
> *
> * Authors: Hollis Blanchard <hollisb@us.ibm.com>
> * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
> + * Scott Wood <scottwood@freescale.com>
> + * Varun Sethi <varun.sethi@freescale.com>
> */
>=20
> #include <linux/errno.h>
> @@ -30,9 +32,12 @@
> #include <asm/cputable.h>
> #include <asm/uaccess.h>
> #include <asm/kvm_ppc.h>
> -#include "timing.h"
> #include <asm/cacheflush.h>
> +#include <asm/dbell.h>
> +#include <asm/hw_irq.h>
> +#include <asm/irq.h>
>=20
> +#include "timing.h"
> #include "booke.h"
>=20
> unsigned long kvmppc_booke_handlers;
> @@ -55,6 +60,8 @@ struct kvm_stats_debugfs_item debugfs_entries[] =3D =
{
> { "dec", VCPU_STAT(dec_exits) },
> { "ext_intr", VCPU_STAT(ext_intr_exits) },
> { "halt_wakeup", VCPU_STAT(halt_wakeup) },
> + { "doorbell", VCPU_STAT(dbell_exits) },
> + { "guest doorbell", VCPU_STAT(gdbell_exits) },
> { NULL }
> };
>=20
> @@ -123,6 +130,10 @@ void kvmppc_set_msr(struct kvm_vcpu *vcpu, u32 =
new_msr)
> {
> u32 old_msr =3D vcpu->arch.shared->msr;
>=20
> +#ifdef CONFIG_KVM_BOOKE_HV
> + new_msr |=3D MSR_GS;
> +#endif
> +
> vcpu->arch.shared->msr =3D new_msr;
>=20
> kvmppc_mmu_msr_notify(vcpu, old_msr);
> @@ -197,6 +208,75 @@ void kvmppc_core_dequeue_external(struct kvm_vcpu =
*vcpu,
> clear_bit(BOOKE_IRQPRIO_EXTERNAL_LEVEL, =
&vcpu->arch.pending_exceptions);
> }
>=20
> +static void set_guest_srr(struct kvm_vcpu *vcpu, unsigned long srr0, =
u32 srr1)
> +{
> +#ifdef CONFIG_KVM_BOOKE_HV
> + mtspr(SPRN_GSRR0, srr0);
> + mtspr(SPRN_GSRR1, srr1);
> +#else
> + vcpu->arch.shared->srr0 =3D srr0;
> + vcpu->arch.shared->srr1 =3D srr1;
> +#endif
> +}
> +
> +static void set_guest_csrr(struct kvm_vcpu *vcpu, unsigned long srr0, =
u32 srr1)
> +{
> + vcpu->arch.csrr0 =3D srr0;
> + vcpu->arch.csrr1 =3D srr1;
> +}
> +
> +static void set_guest_dsrr(struct kvm_vcpu *vcpu, unsigned long srr0, =
u32 srr1)
> +{
> + if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) {
> + vcpu->arch.dsrr0 =3D srr0;
> + vcpu->arch.dsrr1 =3D srr1;
> + } else {
> + set_guest_csrr(vcpu, srr0, srr1);
> + }
> +}
> +
> +static void set_guest_mcsrr(struct kvm_vcpu *vcpu, unsigned long =
srr0, u32 srr1)
> +{
> + vcpu->arch.mcsrr0 =3D srr0;
> + vcpu->arch.mcsrr1 =3D srr1;
> +}
> +
> +static unsigned long get_guest_dear(struct kvm_vcpu *vcpu)
> +{
> +#ifdef CONFIG_KVM_BOOKE_HV
> + return mfspr(SPRN_GDEAR);
> +#else
> + return vcpu->arch.shared->dar;
> +#endif
> +}
> +
> +static void set_guest_dear(struct kvm_vcpu *vcpu, unsigned long dear)
> +{
> +#ifdef CONFIG_KVM_BOOKE_HV
> + mtspr(SPRN_GDEAR, dear);
> +#else
> + vcpu->arch.shared->dar =3D dear;
> +#endif
> +}
> +
> +static unsigned long get_guest_esr(struct kvm_vcpu *vcpu)
> +{
> +#ifdef CONFIG_KVM_BOOKE_HV
> + return mfspr(SPRN_ESR);
> +#else
> + return vcpu->arch.shared->esr;
> +#endif
> +}
> +
> +static void set_guest_esr(struct kvm_vcpu *vcpu, u32 esr)
> +{
> +#ifdef CONFIG_KVM_BOOKE_HV
> + mtspr(SPRN_GESR, esr);
> +#else
> + vcpu->arch.shared->esr =3D esr;
> +#endif
> +}
> +
> /* Deliver the interrupt of the corresponding priority, if possible. =
*/
> static int kvmppc_booke_irqprio_deliver(struct kvm_vcpu *vcpu,
> unsigned int priority)
> @@ -208,6 +288,7 @@ static int kvmppc_booke_irqprio_deliver(struct =
kvm_vcpu *vcpu,
> ulong crit_r1 =3D kvmppc_get_gpr(vcpu, 1);
> bool crit;
> bool keep_irq =3D false;
> + enum int_class int_class;
>=20
> /* Truncate crit indicators in 32 bit mode */
> if (!(vcpu->arch.shared->msr & MSR_SF)) {
> @@ -243,16 +324,20 @@ static int kvmppc_booke_irqprio_deliver(struct =
kvm_vcpu *vcpu,
> case BOOKE_IRQPRIO_AP_UNAVAIL:
> case BOOKE_IRQPRIO_ALIGNMENT:
> allowed =3D 1;
> - msr_mask =3D MSR_CE|MSR_ME|MSR_DE;
> + msr_mask =3D MSR_GS | MSR_CE | MSR_ME | MSR_DE;
No need to do this. You already force MSR_GS in set_msr();
> + int_class =3D INT_CLASS_NONCRIT;
> break;
> case BOOKE_IRQPRIO_CRITICAL:
> - case BOOKE_IRQPRIO_WATCHDOG:
> allowed =3D vcpu->arch.shared->msr & MSR_CE;
> - msr_mask =3D MSR_ME;
> + allowed =3D allowed && !crit;
> + msr_mask =3D MSR_GS | MSR_ME;
> + int_class =3D INT_CLASS_CRIT;
> break;
> case BOOKE_IRQPRIO_MACHINE_CHECK:
> allowed =3D vcpu->arch.shared->msr & MSR_ME;
> - msr_mask =3D 0;
> + allowed =3D allowed && !crit;
> + msr_mask =3D MSR_GS;
> + int_class =3D INT_CLASS_MC;
> break;
> case BOOKE_IRQPRIO_DECREMENTER:
> case BOOKE_IRQPRIO_FIT:
> @@ -261,29 +346,63 @@ static int kvmppc_booke_irqprio_deliver(struct =
kvm_vcpu *vcpu,
> case BOOKE_IRQPRIO_EXTERNAL:
> allowed =3D vcpu->arch.shared->msr & MSR_EE;
> allowed =3D allowed && !crit;
> - msr_mask =3D MSR_CE|MSR_ME|MSR_DE;
> + msr_mask =3D MSR_GS | MSR_CE | MSR_ME | MSR_DE;
> + int_class =3D INT_CLASS_NONCRIT;
> break;
> case BOOKE_IRQPRIO_DEBUG:
> allowed =3D vcpu->arch.shared->msr & MSR_DE;
> - msr_mask =3D MSR_ME;
> + allowed =3D allowed && !crit;
> + msr_mask =3D MSR_GS | MSR_ME;
> + int_class =3D INT_CLASS_CRIT;
> break;
> }
>=20
> if (allowed) {
> - vcpu->arch.shared->srr0 =3D vcpu->arch.regs.nip;
> - vcpu->arch.shared->srr1 =3D vcpu->arch.shared->msr;
> + switch (int_class) {
> + case INT_CLASS_NONCRIT:
> + set_guest_srr(vcpu, vcpu->arch.regs.nip,
> + vcpu->arch.shared->msr);
> + break;
> + case INT_CLASS_CRIT:
> + set_guest_csrr(vcpu, vcpu->arch.regs.nip,
> + vcpu->arch.shared->msr);
> + break;
> + case INT_CLASS_DBG:
> + set_guest_dsrr(vcpu, vcpu->arch.regs.nip,
> + vcpu->arch.shared->msr);
> + break;
> + case INT_CLASS_MC:
> + set_guest_mcsrr(vcpu, vcpu->arch.regs.nip,
> + vcpu->arch.shared->msr);
> + break;
> + }
> +
> vcpu->arch.regs.nip =3D vcpu->arch.ivpr |
> vcpu->arch.ivor[priority];
> if (update_esr =3D=3D true)
> - vcpu->arch.shared->esr =3D =
vcpu->arch.queued_esr;
> + set_guest_esr(vcpu, vcpu->arch.queued_esr);
> if (update_dear =3D=3D true)
> - vcpu->arch.shared->dar =3D =
vcpu->arch.queued_dear;
> + set_guest_dear(vcpu, vcpu->arch.queued_dear);
> kvmppc_set_msr(vcpu, vcpu->arch.shared->msr & msr_mask);
>=20
> if (!keep_irq)
> clear_bit(priority, =
&vcpu->arch.pending_exceptions);
> }
>=20
> +#ifdef CONFIG_KVM_BOOKE_HV
> + /*
> + * If an interrupt is pending but masked, raise a guest doorbell
> + * so that we are notified when the guest enables the relevant
> + * MSR bit.
> + */
> + if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_EE)
> + kvmppc_set_pending_interrupt(vcpu, INT_CLASS_NONCRIT);
> + if (vcpu->arch.pending_exceptions & BOOKE_IRQMASK_CE)
> + kvmppc_set_pending_interrupt(vcpu, INT_CLASS_CRIT);
> + if (vcpu->arch.pending_exceptions & BOOKE_IRQPRIO_MACHINE_CHECK)
> + kvmppc_set_pending_interrupt(vcpu, INT_CLASS_MC);
> +#endif
> +
> return allowed;
> }
>=20
> @@ -347,6 +466,11 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, =
struct kvm_vcpu *vcpu)
> return -EINVAL;
> }
>=20
> + if (!current->thread.kvm_vcpu) {
> + WARN(1, "no vcpu\n");
> + return -EPERM;
> + }
Huh?
> +
> local_irq_disable();
>=20
> kvmppc_core_prepare_to_enter(vcpu);
> @@ -366,6 +490,38 @@ out:
> return ret;
> }
>=20
> +static int emulation_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
> +{
> + enum emulation_result er;
> +
> + er =3D kvmppc_emulate_instruction(run, vcpu);
> + switch (er) {
> + case EMULATE_DONE:
> + /* don't overwrite subtypes, just account kvm_stats */
> + kvmppc_account_exit_stat(vcpu, EMULATED_INST_EXITS);
> + /* Future optimization: only reload non-volatiles if
> + * they were actually modified by emulation. */
> + return RESUME_GUEST_NV;
> +
> + case EMULATE_DO_DCR:
> + run->exit_reason =3D KVM_EXIT_DCR;
> + return RESUME_HOST;
> +
> + case EMULATE_FAIL:
> + /* XXX Deliver Program interrupt to guest. */
> + printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
> + __func__, vcpu->arch.regs.nip, =
vcpu->arch.last_inst);
This should be throttled, otherwise the guest can spam our logs.
> + /* For debugging, encode the failing instruction and
> + * report it to userspace. */
> + run->hw.hardware_exit_reason =3D ~0ULL << 32;
> + run->hw.hardware_exit_reason |=3D vcpu->arch.last_inst;
I'm fairly sure you want to fix this :)
> + return RESUME_HOST;
> +
> + default:
> + BUG();
> + }
> +}
> +
> /**
> * kvmppc_handle_exit
> *
> @@ -374,12 +530,39 @@ out:
> int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
> unsigned int exit_nr)
> {
> - enum emulation_result er;
> int r =3D RESUME_HOST;
>=20
> /* update before a new last_exit_type is rewritten */
> kvmppc_update_timing_stats(vcpu);
>=20
> + /*
> + * If we actually care, we could copy MSR, DEAR, and ESR to =
regs,
> + * insert an appropriate trap number, etc.
> + *
> + * Seems like a waste of cycles for something that should only =
matter
> + * to someone using sysrq-t/p or similar host kernel debug =
facility.
> + * We have other debug facilities to get that information from a
> + * guest through userspace.
> + */
> + switch (exit_nr) {
> + case BOOKE_INTERRUPT_EXTERNAL:
> + do_IRQ(&vcpu->arch.regs);
Ah, so that's what you want to use regs for. So is having a pt_regs =
struct that only contains useful register values in half its fields any =
useful here? Or could we keep control of the registers ourselves, =
enabling us to maybe one day optimize things more.
> + break;
> +
> + case BOOKE_INTERRUPT_DECREMENTER:
> + timer_interrupt(&vcpu->arch.regs);
> + break;
> +
> +#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_BOOK3E_64)
> + case BOOKE_INTERRUPT_DOORBELL:
> + doorbell_exception(&vcpu->arch.regs);
> + break;
> +#endif
> + case BOOKE_INTERRUPT_MACHINE_CHECK:
> + /* FIXME */
> + break;
> + }
> +
> local_irq_enable();
>=20
> run->exit_reason =3D KVM_EXIT_UNKNOWN;
> @@ -387,30 +570,56 @@ int kvmppc_handle_exit(struct kvm_run *run, =
struct kvm_vcpu *vcpu,
>=20
> switch (exit_nr) {
> case BOOKE_INTERRUPT_MACHINE_CHECK:
> - printk("MACHINE CHECK: %lx\n", mfspr(SPRN_MCSR));
> - kvmppc_dump_vcpu(vcpu);
> - r =3D RESUME_HOST;
> + kvm_resched(vcpu);
> + r =3D RESUME_GUEST;
huh?
> break;
>=20
> case BOOKE_INTERRUPT_EXTERNAL:
> kvmppc_account_exit(vcpu, EXT_INTR_EXITS);
> - if (need_resched())
> - cond_resched();
> + kvm_resched(vcpu);
Why are we explicit about the resched? On book3s I just call =
kvm_resched(vcpu) before the switch().
> r =3D RESUME_GUEST;
> break;
>=20
> case BOOKE_INTERRUPT_DECREMENTER:
> - /* Since we switched IVPR back to the host's value, the =
host
> - * handled this interrupt the moment we enabled =
interrupts.
> - * Now we just offer it a chance to reschedule the =
guest. */
> kvmppc_account_exit(vcpu, DEC_EXITS);
> - if (need_resched())
> - cond_resched();
> + kvm_resched(vcpu);
> + r =3D RESUME_GUEST;
> + break;
> +
> + case BOOKE_INTERRUPT_DOORBELL:
> + kvmppc_account_exit(vcpu, DBELL_EXITS);
> + kvm_resched(vcpu);
> + r =3D RESUME_GUEST;
> + break;
> +
> + case BOOKE_INTERRUPT_GUEST_DBELL_CRIT:
> + kvmppc_account_exit(vcpu, GDBELL_EXITS);
> +
> + /*
> + * We are here because there is a pending guest =
interrupt
> + * which could not be delivered as MSR_CE or MSR_ME was =
not
> + * set. Once we break from here we will retry delivery.
> + */
> r =3D RESUME_GUEST;
> break;
>=20
> + case BOOKE_INTERRUPT_GUEST_DBELL:
> + kvmppc_account_exit(vcpu, GDBELL_EXITS);
> +
> + /*
> + * We are here because there is a pending guest =
interrupt
> + * which could not be delivered as MSR_EE was not set. =
Once
> + * we break from here we will retry delivery.
> + */
> + r =3D RESUME_GUEST;
> + break;
> +
> + case BOOKE_INTERRUPT_HV_PRIV:
> + r =3D emulation_exit(run, vcpu);
> + break;
> +
> case BOOKE_INTERRUPT_PROGRAM:
> - if (vcpu->arch.shared->msr & MSR_PR) {
> + if (vcpu->arch.shared->msr & (MSR_PR | MSR_GS)) {
> /* Program traps generated by user-level =
software must be handled
> * by the guest kernel. */
> kvmppc_core_queue_program(vcpu, =
vcpu->arch.fault_esr);
> @@ -419,33 +628,7 @@ int kvmppc_handle_exit(struct kvm_run *run, =
struct kvm_vcpu *vcpu,
> break;
> }
>=20
> - er =3D kvmppc_emulate_instruction(run, vcpu);
> - switch (er) {
> - case EMULATE_DONE:
> - /* don't overwrite subtypes, just account =
kvm_stats */
> - kvmppc_account_exit_stat(vcpu, =
EMULATED_INST_EXITS);
> - /* Future optimization: only reload =
non-volatiles if
> - * they were actually modified by emulation. */
> - r =3D RESUME_GUEST_NV;
> - break;
> - case EMULATE_DO_DCR:
> - run->exit_reason =3D KVM_EXIT_DCR;
> - r =3D RESUME_HOST;
> - break;
> - case EMULATE_FAIL:
> - /* XXX Deliver Program interrupt to guest. */
> - printk(KERN_CRIT "%s: emulation at %lx failed =
(%08x)\n",
> - __func__, vcpu->arch.regs.nip,
> - vcpu->arch.last_inst);
> - /* For debugging, encode the failing instruction =
and
> - * report it to userspace. */
> - run->hw.hardware_exit_reason =3D ~0ULL << 32;
> - run->hw.hardware_exit_reason |=3D =
vcpu->arch.last_inst;
> - r =3D RESUME_HOST;
> - break;
> - default:
> - BUG();
> - }
> + r =3D emulation_exit(run, vcpu);
> break;
>=20
> case BOOKE_INTERRUPT_FP_UNAVAIL:
> @@ -510,6 +693,21 @@ int kvmppc_handle_exit(struct kvm_run *run, =
struct kvm_vcpu *vcpu,
> r =3D RESUME_GUEST;
> break;
>=20
> +#ifdef CONFIG_KVM_BOOKE_HV
> + case BOOKE_INTERRUPT_HV_SYSCALL:
> + if (!(vcpu->arch.shared->msr & MSR_PR)) {
> + kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
> + } else {
> + /*
> + * hcall from guest userspace -- send privileged
> + * instruction program check.
> + */
> + kvmppc_core_queue_program(vcpu, ESR_PPR);
> + }
> +
> + r =3D RESUME_GUEST;
> + break;
> +#else
> case BOOKE_INTERRUPT_SYSCALL:
> if (!(vcpu->arch.shared->msr & MSR_PR) &&
> (((u32)kvmppc_get_gpr(vcpu, 0)) =3D=3D =
KVM_SC_MAGIC_R0)) {
> @@ -523,6 +721,47 @@ int kvmppc_handle_exit(struct kvm_run *run, =
struct kvm_vcpu *vcpu,
> kvmppc_account_exit(vcpu, SYSCALL_EXITS);
> r =3D RESUME_GUEST;
> break;
> +#endif
> +
> + case BOOKE_INTERRUPT_ITLB_MISS: {
> + unsigned long eaddr =3D vcpu->arch.regs.nip;
> + gpa_t gpaddr;
> + gfn_t gfn;
> + int gtlb_index;
> +
> + r =3D RESUME_GUEST;
> +
> + /* Check the guest TLB. */
> + gtlb_index =3D kvmppc_mmu_itlb_index(vcpu, eaddr);
> + if (gtlb_index < 0) {
> + /* The guest didn't have a mapping for it. */
> + kvmppc_booke_queue_irqprio(vcpu,
> + =
BOOKE_IRQPRIO_ITLB_MISS);
> + kvmppc_mmu_itlb_miss(vcpu);
> + kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
> + break;
> + }
> +
> + kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
> +
> + gpaddr =3D kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
> + gfn =3D gpaddr >> PAGE_SHIFT;
> +
> + if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
> + /* The guest TLB had a mapping, but the shadow =
TLB
> + * didn't. This could be because:
> + * a) the entry is mapping the host kernel, or
> + * b) the guest used a large mapping which we're =
faking
> + * Either way, we need to satisfy the fault =
without
> + * invoking the guest. */
> + kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
> + } else {
> + /* Guest mapped and leaped at non-RAM! */
> + kvmppc_booke_queue_irqprio(vcpu,
> + =
BOOKE_IRQPRIO_MACHINE_CHECK);
Are you sure? Couldn't this also be MMIO? That doesn't really improve =
the situation as executing from MMIO is tricky with the KVM model, but =
it's not necessarily bad. Oh well, I guess we'll have to do something =
and throwing an #MC isn't all that ugly.
> + }
> + break;
> + }
>=20
> case BOOKE_INTERRUPT_DTLB_MISS: {
> unsigned long eaddr =3D vcpu->arch.fault_dear;
> @@ -578,45 +817,6 @@ int kvmppc_handle_exit(struct kvm_run *run, =
struct kvm_vcpu *vcpu,
> break;
> }
>=20
> - case BOOKE_INTERRUPT_ITLB_MISS: {
> - unsigned long eaddr =3D vcpu->arch.regs.nip;
> - gpa_t gpaddr;
> - gfn_t gfn;
> - int gtlb_index;
> -
> - r =3D RESUME_GUEST;
> -
> - /* Check the guest TLB. */
> - gtlb_index =3D kvmppc_mmu_itlb_index(vcpu, eaddr);
> - if (gtlb_index < 0) {
> - /* The guest didn't have a mapping for it. */
> - kvmppc_booke_queue_irqprio(vcpu, =
BOOKE_IRQPRIO_ITLB_MISS);
> - kvmppc_mmu_itlb_miss(vcpu);
> - kvmppc_account_exit(vcpu, ITLB_REAL_MISS_EXITS);
> - break;
> - }
> -
> - kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
> -
> - gpaddr =3D kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
> - gfn =3D gpaddr >> PAGE_SHIFT;
> -
> - if (kvm_is_visible_gfn(vcpu->kvm, gfn)) {
> - /* The guest TLB had a mapping, but the shadow =
TLB
> - * didn't. This could be because:
> - * a) the entry is mapping the host kernel, or
> - * b) the guest used a large mapping which we're =
faking
> - * Either way, we need to satisfy the fault =
without
> - * invoking the guest. */
> - kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
> - } else {
> - /* Guest mapped and leaped at non-RAM! */
> - kvmppc_booke_queue_irqprio(vcpu, =
BOOKE_IRQPRIO_MACHINE_CHECK);
Ah, you just shoved the code around :)
> - }
> -
> - break;
> - }
> -
> case BOOKE_INTERRUPT_DEBUG: {
> u32 dbsr;
>=20
> @@ -663,12 +863,15 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
> int r;
>=20
> vcpu->arch.regs.nip =3D 0;
> - vcpu->arch.shared->msr =3D 0;
> - vcpu->arch.shadow_msr =3D MSR_USER | MSR_DE | MSR_IS | MSR_DS;
> vcpu->arch.shared->pir =3D vcpu->vcpu_id;
> kvmppc_set_gpr(vcpu, 1, (16<<20) - 8); /* -8 for the callee-save =
LR slot */
> + kvmppc_set_msr(vcpu, 0);
>=20
> +#ifndef CONFIG_KVM_BOOKE_HV
> + vcpu->arch.shadow_msr =3D MSR_USER | MSR_DE | MSR_IS | MSR_DS;
> vcpu->arch.shadow_pid =3D 1;
> + vcpu->arch.shared->msr =3D 0;
> +#endif
>=20
> /* Eye-catching numbers so we know if the guest takes an =
interrupt
> * before it's programmed its own IVPR/IVORs. */
> @@ -749,8 +952,8 @@ static void get_sregs_base(struct kvm_vcpu *vcpu,
> sregs->u.e.csrr0 =3D vcpu->arch.csrr0;
> sregs->u.e.csrr1 =3D vcpu->arch.csrr1;
> sregs->u.e.mcsr =3D vcpu->arch.mcsr;
> - sregs->u.e.esr =3D vcpu->arch.shared->esr;
> - sregs->u.e.dear =3D vcpu->arch.shared->dar;
> + sregs->u.e.esr =3D get_guest_esr(vcpu);
> + sregs->u.e.dear =3D get_guest_dear(vcpu);
> sregs->u.e.tsr =3D vcpu->arch.tsr;
> sregs->u.e.tcr =3D vcpu->arch.tcr;
> sregs->u.e.dec =3D kvmppc_get_dec(vcpu, tb);
> @@ -767,8 +970,8 @@ static int set_sregs_base(struct kvm_vcpu *vcpu,
> vcpu->arch.csrr0 =3D sregs->u.e.csrr0;
> vcpu->arch.csrr1 =3D sregs->u.e.csrr1;
> vcpu->arch.mcsr =3D sregs->u.e.mcsr;
> - vcpu->arch.shared->esr =3D sregs->u.e.esr;
> - vcpu->arch.shared->dar =3D sregs->u.e.dear;
> + set_guest_esr(vcpu, sregs->u.e.esr);
> + set_guest_dear(vcpu, sregs->u.e.dear);
> vcpu->arch.vrsave =3D sregs->u.e.vrsave;
> kvmppc_set_tcr(vcpu, sregs->u.e.tcr);
>=20
> @@ -965,14 +1168,17 @@ void kvmppc_decrementer_func(unsigned long =
data)
>=20
> void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
> {
> + current->thread.kvm_vcpu =3D vcpu;
> }
>=20
> void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu)
> {
> + current->thread.kvm_vcpu =3D NULL;
> }
>=20
> int __init kvmppc_booke_init(void)
> {
> +#ifndef CONFIG_KVM_BOOKE_HV
> unsigned long ivor[16];
> unsigned long max_ivor =3D 0;
> int i;
> @@ -1015,7 +1221,7 @@ int __init kvmppc_booke_init(void)
> }
> flush_icache_range(kvmppc_booke_handlers,
> kvmppc_booke_handlers + max_ivor + =
kvmppc_handler_len);
> -
> +#endif /* !BOOKE_HV */
> return 0;
> }
>=20
> diff --git a/arch/powerpc/kvm/booke.h b/arch/powerpc/kvm/booke.h
> index 05d1d99..d53bcf2 100644
> --- a/arch/powerpc/kvm/booke.h
> +++ b/arch/powerpc/kvm/booke.h
> @@ -48,7 +48,20 @@
> #define BOOKE_IRQPRIO_PERFORMANCE_MONITOR 19
> /* Internal pseudo-irqprio for level triggered externals */
> #define BOOKE_IRQPRIO_EXTERNAL_LEVEL 20
> -#define BOOKE_IRQPRIO_MAX 20
> +#define BOOKE_IRQPRIO_DBELL 21
> +#define BOOKE_IRQPRIO_DBELL_CRIT 22
> +#define BOOKE_IRQPRIO_MAX 23
So was MAX wrong before or is it too big now?
> +
> +#define BOOKE_IRQMASK_EE ((1 << BOOKE_IRQPRIO_EXTERNAL_LEVEL) | \
> + (1 << BOOKE_IRQPRIO_PERFORMANCE_MONITOR) | \
> + (1 << BOOKE_IRQPRIO_DBELL) | \
> + (1 << BOOKE_IRQPRIO_DECREMENTER) | \
> + (1 << BOOKE_IRQPRIO_FIT) | \
> + (1 << BOOKE_IRQPRIO_EXTERNAL))
> +
> +#define BOOKE_IRQMASK_CE ((1 << BOOKE_IRQPRIO_DBELL_CRIT) | \
> + (1 << BOOKE_IRQPRIO_WATCHDOG) | \
> + (1 << BOOKE_IRQPRIO_CRITICAL))
>=20
> extern unsigned long kvmppc_booke_handlers;
>=20
> @@ -74,4 +87,13 @@ void kvmppc_vcpu_disable_spe(struct kvm_vcpu =
*vcpu);
> void kvmppc_booke_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
> void kvmppc_booke_vcpu_put(struct kvm_vcpu *vcpu);
>=20
> +enum int_class {
> + INT_CLASS_NONCRIT,
> + INT_CLASS_CRIT,
> + INT_CLASS_MC,
> + INT_CLASS_DBG,
> +};
> +
> +void kvmppc_set_pending_interrupt(struct kvm_vcpu *vcpu, enum =
int_class type);
> +
> #endif /* __KVM_BOOKE_H__ */
> diff --git a/arch/powerpc/kvm/booke_emulate.c =
b/arch/powerpc/kvm/booke_emulate.c
> index a4af03b..3eb7fc6 100644
> --- a/arch/powerpc/kvm/booke_emulate.c
> +++ b/arch/powerpc/kvm/booke_emulate.c
> @@ -99,6 +99,12 @@ int kvmppc_booke_emulate_op(struct kvm_run *run, =
struct kvm_vcpu *vcpu,
> return emulated;
> }
>=20
> +/*
> + * NOTE: some of these registers are not emulated on BOOKE_HV =
(GS-mode).
> + * Their backing store is in real registers, and these functions
> + * will return the wrong result if called for them in another context
> + * (such as debugging).
> + */
> int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int =
rs)
> {
> int emulated =3D EMULATE_DONE;
> @@ -122,9 +128,11 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu =
*vcpu, int sprn, int rs)
> kvmppc_set_tcr(vcpu, spr_val);
> break;
>=20
> - /* Note: SPRG4-7 are user-readable. These values are
> - * loaded into the real SPRGs when resuming the
> - * guest. */
> + /*
> + * Note: SPRG4-7 are user-readable.
> + * These values are loaded into the real SPRGs when resuming the
> + * guest (PR-mode only).
> + */
> case SPRN_SPRG4:
> vcpu->arch.shared->sprg4 =3D spr_val; break;
> case SPRN_SPRG5:
> @@ -136,6 +144,9 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu =
*vcpu, int sprn, int rs)
>=20
> case SPRN_IVPR:
> vcpu->arch.ivpr =3D spr_val;
> +#ifdef CONFIG_KVM_BOOKE_HV
> + mtspr(SPRN_GIVPR, spr_val);
> +#endif
> break;
> case SPRN_IVOR0:
> vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] =3D spr_val;
> @@ -145,6 +156,9 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu =
*vcpu, int sprn, int rs)
> break;
> case SPRN_IVOR2:
> vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] =3D spr_val;
> +#ifdef CONFIG_KVM_BOOKE_HV
> + mtspr(SPRN_GIVOR2, spr_val);
> +#endif
> break;
> case SPRN_IVOR3:
> vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] =3D spr_val;
> @@ -163,6 +177,9 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu =
*vcpu, int sprn, int rs)
> break;
> case SPRN_IVOR8:
> vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] =3D spr_val;
> +#ifdef CONFIG_KVM_BOOKE_HV
> + mtspr(SPRN_GIVOR8, spr_val);
> +#endif
> break;
> case SPRN_IVOR9:
> vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] =3D spr_val;
> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S =
b/arch/powerpc/kvm/bookehv_interrupts.S
> new file mode 100644
> index 0000000..9eaeebd
> --- /dev/null
> +++ b/arch/powerpc/kvm/bookehv_interrupts.S
> @@ -0,0 +1,587 @@
> +/*
> + * This program is free software; you can redistribute it and/or =
modify
> + * it under the terms of the GNU General Public License, version 2, =
as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA =
02110-1301, USA.
> + *
> + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
> + *
> + * Author: Varun Sethi <varun.sethi@freescale.com>
> + * Author: Scott Wood <scotwood@freescale.com>
> + *
> + * This file is derived from arch/powerpc/kvm/booke_interrupts.S
> + */
> +
> +#include <asm/ppc_asm.h>
> +#include <asm/kvm_asm.h>
> +#include <asm/reg.h>
> +#include <asm/mmu-44x.h>
> +#include <asm/page.h>
> +#include <asm/asm-compat.h>
> +#include <asm/asm-offsets.h>
> +#include <asm/bitsperlong.h>
> +
> +#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
> +
> +#define GET_VCPU(vcpu, thread) \
> + PPC_LL vcpu, THREAD_KVM_VCPU(thread)
> +
> +#define SET_VCPU(vcpu) \
> + PPC_STL vcpu, (THREAD + THREAD_KVM_VCPU)(r2)
> +
> +#define LONGBYTES (BITS_PER_LONG / 8)
> +
> +#define VCPU_GPR(n) (VCPU_GPRS + (n * LONGBYTES))
> +#define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
> +
> +/* The host stack layout: */
> +#define HOST_R1 (0 * LONGBYTES) /* Implied by stwu. */
> +#define HOST_CALLEE_LR (1 * LONGBYTES)
> +#define HOST_RUN (2 * LONGBYTES) /* struct kvm_run */
> +/*
> + * r2 is special: it holds 'current', and it made nonvolatile in the
> + * kernel with the -ffixed-r2 gcc option.
> + */
> +#define HOST_R2 (3 * LONGBYTES)
> +#define HOST_NV_GPRS (4 * LONGBYTES)
> +#define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
> +#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
> +#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. =
*/
> +#define HOST_STACK_LR (HOST_STACK_SIZE + LONGBYTES) /* In caller =
stack frame. */
> +
> +#define NEED_EMU 0x00000001 /* emulation -- save nv regs =
*/
> +#define NEED_DEAR 0x00000002 /* save faulting DEAR */
> +#define NEED_ESR 0x00000004 /* save faulting ESR */
> +
> +/*
> + * On entry:
> + * r4 =3D vcpu, r5 =3D srr0, r6 =3D srr1
> + * saved in vcpu: cr, ctr, r3-r13
> + */
> +.macro kvm_handler_common intno, srr0, flags
> + mfspr r10, SPRN_PID
> + lwz r8, VCPU_HOST_PID(r4)
> + PPC_LL r11, VCPU_SHARED(r4)
> + PPC_STL r14, VCPU_GPR(r14)(r4) /* We need a non-volatile GPR. */
> + li r14, \intno
> +
> + stw r10, VCPU_GUEST_PID(r4)
> + mtspr SPRN_PID, r8
> +
> + .if \flags & NEED_EMU
> + lwz r9, VCPU_KVM(r4)
writing r9
> + .endif
> +
> +#ifdef CONFIG_KVM_EXIT_TIMING
> + /* save exit time */
> +1: mfspr r7, SPRN_TBRU
> + mfspr r8, SPRN_TBRL
> + mfspr r9, SPRN_TBRU
overwriting r9 again?
> + cmpw r9, r7
> + PPC_STL r8, VCPU_TIMING_EXIT_TBL(r4)
> + bne- 1b
> + PPC_STL r9, VCPU_TIMING_EXIT_TBU(r4)
> +#endif
> +
> + oris r8, r6, MSR_CE@h
> +#ifndef CONFIG_64BIT
Double negation is always hard to read. Please reverse the ifdef :)
> + stw r6, (VCPU_SHARED_MSR + 4)(r11)
> +#else
> + std r6, (VCPU_SHARED_MSR)(r11)
> +#endif
> + ori r8, r8, MSR_ME | MSR_RI
> + PPC_STL r5, VCPU_PC(r4)
> +
> + /*
> + * Make sure CE/ME/RI are set (if appropriate for exception =
type)
> + * whether or not the guest had it set. Since mfmsr/mtmsr are
> + * somewhat expensive, skip in the common case where the guest
> + * had all these bits set (and thus they're still set if
> + * appropriate for the exception type).
> + */
> + cmpw r6, r8
> + .if \flags & NEED_EMU
> + lwz r9, KVM_LPID(r9)
And here r9 is already clobbered
> + .endif
> + beq 1f
> + mfmsr r7
> + .if \srr0 !=3D SPRN_MCSRR0 && \srr0 !=3D SPRN_CSRR0
> + oris r7, r7, MSR_CE@h
> + .endif
> + .if \srr0 !=3D SPRN_MCSRR0
> + ori r7, r7, MSR_ME | MSR_RI
> + .endif
> + mtmsr r7
> +1:
> +
> + .if \flags & NEED_EMU
> + /*
> + * This assumes you have external PID support.
> + * To support a bookehv CPU without external PID, you'll
> + * need to look up the TLB entry and create a temporary mapping.
> + *
> + * FIXME: we don't currently handle if the lwepx faults. =
PR-mode
> + * booke doesn't handle it either. Since Linux doesn't use
> + * broadcast tlbivax anymore, the only way this should happen is
> + * if the guest maps its memory execute-but-not-read, or if we
> + * somehow take a TLB miss in the middle of this entry code and
> + * evict the relevant entry. On e500mc, all kernel lowmem is
> + * bolted into TLB1 large page mappings, and we don't use
> + * broadcast invalidates, so we should not take a TLB miss here.
> + *
> + * Later we'll need to deal with faults here. Disallowing guest
> + * mappings that are execute-but-not-read could be an option on
> + * e500mc, but not on chips with an LRAT if it is used.
> + */
> +
> + mfspr r3, SPRN_EPLC /* will already have correct ELPID and =
EGS */
> + PPC_STL r15, VCPU_GPR(r15)(r4)
> + PPC_STL r16, VCPU_GPR(r16)(r4)
> + PPC_STL r17, VCPU_GPR(r17)(r4)
> + PPC_STL r18, VCPU_GPR(r18)(r4)
> + PPC_STL r19, VCPU_GPR(r19)(r4)
> + mr r8, r3
> + PPC_STL r20, VCPU_GPR(r20)(r4)
> + rlwimi r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
> + PPC_STL r21, VCPU_GPR(r21)(r4)
> + rlwimi r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
> + PPC_STL r22, VCPU_GPR(r22)(r4)
> + rlwimi r8, r10, EPC_EPID_SHIFT, EPC_EPID
> + PPC_STL r23, VCPU_GPR(r23)(r4)
> + PPC_STL r24, VCPU_GPR(r24)(r4)
> + PPC_STL r25, VCPU_GPR(r25)(r4)
> + PPC_STL r26, VCPU_GPR(r26)(r4)
> + PPC_STL r27, VCPU_GPR(r27)(r4)
> + PPC_STL r28, VCPU_GPR(r28)(r4)
> + PPC_STL r29, VCPU_GPR(r29)(r4)
> + PPC_STL r30, VCPU_GPR(r30)(r4)
> + PPC_STL r31, VCPU_GPR(r31)(r4)
> + mtspr SPRN_EPLC, r8
> + isync
> + lwepx r9, 0, r5
> + mtspr SPRN_EPLC, r3
> + stw r9, VCPU_LAST_INST(r4)
> + .endif
> +
> + .if \flags & NEED_ESR
> + mfspr r8, SPRN_ESR
> + PPC_STL r8, VCPU_FAULT_ESR(r4)
> + .endif
> +
> + .if \flags & NEED_DEAR
> + mfspr r9, SPRN_DEAR
> + PPC_STL r9, VCPU_FAULT_DEAR(r4)
> + .endif
> +
> + b kvmppc_resume_host
> +.endm
> +
> +/*
> + * For input register values, see =
arch/powerpc/include/asm/kvm_booke_hv_asm.h
> + */
> +.macro kvm_handler intno srr0, srr1, flags
> +_GLOBAL(kvmppc_handler_\intno\()_\srr1)
> + GET_VCPU(r11, r10)
> + PPC_STL r3, VCPU_GPR(r3)(r11)
> + mfspr r3, SPRN_SPRG_RSCRATCH0
> + PPC_STL r4, VCPU_GPR(r4)(r11)
> + PPC_LL r4, THREAD_NORMSAVE(0)(r10)
> + PPC_STL r5, VCPU_GPR(r5)(r11)
> + PPC_STL r13, VCPU_CR(r11)
> + mfspr r5, \srr0
> + PPC_STL r3, VCPU_GPR(r10)(r11)
> + PPC_LL r3, THREAD_NORMSAVE(2)(r10)
> + PPC_STL r6, VCPU_GPR(r6)(r11)
> + PPC_STL r4, VCPU_GPR(r11)(r11)
> + mfspr r6, \srr1
> + PPC_STL r7, VCPU_GPR(r7)(r11)
> + PPC_STL r8, VCPU_GPR(r8)(r11)
> + PPC_STL r9, VCPU_GPR(r9)(r11)
> + PPC_STL r3, VCPU_GPR(r13)(r11)
> + mfctr r7
> + PPC_STL r12, VCPU_GPR(r12)(r11)
> + PPC_STL r7, VCPU_CTR(r11)
> + mr r4, r11
> + kvm_handler_common \intno, \srr0, \flags
> +.endm
> +
> +.macro kvm_lvl_handler intno scratch srr0, srr1, flags
> +_GLOBAL(kvmppc_handler_\intno\()_\srr1)
> + mfspr r10, SPRN_SPRG_THREAD
> + GET_VCPU(r11, r10)
> + PPC_STL r3, VCPU_GPR(r3)(r11)
> + mfspr r3, \scratch
> + PPC_STL r4, VCPU_GPR(r4)(r11)
> + PPC_LL r4, GPR9(r8)
> + PPC_STL r5, VCPU_GPR(r5)(r11)
> + PPC_STL r9, VCPU_CR(r11)
> + mfspr r5, \srr0
> + PPC_STL r3, VCPU_GPR(r8)(r11)
> + PPC_LL r3, GPR10(r8)
> + PPC_STL r6, VCPU_GPR(r6)(r11)
> + PPC_STL r4, VCPU_GPR(r9)(r11)
> + mfspr r6, \srr1
> + PPC_LL r4, GPR11(r8)
> + PPC_STL r7, VCPU_GPR(r7)(r11)
> + PPC_STL r8, VCPU_GPR(r8)(r11)
> + PPC_STL r3, VCPU_GPR(r10)(r11)
> + mfctr r7
> + PPC_STL r12, VCPU_GPR(r12)(r11)
> + PPC_STL r4, VCPU_GPR(r11)(r11)
> + PPC_STL r7, VCPU_CTR(r11)
> + mr r4, r11
> + kvm_handler_common \intno, \srr0, \flags
> +.endm
> +
> +kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
> + SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
> +kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
> + SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
> +kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
> + SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR)
> +kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, =
NEED_ESR
> +kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
> + SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
> +kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
> +kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
> + SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
> +kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
> + SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
> +kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, =
SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
> + SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
> +kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
> +kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
> +kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
> +kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
> + SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
> +kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
> + SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
> +kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
> + SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
> +
> +
> +/* Registers:
> + * SPRG_SCRATCH0: guest r10
> + * r4: vcpu pointer
> + * r11: vcpu->arch.shared
> + * r14: KVM exit number
> + */
> +_GLOBAL(kvmppc_resume_host)
> + /* Save remaining volatile guest register state to vcpu. */
> + mfspr r3, SPRN_VRSAVE
> + PPC_STL r0, VCPU_GPR(r0)(r4)
> + PPC_STL r1, VCPU_GPR(r1)(r4)
> + mflr r5
> + mfspr r6, SPRN_SPRG4
> + PPC_STL r2, VCPU_GPR(r2)(r4)
> + PPC_STL r5, VCPU_LR(r4)
> + mfspr r7, SPRN_SPRG5
> + PPC_STL r3, VCPU_VRSAVE(r4)
> + PPC_STL r6, VCPU_SHARED_SPRG4(r11)
> + mfspr r8, SPRN_SPRG6
> + PPC_STL r7, VCPU_SHARED_SPRG5(r11)
> + mfspr r9, SPRN_SPRG7
> + PPC_STL r8, VCPU_SHARED_SPRG6(r11)
> + mfxer r3
> + PPC_STL r9, VCPU_SHARED_SPRG7(r11)
> +
> + /* save guest MAS registers and restore host mas4 & mas6 */
> + mfspr r5, SPRN_MAS0
> + PPC_STL r3, VCPU_XER(r4)
> + mfspr r6, SPRN_MAS1
> + stw r5, VCPU_SHARED_MAS0(r11)
> + mfspr r7, SPRN_MAS2
> + stw r6, VCPU_SHARED_MAS1(r11)
> +#ifndef CONFIG_64BIT
see above
> + stw r7, (VCPU_SHARED_MAS2 + 4)(r11)
> +#else
> + std r7, (VCPU_SHARED_MAS2)(r11)
> +#endif
> + mfspr r5, SPRN_MAS3
> + mfspr r6, SPRN_MAS4
> + stw r5, VCPU_SHARED_MAS7_3+4(r11)
> + mfspr r7, SPRN_MAS6
> + stw r6, VCPU_SHARED_MAS4(r11)
> + mfspr r5, SPRN_MAS7
> + lwz r6, VCPU_HOST_MAS4(r4)
> + stw r7, VCPU_SHARED_MAS6(r11)
> + lwz r8, VCPU_HOST_MAS6(r4)
> + mtspr SPRN_MAS4, r6
> + stw r5, VCPU_SHARED_MAS7_3+0(r11)
> + mtspr SPRN_MAS6, r8
> + mfspr r3, SPRN_EPCR
> + rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH
> + mtspr SPRN_EPCR, r3
> + isync
> +
> + /* Restore host stack pointer */
> + PPC_LL r1, VCPU_HOST_STACK(r4)
> + PPC_LL r2, HOST_R2(r1)
> +
> + /* Switch to kernel stack and jump to handler. */
> + PPC_LL r3, HOST_RUN(r1)
> + mr r5, r14 /* intno */
> + mr r14, r4 /* Save vcpu pointer. */
> + bl kvmppc_handle_exit
> +
> + /* Restore vcpu pointer and the nonvolatiles we used. */
> + mr r4, r14
> + PPC_LL r14, VCPU_GPR(r14)(r4)
> +
> + andi. r5, r3, RESUME_FLAG_NV
> + beq skip_nv_load
> + PPC_LL r15, VCPU_GPR(r15)(r4)
> + PPC_LL r16, VCPU_GPR(r16)(r4)
> + PPC_LL r17, VCPU_GPR(r17)(r4)
> + PPC_LL r18, VCPU_GPR(r18)(r4)
> + PPC_LL r19, VCPU_GPR(r19)(r4)
> + PPC_LL r20, VCPU_GPR(r20)(r4)
> + PPC_LL r21, VCPU_GPR(r21)(r4)
> + PPC_LL r22, VCPU_GPR(r22)(r4)
> + PPC_LL r23, VCPU_GPR(r23)(r4)
> + PPC_LL r24, VCPU_GPR(r24)(r4)
> + PPC_LL r25, VCPU_GPR(r25)(r4)
> + PPC_LL r26, VCPU_GPR(r26)(r4)
> + PPC_LL r27, VCPU_GPR(r27)(r4)
> + PPC_LL r28, VCPU_GPR(r28)(r4)
> + PPC_LL r29, VCPU_GPR(r29)(r4)
> + PPC_LL r30, VCPU_GPR(r30)(r4)
> + PPC_LL r31, VCPU_GPR(r31)(r4)
> +skip_nv_load:
> + /* Should we return to the guest? */
> + andi. r5, r3, RESUME_FLAG_HOST
> + beq lightweight_exit
> +
> + srawi r3, r3, 2 /* Shift -ERR back down. */
> +
> +heavyweight_exit:
> + /* Not returning to guest. */
> + PPC_LL r5, HOST_STACK_LR(r1)
> +
> + /*
> + * We already saved guest volatile register state; now save the
> + * non-volatiles.
> + */
> +
> + PPC_STL r15, VCPU_GPR(r15)(r4)
> + PPC_STL r16, VCPU_GPR(r16)(r4)
> + PPC_STL r17, VCPU_GPR(r17)(r4)
> + PPC_STL r18, VCPU_GPR(r18)(r4)
> + PPC_STL r19, VCPU_GPR(r19)(r4)
> + PPC_STL r20, VCPU_GPR(r20)(r4)
> + PPC_STL r21, VCPU_GPR(r21)(r4)
> + PPC_STL r22, VCPU_GPR(r22)(r4)
> + PPC_STL r23, VCPU_GPR(r23)(r4)
> + PPC_STL r24, VCPU_GPR(r24)(r4)
> + PPC_STL r25, VCPU_GPR(r25)(r4)
> + PPC_STL r26, VCPU_GPR(r26)(r4)
> + PPC_STL r27, VCPU_GPR(r27)(r4)
> + PPC_STL r28, VCPU_GPR(r28)(r4)
> + PPC_STL r29, VCPU_GPR(r29)(r4)
> + PPC_STL r30, VCPU_GPR(r30)(r4)
> + PPC_STL r31, VCPU_GPR(r31)(r4)
> +
> + /* Load host non-volatile register state from host stack. */
> + PPC_LL r14, HOST_NV_GPR(r14)(r1)
> + PPC_LL r15, HOST_NV_GPR(r15)(r1)
> + PPC_LL r16, HOST_NV_GPR(r16)(r1)
> + PPC_LL r17, HOST_NV_GPR(r17)(r1)
> + PPC_LL r18, HOST_NV_GPR(r18)(r1)
> + PPC_LL r19, HOST_NV_GPR(r19)(r1)
> + PPC_LL r20, HOST_NV_GPR(r20)(r1)
> + PPC_LL r21, HOST_NV_GPR(r21)(r1)
> + PPC_LL r22, HOST_NV_GPR(r22)(r1)
> + PPC_LL r23, HOST_NV_GPR(r23)(r1)
> + PPC_LL r24, HOST_NV_GPR(r24)(r1)
> + PPC_LL r25, HOST_NV_GPR(r25)(r1)
> + PPC_LL r26, HOST_NV_GPR(r26)(r1)
> + PPC_LL r27, HOST_NV_GPR(r27)(r1)
> + PPC_LL r28, HOST_NV_GPR(r28)(r1)
> + PPC_LL r29, HOST_NV_GPR(r29)(r1)
> + PPC_LL r30, HOST_NV_GPR(r30)(r1)
> + PPC_LL r31, HOST_NV_GPR(r31)(r1)
> +
> + /* Return to kvm_vcpu_run(). */
> + mtlr r5
> + addi r1, r1, HOST_STACK_SIZE
> + /* r3 still contains the return code from kvmppc_handle_exit(). =
*/
> + blr
> +
> +/* Registers:
> + * r3: kvm_run pointer
> + * r4: vcpu pointer
> + */
> +_GLOBAL(__kvmppc_vcpu_run)
> + stwu r1, -HOST_STACK_SIZE(r1)
> + PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. =
*/
> +
> + /* Save host state to stack. */
> + PPC_STL r3, HOST_RUN(r1)
> + mflr r3
> + PPC_STL r3, HOST_STACK_LR(r1)
> +
> + /* Save host non-volatile register state to stack. */
> + PPC_STL r14, HOST_NV_GPR(r14)(r1)
> + PPC_STL r15, HOST_NV_GPR(r15)(r1)
> + PPC_STL r16, HOST_NV_GPR(r16)(r1)
> + PPC_STL r17, HOST_NV_GPR(r17)(r1)
> + PPC_STL r18, HOST_NV_GPR(r18)(r1)
> + PPC_STL r19, HOST_NV_GPR(r19)(r1)
> + PPC_STL r20, HOST_NV_GPR(r20)(r1)
> + PPC_STL r21, HOST_NV_GPR(r21)(r1)
> + PPC_STL r22, HOST_NV_GPR(r22)(r1)
> + PPC_STL r23, HOST_NV_GPR(r23)(r1)
> + PPC_STL r24, HOST_NV_GPR(r24)(r1)
> + PPC_STL r25, HOST_NV_GPR(r25)(r1)
> + PPC_STL r26, HOST_NV_GPR(r26)(r1)
> + PPC_STL r27, HOST_NV_GPR(r27)(r1)
> + PPC_STL r28, HOST_NV_GPR(r28)(r1)
> + PPC_STL r29, HOST_NV_GPR(r29)(r1)
> + PPC_STL r30, HOST_NV_GPR(r30)(r1)
> + PPC_STL r31, HOST_NV_GPR(r31)(r1)
> +
> + /* Load guest non-volatiles. */
> + PPC_LL r14, VCPU_GPR(r14)(r4)
> + PPC_LL r15, VCPU_GPR(r15)(r4)
> + PPC_LL r16, VCPU_GPR(r16)(r4)
> + PPC_LL r17, VCPU_GPR(r17)(r4)
> + PPC_LL r18, VCPU_GPR(r18)(r4)
> + PPC_LL r19, VCPU_GPR(r19)(r4)
> + PPC_LL r20, VCPU_GPR(r20)(r4)
> + PPC_LL r21, VCPU_GPR(r21)(r4)
> + PPC_LL r22, VCPU_GPR(r22)(r4)
> + PPC_LL r23, VCPU_GPR(r23)(r4)
> + PPC_LL r24, VCPU_GPR(r24)(r4)
> + PPC_LL r25, VCPU_GPR(r25)(r4)
> + PPC_LL r26, VCPU_GPR(r26)(r4)
> + PPC_LL r27, VCPU_GPR(r27)(r4)
> + PPC_LL r28, VCPU_GPR(r28)(r4)
> + PPC_LL r29, VCPU_GPR(r29)(r4)
> + PPC_LL r30, VCPU_GPR(r30)(r4)
> + PPC_LL r31, VCPU_GPR(r31)(r4)
> +
> +
> +lightweight_exit:
> + PPC_STL r2, HOST_R2(r1)
> +
> + mfspr r3, SPRN_PID
> + stw r3, VCPU_HOST_PID(r4)
> + lwz r3, VCPU_GUEST_PID(r4)
> + mtspr SPRN_PID, r3
> +
> + /* Save vcpu pointer for the exception handlers
> + * must be done before loading guest r2.
> + */
> +// SET_VCPU(r4)
hm?
> +
> + PPC_LL r11, VCPU_SHARED(r4)
> + /* Save host mas4 and mas6 and load guest MAS registers */
> + mfspr r3, SPRN_MAS4
> + stw r3, VCPU_HOST_MAS4(r4)
> + mfspr r3, SPRN_MAS6
> + stw r3, VCPU_HOST_MAS6(r4)
> + lwz r3, VCPU_SHARED_MAS0(r11)
> + lwz r5, VCPU_SHARED_MAS1(r11)
> +#ifndef CONFIG_64BIT
see above
> + lwz r6, (VCPU_SHARED_MAS2 + 4)(r11)
> +#else
> + ld r6, (VCPU_SHARED_MAS2)(r11)
> +#endif
> + lwz r7, VCPU_SHARED_MAS7_3+4(r11)
> + lwz r8, VCPU_SHARED_MAS4(r11)
> + mtspr SPRN_MAS0, r3
> + mtspr SPRN_MAS1, r5
> + mtspr SPRN_MAS2, r6
> + mtspr SPRN_MAS3, r7
> + mtspr SPRN_MAS4, r8
> + lwz r3, VCPU_SHARED_MAS6(r11)
> + lwz r5, VCPU_SHARED_MAS7_3+0(r11)
> + mtspr SPRN_MAS6, r3
> + mtspr SPRN_MAS7, r5
> + /* Disable MAS register updates via exception */
> + mfspr r3, SPRN_EPCR
> + oris r3, r3, SPRN_EPCR_DMIUH@h
> + mtspr SPRN_EPCR, r3
Shouldn't this happen before you set the MAS registers? :)
> +
> + /*
> + * Host interrupt handlers may have clobbered these =
guest-readable
> + * SPRGs, so we need to reload them here with the guest's =
values.
> + */
> + lwz r3, VCPU_VRSAVE(r4)
> + lwz r5, VCPU_SHARED_SPRG4(r11)
> + mtspr SPRN_VRSAVE, r3
> + lwz r6, VCPU_SHARED_SPRG5(r11)
> + mtspr SPRN_SPRG4W, r5
> + lwz r7, VCPU_SHARED_SPRG6(r11)
> + mtspr SPRN_SPRG5W, r6
> + lwz r8, VCPU_SHARED_SPRG7(r11)
> + mtspr SPRN_SPRG6W, r7
> + mtspr SPRN_SPRG7W, r8
> +
> + /* Load some guest volatiles. */
> + PPC_LL r3, VCPU_LR(r4)
> + PPC_LL r5, VCPU_XER(r4)
> + PPC_LL r6, VCPU_CTR(r4)
> + PPC_LL r7, VCPU_CR(r4)
> + PPC_LL r8, VCPU_PC(r4)
> +#ifndef CONFIG_64BIT
> + lwz r9, (VCPU_SHARED_MSR + 4)(r11)
> +#else
> + ld r9, (VCPU_SHARED_MSR)(r11)
> +#endif
> + PPC_LL r0, VCPU_GPR(r0)(r4)
> + PPC_LL r1, VCPU_GPR(r1)(r4)
> + PPC_LL r2, VCPU_GPR(r2)(r4)
> + PPC_LL r10, VCPU_GPR(r10)(r4)
> + PPC_LL r11, VCPU_GPR(r11)(r4)
> + PPC_LL r12, VCPU_GPR(r12)(r4)
> + PPC_LL r13, VCPU_GPR(r13)(r4)
> + mtlr r3
> + mtxer r5
> + mtctr r6
> + mtcr r7
> + mtsrr0 r8
> + mtsrr1 r9
Are you sure this should be shared->msr, not shadow_msr?
> +
> +#ifdef CONFIG_KVM_EXIT_TIMING
> + /* save enter time */
> +1:
> + mfspr r6, SPRN_TBRU
> + mfspr r7, SPRN_TBRL
> + mfspr r8, SPRN_TBRU
> + cmpw r8, r6
> + PPC_STL r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
> + bne 1b
> + PPC_STL r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
> +#endif
> +
> + /* Finish loading guest volatiles and jump to guest. */
> + PPC_LL r5, VCPU_GPR(r5)(r4)
> + PPC_LL r6, VCPU_GPR(r6)(r4)
> + PPC_LL r7, VCPU_GPR(r7)(r4)
> + PPC_LL r8, VCPU_GPR(r8)(r4)
> + PPC_LL r9, VCPU_GPR(r9)(r4)
> +
> + PPC_LL r3, VCPU_GPR(r3)(r4)
> + PPC_LL r4, VCPU_GPR(r4)(r4)
> + rfi
> diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
> index 42701e5..f9c62dd 100644
> --- a/arch/powerpc/kvm/powerpc.c
> +++ b/arch/powerpc/kvm/powerpc.c
> @@ -109,6 +109,11 @@ int kvmppc_sanity_check(struct kvm_vcpu *vcpu)
> goto out;
> #endif
>=20
> +#ifdef CONFIG_KVM_BOOKE_HV
> + if (!cpu_has_feature(CPU_FTR_EMB_HV))
> + goto out;
> +#endif
> +
> r =3D true;
>=20
> out:
> diff --git a/arch/powerpc/kvm/timing.h b/arch/powerpc/kvm/timing.h
> index 8167d42..bf191e7 100644
> --- a/arch/powerpc/kvm/timing.h
> +++ b/arch/powerpc/kvm/timing.h
> @@ -93,6 +93,12 @@ static inline void kvmppc_account_exit_stat(struct =
kvm_vcpu *vcpu, int type)
> case SIGNAL_EXITS:
> vcpu->stat.signal_exits++;
> break;
> + case DBELL_EXITS:
> + vcpu->stat.dbell_exits++;
> + break;
> + case GDBELL_EXITS:
> + vcpu->stat.gdbell_exits++;
> + break;
> }
> }
>=20
> --=20
> 1.7.7.rc3.4.g8d714
>=20
>=20
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox