* RE: [PATCH 0/6] Description for PCI patches using platform driver
From: Bhushan Bharat-R65777 @ 2012-06-14 9:52 UTC (permalink / raw)
To: Jia Hongtao-B38951, linuxppc-dev@lists.ozlabs.org,
galak@kernel.crashing.org, benh@kernel.crashing.org
Cc: Wood Scott-B07421, Li Yang-R58472
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5D01A0973E@039-SN1MPN1-002.039d.mgd.msft.net>
Hello Ben, Kumar, others
Please provide your comments/thoughts on this ?
Thanks
-Bharat
> > > >
> > > > > -----Original Message-----
> > > > > From: Jia Hongtao-B38951
> > > > > Sent: Friday, June 08, 2012 3:12 PM
> > > > > To: linuxppc-dev@lists.ozlabs.org; galak@kernel.crashing.org
> > > > > Cc: Li Yang-R58472; benh@kernel.crashing.org; Wood Scott-B07421;
> > > > Bhushan Bharat-
> > > > > R65777; Jia Hongtao-B38951
> > > > > Subject: [PATCH 0/6] Description for PCI patches using platform
> > > > > driver
> > > > >
> > > > > This series of patches are to unify pci initialization code and
> > > > > add PM
> > > > support
> > > > > for all 85xx/86xx powerpc boards. But two side effects are
> > > > > introduced
> > > > by this
> > > > > mechanism which listed below:
> > > > >
> > > > > 1. of_platform_bus_probe() will be called twice but in some
> > > > > cases
> > > > duplication
> > > > > warning occured. We fix this in [PATCH 5/6].
> > > > >
> > > > > 2. Edac driver failed to register pci nodes as platform devices.
> > > > > We fix
> > > > this
> > > > > in [PATCH 6/6].
> > > >
> > > > With these patches will not the SWIOTLB will not be initialized
> > > > even if PCI/PCIe demanded?
> > > >
> > > > Thanks
> > > > -Bharat
> > > >
> > >
> > > These patches still have the swiotlb init problem if
> > "ppc_swiotlb_enable" is
> > > only demanded by PCI/PCIe. One of the purposes of sending out these
> > patches is
> > > to let us start a discussion for this problem in upstream.
> >
> > Ok, I did not find any mention of that, so I thought that you have
> > resolved the issue by some means in these patches which I did not catch=
.
> >
> > So, these patches introduces the issue, that SWIOTLB will not be
> > initialized if requested by pci/pcie. The request is raised by setting
> > the flag ppc_swiotlb_enable. The swiotlb_init() will be called in
> > mem_init() if ppc_swiotlb_enable is set. Now with these patches, the
> > request is raised after mem_init() is called. So request not handled :)=
.
> >
> > Following are the solutions we have thought of during our internal
> > discussions (if I did not missed any):
> >
> > 1. These patches move the code from platform init to device init
> > (arch_initcall()). Rather than moving the whole code, let us divide
> > the code into two. First, which is needed to raise the swiotlb init
> > request and second the rest. Define this first as an function in
> > arch/powerpc/sysdev/fsl_pci.c and call this from platform init code of
> > the SOCs.
> >
> > 2. All known devices, the lowest PCIe outbound range starts at
> > 0x80000000, but there's nothing above 0xc0000000. So the inbound of
> > size 0x8000_0000 is always availbe on all devices. Hardcode the check
> > in platform code to check memblock_end_of_DRAM() to 0x80000000.
> >
> > Something like this:
> >
> > diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c
> > b/arch/powerpc/platforms/85xx/corenet_ds.c
> > index 1f7028e..ef4e215 100644
> > --- a/arch/powerpc/platforms/85xx/corenet_ds.c
> > +++ b/arch/powerpc/platforms/85xx/corenet_ds.c
> > @@ -79,7 +79,7 @@ void __init corenet_ds_setup_arch(void) #endif
> >
> > #ifdef CONFIG_SWIOTLB
> > - if (memblock_end_of_DRAM() > 0xffffffff)
> > + if (memblock_end_of_DRAM() > 0xff000000)
> > ppc_swiotlb_enable =3D 1; #endif
> > pr_info("%s board from Freescale Semiconductor\n",
> > ppc_md.name);
> >
> > -------------
> >
> > 3. Always do swiotlb_init() in mem_init() and later after PCI init, if
> > the swiotlb is not needed then free it (swiotlb_free()).
> >
> > 4. etc, please provide some other better way.
> >
> > Thanks
> > -Bharat
>=20
> Thanks.
> In my point of view the 2nd solution is better for it does not treat PCI/=
PCIe as
> the special kind of devices from others.
>=20
> -Jia Hongtao.
^ permalink raw reply
* [PATCH] Make hard_irq_disable() actually hard-disable interrupts
From: Paul Mackerras @ 2012-06-14 10:31 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linuxppc-dev
At present, hard_irq_disable() does nothing because of this code in
include/linux/interrupt.h:
#ifndef hard_irq_disable
#define hard_irq_disable() do { } while(0)
#endif
So we need to make our hard_irq_disable() be a macro.
Signed-off-by: Paul Mackerras <paulus@samba.org>
---
arch/powerpc/include/asm/hw_irq.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index c9aac24..d8f873f 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -93,12 +93,13 @@ static inline bool arch_irqs_disabled(void)
#define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1)
#endif
-static inline void hard_irq_disable(void)
+static inline void _hard_irq_disable(void)
{
__hard_irq_disable();
get_paca()->soft_enabled = 0;
get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
}
+#define hard_irq_disable() _hard_irq_disable()
/*
* This is called by asynchronous interrupts to conditionally
^ permalink raw reply related
* Re: [PATCH] i2c: let the core register devices from devicetree
From: Pawel Moll @ 2012-06-14 10:28 UTC (permalink / raw)
To: Wolfram Sang
Cc: Viresh Kumar, Mauro Carvalho Chehab, Tony Lindgren, Linus Walleij,
Laxman Dewangan, linux-i2c, Kukjin Kim, Stephen Warren,
Barry Song, Haojian Zhuang, Deepak Sikri, Haavard Skinnemoen,
Dirk Brandewie, Wolfram Sang, Sascha Hauer, Rusty Russell,
Tang Yuantian, Jean Delvare (PC drivers, core), Magnus Damm,
Lars-Peter Clausen, Ben Dooks (embedded platforms),
linux-arm-kernel, Jiri Kosina, Kyungmin Park, Karol Lewandowski,
Olof Johansson, Shawn Guo, linuxppc-dev
In-Reply-To: <1339622215-4733-1-git-send-email-w.sang@pengutronix.de>
On Wed, 2012-06-13 at 23:12 +0200, Wolfram Sang wrote:
> Currently, every driver has to do it on its own, but it should be done
> in the core, like we already do with board_info structs.
>=20
> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
> ---
> drivers/i2c/busses/i2c-versatile.c | 1 -
> drivers/i2c/i2c-core.c | 3 +++
For what it's worth
Tested-by: Pawel Moll <pawel.moll@arm.com>
on Versatile Express.
Regards
Pawe=C5=82
^ permalink raw reply
* Re: [PATCH] i2c: let the core register devices from devicetree
From: Jean Delvare @ 2012-06-14 10:42 UTC (permalink / raw)
To: Wolfram Sang
Cc: Viresh Kumar, Mauro Carvalho Chehab, Tony Lindgren, Linus Walleij,
Haojian Zhuang, Laxman Dewangan, linux-i2c, Kukjin Kim,
Stephen Warren, Barry Song, Deepak Sikri, Haavard Skinnemoen,
Pawel Moll, Wolfram Sang, Sascha Hauer, Rusty Russell,
Tang Yuantian, Olof Johansson, Magnus Damm, Lars-Peter Clausen,
Ben Dooks (embedded platforms), linux-arm-kernel, Jiri Kosina,
Kyungmin Park, Karol Lewandowski, Dirk Brandewie, Shawn Guo,
linuxppc-dev
In-Reply-To: <1339622215-4733-1-git-send-email-w.sang@pengutronix.de>
Hi Wolfram,
On Wed, 13 Jun 2012 23:12:10 +0200, Wolfram Sang wrote:
> Currently, every driver has to do it on its own, but it should be done
> in the core, like we already do with board_info structs.
>
> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
> ---
>
> Based on v3.5-rc2. Only build tested, I don't have a OF based device
> around at the moment.
> (...)
> diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
> index a6ad32b..4791833 100644
> --- a/drivers/i2c/i2c-core.c
> +++ b/drivers/i2c/i2c-core.c
> @@ -39,6 +39,7 @@
> #include <linux/irqflags.h>
> #include <linux/rwsem.h>
> #include <linux/pm_runtime.h>
> +#include <linux/of_i2c.h>
> #include <asm/uaccess.h>
>
> #include "i2c-core.h"
> @@ -880,6 +881,8 @@ static int i2c_register_adapter(struct i2c_adapter *adap)
> #endif
>
> /* create pre-declared device nodes */
> + of_i2c_register_devices(adap);
> +
> if (adap->nr < __i2c_first_dynamic_bus_num)
> i2c_scan_static_board_info(adap);
>
This was proposed in the past, and rejected because of dependency
issues. I don't think the situation changed. of_i2c needs i2c-core for
i2c_new_device(), and with the change above, i2c-core needs of_i2c for
of_i2c_register_devices(). If either is built as a module, it will fail.
This might be the reason why of_spi ended up being merged into
drivers/spi according to Grant? I have no objection to the same being
done for of_i2c if it makes everybody happy, as long as it does not
create additional dependencies (i.e. I2C should not depend on OF.)
--
Jean Delvare
^ permalink raw reply
* Re: [PATCH] Make hard_irq_disable() actually hard-disable interrupts
From: Benjamin Herrenschmidt @ 2012-06-14 11:34 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120614103112.GA15685@bloggs.ozlabs.ibm.com>
On Thu, 2012-06-14 at 20:31 +1000, Paul Mackerras wrote:
> At present, hard_irq_disable() does nothing because of this code in
> include/linux/interrupt.h:
>
> #ifndef hard_irq_disable
> #define hard_irq_disable() do { } while(0)
> #endif
>
> So we need to make our hard_irq_disable() be a macro.
>
> Signed-off-by: Paul Mackerras <paulus@samba.org>
This was broken by my rewrite of the lazy irq stuff when I turned that
from a macro to a function. So it should be CC'ed to stable 3.4.
Also I think it's simpler (and we do that commonly) to just do
#define hard_irq_disable hard_irq_disable
Cheers,
Ben.
> ---
> arch/powerpc/include/asm/hw_irq.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
> diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
> index c9aac24..d8f873f 100644
> --- a/arch/powerpc/include/asm/hw_irq.h
> +++ b/arch/powerpc/include/asm/hw_irq.h
> @@ -93,12 +93,13 @@ static inline bool arch_irqs_disabled(void)
> #define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1)
> #endif
>
> -static inline void hard_irq_disable(void)
> +static inline void _hard_irq_disable(void)
> {
> __hard_irq_disable();
> get_paca()->soft_enabled = 0;
> get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
> }
> +#define hard_irq_disable() _hard_irq_disable()
>
> /*
> * This is called by asynchronous interrupts to conditionally
^ permalink raw reply
* Re: [PATCH] i2c: let the core register devices from devicetree
From: Benjamin Herrenschmidt @ 2012-06-14 11:35 UTC (permalink / raw)
To: Wolfram Sang
Cc: Viresh Kumar, Mauro Carvalho Chehab, Tony Lindgren, Linus Walleij,
Laxman Dewangan, linux-i2c, Kukjin Kim, Stephen Warren,
Barry Song, Haojian Zhuang, Deepak Sikri, Haavard Skinnemoen,
Dirk Brandewie, Pawel Moll, Wolfram Sang, Sascha Hauer,
Rusty Russell, Tang Yuantian, Jean Delvare (PC drivers, core),
Magnus Damm, Lars-Peter Clausen, Ben Dooks (embedded platforms),
linux-arm-kernel, Jiri Kosina, Kyungmin Park, Karol Lewandowski,
Olof Johansson, Shawn Guo, linuxppc-dev
In-Reply-To: <20120614091434.GB14419@pengutronix.de>
On Thu, 2012-06-14 at 11:14 +0200, Wolfram Sang wrote:
> On Thu, Jun 14, 2012 at 07:33:37AM +1000, Benjamin Herrenschmidt wrote:
> > On Wed, 2012-06-13 at 23:12 +0200, Wolfram Sang wrote:
> > > Currently, every driver has to do it on its own, but it should be done
> > > in the core, like we already do with board_info structs.
> > >
> > > Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
> > > ---
> > >
> > > Based on v3.5-rc2. Only build tested, I don't have a OF based device
> > > around at the moment.
> >
> > Won't that conflict with i2c-powermac doing it its own way ?
>
> Yup :(
>
> I assume there is no chance that the powermac devicetree can be
> pre-processed to be compatible with of_i2c_register_devices?
That would be nasty and need a lot of testing on all sort of machines I
don't have direct access to.
Maybe we can set a flag somewhere to indicate to the core not to run the
default probing on that controller ?
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v2 1/2] uprobes: Pass probed vaddr to arch_uprobe_analyze_insn()
From: Srikar Dronamraju @ 2012-06-14 11:45 UTC (permalink / raw)
To: Oleg Nesterov
Cc: peterz, antonb, lkml, Jim Keniston, Paul Mackerras, Ingo Molnar,
linuxppc-dev
In-Reply-To: <20120613191519.GA14246@redhat.com>
* Oleg Nesterov <oleg@redhat.com> [2012-06-13 21:15:19]:
> On 06/12, Oleg Nesterov wrote:
> >
> > On 06/12, Srikar Dronamraju wrote:
> > > >
> > > > Note also that we should move this !UPROBE_COPY_INSN from
> > > > install_breakpoint() to somewhere near alloc_uprobe(). This code
> > > > is called only once, it looks a bit strange to use the "random" mm
> > > > (the first mm vma_prio_tree_foreach() finds) and its mapping to
> > > > verify the insn. In fact this is simply not correct and should be
> > > > fixed, note that on x86 arch_uprobe_analyze_insn() checks
> > >
> > > The reason we "delay" the copy_insn to the first insert is because
> > > we have to get access to mm. For archs like x86, we want to know if the
> > > executable is 32 bit or not
> >
> > Yes. And this is wrong afaics.
> >
> > Once again. This !UPROBE_COPY_INSN code is called only once, and it
> > uses the "random" mm. After that install_breakpoint() just calls
> > set_swbp(another_mm) while the insn can be invalid because
> > another_mm->ia32_compat != mm->ia32_compat.
> >
> > > So in effect, if we get access to
> > > struct file corresponding to the inode and if the inode corresponds to
> > > 32 bit executable file or 64 bit executable file during register, then
> > > we can move it around alloc_uprobe().
> >
> > I don't think this can work. I have another simple fix in mind, I'll
> > write another email later.
>
> For example. Suppose there is some instruction in /lib64/libc.so which
> is valid for 64-bit, but not for 32-bit.
>
> Suppose that a 32-bit application does mmap("/lib64/libc.so", PROT_EXEC).
>
How correct is it to have a 32 bit binary link to a 64 bit binary/library?
what if the 64 bit binary/executable were to make a jump to a 64 bit
address?
> Now. If vma_prio_tree_foreach() finds this 32-bit mm first, uprobe_register()
> fails even if there are other 64-bit applications which could be traced.
>
> Or. uprobe_register() succeeds because it finds a 64-bit mm first, and
> then that 32-bit application actually executes the invalid insn.
>
> We can move arch_uprobe_analyze_insn() outside of !UPROBE_COPY_INSN block.
>
> Or, perhaps, validate_insn_bits() should call both
> validate_insn_32bits() and validate_insn_64bits(), and set the
> UPROBE_VALID_IF_32 / UPROBE_VALID_IF_64 flags. install_breakpoint()
> should do the additinal check before set_swbp() and verify that
> .ia32_compat matches UPROBE_VALID_IF_*.
>
> What do you think?
>
Lets say we do find a 32 bit app and 64 bit app using the same library
and the underlying instruction is valid for tracing in 64 bit and not 32
bit. So when we are registering, and failed to insert a breakpoint for
the 32 bit app, should we just bail out or should we return a failure?
I would probably prefer to read the underlying file something similar to
what exec does and based on the magic decipher if we should verify for
32 bit instructions or 64 bit instructions.
I didnt find a good way to read the first few bytes just by looking at
the inode. So one option is to read the underlying file at the first
insertion (i.e similar to what we do now .. but instead of depending on
ia32_compat of a random mm, depend on the exec magic)
Better option would be read the underlying file at the register time and
return an error even without attempting an insert if the instruction
wasnt valid. But I am still ignorant on how to do this because we need a
struct file to do this.
--
Thanks and Regards
Srikar
^ permalink raw reply
* Re: [PATCH] i2c: let the core register devices from devicetree
From: Linus Walleij @ 2012-06-14 17:29 UTC (permalink / raw)
To: Wolfram Sang, Lee Jones
Cc: Viresh Kumar, Mauro Carvalho Chehab, Tony Lindgren,
Haojian Zhuang, Laxman Dewangan, linux-i2c, Kukjin Kim,
Stephen Warren, Olof Johansson, Barry Song, Deepak Sikri,
Haavard Skinnemoen, Pawel Moll, Wolfram Sang, Sascha Hauer,
Rusty Russell, Tang Yuantian, Jean Delvare (PC drivers, core),
Magnus Damm, Lars-Peter Clausen, Ben Dooks (embedded platforms),
linux-arm-kernel, Jiri Kosina, Kyungmin Park, Karol Lewandowski,
Dirk Brandewie, Shawn Guo, linuxppc-dev
In-Reply-To: <1339622215-4733-1-git-send-email-w.sang@pengutronix.de>
On Wed, Jun 13, 2012 at 11:12 PM, Wolfram Sang <w.sang@pengutronix.de> wrote:
> Currently, every driver has to do it on its own, but it should be done
> in the core, like we already do with board_info structs.
>
> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Lee might be able to test this with his DT bindings (and patch them to use
the new handling in the core..)
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] powerpc/44x: Support OCM(On Chip Memory) for APM821xx SoC and Bluestone board
From: Josh Boyer @ 2012-06-14 17:47 UTC (permalink / raw)
To: Vinh Nguyen Huu Tuong
Cc: Anatolij Gustschin, devicetree-discuss, Duc Dang, Rob Herring,
linux-kernel, Liu Gang, Paul Mackerras, Ashish Kalra,
linuxppc-dev, David S. Miller
In-Reply-To: <1336362768-31326-1-git-send-email-vhtnguyen@apm.com>
On Sun, May 6, 2012 at 11:52 PM, Vinh Nguyen Huu Tuong
<vhtnguyen@apm.com> wrote:
> This patch consists of:
> - Add driver for OCM component
> - Export OCM Information at /sys/class/ocm/ocminfo
Again, apologies for the delay. Aside from the incorrect sysfs usage
I pointed out in my other reply, I have just a few comments/questions
below.
> diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/=
bluestone.dts
> index 7bda373..2687c11 100644
> --- a/arch/powerpc/boot/dts/bluestone.dts
> +++ b/arch/powerpc/boot/dts/bluestone.dts
> @@ -107,6 +107,14 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D <&UIC0>;
> =A0 =A0 =A0 =A0};
>
> + =A0 =A0 =A0 OCM1: ocm@400040000 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "ibm,ocm";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 status =3D "ok";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cell-index =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* configured in U-Boot */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <4 0x00040000 0x8000>; /* 32K */
> + =A0 =A0 =A0 };
> +
> =A0 =A0 =A0 =A0SDR0: sdr {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "ibm,sdr-apm821xx";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dcr-reg =3D <0x00e 0x002>;
> diff --git a/arch/powerpc/include/asm/ppc4xx_ocm.h b/arch/powerpc/include=
/asm/ppc4xx_ocm.h
> new file mode 100644
> index 0000000..ff7f386
> --- /dev/null
> +++ b/arch/powerpc/include/asm/ppc4xx_ocm.h
> @@ -0,0 +1,47 @@
> +/*
> + * PowerPC 4xx OCM memory allocation support
> + *
> + * (C) Copyright 2009, Applied Micro Circuits Corporation
> + * Victor Gallardo (vgallardo@amcc.com)
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __ASM_POWERPC_PPC4xx_OCM_H__
> +#define __ASM_POWERPC_PPC4xx_OCM_H__
> +
> +#include <linux/types.h>
> +
> +#define OCM_NON_CACHED 0
> +#define OCM_CACHED =A0 =A0 1
> +
> +#if defined(CONFIG_PPC4xx_OCM)
> +
> +void *ocm_alloc(phys_addr_t *phys, int size, int align,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 int flags, const char *owner);
> +void ocm_free(const void *virt);
> +
> +#else
> +
> +#define ocm_alloc(phys, size, align, flags, owner) =A0 =A0 NULL
> +#define ocm_free(addr) ((void)0)
> +
> +#endif /* CONFIG_PPC4xx_OCM */
> +
> +#endif =A0/* __ASM_POWERPC_PPC4xx_OCM_H__ */
I don't see any users of this header included in the patch. I'm going
to guess that follow-on drivers/users are queued once this is in the
tree? Also, you might want to name these 'ppc4xx_ocm_alloc' or
similar. The concept of OCM isn't limited to ppc4xx or even SoCs, so
just using 'ocm' in the global kernel namespace might not be great.
> diff --git a/arch/powerpc/sysdev/ppc4xx_ocm.c b/arch/powerpc/sysdev/ppc4x=
x_ocm.c
> new file mode 100644
> index 0000000..ba3e450
> --- /dev/null
> +++ b/arch/powerpc/sysdev/ppc4xx_ocm.c
> @@ -0,0 +1,420 @@
> +#include <linux/kernel.h>
> +#include <linux/errno.h>
> +#include <linux/proc_fs.h>
Why do you need proc_fs.h?
> +#include <linux/seq_file.h>
> +#include <linux/spinlock.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/list.h>
> +#include <asm/uaccess.h>
> +#include <asm/prom.h>
> +#include <asm/dcr.h>
> +#include <asm/rheap.h>
> +#include <asm/mmu.h>
> +#include <asm/ppc4xx_ocm.h>
> +#include <linux/export.h>
> +
> +#define OCM_DISABLED =A0 0
> +#define OCM_ENABLED =A0 =A0 =A0 =A0 =A0 =A01
> +
> +struct ocm_block {
> + =A0 =A0 =A0 struct list_head =A0 =A0 =A0 =A0list;
> + =A0 =A0 =A0 void __iomem =A0 =A0 =A0 =A0 =A0 =A0*addr;
> + =A0 =A0 =A0 int =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 size;
> + =A0 =A0 =A0 const char =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0*owne=
r;
> +};
> +
> +/* non-cached or cached region */
> +struct ocm_region {
> + =A0 =A0 =A0 phys_addr_t =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phys;
> + =A0 =A0 =A0 void __iomem =A0 =A0 =A0 =A0 =A0 =A0*virt;
> +
> + =A0 =A0 =A0 int =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 memtotal;
> + =A0 =A0 =A0 int =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
=A0 =A0 =A0 =A0 memfree;
> +
> + =A0 =A0 =A0 rh_info_t =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 *rh;
> + =A0 =A0 =A0 struct list_head =A0 =A0 =A0 =A0list;
> +};
There's some interesting whitespace usage in these struct definitions.
josh
^ permalink raw reply
* Re: [PATCH v2 1/2] uprobes: Pass probed vaddr to arch_uprobe_analyze_insn()
From: Oleg Nesterov @ 2012-06-14 18:19 UTC (permalink / raw)
To: Srikar Dronamraju
Cc: peterz, antonb, lkml, Jim Keniston, Paul Mackerras, Ingo Molnar,
linuxppc-dev
In-Reply-To: <20120614114514.GA12051@linux.vnet.ibm.com>
On 06/14, Srikar Dronamraju wrote:
>
> * Oleg Nesterov <oleg@redhat.com> [2012-06-13 21:15:19]:
>
> > For example. Suppose there is some instruction in /lib64/libc.so which
> > is valid for 64-bit, but not for 32-bit.
> >
> > Suppose that a 32-bit application does mmap("/lib64/libc.so", PROT_EXEC).
> >
>
> How correct is it to have a 32 bit binary link to a 64 bit binary/library?
No, I didn't mean this. I guess you misunderstood my point, see below.
> > Now. If vma_prio_tree_foreach() finds this 32-bit mm first, uprobe_register()
> > fails even if there are other 64-bit applications which could be traced.
> >
> > Or. uprobe_register() succeeds because it finds a 64-bit mm first, and
> > then that 32-bit application actually executes the invalid insn.
> >
> > We can move arch_uprobe_analyze_insn() outside of !UPROBE_COPY_INSN block.
> >
> > Or, perhaps, validate_insn_bits() should call both
> > validate_insn_32bits() and validate_insn_64bits(), and set the
> > UPROBE_VALID_IF_32 / UPROBE_VALID_IF_64 flags. install_breakpoint()
> > should do the additinal check before set_swbp() and verify that
> > .ia32_compat matches UPROBE_VALID_IF_*.
> >
>
> > What do you think?
> >
>
> Lets say we do find a 32 bit app and 64 bit app using the same library
> and the underlying instruction is valid for tracing in 64 bit and not 32
> bit. So when we are registering, and failed to insert a breakpoint for
> the 32 bit app, should we just bail out or should we return a failure?
I do not really know, I tend to think we should not fail. But this is
another story...
Look. Suppose that a 32-bit app starts after uprobe_register() succeeds.
In this case we have no option, uprobe_mmap()->install_breakpoint()
should "silently" fail. Currently it doesn't, this is one of the reasons
why I think the validation logic is wrong.
And. if install_breakpoint() can fail later anyway (in this case), then
I think uprobe_register() should not fail.
But probably this needs more discussion.
> I would probably prefer to read the underlying file something similar to
> what exec does and based on the magic decipher if we should verify for
> 32 bit instructions or 64 bit instructions.
But this can't protect from the malicious user who does
mmap(64-bit-code, PROT_EXEC) from a 32-bit app, and this can confuse
uprobes even if that 32-bit app never tries to actually execute that
64-bit-code.
That is why I think we need the additional (and arch-dependant) check
before every set_swbp(), but arch_uprobe_analyze_insn/etc should not
depend on task/mm/vaddr/whatever.
Oleg.
^ permalink raw reply
* [PATCH 1/2] powerpc/mm: remove obsolete comment about page size name array
From: Scott Wood @ 2012-06-14 23:40 UTC (permalink / raw)
To: benh, galak; +Cc: linuxppc-dev
The array of names in hugetlbpage.c no longer exists.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/include/asm/mmu.h | 7 +------
1 files changed, 1 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index f014552..a9e9ec6 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -163,12 +163,7 @@ extern u64 ppc64_rma_size;
* to think about, feedback welcome. --BenH.
*/
-/* There are #define as they have to be used in assembly
- *
- * WARNING: If you change this list, make sure to update the array of
- * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
- * happen
- */
+/* There are #define as they have to be used in assembly */
#define MMU_PAGE_4K 0
#define MMU_PAGE_16K 1
#define MMU_PAGE_64K 2
--
1.7.5.4
^ permalink raw reply related
* [PATCH 2/2] powerpc/e6500: TLB miss handler with hardware tablewalk support
From: Scott Wood @ 2012-06-14 23:41 UTC (permalink / raw)
To: benh, galak; +Cc: linuxppc-dev
There are a few things that make the existing hw tablewalk handlers
unsuitable for e6500:
- Indirect entries go in TLB1 (though the resulting direct entries go in
TLB0).
- It has threads, but no "tlbsrx." -- so we need a spinlock and
a normal "tlbsx". Because we need this lock, hardware tablewalk
is mandatory on e6500 unless we want to add spinlock+tlbsx to
the normal bolted TLB miss handler.
- TLB1 has no HES (nor next-victim hint) so we need software round robin
(TODO: integrate this round robin data with hugetlb/KVM)
- The existing tablewalk handlers map half of a page table at a time,
because IBM hardware has a fixed 1MiB indirect page size. e6500
has variable size indirect entries, with a minimum of 2MiB.
So we can't do the half-page indirect mapping, and even if we
could it would be less efficient than mapping the full page.
- Like on e5500, the linear mapping is bolted, so we don't need the
overhead of supporting nested tlb misses.
Note that hardware tablewalk does not work in rev1 of e6500.
We do not expect to support e6500 rev1 in mainline Linux.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/include/asm/mmu-book3e.h | 13 +++
arch/powerpc/include/asm/mmu.h | 21 ++--
arch/powerpc/include/asm/paca.h | 6 +
arch/powerpc/kernel/asm-offsets.c | 10 ++
arch/powerpc/kernel/paca.c | 5 +
arch/powerpc/kernel/setup_64.c | 33 +++++++
arch/powerpc/mm/fsl_booke_mmu.c | 8 ++
arch/powerpc/mm/tlb_low_64e.S | 167 +++++++++++++++++++++++++++++++++
arch/powerpc/mm/tlb_nohash.c | 109 ++++++++++++++++------
9 files changed, 335 insertions(+), 37 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index eeabcdb..3072aa0 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -264,8 +264,21 @@ extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
extern int mmu_linear_psize;
extern int mmu_vmemmap_psize;
+struct book3e_tlb_per_core {
+ /* For software way selection, as on Freescale TLB1 */
+ u8 esel_next, esel_max, esel_first;
+
+ /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
+ u8 lock;
+};
+
#ifdef CONFIG_PPC64
extern unsigned long linear_map_top;
+extern int book3e_htw_mode;
+
+#define PPC_HTW_NONE 0
+#define PPC_HTW_IBM 1
+#define PPC_HTW_E6500 2
/*
* 64-bit booke platforms don't load the tlb in the tlb miss handler code.
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index a9e9ec6..63d97eb 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -170,16 +170,17 @@ extern u64 ppc64_rma_size;
#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
#define MMU_PAGE_256K 4
#define MMU_PAGE_1M 5
-#define MMU_PAGE_4M 6
-#define MMU_PAGE_8M 7
-#define MMU_PAGE_16M 8
-#define MMU_PAGE_64M 9
-#define MMU_PAGE_256M 10
-#define MMU_PAGE_1G 11
-#define MMU_PAGE_16G 12
-#define MMU_PAGE_64G 13
-
-#define MMU_PAGE_COUNT 14
+#define MMU_PAGE_2M 6
+#define MMU_PAGE_4M 7
+#define MMU_PAGE_8M 8
+#define MMU_PAGE_16M 9
+#define MMU_PAGE_64M 10
+#define MMU_PAGE_256M 11
+#define MMU_PAGE_1G 12
+#define MMU_PAGE_16G 13
+#define MMU_PAGE_64G 14
+
+#define MMU_PAGE_COUNT 15
#if defined(CONFIG_PPC_STD_MMU_64)
/* 64-bit classic hash table MMU */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index daf813f..4e18bb5 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -108,6 +108,12 @@ struct paca_struct {
/* Keep pgd in the same cacheline as the start of extlb */
pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
pgd_t *kernel_pgd; /* Kernel PGD */
+
+ struct book3e_tlb_per_core tlb_per_core;
+
+ /* Points to the tlb_per_core of the first thread on this core. */
+ struct book3e_tlb_per_core *tlb_per_core_ptr;
+
/* We can have up to 3 levels of reentrancy in the TLB miss handler */
u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
u64 exmc[8]; /* used for machine checks */
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 52c7ad7..61f4634 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -168,6 +168,16 @@ int main(void)
DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
+ DEFINE(PACA_TLB_PER_CORE_PTR,
+ offsetof(struct paca_struct, tlb_per_core_ptr));
+
+ DEFINE(PERCORE_TLB_ESEL_NEXT,
+ offsetof(struct book3e_tlb_per_core, esel_next));
+ DEFINE(PERCORE_TLB_ESEL_MAX,
+ offsetof(struct book3e_tlb_per_core, esel_max));
+ DEFINE(PERCORE_TLB_ESEL_FIRST,
+ offsetof(struct book3e_tlb_per_core, esel_first));
+ DEFINE(PERCORE_TLB_LOCK, offsetof(struct book3e_tlb_per_core, lock));
#endif /* CONFIG_PPC_BOOK3E */
#ifdef CONFIG_PPC_STD_MMU_64
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index fbe1a12..65abfc0 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -145,6 +145,11 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
#ifdef CONFIG_PPC_STD_MMU_64
new_paca->slb_shadow_ptr = &slb_shadow[cpu];
#endif /* CONFIG_PPC_STD_MMU_64 */
+
+#ifdef CONFIG_PPC_BOOK3E
+ /* For now -- if we have threads this will be adjusted later */
+ new_paca->tlb_per_core_ptr = &new_paca->tlb_per_core;
+#endif
}
/* Put the paca pointer into r13 and SPRG_PACA */
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 389bd4f..271b85d 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -102,6 +102,37 @@ int ucache_bsize;
static char *smt_enabled_cmdline;
+#ifdef CONFIG_PPC_BOOK3E
+static void setup_tlb_per_core(void)
+{
+ int cpu;
+
+ for_each_possible_cpu(cpu) {
+ int first = cpu_first_thread_sibling(cpu);
+
+ paca[cpu].tlb_per_core_ptr = &paca[first].tlb_per_core;
+
+ /*
+ * If we have threads, we need either tlbsrx.
+ * or e6500 tablewalk mode, or else TLB handlers
+ * will be racy and could produce duplicate entries.
+ */
+ if (smt_enabled_at_boot >= 2 &&
+ !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
+ book3e_htw_mode != PPC_HTW_E6500) {
+ /* Should we panic instead? */
+ WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
+ __func__);
+ }
+ }
+}
+#else
+static void setup_tlb_per_core(void)
+{
+}
+#endif
+
+
/* Look for ibm,smt-enabled OF option */
static void check_smt_enabled(void)
{
@@ -142,6 +173,8 @@ static void check_smt_enabled(void)
of_node_put(dn);
}
}
+
+ setup_tlb_per_core();
}
/* Look for smt-enabled= cmdline option */
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 07ba45b..bf06d36b 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -52,6 +52,7 @@
#include <asm/smp.h>
#include <asm/machdep.h>
#include <asm/setup.h>
+#include <asm/paca.h>
#include "mmu_decl.h"
@@ -192,6 +193,13 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
}
tlbcam_index = i;
+#ifdef CONFIG_PPC64
+ get_paca()->tlb_per_core.esel_next = i;
+ get_paca()->tlb_per_core.esel_max =
+ mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
+ get_paca()->tlb_per_core.esel_first = i;
+#endif
+
return amount_mapped;
}
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index efe0f33..8e82772 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -232,6 +232,173 @@ itlb_miss_fault_bolted:
beq tlb_miss_common_bolted
b itlb_miss_kernel_bolted
+/*
+ * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
+ *
+ * Linear mapping is bolted: no virtual page table or nested TLB misses
+ * Indirect entries in TLB1, hardware loads resulting direct entries
+ * into TLB0
+ * No HES or NV hint on TLB1, so we need to do software round-robin
+ * No tlbsrx. so we need a spinlock, and we have to deal
+ * with MAS-damage caused by tlbsx
+ * 4K pages only
+ */
+
+ START_EXCEPTION(instruction_tlb_miss_e6500)
+ tlb_prolog_bolted SPRN_SRR0
+
+ ld r11,PACA_TLB_PER_CORE_PTR(r13)
+ srdi. r15,r16,60 /* get region */
+ ori r16,r16,1
+
+ TLB_MISS_STATS_SAVE_INFO_BOLTED
+ bne tlb_miss_kernel_e6500 /* user/kernel test */
+
+ b tlb_miss_common_e6500
+
+ START_EXCEPTION(data_tlb_miss_e6500)
+ tlb_prolog_bolted SPRN_DEAR
+
+ ld r11,PACA_TLB_PER_CORE_PTR(r13)
+ srdi. r15,r16,60 /* get region */
+ rldicr r16,r16,0,62
+
+ TLB_MISS_STATS_SAVE_INFO_BOLTED
+ bne tlb_miss_kernel_e6500 /* user vs kernel check */
+
+/*
+ * This is the guts of the TLB miss handler for e6500 and derivatives.
+ * We are entered with:
+ *
+ * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
+ * r15 = crap (free to use)
+ * r14 = page table base
+ * r13 = PACA
+ * r11 = tlb_per_core ptr
+ * r10 = crap (free to use)
+ */
+tlb_miss_common_e6500:
+ /*
+ * Search if we already have an indirect entry for that virtual
+ * address, and if we do, bail out.
+ *
+ * MAS6:IND should be already set based on MAS4
+ */
+ addi r10,r11,PERCORE_TLB_LOCK
+1: lbarx r15,0,r10
+ cmpdi r15,0
+ bne 2f
+ li r15,1
+ stbcx. r15,0,r10
+ bne 1b
+ .subsection 1
+2: lbz r15,0(r10)
+ cmpdi r15,0
+ bne 2b
+ b 1b
+ .previous
+
+ mfspr r15,SPRN_MAS2
+
+ tlbsx 0,r16
+ mfspr r10,SPRN_MAS1
+ andis. r10,r10,MAS1_VALID@h
+ bne tlb_miss_done_e6500
+
+ /* Undo MAS-damage from the tlbsx */
+ mfspr r10,SPRN_MAS1
+ oris r10,r10,MAS1_VALID@h
+ mtspr SPRN_MAS1,r10
+ mtspr SPRN_MAS2,r15
+
+ /* Now, we need to walk the page tables. First check if we are in
+ * range.
+ */
+ rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
+ bne- tlb_miss_fault_e6500
+
+ rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
+ cmpldi cr0,r14,0
+ clrrdi r15,r15,3
+ beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
+ ldx r14,r14,r15 /* grab pgd entry */
+
+ rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
+ clrrdi r15,r15,3
+ cmpdi cr0,r14,0
+ bge tlb_miss_fault_e6500 /* Bad pgd entry or hugepage; bail */
+ ldx r14,r14,r15 /* grab pud entry */
+
+ rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
+ clrrdi r15,r15,3
+ cmpdi cr0,r14,0
+ bge tlb_miss_fault_e6500
+ ldx r14,r14,r15 /* Grab pmd entry */
+
+ mfspr r10,SPRN_MAS0
+ cmpdi cr0,r14,0
+ bge tlb_miss_fault_e6500
+
+ /* Now we build the MAS for a 2M indirect page:
+ *
+ * MAS 0 : ESEL needs to be filled by software round-robin
+ * MAS 1 : Almost fully setup
+ * - PID already updated by caller if necessary
+ * - TSIZE for now is base ind page size always
+ * MAS 2 : Use defaults
+ * MAS 3+7 : Needs to be done
+ */
+
+ ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
+ mtspr SPRN_MAS7_MAS3,r14
+
+ lbz r15,PERCORE_TLB_ESEL_NEXT(r11)
+ lbz r16,PERCORE_TLB_ESEL_MAX(r11)
+ lbz r14,PERCORE_TLB_ESEL_FIRST(r11)
+ rlwimi r10,r15,16,0x00ff0000 /* insert esel_next into MAS0 */
+ addi r15,r15,1 /* increment esel_next */
+ mtspr SPRN_MAS0,r10
+ cmpw r15,r16
+ iseleq r15,r14,r15 /* if next == last use first */
+ stb r15,PERCORE_TLB_ESEL_NEXT(r11)
+
+ tlbwe
+
+tlb_miss_done_e6500:
+ .macro tlb_unlock_e6500
+ li r15,0
+ isync
+ stb r15,PERCORE_TLB_LOCK(r11)
+ .endm
+
+ tlb_unlock_e6500
+ TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
+ tlb_epilog_bolted
+ rfi
+
+tlb_miss_kernel_e6500:
+ mfspr r10,SPRN_MAS1
+ ld r14,PACA_KERNELPGD(r13)
+ cmpldi cr0,r15,8 /* Check for vmalloc region */
+ rlwinm r10,r10,0,16,1 /* Clear TID */
+ mtspr SPRN_MAS1,r10
+ beq+ tlb_miss_common_e6500
+
+tlb_miss_fault_e6500:
+ tlb_unlock_e6500
+ /* We need to check if it was an instruction miss */
+ andi. r16,r16,1
+ bne itlb_miss_fault_e6500
+dtlb_miss_fault_e6500:
+ TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+ tlb_epilog_bolted
+ b exc_data_storage_book3e
+itlb_miss_fault_e6500:
+ TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+ tlb_epilog_bolted
+ b exc_instruction_storage_book3e
+
+
/**********************************************************************
* *
* TLB miss handling for Book3E with TLB reservation and HES support *
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index df32a83..2f09ddf 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -43,6 +43,7 @@
#include <asm/tlb.h>
#include <asm/code-patching.h>
#include <asm/hugetlb.h>
+#include <asm/paca.h>
#include "mmu_decl.h"
@@ -58,6 +59,10 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
.shift = 12,
.enc = BOOK3E_PAGESZ_4K,
},
+ [MMU_PAGE_2M] = {
+ .shift = 21,
+ .enc = BOOK3E_PAGESZ_2M,
+ },
[MMU_PAGE_4M] = {
.shift = 22,
.enc = BOOK3E_PAGESZ_4M,
@@ -136,7 +141,7 @@ static inline int mmu_get_tsize(int psize)
int mmu_linear_psize; /* Page size used for the linear mapping */
int mmu_pte_psize; /* Page size used for PTE pages */
int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
-int book3e_htw_enabled; /* Is HW tablewalk enabled ? */
+int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
unsigned long linear_map_top; /* Top of linear mapping */
#endif /* CONFIG_PPC64 */
@@ -377,7 +382,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
{
int tsize = mmu_psize_defs[mmu_pte_psize].enc;
- if (book3e_htw_enabled) {
+ if (book3e_htw_mode) {
unsigned long start = address & PMD_MASK;
unsigned long end = address + PMD_SIZE;
unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
@@ -413,10 +418,10 @@ static void setup_page_sizes(void)
int i, psize;
#ifdef CONFIG_PPC_FSL_BOOK3E
+ int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
unsigned int mmucfg = mfspr(SPRN_MMUCFG);
- if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) &&
- (mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
+ if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
unsigned int min_pg, max_pg;
@@ -430,7 +435,7 @@ static void setup_page_sizes(void)
def = &mmu_psize_defs[psize];
shift = def->shift;
- if (shift == 0)
+ if (shift == 0 || shift & 1)
continue;
/* adjust to be in terms of 4^shift Kb */
@@ -440,7 +445,40 @@ static void setup_page_sizes(void)
def->flags |= MMU_PAGE_SIZE_DIRECT;
}
- goto no_indirect;
+ goto out;
+ }
+
+ if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+ u32 tlb1cfg, tlb1ps;
+
+ tlb0cfg = mfspr(SPRN_TLB0CFG);
+ tlb1cfg = mfspr(SPRN_TLB1CFG);
+ tlb1ps = mfspr(SPRN_TLB1PS);
+ eptcfg = mfspr(SPRN_EPTCFG);
+
+ if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
+ book3e_htw_mode = PPC_HTW_E6500;
+
+ /*
+ * We expect 4K subpage size and unrestricted indirect size.
+ * The lack of a restriction on indirect size is a Freescale
+ * extension, indicated by PSn = 0 but SPSn != 0.
+ */
+ if (eptcfg != 2)
+ book3e_htw_mode = PPC_HTW_NONE;
+
+ for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
+ struct mmu_psize_def *def = &mmu_psize_defs[psize];
+
+ if (tlb1ps & (1U << (def->shift - 10))) {
+ def->flags |= MMU_PAGE_SIZE_DIRECT;
+
+ if (book3e_htw_mode && psize == MMU_PAGE_2M)
+ def->flags |= MMU_PAGE_SIZE_INDIRECT;
+ }
+ }
+
+ goto out;
}
#endif
@@ -457,8 +495,11 @@ static void setup_page_sizes(void)
}
/* Indirect page sizes supported ? */
- if ((tlb0cfg & TLBnCFG_IND) == 0)
- goto no_indirect;
+ if ((tlb0cfg & TLBnCFG_IND) == 0 ||
+ (tlb0cfg & TLBnCFG_PT) == 0)
+ goto out;
+
+ book3e_htw_mode = PPC_HTW_IBM;
/* Now, we only deal with one IND page size for each
* direct size. Hopefully all implementations today are
@@ -483,8 +524,8 @@ static void setup_page_sizes(void)
def->ind = ps + 10;
}
}
- no_indirect:
+out:
/* Cleanup array and print summary */
pr_info("MMU: Supported page sizes\n");
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
@@ -525,23 +566,23 @@ static void __patch_exception(int exc, unsigned long addr)
static void setup_mmu_htw(void)
{
- /* Check if HW tablewalk is present, and if yes, enable it by:
- *
- * - patching the TLB miss handlers to branch to the
- * one dedicates to it
- *
- * - setting the global book3e_htw_enabled
- */
- unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+ /*
+ * If we want to use HW tablewalk, enable it by patching the TLB miss
+ * handlers to branch to the one dedicated to it.
+ */
- if ((tlb0cfg & TLBnCFG_IND) &&
- (tlb0cfg & TLBnCFG_PT)) {
+ switch (book3e_htw_mode) {
+ case PPC_HTW_IBM:
patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
- book3e_htw_enabled = 1;
+ break;
+ case PPC_HTW_E6500:
+ patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
+ patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
+ break;
}
pr_info("MMU: Book3E HW tablewalk %s\n",
- book3e_htw_enabled ? "enabled" : "not supported");
+ book3e_htw_mode ? "enabled" : "not supported");
}
/*
@@ -581,8 +622,16 @@ static void __early_init_mmu(int boot_cpu)
/* Set MAS4 based on page table setting */
mas4 = 0x4 << MAS4_WIMGED_SHIFT;
- if (book3e_htw_enabled) {
- mas4 |= mas4 | MAS4_INDD;
+ switch (book3e_htw_mode) {
+ case PPC_HTW_E6500:
+ mas4 |= MAS4_INDD;
+ mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
+ mas4 |= MAS4_TLBSELD(1);
+ mmu_pte_psize = MMU_PAGE_2M;
+ break;
+
+ case PPC_HTW_IBM:
+ mas4 |= MAS4_INDD;
#ifdef CONFIG_PPC_64K_PAGES
mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
mmu_pte_psize = MMU_PAGE_256M;
@@ -590,13 +639,16 @@ static void __early_init_mmu(int boot_cpu)
mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
mmu_pte_psize = MMU_PAGE_1M;
#endif
- } else {
+ break;
+
+ case PPC_HTW_NONE:
#ifdef CONFIG_PPC_64K_PAGES
mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
#else
mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
#endif
mmu_pte_psize = mmu_virtual_psize;
+ break;
}
mtspr(SPRN_MAS4, mas4);
@@ -616,8 +668,11 @@ static void __early_init_mmu(int boot_cpu)
/* limit memory so we dont have linear faults */
memblock_enforce_memory_limit(linear_map_top);
- patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
- patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
+ if (book3e_htw_mode == PPC_HTW_NONE) {
+ patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
+ patch_exception(0x1e0,
+ exc_instruction_tlb_miss_bolted_book3e);
+ }
}
#endif
--
1.7.5.4
^ permalink raw reply related
* Re: [PATCH 2/2] powerpc/e6500: TLB miss handler with hardware tablewalk support
From: Benjamin Herrenschmidt @ 2012-06-15 1:05 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20120614234101.GB17147@tyr.buserror.net>
On Thu, 2012-06-14 at 18:41 -0500, Scott Wood wrote:
> There are a few things that make the existing hw tablewalk handlers
> unsuitable for e6500:
>
> - Indirect entries go in TLB1 (though the resulting direct entries go in
> TLB0).
That per-se doesn't justify a whole new handler... patching instructions
would do or storing the default target in the PACA... The rest
however...
> - It has threads, but no "tlbsrx." -- so we need a spinlock and
> a normal "tlbsx". Because we need this lock, hardware tablewalk
> is mandatory on e6500 unless we want to add spinlock+tlbsx to
> the normal bolted TLB miss handler.
Isn't this a violation of the architecture ? (Isn't tlbsrx. mandatory ?
in 2.06 MAV2 ?).
> - TLB1 has no HES (nor next-victim hint) so we need software round robin
> (TODO: integrate this round robin data with hugetlb/KVM)
Yuck :-)
> - The existing tablewalk handlers map half of a page table at a time,
> because IBM hardware has a fixed 1MiB indirect page size. e6500
> has variable size indirect entries, with a minimum of 2MiB.
> So we can't do the half-page indirect mapping, and even if we
> could it would be less efficient than mapping the full page.
Ok.
> - Like on e5500, the linear mapping is bolted, so we don't need the
> overhead of supporting nested tlb misses.
>
> Note that hardware tablewalk does not work in rev1 of e6500.
> We do not expect to support e6500 rev1 in mainline Linux.
I'll try to review that in more details next week....
Ben.
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> arch/powerpc/include/asm/mmu-book3e.h | 13 +++
> arch/powerpc/include/asm/mmu.h | 21 ++--
> arch/powerpc/include/asm/paca.h | 6 +
> arch/powerpc/kernel/asm-offsets.c | 10 ++
> arch/powerpc/kernel/paca.c | 5 +
> arch/powerpc/kernel/setup_64.c | 33 +++++++
> arch/powerpc/mm/fsl_booke_mmu.c | 8 ++
> arch/powerpc/mm/tlb_low_64e.S | 167 +++++++++++++++++++++++++++++++++
> arch/powerpc/mm/tlb_nohash.c | 109 ++++++++++++++++------
> 9 files changed, 335 insertions(+), 37 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
> index eeabcdb..3072aa0 100644
> --- a/arch/powerpc/include/asm/mmu-book3e.h
> +++ b/arch/powerpc/include/asm/mmu-book3e.h
> @@ -264,8 +264,21 @@ extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
> extern int mmu_linear_psize;
> extern int mmu_vmemmap_psize;
>
> +struct book3e_tlb_per_core {
> + /* For software way selection, as on Freescale TLB1 */
> + u8 esel_next, esel_max, esel_first;
> +
> + /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */
> + u8 lock;
> +};
> +
> #ifdef CONFIG_PPC64
> extern unsigned long linear_map_top;
> +extern int book3e_htw_mode;
> +
> +#define PPC_HTW_NONE 0
> +#define PPC_HTW_IBM 1
> +#define PPC_HTW_E6500 2
>
> /*
> * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index a9e9ec6..63d97eb 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -170,16 +170,17 @@ extern u64 ppc64_rma_size;
> #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
> #define MMU_PAGE_256K 4
> #define MMU_PAGE_1M 5
> -#define MMU_PAGE_4M 6
> -#define MMU_PAGE_8M 7
> -#define MMU_PAGE_16M 8
> -#define MMU_PAGE_64M 9
> -#define MMU_PAGE_256M 10
> -#define MMU_PAGE_1G 11
> -#define MMU_PAGE_16G 12
> -#define MMU_PAGE_64G 13
> -
> -#define MMU_PAGE_COUNT 14
> +#define MMU_PAGE_2M 6
> +#define MMU_PAGE_4M 7
> +#define MMU_PAGE_8M 8
> +#define MMU_PAGE_16M 9
> +#define MMU_PAGE_64M 10
> +#define MMU_PAGE_256M 11
> +#define MMU_PAGE_1G 12
> +#define MMU_PAGE_16G 13
> +#define MMU_PAGE_64G 14
> +
> +#define MMU_PAGE_COUNT 15
>
> #if defined(CONFIG_PPC_STD_MMU_64)
> /* 64-bit classic hash table MMU */
> diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
> index daf813f..4e18bb5 100644
> --- a/arch/powerpc/include/asm/paca.h
> +++ b/arch/powerpc/include/asm/paca.h
> @@ -108,6 +108,12 @@ struct paca_struct {
> /* Keep pgd in the same cacheline as the start of extlb */
> pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */
> pgd_t *kernel_pgd; /* Kernel PGD */
> +
> + struct book3e_tlb_per_core tlb_per_core;
> +
> + /* Points to the tlb_per_core of the first thread on this core. */
> + struct book3e_tlb_per_core *tlb_per_core_ptr;
> +
> /* We can have up to 3 levels of reentrancy in the TLB miss handler */
> u64 extlb[3][EX_TLB_SIZE / sizeof(u64)];
> u64 exmc[8]; /* used for machine checks */
> diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
> index 52c7ad7..61f4634 100644
> --- a/arch/powerpc/kernel/asm-offsets.c
> +++ b/arch/powerpc/kernel/asm-offsets.c
> @@ -168,6 +168,16 @@ int main(void)
> DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
> DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
> DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
> + DEFINE(PACA_TLB_PER_CORE_PTR,
> + offsetof(struct paca_struct, tlb_per_core_ptr));
> +
> + DEFINE(PERCORE_TLB_ESEL_NEXT,
> + offsetof(struct book3e_tlb_per_core, esel_next));
> + DEFINE(PERCORE_TLB_ESEL_MAX,
> + offsetof(struct book3e_tlb_per_core, esel_max));
> + DEFINE(PERCORE_TLB_ESEL_FIRST,
> + offsetof(struct book3e_tlb_per_core, esel_first));
> + DEFINE(PERCORE_TLB_LOCK, offsetof(struct book3e_tlb_per_core, lock));
> #endif /* CONFIG_PPC_BOOK3E */
>
> #ifdef CONFIG_PPC_STD_MMU_64
> diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
> index fbe1a12..65abfc0 100644
> --- a/arch/powerpc/kernel/paca.c
> +++ b/arch/powerpc/kernel/paca.c
> @@ -145,6 +145,11 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
> #ifdef CONFIG_PPC_STD_MMU_64
> new_paca->slb_shadow_ptr = &slb_shadow[cpu];
> #endif /* CONFIG_PPC_STD_MMU_64 */
> +
> +#ifdef CONFIG_PPC_BOOK3E
> + /* For now -- if we have threads this will be adjusted later */
> + new_paca->tlb_per_core_ptr = &new_paca->tlb_per_core;
> +#endif
> }
>
> /* Put the paca pointer into r13 and SPRG_PACA */
> diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
> index 389bd4f..271b85d 100644
> --- a/arch/powerpc/kernel/setup_64.c
> +++ b/arch/powerpc/kernel/setup_64.c
> @@ -102,6 +102,37 @@ int ucache_bsize;
>
> static char *smt_enabled_cmdline;
>
> +#ifdef CONFIG_PPC_BOOK3E
> +static void setup_tlb_per_core(void)
> +{
> + int cpu;
> +
> + for_each_possible_cpu(cpu) {
> + int first = cpu_first_thread_sibling(cpu);
> +
> + paca[cpu].tlb_per_core_ptr = &paca[first].tlb_per_core;
> +
> + /*
> + * If we have threads, we need either tlbsrx.
> + * or e6500 tablewalk mode, or else TLB handlers
> + * will be racy and could produce duplicate entries.
> + */
> + if (smt_enabled_at_boot >= 2 &&
> + !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
> + book3e_htw_mode != PPC_HTW_E6500) {
> + /* Should we panic instead? */
> + WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
> + __func__);
> + }
> + }
> +}
> +#else
> +static void setup_tlb_per_core(void)
> +{
> +}
> +#endif
> +
> +
> /* Look for ibm,smt-enabled OF option */
> static void check_smt_enabled(void)
> {
> @@ -142,6 +173,8 @@ static void check_smt_enabled(void)
> of_node_put(dn);
> }
> }
> +
> + setup_tlb_per_core();
> }
>
> /* Look for smt-enabled= cmdline option */
> diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
> index 07ba45b..bf06d36b 100644
> --- a/arch/powerpc/mm/fsl_booke_mmu.c
> +++ b/arch/powerpc/mm/fsl_booke_mmu.c
> @@ -52,6 +52,7 @@
> #include <asm/smp.h>
> #include <asm/machdep.h>
> #include <asm/setup.h>
> +#include <asm/paca.h>
>
> #include "mmu_decl.h"
>
> @@ -192,6 +193,13 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx)
> }
> tlbcam_index = i;
>
> +#ifdef CONFIG_PPC64
> + get_paca()->tlb_per_core.esel_next = i;
> + get_paca()->tlb_per_core.esel_max =
> + mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
> + get_paca()->tlb_per_core.esel_first = i;
> +#endif
> +
> return amount_mapped;
> }
>
> diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
> index efe0f33..8e82772 100644
> --- a/arch/powerpc/mm/tlb_low_64e.S
> +++ b/arch/powerpc/mm/tlb_low_64e.S
> @@ -232,6 +232,173 @@ itlb_miss_fault_bolted:
> beq tlb_miss_common_bolted
> b itlb_miss_kernel_bolted
>
> +/*
> + * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
> + *
> + * Linear mapping is bolted: no virtual page table or nested TLB misses
> + * Indirect entries in TLB1, hardware loads resulting direct entries
> + * into TLB0
> + * No HES or NV hint on TLB1, so we need to do software round-robin
> + * No tlbsrx. so we need a spinlock, and we have to deal
> + * with MAS-damage caused by tlbsx
> + * 4K pages only
> + */
> +
> + START_EXCEPTION(instruction_tlb_miss_e6500)
> + tlb_prolog_bolted SPRN_SRR0
> +
> + ld r11,PACA_TLB_PER_CORE_PTR(r13)
> + srdi. r15,r16,60 /* get region */
> + ori r16,r16,1
> +
> + TLB_MISS_STATS_SAVE_INFO_BOLTED
> + bne tlb_miss_kernel_e6500 /* user/kernel test */
> +
> + b tlb_miss_common_e6500
> +
> + START_EXCEPTION(data_tlb_miss_e6500)
> + tlb_prolog_bolted SPRN_DEAR
> +
> + ld r11,PACA_TLB_PER_CORE_PTR(r13)
> + srdi. r15,r16,60 /* get region */
> + rldicr r16,r16,0,62
> +
> + TLB_MISS_STATS_SAVE_INFO_BOLTED
> + bne tlb_miss_kernel_e6500 /* user vs kernel check */
> +
> +/*
> + * This is the guts of the TLB miss handler for e6500 and derivatives.
> + * We are entered with:
> + *
> + * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
> + * r15 = crap (free to use)
> + * r14 = page table base
> + * r13 = PACA
> + * r11 = tlb_per_core ptr
> + * r10 = crap (free to use)
> + */
> +tlb_miss_common_e6500:
> + /*
> + * Search if we already have an indirect entry for that virtual
> + * address, and if we do, bail out.
> + *
> + * MAS6:IND should be already set based on MAS4
> + */
> + addi r10,r11,PERCORE_TLB_LOCK
> +1: lbarx r15,0,r10
> + cmpdi r15,0
> + bne 2f
> + li r15,1
> + stbcx. r15,0,r10
> + bne 1b
> + .subsection 1
> +2: lbz r15,0(r10)
> + cmpdi r15,0
> + bne 2b
> + b 1b
> + .previous
> +
> + mfspr r15,SPRN_MAS2
> +
> + tlbsx 0,r16
> + mfspr r10,SPRN_MAS1
> + andis. r10,r10,MAS1_VALID@h
> + bne tlb_miss_done_e6500
> +
> + /* Undo MAS-damage from the tlbsx */
> + mfspr r10,SPRN_MAS1
> + oris r10,r10,MAS1_VALID@h
> + mtspr SPRN_MAS1,r10
> + mtspr SPRN_MAS2,r15
> +
> + /* Now, we need to walk the page tables. First check if we are in
> + * range.
> + */
> + rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
> + bne- tlb_miss_fault_e6500
> +
> + rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
> + cmpldi cr0,r14,0
> + clrrdi r15,r15,3
> + beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
> + ldx r14,r14,r15 /* grab pgd entry */
> +
> + rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
> + clrrdi r15,r15,3
> + cmpdi cr0,r14,0
> + bge tlb_miss_fault_e6500 /* Bad pgd entry or hugepage; bail */
> + ldx r14,r14,r15 /* grab pud entry */
> +
> + rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
> + clrrdi r15,r15,3
> + cmpdi cr0,r14,0
> + bge tlb_miss_fault_e6500
> + ldx r14,r14,r15 /* Grab pmd entry */
> +
> + mfspr r10,SPRN_MAS0
> + cmpdi cr0,r14,0
> + bge tlb_miss_fault_e6500
> +
> + /* Now we build the MAS for a 2M indirect page:
> + *
> + * MAS 0 : ESEL needs to be filled by software round-robin
> + * MAS 1 : Almost fully setup
> + * - PID already updated by caller if necessary
> + * - TSIZE for now is base ind page size always
> + * MAS 2 : Use defaults
> + * MAS 3+7 : Needs to be done
> + */
> +
> + ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
> + mtspr SPRN_MAS7_MAS3,r14
> +
> + lbz r15,PERCORE_TLB_ESEL_NEXT(r11)
> + lbz r16,PERCORE_TLB_ESEL_MAX(r11)
> + lbz r14,PERCORE_TLB_ESEL_FIRST(r11)
> + rlwimi r10,r15,16,0x00ff0000 /* insert esel_next into MAS0 */
> + addi r15,r15,1 /* increment esel_next */
> + mtspr SPRN_MAS0,r10
> + cmpw r15,r16
> + iseleq r15,r14,r15 /* if next == last use first */
> + stb r15,PERCORE_TLB_ESEL_NEXT(r11)
> +
> + tlbwe
> +
> +tlb_miss_done_e6500:
> + .macro tlb_unlock_e6500
> + li r15,0
> + isync
> + stb r15,PERCORE_TLB_LOCK(r11)
> + .endm
> +
> + tlb_unlock_e6500
> + TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
> + tlb_epilog_bolted
> + rfi
> +
> +tlb_miss_kernel_e6500:
> + mfspr r10,SPRN_MAS1
> + ld r14,PACA_KERNELPGD(r13)
> + cmpldi cr0,r15,8 /* Check for vmalloc region */
> + rlwinm r10,r10,0,16,1 /* Clear TID */
> + mtspr SPRN_MAS1,r10
> + beq+ tlb_miss_common_e6500
> +
> +tlb_miss_fault_e6500:
> + tlb_unlock_e6500
> + /* We need to check if it was an instruction miss */
> + andi. r16,r16,1
> + bne itlb_miss_fault_e6500
> +dtlb_miss_fault_e6500:
> + TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
> + tlb_epilog_bolted
> + b exc_data_storage_book3e
> +itlb_miss_fault_e6500:
> + TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
> + tlb_epilog_bolted
> + b exc_instruction_storage_book3e
> +
> +
> /**********************************************************************
> * *
> * TLB miss handling for Book3E with TLB reservation and HES support *
> diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
> index df32a83..2f09ddf 100644
> --- a/arch/powerpc/mm/tlb_nohash.c
> +++ b/arch/powerpc/mm/tlb_nohash.c
> @@ -43,6 +43,7 @@
> #include <asm/tlb.h>
> #include <asm/code-patching.h>
> #include <asm/hugetlb.h>
> +#include <asm/paca.h>
>
> #include "mmu_decl.h"
>
> @@ -58,6 +59,10 @@ struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
> .shift = 12,
> .enc = BOOK3E_PAGESZ_4K,
> },
> + [MMU_PAGE_2M] = {
> + .shift = 21,
> + .enc = BOOK3E_PAGESZ_2M,
> + },
> [MMU_PAGE_4M] = {
> .shift = 22,
> .enc = BOOK3E_PAGESZ_4M,
> @@ -136,7 +141,7 @@ static inline int mmu_get_tsize(int psize)
> int mmu_linear_psize; /* Page size used for the linear mapping */
> int mmu_pte_psize; /* Page size used for PTE pages */
> int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
> -int book3e_htw_enabled; /* Is HW tablewalk enabled ? */
> +int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
> unsigned long linear_map_top; /* Top of linear mapping */
>
> #endif /* CONFIG_PPC64 */
> @@ -377,7 +382,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
> {
> int tsize = mmu_psize_defs[mmu_pte_psize].enc;
>
> - if (book3e_htw_enabled) {
> + if (book3e_htw_mode) {
> unsigned long start = address & PMD_MASK;
> unsigned long end = address + PMD_SIZE;
> unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
> @@ -413,10 +418,10 @@ static void setup_page_sizes(void)
> int i, psize;
>
> #ifdef CONFIG_PPC_FSL_BOOK3E
> + int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
> unsigned int mmucfg = mfspr(SPRN_MMUCFG);
>
> - if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) &&
> - (mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
> + if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
> unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
> unsigned int min_pg, max_pg;
>
> @@ -430,7 +435,7 @@ static void setup_page_sizes(void)
> def = &mmu_psize_defs[psize];
> shift = def->shift;
>
> - if (shift == 0)
> + if (shift == 0 || shift & 1)
> continue;
>
> /* adjust to be in terms of 4^shift Kb */
> @@ -440,7 +445,40 @@ static void setup_page_sizes(void)
> def->flags |= MMU_PAGE_SIZE_DIRECT;
> }
>
> - goto no_indirect;
> + goto out;
> + }
> +
> + if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
> + u32 tlb1cfg, tlb1ps;
> +
> + tlb0cfg = mfspr(SPRN_TLB0CFG);
> + tlb1cfg = mfspr(SPRN_TLB1CFG);
> + tlb1ps = mfspr(SPRN_TLB1PS);
> + eptcfg = mfspr(SPRN_EPTCFG);
> +
> + if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
> + book3e_htw_mode = PPC_HTW_E6500;
> +
> + /*
> + * We expect 4K subpage size and unrestricted indirect size.
> + * The lack of a restriction on indirect size is a Freescale
> + * extension, indicated by PSn = 0 but SPSn != 0.
> + */
> + if (eptcfg != 2)
> + book3e_htw_mode = PPC_HTW_NONE;
> +
> + for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
> + struct mmu_psize_def *def = &mmu_psize_defs[psize];
> +
> + if (tlb1ps & (1U << (def->shift - 10))) {
> + def->flags |= MMU_PAGE_SIZE_DIRECT;
> +
> + if (book3e_htw_mode && psize == MMU_PAGE_2M)
> + def->flags |= MMU_PAGE_SIZE_INDIRECT;
> + }
> + }
> +
> + goto out;
> }
> #endif
>
> @@ -457,8 +495,11 @@ static void setup_page_sizes(void)
> }
>
> /* Indirect page sizes supported ? */
> - if ((tlb0cfg & TLBnCFG_IND) == 0)
> - goto no_indirect;
> + if ((tlb0cfg & TLBnCFG_IND) == 0 ||
> + (tlb0cfg & TLBnCFG_PT) == 0)
> + goto out;
> +
> + book3e_htw_mode = PPC_HTW_IBM;
>
> /* Now, we only deal with one IND page size for each
> * direct size. Hopefully all implementations today are
> @@ -483,8 +524,8 @@ static void setup_page_sizes(void)
> def->ind = ps + 10;
> }
> }
> - no_indirect:
>
> +out:
> /* Cleanup array and print summary */
> pr_info("MMU: Supported page sizes\n");
> for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
> @@ -525,23 +566,23 @@ static void __patch_exception(int exc, unsigned long addr)
>
> static void setup_mmu_htw(void)
> {
> - /* Check if HW tablewalk is present, and if yes, enable it by:
> - *
> - * - patching the TLB miss handlers to branch to the
> - * one dedicates to it
> - *
> - * - setting the global book3e_htw_enabled
> - */
> - unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
> + /*
> + * If we want to use HW tablewalk, enable it by patching the TLB miss
> + * handlers to branch to the one dedicated to it.
> + */
>
> - if ((tlb0cfg & TLBnCFG_IND) &&
> - (tlb0cfg & TLBnCFG_PT)) {
> + switch (book3e_htw_mode) {
> + case PPC_HTW_IBM:
> patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
> patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
> - book3e_htw_enabled = 1;
> + break;
> + case PPC_HTW_E6500:
> + patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
> + patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
> + break;
> }
> pr_info("MMU: Book3E HW tablewalk %s\n",
> - book3e_htw_enabled ? "enabled" : "not supported");
> + book3e_htw_mode ? "enabled" : "not supported");
> }
>
> /*
> @@ -581,8 +622,16 @@ static void __early_init_mmu(int boot_cpu)
> /* Set MAS4 based on page table setting */
>
> mas4 = 0x4 << MAS4_WIMGED_SHIFT;
> - if (book3e_htw_enabled) {
> - mas4 |= mas4 | MAS4_INDD;
> + switch (book3e_htw_mode) {
> + case PPC_HTW_E6500:
> + mas4 |= MAS4_INDD;
> + mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
> + mas4 |= MAS4_TLBSELD(1);
> + mmu_pte_psize = MMU_PAGE_2M;
> + break;
> +
> + case PPC_HTW_IBM:
> + mas4 |= MAS4_INDD;
> #ifdef CONFIG_PPC_64K_PAGES
> mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
> mmu_pte_psize = MMU_PAGE_256M;
> @@ -590,13 +639,16 @@ static void __early_init_mmu(int boot_cpu)
> mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
> mmu_pte_psize = MMU_PAGE_1M;
> #endif
> - } else {
> + break;
> +
> + case PPC_HTW_NONE:
> #ifdef CONFIG_PPC_64K_PAGES
> mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
> #else
> mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
> #endif
> mmu_pte_psize = mmu_virtual_psize;
> + break;
> }
> mtspr(SPRN_MAS4, mas4);
>
> @@ -616,8 +668,11 @@ static void __early_init_mmu(int boot_cpu)
> /* limit memory so we dont have linear faults */
> memblock_enforce_memory_limit(linear_map_top);
>
> - patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
> - patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
> + if (book3e_htw_mode == PPC_HTW_NONE) {
> + patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
> + patch_exception(0x1e0,
> + exc_instruction_tlb_miss_bolted_book3e);
> + }
> }
> #endif
>
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/mm: remove obsolete comment about page size name array
From: Michael Ellerman @ 2012-06-15 2:50 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20120614234055.GA17147@tyr.buserror.net>
On Thu, 2012-06-14 at 18:40 -0500, Scott Wood wrote:
> The array of names in hugetlbpage.c no longer exists.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
> arch/powerpc/include/asm/mmu.h | 7 +------
> 1 files changed, 1 insertions(+), 6 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index f014552..a9e9ec6 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -163,12 +163,7 @@ extern u64 ppc64_rma_size;
> * to think about, feedback welcome. --BenH.
> */
>
> -/* There are #define as they have to be used in assembly
> - *
> - * WARNING: If you change this list, make sure to update the array of
> - * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
> - * happen
> - */
> +/* There are #define as they have to be used in assembly */
^^^^^^
Should be "These", I'll fix it up.
cheers
^ permalink raw reply
* RE: [PATCH] powerpc/44x: Support OCM(On Chip Memory) for APM821xx SoC and Bluestone board
From: Vinh Huu Tuong Nguyen @ 2012-06-15 3:19 UTC (permalink / raw)
To: Josh Boyer
Cc: Anatolij Gustschin, devicetree-discuss, Duc Dang, Rob Herring,
linux-kernel, Liu Gang, Paul Mackerras, linuxppc-dev,
David S. Miller
In-Reply-To: <CA+5PVA7vnLvqwsDAboR4s-QCLWSDm34N2tE+sFiBMsE2f=qYEg@mail.gmail.com>
> -----Original Message-----
> From: Josh Boyer [mailto:jwboyer@gmail.com]
> Sent: Friday, June 15, 2012 12:47 AM
> To: Vinh Nguyen Huu Tuong
> Cc: Benjamin Herrenschmidt; Paul Mackerras; Matt Porter; Grant Likely;
> Rob Herring; Duc Dang; David S. Miller; Kumar Gala; Li Yang; Ashish
> Kalra; Anatolij Gustschin; Liu Gang; linuxppc-dev@lists.ozlabs.org;
> linux-kernel@vger.kernel.org; devicetree-discuss@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc/44x: Support OCM(On Chip Memory) for
> APM821xx SoC and Bluestone board
>
> On Sun, May 6, 2012 at 11:52 PM, Vinh Nguyen Huu Tuong
> <vhtnguyen@apm.com> wrote:
> > This patch consists of:
> > - Add driver for OCM component
> > - Export OCM Information at /sys/class/ocm/ocminfo
>
> Again, apologies for the delay. Aside from the incorrect sysfs usage I
> pointed out in my other reply, I have just a few comments/questions
> below.
[Vinh Nguyen] You're welcome. About the files on sysfs, the first place of
ocm is in procfs, but procfs is deprecated and replaced by sysfs, then I
decided to move it to sysfs. With your comments, I think I can move it to
debugfs.
>
> > diff --git a/arch/powerpc/boot/dts/bluestone.dts
> > b/arch/powerpc/boot/dts/bluestone.dts
> > index 7bda373..2687c11 100644
> > --- a/arch/powerpc/boot/dts/bluestone.dts
> > +++ b/arch/powerpc/boot/dts/bluestone.dts
> > @@ -107,6 +107,14 @@
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D <&UIC0>;
> > =A0 =A0 =A0 =A0};
> >
> > + =A0 =A0 =A0 OCM1: ocm@400040000 {
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "ibm,ocm";
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 status =3D "ok";
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cell-index =3D <1>;
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* configured in U-Boot */
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <4 0x00040000 0x8000>; /* 32K */
> > + =A0 =A0 =A0 };
> > +
> > =A0 =A0 =A0 =A0SDR0: sdr {
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "ibm,sdr-apm821xx";
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dcr-reg =3D <0x00e 0x002>; diff --git
> > a/arch/powerpc/include/asm/ppc4xx_ocm.h
> > b/arch/powerpc/include/asm/ppc4xx_ocm.h
> > new file mode 100644
> > index 0000000..ff7f386
> > --- /dev/null
> > +++ b/arch/powerpc/include/asm/ppc4xx_ocm.h
> > @@ -0,0 +1,47 @@
> > +/*
> > + * PowerPC 4xx OCM memory allocation support
> > + *
> > + * (C) Copyright 2009, Applied Micro Circuits Corporation
> > + * Victor Gallardo (vgallardo@amcc.com)
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#ifndef __ASM_POWERPC_PPC4xx_OCM_H__
> > +#define __ASM_POWERPC_PPC4xx_OCM_H__
> > +
> > +#include <linux/types.h>
> > +
> > +#define OCM_NON_CACHED 0
> > +#define OCM_CACHED =A0 =A0 1
> > +
> > +#if defined(CONFIG_PPC4xx_OCM)
> > +
> > +void *ocm_alloc(phys_addr_t *phys, int size, int align,
> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 int flags, const char *owner); void o=
cm_free(const
> > +void *virt);
> > +
> > +#else
> > +
> > +#define ocm_alloc(phys, size, align, flags, owner) =A0 =A0 NULL #defin=
e
> > +ocm_free(addr) ((void)0)
> > +
> > +#endif /* CONFIG_PPC4xx_OCM */
> > +
> > +#endif =A0/* __ASM_POWERPC_PPC4xx_OCM_H__ */
>
> I don't see any users of this header included in the patch. I'm going
> to guess that follow-on drivers/users are queued once this is in the
> tree? Also, you might want to name these 'ppc4xx_ocm_alloc' or
> similar. The concept of OCM isn't limited to ppc4xx or even SoCs, so
> just using 'ocm' in the global kernel namespace might not be great.
>
[Vinh Nguyen] With our plan, the next submit of IBM NEW EMAC will use it
for speedup. About the naming convention, I will change as your comments.
> > diff --git a/arch/powerpc/sysdev/ppc4xx_ocm.c
> > b/arch/powerpc/sysdev/ppc4xx_ocm.c
> > new file mode 100644
> > index 0000000..ba3e450
> > --- /dev/null
> > +++ b/arch/powerpc/sysdev/ppc4xx_ocm.c
> > @@ -0,0 +1,420 @@
> > +#include <linux/kernel.h>
> > +#include <linux/errno.h>
> > +#include <linux/proc_fs.h>
>
> Why do you need proc_fs.h?
[Vinh Nguyen] I will remove it.
>
> > +#include <linux/seq_file.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/list.h>
> > +#include <asm/uaccess.h>
> > +#include <asm/prom.h>
> > +#include <asm/dcr.h>
> > +#include <asm/rheap.h>
> > +#include <asm/mmu.h>
> > +#include <asm/ppc4xx_ocm.h>
> > +#include <linux/export.h>
> > +
> > +#define OCM_DISABLED =A0 0
> > +#define OCM_ENABLED =A0 =A0 =A0 =A0 =A0 =A01
> > +
> > +struct ocm_block {
> > + =A0 =A0 =A0 struct list_head =A0 =A0 =A0 =A0list;
> > + =A0 =A0 =A0 void __iomem =A0 =A0 =A0 =A0 =A0 =A0*addr;
> > + =A0 =A0 =A0 int =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 size;
> > + =A0 =A0 =A0 const char =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0*ow=
ner; };
> > +
> > +/* non-cached or cached region */
> > +struct ocm_region {
> > + =A0 =A0 =A0 phys_addr_t =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 phys;
> > + =A0 =A0 =A0 void __iomem =A0 =A0 =A0 =A0 =A0 =A0*virt;
> > +
> > + =A0 =A0 =A0 int =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 memtotal;
> > + =A0 =A0 =A0 int =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 memfree;
> > +
> > + =A0 =A0 =A0 rh_info_t =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 *rh=
;
> > + =A0 =A0 =A0 struct list_head =A0 =A0 =A0 =A0list;
> > +};
>
> There's some interesting whitespace usage in these struct definitions.
[Vinh Nguyen] I'll check again and remove them. I used the scripts check
in kernel but it can't remove them all.
>
> josh
I'll update the patch soon but I need send out to internal review first
before sending out to community. It takes one or two week, please be
patient for the next review.
Best regards,
Vinh Nguyen
^ permalink raw reply
* [PATCH v2] Make hard_irq_disable() actually hard-disable interrupts
From: Paul Mackerras @ 2012-06-15 4:51 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt
At present, hard_irq_disable() does nothing on powerpc because of
this code in include/linux/interrupt.h:
#ifndef hard_irq_disable
#define hard_irq_disable() do { } while(0)
#endif
So we need to make our hard_irq_disable be a macro.
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
--
arch/powerpc/include/asm/hw_irq.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index c9aac24..32b394f 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -100,6 +100,9 @@ static inline void hard_irq_disable(void)
get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
}
+/* include/linux/interrupt.h needs hard_irq_disable to be a macro */
+#define hard_irq_disable hard_irq_disable
+
/*
* This is called by asynchronous interrupts to conditionally
* re-enable hard interrupts when soft-disabled after having
^ permalink raw reply related
* Re: [PATCH v2] Make hard_irq_disable() actually hard-disable interrupts
From: Benjamin Herrenschmidt @ 2012-06-15 6:02 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120615045139.GA11041@pale.ozlabs.ibm.com>
On Fri, 2012-06-15 at 14:51 +1000, Paul Mackerras wrote:
> At present, hard_irq_disable() does nothing on powerpc because of
> this code in include/linux/interrupt.h:
>
> #ifndef hard_irq_disable
> #define hard_irq_disable() do { } while(0)
> #endif
>
> So we need to make our hard_irq_disable be a macro.
>
> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Paul Mackerras <paulus@samba.org>
Add:
CC: <stable@kernel.org> [v3.4]
Before sending to Linus so it hits stable automagically.
Cheers,
Ben.
> --
> arch/powerpc/include/asm/hw_irq.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
> index c9aac24..32b394f 100644
> --- a/arch/powerpc/include/asm/hw_irq.h
> +++ b/arch/powerpc/include/asm/hw_irq.h
> @@ -100,6 +100,9 @@ static inline void hard_irq_disable(void)
> get_paca()->irq_happened |= PACA_IRQ_HARD_DIS;
> }
>
> +/* include/linux/interrupt.h needs hard_irq_disable to be a macro */
> +#define hard_irq_disable hard_irq_disable
> +
> /*
> * This is called by asynchronous interrupts to conditionally
> * re-enable hard interrupts when soft-disabled after having
^ permalink raw reply
* [PATCH] common: dma-mapping: add support for generic dma_mmap_* calls
From: Marek Szyprowski @ 2012-06-15 6:18 UTC (permalink / raw)
To: linux-arm-kernel, linuxppc-dev, linaro-mm-sig, linux-mm,
linux-arch, linux-kernel
Cc: Russell King - ARM Linux, Arnd Bergmann, Konrad Rzeszutek Wilk,
Subash Patel, Kyungmin Park, David Gibson, Sumit Semwal,
Marek Szyprowski
Commit 9adc5374 ('common: dma-mapping: introduce mmap method') added a
generic method for implementing mmap user call to dma_map_ops structure.
This patch converts ARM and PowerPC architectures (the only providers of
dma_mmap_coherent/dma_mmap_writecombine calls) to use this generic
dma_map_ops based call and adds a generic cross architecture
definition for dma_mmap_attrs, dma_mmap_coherent, dma_mmap_writecombine
functions.
The generic mmap virt_to_page-based fallback implementation is provided for
architectures which don't provide their own implementation for mmap method.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
---
Hello,
This patch is a continuation of my works on dma-mapping cleanup and
unification. Previous works (commit 58bca4a8fa ('Merge branch
'for-linus' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping')
has been merged to v3.4-rc2. Now I've focuses on providing implementation
for all architectures so the drivers and some cross-architecture common
helpers (like for example videobuf2) can start using this new api.
I'm not 100% sure if the PowerPC changes are correct. The cases of
dma_iommu_ops and vio_dma_mapping_ops are a bit suspicious for me, but I
have no way to test and check if my changes works for that hardware.
Best regards
Marek Szyprowski
Samsung Poland R&D Center
---
arch/arm/include/asm/dma-mapping.h | 19 ---------------
arch/powerpc/include/asm/dma-mapping.h | 8 +++---
arch/powerpc/kernel/dma-iommu.c | 1 +
arch/powerpc/kernel/dma-swiotlb.c | 1 +
arch/powerpc/kernel/dma.c | 36 +++++++++++++++-------------
arch/powerpc/kernel/vio.c | 1 +
drivers/base/dma-mapping.c | 31 +++++++++++++++++++++++++
include/asm-generic/dma-coherent.h | 1 +
include/asm-generic/dma-mapping-common.h | 37 ++++++++++++++++++++++++++++++
9 files changed, 95 insertions(+), 40 deletions(-)
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index bbef15d..8645088 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -186,17 +186,6 @@ extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
void *cpu_addr, dma_addr_t dma_addr, size_t size,
struct dma_attrs *attrs);
-#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL)
-
-static inline int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
- void *cpu_addr, dma_addr_t dma_addr,
- size_t size, struct dma_attrs *attrs)
-{
- struct dma_map_ops *ops = get_dma_ops(dev);
- BUG_ON(!ops);
- return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
-}
-
static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag)
{
@@ -213,14 +202,6 @@ static inline void dma_free_writecombine(struct device *dev, size_t size,
return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
}
-static inline int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
- void *cpu_addr, dma_addr_t dma_addr, size_t size)
-{
- DEFINE_DMA_ATTRS(attrs);
- dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
- return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
-}
-
/*
* This can be called during boot to increase the size of the consistent
* DMA region above it's default value of 2MB. It must be called before the
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index 62678e3..7816087 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -27,7 +27,10 @@ extern void *dma_direct_alloc_coherent(struct device *dev, size_t size,
extern void dma_direct_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle,
struct dma_attrs *attrs);
-
+extern int dma_direct_mmap_coherent(struct device *dev,
+ struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t handle,
+ size_t size, struct dma_attrs *attrs);
#ifdef CONFIG_NOT_COHERENT_CACHE
/*
@@ -207,11 +210,8 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-extern int dma_mmap_coherent(struct device *, struct vm_area_struct *,
- void *, dma_addr_t, size_t);
#define ARCH_HAS_DMA_MMAP_COHERENT
-
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction direction)
{
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index bcfdcd2..2d7bb8c 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -109,6 +109,7 @@ static u64 dma_iommu_get_required_mask(struct device *dev)
struct dma_map_ops dma_iommu_ops = {
.alloc = dma_iommu_alloc_coherent,
.free = dma_iommu_free_coherent,
+ .mmap = dma_direct_mmap_coherent,
.map_sg = dma_iommu_map_sg,
.unmap_sg = dma_iommu_unmap_sg,
.dma_supported = dma_iommu_dma_supported,
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index 4ab88da..4694365 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -49,6 +49,7 @@ static u64 swiotlb_powerpc_get_required(struct device *dev)
struct dma_map_ops swiotlb_dma_ops = {
.alloc = dma_direct_alloc_coherent,
.free = dma_direct_free_coherent,
+ .mmap = dma_direct_mmap_coherent,
.map_sg = swiotlb_map_sg_attrs,
.unmap_sg = swiotlb_unmap_sg_attrs,
.dma_supported = swiotlb_dma_supported,
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index b1ec983..062bf20 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -65,6 +65,24 @@ void dma_direct_free_coherent(struct device *dev, size_t size,
#endif
}
+int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t handle, size_t size,
+ struct dma_attrs *attrs)
+{
+ unsigned long pfn;
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+ pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr);
+#else
+ pfn = page_to_pfn(virt_to_page(cpu_addr));
+#endif
+ return remap_pfn_range(vma, vma->vm_start,
+ pfn + vma->vm_pgoff,
+ vma->vm_end - vma->vm_start,
+ vma->vm_page_prot);
+}
+
static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
int nents, enum dma_data_direction direction,
struct dma_attrs *attrs)
@@ -154,6 +172,7 @@ static inline void dma_direct_sync_single(struct device *dev,
struct dma_map_ops dma_direct_ops = {
.alloc = dma_direct_alloc_coherent,
.free = dma_direct_free_coherent,
+ .mmap = dma_direct_mmap_coherent,
.map_sg = dma_direct_map_sg,
.unmap_sg = dma_direct_unmap_sg,
.dma_supported = dma_direct_dma_supported,
@@ -211,20 +230,3 @@ static int __init dma_init(void)
}
fs_initcall(dma_init);
-int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
- void *cpu_addr, dma_addr_t handle, size_t size)
-{
- unsigned long pfn;
-
-#ifdef CONFIG_NOT_COHERENT_CACHE
- vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
- pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr);
-#else
- pfn = page_to_pfn(virt_to_page(cpu_addr));
-#endif
- return remap_pfn_range(vma, vma->vm_start,
- pfn + vma->vm_pgoff,
- vma->vm_end - vma->vm_start,
- vma->vm_page_prot);
-}
-EXPORT_SYMBOL_GPL(dma_mmap_coherent);
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index cb87301..dda3d9a 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -613,6 +613,7 @@ static u64 vio_dma_get_required_mask(struct device *dev)
struct dma_map_ops vio_dma_mapping_ops = {
.alloc = vio_dma_iommu_alloc_coherent,
.free = vio_dma_iommu_free_coherent,
+ .mmap = dma_direct_mmap_coherent,
.map_sg = vio_dma_iommu_map_sg,
.unmap_sg = vio_dma_iommu_unmap_sg,
.map_page = vio_dma_iommu_map_page,
diff --git a/drivers/base/dma-mapping.c b/drivers/base/dma-mapping.c
index 6f3676f..db5db02 100644
--- a/drivers/base/dma-mapping.c
+++ b/drivers/base/dma-mapping.c
@@ -10,6 +10,7 @@
#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <linux/gfp.h>
+#include <asm-generic/dma-coherent.h>
/*
* Managed DMA API
@@ -218,3 +219,33 @@ void dmam_release_declared_memory(struct device *dev)
EXPORT_SYMBOL(dmam_release_declared_memory);
#endif
+
+/*
+ * Create userspace mapping for the DMA-coherent memory.
+ */
+int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+ int ret = -ENXIO;
+#ifdef CONFIG_MMU
+ unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
+ unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
+ unsigned long pfn = page_to_pfn(virt_to_page(cpu_addr));
+ unsigned long off = vma->vm_pgoff;
+
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+ if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
+ return ret;
+
+ if (off < count && user_count <= (count - off)) {
+ ret = remap_pfn_range(vma, vma->vm_start,
+ pfn + off,
+ user_count << PAGE_SHIFT,
+ vma->vm_page_prot);
+ }
+#endif /* CONFIG_MMU */
+
+ return ret;
+}
+EXPORT_SYMBOL(dma_common_mmap);
diff --git a/include/asm-generic/dma-coherent.h b/include/asm-generic/dma-coherent.h
index abfb268..2be8a2d 100644
--- a/include/asm-generic/dma-coherent.h
+++ b/include/asm-generic/dma-coherent.h
@@ -29,6 +29,7 @@ dma_mark_declared_memory_occupied(struct device *dev,
#else
#define dma_alloc_from_coherent(dev, size, handle, ret) (0)
#define dma_release_from_coherent(dev, order, vaddr) (0)
+#define dma_mmap_from_coherent(dev, vma, vaddr, order, ret) (0)
#endif
#endif
diff --git a/include/asm-generic/dma-mapping-common.h b/include/asm-generic/dma-mapping-common.h
index 2e248d8..9073aeb 100644
--- a/include/asm-generic/dma-mapping-common.h
+++ b/include/asm-generic/dma-mapping-common.h
@@ -176,4 +176,41 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
#define dma_map_sg(d, s, n, r) dma_map_sg_attrs(d, s, n, r, NULL)
#define dma_unmap_sg(d, s, n, r) dma_unmap_sg_attrs(d, s, n, r, NULL)
+extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_addr, size_t size);
+
+/**
+ * dma_mmap_attrs - map a coherent DMA allocation into user space
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @vma: vm_area_struct describing requested user mapping
+ * @cpu_addr: kernel CPU-view address returned from dma_alloc_attrs
+ * @handle: device-view address returned from dma_alloc_attrs
+ * @size: size of memory originally requested in dma_alloc_attrs
+ * @attrs: attributes of mapping properties requested in dma_alloc_attrs
+ *
+ * Map a coherent DMA buffer previously allocated by dma_alloc_attrs
+ * into user space. The coherent DMA buffer must not be freed by the
+ * driver until the user space mapping has been released.
+ */
+static inline int
+dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr,
+ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs)
+{
+ struct dma_map_ops *ops = get_dma_ops(dev);
+ BUG_ON(!ops);
+ if (ops->mmap)
+ return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
+ return dma_common_mmap(dev, vma, cpu_addr, dma_addr, size);
+}
+
+#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL)
+
+static inline int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
+ void *cpu_addr, dma_addr_t dma_addr, size_t size)
+{
+ DEFINE_DMA_ATTRS(attrs);
+ dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
+ return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
+}
+
#endif
--
1.7.1.569.g6f426
^ permalink raw reply related
* [GIT PULL] Please pull a powerpc fix
From: Paul Mackerras @ 2012-06-15 7:51 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev
Linus,
The following changes since commit cfaf025112d3856637ff34a767ef785ef5cf2ca9:
Linux 3.5-rc2 (2012-06-08 18:40:09 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc.git tags/for-linus
for you to fetch changes up to f948501b36c6b3d9352ce212a197098a7e958971:
Make hard_irq_disable() actually hard-disable interrupts (2012-06-15 15:27:41 +1000)
----------------------------------------------------------------
PowerPC fix for Linus
Just one commit, and a one-liner at that, but an important one;
without it hard_irq_disable() does nothing on powerpc.
----------------------------------------------------------------
Paul Mackerras (1):
Make hard_irq_disable() actually hard-disable interrupts
arch/powerpc/include/asm/hw_irq.h | 3 +++
1 file changed, 3 insertions(+)
^ permalink raw reply
* [MPC5200] using GPT's for interrupts
From: Albrecht Dreß @ 2012-06-15 12:58 UTC (permalink / raw)
To: linuxppc-dev
Hi all,
I currently try to use a MPC5200B GPT as interrupt source, which according to the comment at the start of arch/powerpc/platforms/52xx/mpc52xx_gpt.c is possible if the "interrupt-controller" and "#interrupt-cells = < 1 >" properties are added to the device tree node.
Apparently, /some/ work is done during startup, as I can see in the boot log:
[ 0.438623] gpiochip_find_base: found new base at 251
[ 0.444202] mpc52xx-gpt f0000650.timer: mpc52xx_gpt_irq_setup() complete. virq=78
In my driver, I identify the GPT node, call irq_of_parse_and_map() to get the irq number (which succeeds, with the same number as above), but unfortunately request_irq() or devm_request_irq() for this irq fail with error -22. I tracked the failed call down to request_threaded_irq() which ejects because irq_settings_can_request(desc) returns false.
Before digging deeper into the code, maybe someone can tell me what I missed... I'm using kernel 3.2.16.
Thanks in advance,
Albrecht.
^ permalink raw reply
* [PATCH 1/7][TRIVIAL][resend] powerpc: cleanup kernel-doc warning
From: Wanpeng Li @ 2012-06-15 13:10 UTC (permalink / raw)
To: trivial
Cc: Christoph Lameter, Srikar Dronamraju, linux-pci, Jesse Barnes,
David Howells, Paul Gortmaker, H. Peter Anvin, Larry Woodman,
Andrea Arcangeli, Stephen Rothwell, Gavin Shan, x86, Hugh Dickins,
Ingo Molnar, KOSAKI Motohiro, Jan Kiszka, Nishanth Aravamudan,
Wanpeng Li, Peter Zijlstra, Mel Gorman, Jason Wessel, Al Viro,
Bjorn Helgaas, cgroups, Thomas Gleixner, KAMEZAWA Hiroyuki,
Michal Hocko, linux-mm, linux-kernel, Milton Miller, Minchan Kim,
Li Zefan, Johannes Weiner, Tejun Heo, David Rientjes,
Andrew Morton, linuxppc-dev
From: Wanpeng Li <liwp@linux.vnet.ibm.com>
Warning(arch/powerpc/kernel/pci_of_scan.c:210): Excess function parameter 'node' description in 'of_scan_pci_bridge'
Warning(arch/powerpc/kernel/vio.c:636): No description found for parameter 'desired'
Warning(arch/powerpc/kernel/vio.c:636): Excess function parameter 'new_desired' description in 'vio_cmo_set_dev_desired'
Warning(arch/powerpc/kernel/vio.c:1270): No description found for parameter 'viodrv'
Warning(arch/powerpc/kernel/vio.c:1270): Excess function parameter 'drv' description in '__vio_register_driver'
Warning(arch/powerpc/kernel/vio.c:1289): No description found for parameter 'viodrv'
Warning(arch/powerpc/kernel/vio.c:1289): Excess function parameter 'driver' description in 'vio_unregister_driver'
Signed-off-by: Wanpeng Li <liwp.linux@gmail.com>
---
arch/powerpc/kernel/pci_of_scan.c | 1 -
arch/powerpc/kernel/vio.c | 6 +++---
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index 89dde17..d7dd42b 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -198,7 +198,6 @@ EXPORT_SYMBOL(of_create_pci_dev);
/**
* of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
- * @node: device tree node of bridge
* @dev: pci_dev structure for the bridge
*
* of_scan_bus() calls this routine for each PCI bridge that it finds, and
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index cb87301..06cbc30 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -625,7 +625,7 @@ struct dma_map_ops vio_dma_mapping_ops = {
* vio_cmo_set_dev_desired - Set desired entitlement for a device
*
* @viodev: struct vio_dev for device to alter
- * @new_desired: new desired entitlement level in bytes
+ * @desired: new desired entitlement level in bytes
*
* For use by devices to request a change to their entitlement at runtime or
* through sysfs. The desired entitlement level is changed and a balancing
@@ -1262,7 +1262,7 @@ static int vio_bus_remove(struct device *dev)
/**
* vio_register_driver: - Register a new vio driver
- * @drv: The vio_driver structure to be registered.
+ * @viodrv: The vio_driver structure to be registered.
*/
int __vio_register_driver(struct vio_driver *viodrv, struct module *owner,
const char *mod_name)
@@ -1282,7 +1282,7 @@ EXPORT_SYMBOL(__vio_register_driver);
/**
* vio_unregister_driver - Remove registration of vio driver.
- * @driver: The vio_driver struct to be removed form registration
+ * @viodrv: The vio_driver struct to be removed form registration
*/
void vio_unregister_driver(struct vio_driver *viodrv)
{
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/7][TRIVIAL][resend] x86/kernel: cleanup some kernel-doc warnings
From: Wanpeng Li @ 2012-06-15 13:13 UTC (permalink / raw)
To: trivial
Cc: Christoph Lameter, Srikar Dronamraju, linux-pci, Jesse Barnes,
David Howells, Paul Gortmaker, H. Peter Anvin, Larry Woodman,
Andrea Arcangeli, Stephen Rothwell, Gavin Shan, x86, Hugh Dickins,
Ingo Molnar, KOSAKI Motohiro, Jan Kiszka, Nishanth Aravamudan,
Wanpeng Li, Peter Zijlstra, Mel Gorman, Jason Wessel, Al Viro,
Bjorn Helgaas, cgroups, Thomas Gleixner, KAMEZAWA Hiroyuki,
Michal Hocko, linux-mm, linux-kernel, Milton Miller, Minchan Kim,
Li Zefan, Johannes Weiner, Tejun Heo, David Rientjes,
Andrew Morton, linuxppc-dev
From: Wanpeng Li <liwp@linux.vnet.ibm.com>
Warning(arch/x86/kernel/kgdb.c:465): No description found for parameter 'e_vector'
Warning(arch/x86/kernel/kgdb.c:465): No description found for parameter 'remcomInBuffer'
Warning(arch/x86/kernel/kgdb.c:465): No description found for parameter 'remcomOutBuffer'
Warning(arch/x86/kernel/kgdb.c:465): No description found for parameter 'linux_regs'
Warning(arch/x86/kernel/kgdb.c:465): Excess function parameter 'vector' description in 'kgdb_arch_handle_exception'
Warning(arch/x86/kernel/kgdb.c:465): Excess function parameter 'remcom_in_buffer' description in 'kgdb_arch_handle_exception'
Warning(arch/x86/kernel/kgdb.c:465): Excess function parameter 'remcom_out_buffer' description in 'kgdb_arch_handle_exception'
Warning(arch/x86/kernel/kgdb.c:465): Excess function parameter 'regs' description in 'kgdb_arch_handle_exception'
Warning(arch/x86/kernel/uprobes.c:416): No description found for parameter 'auprobe'
Warning(arch/x86/kernel/uprobes.c:416): Excess function parameter 'arch_uprobe' description in 'arch_uprobe_analyze_insn'
Warning(arch/x86/lib/csum-wrappers_64.c:125): No description found for parameter 'sum'
Warning(arch/x86/lib/csum-wrappers_64.c:125): Excess function parameter 'isum' description in 'csum_partial_copy_nocheck'
Signed-off-by: Wanpeng Li <liwp.linux@gmail.com>
---
arch/x86/kernel/kgdb.c | 8 ++++----
arch/x86/kernel/uprobes.c | 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index 8bfb614..3f61904 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -444,12 +444,12 @@ void kgdb_roundup_cpus(unsigned long flags)
/**
* kgdb_arch_handle_exception - Handle architecture specific GDB packets.
- * @vector: The error vector of the exception that happened.
+ * @e_vector: The error vector of the exception that happened.
* @signo: The signal number of the exception that happened.
* @err_code: The error code of the exception that happened.
- * @remcom_in_buffer: The buffer of the packet we have read.
- * @remcom_out_buffer: The buffer of %BUFMAX bytes to write a packet into.
- * @regs: The &struct pt_regs of the current process.
+ * @remcomInBuffer: The buffer of the packet we have read.
+ * @remcomOutBuffer: The buffer of %BUFMAX bytes to write a packet into.
+ * @linux_regs: The &struct pt_regs of the current process.
*
* This function MUST handle the 'c' and 's' command packets,
* as well packets to set / remove a hardware breakpoint, if used.
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c
index dc4e910..f785a06 100644
--- a/arch/x86/kernel/uprobes.c
+++ b/arch/x86/kernel/uprobes.c
@@ -408,7 +408,7 @@ static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm,
/**
* arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
* @mm: the probed address space.
- * @arch_uprobe: the probepoint information.
+ * @auprobe: the probepoint information.
* Return 0 on success or a -ve number on error.
*/
int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/7][TRIVIAL][resend] drivers/pci: cleanup kernel-doc warning
From: Wanpeng Li @ 2012-06-15 13:15 UTC (permalink / raw)
To: trivial
Cc: Christoph Lameter, Srikar Dronamraju, linux-pci, Jesse Barnes,
David Howells, Paul Gortmaker, H. Peter Anvin, Larry Woodman,
Andrea Arcangeli, Stephen Rothwell, Gavin Shan, x86, Hugh Dickins,
Ingo Molnar, KOSAKI Motohiro, Jan Kiszka, Nishanth Aravamudan,
Wanpeng Li, Peter Zijlstra, Mel Gorman, Jason Wessel, Al Viro,
Bjorn Helgaas, cgroups, Thomas Gleixner, KAMEZAWA Hiroyuki,
Michal Hocko, linux-mm, linux-kernel, Milton Miller, Minchan Kim,
Li Zefan, Johannes Weiner, Tejun Heo, David Rientjes,
Andrew Morton, linuxppc-dev
From: Wanpeng Li <liwp@linux.vnet.ibm.com>
Warning(drivers/pci/setup-bus.c:277): No description found for parameter 'fail_head'
Warning(drivers/pci/setup-bus.c:277): Excess function parameter 'failed_list' description in 'assign_requested_resources_sorted'
Signed-off-by: Wanpeng Li <liwp.linux@gmail.com>
---
drivers/pci/setup-bus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 8fa2d4b..9165d25 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -265,7 +265,7 @@ out:
* assign_requested_resources_sorted() - satisfy resource requests
*
* @head : head of the list tracking requests for resources
- * @failed_list : head of the list tracking requests that could
+ * @fail_head : head of the list tracking requests that could
* not be allocated
*
* Satisfy resource requests of each element in the list. Add
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/7][TRIVIAL][resend] mm: cleanup on the comments of zone_reclaim_stat
From: Wanpeng Li @ 2012-06-15 13:17 UTC (permalink / raw)
To: trivial
Cc: Christoph Lameter, Srikar Dronamraju, linux-pci, Jesse Barnes,
David Howells, Paul Gortmaker, H. Peter Anvin, Larry Woodman,
Andrea Arcangeli, Stephen Rothwell, Gavin Shan, x86, Hugh Dickins,
Ingo Molnar, KOSAKI Motohiro, Jan Kiszka, Nishanth Aravamudan,
Wanpeng Li, Peter Zijlstra, Mel Gorman, Jason Wessel, Al Viro,
Bjorn Helgaas, cgroups, Thomas Gleixner, KAMEZAWA Hiroyuki,
Michal Hocko, linux-mm, linux-kernel, Milton Miller, Minchan Kim,
Li Zefan, Johannes Weiner, Tejun Heo, David Rientjes,
Andrew Morton, linuxppc-dev
From: Wanpeng Li <liwp@linux.vnet.ibm.com>
Signed-off-by: Wanpeng Li <liwp.linux@gmail.com>
Acked-by: Minchan Kim <minchan@kernel.org>
---
include/linux/mmzone.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 2427706..d6a5f83 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -188,7 +188,7 @@ static inline int is_unevictable_lru(enum lru_list lru)
struct zone_reclaim_stat {
/*
* The pageout code in vmscan.c keeps track of how many of the
- * mem/swap backed and file backed pages are refeferenced.
+ * mem/swap backed and file backed pages are referenced.
* The higher the rotated/scanned ratio, the more valuable
* that cache is.
*
--
1.7.9.5
^ permalink raw reply related
* [PATCH 5/7][TRIVIAL][resend] mm: cleanup kernel-doc warnings
From: Wanpeng Li @ 2012-06-15 13:18 UTC (permalink / raw)
To: trivial
Cc: Christoph Lameter, Srikar Dronamraju, linux-pci, Jesse Barnes,
David Howells, Paul Gortmaker, H. Peter Anvin, Larry Woodman,
Andrea Arcangeli, Stephen Rothwell, Gavin Shan, x86, Hugh Dickins,
Ingo Molnar, KOSAKI Motohiro, Jan Kiszka, Nishanth Aravamudan,
Wanpeng Li, Peter Zijlstra, Mel Gorman, Jason Wessel, Al Viro,
Bjorn Helgaas, cgroups, Thomas Gleixner, KAMEZAWA Hiroyuki,
Michal Hocko, linux-mm, linux-kernel, Milton Miller, Minchan Kim,
Li Zefan, Johannes Weiner, Tejun Heo, David Rientjes,
Andrew Morton, linuxppc-dev
From: Wanpeng Li <liwp@linux.vnet.ibm.com>
fix kernel-doc warnings just like this one:
Warning(../mm/page_cgroup.c:432): No description found for parameter 'id'
Warning(../mm/page_cgroup.c:432): Excess function parameter 'mem' description in 'swap_cgroup_record'
Signed-off-by: Wanpeng Li <liwp.linux@gmail.com>
---
mm/memblock.c | 12 ++++++------
mm/memcontrol.c | 4 ++--
mm/oom_kill.c | 2 +-
mm/page_cgroup.c | 4 ++--
mm/pagewalk.c | 1 -
mm/percpu-vm.c | 1 -
6 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/mm/memblock.c b/mm/memblock.c
index 952123e..b84f258 100644
--- a/mm/memblock.c
+++ b/mm/memblock.c
@@ -540,9 +540,9 @@ int __init_memblock memblock_reserve(phys_addr_t base, phys_addr_t size)
* __next_free_mem_range - next function for for_each_free_mem_range()
* @idx: pointer to u64 loop variable
* @nid: nid: node selector, %MAX_NUMNODES for all nodes
- * @p_start: ptr to phys_addr_t for start address of the range, can be %NULL
- * @p_end: ptr to phys_addr_t for end address of the range, can be %NULL
- * @p_nid: ptr to int for nid of the range, can be %NULL
+ * @out_start: ptr to phys_addr_t for start address of the range, can be %NULL
+ * @out_end: ptr to phys_addr_t for end address of the range, can be %NULL
+ * @out_nid: ptr to int for nid of the range, can be %NULL
*
* Find the first free area from *@idx which matches @nid, fill the out
* parameters, and update *@idx for the next iteration. The lower 32bit of
@@ -616,9 +616,9 @@ void __init_memblock __next_free_mem_range(u64 *idx, int nid,
* __next_free_mem_range_rev - next function for for_each_free_mem_range_reverse()
* @idx: pointer to u64 loop variable
* @nid: nid: node selector, %MAX_NUMNODES for all nodes
- * @p_start: ptr to phys_addr_t for start address of the range, can be %NULL
- * @p_end: ptr to phys_addr_t for end address of the range, can be %NULL
- * @p_nid: ptr to int for nid of the range, can be %NULL
+ * @out_start: ptr to phys_addr_t for start address of the range, can be %NULL
+ * @out_end: ptr to phys_addr_t for end address of the range, can be %NULL
+ * @out_nid: ptr to int for nid of the range, can be %NULL
*
* Reverse of __next_free_mem_range().
*/
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index ac35bcc..a9c3d01 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -1234,7 +1234,7 @@ int mem_cgroup_inactive_file_is_low(struct lruvec *lruvec)
/**
* mem_cgroup_margin - calculate chargeable space of a memory cgroup
- * @mem: the memory cgroup
+ * @memcg: the memory cgroup
*
* Returns the maximum amount of memory @mem can be charged with, in
* pages.
@@ -1508,7 +1508,7 @@ static unsigned long mem_cgroup_reclaim(struct mem_cgroup *memcg,
/**
* test_mem_cgroup_node_reclaimable
- * @mem: the target memcg
+ * @memcg: the target memcg
* @nid: the node ID to be checked.
* @noswap : specify true here if the user wants flle only information.
*
diff --git a/mm/oom_kill.c b/mm/oom_kill.c
index 416637f..c1956f1 100644
--- a/mm/oom_kill.c
+++ b/mm/oom_kill.c
@@ -366,7 +366,7 @@ static struct task_struct *select_bad_process(unsigned int *ppoints,
/**
* dump_tasks - dump current memory state of all system tasks
- * @mem: current's memory controller, if constrained
+ * @memcg: current's memory controller, if constrained
* @nodemask: nodemask passed to page allocator for mempolicy ooms
*
* Dumps the current memory state of all eligible tasks. Tasks not in the same
diff --git a/mm/page_cgroup.c b/mm/page_cgroup.c
index 1ccbd71..eb750f8 100644
--- a/mm/page_cgroup.c
+++ b/mm/page_cgroup.c
@@ -392,7 +392,7 @@ static struct swap_cgroup *lookup_swap_cgroup(swp_entry_t ent,
/**
* swap_cgroup_cmpxchg - cmpxchg mem_cgroup's id for this swp_entry.
- * @end: swap entry to be cmpxchged
+ * @ent: swap entry to be cmpxchged
* @old: old id
* @new: new id
*
@@ -422,7 +422,7 @@ unsigned short swap_cgroup_cmpxchg(swp_entry_t ent,
/**
* swap_cgroup_record - record mem_cgroup for this swp_entry.
* @ent: swap entry to be recorded into
- * @mem: mem_cgroup to be recorded
+ * @id: mem_cgroup to be recorded
*
* Returns old value at success, 0 at failure.
* (Of course, old value can be 0.)
diff --git a/mm/pagewalk.c b/mm/pagewalk.c
index aa9701e..6c118d0 100644
--- a/mm/pagewalk.c
+++ b/mm/pagewalk.c
@@ -162,7 +162,6 @@ static int walk_hugetlb_range(struct vm_area_struct *vma,
/**
* walk_page_range - walk a memory map's page tables with a callback
- * @mm: memory map to walk
* @addr: starting address
* @end: ending address
* @walk: set of callbacks to invoke for each level of the tree
diff --git a/mm/percpu-vm.c b/mm/percpu-vm.c
index 405d331..3707c71 100644
--- a/mm/percpu-vm.c
+++ b/mm/percpu-vm.c
@@ -360,7 +360,6 @@ err_free:
* @chunk: chunk to depopulate
* @off: offset to the area to depopulate
* @size: size of the area to depopulate in bytes
- * @flush: whether to flush cache and tlb or not
*
* For each cpu, depopulate and unmap pages [@page_start,@page_end)
* from @chunk. If @flush is true, vcache is flushed before unmapping
--
1.7.9.5
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