* Re: [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
From: Paul Mackerras @ 2012-07-23 3:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1343006528.29855.25.camel@pasglop>
On Mon, Jul 23, 2012 at 11:22:08AM +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2012-07-23 at 09:56 +1000, Paul Mackerras wrote:
> > > That indicate we should not mask the top 16 bits. So remove the
> > same.
> >
> > Older versions of the architecture (2.02 and earler) require the
> > masking, so we can't just unconditionally remove it, since that would
> > potentially break POWER5 and PPC970. People are definitely still
> > running Linux bare-metal on PPC970s (though arguably not on POWER5).
>
> Are you sure ? I couldn't convince myself ... the old architectures say
> that it only uses some of the bits but it doesn't mark the other ones as
> "reserved" (as in must be 0).
>
> (At least 1.x, I haven't looked at 2.x with x < 03)
2.01 and 2.02 say bits 0..15 must be zero.
Paul.
^ permalink raw reply
* [git pull] Please pull powerpc.git next branch
From: Benjamin Herrenschmidt @ 2012-07-23 4:46 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, Andrew Morton, Linux Kernel list
Hi Linus !
Here's the powerpc batch for 3.6 merge window. Notable highlights:
- iommu improvements from Anton removing the per-iommu global lock
in favor of dividing the DMA space into pools, each with its own lock,
and hashed on the CPU number. Along with making the locking more fine
grained, this gives significant improvements in multiqueue networking
scalability.
- Still from Anton, we know provide a vdso based variant of getcpu
which makes sched_getcpu with the appropriate glibc patch something
like 18 times faster.
- More anton goodness (he's been busy !) in other areas such as a
faster __clear_user and copy_page on P7, various perf fixes to improve
sampling quality, etc...
- One more step toward removing legacy i2c interfaces by using
new device-tree based probing of platform devices for the AOA audio
drivers
- A nice series of patches from Michael Neuling that helps avoiding
confusion between register numbers and litterals in assembly code,
trying to enforce the use of "%rN" register names in gas rather than
plain numbers.
- A pile of FSL updates
- The usual bunch of small fixes, cleanups etc...
You may spot a change to drivers/char/mem. The patch got no comment or
ack from outside, it's a trivial patch to allow the architecture to
skip creating /dev/port, which we use to disable it on ppc64 that don't
have a legacy brige. On those, IO ports 0...64K are not mapped in kernel
space at all, so accesses to /dev/port cause oopses (and yes, distros
-still- ship userspace that bangs hard coded ports such as kbdrate).
Cheers,
Ben.
The following changes since commit 50fb31cfed9218b439360caf7c0399b00042da15:
tty/hvc_opal: Fix debug function name (2012-07-10 19:16:25 +1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next
for you to fetch changes up to 574ce79cea9d3fda109ffcc82f81733de4740e5c:
powerpc/mpic: Create a revmap with enough entries for IPIs and timers (2012-07-23 14:20:42 +1000)
----------------------------------------------------------------
Andreas Schwab (1):
sound/aoa: Adapt to new i2c probing scheme
Anton Blanchard (24):
powerpc: Enable jump label support
powerpc: tracing: Avoid tracepoint duplication with DECLARE_EVENT_CLASS
powerpc: 64bit optimised __clear_user
powerpc: Use enhanced touch instructions in POWER7 copy_to_user/copy_from_user
powerpc: Clear RI and EE at the same time in system call exit
powerpc: Rename copyuser_power7_vmx.c to vmx-helper.c
powerpc: POWER7 optimised copy_page using VMX and enhanced prefetch
powerpc: Use enhanced touch instructions in POWER7 copy_to_user/copy_from_user
powerpc: POWER7 optimised memcpy using VMX and enhanced prefetch
powerpc/pseries: Disable interrupts around IOMMU percpu data accesses
powerpc/iommu: Reduce spinlock coverage in iommu_alloc and iommu_free
powerpc/iommu: Reduce spinlock coverage in iommu_free
powerpc/iommu: Push spinlock into iommu_range_alloc and __iommu_free
powerpc/iommu: Implement IOMMU pools to improve multiqueue adapter performance
powerpc: Optimise the 64bit optimised __clear_user
powerpc/perf: Create mmcra_sihv/mmcra_sipv helpers
powerpc/perf: Move code to select SIAR or pt_regs into perf_read_regs
powerpc/perf: Always use pt_regs for userspace samples
powerpc/perf: Use perf_instruction_pointer in callchains
powerpc/vio: Remove dma not supported warnings
powerpc/vio: Separate vio bus probe and device probe
powerpc: Call dma_debug_add_bus for PCI and VIO buses
powerpc: IOMMU fault injection
powerpc: Add VDSO version of getcpu
Benjamin Herrenschmidt (8):
Merge branch 'merge' into next
powerpc: Move and fix MTMSR_EERI definition
powerpc: Fixup oddity in entry_32.S
i2c/powermac: Improve detection of devices from device-tree
Merge remote-tracking branch 'kumar/next' into next
powerpc/iommu: Fix iommu pool initialization
Remove stale .rej file
powerpc/mpic: Create a revmap with enough entries for IPIs and timers
Bharat Bhushan (1):
powerpc: Fix assmption of end_of_DRAM() returns end address
Christian Herzig (1):
powerpc/83xx: fix RGMII AC values workaround for km83xx
Deepthi Dharwar (2):
powerpc/pseries/cpuidle: Replace pseries_notify_cpuidle_add call with notifier
powerpc/cpuidle: Fixes for pseries_idle hotplug notifier
Dong Aisheng (1):
of: Improve prom_update_property() function
Gavin Shan (2):
powerpc/numa: Fix OF node refcounting bug
powerpc/pci: cleanup on duplicate assignment
Gustavo Zacarias (1):
powerpc/p1010rdb: add EEPROMs to device tree
Haren Myneni (1):
powerpc: Disable /dev/port interface on systems without an ISA bridge
Holger Brunck (3):
powerpc/83xx: use for_each_node_by_name for km83xx.c
powerpc/83xx: update defconfig for kmeter1
powerpc/82xx: add SPI support for mgcoge
Jerry Huang (1):
powerpc/p1022ds: Add RTC support
Jia Hongtao (3):
powerpc/85xx: MPC8572DS - Fix eTSEC is not available on core1 of AMP boot
powerpc/85xx: MPC8572DS - Update the MSI interrupts into 4-cell format
powerpc/85xx: Add phy nodes in SGMII mode for MPC8536/44/72DS & P2020DS
Kim Phillips (1):
powerpc/fsl: Distribute interrupts on all CPUs by default
Kleber Sacilotto de Souza (1):
powerpc/eeh: Check handle_eeh_events() return value
Kokoris, Ioannis (1):
powerpc/qe: set IReady in QE Microcode Upload
Liu Yu (1):
powerpc/e500: make load_up_spe a normal fuction
Matias Garcia (1):
powerpc/fsl/pci: Fix when quirk_fsl_pcie_header is freed up
Michael Ellerman (2):
powerpc: Turn on BPF_JIT in ppc64_defconfig
powerpc: Add a symbol for hypervisor trampolines
Michael Neuling (18):
powerpc: Add defines for R0-R31
powerpc: Modify macro ready for %r0 register change
powerpc: Fix usage of register macros getting ready for %r0 change
powerpc: Convert to %r for all GPR usage
powerpc/pasemi: Move lbz/stbciz to ppc-opcode.h
powerpc: Merge STK_REG/PARAM/FRAMESIZE
powerpc: Merge VCPU_GPR
powerpc: Change mtcrf to use real register names
powerpc: Change LOAD_REG_ADDR to use real register names
powerpc: Fixes for instructions not using correct register naming
powerpc: Fix VSX macros so register names aren't wrapped
powerpc: Introduce new ___PPC_RA/B/S/T macros
powerpc: Start using ___PPC_RA/B/S/T where necessary
powerpc: Introduce new __REG_R macros
powerpc: Enforce usage of R0-R31 where possible
powerpc: Add defines for RA 0-R31
powerpc: Enforce usage of RA 0-R31 where possible
powerpc/pseries: Fix whitespace in eeh
Naveen N. Rao (1):
powerpc/hw_breakpoints: Fix incorrect pointer access
Nishanth Aravamudan (1):
powerpc/pseries/iommu: remove default window before attempting DDW manipulation
Paul Bolle (1):
powerpc: Kill flatdevtree_env.h too
Paul Gortmaker (1):
powerpc: remove Wind River SBC8560 support
Prabhakar Kushwaha (1):
powerpc/85xx: Add BSC9131 RDB Support
Scott Wood (4):
powerpc/mm: remove obsolete comment about page size name array
powerpc/fsl-pci: get PCI init out of board files
powerpc/mpc85xx_ds: convert to unified PCI init
powerpc/e500: add paravirt QEMU platform
Sebastian Andrzej Siewior (1):
Revert "powerpc/85xx: p2020rdb - move the NAND address."
Shaohui Xie (3):
powerpc/p2041rdb: add NAND node in device tree
powerpc/watchdog: replace CONFIG_FSL_BOOKE with CONFIG_PPC_FSL_BOOK3E
powerpc/watchdog: move booke watchdog param related code to setup-common.c
Shawn Guo (1):
powerpc: select PPC_CLOCK unconditionally for FSL_SOC
Shengzhou Liu (3):
powerpc/85xx: Enable MTD/NOR/NAND options by default in defconfig
powerpc/85xx: Update corenet32_smp_defconfig
powerpc/85xx: Update corenet64_smp_defconfig
Stephen Rothwell (1):
powerpc: Put the gpr save/restore functions in their own section
Steven Rostedt (3):
powerpc/ftrace: Have PPC skip updating with stop_machine()
powerpc: Have patch_instruction detect faults
powerpc/ftrace: Use patch_instruction instead of probe_kernel_write()
Stuart Yoder (1):
powerpc: Use CURRENT_THREAD_INFO instead of open coded assembly
Tang Yuantian (2):
powerpc/85xx: Add P1024rdb board support
powerpc/85xx: Add P1024rdb dts support
Tiejun Chen (1):
powerpc: Add "memory" attribute for mfmsr()
Timur Tabi (2):
powerpc/85xx: use the BRx registers to enable indirect mode on the P1022DS
Revert "powerpc/p3060qds: Add support for P3060QDS board"
Tony Breeds (1):
powerpc/boot: Only build board support files when required.
Varun Sethi (1):
powerpc/mpic: Use the MPIC_LARGE_VECTORS flag for FSL MPIC.
Wanpeng Li (1):
powerpc: Fix kernel-doc warning
Xu Jiucheng (1):
powerpc/85xx: Rename P1021RDB-PC device trees to be consistent
Yong Zhang (1):
powerpc/smp: remove call to ipi_call_lock()/ipi_call_unlock()
Zhicheng Fan (1):
powerpc/85xx: Add ucc uart support for p1025rdb
roger blofeld (1):
powerpc/ftrace: Fix assembly trampoline register usage
arch/powerpc/Kconfig | 2 +-
arch/powerpc/Kconfig.debug | 9 +
arch/powerpc/boot/Makefile | 57 +-
arch/powerpc/boot/dts/bsc9131rdb.dts | 34 +
arch/powerpc/boot/dts/bsc9131rdb.dtsi | 142 +++++
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 193 ++++++
.../fsl/{p3060si-pre.dtsi => bsc9131si-pre.dtsi} | 84 +--
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi | 16 +-
arch/powerpc/boot/dts/fsl/p3060si-post.dtsi | 302 ---------
arch/powerpc/boot/dts/mgcoge.dts | 23 +
arch/powerpc/boot/dts/mpc8536ds.dtsi | 8 +
arch/powerpc/boot/dts/mpc8544ds.dtsi | 9 +
arch/powerpc/boot/dts/mpc8572ds.dtsi | 17 +
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts | 8 +-
arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts | 11 +-
arch/powerpc/boot/dts/p1010rdb.dtsi | 12 +
.../boot/dts/{p1021rdb.dtsi => p1021rdb-pc.dtsi} | 2 +-
.../boot/dts/{p1021rdb.dts => p1021rdb-pc_32b.dts} | 4 +-
.../dts/{p1021rdb_36b.dts => p1021rdb-pc_36b.dts} | 4 +-
arch/powerpc/boot/dts/p1022ds.dtsi | 20 +-
arch/powerpc/boot/dts/p1024rdb.dtsi | 228 +++++++
arch/powerpc/boot/dts/p1024rdb_32b.dts | 87 +++
arch/powerpc/boot/dts/p1024rdb_36b.dts | 87 +++
arch/powerpc/boot/dts/p1025rdb.dtsi | 40 ++
arch/powerpc/boot/dts/p2020ds.dtsi | 10 +
arch/powerpc/boot/dts/p2020rdb.dts | 2 +-
arch/powerpc/boot/dts/p2041rdb.dts | 41 +-
arch/powerpc/boot/dts/p3060qds.dts | 242 --------
arch/powerpc/boot/dts/sbc8560.dts | 406 ------------
arch/powerpc/boot/flatdevtree_env.h | 27 -
arch/powerpc/configs/83xx/kmeter1_defconfig | 22 +-
arch/powerpc/configs/85xx/sbc8560_defconfig | 65 --
arch/powerpc/configs/corenet32_smp_defconfig | 10 +-
arch/powerpc/configs/corenet64_smp_defconfig | 66 +-
arch/powerpc/configs/mgcoge_defconfig | 12 +-
arch/powerpc/configs/mpc85xx_defconfig | 24 +
arch/powerpc/configs/mpc85xx_smp_defconfig | 25 +
arch/powerpc/configs/ppc64_defconfig | 2 +
arch/powerpc/configs/pseries_defconfig | 1 +
arch/powerpc/include/asm/asm-compat.h | 2 +-
arch/powerpc/include/asm/code-patching.h | 4 +-
arch/powerpc/include/asm/device.h | 3 +
arch/powerpc/include/asm/exception-64s.h | 4 +-
arch/powerpc/include/asm/immap_qe.h | 4 +-
arch/powerpc/include/asm/io.h | 8 +
arch/powerpc/include/asm/iommu.h | 18 +-
arch/powerpc/include/asm/kvm_book3s_asm.h | 1 +
arch/powerpc/include/asm/mmu.h | 7 +-
arch/powerpc/include/asm/perf_event.h | 5 +
arch/powerpc/include/asm/ppc-opcode.h | 118 +++-
arch/powerpc/include/asm/ppc_asm.h | 121 ++--
arch/powerpc/include/asm/processor.h | 2 -
arch/powerpc/include/asm/qe.h | 1 +
arch/powerpc/include/asm/reg.h | 8 +-
arch/powerpc/include/asm/thread_info.h | 6 +
arch/powerpc/include/asm/trace.h | 45 +-
arch/powerpc/include/asm/vdso.h | 2 +
arch/powerpc/include/asm/vio.h | 2 +
arch/powerpc/kernel/asm-offsets.c | 1 +
arch/powerpc/kernel/cpu_setup_a2.S | 6 +-
arch/powerpc/kernel/dma.c | 10 +-
arch/powerpc/kernel/entry_32.S | 30 +-
arch/powerpc/kernel/entry_64.S | 37 +-
arch/powerpc/kernel/exceptions-64e.S | 10 +-
arch/powerpc/kernel/exceptions-64s.S | 3 +-
arch/powerpc/kernel/fpu.S | 16 +-
arch/powerpc/kernel/ftrace.c | 81 ++-
arch/powerpc/kernel/head_fsl_booke.S | 25 +-
arch/powerpc/kernel/hw_breakpoint.c | 2 +-
arch/powerpc/kernel/idle_6xx.S | 4 +-
arch/powerpc/kernel/idle_book3e.S | 2 +-
arch/powerpc/kernel/idle_e500.S | 4 +-
arch/powerpc/kernel/idle_power4.S | 2 +-
arch/powerpc/kernel/iommu.c | 291 +++++++--
arch/powerpc/kernel/kvm.c | 2 +-
arch/powerpc/kernel/misc_32.S | 4 +-
arch/powerpc/kernel/misc_64.S | 9 +-
arch/powerpc/kernel/pci-common.c | 1 -
arch/powerpc/kernel/pci_of_scan.c | 1 -
arch/powerpc/kernel/setup-common.c | 27 +
arch/powerpc/kernel/setup_32.c | 24 -
arch/powerpc/kernel/smp.c | 5 +-
arch/powerpc/kernel/vdso.c | 28 +
arch/powerpc/kernel/vdso32/Makefile | 4 +-
arch/powerpc/kernel/vdso32/getcpu.S | 45 ++
arch/powerpc/kernel/vdso32/vdso32.lds.S | 3 +
arch/powerpc/kernel/vdso64/Makefile | 2 +-
arch/powerpc/kernel/vdso64/getcpu.S | 45 ++
arch/powerpc/kernel/vdso64/vdso64.lds.S | 1 +
arch/powerpc/kernel/vio.c | 42 +-
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 227 +++----
arch/powerpc/kvm/book3s_interrupts.S | 80 ++-
arch/powerpc/kvm/book3s_rmhandlers.S | 1 -
arch/powerpc/kvm/book3s_segment.S | 2 -
arch/powerpc/kvm/booke_interrupts.S | 277 +++++----
arch/powerpc/kvm/bookehv_interrupts.S | 229 ++++---
arch/powerpc/lib/Makefile | 5 +-
arch/powerpc/lib/checksum_64.S | 27 +-
arch/powerpc/lib/code-patching.c | 14 +-
arch/powerpc/lib/copypage_64.S | 4 +
arch/powerpc/lib/copypage_power7.S | 165 +++++
arch/powerpc/lib/copyuser_power7.S | 157 +++--
arch/powerpc/lib/crtsavres.S | 5 +-
arch/powerpc/lib/hweight_64.S | 14 +-
arch/powerpc/lib/ldstfp.S | 12 +-
arch/powerpc/lib/memcpy_64.S | 4 +
arch/powerpc/lib/memcpy_power7.S | 647 ++++++++++++++++++++
arch/powerpc/lib/string.S | 2 +
arch/powerpc/lib/string_64.S | 202 ++++++
.../lib/{copyuser_power7_vmx.c => vmx-helper.c} | 27 +-
arch/powerpc/mm/hash_low_32.S | 8 +-
arch/powerpc/mm/hash_low_64.S | 156 +++--
arch/powerpc/mm/numa.c | 2 +
arch/powerpc/mm/tlb_low_64e.S | 10 +-
arch/powerpc/mm/tlb_nohash_low.S | 16 +-
arch/powerpc/net/bpf_jit.h | 106 ++--
arch/powerpc/net/bpf_jit_comp.c | 4 +-
arch/powerpc/perf/callchain.c | 6 +-
arch/powerpc/perf/core-book3s.c | 99 ++-
arch/powerpc/platforms/44x/currituck.c | 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 5 +
arch/powerpc/platforms/83xx/km83xx.c | 100 ++-
arch/powerpc/platforms/85xx/Kconfig | 43 +-
arch/powerpc/platforms/85xx/Makefile | 4 +-
arch/powerpc/platforms/85xx/bsc913x_rdb.c | 67 ++
arch/powerpc/platforms/85xx/corenet_ds.c | 2 +-
arch/powerpc/platforms/85xx/ge_imp3a.c | 2 +-
arch/powerpc/platforms/85xx/mpc8536_ds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 97 +--
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 22 +
arch/powerpc/platforms/85xx/p1022_ds.c | 116 +++-
arch/powerpc/platforms/85xx/p3060_qds.c | 77 ---
arch/powerpc/platforms/85xx/qemu_e500.c | 72 +++
arch/powerpc/platforms/85xx/sbc8560.c | 254 --------
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 2 +-
arch/powerpc/platforms/Kconfig.cputype | 4 +
arch/powerpc/platforms/cell/beat_hvCall.S | 28 +-
arch/powerpc/platforms/cell/iommu.c | 1 -
arch/powerpc/platforms/powernv/opal-takeover.S | 10 +-
arch/powerpc/platforms/pseries/eeh_event.c | 6 +-
arch/powerpc/platforms/pseries/eeh_pseries.c | 4 +-
arch/powerpc/platforms/pseries/hvCall.S | 78 ++-
arch/powerpc/platforms/pseries/iommu.c | 113 +++-
arch/powerpc/platforms/pseries/mobility.c | 8 +-
arch/powerpc/platforms/pseries/processor_idle.c | 36 +-
arch/powerpc/platforms/pseries/reconfig.c | 16 +-
arch/powerpc/platforms/pseries/smp.c | 1 -
arch/powerpc/sysdev/6xx-suspend.S | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 73 ++-
arch/powerpc/sysdev/fsl_pci.h | 8 +
arch/powerpc/sysdev/mpic.c | 4 +-
arch/powerpc/sysdev/qe_lib/qe.c | 3 +
drivers/char/mem.c | 11 +-
drivers/i2c/busses/i2c-powermac.c | 157 ++++-
drivers/of/base.c | 15 +-
drivers/watchdog/Kconfig | 8 +-
drivers/watchdog/booke_wdt.c | 4 +-
fs/proc/proc_devtree.c | 5 +
include/linux/io.h | 9 +
include/linux/of.h | 3 +-
sound/aoa/codecs/onyx.c | 75 +--
sound/aoa/codecs/tas.c | 80 +--
163 files changed, 4611 insertions(+), 3010 deletions(-)
create mode 100644 arch/powerpc/boot/dts/bsc9131rdb.dts
create mode 100644 arch/powerpc/boot/dts/bsc9131rdb.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
rename arch/powerpc/boot/dts/fsl/{p3060si-pre.dtsi => bsc9131si-pre.dtsi} (56%)
delete mode 100644 arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
rename arch/powerpc/boot/dts/{p1021rdb.dtsi => p1021rdb-pc.dtsi} (99%)
rename arch/powerpc/boot/dts/{p1021rdb.dts => p1021rdb-pc_32b.dts} (97%)
rename arch/powerpc/boot/dts/{p1021rdb_36b.dts => p1021rdb-pc_36b.dts} (97%)
create mode 100644 arch/powerpc/boot/dts/p1024rdb.dtsi
create mode 100644 arch/powerpc/boot/dts/p1024rdb_32b.dts
create mode 100644 arch/powerpc/boot/dts/p1024rdb_36b.dts
delete mode 100644 arch/powerpc/boot/dts/p3060qds.dts
delete mode 100644 arch/powerpc/boot/dts/sbc8560.dts
delete mode 100644 arch/powerpc/boot/flatdevtree_env.h
delete mode 100644 arch/powerpc/configs/85xx/sbc8560_defconfig
create mode 100644 arch/powerpc/kernel/vdso32/getcpu.S
create mode 100644 arch/powerpc/kernel/vdso64/getcpu.S
create mode 100644 arch/powerpc/lib/copypage_power7.S
create mode 100644 arch/powerpc/lib/memcpy_power7.S
create mode 100644 arch/powerpc/lib/string_64.S
rename arch/powerpc/lib/{copyuser_power7_vmx.c => vmx-helper.c} (79%)
create mode 100644 arch/powerpc/platforms/85xx/bsc913x_rdb.c
delete mode 100644 arch/powerpc/platforms/85xx/p3060_qds.c
create mode 100644 arch/powerpc/platforms/85xx/qemu_e500.c
delete mode 100644 arch/powerpc/platforms/85xx/sbc8560.c
^ permalink raw reply
* Re: [PATCH -V3 02/11] arch/powerpc: Simplify hpte_decode
From: Aneesh Kumar K.V @ 2012-07-23 5:41 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120722232635.GB17790@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:32PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> This patch simplify hpte_decode for easy switching of virtual address to
>> virtual page number in the later patch
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> I'm not convinced your version is simpler than what was there before.
> It's certainly longer now. But it does seem to do the same calculation
> as before, so:
This actually make patch 3 "arch/powerpc: Convert virtual address to vpn"
simpler. The hpte_decode hunk is a one line change after this
>
> Reviewed-by: Paul Mackerras <paulus@samba.org>
-aneesh
^ permalink raw reply
* Re: [PATCH -V3 03/11] arch/powerpc: Convert virtual address to vpn
From: Aneesh Kumar K.V @ 2012-07-23 5:54 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120722234203.GC17790@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:33PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> This patch convert different functions to take virtual page number
>> instead of virtual address. Virtual page number is virtual address
>> shifted right by VPN_SHIFT (12) bits. This enable us to have an
>> address range of upto 76 bits.
>
> Some comments inline below...
>
>> +/*
>> + * encode page number shift.
>> + * Inorder to fit the 78 bit va in a 64 bit variable we shift the va by
> ^ "in order"
>
>> + * 12 bits. This enable us to address upto 76 bit va.
> ^ "up to"
>
>> + * For hpt hash from a va we can ignore the page size bits of va and for
>> + * hpte encoding we ignore upto 23 bits of va. So ignoring lower 12 bits ensure
>> + * we work in all cases including 4k page size.
>> + */
>> +#define VPN_SHIFT 12
>
> This can't be more than 12 bits because we sometimes use 4k pages even
> in a kernel configured for 64k pages (e.g. with the subpage_protection
> system call).
Yes, I wanted to make that explicit, ie this is not a virtual page
number and hence all these BUG_ON. I actually updated few of them
to BUILD_BUG_ON() based of earlier review.
>
>> +static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
>> + int ssize)
>> +{
>> + unsigned long v;
>> + /*
>> + * The AVA field omits the low-order 23 bits of the 78 bits VA.
>> + * These bits are not needed in the PTE, because the
>> + * low-order b of these bits are part of the byte offset
>> + * into the virtual page and, if b < 23, the high-order
>> + * 23-b of these bits are always used in selecting the
>> + * PTEGs to be searched
>> + */
>> + BUG_ON(VPN_SHIFT > 23);
>
> I don't think we need this. If VPN_SHIFT was computed by some complex
> expression whose value is not obvious, then BUG_ON (or BUILD_BUG_ON)
> would be appropriate, but since it's just a #define, a comment at the
> site of the definition will suffice.
>
>> static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
>> int ssize)
>> {
>> + int mask;
>> unsigned long hash, vsid;
>>
>> + BUG_ON(shift < VPN_SHIFT);
>
> So VPN_SHIFT can be at most 12, since 12 is the smallest shift value
> possible here.
>
>> -static inline void __tlbiel(unsigned long va, int psize, int ssize)
>> +static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
>> {
>> + unsigned long va;
>> unsigned int penc;
>>
>> + BUG_ON((77 - 65) > VPN_SHIFT);
>> + va = vpn << VPN_SHIFT;
>
> So VPN_SHIFT has to be at least 12. What is the significance of 77
> and 65 here?
>
It is the other way around . I updated that in 77guccfav.fsf@skywalker.in.ibm.com
BUILD_BUG_ON(VPN_SHIFT > (77 - 65));
tlbiel says we can only ignore bits above 65 of va. hence the math of 77- 65.
-aneesh
^ permalink raw reply
* Re: [PATCH] powerpc/mm: add ZONE_NORMAL zone for 64 bit kernel
From: Benjamin Herrenschmidt @ 2012-07-23 6:06 UTC (permalink / raw)
To: Shaohui Xie; +Cc: Mingkai Hu, linuxppc-dev, Chen Yuanquan
In-Reply-To: <1342786906-12634-1-git-send-email-Shaohui.Xie@freescale.com>
On Fri, 2012-07-20 at 20:21 +0800, Shaohui Xie wrote:
> PowerPC platform only supports ZONE_DMA zone for 64bit kernel, so all the
> memory will be put into this zone. If the memory size is greater than
> the device's DMA capability and device uses dma_alloc_coherent to allocate
> memory, it will get an address which is over the device's DMA addressing,
> the device will fail.
>
> So we split the memory to two zones by adding a zone ZONE_NORMAL, since
> we already allocate PCICSRBAR/PEXCSRBAR right below the 4G boundary (if the
> lowest PCI address is above 4G), so we constrain the DMA zone ZONE_DMA
> to 2GB, also, we clear the flag __GFP_DMA and set it only if the device's
> dma_mask < total memory size. By doing this, devices which cannot DMA all
> the memory will be limited to ZONE_DMA, but devices which can DMA all the
> memory will not be affected by this limitation.
This is wrong. Don't you have an iommu do deal with those devices
anyway ? What about swiotlb ?
If you *really* need to honor 32 (or 31 even) bit DMAs, what you -may-
want to do is create a ZONE_DMA32 like other architectures, do not
hijack the historical ZONE_DMA.
But even then, I'm dubious this is really needed.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH -V3 04/11] arch/powerpc: Rename va to vpn
From: Aneesh Kumar K.V @ 2012-07-23 6:14 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120722234623.GD17790@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:34PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> Rename the variable to better reflect the values. No functional change
>> in this patch.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> I think you missed a couple: kernel_map_linear_page and
> kernel_unmap_linear_page are now broken since you change va to vpn in
> the declaration but not in the uses, and you change host_va to
> host_vpn in struct hpte_cache but don't fix up the use in
> kvmppc_mmu_invalidate_pte.
Will fix.
> How many configs did you compile-test this
> with?
Not much. I will try to do a test build of multiple configs.
Thanks
-aneesh
^ permalink raw reply
* [PATCH] powerpc: Enable pseries hardware RNG and crypto modules
From: Anton Blanchard @ 2012-07-23 6:26 UTC (permalink / raw)
To: benh, paulus, linuxppc-dev
Enable the hardware RNG and crypto modules. I verified they both
autoload via the VIO subsystem, so there is no need to build them in.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: b/arch/powerpc/configs/ppc64_defconfig
===================================================================
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -278,7 +278,8 @@ CONFIG_HVC_RTAS=y
CONFIG_HVC_BEAT=y
CONFIG_HVCS=m
CONFIG_IBM_BSR=m
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_PSERIES=m
CONFIG_RAW_DRIVER=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_AMD8111=y
@@ -484,7 +485,8 @@ CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_LZO=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_NX=m
CONFIG_VIRTUALIZATION=y
CONFIG_KVM_BOOK3S_64=m
CONFIG_KVM_BOOK3S_64_HV=y
Index: b/arch/powerpc/configs/pseries_defconfig
===================================================================
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -225,7 +225,8 @@ CONFIG_HVC_CONSOLE=y
CONFIG_HVC_RTAS=y
CONFIG_HVCS=m
CONFIG_IBM_BSR=m
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_PSERIES=m
CONFIG_GEN_RTC=y
CONFIG_RAW_DRIVER=y
CONFIG_MAX_RAW_DEVS=1024
@@ -366,7 +367,8 @@ CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_LZO=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_NX=m
CONFIG_VIRTUALIZATION=y
CONFIG_KVM_BOOK3S_64=m
CONFIG_KVM_BOOK3S_64_HV=y
^ permalink raw reply
* More irqdomain problems (Was: next/mmotm unbootable on G5: irqdomain)
From: Benjamin Herrenschmidt @ 2012-07-23 6:32 UTC (permalink / raw)
To: Grant Likely
Cc: Stephen Rothwell, Hugh Dickins, linux-kernel, Milton Miller,
ul Mundt, Rob Herring, Andrew Morton, linuxppc-dev,
Thomas Gleixner
In-Reply-To: <1343011543.2957.2.camel@pasglop>
Allright, another one Grant:
unsigned int irq_find_mapping(struct irq_domain *domain,
irq_hw_number_t hwirq)
{
struct irq_data *data;
/* Look for default domain if nececssary */
if (domain == NULL)
domain = irq_default_domain;
if (domain == NULL)
return 0;
switch (domain->revmap_type) {
case IRQ_DOMAIN_MAP_LEGACY:
return irq_domain_legacy_revmap(domain, hwirq);
case IRQ_DOMAIN_MAP_LINEAR:
return irq_linear_revmap(domain, hwirq);
case IRQ_DOMAIN_MAP_TREE:
rcu_read_lock();
data = radix_tree_lookup(&domain->revmap_data.tree, hwirq);
rcu_read_unlock();
if (data)
return data->irq;
- break;
+ return 0;
case IRQ_DOMAIN_MAP_NOMAP:
Please, stick a proper commit message and my s-o-b and see if you can fix
your tree before you ask Linus to pull because that's not pretty on any
pseries .... irq_find_mapping() does get called for all interrupt the
first time it's mapped to check if there's a pre-existing mapping, so
the case of the thing being unpopulated is absolutely legit.
the NOMAP case has a similar dubious exit case but since I'm not that
familiar with NOMAP I haven't touched it.
Cheers,
Ben.
^ permalink raw reply
* [PATCH] powerpc: Lack of firmware flash support is not an error
From: Anton Blanchard @ 2012-07-23 6:42 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
Reduce the severity of the warning given when firmware flash is
not supported. Not all platforms have it.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Index: b/arch/powerpc/kernel/rtas_flash.c
===================================================================
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -709,7 +709,7 @@ static int __init rtas_flash_init(void)
if (rtas_token("ibm,update-flash-64-and-reboot") ==
RTAS_UNKNOWN_SERVICE) {
- printk(KERN_ERR "rtas_flash: no firmware flash support\n");
+ pr_info("rtas_flash: no firmware flash support\n");
return 1;
}
^ permalink raw reply
* Re: [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
From: Aneesh Kumar K.V @ 2012-07-23 6:44 UTC (permalink / raw)
To: Paul Mackerras, Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20120723034912.GA5019@drongo>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 23, 2012 at 11:22:08AM +1000, Benjamin Herrenschmidt wrote:
>> On Mon, 2012-07-23 at 09:56 +1000, Paul Mackerras wrote:
>> > > That indicate we should not mask the top 16 bits. So remove the
>> > same.
>> >
>> > Older versions of the architecture (2.02 and earler) require the
>> > masking, so we can't just unconditionally remove it, since that would
>> > potentially break POWER5 and PPC970. People are definitely still
>> > running Linux bare-metal on PPC970s (though arguably not on POWER5).
>>
>> Are you sure ? I couldn't convince myself ... the old architectures say
>> that it only uses some of the bits but it doesn't mark the other ones as
>> "reserved" (as in must be 0).
>>
>> (At least 1.x, I haven't looked at 2.x with x < 03)
>
> 2.01 and 2.02 say bits 0..15 must be zero.
is this 0..15 of va or 0..15 of AVA ?
if it is 0.. 15 then that clear bit is wrong right ? We are doing that
on a 64 bit va. So with that we already have ignored 0..14.
-aneesh
^ permalink raw reply
* Re: [PATCH -V3 05/11] arch/powerpc: remove masking top 16 bit of va in tlb invalidate
From: Benjamin Herrenschmidt @ 2012-07-23 6:48 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, Paul Mackerras
In-Reply-To: <87d33nht7x.fsf@skywalker.in.ibm.com>
On Mon, 2012-07-23 at 12:14 +0530, Aneesh Kumar K.V wrote:
>
> if it is 0.. 15 then that clear bit is wrong right ? We are doing that
> on a 64 bit va. So with that we already have ignored 0..14.
It's bit 0..15 of RB passed to tlbie
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Update g5_defconfig
From: Andreas Schwab @ 2012-07-23 7:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1343011712.2957.5.camel__22210.4697292254$1343011753$gmane$org@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> This updates the g5 defconfig to include nouveau instead of nvidiafb
> (which works much better nowadays, in fact the latter crashes on modern
> distros),
Does it? Nvidiafb is super stable here, whereas nouveau has a lot of
problems.
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* Re: [PATCH] powerpc: Update g5_defconfig
From: Benjamin Herrenschmidt @ 2012-07-23 7:06 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev
In-Reply-To: <m2fw8jyn43.fsf@igel.home>
On Mon, 2012-07-23 at 09:04 +0200, Andreas Schwab wrote:
> Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
>
> > This updates the g5 defconfig to include nouveau instead of nvidiafb
> > (which works much better nowadays, in fact the latter crashes on modern
> > distros),
>
> Does it? Nvidiafb is super stable here, whereas nouveau has a lot of
> problems.
nvidiafb crashes solid here when X gets involved.
What do you mean by "lots of problems" ? I've been using nouveau for a
long time now on my two quad g5's including 3D, gnome-shell etc...
without anything more than a glitch or two on the edge of windows...
Also can you remind me what machine model and what video card variant ?
Cheers,
Ben.
^ permalink raw reply
* [PATCH 1/2] edac: Use ccsr_pci structure instead of hardcoded define
From: Chunhe Lan @ 2012-07-23 7:13 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Chunhe Lan
There are some differences of register offset and definition between
pci and pcie error management registers. While, some other pci/pcie
error management registers are nearly the same.
To merge pci and pcie edac code into one, it is easier to use ccsr_pci
structure than the hardcoded define. So remove the hardcoded define and
add pci/pcie error management register in ccsr_pci structure.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
---
arch/powerpc/sysdev/fsl_pci.h | 46 +++++++++++++++++++++++++++++++++-------
drivers/edac/mpc85xx_edac.h | 13 +---------
2 files changed, 40 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5c..5378a47 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -1,7 +1,7 @@
/*
* MPC85xx/86xx PCI Express structure define
*
- * Copyright 2007,2011 Freescale Semiconductor, Inc
+ * Copyright 2007,2011,2012 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -14,6 +14,8 @@
#ifndef __POWERPC_FSL_PCI_H
#define __POWERPC_FSL_PCI_H
+#include <asm/pci-bridge.h>
+
#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
#define PCIE_LTSSM_L0 0x16 /* L0 state */
#define PIWAR_EN 0x80000000 /* Enable */
@@ -74,13 +76,41 @@ struct ccsr_pci {
*/
struct pci_inbound_window_regs piw[4];
- __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
- u8 res21[4];
- __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
- u8 res22[4];
- __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
- u8 res23[12];
- __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
+/* Merge PCI Express/PCI error management registers */
+ __be32 pex_err_dr; /* 0x.e00
+ * - PCI/PCIE error detect register
+ */
+ __be32 pex_err_cap_dr; /* 0x.e04
+ * - PCI error capture disabled register
+ * - PCIE has no this register
+ */
+ __be32 pex_err_en; /* 0x.e08
+ * - PCI/PCIE error interrupt enable register
+ */
+ __be32 pex_err_attrib; /* 0x.e0c
+ * - PCI error attributes capture register
+ * - PCIE has no this register
+ */
+ __be32 pex_err_disr; /* 0x.e10
+ * - PCI error address capture register
+ * - PCIE error disable register
+ */
+ __be32 pex_err_ext_addr; /* 0x.e14
+ * - PCI error extended addr capture register
+ * - PCIE has no this register
+ */
+ __be32 pex_err_dl; /* 0x.e18
+ * - PCI error data low capture register
+ * - PCIE has no this register
+ */
+ __be32 pex_err_dh; /* 0x.e1c
+ * - PCI error data high capture register
+ * - PCIE has no this register
+ */
+ __be32 pex_err_cap_stat; /* 0x.e20
+ * - PCI gasket timer register
+ * - PCIE error capture status register
+ */
u8 res24[4];
__be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
__be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h
index 932016f..8ba4152 100644
--- a/drivers/edac/mpc85xx_edac.h
+++ b/drivers/edac/mpc85xx_edac.h
@@ -1,5 +1,7 @@
/*
* Freescale MPC85xx Memory Controller kenel module
+ * Copyright (c) 2012 Freescale Semiconductor, Inc.
+ *
* Author: Dave Jiang <djiang@mvista.com>
*
* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
@@ -131,17 +133,6 @@
#define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
PCI_EDE_ADDR_PERR)
-#define MPC85XX_PCI_ERR_DR 0x0000
-#define MPC85XX_PCI_ERR_CAP_DR 0x0004
-#define MPC85XX_PCI_ERR_EN 0x0008
-#define MPC85XX_PCI_ERR_ATTRIB 0x000c
-#define MPC85XX_PCI_ERR_ADDR 0x0010
-#define MPC85XX_PCI_ERR_EXT_ADDR 0x0014
-#define MPC85XX_PCI_ERR_DL 0x0018
-#define MPC85XX_PCI_ERR_DH 0x001c
-#define MPC85XX_PCI_GAS_TIMR 0x0020
-#define MPC85XX_PCI_PCIX_TIMR 0x0024
-
struct mpc85xx_mc_pdata {
char *name;
int edac_idx;
--
1.5.6.5
^ permalink raw reply related
* [PATCH 2/2] edac/85xx: PCI/PCIe error interrupt edac support
From: Chunhe Lan @ 2012-07-23 7:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Chunhe Lan
Adding pcie error interrupt edac support for mpc85xx and p4080.
mpc85xx uses the legacy interrupt report mechanism - the error
interrupts are reported directly to mpic. While, p4080 attaches
the most of error interrupts to interrupt 0. And report error
interrupts to mpic via interrupt 0. This patch can handle both
of them.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
---
drivers/edac/mpc85xx_edac.c | 236 +++++++++++++++++++++++++++++++++----------
drivers/edac/mpc85xx_edac.h | 9 ++-
2 files changed, 191 insertions(+), 54 deletions(-)
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index 73464a6..35eef79 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -1,5 +1,6 @@
/*
* Freescale MPC85xx Memory Controller kenel module
+ * Copyright (c) 2012 Freescale Semiconductor, Inc.
*
* Author: Dave Jiang <djiang@mvista.com>
*
@@ -21,6 +22,7 @@
#include <linux/of_platform.h>
#include <linux/of_device.h>
+#include <sysdev/fsl_pci.h>
#include "edac_module.h"
#include "edac_core.h"
#include "mpc85xx_edac.h"
@@ -37,11 +39,6 @@ static u32 orig_ddr_err_sbe;
/*
* PCI Err defines
*/
-#ifdef CONFIG_PCI
-static u32 orig_pci_err_cap_dr;
-static u32 orig_pci_err_en;
-#endif
-
static u32 orig_l2_err_disable;
#ifdef CONFIG_FSL_SOC_BOOKE
static u32 orig_hid1[2];
@@ -151,37 +148,52 @@ static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
{
struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
u32 err_detect;
+ struct ccsr_pci *reg = pdata->pci_reg;
+
+ err_detect = in_be32(&pdata->pci_reg->pex_err_dr);
+
+ if (pdata->pcie_flag) {
+ printk(KERN_ERR "PCIE error(s) detected\n");
+ printk(KERN_ERR "PCIE ERR_DR register: 0x%08x\n", err_detect);
+ printk(KERN_ERR "PCIE ERR_CAP_STAT register: 0x%08x\n",
+ in_be32(®->pex_err_cap_stat));
+ printk(KERN_ERR "PCIE ERR_CAP_R0 register: 0x%08x\n",
+ in_be32(®->pex_err_cap_r0));
+ printk(KERN_ERR "PCIE ERR_CAP_R1 register: 0x%08x\n",
+ in_be32(®->pex_err_cap_r1));
+ printk(KERN_ERR "PCIE ERR_CAP_R2 register: 0x%08x\n",
+ in_be32(®->pex_err_cap_r2));
+ printk(KERN_ERR "PCIE ERR_CAP_R3 register: 0x%08x\n",
+ in_be32(®->pex_err_cap_r3));
+ } else {
+ /* master aborts can happen during PCI config cycles */
+ if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
+ out_be32(®->pex_err_dr, err_detect);
+ return;
+ }
- err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
-
- /* master aborts can happen during PCI config cycles */
- if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
- return;
+ printk(KERN_ERR "PCI error(s) detected\n");
+ printk(KERN_ERR "PCI/X ERR_DR register: 0x%08x\n", err_detect);
+ printk(KERN_ERR "PCI/X ERR_ATTRIB register: 0x%08x\n",
+ in_be32(®->pex_err_attrib));
+ printk(KERN_ERR "PCI/X ERR_ADDR register: 0x%08x\n",
+ in_be32(®->pex_err_disr));
+ printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: 0x%08x\n",
+ in_be32(®->pex_err_ext_addr));
+ printk(KERN_ERR "PCI/X ERR_DL register: 0x%08x\n",
+ in_be32(®->pex_err_dl));
+ printk(KERN_ERR "PCI/X ERR_DH register: 0x%08x\n",
+ in_be32(®->pex_err_dh));
+
+ if (err_detect & PCI_EDE_PERR_MASK)
+ edac_pci_handle_pe(pci, pci->ctl_name);
+
+ if (err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_PERR_MASK))
+ edac_pci_handle_npe(pci, pci->ctl_name);
}
- printk(KERN_ERR "PCI error(s) detected\n");
- printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
-
- printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
- printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
- printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
- printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
- printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
-
/* clear error bits */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
-
- if (err_detect & PCI_EDE_PERR_MASK)
- edac_pci_handle_pe(pci, pci->ctl_name);
-
- if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
- edac_pci_handle_npe(pci, pci->ctl_name);
+ out_be32(®->pex_err_dr, err_detect);
}
static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
@@ -190,7 +202,7 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
u32 err_detect;
- err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
+ err_detect = in_be32(&pdata->pci_reg->pex_err_dr);
if (!err_detect)
return IRQ_NONE;
@@ -200,11 +212,104 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
+/*
+ * This function is for error interrupt ORed mechanism.
+ * This mechanism attaches most functions' error interrupts to interrupt 0.
+ * And report error interrupt to mpic via interrupt 0.
+ * EIMR0 - Error Interrupt Mask Register 0.
+ *
+ * This function check whether the device support error interrupt ORed
+ * mechanism via device tree. If supported, umask pcie error interrupt
+ * bit in EIMR0.
+ */
+static int mpc85xx_err_int_en(struct platform_device *op)
+{
+ u32 *int_cell;
+ struct device_node *np;
+ void __iomem *mpic_base;
+ u32 reg_tmp;
+ u32 int_len;
+ struct resource r;
+ int res;
+
+ if (!op->dev.of_node)
+ return -EINVAL;
+
+ /*
+ * Unmask pcie error interrupt bit in EIMR0.
+ * Extend interrupt specifier has 4 cells.
+ * For the 3rd cell:
+ * 0 -- normal interrupt;
+ * 1 -- error interrupt.
+ */
+ int_cell = (u32 *)of_get_property(op->dev.of_node, "interrupts",
+ &int_len);
+ if ((int_len/sizeof(u32)) == 4) {
+ /* soc has error interrupt integration handling mechanism */
+ if (*(int_cell + 2) == 1) {
+ np = of_find_node_by_type(NULL, "open-pic");
+
+ if (of_address_to_resource(np, 0, &r)) {
+ printk(KERN_ERR "%s: Failed to map mpic regs\n",
+ __func__);
+ of_node_put(np);
+ res = -ENOMEM;
+ goto err;
+ }
+
+ if (!request_mem_region(r.start, r.end - r.start + 1,
+ "mpic")) {
+ printk(KERN_ERR
+ "%s: Error when requesting mem region\n",
+ __func__);
+ res = -EBUSY;
+ goto err;
+ }
+
+ mpic_base = ioremap(r.start, r.end - r.start + 1);
+ if (!mpic_base) {
+ printk(KERN_ERR "%s: Unable to map mpic regs\n",
+ __func__);
+ res = -ENOMEM;
+ goto err_ioremap;
+ }
+
+ reg_tmp = in_be32(mpic_base + MPC85XX_MPIC_EIMR0);
+ out_be32(mpic_base + MPC85XX_MPIC_EIMR0,
+ reg_tmp & ~(1 << (31 - *(int_cell + 3))));
+ iounmap(mpic_base);
+ release_mem_region(r.start, r.end - r.start + 1);
+ of_node_put(np);
+ }
+ }
+
+ return 0;
+
+err_ioremap:
+ release_mem_region(r.start, r.end - r.start + 1);
+err:
+ return res;
+}
+
+static int mpc85xx_pcie_find_capability(struct device_node *np)
+{
+ struct pci_controller *hose;
+
+ if (!np)
+ return -EINVAL;
+
+ hose = pci_find_hose_for_OF_device(np);
+
+ return early_find_capability(hose, hose->bus->number, 0,
+ PCI_CAP_ID_EXP);
+}
+
static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
{
struct edac_pci_ctl_info *pci;
struct mpc85xx_pci_pdata *pdata;
struct resource r;
+ struct ccsr_pci *reg;
int res = 0;
if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
@@ -223,6 +328,9 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
pci->ctl_name = pdata->name;
pci->dev_name = dev_name(&op->dev);
+ if (mpc85xx_pcie_find_capability(op->dev.of_node) > 0)
+ pdata->pcie_flag = 1;
+
if (edac_op_state == EDAC_OPSTATE_POLL)
pci->edac_check = mpc85xx_pci_check;
@@ -234,10 +342,6 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
"PCI err regs\n", __func__);
goto err;
}
-
- /* we only need the error registers */
- r.start += 0xe00;
-
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
pdata->name)) {
printk(KERN_ERR "%s: Error while requesting mem region\n",
@@ -246,26 +350,32 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
goto err;
}
- pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
- if (!pdata->pci_vbase) {
+ pdata->pci_reg = devm_ioremap(&op->dev, r.start, resource_size(&r));
+ if (!pdata->pci_reg) {
printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
res = -ENOMEM;
goto err;
}
- orig_pci_err_cap_dr =
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
-
- /* PCI master abort is expected during config cycles */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
+ if (mpc85xx_err_int_en(op) < 0)
+ goto err;
- orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
+ reg = pdata->pci_reg;
+ /* disable pci/pcie error detect */
+ if (pdata->pcie_flag) {
+ pdata->orig_pci_err_dr = in_be32(®->pex_err_disr);
+ out_be32(®->pex_err_disr, ~0);
+ } else {
+ pdata->orig_pci_err_dr = in_be32(®->pex_err_cap_dr);
+ out_be32(®->pex_err_cap_dr, ~0);
+ }
- /* disable master abort reporting */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
+ /* disable all pcie error interrupt */
+ pdata->orig_pci_err_en = in_be32(®->pex_err_en);
+ out_be32(®->pex_err_en, 0);
- /* clear error bits */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
+ /* clear all error bits */
+ out_be32(®->pex_err_dr, ~0);
if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
debugf3("%s(): failed edac_pci_add_device()\n", __func__);
@@ -275,7 +385,7 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
if (edac_op_state == EDAC_OPSTATE_INT) {
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
res = devm_request_irq(&op->dev, pdata->irq,
- mpc85xx_pci_isr, IRQF_DISABLED,
+ mpc85xx_pci_isr, IRQF_SHARED,
"[EDAC] PCI err", pci);
if (res < 0) {
printk(KERN_ERR
@@ -290,6 +400,17 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
pdata->irq);
}
+ if (pdata->pcie_flag) {
+ /* enable all pcie error interrupt & error detect */
+ out_be32(®->pex_err_en, ~0);
+ out_be32(®->pex_err_disr, 0);
+ } else {
+ /* PCI master abort is expected during config cycles */
+ out_be32(®->pex_err_cap_dr, PCI_ERR_CAP_DR_DIS_MST);
+ /* disable master abort reporting */
+ out_be32(®->pex_err_en, PCI_ERR_EN_DIS_MST);
+ }
+
devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
debugf3("%s(): success\n", __func__);
printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
@@ -311,10 +432,13 @@ static int mpc85xx_pci_err_remove(struct platform_device *op)
debugf0("%s()\n", __func__);
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
- orig_pci_err_cap_dr);
+ if (pdata->pcie_flag)
+ out_be32(&pdata->pci_reg->pex_err_disr, pdata->orig_pci_err_dr);
+ else
+ out_be32(&pdata->pci_reg->pex_err_cap_dr,
+ pdata->orig_pci_err_dr);
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
+ out_be32(&pdata->pci_reg->pex_err_en, pdata->orig_pci_err_en);
edac_pci_del_device(pci->dev);
@@ -333,6 +457,12 @@ static struct of_device_id mpc85xx_pci_err_of_match[] = {
{
.compatible = "fsl,mpc8540-pci",
},
+ {
+ .compatible = "fsl,mpc8548-pcie",
+ },
+ {
+ .compatible = "fsl,p4080-pcie",
+ },
{},
};
MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h
index 8ba4152..262004d 100644
--- a/drivers/edac/mpc85xx_edac.h
+++ b/drivers/edac/mpc85xx_edac.h
@@ -133,6 +133,10 @@
#define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
PCI_EDE_ADDR_PERR)
+#define PCI_ERR_CAP_DR_DIS_MST 0x40
+#define PCI_ERR_EN_DIS_MST (~PCI_ERR_CAP_DR_DIS_MST)
+#define MPC85XX_MPIC_EIMR0 0x3910
+
struct mpc85xx_mc_pdata {
char *name;
int edac_idx;
@@ -149,8 +153,11 @@ struct mpc85xx_l2_pdata {
struct mpc85xx_pci_pdata {
char *name;
+ u8 pcie_flag;
int edac_idx;
- void __iomem *pci_vbase;
+ struct ccsr_pci *pci_reg;
+ u32 orig_pci_err_dr;
+ u32 orig_pci_err_en;
int irq;
};
--
1.5.6.5
^ permalink raw reply related
* Re: [PATCH -V3 07/11] arch/powerpc: Increase the slice range to 64TB
From: Aneesh Kumar K.V @ 2012-07-23 7:13 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120723000048.GG17790@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:37PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> This patch makes the high psizes mask as an unsigned char array
>> so that we can have more than 16TB. Currently we support upto
>> 64TB
>
> Some comments inline...
>
>> @@ -804,16 +804,19 @@ unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
>> #ifdef CONFIG_PPC_MM_SLICES
>> unsigned int get_paca_psize(unsigned long addr)
>> {
>> - unsigned long index, slices;
>> + u64 lpsizes;
>> + unsigned char *hpsizes;
>> + unsigned long index, mask_index;
>>
>> if (addr < SLICE_LOW_TOP) {
>> - slices = get_paca()->context.low_slices_psize;
>> + lpsizes = get_paca()->context.low_slices_psize;
>> index = GET_LOW_SLICE_INDEX(addr);
>> - } else {
>> - slices = get_paca()->context.high_slices_psize;
>> - index = GET_HIGH_SLICE_INDEX(addr);
>> + return (lpsizes >> (index * 4)) & 0xF;
>> }
>> - return (slices >> (index * 4)) & 0xF;
>> + hpsizes = get_paca()->context.high_slices_psize;
>> + index = GET_HIGH_SLICE_INDEX(addr) >> 1;
>> + mask_index = GET_HIGH_SLICE_INDEX(addr) - (index << 1);
>> + return (hpsizes[index] >> (mask_index * 4)) & 0xF;
>
> The last 3 lines here feel awkward. How about:
>
index = GET_HIGH_SLICE_INDEX(addr);
mask_index = index & 1;
return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
That is much simpler. I updated the patch, changing to the above format in
all the location.
>
>> static struct slice_mask slice_mask_for_size(struct mm_struct *mm, int psize)
>> {
>> + unsigned char *hpsizes;
>> + int index, mask_index;
>> struct slice_mask ret = { 0, 0 };
>> unsigned long i;
>> - u64 psizes;
>> + u64 lpsizes;
>>
>> - psizes = mm->context.low_slices_psize;
>> + lpsizes = mm->context.low_slices_psize;
>> for (i = 0; i < SLICE_NUM_LOW; i++)
>> - if (((psizes >> (i * 4)) & 0xf) == psize)
>> + if (((lpsizes >> (i * 4)) & 0xf) == psize)
>> ret.low_slices |= 1u << i;
>>
>> - psizes = mm->context.high_slices_psize;
>> - for (i = 0; i < SLICE_NUM_HIGH; i++)
>> - if (((psizes >> (i * 4)) & 0xf) == psize)
>> + hpsizes = mm->context.high_slices_psize;
>> + for (i = 0; i < SLICE_NUM_HIGH; i++) {
>> + index = i >> 1;
>> + mask_index = i - (index << 1);
>
> Again, seems like a complicated way to do mask_index = i & 1 (or
> even i % 2, if you prefer, but then make i an unsigned type).
>
> Paul.
-aneesh
^ permalink raw reply
* Re: next/mmotm unbootable on G5: irqdomain
From: Hugh Dickins @ 2012-07-23 7:24 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Stephen Rothwell, linux-kernel, Milton Miller, Paul Mundt,
Rob Herring, Andrew Morton, linuxppc-dev, Thomas Gleixner
In-Reply-To: <1343011543.2957.2.camel@pasglop>
On Mon, 23 Jul 2012, Benjamin Herrenschmidt wrote:
> On Sat, 2012-07-21 at 19:47 -0700, Hugh Dickins wrote:
> > I have to revert the patch below from mmotm 2012-07-20-16-30 or
> > next-20120720 in order to boot on the PowerPC G5: otherwise it
> > freezes before switching to the framebuffer console - but I'm
> > not certain where because that initial console doesn't scroll
> > (there are mpic messages at bottom and at top of screen, probably
> > later messages at the top but I don't know the sequence).
>
> This fixes it
Confirmed: many thanks, Ben.
> (Grant, how do we avoid bisection breakage here ? I can
> put that in -powerpc and we can make sure that gets merged before your
> tree ?)
>
> powerpc/mpic: Create a revmap with enough entries for IPIs and timers
>
> The current mpic code creates a linear revmap just big enough for all
> the sources, which happens to miss the IPIs and timers on some machines.
>
> This will in turn break when the irqdomain code loses the fallback of
> doing a linear search when the revmap fails (and really slows down IPIs
> otherwise).
>
> This happens for example on the U4 based Apple machines such as the
> dual core PowerMac G5s.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
> index 906f29c..bfc6211 100644
> --- a/arch/powerpc/sysdev/mpic.c
> +++ b/arch/powerpc/sysdev/mpic.c
> @@ -1376,7 +1376,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
> mpic->isu_mask = (1 << mpic->isu_shift) - 1;
>
> mpic->irqhost = irq_domain_add_linear(mpic->node,
> - last_irq + 1,
> + intvec_top,
> &mpic_host_ops, mpic);
>
> /*
>
>
>
^ permalink raw reply
* Re: [PATCH] powerpc: Update g5_defconfig
From: Andreas Schwab @ 2012-07-23 7:27 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1343027168.2957.30.camel@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> What do you mean by "lots of problems" ?
For example, only half of the screen is drawn. There is a bug open
about this, but no comments.
> Also can you remind me what machine model and what video card variant ?
PowerMac7,3 with NV34 [GeForce FX 5200 Ultra] (rev a1).
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* Re: [PATCH -V3 08/11] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit
From: Aneesh Kumar K.V @ 2012-07-23 7:29 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120723002019.GJ17790@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:38PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> slice array size and slice mask size depend on PGTABLE_RANGE. We
>> can't directly include pgtable.h in these header because there is
>> a circular dependency. So add compile time check for these values.
>
> Some comments below...
>
>> struct slice_mask {
>> u16 low_slices;
>> /*
>> - * This should be derived out of PGTABLE_RANGE. For the current
>> - * max 64TB, u64 should be ok.
>> + * We do this as a union so that we can verify
>> + * SLICE_MASK_SIZE against PGTABLE_RANGE
>> */
>> - u64 high_slices;
>> + union {
>> + u64 high_slices;
>> + unsigned char not_used[SLICE_MASK_SIZE];
>> + };
>
> Seems ugly to have to have a union just for that. Can't we do
> something like BUILD_BUG_ON(sizeof(u64) < SLICE_MASK_SIZE) instead?
Dropped the union from the patch
>
>> @@ -73,7 +73,7 @@ static struct slice_mask slice_range_to_mask(unsigned long start,
>> unsigned long len)
>> {
>> unsigned long end = start + len - 1;
>> - struct slice_mask ret = { 0, 0 };
>> + struct slice_mask ret = { 0, {0} };
>
> Wouldn't { 0 } suffice? Similarly in several places below.
Once i drop the union all these changes can be dropped.
-aneesh
^ permalink raw reply
* Re: [PATCH] powerpc: Update g5_defconfig
From: Benjamin Herrenschmidt @ 2012-07-23 7:39 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev, Ben Skeggs
In-Reply-To: <m2boj7ym24.fsf@igel.home>
On Mon, 2012-07-23 at 09:27 +0200, Andreas Schwab wrote:
> Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
>
> > What do you mean by "lots of problems" ?
>
> For example, only half of the screen is drawn. There is a bug open
> about this, but no comments.
>
> > Also can you remind me what machine model and what video card variant ?
>
> PowerMac7,3 with NV34 [GeForce FX 5200 Ultra] (rev a1).
Ah ok, I haven't seen these problems.
Ben, any idea ? I was trying to make nouveau the default instead of
nvidiafb on G5's but it seems like some old G5's with those NV34 aren't
happy.
BTW. Are we trying to use AGP on these things ? If yes, I would suggest
we just blacklist AGP on all powermac unless specifically requested via
a kernel command line arg. That would be half of the problems solved...
I have access to an iMac G5 with an old 5200 variant as well which I
could dig out & try if there's anything I can do to help debug that.
(On my G5s it's all PCIe so that problem doesn't happen).
Cheers,
Ben.
^ permalink raw reply
* Re: next/mmotm unbootable on G5: irqdomain
From: Grant Likely @ 2012-07-23 7:59 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Stephen Rothwell, Hugh Dickins, linux-kernel, Milton Miller,
Paul Mundt, Rob Herring, Andrew Morton, linuxppc-dev,
Thomas Gleixner
In-Reply-To: <1343011543.2957.2.camel@pasglop>
On Sun, Jul 22, 2012 at 8:45 PM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Sat, 2012-07-21 at 19:47 -0700, Hugh Dickins wrote:
>> I have to revert the patch below from mmotm 2012-07-20-16-30 or
>> next-20120720 in order to boot on the PowerPC G5: otherwise it
>> freezes before switching to the framebuffer console - but I'm
>> not certain where because that initial console doesn't scroll
>> (there are mpic messages at bottom and at top of screen, probably
>> later messages at the top but I don't know the sequence).
>
> This fixes it (Grant, how do we avoid bisection breakage here ? I can
> put that in -powerpc and we can make sure that gets merged before your
> tree ?)
My tree must be rebased to eliminate bisect breakage. The existing
commits in my tree have the breakage, and fiddling with the merge
order doesn't affect that. I don't want to rebase though. The safest
approach (smallest window of breakage) is to apply that fix onto my
irqdomain tree.
g.
>
> powerpc/mpic: Create a revmap with enough entries for IPIs and timers
>
> The current mpic code creates a linear revmap just big enough for all
> the sources, which happens to miss the IPIs and timers on some machines.
>
> This will in turn break when the irqdomain code loses the fallback of
> doing a linear search when the revmap fails (and really slows down IPIs
> otherwise).
>
> This happens for example on the U4 based Apple machines such as the
> dual core PowerMac G5s.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
> index 906f29c..bfc6211 100644
> --- a/arch/powerpc/sysdev/mpic.c
> +++ b/arch/powerpc/sysdev/mpic.c
> @@ -1376,7 +1376,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
> mpic->isu_mask = (1 << mpic->isu_shift) - 1;
>
> mpic->irqhost = irq_domain_add_linear(mpic->node,
> - last_irq + 1,
> + intvec_top,
> &mpic_host_ops, mpic);
>
> /*
>
>
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH -V3 09/11] arch/powerpc: Use 50 bits of VSID in slbmte
From: Aneesh Kumar K.V @ 2012-07-23 8:21 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120723000658.GH17790@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:39PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> Increase the number of valid VSID bits in slbmte instruction.
>> We will use the new bits when we increase valid VSID bits.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> arch/powerpc/mm/slb_low.S | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
>> index c355af6..c1fc81c 100644
>> --- a/arch/powerpc/mm/slb_low.S
>> +++ b/arch/powerpc/mm/slb_low.S
>> @@ -226,7 +226,7 @@ _GLOBAL(slb_allocate_user)
>> */
>> slb_finish_load:
>> ASM_VSID_SCRAMBLE(r10,r9,256M)
>> - rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
>> + rldimi r11,r10,SLB_VSID_SHIFT,2 /* combine VSID and flags */
>
> You can't do that without either changing ASM_VSID_SCRAMBLE or masking
> the VSID it generates to 36 bits, since the logic in ASM_VSID_SCRAMBLE
> can leave non-zero bits in the high 28 bits of the result. Similarly
> for the 1T case.
>
How about change ASM_VSID_SCRAMBLE to clear the high bits ? That would
also make it close to vsid_scramble()
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index d24d484..173bb34 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -420,7 +420,8 @@ extern void slb_set_size(u16 size);
* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
addi rx,rt,1; \
srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
- add rt,rt,rx
+ add rt,rt,rx; \
+ clrldi rt,rt,(64 - VSID_BITS_##size);
/* 4 bits per slice and we have one slice per 1TB */
#if 0 /* We can't directly include pgtable.h hence this hack */
^ permalink raw reply related
* Re: [PATCH -V3 10/11] arch/powerpc: Use 32bit array for slb cache
From: Aneesh Kumar K.V @ 2012-07-23 8:25 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120723002738.GK17790@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:40PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> With larger vsid we need to track more bits of ESID in slb cache
>> for slb invalidate.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> Minor comment below, but apart from that...
>
> Reviewed-by: Paul Mackerras <paulus@samba.org>
>
>> - sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
>> - rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
>> - add r11,r11,r13 /* r11 = (u16 *)paca + offset */
>> - sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
>> + sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
>> + rldicl r10,r10,36,28 /* get the 36 bits of the ESID */
>
> You're correct that the rldicl instruction produces 36 bits of result,
> and in fact it is equivalent to srdi r10,r10,28. If you're changing
> the line you might as well change the instruction to the simpler form
> too.
done.
-aneesh
^ permalink raw reply
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
From: Aneesh Kumar K.V @ 2012-07-23 8:49 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120723001539.GI17790@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> Increase max addressable range to 64TB. This is not tested on
>> real hardware yet.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> arch/powerpc/include/asm/mmu-hash64.h | 8 ++++----
>> arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +-
>> arch/powerpc/include/asm/pgtable-ppc64-64k.h | 2 +-
>> arch/powerpc/include/asm/processor.h | 4 ++--
>> arch/powerpc/include/asm/sparsemem.h | 4 ++--
>> 5 files changed, 10 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
>> index aa0d560..a227ba7 100644
>> --- a/arch/powerpc/include/asm/mmu-hash64.h
>> +++ b/arch/powerpc/include/asm/mmu-hash64.h
>> @@ -374,16 +374,16 @@ extern void slb_set_size(u16 size);
>> */
>>
>> #define VSID_MULTIPLIER_256M ASM_CONST(200730139) /* 28-bit prime */
>> -#define VSID_BITS_256M 36
>> +#define VSID_BITS_256M 38
>> #define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
>
> With these settings, the multiplication in ASM_VSID_SCRAMBLE could
> overflow, leading to incorrect results (which would cause occasional
> corruption of user processes under heavy load). You will need to
> reduce the multiplier to be less than 2^26, and it will need to be
> co-prime with 2^38 - 1. (Probably, the same value as we use in the 1T
> case would be OK.)
I ended up using the same value as VSID_MULTIPLIER_1T.
(gdb) p/d 1ull << 38
$1 = 274877906944
(gdb) p/d 274877906943/12538073
$2 = 21923
(gdb) p/d 12538073ll*21923
$5 = 274872174379
^ permalink raw reply
* Re: [RFC PATCH 0/8] memory-hotplug : hot-remove physical memory(clear page table)
From: Wen Congyang @ 2012-07-23 9:11 UTC (permalink / raw)
To: Yasuaki Ishimatsu
Cc: len.brown, linux-acpi, linux-kernel, linux-mm, paulus,
minchan.kim, kosaki.motohiro, rientjes, cl, linuxppc-dev, akpm,
liuj97
In-Reply-To: <5009094B.3090506@jp.fujitsu.com>
At 07/20/2012 03:31 PM, Yasuaki Ishimatsu Wrote:
> [Hi Wen,
>
> Good news!! I was waiting for this patch to come.
> Applying the patches, can we hot-remove physical memory completely?
If all functions success, I guess so.
Thanks
Wen Congyang
>
> Thanks,
> Yasuaki Ishimatsu
>
> 2012/07/20 16:06, Wen Congyang wrote:
>> This patch series aims to support physical memory hot-remove(clear
>> page table).
>>
>> This patch series base on ishimatsu's patch series. You can get it here:
>> http://www.spinics.net/lists/linux-acpi/msg36804.html
>>
>> The patches can remove following things:
>> - page table of removed memory
>>
>> If you find lack of function for physical memory hot-remove, please
>> let me
>> know.
>>
>> Note:
>> * The patch "remove memory info from list before freeing it" is being
>> disccussed
>> in other thread. But for testing the patch series, the patch is
>> needed.
>> So I added the patch as [PATCH 0/8].
>> * You need to apply ishimatsu's patch series first before applying
>> this patch
>> series.
>>
>> Wen Congyang (8):
>> memory-hotplug: store the node id in acpi_memory_device
>> memory-hotplug: offline memory only when it is onlined
>> memory-hotplug: call remove_memory() to cleanup when removing memory
>> device
>> memory-hotplug: export the function acpi_bus_remove()
>> memory-hotplug: call acpi_bus_remove() to remove memory device
>> memory-hotplug: introduce new function arch_remove_memory()
>> x86: make __split_large_page() generally avialable
>> memory-hotplug: implement arch_remove_memory()
>>
>> arch/ia64/mm/init.c | 16 ++++
>> arch/powerpc/mm/mem.c | 14 +++
>> arch/s390/mm/init.c | 8 ++
>> arch/sh/mm/init.c | 15 +++
>> arch/tile/mm/init.c | 8 ++
>> arch/x86/include/asm/pgtable_types.h | 1 +
>> arch/x86/mm/init_32.c | 10 ++
>> arch/x86/mm/init_64.c | 160
>> ++++++++++++++++++++++++++++++++++
>> arch/x86/mm/pageattr.c | 47 +++++-----
>> drivers/acpi/acpi_memhotplug.c | 24 ++++--
>> drivers/acpi/scan.c | 3 +-
>> include/acpi/acpi_bus.h | 1 +
>> include/linux/memory_hotplug.h | 1 +
>> mm/memory_hotplug.c | 2 +-
>> 14 files changed, 280 insertions(+), 30 deletions(-)
>>
>
>
>
^ permalink raw reply
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