* Re: next/mmotm unbootable on G5: irqdomain
From: Grant Likely @ 2012-07-24 4:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Stephen Rothwell, Hugh Dickins, linux-kernel, Milton Miller,
Paul Mundt, Rob Herring, Andrew Morton, linuxppc-dev,
Thomas Gleixner
In-Reply-To: <1343100106.3715.2.camel@pasglop>
On Mon, Jul 23, 2012 at 9:21 PM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> On Mon, 2012-07-23 at 16:32 -0600, Grant Likely wrote:
>> > As-is I'm backing off from the linear/legacy/tree merge patch as just
>> > too risky. I've already pulled that stuff out of linux-next.
>>
>> Can I pull you pseries fix into my tree (my preference), or do I need
>> to rebase on top of yours?
>
> The mpic fix for the g5 is in Linus tree already, I added it on top of
> powerpc -next before I asked Linus to pull.
>
> For pseries (ie the fix for irq_find_mapping vs. radix), I don't have a
> formal patch, just the one I hand typed in my previous email, so do
> whatever you want with it.
Okay, I'll merge in Linus' tree at the appropriate point to protect
against bisection, and I'll fix up the appropriate patch that touches
irq_find_mapping.
g.
^ permalink raw reply
* Re: [PATCH] powerpc/mm: add ZONE_NORMAL zone for 64 bit kernel
From: Benjamin Herrenschmidt @ 2012-07-24 4:45 UTC (permalink / raw)
To: Tabi Timur-B04825
Cc: Wood Scott-B07421, Hu Mingkai-B21284,
linuxppc-dev@lists.ozlabs.org, Xie Shaohui-B21989,
Chen Yuanquan-B41889
In-Reply-To: <500E1EB3.6060203@freescale.com>
On Tue, 2012-07-24 at 04:04 +0000, Tabi Timur-B04825 wrote:
> Benjamin Herrenschmidt wrote:
> > Sure but I don't want to create the zones in the first place (and thus
> > introduce the added pressure on the memory management) on machines that
> > don't need it.
>
> One thing that does confuse me -- by default, we don't create a
> ZONE_NORMAL. We only create a ZONE_DMA. Why is that? Shouldn't it be
> the other way around?
Because ZONE_NORMAL allocations can be serviced from the ZONE_DMA while
the other way isn't possible.
Especially in the old days, there were quite a few cases of drivers
and/or subsystems who were a bit heavy handed at using ZONE_DMA, so not
having one would essentially make them not work at all.
Cheers,
Ben.
^ permalink raw reply
* hvc_console: Better kernel console support
From: Benjamin Herrenschmidt @ 2012-07-24 7:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Linux Kernel list
hvc_console has two methods to instanciate the consoles.
hvc_instanciate is meant to be called at early boot, while hvc_alloc is
called for more dynamically probed objects.
Currently, it only deals with adding kernel consoles in the former case,
which means for example that if a console only uses dynamic probing, it
will never be usable as a kernel console even when specifying
console=hvc0 explicitly, which could be considered annoying...
More specifically, on pseries, we only do the early instanciate for the
console currently used by the firmware, so if you have your firmware
configured to go to a video card, for example, you cannot get your
kernel console, oops messages, etc... on your serial port or hypervisor
console, which would be handy to deal with oopses.
This fixes it by checking if hvc_console.flags & CON_ENABLED is set when
registering a new dynamic console, and if not, redo the index check and
re-register the console if the index matches, allowing console=hvcN to
work.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c
index 2d691eb..f1d4d96 100644
--- a/drivers/tty/hvc/hvc_console.c
+++ b/drivers/tty/hvc/hvc_console.c
@@ -245,6 +245,20 @@ static void hvc_port_destruct(struct tty_port *port)
kfree(hp);
}
+static void hvc_check_console(int index)
+{
+ /* Already enabled, bail out */
+ if (hvc_console.flags & CON_ENABLED)
+ return;
+
+ /* If this index is what the user requested, then register
+ * now (setup won't fail at this point). It's ok to just
+ * call register again if previously .setup failed.
+ */
+ if (index == hvc_console.index)
+ register_console(&hvc_console);
+}
+
/*
* hvc_instantiate() is an early console discovery method which locates
* consoles * prior to the vio subsystem discovering them. Hotplugged
@@ -275,12 +289,8 @@ int hvc_instantiate(uint32_t vtermno, int index, const struct hv_ops *ops)
if (last_hvc < index)
last_hvc = index;
- /* if this index is what the user requested, then register
- * now (setup won't fail at this point). It's ok to just
- * call register again if previously .setup failed.
- */
- if (index == hvc_console.index)
- register_console(&hvc_console);
+ /* check if we need to re-register the kernel console */
+ hvc_check_console(index);
return 0;
}
@@ -858,10 +868,15 @@ struct hvc_struct *hvc_alloc(uint32_t vtermno, int data,
i = ++last_hvc;
hp->index = i;
+ cons_ops[i] = ops;
+ vtermnos[i] = vtermno;
list_add_tail(&(hp->next), &hvc_structs);
spin_unlock(&hvc_structs_lock);
+ /* check if we need to re-register the kernel console */
+ hvc_check_console(i);
+
return hp;
}
EXPORT_SYMBOL_GPL(hvc_alloc);
@@ -874,8 +889,12 @@ int hvc_remove(struct hvc_struct *hp)
tty = tty_port_tty_get(&hp->port);
spin_lock_irqsave(&hp->lock, flags);
- if (hp->index < MAX_NR_HVC_CONSOLES)
+ if (hp->index < MAX_NR_HVC_CONSOLES) {
+ console_lock();
vtermnos[hp->index] = -1;
+ cons_ops[hp->index] = NULL;
+ console_unlock();
+ }
/* Don't whack hp->irq because tty_hangup() will need to free the irq. */
^ permalink raw reply related
* [PATCH] hvc_vio: Improve registration of udbg backend
From: Benjamin Herrenschmidt @ 2012-07-24 7:47 UTC (permalink / raw)
To: linuxppc-dev
The pseries hvterm driver only registers a udbg backend (for xmon and
other low level debugging mechanisms) when hvc0 is recognized as the
firmware console at boot time, not if it's detected later on, for
example because the firmware is using a graphics card.
This can make debugging challenging especially under X11, and there's
really no good reason for that limitation, so let's hookup udbg
whenever hvc0 is detected instead.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
diff --git a/drivers/tty/hvc/hvc_vio.c b/drivers/tty/hvc/hvc_vio.c
index ee30779..070c0ee6 100644
--- a/drivers/tty/hvc/hvc_vio.c
+++ b/drivers/tty/hvc/hvc_vio.c
@@ -230,6 +230,69 @@ static const struct hv_ops hvterm_hvsi_ops = {
.tiocmset = hvterm_hvsi_tiocmset,
};
+static void udbg_hvc_putc(char c)
+{
+ int count = -1;
+
+ if (!hvterm_privs[0])
+ return;
+
+ if (c == '\n')
+ udbg_hvc_putc('\r');
+
+ do {
+ switch(hvterm_privs[0]->proto) {
+ case HV_PROTOCOL_RAW:
+ count = hvterm_raw_put_chars(0, &c, 1);
+ break;
+ case HV_PROTOCOL_HVSI:
+ count = hvterm_hvsi_put_chars(0, &c, 1);
+ break;
+ }
+ } while(count == 0);
+}
+
+static int udbg_hvc_getc_poll(void)
+{
+ int rc = 0;
+ char c;
+
+ if (!hvterm_privs[0])
+ return -1;
+
+ switch(hvterm_privs[0]->proto) {
+ case HV_PROTOCOL_RAW:
+ rc = hvterm_raw_get_chars(0, &c, 1);
+ break;
+ case HV_PROTOCOL_HVSI:
+ rc = hvterm_hvsi_get_chars(0, &c, 1);
+ break;
+ }
+ if (!rc)
+ return -1;
+ return c;
+}
+
+static int udbg_hvc_getc(void)
+{
+ int ch;
+
+ if (!hvterm_privs[0])
+ return -1;
+
+ for (;;) {
+ ch = udbg_hvc_getc_poll();
+ if (ch == -1) {
+ /* This shouldn't be needed...but... */
+ volatile unsigned long delay;
+ for (delay=0; delay < 2000000; delay++)
+ ;
+ } else {
+ return ch;
+ }
+ }
+}
+
static int __devinit hvc_vio_probe(struct vio_dev *vdev,
const struct vio_device_id *id)
{
@@ -289,6 +352,13 @@ static int __devinit hvc_vio_probe(struct vio_dev *vdev,
return PTR_ERR(hp);
dev_set_drvdata(&vdev->dev, hp);
+ /* register udbg if it's not there already for console 0 */
+ if (hp->index == 0 && !udbg_putc) {
+ udbg_putc = udbg_hvc_putc;
+ udbg_getc = udbg_hvc_getc;
+ udbg_getc_poll = udbg_hvc_getc_poll;
+ }
+
return 0;
}
@@ -331,59 +401,6 @@ static void __exit hvc_vio_exit(void)
}
module_exit(hvc_vio_exit);
-static void udbg_hvc_putc(char c)
-{
- int count = -1;
-
- if (c == '\n')
- udbg_hvc_putc('\r');
-
- do {
- switch(hvterm_priv0.proto) {
- case HV_PROTOCOL_RAW:
- count = hvterm_raw_put_chars(0, &c, 1);
- break;
- case HV_PROTOCOL_HVSI:
- count = hvterm_hvsi_put_chars(0, &c, 1);
- break;
- }
- } while(count == 0);
-}
-
-static int udbg_hvc_getc_poll(void)
-{
- int rc = 0;
- char c;
-
- switch(hvterm_priv0.proto) {
- case HV_PROTOCOL_RAW:
- rc = hvterm_raw_get_chars(0, &c, 1);
- break;
- case HV_PROTOCOL_HVSI:
- rc = hvterm_hvsi_get_chars(0, &c, 1);
- break;
- }
- if (!rc)
- return -1;
- return c;
-}
-
-static int udbg_hvc_getc(void)
-{
- int ch;
- for (;;) {
- ch = udbg_hvc_getc_poll();
- if (ch == -1) {
- /* This shouldn't be needed...but... */
- volatile unsigned long delay;
- for (delay=0; delay < 2000000; delay++)
- ;
- } else {
- return ch;
- }
- }
-}
-
void __init hvc_vio_init_early(void)
{
struct device_node *stdout_node;
^ permalink raw reply related
* RE: [PATCH] powerpc/mm: add ZONE_NORMAL zone for 64 bit kernel
From: Bhushan Bharat-R65777 @ 2012-07-24 8:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Tabi Timur-B04825
Cc: Wood Scott-B07421, Hu Mingkai-B21284,
linuxppc-dev@lists.ozlabs.org, Xie Shaohui-B21989,
Chen Yuanquan-B41889
In-Reply-To: <1343105157.3715.6.camel@pasglop>
> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Ben=
jamin
> Herrenschmidt
> Sent: Tuesday, July 24, 2012 10:16 AM
> To: Tabi Timur-B04825
> Cc: Wood Scott-B07421; Hu Mingkai-B21284; linuxppc-dev@lists.ozlabs.org; =
Xie
> Shaohui-B21989; Chen Yuanquan-B41889
> Subject: Re: [PATCH] powerpc/mm: add ZONE_NORMAL zone for 64 bit kernel
>=20
> On Tue, 2012-07-24 at 04:04 +0000, Tabi Timur-B04825 wrote:
> > Benjamin Herrenschmidt wrote:
> > > Sure but I don't want to create the zones in the first place (and
> > > thus introduce the added pressure on the memory management) on
> > > machines that don't need it.
> >
> > One thing that does confuse me -- by default, we don't create a
> > ZONE_NORMAL. We only create a ZONE_DMA. Why is that? Shouldn't it
> > be the other way around?
>=20
> Because ZONE_NORMAL allocations can be serviced from the ZONE_DMA while t=
he
> other way isn't possible.
Say, if we have defined only one zone (ZONE_DMA) to which we give all memor=
y ( > 4G).
Device set the DMA_MASK to 4G or less.
dma_alloc_coherent() will set GFP_DMA flag, But that is of no use, because =
the memory allocator have only one zone which have all memory (which assume=
s all dma-able). And can return memory at address at > 4G. which will crash=
!!
I think we have to have at least one zone which gives memory to be dma-able=
for all devices (memory limit should be set by platform, because different=
platform have different devices with different limits.). And another ( 1 =
or more) will cover rest of memory.
Thanks
-Bharat
>=20
> Especially in the old days, there were quite a few cases of drivers and/o=
r
> subsystems who were a bit heavy handed at using ZONE_DMA, so not having o=
ne
> would essentially make them not work at all.
>=20
> Cheers,
> Ben.
>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
From: Aneesh Kumar K.V @ 2012-07-24 8:37 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <20120723110654.GC29264@bloggs.ozlabs.ibm.com>
Paul Mackerras <paulus@samba.org> writes:
> On Mon, Jul 23, 2012 at 03:52:05PM +0530, Aneesh Kumar K.V wrote:
>> Paul Mackerras <paulus@samba.org> writes:
>>
>> > On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
>> >
>> >> -#define USER_ESID_BITS 16
>> >> -#define USER_ESID_BITS_1T 4
>> >> +#define USER_ESID_BITS 18
>> >> +#define USER_ESID_BITS_1T 6
>> >
>> > You also need to change the proto-VSID generation for kernel addresses
>> > when you do this. If you don't you'll end up with some user processes
>> > using the same VSIDs as we use for the kernel addresses, meaning that
>> > those processes won't run very well...
>> >
>>
>> Can you explain this more. right now we generate vsid as below
>>
>> vsid_scramble(ea >> SID_SHIFT, 256M) for kernel
>>
>> vsid_scramble((context << USER_ESID_BITS) | (ea >> SID_SHIFT), 256M);
>> for user
>>
>> what changes are you suggesting ?
>
> Think about it. With the current values of USER_ESID_BITS and
> CONTEXT_BITS, and the addresses we use for kernel mappings, there are
> no values of context, user_ea and kernel_ea for which
>
> kernel_ea >> SID_SHIFT == (context << USER_ESID_BITS) | (user_ea >> SID_SHIFT)
>
> If you increase USER_ESID_BITS, then there will be some context values
> for which that equation becomes true. For example, if you increase
> USER_ESID_BITS to 18, then context 0x30000 will generate the same
> proto-VSIDs as the kernel linear mapping. Since we can hand out
> contexts up to 0x7ffff (with CONTEXT_BITS = 19), there is a collision.
>
> In other words, the proto-VSID space (the space of values that are
> input to vsid_scramble) is currently divided into two mutually
> exclusive regions: from 0 to 2^35 - 1 for user processes, and from
> 2^35 to 2^36 - 1 for kernel addresses. You are wanting to expand the
> amount of proto-VSID space that user processes can use, but you need
> either to move the kernel portion of the space, or to make sure that
> the context allocator doesn't hand out context values that would
> collide with the kernel portion of the space (or both).
How about this ?. There is a FIXME in there which is not related.
commit 4881230dc34cbe24141f06004371082da6b121a5
Author: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Date: Tue Jul 24 11:40:29 2012 +0530
proto vsid fixes
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index daa3e4b..736df15 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -516,9 +516,19 @@ typedef struct {
/* This is only valid for addresses >= PAGE_OFFSET */
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble(ea >> SID_SHIFT, 256M);
- return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
+ unsigned long proto_vsid;
+ /*
+ * We need to make sure proto_vsid for the kernel is
+ * >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
+ */
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ea >> SID_SHIFT;
+ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ea >> SID_SHIFT_1T;
+ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
+ return vsid_scramble(proto_vsid, 1T);
}
/* Returns the segment size indicator for a user address */
@@ -534,11 +544,17 @@ static inline int user_segment_size(unsigned long addr)
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble((context << USER_ESID_BITS)
- | (ea >> SID_SHIFT), 256M);
- return vsid_scramble((context << USER_ESID_BITS_1T)
- | (ea >> SID_SHIFT_1T), 1T);
+ unsigned long proto_vsid;
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ((context << USER_ESID_BITS) |(ea >> SID_SHIFT));
+ /* truncate this to 37 bits */
+ proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS)) - 1;
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ((context << USER_ESID_BITS_1T) | (ea >> SID_SHIFT_1T));
+ /* truncate this to 25 bits */
+ proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T)) - 1;
+ return vsid_scramble( proto_vsid, 1T);
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 1c06d29..40ed208 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -958,7 +958,9 @@ _GLOBAL(do_stab_bolted)
rldimi r10,r11,7,52 /* r10 = first ste of the group */
/* Calculate VSID */
- /* This is a kernel address, so protovsid = ESID */
+ /* This is a kernel address, so protovsid = ESID | 1 << 37 */
+ li r9,0x1
+ rldimi r11,r9,(CONTEXT_BITS + USER_ESID_BITS),0
ASM_VSID_SCRAMBLE(r11, r9, 256M)
rldic r9,r11,12,16 /* r9 = vsid << 12 */
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index db2cb3f..792bfa8 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -57,8 +57,13 @@ _GLOBAL(slb_allocate_realmode)
_GLOBAL(slb_miss_kernel_load_linear)
li r11,0
BEGIN_FTR_SECTION
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS_1T),0
b slb_finish_load_1T
1:
@@ -86,8 +91,13 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
li r11,0
6:
BEGIN_FTR_SECTION
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS_1T),0
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -156,10 +166,13 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
BEGIN_FTR_SECTION
cmpldi r10,0x1000
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- rldimi r10,r9,USER_ESID_BITS,0
+ rldimi r10,r9,USER_ESID_BITS,0 /* FIXME!! ? We should do it after srdi ? */
BEGIN_FTR_SECTION
+ srdi r10,r10,40-28 /* get 1T ESID */
+ clrldi r10,r10,(64 - (CONTEXT_BITS + USER_ESID_BITS_1T))
bge slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
+ clrldi r10,r10,(64 - (CONTEXT_BITS + USER_ESID_BITS))
b slb_finish_load
8: /* invalid EA */
@@ -292,7 +305,6 @@ _GLOBAL(slb_compare_rr_to_size)
* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
*/
slb_finish_load_1T:
- srdi r10,r10,40-28 /* get 1T ESID */
ASM_VSID_SCRAMBLE(r10,r9,1T)
/*
* bits above VSID_BITS_1T need to be ignored from r10
^ permalink raw reply related
* Re: [PATCH -V3 11/11] arch/powerpc: Add 64TB support
From: Aneesh Kumar K.V @ 2012-07-24 9:14 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <87eho1o8pv.fsf@skywalker.in.ibm.com>
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
> Paul Mackerras <paulus@samba.org> writes:
>
>> On Mon, Jul 23, 2012 at 03:52:05PM +0530, Aneesh Kumar K.V wrote:
>>> Paul Mackerras <paulus@samba.org> writes:
>>>
>>> > On Mon, Jul 09, 2012 at 06:43:41PM +0530, Aneesh Kumar K.V wrote:
>>> >
>>> >> -#define USER_ESID_BITS 16
>>> >> -#define USER_ESID_BITS_1T 4
>>> >> +#define USER_ESID_BITS 18
>>> >> +#define USER_ESID_BITS_1T 6
>>> >
>>> > You also need to change the proto-VSID generation for kernel addresses
>>> > when you do this. If you don't you'll end up with some user processes
>>> > using the same VSIDs as we use for the kernel addresses, meaning that
>>> > those processes won't run very well...
>>> >
>>>
>>> Can you explain this more. right now we generate vsid as below
>>>
>>> vsid_scramble(ea >> SID_SHIFT, 256M) for kernel
>>>
>>> vsid_scramble((context << USER_ESID_BITS) | (ea >> SID_SHIFT), 256M);
>>> for user
>>>
>>> what changes are you suggesting ?
>>
>> Think about it. With the current values of USER_ESID_BITS and
>> CONTEXT_BITS, and the addresses we use for kernel mappings, there are
>> no values of context, user_ea and kernel_ea for which
>>
>> kernel_ea >> SID_SHIFT == (context << USER_ESID_BITS) | (user_ea >> SID_SHIFT)
>>
>> If you increase USER_ESID_BITS, then there will be some context values
>> for which that equation becomes true. For example, if you increase
>> USER_ESID_BITS to 18, then context 0x30000 will generate the same
>> proto-VSIDs as the kernel linear mapping. Since we can hand out
>> contexts up to 0x7ffff (with CONTEXT_BITS = 19), there is a collision.
>>
>> In other words, the proto-VSID space (the space of values that are
>> input to vsid_scramble) is currently divided into two mutually
>> exclusive regions: from 0 to 2^35 - 1 for user processes, and from
>> 2^35 to 2^36 - 1 for kernel addresses. You are wanting to expand the
>> amount of proto-VSID space that user processes can use, but you need
>> either to move the kernel portion of the space, or to make sure that
>> the context allocator doesn't hand out context values that would
>> collide with the kernel portion of the space (or both).
>
> How about this ?. There is a FIXME in there which is not related.
Updated one with both the fixes. Let me know what you think
>From f04a505be381b9c162fa41bda5df4a1a9edfdeb9 Mon Sep 17 00:00:00 2001
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Date: Tue, 24 Jul 2012 14:22:15 +0530
Subject: [PATCH 1/2] arch/powerpc: properly offset the context bits for 1T
segemnts
We should do rldimi r10,r9,USER_ESID_BITS,0 only after populating
r10 with ESID bits.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/slb_low.S | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index db2cb3f..7bd8438 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -59,6 +59,7 @@ _GLOBAL(slb_miss_kernel_load_linear)
BEGIN_FTR_SECTION
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
b slb_finish_load_1T
1:
@@ -88,6 +89,7 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
BEGIN_FTR_SECTION
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+ srdi r10,r10,40-28 /* get 1T ESID */
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -155,13 +157,16 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
ld r9,PACACONTEXTID(r13)
BEGIN_FTR_SECTION
cmpldi r10,0x1000
+ bge 9f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
rldimi r10,r9,USER_ESID_BITS,0
+ b slb_finish_load
BEGIN_FTR_SECTION
- bge slb_finish_load_1T
+9:
+ srdi r10,r10,40-28 /* get 1T ESID */
+ rldimi r10,r9,USER_ESID_BITS,0
+ b slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- b slb_finish_load
-
8: /* invalid EA */
li r10,0 /* BAD_VSID */
li r11,SLB_VSID_USER /* flags don't much matter */
@@ -292,7 +297,6 @@ _GLOBAL(slb_compare_rr_to_size)
* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
*/
slb_finish_load_1T:
- srdi r10,r10,40-28 /* get 1T ESID */
ASM_VSID_SCRAMBLE(r10,r9,1T)
/*
* bits above VSID_BITS_1T need to be ignored from r10
--
1.7.10
>From 43792d9e2c394370c71623f2769d11ff98090918 Mon Sep 17 00:00:00 2001
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Date: Tue, 24 Jul 2012 11:40:29 +0530
Subject: [PATCH 2/2] arch/powerpc: properly isolate kernel and user
proto-VSID
The proto-VSID space is divided into two class
User: 0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
This patch does above isolation
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 32 ++++++++++++++++++++++++--------
arch/powerpc/kernel/exceptions-64s.S | 4 +++-
arch/powerpc/mm/slb_low.S | 10 ++++++++++
3 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index daa3e4b..736df15 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -516,9 +516,19 @@ typedef struct {
/* This is only valid for addresses >= PAGE_OFFSET */
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble(ea >> SID_SHIFT, 256M);
- return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
+ unsigned long proto_vsid;
+ /*
+ * We need to make sure proto_vsid for the kernel is
+ * >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
+ */
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ea >> SID_SHIFT;
+ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ea >> SID_SHIFT_1T;
+ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
+ return vsid_scramble(proto_vsid, 1T);
}
/* Returns the segment size indicator for a user address */
@@ -534,11 +544,17 @@ static inline int user_segment_size(unsigned long addr)
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
int ssize)
{
- if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble((context << USER_ESID_BITS)
- | (ea >> SID_SHIFT), 256M);
- return vsid_scramble((context << USER_ESID_BITS_1T)
- | (ea >> SID_SHIFT_1T), 1T);
+ unsigned long proto_vsid;
+ if (ssize == MMU_SEGSIZE_256M) {
+ proto_vsid = ((context << USER_ESID_BITS) |(ea >> SID_SHIFT));
+ /* truncate this to 37 bits */
+ proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS)) - 1;
+ return vsid_scramble(proto_vsid, 256M);
+ }
+ proto_vsid = ((context << USER_ESID_BITS_1T) | (ea >> SID_SHIFT_1T));
+ /* truncate this to 25 bits */
+ proto_vsid &= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T)) - 1;
+ return vsid_scramble( proto_vsid, 1T);
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 1c06d29..40ed208 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -958,7 +958,9 @@ _GLOBAL(do_stab_bolted)
rldimi r10,r11,7,52 /* r10 = first ste of the group */
/* Calculate VSID */
- /* This is a kernel address, so protovsid = ESID */
+ /* This is a kernel address, so protovsid = ESID | 1 << 37 */
+ li r9,0x1
+ rldimi r11,r9,(CONTEXT_BITS + USER_ESID_BITS),0
ASM_VSID_SCRAMBLE(r11, r9, 256M)
rldic r9,r11,12,16 /* r9 = vsid << 12 */
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 7bd8438..e6bace3 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -57,9 +57,13 @@ _GLOBAL(slb_allocate_realmode)
_GLOBAL(slb_miss_kernel_load_linear)
li r11,0
BEGIN_FTR_SECTION
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
srdi r10,r10,40-28 /* get 1T ESID */
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS_1T),0
b slb_finish_load_1T
1:
@@ -87,9 +91,13 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
li r11,0
6:
BEGIN_FTR_SECTION
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
srdi r10,r10,40-28 /* get 1T ESID */
+ li r9,0x1
+ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS_1T),0
b slb_finish_load_1T
0: /* user address: proto-VSID = context << 15 | ESID. First check
@@ -160,11 +168,13 @@ BEGIN_FTR_SECTION
bge 9f
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
rldimi r10,r9,USER_ESID_BITS,0
+ clrldi r10,r10,(64 - (CONTEXT_BITS + USER_ESID_BITS))
b slb_finish_load
BEGIN_FTR_SECTION
9:
srdi r10,r10,40-28 /* get 1T ESID */
rldimi r10,r9,USER_ESID_BITS,0
+ clrldi r10,r10,(64 - (CONTEXT_BITS + USER_ESID_BITS_1T))
b slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
8: /* invalid EA */
--
1.7.10
^ permalink raw reply related
* Re: Memory management problems on a custom PPC 8270 board
From: Geoffrey Bugniot @ 2012-07-24 9:16 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <500D8067.6070805@freescale.com>
Scott Wood <scottwood <at> freescale.com> writes:
>
> On 07/23/2012 10:34 AM, Geoffrey Bugniot wrote:
> > I got something like that :
> > [ 148.891584] Kernel panic - not syncing: Attempted to kill init!
>
> Was there anything before this?
>
No, that's the complete dump.
> > [ 148.897503] Call Trace:
> > [ 148.899934] [c7829d10] [c0008fbc] show_stack+0x4c/0x138 (unreliable)
> > [ 148.906470] [c7829d50] [c03be7d8] panic+0xa4/0x1e8
> > [ 148.911401] [c7829db0] [c0025580] do_exit+0x94/0x630
> > [ 148.916501] [c7829e00] [c0025bdc] do_group_exit+0x80/0xac
> > [ 148.922071] [c7829e10] [c00340d8] get_signal_to_deliver+0x474/0x490
> > [ 148.928515] [c7829e70] [c0009aa4] do_signal_pending.constprop.9+0x40/0x22c
> > [ 148.935586] [c7829f30] [c0009d88] do_signal+0x24/0x50
> > [ 148.940793] [c7829f40] [c000f76c] do_user_signal+0x74/0xc4
> > [ 148.946419] --- Exception: 700 at 0xfec5394
> > [ 148.946433] LR = 0x1000410c
> > [ 148.954009] Rebooting in 3 seconds..
>
> This looks like your init process crashed. You could try enabling
> show_unhandled_signals in arch/powerpc/signal.c.
With "show_unhandled_signals = 1", I get few lines more :
root@pLinesE_VMEb:~# tar cvf file.tar.gz file1 file2 file3 file4
file1
file2
file3
file4
tar[243]: unhandled signal 11 at bfaec004 nip 100064fc lr 100063dc code
30001
Segmentation fault
sh[233]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0febf0e0 code 30001
klogd[227]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0ffabb8c code
30001
init[244]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0ffabb8c code 30001
init[245]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0ffabb8c code 30001
init[246]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0ffabb8c code 30001
init[247]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0ffabb8c code 30001
init[248]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0ffabb8c code 30001
init[249]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0ffabb8c code 30001
init[250]: unhandled signal 4 at 0febf184 nip 0febf184 lr 0ffabb8c code 30001
Kernel panic - not syncing: Attempted to kill init!
Call Trace:
[c7815d30] [c0007d1c] show_stack+0x4c/0x138 (unreliable)
[c7815d70] [c01e2004] panic+0xa4/0x1d8
[c7815dd0] [c001ddb0] do_exit+0xa0/0x5c0
[c7815e20] [c001e390] do_group_exit+0x80/0xac
[c7815e30] [c00285c0] get_signal_to_deliver+0x2e4/0x300
[c7815e70] [c00087f4] do_signal_pending.constprop.9+0x40/0x22c
[c7815f30] [c0008ad8] do_signal+0x24/0x50
[c7815f40] [c000deec] do_user_signal+0x74/0xc4
--- Exception: 700 at 0xfebf184
LR = 0xffabb8c
Rebooting in 3 seconds..
> What are you running as your init process? Do you have a normal
> init/login scheme, or are you running a shell (esp. busybox, which would
> have cp built in) directly as init?
I build the kernel with an initramfs. In this one, I have an init script for
mounting my flash device (which contains a JFF2 filesystem based on ELDK),
and to process the "switch_root". Indeed, I used BusyBox in my initramfs and in
the ELDK filesystem.
> > When I use netsniff-ng, with default parameters, kernel hangs too. But If I
> > specify a small ring buffer size with option "netsniff-ng -S 3MB" all is
> > running fine. Here, is the dump when netsniff-ng causes a crash:
> >
> > root <at> pLinesE_VMEb:~# netsniff-ng
> > netsniff-ng 0.5.5.0 -- pid (245)
> > [ 36.065574] device eth0 entered promiscuous mode
> > nice (0), scheduler (0 prio 0)
> > 1 of 1 CPUs online, affinity bitstring (1)
> > No device specified, using `eth0`.
> > No filter applied. Switching to `all traffic`.
> >
> > [ 36.159714] BUG: Bad page state in process netsniff-ng pfn:05401
> > [ 36.165759] page:c0401020 count:0 mapcount:1 mapping: (null)
> > index:0x0
> > [ 36.172548] page flags: 0x0()
>
> Could you have bad memory timings (or bad memory)? Usually when I see
> things like this, it's because memory is getting corrupted.
After more investigation, with gdb, the panic occurs when the the function
"setsockopt" is called with the famous buffer (specify with -S xxMB) as a
parameter. And it's the first use of the buffer in the code.
I noticed that too : when I run tcpdump, It works, but if I run two tcpdump at
the same time, segmentation faults or illegal instructions appears.
It seems link to the usage of my memory. How can I investigate further to
identify eventuals memory timing problems?
^ permalink raw reply
* [PATCH 2/6] powerpc/fsl-pci: Check swiotlb enable at board setup_arch stage
From: Jia Hongtao @ 2012-07-24 10:20 UTC (permalink / raw)
To: linuxppc-dev, galak, B07421; +Cc: b38951
In-Reply-To: <1343125210-16720-1-git-send-email-B38951@freescale.com>
PCI initialization is called later than swiotlb_init() due to PCI controller is
a platform driver now. So we provide a function which called at board setup_arch
stage to address swiotlb enable by parsing pci ranges.
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/sysdev/fsl_pci.c | 125 ++++++++++++++++++++++++++++++++++++-----
arch/powerpc/sysdev/fsl_pci.h | 6 ++
2 files changed, 116 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index feed364..99a3e78 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -822,6 +822,116 @@ static const struct of_device_id pci_ids[] = {
{},
};
+#ifdef CONFIG_SWIOTLB
+void pci_check_swiotlb(void)
+{
+ const u32 *ranges;
+ int rlen;
+ int pna;
+ int np;
+ struct device_node *node;
+ int memno;
+ u32 pci_space;
+ unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
+ unsigned long long pci_addr_lo = ULLONG_MAX;
+ unsigned long long pci_addr_hi = 0x0;
+ dma_addr_t pci_dma_sz;
+
+ for_each_node_by_type(node, "pci") {
+ if (of_match_node(pci_ids, node)) {
+ memno = 0;
+ pna = of_n_addr_cells(node);
+ np = pna + 5;
+ /* Get ranges property */
+ ranges = of_get_property(node, "ranges", &rlen);
+ if (ranges == NULL)
+ return;
+
+ /* Parse outbound MEM window range */
+ while ((rlen -= np * 4) >= 0) {
+ /* Read next ranges element */
+ pci_space = ranges[0];
+ if (!((pci_space >> 24) & 0x2)) {
+ ranges += np;
+ break;
+ }
+ pci_addr = of_read_number(ranges + 1, 2);
+ cpu_addr = of_translate_address(
+ node, ranges + 3);
+ size = of_read_number(ranges + pna + 3, 2);
+ ranges += np;
+
+ /*
+ * If we failed translation or got a zero-sized
+ * region (some FW try to feed us with non
+ * sensical zero sized regions such as power3
+ * which look like some kind of attempt at
+ * exposing the VGA memory hole)
+ */
+ if (cpu_addr == OF_BAD_ADDR || size == 0)
+ continue;
+
+ /*
+ * Now consume following elements while they
+ * are contiguous
+ */
+ for (; rlen >= np * sizeof(u32);
+ ranges += np, rlen -= np * 4) {
+ if (ranges[0] != pci_space)
+ break;
+ pci_next = of_read_number(ranges + 1,
+ 2);
+ cpu_next = of_translate_address(node,
+ ranges + 3);
+ if (pci_next != pci_addr + size ||
+ cpu_next != cpu_addr + size)
+ break;
+ size += of_read_number(
+ ranges + pna + 3, 2);
+ }
+
+ /* We support only 3 memory ranges */
+ if (memno >= 3) {
+ printk(KERN_INFO
+ " \\--> Skipped (too many) !\n");
+ continue;
+ }
+
+ pci_addr_lo = min(pci_addr, pci_addr_lo);
+ pci_addr_hi = max(pci_addr + size, pci_addr_hi);
+ memno++;
+ }
+ }
+ }
+
+ /* Get PEXCSRBAR size (equal to CCSR size) */
+ node = of_find_node_by_type(NULL, "soc");
+ ranges = of_get_property(node, "ranges", &rlen);
+ if (ranges == NULL)
+ return;
+
+ size = of_read_number(ranges + 3, 1);
+ of_node_put(node);
+
+ if (pci_addr_hi < (0x100000000ull - size))
+ pci_dma_sz = pci_addr_lo;
+ else
+ pci_dma_sz = pci_addr_lo - size;
+
+ /*
+ * if we couldn't map all of DRAM via the dma windows
+ * we need SWIOTLB to handle buffers located outside of
+ * dma capable memory region
+ */
+ if (memblock_end_of_DRAM() > pci_dma_sz) {
+ ppc_swiotlb_enable = 1;
+ set_pci_dma_ops(&swiotlb_dma_ops);
+ ppc_md.pci_dma_dev_setup =
+ pci_dma_dev_setup_swiotlb;
+ }
+}
+#endif
+
int primary_phb_addr;
static int __devinit fsl_pci_probe(struct platform_device *pdev)
{
@@ -833,21 +943,6 @@ static int __devinit fsl_pci_probe(struct platform_device *pdev)
of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
is_primary = ((rsrc.start & 0xfffff) == primary_phb_addr);
fsl_add_bridge(pdev->dev.of_node, is_primary);
-
-#ifdef CONFIG_SWIOTLB
- hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
- /*
- * if we couldn't map all of DRAM via the dma windows
- * we need SWIOTLB to handle buffers located outside of
- * dma capable memory region
- */
- if (memblock_end_of_DRAM() > hose->dma_window_base_cur
- + hose->dma_window_size) {
- ppc_swiotlb_enable = 1;
- set_pci_dma_ops(&swiotlb_dma_ops);
- ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
- }
-#endif
}
return 0;
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index df9fc44..c2c1de5 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -94,5 +94,11 @@ extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
u64 fsl_pci_immrbar_base(struct pci_controller *hose);
+#ifdef CONFIG_SWIOTLB
+extern void pci_check_swiotlb(void);
+#else
+static inline void pci_check_swiotlb(void) {}
+#endif
+
#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */
--
1.7.5.1
^ permalink raw reply related
* [PATCH 1/6] powerpc/fsl-pci: Unify pci/pcie initialization code
From: Jia Hongtao @ 2012-07-24 10:20 UTC (permalink / raw)
To: linuxppc-dev, galak, B07421; +Cc: b38951
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver.
In previous version pci/pcie initialization is in platform code which
Initialize pci bridge base on EP/RC or host/agent settings.
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/sysdev/fsl_pci.c | 60 +++++++++++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/fsl_pci.h | 1 +
2 files changed, 61 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index edbf794..feed364 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -807,3 +807,63 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return 0;
}
+
+#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
+static const struct of_device_id pci_ids[] = {
+ { .compatible = "fsl,mpc8540-pci", },
+ { .compatible = "fsl,mpc8548-pcie", },
+ { .compatible = "fsl,mpc8641-pcie", },
+ { .compatible = "fsl,p1022-pcie", },
+ { .compatible = "fsl,p1010-pcie", },
+ { .compatible = "fsl,p1023-pcie", },
+ { .compatible = "fsl,p4080-pcie", },
+ { .compatible = "fsl,qoriq-pcie-v2.3", },
+ { .compatible = "fsl,qoriq-pcie-v2.2", },
+ {},
+};
+
+int primary_phb_addr;
+static int __devinit fsl_pci_probe(struct platform_device *pdev)
+{
+ struct pci_controller *hose;
+ bool is_primary;
+
+ if (of_match_node(pci_ids, pdev->dev.of_node)) {
+ struct resource rsrc;
+ of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
+ is_primary = ((rsrc.start & 0xfffff) == primary_phb_addr);
+ fsl_add_bridge(pdev->dev.of_node, is_primary);
+
+#ifdef CONFIG_SWIOTLB
+ hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
+ /*
+ * if we couldn't map all of DRAM via the dma windows
+ * we need SWIOTLB to handle buffers located outside of
+ * dma capable memory region
+ */
+ if (memblock_end_of_DRAM() > hose->dma_window_base_cur
+ + hose->dma_window_size) {
+ ppc_swiotlb_enable = 1;
+ set_pci_dma_ops(&swiotlb_dma_ops);
+ ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+ }
+#endif
+ }
+
+ return 0;
+}
+
+static struct platform_driver fsl_pci_driver = {
+ .driver = {
+ .name = "fsl-pci",
+ .of_match_table = pci_ids,
+ },
+ .probe = fsl_pci_probe,
+};
+
+static int __init fsl_pci_init(void)
+{
+ return platform_driver_register(&fsl_pci_driver);
+}
+arch_initcall(fsl_pci_init);
+#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5c..df9fc44 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -88,6 +88,7 @@ struct ccsr_pci {
__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
};
+extern int primary_phb_addr;
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
--
1.7.5.1
^ permalink raw reply related
* [PATCH 3/6] powerpc/fsl-pci: Determine primary bus by looking for ISA node
From: Jia Hongtao @ 2012-07-24 10:20 UTC (permalink / raw)
To: linuxppc-dev, galak, B07421; +Cc: b38951
In-Reply-To: <1343125210-16720-1-git-send-email-B38951@freescale.com>
PCI host bridge is primary bus if it contains an ISA node. But not all boards
fit this rule. Device tree should be updated for all these boards.
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/include/asm/pci-bridge.h | 1 +
arch/powerpc/sysdev/fsl_pci.c | 31 ++++++++++++++++++++++++-------
arch/powerpc/sysdev/fsl_pci.h | 12 +++++++++++-
3 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index ac39e6a..b48fa7f 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -20,6 +20,7 @@ struct device_node;
struct pci_controller {
struct pci_bus *bus;
char is_dynamic;
+ int is_primary;
#ifdef CONFIG_PPC64
int node;
#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 99a3e78..2a369be 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -453,6 +453,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
+ hose->is_primary = is_primary;
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN);
@@ -932,18 +933,34 @@ void pci_check_swiotlb(void)
}
#endif
-int primary_phb_addr;
+/*
+ * Recursively scan all the children nodes of parent and find out if there
+ * is "isa" node. Return 1 if parent has isa node otherwise return 0.
+ */
+int has_isa_node(struct device_node *parent)
+{
+ static int result;
+ struct device_node *cur_child;
+
+ cur_child = NULL;
+ result = 0;
+ while (!result && (cur_child = of_get_next_child(parent, cur_child))) {
+ /* Get "isa" node and return 1 */
+ if (of_node_cmp(cur_child->type, "isa") == 0)
+ return result = 1;
+ has_isa_node(cur_child);
+ }
+
+ return result;
+}
+
static int __devinit fsl_pci_probe(struct platform_device *pdev)
{
- struct pci_controller *hose;
bool is_primary;
+ is_primary = has_isa_node(pdev->dev.of_node);
- if (of_match_node(pci_ids, pdev->dev.of_node)) {
- struct resource rsrc;
- of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
- is_primary = ((rsrc.start & 0xfffff) == primary_phb_addr);
+ if (of_match_node(pci_ids, pdev->dev.of_node))
fsl_add_bridge(pdev->dev.of_node, is_primary);
- }
return 0;
}
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index c2c1de5..abbc09d 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -88,7 +88,17 @@ struct ccsr_pci {
__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
};
-extern int primary_phb_addr;
+
+#ifdef CONFIG_SUSPEND
+struct fsl_pci_private_data {
+ int inbound_num;
+ struct pci_outbound_window_regs __iomem *pci_pow;
+ struct pci_inbound_window_regs __iomem *pci_piw;
+ void *saved_regs;
+};
+#endif
+
+extern int is_has_isa_node(struct device_node *parent);
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
extern int mpc83xx_add_bridge(struct device_node *dev);
--
1.7.5.1
^ permalink raw reply related
* [PATCH 4/6] powerpc/mpc85xx_ds: convert to unified PCI init
From: Jia Hongtao @ 2012-07-24 10:20 UTC (permalink / raw)
To: linuxppc-dev, galak, B07421; +Cc: b38951
In-Reply-To: <1343125210-16720-1-git-send-email-B38951@freescale.com>
PCI initialization is now done by PCI controller driver. In board setup_arch
stage we don't need PCI init any more but swiotlb should be determined at this
stage.
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/platforms/85xx/common.c | 9 ++++
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 75 +++--------------------------
2 files changed, 17 insertions(+), 67 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 67dac22..303fedb 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -27,6 +27,15 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
{ .compatible = "fsl,mpc8548-guts", },
/* Probably unnecessary? */
{ .compatible = "gpio-leds", },
+ /* For all PCI controllers */
+ { .compatible = "fsl,mpc8540-pci", },
+ { .compatible = "fsl,mpc8548-pcie", },
+ { .compatible = "fsl,p1022-pcie", },
+ { .compatible = "fsl,p1010-pcie", },
+ { .compatible = "fsl,p1023-pcie", },
+ { .compatible = "fsl,p4080-pcie", },
+ { .compatible = "fsl,qoriq-pcie-v2.3", },
+ { .compatible = "fsl,qoriq-pcie-v2.2", },
{},
};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index d30f6c4..b7ef007 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -114,22 +114,14 @@ void __init mpc85xx_ds_pic_init(void)
}
#ifdef CONFIG_PCI
-static int primary_phb_addr;
extern int uli_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn);
static int mpc85xx_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn)
{
- struct device_node* node;
- struct resource rsrc;
-
- node = hose->dn;
- of_address_to_resource(node, 0, &rsrc);
-
- if ((rsrc.start & 0xfffff) == primary_phb_addr) {
+ if (hose->is_primary)
return uli_exclude_device(hose, bus, devfn);
- }
return PCIBIOS_SUCCESSFUL;
}
@@ -140,46 +132,16 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
*/
static void __init mpc85xx_ds_setup_arch(void)
{
-#ifdef CONFIG_PCI
- struct device_node *np;
- struct pci_controller *hose;
-#endif
- dma_addr_t max = 0xffffffff;
-
if (ppc_md.progress)
ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
#ifdef CONFIG_PCI
- for_each_node_by_type(np, "pci") {
- if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
- of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
- of_device_is_compatible(np, "fsl,p2020-pcie")) {
- struct resource rsrc;
- of_address_to_resource(np, 0, &rsrc);
- if ((rsrc.start & 0xfffff) == primary_phb_addr)
- fsl_add_bridge(np, 1);
- else
- fsl_add_bridge(np, 0);
-
- hose = pci_find_hose_for_OF_device(np);
- max = min(max, hose->dma_window_base_cur +
- hose->dma_window_size);
- }
- }
-
+ pci_check_swiotlb();
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif
mpc85xx_smp_init();
-#ifdef CONFIG_SWIOTLB
- if ((memblock_end_of_DRAM() - 1) > max) {
- ppc_swiotlb_enable = 1;
- set_pci_dma_ops(&swiotlb_dma_ops);
- ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
- }
-#endif
-
printk("MPC85xx DS board from Freescale Semiconductor\n");
}
@@ -190,19 +152,12 @@ static int __init mpc8544_ds_probe(void)
{
unsigned long root = of_get_flat_dt_root();
- if (of_flat_dt_is_compatible(root, "MPC8544DS")) {
-#ifdef CONFIG_PCI
- primary_phb_addr = 0xb000;
-#endif
- return 1;
- }
-
- return 0;
+ return of_flat_dt_is_compatible(root, "MPC8544DS");
}
-machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
-machine_device_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
-machine_device_initcall(p2020_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
+machine_arch_initcall(p2020_ds, mpc85xx_common_publish_devices);
machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
@@ -215,14 +170,7 @@ static int __init mpc8572_ds_probe(void)
{
unsigned long root = of_get_flat_dt_root();
- if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) {
-#ifdef CONFIG_PCI
- primary_phb_addr = 0x8000;
-#endif
- return 1;
- }
-
- return 0;
+ return of_flat_dt_is_compatible(root, "fsl,MPC8572DS");
}
/*
@@ -232,14 +180,7 @@ static int __init p2020_ds_probe(void)
{
unsigned long root = of_get_flat_dt_root();
- if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
-#ifdef CONFIG_PCI
- primary_phb_addr = 0x9000;
-#endif
- return 1;
- }
-
- return 0;
+ return of_flat_dt_is_compatible(root, "fsl,P2020DS");
}
define_machine(mpc8544_ds) {
--
1.7.5.1
^ permalink raw reply related
* [PATCH 5/6] powerpc/fsl-pci: Add pci inbound/outbound PM support
From: Jia Hongtao @ 2012-07-24 10:20 UTC (permalink / raw)
To: linuxppc-dev, galak, B07421; +Cc: b38951
In-Reply-To: <1343125210-16720-1-git-send-email-B38951@freescale.com>
Power supply for PCI inbound/outbound window registers is off when system
go to deep-sleep state. We save the values of registers before suspend
and restore to registers after resume.
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/include/asm/pci-bridge.h | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 121 +++++++++++++++++++++++++++++++++
2 files changed, 122 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index b48fa7f..f0f00a7 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -90,9 +90,9 @@ struct pci_controller {
#ifdef CONFIG_PPC64
unsigned long buid;
+#endif /* CONFIG_PPC64 */
void *private_data;
-#endif /* CONFIG_PPC64 */
};
/* These are used for config access before all the PCI probing
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 2a369be..a14ee6f 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -965,12 +965,133 @@ static int __devinit fsl_pci_probe(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_SUSPEND
+
+#define PCI_POW_PIW_OFFSET 0xc00
+#define PCI_POW_PIW_SIZE 0x200
+#define PCI_POW_NUMBER 5
+
+static int fsl_pci_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct pci_controller *hose;
+ struct pci_outbound_window_regs *pci_saved_pow;
+ struct pci_inbound_window_regs *pci_saved_piw, *temp_piw;
+ struct resource pci_rsrc;
+ unsigned int i;
+ struct fsl_pci_private_data *sus_info;
+
+ hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
+ of_address_to_resource(pdev->dev.of_node, 0, &pci_rsrc);
+
+ sus_info = kmalloc(
+ sizeof(struct fsl_pci_private_data), GFP_KERNEL);
+ if (!sus_info)
+ return -ENOMEM;
+
+ hose->private_data = sus_info;
+
+ sus_info->pci_pow = ioremap(pci_rsrc.start + PCI_POW_PIW_OFFSET,
+ PCI_POW_PIW_SIZE);
+ if (!sus_info->pci_pow) {
+ dev_err(&pdev->dev, "pci outbound/inbound windows ioremap error!\n");
+ goto err1;
+ }
+
+ sus_info->pci_piw = (struct pci_inbound_window_regs *)
+ ((void *)sus_info->pci_pow + PCI_POW_PIW_SIZE) - 1;
+
+ if (of_device_is_compatible(pdev->dev.of_node, "fsl,qoriq-pcie-v2.2"))
+ sus_info->inbound_num = 4;
+ else
+ sus_info->inbound_num = 3;
+
+ sus_info->saved_regs = kmalloc(
+ sizeof(struct pci_outbound_window_regs) * PCI_POW_NUMBER +
+ sizeof(struct pci_inbound_window_regs) * sus_info->inbound_num,
+ GFP_KERNEL);
+ if (!sus_info->saved_regs)
+ goto err2;
+
+ pci_saved_pow = sus_info->saved_regs;
+ for (i = 0; i < PCI_POW_NUMBER; i++) {
+ pci_saved_pow[i].potar = in_be32(&sus_info->pci_pow[i].potar);
+ pci_saved_pow[i].potear = in_be32(&sus_info->pci_pow[i].potear);
+ pci_saved_pow[i].powbar = in_be32(&sus_info->pci_pow[i].powbar);
+ pci_saved_pow[i].powar = in_be32(&sus_info->pci_pow[i].powar);
+ }
+
+ pci_saved_piw = (struct pci_inbound_window_regs *)
+ (pci_saved_pow + PCI_POW_NUMBER);
+ temp_piw = sus_info->pci_piw;
+ for (i = 0; i < sus_info->inbound_num; i++, temp_piw--) {
+ pci_saved_piw[i].pitar = in_be32(&temp_piw->pitar);
+ pci_saved_piw[i].piwbar = in_be32(&temp_piw->piwbar);
+ pci_saved_piw[i].piwbear = in_be32(&temp_piw->piwbear);
+ pci_saved_piw[i].piwar = in_be32(&temp_piw->piwar);
+ }
+
+ return 0;
+
+err2:
+ iounmap(sus_info->pci_pow);
+
+err1:
+ kfree(sus_info);
+ return -ENOMEM;
+}
+
+static int fsl_pci_resume(struct platform_device *pdev)
+{
+ struct pci_controller *hose;
+ struct pci_outbound_window_regs *pci_saved_pow;
+ struct pci_inbound_window_regs *pci_saved_piw, *temp_piw;
+ unsigned int i;
+ struct fsl_pci_private_data *sus_info;
+
+ hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
+ sus_info = (struct fsl_pci_private_data *)hose->private_data;
+
+ if (!sus_info->pci_pow || !sus_info->pci_piw || !sus_info->saved_regs)
+ return 0;
+
+ pci_saved_pow = sus_info->saved_regs;
+ for (i = 0; i < PCI_POW_NUMBER; i++) {
+ out_be32(&sus_info->pci_pow[i].potar, pci_saved_pow[i].potar);
+ out_be32(&sus_info->pci_pow[i].potear, pci_saved_pow[i].potear);
+ out_be32(&sus_info->pci_pow[i].powbar, pci_saved_pow[i].powbar);
+ out_be32(&sus_info->pci_pow[i].powar, pci_saved_pow[i].powar);
+ }
+
+ pci_saved_piw = (struct pci_inbound_window_regs *)
+ (pci_saved_pow + PCI_POW_NUMBER);
+ temp_piw = sus_info->pci_piw;
+ for (i = 0; i < sus_info->inbound_num; i++, temp_piw--) {
+ out_be32(&temp_piw->pitar, pci_saved_piw[i].pitar);
+ out_be32(&temp_piw->piwbar, pci_saved_piw[i].piwbar);
+ out_be32(&temp_piw->piwbear, pci_saved_piw[i].piwbear);
+ out_be32(&temp_piw->piwar, pci_saved_piw[i].piwar);
+ }
+ iounmap(sus_info->pci_pow);
+ kfree(sus_info->saved_regs);
+ sus_info->saved_regs = NULL;
+ kfree(sus_info);
+ sus_info = NULL;
+ hose->private_data = NULL;
+
+ return 0;
+}
+#endif
+
static struct platform_driver fsl_pci_driver = {
.driver = {
.name = "fsl-pci",
.of_match_table = pci_ids,
},
.probe = fsl_pci_probe,
+#ifdef CONFIG_SUSPEND
+ .suspend = fsl_pci_suspend,
+ .resume = fsl_pci_resume,
+#endif
};
static int __init fsl_pci_init(void)
--
1.7.5.1
^ permalink raw reply related
* [PATCH 6/6] Edac/85xx: Register mpc85xx_pci_err_driver by fsl_pci_driver
From: Jia Hongtao @ 2012-07-24 10:20 UTC (permalink / raw)
To: linuxppc-dev, galak, B07421; +Cc: b38951
In-Reply-To: <1343125210-16720-1-git-send-email-B38951@freescale.com>
From: Chunhe Lan <Chunhe.Lan@freescale.com>
Now we registered pci controllers as platform devices. It will make edac
driver failed to register pci nodes as platform devices too. So we combine
two initialization code as one platform driver.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
---
arch/powerpc/sysdev/fsl_pci.c | 4 +++
arch/powerpc/sysdev/fsl_pci.h | 4 +++
drivers/edac/mpc85xx_edac.c | 43 +++++++++++-----------------------------
3 files changed, 20 insertions(+), 31 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index a14ee6f..5bc8222 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -962,6 +962,10 @@ static int __devinit fsl_pci_probe(struct platform_device *pdev)
if (of_match_node(pci_ids, pdev->dev.of_node))
fsl_add_bridge(pdev->dev.of_node, is_primary);
+#ifdef CONFIG_EDAC_MPC85XX
+ mpc85xx_pci_err_probe(pdev);
+#endif
+
return 0;
}
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index abbc09d..1dfe85d 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -110,5 +110,9 @@ extern void pci_check_swiotlb(void);
static inline void pci_check_swiotlb(void) {}
#endif
+#ifdef CONFIG_EDAC_MPC85XX
+extern int mpc85xx_pci_err_probe(struct platform_device *op);
+#endif
+
#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index 0e37462..e4b6113 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -200,7 +200,7 @@ static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
+int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
{
struct edac_pci_ctl_info *pci;
struct mpc85xx_pci_pdata *pdata;
@@ -214,6 +214,16 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
if (!pci)
return -ENOMEM;
+ /* make sure error reporting method is sane */
+ switch (edac_op_state) {
+ case EDAC_OPSTATE_POLL:
+ case EDAC_OPSTATE_INT:
+ break;
+ default:
+ edac_op_state = EDAC_OPSTATE_INT;
+ break;
+ }
+
pdata = pci->pvt_info;
pdata->name = "mpc85xx_pci_err";
pdata->irq = NO_IRQ;
@@ -303,6 +313,7 @@ err:
devres_release_group(&op->dev, mpc85xx_pci_err_probe);
return res;
}
+EXPORT_SYMBOL(mpc85xx_pci_err_probe);
static int mpc85xx_pci_err_remove(struct platform_device *op)
{
@@ -326,27 +337,6 @@ static int mpc85xx_pci_err_remove(struct platform_device *op)
return 0;
}
-static struct of_device_id mpc85xx_pci_err_of_match[] = {
- {
- .compatible = "fsl,mpc8540-pcix",
- },
- {
- .compatible = "fsl,mpc8540-pci",
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
-
-static struct platform_driver mpc85xx_pci_err_driver = {
- .probe = mpc85xx_pci_err_probe,
- .remove = __devexit_p(mpc85xx_pci_err_remove),
- .driver = {
- .name = "mpc85xx_pci_err",
- .owner = THIS_MODULE,
- .of_match_table = mpc85xx_pci_err_of_match,
- },
-};
-
#endif /* CONFIG_PCI */
/**************************** L2 Err device ***************************/
@@ -1193,12 +1183,6 @@ static int __init mpc85xx_mc_init(void)
if (res)
printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
-#ifdef CONFIG_PCI
- res = platform_driver_register(&mpc85xx_pci_err_driver);
- if (res)
- printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
-#endif
-
#ifdef CONFIG_FSL_SOC_BOOKE
pvr = mfspr(SPRN_PVR);
@@ -1235,9 +1219,6 @@ static void __exit mpc85xx_mc_exit(void)
on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
}
#endif
-#ifdef CONFIG_PCI
- platform_driver_unregister(&mpc85xx_pci_err_driver);
-#endif
platform_driver_unregister(&mpc85xx_l2_err_driver);
platform_driver_unregister(&mpc85xx_mc_err_driver);
}
--
1.7.5.1
^ permalink raw reply related
* RE: [2/3][PATCH][upstream] TDM Framework
From: Singh Sandeep-B37400 @ 2012-07-24 13:22 UTC (permalink / raw)
To: Tabi Timur-B04825; +Cc: Aggrwal Poonam-B10812, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <CAOZdJXVnEUEQesyG52pL_jerGDrmJLxdfBNFrj_xvhPs=ue4DA@mail.gmail.com>
Hi Timur,
Thanks for your comments, please find response inline.
Regards,
Sandeep
-----Original Message-----
From: Tabi Timur-B04825=20
Sent: Monday, July 23, 2012 10:03 PM
To: Singh Sandeep-B37400
Cc: linuxppc-dev@lists.ozlabs.org; Singh Sandeep-B37400; Aggrwal Poonam-B10=
812
Subject: Re: [2/3][PATCH][upstream] TDM Framework
On Mon, Jul 23, 2012 at 5:49 AM, <b37400@freescale.com> wrote:
> From: Sandeep Singh <Sandeep@freescale.com>
Please fix your git configuration so that the From: line in your
emails contains your full name. This patch was sent with this From:
line:
From: <b37400@freescale.com>
It should say:
From: Sandeep Singh <sandeep@freescale.com>
Three more things:
1) You don't need to add [upstream] to patches that are posted upstream.
2) This patch needs to be CC'd to linux-kernel@vger.kernel.org and devel@dr=
iverdev.osuosl.org.
3) I'm concerned that there is no "struct device" anywhere in this framewor=
k. I think that's a serious omission, and you need to figure out where you=
can put this.
[Sandeep] 1) & 2) Ok, Will take care. 3)Ok, will check.
> diff --git a/drivers/tdm/tdm-core.c b/drivers/tdm/tdm-core.c new file=20
> mode 100644 index 0000000..9973b6b
> --- /dev/null
> +++ b/drivers/tdm/tdm-core.c
> @@ -0,0 +1,1082 @@
> +/* driver/tdm/tdm-core.c
> + *
> + * Copyright (C) 2012 Freescale Semiconductor, Inc, All rights reserved.
I've been seeing this copyright messages a lot recently, and I don't unders=
tand why. This message is incorrectly formatted. The "(C)" is redundant, =
and the phrase "All rights reserved." is wrong. This patch is licensed und=
er the GPL, so we are NOT reserving all rights, we are actually giving up s=
ome rights.
Please change this to:
Copyright 2012 Freescale Semiconductor, Inc.
[Sandeep] Will correct this.
> + *
> + * TDM core is the interface between TDM clients and TDM devices.
> + * It is also intended to serve as an interface for line controlled
> + * devices later on.
> + *
> + * Author:Hemant Agrawal <hemant@freescale.com>
> + * Rajesh Gumasta <rajesh.gumasta@freescale.com>
If these two are the authors, why are they not on the signed-off-by lines?
[Sandeep] Will add them to signoff.
> + *
> + * Modified by Sandeep Kr Singh <sandeep@freescale.com>
> + * Poonam Aggarwal <poonam.aggarwal@freescale.com>
Do not add "modified" by lines to the code. That's why we have a git histo=
ry.
[Sandeep] Ok.
> + * 1. Added framework based initialization of device.
> + * 2. All the init/run time configuration is now done by framework.
> + * 3. Added channel level operations.
> + * 4. Added sysfs knob to configure use_latest_tdm_data at runtime.
Again, this is not information that belongs in the source file.
[Sandeep] OK
> + *
> + * Note that some parts of this code may have been derived from i2c subs=
ystem.
> + *
> + * This program is free software; you can redistribute it and/or=20
> + modify it
> + * under the terms of the GNU General Public License as published=20
> + by the
> + * Free Software Foundation; either version 2 of the License, or=20
> + (at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,=20
> + but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License=20
> + along
> + * with this program; if not, write to the Free Software Foundation,=20
> + Inc.,
> + * 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/errno.h>
> +#include <linux/slab.h>
> +#include <linux/tdm.h>
> +#include <linux/init.h>
> +#include <linux/idr.h>
> +#include <linux/mutex.h>
> +#include <linux/completion.h>
> +#include <linux/hardirq.h>
> +#include <linux/irqflags.h>
> +#include <linux/list.h>
> +#include <linux/uaccess.h>
> +#include <linux/io.h>
Are you sure you need all of these header files?
[Sandeep] Will check.
> +
> +
> +static DEFINE_MUTEX(tdm_core_lock);
> +static DEFINE_IDR(tdm_adapter_idr);
> +/* List of TDM adapters registered with TDM framework */=20
> +LIST_HEAD(adapter_list);
> +
> +/* List of TDM clients registered with TDM framework */=20
> +LIST_HEAD(driver_list);
> +
> +/* In case the previous data is not fetched by the client driver, the
> + * de-interleaving function will discard the old data and rewrite=20
> +the
> + * new data */
Proper multi-line comment format is like this:
[Sandeep] Ok.
/*
* In case the previous data is not fetched by the client driver, the
* de-interleaving function will discard the old data and rewrite the
* new data.
*/
> +static int use_latest_tdm_data =3D 1;
> +
> +/* Data structures required for sysfs */ static struct tdm_sysfs attr=20
> +=3D {
> + .attr.name =3D "use_latest_data",
> + .attr.mode =3D 0664,
> + .cmd_type =3D TDM_LATEST_DATA,
> +};
> +
> +static struct attribute *tdm_attr[] =3D {
> + &attr.attr,
> + NULL
> +};
> +
> +const struct sysfs_ops tdm_ops =3D {
> + .show =3D tdm_show_sysfs,
> + .store =3D tdm_store_sysfs,
> +};
> +
> +static struct kobj_type tdm_type =3D {
> + .sysfs_ops =3D &tdm_ops,
> + .default_attrs =3D tdm_attr,
> +};
Why are some of these 'const' and some aren't? They should all be 'const'
[Sandeep] Ok.
> +
> +/* tries to match client driver with the adapter */ static int=20
> +tdm_device_match(struct tdm_driver *driver, struct tdm_adapter *adap)=20
> +{
> + /* match on an id table if there is one */
> + if (driver->id_table && driver->id_table->name[0]) {
> + if (!(strcmp(driver->id_table->name, adap->name)))
> + return (int)driver->id_table;
> + }
> + return TDM_E_OK;
Get rid of TDM_E_OK. It's the only error code that you've defined, and it'=
s set to 0. That doesn't mean anything.
[Sandeep] Ok
> +}
> +
> +static int tdm_attach_driver_adap(struct tdm_driver *driver,
> + struct tdm_adapter *adap) {
> + int ret =3D TDM_E_OK;
> + /* if driver is already attached to any other adapter, return*/
> + if (driver->adapter && (driver->adapter !=3D adap))
> + return ret;
> +
> + driver->adapter =3D adap;
> +
> + if (driver->attach_adapter) {
> + ret =3D driver->attach_adapter(adap);
> + if (ret < 0) {
> + pr_err("attach_adapter failed for driver [%s] err=
:%d\n"
> + , driver->name, ret);
> + return ret;
> + }
> + }
> + adap->drv_count++;
> +
> + if (!adap->tasklet_conf) {
> + tdm_sysfs_init();
> + tasklet_init(&adap->tdm_data_tasklet, tdm_data_tasklet_fn=
,
> + (unsigned long)adap);
> + adap->tasklet_conf =3D 1;
> + }
> +
> + return ret;
If 'ret' can only be 0, then just return 0.
return 0;
[Sandeep] Ok, will change.
> +/* tdm_adap_send - issue a TDM write
> + * @adap: Handle to TDM device
> + * @buf: Data that will be written to the TDM device
> + * @count: How many bytes to write
> + *
> + * Returns negative errno, or else the number of bytes written.
"Returns negative error number, or else the number of bytes written."
You're typing this on a full keyboard, not a smart phone. Please don't use=
abbreviations unnecessarily.
[Sandeep] Ok, will rectify.
> + */
> +int tdm_adap_send(struct tdm_adapter *adap, void **buf, int count) {
> + int res;
> +
> + if (adap->algo->tdm_write)
> + res =3D adap->algo->tdm_write(adap, buf, count);
Why does tdm_write() return a u32? And shouldn't 'res' also be a u32, to m=
ake tdm_write()?
[Sandeep] tdm_write() returns number of bytes written. You are right, 'res'=
should be declared as u32
> +/* Port Level APIs of TDM Framework */ int tdm_port_open(struct=20
> +tdm_driver *driver, struct tdm_port **h_port) {
> + struct tdm_port *port;
> + struct tdm_adapter *adap;
> + unsigned long flags;
> + int res =3D TDM_E_OK;
> +
> + adap =3D tdm_get_adapter(driver->adapter->id);
> + if (!adap)
> + return -ENODEV;
> +
> + /* This creates an anonymous tdm_port, which may later be
> + * pointed to some slot.
> + *
> + */
> + port =3D kzalloc(sizeof(*port), GFP_KERNEL);
> + if (!port) {
> + res =3D -ENOMEM;
> + goto out;
> + }
Just return here. You don't need to "goto out". And I think you forgot to=
call tdm_put_adapter(), although it might be easier if you call kzalloc() =
first, and then tdm_get_adapter().
[Sandeep] Ok.
> +
> + port->rx_max_frames =3D NUM_SAMPLES_PER_FRAME;
> + port->port_cfg.port_mode =3D TDM_PORT_CHANNELIZED;
> +
> + snprintf(driver->name, TDM_NAME_SIZE, "tdm-dev");
> + port->driver =3D driver;
> + port->adapter =3D adap;
> +
> + spin_lock_irqsave(&adap->portlist_lock, flags);
> + list_add_tail(&port->list, &adap->myports);
> + spin_unlock_irqrestore(&adap->portlist_lock, flags);
Are you sure you need to disable interrupts? That seems excessive.
[Sandeep] Will check once.
> +int tdm_channel_read(struct tdm_port *h_port, struct tdm_channel *h_chan=
nel,
> + void *p_data, u16 *size) {
> + struct tdm_channel *channel;
> + struct tdm_bd *rx_bd;
> + unsigned long flags;
> + int i, res =3D TDM_E_OK;
> + unsigned short *buf, *buf1;
> + channel =3D h_channel;
> +
> + if (!channel->p_ch_data || !channel->in_use)
> + return -EIO;
> +
> + spin_lock_irqsave(&channel->p_ch_data->rx_channel_lock, flags);
> + rx_bd =3D channel->p_ch_data->rx_out_data;
> +
> + if (rx_bd->flag) {
> + *size =3D rx_bd->length;
> + buf =3D (u16 *) p_data;
> + buf1 =3D (u16 *)rx_bd->p_data;
> + for (i =3D 0; i < NUM_SAMPLES_PER_FRAME; i++)
> + buf[i] =3D buf1[i];
Use memcpy() instead.
[Sandeep] Ok
> +int tdm_channel_write(struct tdm_port *h_port, struct tdm_channel *h_cha=
nnel,
> + void *p_data, u16 size) {
> + struct tdm_port *port;
> + struct tdm_channel *channel;
> + struct tdm_bd *tx_bd;
> + unsigned long flags;
> + int err =3D TDM_E_OK;
> + port =3D h_port;
> + channel =3D h_channel;
> +#ifdef DEBUG
> + bool data_flag =3D 0;
> +#endif
> +
> + if (p_data =3D=3D NULL) { /* invalid data*/
> + pr_err("Invalid Data");
> + return -EFAULT;
> + }
EFAULT is for invalid memory access. I think you mean EINVAL here.
[Sandeep] Right. Will correct.
> +
> + if (!channel->p_ch_data || !channel->in_use)
> + return -EIO;
> +
> + spin_lock_irqsave(&channel->p_ch_data->tx_channel_lock, flags);
> + tx_bd =3D channel->p_ch_data->tx_in_data;
> +
> + if (!tx_bd->flag) {
> + tx_bd->length =3D size;
> + memcpy(tx_bd->p_data, p_data,
> + size * port->adapter->adapt_cfg.slot_widt=
h);
> + tx_bd->flag =3D 1;
> + tx_bd->offset =3D 0;
> + channel->p_ch_data->tx_in_data =3D (tx_bd->wrap) ?
> + channel->p_ch_data->tx_data_fifo : tx_bd+1;
> + port->port_stat.tx_pkt_count++; #ifdef DEBUG
> + data_flag =3D 1;
> +#endif
> + } else {
> + spin_unlock_irqrestore(&channel->p_ch_data->tx_channel_lo=
ck,
> + flags);
> + port->port_stat.tx_pkt_drop_count++;
> + pr_err("E_NO_MEMORY -Failed Transmit");
Please review ALL of your error messages, and make sure that have a proper =
prefix ("tdm: ") and all look the same. Don't use __func__ in any of them,=
and make sure the error messages are clear, English text.
[Sandeep] Ok.
> + return -ENOMEM;
I'm not sure ENOMEM is appropriate here.
[Sandeep] Will check.
> + }
> + spin_unlock_irqrestore(&channel->p_ch_data->tx_channel_lock,=20
> + flags);
> +
> +#ifdef DEBUG
> + if (data_flag) {
> + int k;
> + pr_info("\nTX port:%d - Write - Port TX-%d\n",
> + port->port_id, size);
> + for (k =3D 0; k < size; k++)
> + pr_info("%x", p_data[k]);
> + pr_info("\n");
> + }
> +#endif
> + return err;
> +}
> +EXPORT_SYMBOL(tdm_channel_write);
> +
> +/* Driver Function for select and poll. Based on Channel, it sleeps=20
> +on
> + * waitqueue */
> +int tdm_ch_poll(struct tdm_channel *h_channel, unsigned int=20
> +wait_time) {
> + struct tdm_channel *channel;
> + unsigned long timeout =3D msecs_to_jiffies(wait_time);
> + channel =3D h_channel;
> +
> + if (!channel->p_ch_data || !channel->in_use)
> + return -EIO;
> +
> + if (channel->p_ch_data->rx_out_data->flag) {
> + pr_debug("Data Available");
> + return TDM_E_OK;
> + }
> + if (timeout) {
> + =20
> + wait_event_interruptible_timeout(channel->ch_wait_queue,
It'd be more efficient if you did this:
if (wait_time) {
unsigned long timeout =3D msecs_to_jiffies(wait_time);
wait_event_interruptible_timeout(channel->ch_wait_queue,
[Sandeep] Ok.
> + channel->p_ch_data->rx_out_data->flag,
> + timeout);
> +
> + if (channel->p_ch_data->rx_out_data->flag) {
> + pr_debug("Data Available");
> + return TDM_E_OK;
> + }
> + }
> + return -EAGAIN;
> +}
> +EXPORT_SYMBOL(tdm_ch_poll);
> +
> +unsigned int tdm_port_get_stats(struct tdm_port *h_port,
> + struct tdm_port_stats *portStat)
Do not use CamelCase in variable names.
[Sandeep] Ok, will modify.
> diff --git a/include/linux/tdm.h b/include/linux/tdm.h new file mode=20
> 100644 index 0000000..a2f9628
> --- /dev/null
> +++ b/include/linux/tdm.h
> @@ -0,0 +1,338 @@
> +/* include/linux/tdm.h
> + *
> + * Copyright (C) 2012 Freescale Semiconductor, Inc, All rights reserved.
> + *
> + * tdm.h - definitions for the tdm-device framework interface
> + *
> + * Author:Hemant Agrawal <hemant@freescale.com>
> + * Rajesh Gumasta <rajesh.gumasta@freescale.com>
> + *
> + * This program is free software; you can redistribute it and/or=20
> +modify it
> + * under the terms of the GNU General Public License as published=20
> +by the
> + * Free Software Foundation; either version 2 of the License, or=20
> +(at your
> + * option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,=20
> +but
> + * WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License=20
> +along
> + * with this program; if not, write to the Free Software Foundation,=20
> +Inc.,
> + * 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +
> +#ifndef _LINUX_TDM_H
> +#define _LINUX_TDM_H
> +
> +#include <linux/types.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/device.h> /* for struct device */
> +#include <linux/sched.h> /* for completion */
> +#include <linux/mutex.h>
> +#include <linux/interrupt.h>
> +#include <linux/sysfs.h>
> +
> +#define TDM_LATEST_DATA 1
> +#define CHANNEL_8BIT_LIN 0 /* 8 bit linear */
> +#define CHANNEL_8BIT_ULAW 1 /* 8 bit Mu-law */
> +#define CHANNEL_8BIT_ALAW 2 /* 8 bit A-law */
> +#define CHANNEL_16BIT_LIN 3 /* 16 bit Linear */
> +
> +/*
> + * Default adapter configuration. All the TDM adapters registered=20
> +with
> + * framework will be configured with following default configuration.
> + */
> +#define NUM_CHANNELS 16
> +
> +/* Default configuration for typical voice data sample. These=20
> +parameters
> + * will generally not be required to be changed for voice type applicati=
ons.
> + */
> +#define NUM_SAMPLES_PER_MS 8 /* 8 samples per milli sec per
> + channel. Req for voice data */
> +#define NUM_MS 10
> +#define NUM_SAMPLES_PER_FRAME (NUM_MS * NUM_SAMPLES_PER_MS) /* Number o=
f
> + samples for 1 client buff=
er */
> +#define NUM_OF_TDM_BUF 3
> +
> +/* General options */
> +
> +struct tdm_adapt_algorithm;
> +struct tdm_adapter;
> +struct tdm_port;
> +struct tdm_driver;
I don't think you need "struct tdm_driver;"
[Sandeep] Right. Will remove.
> +/* tdm_adapter_mode is to define in mode of the device */ enum=20
> +tdm_adapter_mode {
> + TDM_ADAPTER_MODE_NONE =3D 0x00,
> + TDM_ADAPTER_MODE_T1 =3D 0x01,
> + TDM_ADAPTER_MODE_E1 =3D 0x02,
> + TDM_ADAPTER_MODE_T1_RAW =3D 0x10,
> + TDM_ADAPTER_MODE_E1_RAW =3D 0x20,
Where did these numbers come from?
[Sandeep] This is not related to any bit definition, just enum values.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [2/3][PATCH][upstream] TDM Framework
From: Timur Tabi @ 2012-07-24 14:43 UTC (permalink / raw)
To: Singh Sandeep-B37400; +Cc: Aggrwal Poonam-B10812, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <3F1D9DCAAB49B94D88DBE05911FA4E6E50ED27@039-SN1MPN1-006.039d.mgd.msft.net>
Singh Sandeep-B37400 wrote:
>> +int tdm_adap_send(struct tdm_adapter *adap, void **buf, int count) {
>> + int res;
>> +
>> + if (adap->algo->tdm_write)
>> + res = adap->algo->tdm_write(adap, buf, count);
>
> Why does tdm_write() return a u32? And shouldn't 'res' also be a u32, to make tdm_write()?
> [Sandeep] tdm_write() returns number of bytes written. You are right, 'res' should be declared as u32
Then it should return an unsigned int. You should used a sized integer
type only when the size really matters (e.g. hardware registers or packed
fields in a structure).
>> +/* tdm_adapter_mode is to define in mode of the device */ enum
>> +tdm_adapter_mode {
>> + TDM_ADAPTER_MODE_NONE = 0x00,
>> + TDM_ADAPTER_MODE_T1 = 0x01,
>> + TDM_ADAPTER_MODE_E1 = 0x02,
>> + TDM_ADAPTER_MODE_T1_RAW = 0x10,
>> + TDM_ADAPTER_MODE_E1_RAW = 0x20,
>
> Where did these numbers come from?
> [Sandeep] This is not related to any bit definition, just enum values.
Yes, but why these particular numbers? Also, do they really need to be an
enum? Since you're defining hard values for each enum, you're not really
using them as an enum. Make these into macros.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* RE: [1/3][PATCH][upstream]Adding documentation for TDM
From: Aggrwal Poonam-B10812 @ 2012-07-24 15:12 UTC (permalink / raw)
To: David Laight, Singh Sandeep-B37400, linuxppc-dev@lists.ozlabs.org
Cc: Singh Sandeep-B37400
In-Reply-To: <AE90C24D6B3A694183C094C60CF0A2F6026B6FA4@saturn3.aculab.com>
Thanks David for the comments.
Response Inline.
Regards
Poonam
> -----Original Message-----
> From: David Laight [mailto:David.Laight@ACULAB.COM]
> Sent: Monday, July 23, 2012 6:02 PM
> To: Singh Sandeep-B37400; linuxppc-dev@lists.ozlabs.org
> Cc: Singh Sandeep-B37400; Aggrwal Poonam-B10812
> Subject: RE: [1/3][PATCH][upstream]Adding documentation for TDM
>=20
> > +3. TDM has programmable slot length (8 bits or 16 bits). This can be
> > + configured by:
> > +
> > + #define NUM_BYTES_PER_SLOT 8
>=20
> I presume you meant NUM_BITS_PER_SLOT ?
> These constants need name-space protection
>=20
> > +or
> > + #define NUM_BYTES_PER_SLOT 16
> > +
This is a mistake, documentation patch not updated with the update design.
> > +depending on the type of sample. For example the sample could be 16
> > +bit linear +or 8bit u-law encoded etc.
> > +Presently only word length of 16 is supported which is the default
> > +configuration.
>=20
> For flexibility you need to allow for 8bit samples being converted as:
> 1) 8bit raw ulaw or alaw data (unchanged from line).
> 2) 8bit raw data, bit reversed, any hdlc protocol
> is bit reversed from audio [1].
> 3) 8bit audio, converted from alaw to ulaw
> 4) 8bit audio, converted from ulaw to alaw
> 5) 16bit linear converted to/from alaw or ulaw and on a per-timeslot
> basis.
I agree. That we only support very limited samples. But We can add this in =
second step once the basic framework is in.
Also right now the testing infrastructure we have, we won't be able to test=
all these scenarios.
>=20
> [1] most hdlc stuff probably can't stand the 10ms epochs though, so this
> is limited use for serious work.
Right now the framework has been customized for voice. We can keep this par=
ameter as a sysfs knob. Please suggest.
Regards
Poonam
>=20
> David
>=20
>=20
>=20
^ permalink raw reply
* [PATCH] powerpc/p5040ds: Add support for P5040DS board
From: Timur Tabi @ 2012-07-24 16:42 UTC (permalink / raw)
To: Kumar Gala, linuxppc-dev
Add support for the Freescale P5040DS Reference Board ("Superhydra"), whi=
ch
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabri=
c
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving sup=
port
Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA
Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I=C2=B2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 320 +++++++++++++++++++=
++++++
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 111 +++++++++
arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi | 118 +++++++++
arch/powerpc/boot/dts/p5040ds.dts | 207 ++++++++++++++++
arch/powerpc/configs/corenet32_smp_defconfig | 1 +
arch/powerpc/configs/corenet64_smp_defconfig | 1 +
arch/powerpc/platforms/85xx/Kconfig | 14 +
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/p5040_ds.c | 96 ++++++++
9 files changed, 869 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
create mode 100644 arch/powerpc/boot/dts/p5040ds.dts
create mode 100644 arch/powerpc/platforms/85xx/p5040_ds.c
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/b=
oot/dts/fsl/p5040si-post.dtsi
new file mode 100644
index 0000000..cc1e606
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -0,0 +1,320 @@
+/*
+ * P5040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions ar=
e met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyrig=
ht
+ * notice, this list of conditions and the following disclaimer in=
the
+ * documentation and/or other materials provided with the distribu=
tion.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote pro=
ducts
+ * derived from this software without specific prior written permi=
ssion.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of th=
e
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the imp=
lied
+ * warranties of merchantability and fitness for a particular purpose ar=
e
+ * disclaimed. In no event shall Freescale Semiconductor be liable for a=
ny
+ * direct, indirect, incidental, special, exemplary, or consequential da=
mages
+ * (including, but not limited to, procurement of substitute goods or se=
rvices;
+ * loss of use, data, or profits; or business interruption) however caus=
ed and
+ * on any theory of liability, whether in contract, strict liability, or=
tort
+ * (including negligence or otherwise) arising in any way out of the use=
of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+&lbc {
+ compatible =3D "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
+ interrupts =3D <25 2 0 0>;
+ #address-cells =3D <2>;
+ #size-cells =3D <1>;
+};
+
+/* controller at 0x200000 */
+&pci0 {
+ compatible =3D "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type =3D "pci";
+ #size-cells =3D <2>;
+ #address-cells =3D <3>;
+ bus-range =3D <0x0 0xff>;
+ clock-frequency =3D <33333333>;
+ interrupts =3D <16 2 1 15>;
+ pcie@0 {
+ reg =3D <0 0 0 0 0>;
+ #interrupt-cells =3D <1>;
+ #size-cells =3D <2>;
+ #address-cells =3D <3>;
+ device_type =3D "pci";
+ interrupts =3D <16 2 1 15>;
+ interrupt-map-mask =3D <0xf800 0 0 7>;
+ interrupt-map =3D <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ };
+};
+
+/* controller at 0x201000 */
+&pci1 {
+ compatible =3D "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type =3D "pci";
+ #size-cells =3D <2>;
+ #address-cells =3D <3>;
+ bus-range =3D <0 0xff>;
+ clock-frequency =3D <33333333>;
+ interrupts =3D <16 2 1 14>;
+ pcie@0 {
+ reg =3D <0 0 0 0 0>;
+ #interrupt-cells =3D <1>;
+ #size-cells =3D <2>;
+ #address-cells =3D <3>;
+ device_type =3D "pci";
+ interrupts =3D <16 2 1 14>;
+ interrupt-map-mask =3D <0xf800 0 0 7>;
+ interrupt-map =3D <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ };
+};
+
+/* controller at 0x202000 */
+&pci2 {
+ compatible =3D "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type =3D "pci";
+ #size-cells =3D <2>;
+ #address-cells =3D <3>;
+ bus-range =3D <0x0 0xff>;
+ clock-frequency =3D <33333333>;
+ interrupts =3D <16 2 1 13>;
+ pcie@0 {
+ reg =3D <0 0 0 0 0>;
+ #interrupt-cells =3D <1>;
+ #size-cells =3D <2>;
+ #address-cells =3D <3>;
+ device_type =3D "pci";
+ interrupts =3D <16 2 1 13>;
+ interrupt-map-mask =3D <0xf800 0 0 7>;
+ interrupt-map =3D <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ };
+};
+
+&dcsr {
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ compatible =3D "fsl,dcsr", "simple-bus";
+
+ dcsr-epu@0 {
+ compatible =3D "fsl,dcsr-epu";
+ interrupts =3D <52 2 0 0
+ 84 2 0 0
+ 85 2 0 0>;
+ reg =3D <0x0 0x1000>;
+ };
+ dcsr-npc {
+ compatible =3D "fsl,dcsr-npc";
+ reg =3D <0x1000 0x1000 0x1000000 0x8000>;
+ };
+ dcsr-nxc@2000 {
+ compatible =3D "fsl,dcsr-nxc";
+ reg =3D <0x2000 0x1000>;
+ };
+ dcsr-corenet {
+ compatible =3D "fsl,dcsr-corenet";
+ reg =3D <0x8000 0x1000 0xB0000 0x1000>;
+ };
+ dcsr-dpaa@9000 {
+ compatible =3D "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
+ reg =3D <0x9000 0x1000>;
+ };
+ dcsr-ocn@11000 {
+ compatible =3D "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
+ reg =3D <0x11000 0x1000>;
+ };
+ dcsr-ddr@12000 {
+ compatible =3D "fsl,dcsr-ddr";
+ dev-handle =3D <&ddr1>;
+ reg =3D <0x12000 0x1000>;
+ };
+ dcsr-ddr@13000 {
+ compatible =3D "fsl,dcsr-ddr";
+ dev-handle =3D <&ddr2>;
+ reg =3D <0x13000 0x1000>;
+ };
+ dcsr-nal@18000 {
+ compatible =3D "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
+ reg =3D <0x18000 0x1000>;
+ };
+ dcsr-rcpm@22000 {
+ compatible =3D "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
+ reg =3D <0x22000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@40000 {
+ compatible =3D "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle =3D <&cpu0>;
+ reg =3D <0x40000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@41000 {
+ compatible =3D "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle =3D <&cpu1>;
+ reg =3D <0x41000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@42000 {
+ compatible =3D "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle =3D <&cpu2>;
+ reg =3D <0x42000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@43000 {
+ compatible =3D "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle =3D <&cpu3>;
+ reg =3D <0x43000 0x1000>;
+ };
+};
+
+&soc {
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ device_type =3D "soc";
+ compatible =3D "simple-bus";
+
+ soc-sram-error {
+ compatible =3D "fsl,soc-sram-error";
+ interrupts =3D <16 2 1 29>;
+ };
+
+ corenet-law@0 {
+ compatible =3D "fsl,corenet-law";
+ reg =3D <0x0 0x1000>;
+ fsl,num-laws =3D <32>;
+ };
+
+ ddr1: memory-controller@8000 {
+ compatible =3D "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-c=
ontroller";
+ reg =3D <0x8000 0x1000>;
+ interrupts =3D <16 2 1 23>;
+ };
+
+ ddr2: memory-controller@9000 {
+ compatible =3D "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-co=
ntroller";
+ reg =3D <0x9000 0x1000>;
+ interrupts =3D <16 2 1 22>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible =3D "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-co=
ntroller", "cache";
+ reg =3D <0x10000 0x1000
+ 0x11000 0x1000>;
+ interrupts =3D <16 2 1 27
+ 16 2 1 26>;
+ };
+
+ corenet-cf@18000 {
+ compatible =3D "fsl,corenet-cf";
+ reg =3D <0x18000 0x1000>;
+ interrupts =3D <16 2 1 31>;
+ fsl,ccf-num-csdids =3D <32>;
+ fsl,ccf-num-snoopids =3D <32>;
+ };
+
+ iommu@20000 {
+ compatible =3D "fsl,pamu-v1.0", "fsl,pamu";
+ reg =3D <0x20000 0x5000>;
+ interrupts =3D <
+ 24 2 0 0
+ 16 2 1 30>;
+ };
+
+/include/ "qoriq-mpic.dtsi"
+
+ guts: global-utilities@e0000 {
+ compatible =3D "fsl,qoriq-device-config-1.0";
+ reg =3D <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ #sleep-cells =3D <1>;
+ fsl,liodn-bits =3D <12>;
+ };
+
+ pins: global-utilities@e0e00 {
+ compatible =3D "fsl,qoriq-pin-control-1.0";
+ reg =3D <0xe0e00 0x200>;
+ #sleep-cells =3D <2>;
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible =3D "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg =3D <0xe1000 0x1000>;
+ clock-frequency =3D <0>;
+ };
+
+ rcpm: global-utilities@e2000 {
+ compatible =3D "fsl,qoriq-rcpm-1.0";
+ reg =3D <0xe2000 0x1000>;
+ #sleep-cells =3D <1>;
+ };
+
+ sfp: sfp@e8000 {
+ compatible =3D "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
+ reg =3D <0xe8000 0x1000>;
+ };
+
+ serdes: serdes@ea000 {
+ compatible =3D "fsl,p5040-serdes";
+ reg =3D <0xea000 0x1000>;
+ };
+
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+ spi@110000 {
+ fsl,espi-num-chipselects =3D <4>;
+ };
+
+/include/ "qoriq-esdhc-0.dtsi"
+ sdhc@114000 {
+ sdhci,auto-cmd12;
+ };
+
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+ usb0: usb@210000 {
+ compatible =3D "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2=
-mph";
+ phy_type =3D "utmi";
+ port0;
+ };
+
+/include/ "qoriq-usb2-dr-0.dtsi"
+ usb1: usb@211000 {
+ compatible =3D "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-d=
r";
+ dr_mode =3D "host";
+ phy_type =3D "utmi";
+ };
+
+/include/ "qoriq-sata2-0.dtsi"
+/include/ "qoriq-sata2-1.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/bo=
ot/dts/fsl/p5040si-pre.dtsi
new file mode 100644
index 0000000..52721b6
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -0,0 +1,111 @@
+/*
+ * P5040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions ar=
e met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyrig=
ht
+ * notice, this list of conditions and the following disclaimer in=
the
+ * documentation and/or other materials provided with the distribu=
tion.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote pro=
ducts
+ * derived from this software without specific prior written permi=
ssion.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of th=
e
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the imp=
lied
+ * warranties of merchantability and fitness for a particular purpose ar=
e
+ * disclaimed. In no event shall Freescale Semiconductor be liable for a=
ny
+ * direct, indirect, incidental, special, exemplary, or consequential da=
mages
+ * (including, but not limited to, procurement of substitute goods or se=
rvices;
+ * loss of use, data, or profits; or business interruption) however caus=
ed and
+ * on any theory of liability, whether in contract, strict liability, or=
tort
+ * (including negligence or otherwise) arising in any way out of the use=
of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+/ {
+ compatible =3D "fsl,P5040";
+ #address-cells =3D <2>;
+ #size-cells =3D <2>;
+ interrupt-parent =3D <&mpic>;
+
+ aliases {
+ ccsr =3D &soc;
+ dcsr =3D &dcsr;
+
+ serial0 =3D &serial0;
+ serial1 =3D &serial1;
+ serial2 =3D &serial2;
+ serial3 =3D &serial3;
+ pci0 =3D &pci0;
+ pci1 =3D &pci1;
+ pci2 =3D &pci2;
+ usb0 =3D &usb0;
+ usb1 =3D &usb1;
+ dma0 =3D &dma0;
+ dma1 =3D &dma1;
+ sdhc =3D &sdhc;
+ msi0 =3D &msi0;
+ msi1 =3D &msi1;
+ msi2 =3D &msi2;
+
+ crypto =3D &crypto;
+ sec_jr0 =3D &sec_jr0;
+ sec_jr1 =3D &sec_jr1;
+ sec_jr2 =3D &sec_jr2;
+ sec_jr3 =3D &sec_jr3;
+ rtic_a =3D &rtic_a;
+ rtic_b =3D &rtic_b;
+ rtic_c =3D &rtic_c;
+ rtic_d =3D &rtic_d;
+ sec_mon =3D &sec_mon;
+ };
+
+ cpus {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type =3D "cpu";
+ reg =3D <0>;
+ next-level-cache =3D <&L2_0>;
+ L2_0: l2-cache {
+ next-level-cache =3D <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type =3D "cpu";
+ reg =3D <1>;
+ next-level-cache =3D <&L2_1>;
+ L2_1: l2-cache {
+ next-level-cache =3D <&cpc>;
+ };
+ };
+ cpu2: PowerPC,e5500@2 {
+ device_type =3D "cpu";
+ reg =3D <2>;
+ next-level-cache =3D <&L2_2>;
+ L2_2: l2-cache {
+ next-level-cache =3D <&cpc>;
+ };
+ };
+ cpu3: PowerPC,e5500@3 {
+ device_type =3D "cpu";
+ reg =3D <3>;
+ next-level-cache =3D <&L2_3>;
+ L2_3: l2-cache {
+ next-level-cache =3D <&cpc>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi b/arch/powerpc=
/boot/dts/fsl/qoriq-sec5.2-0.dtsi
new file mode 100644
index 0000000..7b2ab8a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
@@ -0,0 +1,118 @@
+/*
+ * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 =
]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions ar=
e met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyrig=
ht
+ * notice, this list of conditions and the following disclaimer in=
the
+ * documentation and/or other materials provided with the distribu=
tion.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote pro=
ducts
+ * derived from this software without specific prior written permi=
ssion.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of th=
e
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND AN=
Y
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMP=
LIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AR=
E
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR A=
NY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA=
MAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SE=
RVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUS=
ED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR=
TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE=
OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+crypto: crypto@300000 {
+ compatible =3D "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ reg =3D <0x300000 0x10000>;
+ ranges =3D <0 0x300000 0x10000>;
+ interrupts =3D <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible =3D "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg =3D <0x1000 0x1000>;
+ interrupts =3D <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible =3D "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg =3D <0x2000 0x1000>;
+ interrupts =3D <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible =3D "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg =3D <0x3000 0x1000>;
+ interrupts =3D <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible =3D "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg =3D <0x4000 0x1000>;
+ interrupts =3D <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible =3D "fsl,sec-v5.2-rtic",
+ "fsl,sec-v5.0-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ reg =3D <0x6000 0x100>;
+ ranges =3D <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible =3D "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg =3D <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible =3D "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg =3D <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible =3D "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg =3D <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible =3D "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg =3D <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible =3D "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mo=
n";
+ reg =3D <0x314000 0x1000>;
+ interrupts =3D <93 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/p5040ds.dts b/arch/powerpc/boot/dts/p5=
040ds.dts
new file mode 100644
index 0000000..c15ba68
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5040ds.dts
@@ -0,0 +1,207 @@
+/*
+ * P5040DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions ar=
e met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyrig=
ht
+ * notice, this list of conditions and the following disclaimer in=
the
+ * documentation and/or other materials provided with the distribu=
tion.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote pro=
ducts
+ * derived from this software without specific prior written permi=
ssion.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of th=
e
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the imp=
lied
+ * warranties of merchantability and fitness for a particular purpose ar=
e
+ * disclaimed. In no event shall Freescale Semiconductor be liable for a=
ny
+ * direct, indirect, incidental, special, exemplary, or consequential da=
mages
+ * (including, but not limited to, procurement of substitute goods or se=
rvices;
+ * loss of use, data, or profits; or business interruption) however caus=
ed and
+ * on any theory of liability, whether in contract, strict liability, or=
tort
+ * (including negligence or otherwise) arising in any way out of the use=
of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/p5040si-pre.dtsi"
+
+/ {
+ model =3D "fsl,P5040DS";
+ compatible =3D "fsl,P5040DS";
+ #address-cells =3D <2>;
+ #size-cells =3D <2>;
+ interrupt-parent =3D <&mpic>;
+
+ memory {
+ device_type =3D "memory";
+ };
+
+ dcsr: dcsr@f00000000 {
+ ranges =3D <0x00000000 0xf 0x00000000 0x01008000>;
+ };
+
+ soc: soc@ffe000000 {
+ ranges =3D <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg =3D <0xf 0xfe000000 0 0x00001000>;
+ spi@110000 {
+ flash@0 {
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ compatible =3D "spansion,s25sl12801";
+ reg =3D <0>;
+ spi-max-frequency =3D <40000000>; /* input clock */
+ partition@u-boot {
+ label =3D "u-boot";
+ reg =3D <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition@kernel {
+ label =3D "kernel";
+ reg =3D <0x00100000 0x00500000>;
+ read-only;
+ };
+ partition@dtb {
+ label =3D "dtb";
+ reg =3D <0x00600000 0x00100000>;
+ read-only;
+ };
+ partition@fs {
+ label =3D "file system";
+ reg =3D <0x00700000 0x00900000>;
+ };
+ };
+ };
+
+ i2c@118100 {
+ eeprom@51 {
+ compatible =3D "at24,24c256";
+ reg =3D <0x51>;
+ };
+ eeprom@52 {
+ compatible =3D "at24,24c256";
+ reg =3D <0x52>;
+ };
+ };
+
+ i2c@119100 {
+ rtc@68 {
+ compatible =3D "dallas,ds3232";
+ reg =3D <0x68>;
+ interrupts =3D <0x1 0x1 0 0>;
+ };
+ };
+ };
+
+ lbc: localbus@ffe124000 {
+ reg =3D <0xf 0xfe124000 0 0x1000>;
+ ranges =3D <0 0 0xf 0xe8000000 0x08000000
+ 2 0 0xf 0xffa00000 0x00040000
+ 3 0 0xf 0xffdf0000 0x00008000>;
+
+ flash@0,0 {
+ compatible =3D "cfi-flash";
+ reg =3D <0 0 0x08000000>;
+ bank-width =3D <2>;
+ device-width =3D <2>;
+ };
+
+ nand@2,0 {
+ #address-cells =3D <1>;
+ #size-cells =3D <1>;
+ compatible =3D "fsl,elbc-fcm-nand";
+ reg =3D <0x2 0x0 0x40000>;
+
+ partition@0 {
+ label =3D "NAND U-Boot Image";
+ reg =3D <0x0 0x02000000>;
+ read-only;
+ };
+
+ partition@2000000 {
+ label =3D "NAND Root File System";
+ reg =3D <0x02000000 0x10000000>;
+ };
+
+ partition@12000000 {
+ label =3D "NAND Compressed RFS Image";
+ reg =3D <0x12000000 0x08000000>;
+ };
+
+ partition@1a000000 {
+ label =3D "NAND Linux Kernel Image";
+ reg =3D <0x1a000000 0x04000000>;
+ };
+
+ partition@1e000000 {
+ label =3D "NAND DTB Image";
+ reg =3D <0x1e000000 0x01000000>;
+ };
+
+ partition@1f000000 {
+ label =3D "NAND Writable User area";
+ reg =3D <0x1f000000 0x01000000>;
+ };
+ };
+
+ board-control@3,0 {
+ compatible =3D "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
+ reg =3D <3 0 0x40>;
+ };
+ };
+
+ pci0: pcie@ffe200000 {
+ reg =3D <0xf 0xfe200000 0 0x1000>;
+ ranges =3D <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+ pcie@0 {
+ ranges =3D <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie@ffe201000 {
+ reg =3D <0xf 0xfe201000 0 0x1000>;
+ ranges =3D <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+ pcie@0 {
+ ranges =3D <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie@ffe202000 {
+ reg =3D <0xf 0xfe202000 0 0x1000>;
+ ranges =3D <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+ pcie@0 {
+ ranges =3D <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+};
+
+/include/ "fsl/p5040si-post.dtsi"
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/=
configs/corenet32_smp_defconfig
index cbb98c1..3b40015 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -25,6 +25,7 @@ CONFIG_P2041_RDB=3Dy
CONFIG_P3041_DS=3Dy
CONFIG_P4080_DS=3Dy
CONFIG_P5020_DS=3Dy
+CONFIG_P5040_DS=3Dy
CONFIG_HIGHMEM=3Dy
CONFIG_NO_HZ=3Dy
CONFIG_HIGH_RES_TIMERS=3Dy
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/=
configs/corenet64_smp_defconfig
index dd89de8..36df45b 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -23,6 +23,7 @@ CONFIG_MODVERSIONS=3Dy
CONFIG_PARTITION_ADVANCED=3Dy
CONFIG_MAC_PARTITION=3Dy
CONFIG_P5020_DS=3Dy
+CONFIG_P5040_DS=3Dy
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
CONFIG_BINFMT_MISC=3Dm
CONFIG_IRQ_ALL_CPUS=3Dy
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms=
/85xx/Kconfig
index 159c01e..31f0618 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -254,6 +254,20 @@ config P5020_DS
help
This option enables support for the P5020 DS board
=20
+config P5040_DS
+ bool "Freescale P5040 DS"
+ select DEFAULT_UIMAGE
+ select E500
+ select PPC_E500MC
+ select PHYS_64BIT
+ select SWIOTLB
+ select ARCH_REQUIRE_GPIOLIB
+ select GPIO_MPC8XXX
+ select HAS_RAPIDIO
+ select PPC_EPAPR_HV_PIC
+ help
+ This option enables support for the P5040 DS board
+
config PPC_QEMU_E500
bool "QEMU generic e500 platform"
depends on EXPERIMENTAL
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platform=
s/85xx/Makefile
index 3dfe811..d99268a 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_P2041_RDB) +=3D p2041_rdb.o corenet_ds.o
obj-$(CONFIG_P3041_DS) +=3D p3041_ds.o corenet_ds.o
obj-$(CONFIG_P4080_DS) +=3D p4080_ds.o corenet_ds.o
obj-$(CONFIG_P5020_DS) +=3D p5020_ds.o corenet_ds.o
+obj-$(CONFIG_P5040_DS) +=3D p5040_ds.o corenet_ds.o
obj-$(CONFIG_STX_GP3) +=3D stx_gp3.o
obj-$(CONFIG_TQM85xx) +=3D tqm85xx.o
obj-$(CONFIG_SBC8548) +=3D sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platfo=
rms/85xx/p5040_ds.c
new file mode 100644
index 0000000..ca3358f
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p5040_ds.c
@@ -0,0 +1,96 @@
+/*
+ * P5040 DS Setup
+ *
+ * Copyright 2009-2010 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify=
it
+ * under the terms of the GNU General Public License as published by =
the
+ * Free Software Foundation; either version 2 of the License, or (at y=
our
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p5040_ds_probe(void)
+{
+ unsigned long root =3D of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+ extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+ if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
+ return 1;
+
+ /* Check if we're running under the Freescale hypervisor */
+ if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
+ ppc_md.init_IRQ =3D ehv_pic_init;
+ ppc_md.get_irq =3D ehv_pic_get_irq;
+ ppc_md.restart =3D fsl_hv_restart;
+ ppc_md.power_off =3D fsl_hv_halt;
+ ppc_md.halt =3D fsl_hv_halt;
+#ifdef CONFIG_SMP
+ /*
+ * Disable the timebase sync operations because we can't write
+ * to the timebase registers under the hypervisor.
+ */
+ smp_85xx_ops.give_timebase =3D NULL;
+ smp_85xx_ops.take_timebase =3D NULL;
+#endif
+ return 1;
+ }
+
+ return 0;
+}
+
+define_machine(p5040_ds) {
+ .name =3D "P5040 DS",
+ .probe =3D p5040_ds_probe,
+ .setup_arch =3D corenet_ds_setup_arch,
+ .init_IRQ =3D corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus =3D fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+ .get_irq =3D mpic_get_irq,
+#else
+ .get_irq =3D mpic_get_coreint_irq,
+#endif
+ .restart =3D fsl_rstcr_restart,
+ .calibrate_decr =3D generic_calibrate_decr,
+ .progress =3D udbg_progress,
+#ifdef CONFIG_PPC64
+ .power_save =3D book3e_idle,
+#else
+ .power_save =3D e500_idle,
+#endif
+};
+
+machine_device_initcall(p5040_ds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
+#endif
--=20
1.7.3.4
^ permalink raw reply related
* [PATCH] [v2] powerpc/p5040ds: Add support for P5040DS board
From: Timur Tabi @ 2012-07-24 16:56 UTC (permalink / raw)
To: Kumar Gala, linuxppc-dev
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support
Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA
Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
---
v2: remove extended character from patch description so patch is not mime-encoded
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 320 +++++++++++++++++++++++++
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 111 +++++++++
arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi | 118 +++++++++
arch/powerpc/boot/dts/p5040ds.dts | 207 ++++++++++++++++
arch/powerpc/configs/corenet32_smp_defconfig | 1 +
arch/powerpc/configs/corenet64_smp_defconfig | 1 +
arch/powerpc/platforms/85xx/Kconfig | 14 +
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/p5040_ds.c | 96 ++++++++
9 files changed, 869 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
create mode 100644 arch/powerpc/boot/dts/p5040ds.dts
create mode 100644 arch/powerpc/platforms/85xx/p5040_ds.c
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
new file mode 100644
index 0000000..cc1e606
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -0,0 +1,320 @@
+/*
+ * P5040 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+&lbc {
+ compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
+ interrupts = <25 2 0 0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+};
+
+/* controller at 0x200000 */
+&pci0 {
+ compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <33333333>;
+ interrupts = <16 2 1 15>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 15>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ };
+};
+
+/* controller at 0x201000 */
+&pci1 {
+ compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0 0xff>;
+ clock-frequency = <33333333>;
+ interrupts = <16 2 1 14>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 14>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 41 1 0 0
+ 0000 0 0 2 &mpic 5 1 0 0
+ 0000 0 0 3 &mpic 6 1 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ };
+};
+
+/* controller at 0x202000 */
+&pci2 {
+ compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ clock-frequency = <33333333>;
+ interrupts = <16 2 1 13>;
+ pcie@0 {
+ reg = <0 0 0 0 0>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <16 2 1 13>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 42 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 1 0 0
+ >;
+ };
+};
+
+&dcsr {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+
+ dcsr-epu@0 {
+ compatible = "fsl,dcsr-epu";
+ interrupts = <52 2 0 0
+ 84 2 0 0
+ 85 2 0 0>;
+ reg = <0x0 0x1000>;
+ };
+ dcsr-npc {
+ compatible = "fsl,dcsr-npc";
+ reg = <0x1000 0x1000 0x1000000 0x8000>;
+ };
+ dcsr-nxc@2000 {
+ compatible = "fsl,dcsr-nxc";
+ reg = <0x2000 0x1000>;
+ };
+ dcsr-corenet {
+ compatible = "fsl,dcsr-corenet";
+ reg = <0x8000 0x1000 0xB0000 0x1000>;
+ };
+ dcsr-dpaa@9000 {
+ compatible = "fsl,p5040-dcsr-dpaa", "fsl,dcsr-dpaa";
+ reg = <0x9000 0x1000>;
+ };
+ dcsr-ocn@11000 {
+ compatible = "fsl,p5040-dcsr-ocn", "fsl,dcsr-ocn";
+ reg = <0x11000 0x1000>;
+ };
+ dcsr-ddr@12000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr1>;
+ reg = <0x12000 0x1000>;
+ };
+ dcsr-ddr@13000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr2>;
+ reg = <0x13000 0x1000>;
+ };
+ dcsr-nal@18000 {
+ compatible = "fsl,p5040-dcsr-nal", "fsl,dcsr-nal";
+ reg = <0x18000 0x1000>;
+ };
+ dcsr-rcpm@22000 {
+ compatible = "fsl,p5040-dcsr-rcpm", "fsl,dcsr-rcpm";
+ reg = <0x22000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@40000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu0>;
+ reg = <0x40000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@41000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu1>;
+ reg = <0x41000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@42000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu2>;
+ reg = <0x42000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@43000 {
+ compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu3>;
+ reg = <0x43000 0x1000>;
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law@0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ ddr1: memory-controller@8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ ddr2: memory-controller@9000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
+ reg = <0x9000 0x1000>;
+ interrupts = <16 2 1 22>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,p5040-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000
+ 0x11000 0x1000>;
+ interrupts = <16 2 1 27
+ 16 2 1 26>;
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu@20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x5000>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ };
+
+/include/ "qoriq-mpic.dtsi"
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,qoriq-device-config-1.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ #sleep-cells = <1>;
+ fsl,liodn-bits = <12>;
+ };
+
+ pins: global-utilities@e0e00 {
+ compatible = "fsl,qoriq-pin-control-1.0";
+ reg = <0xe0e00 0x200>;
+ #sleep-cells = <2>;
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ };
+
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,qoriq-rcpm-1.0";
+ reg = <0xe2000 0x1000>;
+ #sleep-cells = <1>;
+ };
+
+ sfp: sfp@e8000 {
+ compatible = "fsl,p5040-sfp", "fsl,qoriq-sfp-1.0";
+ reg = <0xe8000 0x1000>;
+ };
+
+ serdes: serdes@ea000 {
+ compatible = "fsl,p5040-serdes";
+ reg = <0xea000 0x1000>;
+ };
+
+/include/ "qoriq-dma-0.dtsi"
+/include/ "qoriq-dma-1.dtsi"
+/include/ "qoriq-espi-0.dtsi"
+ spi@110000 {
+ fsl,espi-num-chipselects = <4>;
+ };
+
+/include/ "qoriq-esdhc-0.dtsi"
+ sdhc@114000 {
+ sdhci,auto-cmd12;
+ };
+
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-usb2-mph-0.dtsi"
+ usb0: usb@210000 {
+ compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+ phy_type = "utmi";
+ port0;
+ };
+
+/include/ "qoriq-usb2-dr-0.dtsi"
+ usb1: usb@211000 {
+ compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+ dr_mode = "host";
+ phy_type = "utmi";
+ };
+
+/include/ "qoriq-sata2-0.dtsi"
+/include/ "qoriq-sata2-1.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
+};
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
new file mode 100644
index 0000000..52721b6
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -0,0 +1,111 @@
+/*
+ * P5040 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+/ {
+ compatible = "fsl,P5040";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+ dcsr = &dcsr;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ sdhc = &sdhc;
+ msi0 = &msi0;
+ msi1 = &msi1;
+ msi2 = &msi2;
+
+ crypto = &crypto;
+ sec_jr0 = &sec_jr0;
+ sec_jr1 = &sec_jr1;
+ sec_jr2 = &sec_jr2;
+ sec_jr3 = &sec_jr3;
+ rtic_a = &rtic_a;
+ rtic_b = &rtic_b;
+ rtic_c = &rtic_c;
+ rtic_d = &rtic_d;
+ sec_mon = &sec_mon;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e5500@0 {
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu1: PowerPC,e5500@1 {
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2_1>;
+ L2_1: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu2: PowerPC,e5500@2 {
+ device_type = "cpu";
+ reg = <2>;
+ next-level-cache = <&L2_2>;
+ L2_2: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ cpu3: PowerPC,e5500@3 {
+ device_type = "cpu";
+ reg = <3>;
+ next-level-cache = <&L2_3>;
+ L2_3: l2-cache {
+ next-level-cache = <&cpc>;
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
new file mode 100644
index 0000000..7b2ab8a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
@@ -0,0 +1,118 @@
+/*
+ * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+crypto: crypto@300000 {
+ compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v5.2-job-ring",
+ "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v5.2-rtic",
+ "fsl,sec-v5.0-rtic",
+ "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v5.2-rtic-memory",
+ "fsl,sec-v5.0-rtic-memory",
+ "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/p5040ds.dts b/arch/powerpc/boot/dts/p5040ds.dts
new file mode 100644
index 0000000..c15ba68
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5040ds.dts
@@ -0,0 +1,207 @@
+/*
+ * P5040DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/p5040si-pre.dtsi"
+
+/ {
+ model = "fsl,P5040DS";
+ compatible = "fsl,P5040DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ memory {
+ device_type = "memory";
+ };
+
+ dcsr: dcsr@f00000000 {
+ ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ spi@110000 {
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,s25sl12801";
+ reg = <0>;
+ spi-max-frequency = <40000000>; /* input clock */
+ partition@u-boot {
+ label = "u-boot";
+ reg = <0x00000000 0x00100000>;
+ read-only;
+ };
+ partition@kernel {
+ label = "kernel";
+ reg = <0x00100000 0x00500000>;
+ read-only;
+ };
+ partition@dtb {
+ label = "dtb";
+ reg = <0x00600000 0x00100000>;
+ read-only;
+ };
+ partition@fs {
+ label = "file system";
+ reg = <0x00700000 0x00900000>;
+ };
+ };
+ };
+
+ i2c@118100 {
+ eeprom@51 {
+ compatible = "at24,24c256";
+ reg = <0x51>;
+ };
+ eeprom@52 {
+ compatible = "at24,24c256";
+ reg = <0x52>;
+ };
+ };
+
+ i2c@119100 {
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ interrupts = <0x1 0x1 0 0>;
+ };
+ };
+ };
+
+ lbc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x1000>;
+ ranges = <0 0 0xf 0xe8000000 0x08000000
+ 2 0 0xf 0xffa00000 0x00040000
+ 3 0 0xf 0xffdf0000 0x00008000>;
+
+ flash@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0 0x08000000>;
+ bank-width = <2>;
+ device-width = <2>;
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ partition@0 {
+ label = "NAND U-Boot Image";
+ reg = <0x0 0x02000000>;
+ read-only;
+ };
+
+ partition@2000000 {
+ label = "NAND Root File System";
+ reg = <0x02000000 0x10000000>;
+ };
+
+ partition@12000000 {
+ label = "NAND Compressed RFS Image";
+ reg = <0x12000000 0x08000000>;
+ };
+
+ partition@1a000000 {
+ label = "NAND Linux Kernel Image";
+ reg = <0x1a000000 0x04000000>;
+ };
+
+ partition@1e000000 {
+ label = "NAND DTB Image";
+ reg = <0x1e000000 0x01000000>;
+ };
+
+ partition@1f000000 {
+ label = "NAND Writable User area";
+ reg = <0x1f000000 0x01000000>;
+ };
+ };
+
+ board-control@3,0 {
+ compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
+ reg = <3 0 0x40>;
+ };
+ };
+
+ pci0: pcie@ffe200000 {
+ reg = <0xf 0xfe200000 0 0x1000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie@ffe201000 {
+ reg = <0xf 0xfe201000 0 0x1000>;
+ ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie@ffe202000 {
+ reg = <0xf 0xfe202000 0 0x1000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+};
+
+/include/ "fsl/p5040si-post.dtsi"
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index cbb98c1..3b40015 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -25,6 +25,7 @@ CONFIG_P2041_RDB=y
CONFIG_P3041_DS=y
CONFIG_P4080_DS=y
CONFIG_P5020_DS=y
+CONFIG_P5040_DS=y
CONFIG_HIGHMEM=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index dd89de8..36df45b 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -23,6 +23,7 @@ CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
CONFIG_P5020_DS=y
+CONFIG_P5040_DS=y
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
CONFIG_BINFMT_MISC=m
CONFIG_IRQ_ALL_CPUS=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 159c01e..31f0618 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -254,6 +254,20 @@ config P5020_DS
help
This option enables support for the P5020 DS board
+config P5040_DS
+ bool "Freescale P5040 DS"
+ select DEFAULT_UIMAGE
+ select E500
+ select PPC_E500MC
+ select PHYS_64BIT
+ select SWIOTLB
+ select ARCH_REQUIRE_GPIOLIB
+ select GPIO_MPC8XXX
+ select HAS_RAPIDIO
+ select PPC_EPAPR_HV_PIC
+ help
+ This option enables support for the P5040 DS board
+
config PPC_QEMU_E500
bool "QEMU generic e500 platform"
depends on EXPERIMENTAL
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 3dfe811..d99268a 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
+obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
obj-$(CONFIG_STX_GP3) += stx_gp3.o
obj-$(CONFIG_TQM85xx) += tqm85xx.o
obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
new file mode 100644
index 0000000..ca3358f
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p5040_ds.c
@@ -0,0 +1,96 @@
+/*
+ * P5040 DS Setup
+ *
+ * Copyright 2009-2010 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p5040_ds_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+ extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+ if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
+ return 1;
+
+ /* Check if we're running under the Freescale hypervisor */
+ if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
+ ppc_md.init_IRQ = ehv_pic_init;
+ ppc_md.get_irq = ehv_pic_get_irq;
+ ppc_md.restart = fsl_hv_restart;
+ ppc_md.power_off = fsl_hv_halt;
+ ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+ /*
+ * Disable the timebase sync operations because we can't write
+ * to the timebase registers under the hypervisor.
+ */
+ smp_85xx_ops.give_timebase = NULL;
+ smp_85xx_ops.take_timebase = NULL;
+#endif
+ return 1;
+ }
+
+ return 0;
+}
+
+define_machine(p5040_ds) {
+ .name = "P5040 DS",
+ .probe = p5040_ds_probe,
+ .setup_arch = corenet_ds_setup_arch,
+ .init_IRQ = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+ .get_irq = mpic_get_irq,
+#else
+ .get_irq = mpic_get_coreint_irq,
+#endif
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+#ifdef CONFIG_PPC64
+ .power_save = book3e_idle,
+#else
+ .power_save = e500_idle,
+#endif
+};
+
+machine_device_initcall(p5040_ds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
+#endif
--
1.7.3.4
^ permalink raw reply related
* Re: [PATCH] powerpc/p5040ds: Add support for P5040DS board
From: Scott Wood @ 2012-07-24 17:56 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev
In-Reply-To: <1343148122-4584-1-git-send-email-timur@freescale.com>
On 07/24/2012 11:42 AM, Timur Tabi wrote:
> +/* controller at 0x200000 */
> +&pci0 {
> + compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
p5040 has PCIe v2.4.
Note that there is a version register, so perhaps we should drop the
version number from the compatible (and mention the version register in
the binding).
Might want to double check the other version numbers in this file too.
> + bus-range = <0x0 0xff>;
Do we really need this?
> + clock-frequency = <33333333>;
I doubt this is accurate.
> + iommu@20000 {
> + compatible = "fsl,pamu-v1.0", "fsl,pamu";
> + reg = <0x20000 0x5000>;
> + interrupts = <
> + 24 2 0 0
> + 16 2 1 30>;
> + };
It's PAMU v1.1, and there's a version register.
> +/include/ "qoriq-mpic.dtsi"
> +
> + guts: global-utilities@e0000 {
> + compatible = "fsl,qoriq-device-config-1.0";
> + reg = <0xe0000 0xe00>;
> + fsl,has-rstcr;
> + #sleep-cells = <1>;
> + fsl,liodn-bits = <12>;
> + };
> +
> + pins: global-utilities@e0e00 {
> + compatible = "fsl,qoriq-pin-control-1.0";
> + reg = <0xe0e00 0x200>;
> + #sleep-cells = <2>;
> + };
Please add fsl,p5040-device-config and fsl,p5040-pin-control. If you
want to leave the "1.0" thing in (which was a mistake since this stuff
doesn't seem to be versioned in any public way), double check that it's
100% backwards compatible with p4080.
> + rcpm: global-utilities@e2000 {
> + compatible = "fsl,qoriq-rcpm-1.0";
> + reg = <0xe2000 0x1000>;
> + #sleep-cells = <1>;
> + };
Likewise.
> +/dts-v1/;
> +/ {
> + compatible = "fsl,P5040";
When would we not override this?
> + spi@110000 {
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spansion,s25sl12801";
> + reg = <0>;
> + spi-max-frequency = <40000000>; /* input clock */
> + partition@u-boot {
> + label = "u-boot";
> + reg = <0x00000000 0x00100000>;
> + read-only;
> + };
> + partition@kernel {
> + label = "kernel";
> + reg = <0x00100000 0x00500000>;
> + read-only;
> + };
> + partition@dtb {
> + label = "dtb";
> + reg = <0x00600000 0x00100000>;
> + read-only;
> + };
> + partition@fs {
> + label = "file system";
> + reg = <0x00700000 0x00900000>;
> + };
Why are kernel/dtb read only?
> + flash@0,0 {
> + compatible = "cfi-flash";
> + reg = <0 0 0x08000000>;
> + bank-width = <2>;
> + device-width = <2>;
> + };
No partitions on NOR flash?
> + partition@2000000 {
> + label = "NAND Root File System";
> + reg = <0x02000000 0x10000000>;
> + };
> +
> + partition@12000000 {
> + label = "NAND Compressed RFS Image";
> + reg = <0x12000000 0x08000000>;
> + };
Why do we need both of these? Why not one big partition for whichever
type of RFS you have?
> diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
> new file mode 100644
> index 0000000..ca3358f
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/p5040_ds.c
> @@ -0,0 +1,96 @@
> +/*
> + * P5040 DS Setup
> + *
> + * Copyright 2009-2010 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/phy.h>
> +
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/pci-bridge.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <linux/of_platform.h>
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +#include <asm/ehv_pic.h>
> +
> +#include "corenet_ds.h"
Do you really need all these? kdev_t? phy?
> +
> +/*
> + * Called very early, device-tree isn't unflattened
> + */
> +static int __init p5040_ds_probe(void)
> +{
> + unsigned long root = of_get_flat_dt_root();
> +#ifdef CONFIG_SMP
> + extern struct smp_ops_t smp_85xx_ops;
> +#endif
> +
> + if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
> + return 1;
> +
> + /* Check if we're running under the Freescale hypervisor */
> + if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
> + ppc_md.init_IRQ = ehv_pic_init;
> + ppc_md.get_irq = ehv_pic_get_irq;
> + ppc_md.restart = fsl_hv_restart;
> + ppc_md.power_off = fsl_hv_halt;
> + ppc_md.halt = fsl_hv_halt;
> +#ifdef CONFIG_SMP
> + /*
> + * Disable the timebase sync operations because we can't write
> + * to the timebase registers under the hypervisor.
> + */
> + smp_85xx_ops.give_timebase = NULL;
> + smp_85xx_ops.take_timebase = NULL;
> +#endif
Why are they getting set in the first place?
While you're at it, you might want to look into converting corenet_ds to
the new PCI init code.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/p5040ds: Add support for P5040DS board
From: Timur Tabi @ 2012-07-24 18:09 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <500EE1BB.6060104@freescale.com>
Scott Wood wrote:
> On 07/24/2012 11:42 AM, Timur Tabi wrote:
>> +/* controller at 0x200000 */
>> +&pci0 {
>> + compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
>
> p5040 has PCIe v2.4.
Then it's broken on the SDK as well.
> Note that there is a version register, so perhaps we should drop the
> version number from the compatible (and mention the version register in
> the binding).
>
> Might want to double check the other version numbers in this file too.
>
>> + bus-range = <0x0 0xff>;
>
> Do we really need this?
>
>> + clock-frequency = <33333333>;
>
> I doubt this is accurate.
Almost all of this is copy-paste from the P5020, so if it's broken here,
it's either broken on the P5020 or also broken on the SDK.
>> + iommu@20000 {
>> + compatible = "fsl,pamu-v1.0", "fsl,pamu";
>> + reg = <0x20000 0x5000>;
>> + interrupts = <
>> + 24 2 0 0
>> + 16 2 1 30>;
>> + };
>
> It's PAMU v1.1, and there's a version register.
Also broken in the SDK. :-(
>> +/include/ "qoriq-mpic.dtsi"
>> +
>> + guts: global-utilities@e0000 {
>> + compatible = "fsl,qoriq-device-config-1.0";
>> + reg = <0xe0000 0xe00>;
>> + fsl,has-rstcr;
>> + #sleep-cells = <1>;
>> + fsl,liodn-bits = <12>;
>> + };
>> +
>> + pins: global-utilities@e0e00 {
>> + compatible = "fsl,qoriq-pin-control-1.0";
>> + reg = <0xe0e00 0x200>;
>> + #sleep-cells = <2>;
>> + };
>
> Please add fsl,p5040-device-config and fsl,p5040-pin-control. If you
> want to leave the "1.0" thing in (which was a mistake since this stuff
> doesn't seem to be versioned in any public way), double check that it's
> 100% backwards compatible with p4080.
Ok.
>> + rcpm: global-utilities@e2000 {
>> + compatible = "fsl,qoriq-rcpm-1.0";
>> + reg = <0xe2000 0x1000>;
>> + #sleep-cells = <1>;
>> + };
>
> Likewise.
>
>> +/dts-v1/;
>> +/ {
>> + compatible = "fsl,P5040";
>
> When would we not override this?
I don't understand.
>> + spi@110000 {
>> + flash@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "spansion,s25sl12801";
>> + reg = <0>;
>> + spi-max-frequency = <40000000>; /* input clock */
>> + partition@u-boot {
>> + label = "u-boot";
>> + reg = <0x00000000 0x00100000>;
>> + read-only;
>> + };
>> + partition@kernel {
>> + label = "kernel";
>> + reg = <0x00100000 0x00500000>;
>> + read-only;
>> + };
>> + partition@dtb {
>> + label = "dtb";
>> + reg = <0x00600000 0x00100000>;
>> + read-only;
>> + };
>> + partition@fs {
>> + label = "file system";
>> + reg = <0x00700000 0x00900000>;
>> + };
>
> Why are kernel/dtb read only?
Because that's how it is on the P5020!
I'm surprised the P5020 DTS files are so broken.
>> + flash@0,0 {
>> + compatible = "cfi-flash";
>> + reg = <0 0 0x08000000>;
>> + bank-width = <2>;
>> + device-width = <2>;
>> + };
>
> No partitions on NOR flash?
I'll check.
>> + partition@2000000 {
>> + label = "NAND Root File System";
>> + reg = <0x02000000 0x10000000>;
>> + };
>> +
>> + partition@12000000 {
>> + label = "NAND Compressed RFS Image";
>> + reg = <0x12000000 0x08000000>;
>> + };
>
> Why do we need both of these? Why not one big partition for whichever
> type of RFS you have?
Beats me. Like I said, I just copied them over. I know that's bad, but
the source files have been around for quite some time, so I'm surprised
they're still all broken.
>> diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
>> new file mode 100644
>> index 0000000..ca3358f
>> --- /dev/null
>> +++ b/arch/powerpc/platforms/85xx/p5040_ds.c
>> @@ -0,0 +1,96 @@
>> +/*
>> + * P5040 DS Setup
>> + *
>> + * Copyright 2009-2010 Freescale Semiconductor Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License as published by the
>> + * Free Software Foundation; either version 2 of the License, or (at your
>> + * option) any later version.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/pci.h>
>> +#include <linux/kdev_t.h>
>> +#include <linux/delay.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/phy.h>
>> +
>> +#include <asm/time.h>
>> +#include <asm/machdep.h>
>> +#include <asm/pci-bridge.h>
>> +#include <mm/mmu_decl.h>
>> +#include <asm/prom.h>
>> +#include <asm/udbg.h>
>> +#include <asm/mpic.h>
>> +
>> +#include <linux/of_platform.h>
>> +#include <sysdev/fsl_soc.h>
>> +#include <sysdev/fsl_pci.h>
>> +#include <asm/ehv_pic.h>
>> +
>> +#include "corenet_ds.h"
>
> Do you really need all these? kdev_t? phy?
Probably not.
>> +
>> +/*
>> + * Called very early, device-tree isn't unflattened
>> + */
>> +static int __init p5040_ds_probe(void)
>> +{
>> + unsigned long root = of_get_flat_dt_root();
>> +#ifdef CONFIG_SMP
>> + extern struct smp_ops_t smp_85xx_ops;
>> +#endif
>> +
>> + if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
>> + return 1;
>> +
>> + /* Check if we're running under the Freescale hypervisor */
>> + if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
>> + ppc_md.init_IRQ = ehv_pic_init;
>> + ppc_md.get_irq = ehv_pic_get_irq;
>> + ppc_md.restart = fsl_hv_restart;
>> + ppc_md.power_off = fsl_hv_halt;
>> + ppc_md.halt = fsl_hv_halt;
>> +#ifdef CONFIG_SMP
>> + /*
>> + * Disable the timebase sync operations because we can't write
>> + * to the timebase registers under the hypervisor.
>> + */
>> + smp_85xx_ops.give_timebase = NULL;
>> + smp_85xx_ops.take_timebase = NULL;
>> +#endif
>
> Why are they getting set in the first place?
This is how the structure is defined in smp.c:
struct smp_ops_t smp_85xx_ops = {
.kick_cpu = smp_85xx_kick_cpu,
#ifdef CONFIG_KEXEC
.give_timebase = smp_generic_give_timebase,
.take_timebase = smp_generic_take_timebase,
#endif
};
This code has not changed in years. I'm not sure what you think is wrong
with it.
> While you're at it, you might want to look into converting corenet_ds to
> the new PCI init code.
Well, I just want to get this out the door.
>
> -Scott
>
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: [PATCH] powerpc/p5040ds: Add support for P5040DS board
From: Scott Wood @ 2012-07-24 18:32 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev
In-Reply-To: <500EE4C3.40707@freescale.com>
On 07/24/2012 01:09 PM, Timur Tabi wrote:
> Scott Wood wrote:
>> On 07/24/2012 11:42 AM, Timur Tabi wrote:
>>> +/* controller at 0x200000 */
>>> +&pci0 {
>>> + compatible = "fsl,p5040-pcie", "fsl,qoriq-pcie-v2.2";
>>
>> p5040 has PCIe v2.4.
>
> Then it's broken on the SDK as well.
Yes. There was internal discussion about this over the last few days.
>> Note that there is a version register, so perhaps we should drop the
>> version number from the compatible (and mention the version register in
>> the binding).
>>
>> Might want to double check the other version numbers in this file too.
>>
>>> + bus-range = <0x0 0xff>;
>>
>> Do we really need this?
>>
>>> + clock-frequency = <33333333>;
>>
>> I doubt this is accurate.
>
> Almost all of this is copy-paste from the P5020, so if it's broken here,
> it's either broken on the P5020 or also broken on the SDK.
Now's as good a time as any to fix it.
>>> +/dts-v1/;
>>> +/ {
>>> + compatible = "fsl,P5040";
>>
>> When would we not override this?
>
> I don't understand.
I was wondering why we put these chip-based toplevel compatibles in the
dtsi, when we'll always overwrite it with a board-based toplevel compatible.
>>> + spi@110000 {
>>> + flash@0 {
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + compatible = "spansion,s25sl12801";
>>> + reg = <0>;
>>> + spi-max-frequency = <40000000>; /* input clock */
>>> + partition@u-boot {
>>> + label = "u-boot";
>>> + reg = <0x00000000 0x00100000>;
>>> + read-only;
>>> + };
>>> + partition@kernel {
>>> + label = "kernel";
>>> + reg = <0x00100000 0x00500000>;
>>> + read-only;
>>> + };
>>> + partition@dtb {
>>> + label = "dtb";
>>> + reg = <0x00600000 0x00100000>;
>>> + read-only;
>>> + };
>>> + partition@fs {
>>> + label = "file system";
>>> + reg = <0x00700000 0x00900000>;
>>> + };
>>
>> Why are kernel/dtb read only?
>
> Because that's how it is on the P5020!
This is a copy-and-paste meme that I've probably complained about a few
dozen times by now. :-)
>>> +#ifdef CONFIG_SMP
>>> + /*
>>> + * Disable the timebase sync operations because we can't write
>>> + * to the timebase registers under the hypervisor.
>>> + */
>>> + smp_85xx_ops.give_timebase = NULL;
>>> + smp_85xx_ops.take_timebase = NULL;
>>> +#endif
>>
>> Why are they getting set in the first place?
>
> This is how the structure is defined in smp.c:
>
> struct smp_ops_t smp_85xx_ops = {
> .kick_cpu = smp_85xx_kick_cpu,
> #ifdef CONFIG_KEXEC
> .give_timebase = smp_generic_give_timebase,
> .take_timebase = smp_generic_take_timebase,
> #endif
> };
>
> This code has not changed in years.
There was a patch to fix this, but I guess it hasn't been merged yet.
> I'm not sure what you think is wrong
> with it.
We should never be using smp_generic_take/give_timebase. We have a
better way of synchronizing for the few cases where we need to.
-Scott
^ permalink raw reply
* Re: [PATCH 1/6] powerpc/fsl-pci: Unify pci/pcie initialization code
From: Scott Wood @ 2012-07-24 18:42 UTC (permalink / raw)
To: Jia Hongtao; +Cc: B07421, linuxppc-dev
In-Reply-To: <1343125210-16720-1-git-send-email-B38951@freescale.com>
On 07/24/2012 05:20 AM, Jia Hongtao wrote:
> We unified the Freescale pci/pcie initialization by changing the fsl_pci
> to a platform driver.
>
> In previous version pci/pcie initialization is in platform code which
> Initialize pci bridge base on EP/RC or host/agent settings.
The previous version of what? This patch, or the PCI code? What
changed in this patch since the last time you sent it, and where is the
version number?
> +#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
> +static const struct of_device_id pci_ids[] = {
> + { .compatible = "fsl,mpc8540-pci", },
> + { .compatible = "fsl,mpc8548-pcie", },
> + { .compatible = "fsl,mpc8641-pcie", },
> + { .compatible = "fsl,p1022-pcie", },
> + { .compatible = "fsl,p1010-pcie", },
> + { .compatible = "fsl,p1023-pcie", },
> + { .compatible = "fsl,p4080-pcie", },
> + { .compatible = "fsl,qoriq-pcie-v2.3", },
> + { .compatible = "fsl,qoriq-pcie-v2.2", },
> + {},
> +};
Again, please base this on the latest tree, which has my PCI patches.
This table already exists in this file. And you're still missing
fsl,mpc8610-pci.
> +int primary_phb_addr;
> +static int __devinit fsl_pci_probe(struct platform_device *pdev)
> +{
> + struct pci_controller *hose;
> + bool is_primary;
> +
> + if (of_match_node(pci_ids, pdev->dev.of_node)) {
> + struct resource rsrc;
> + of_address_to_resource(pdev->dev.of_node, 0, &rsrc);
> + is_primary = ((rsrc.start & 0xfffff) == primary_phb_addr);
> + fsl_add_bridge(pdev->dev.of_node, is_primary);
> +
> +#ifdef CONFIG_SWIOTLB
> + hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
> + /*
> + * if we couldn't map all of DRAM via the dma windows
> + * we need SWIOTLB to handle buffers located outside of
> + * dma capable memory region
> + */
> + if (memblock_end_of_DRAM() > hose->dma_window_base_cur
> + + hose->dma_window_size) {
> + ppc_swiotlb_enable = 1;
> + set_pci_dma_ops(&swiotlb_dma_ops);
> + ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
> + }
> +#endif
> + }
It's too late for swiotlb here. Again, please don't break something in
one patch and then fix it in a later patch. Use "git rebase -i" to edit
your patchset into a reviewable, bisectable form.
-Scott
^ permalink raw reply
* Re: [PATCH 3/6] powerpc/fsl-pci: Determine primary bus by looking for ISA node
From: Scott Wood @ 2012-07-24 18:47 UTC (permalink / raw)
To: Jia Hongtao; +Cc: B07421, linuxppc-dev
In-Reply-To: <1343125210-16720-3-git-send-email-B38951@freescale.com>
On 07/24/2012 05:20 AM, Jia Hongtao wrote:
> PCI host bridge is primary bus if it contains an ISA node. But not all boards
> fit this rule. Device tree should be updated for all these boards.
>
> Signed-off-by: Jia Hongtao <B38951@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/include/asm/pci-bridge.h | 1 +
> arch/powerpc/sysdev/fsl_pci.c | 31 ++++++++++++++++++++++++-------
> arch/powerpc/sysdev/fsl_pci.h | 12 +++++++++++-
> 3 files changed, 36 insertions(+), 8 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
> index ac39e6a..b48fa7f 100644
> --- a/arch/powerpc/include/asm/pci-bridge.h
> +++ b/arch/powerpc/include/asm/pci-bridge.h
> @@ -20,6 +20,7 @@ struct device_node;
> struct pci_controller {
> struct pci_bus *bus;
> char is_dynamic;
> + int is_primary;
> #ifdef CONFIG_PPC64
> int node;
> #endif
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index 99a3e78..2a369be 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -453,6 +453,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
>
> hose->first_busno = bus_range ? bus_range[0] : 0x0;
> hose->last_busno = bus_range ? bus_range[1] : 0xff;
> + hose->is_primary = is_primary;
>
> setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> PPC_INDIRECT_TYPE_BIG_ENDIAN);
> @@ -932,18 +933,34 @@ void pci_check_swiotlb(void)
> }
> #endif
>
> -int primary_phb_addr;
> +/*
> + * Recursively scan all the children nodes of parent and find out if there
> + * is "isa" node. Return 1 if parent has isa node otherwise return 0.
> + */
> +int has_isa_node(struct device_node *parent)
> +{
> + static int result;
> + struct device_node *cur_child;
> +
> + cur_child = NULL;
> + result = 0;
> + while (!result && (cur_child = of_get_next_child(parent, cur_child))) {
> + /* Get "isa" node and return 1 */
> + if (of_node_cmp(cur_child->type, "isa") == 0)
> + return result = 1;
> + has_isa_node(cur_child);
> + }
> +
> + return result;
> +}
Why are you reimplementing this? It's already in Linus's tree. See
fsl_pci_init().
Plus, your version is recursive which is unacceptable in kernel code
with a small stack (outside of a few rare examples where the depth has a
small fixed upper bound), and once it finds an ISA node, it returns 1
forever, regardless of what node you pass in in the future.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/p5040ds: Add support for P5040DS board
From: Timur Tabi @ 2012-07-24 18:55 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <500EEA46.6030807@freescale.com>
Scott Wood wrote:
>>>> + compatible = "fsl,P5040";
>>>
>>> When would we not override this?
>>
>> I don't understand.
>
> I was wondering why we put these chip-based toplevel compatibles in the
> dtsi, when we'll always overwrite it with a board-based toplevel compatible.
That's a good point, but I'm loathe to break the current convention. I'd
rather post a patch that removes them from all boards, but I'd like an ACK
from Kumar first.
>>> Why are kernel/dtb read only?
>>
>> Because that's how it is on the P5020!
>
> This is a copy-and-paste meme that I've probably complained about a few
> dozen times by now. :-)
I know, I know, but you would think problems like this would already be
fixed upstream. I didn't think I would need to review every single
property in the P5020 device trees.
>>>> +#ifdef CONFIG_SMP
>>>> + /*
>>>> + * Disable the timebase sync operations because we can't write
>>>> + * to the timebase registers under the hypervisor.
>>>> + */
>>>> + smp_85xx_ops.give_timebase = NULL;
>>>> + smp_85xx_ops.take_timebase = NULL;
>>>> +#endif
>>>
>>> Why are they getting set in the first place?
>>
>> This is how the structure is defined in smp.c:
>>
>> struct smp_ops_t smp_85xx_ops = {
>> .kick_cpu = smp_85xx_kick_cpu,
>> #ifdef CONFIG_KEXEC
>> .give_timebase = smp_generic_give_timebase,
>> .take_timebase = smp_generic_take_timebase,
>> #endif
>> };
>>
>> This code has not changed in years.
>
> There was a patch to fix this, but I guess it hasn't been merged yet.
Can you give me a clue which patch this is, so I can find it on the
mailing list?
>> I'm not sure what you think is wrong
>> with it.
>
> We should never be using smp_generic_take/give_timebase. We have a
> better way of synchronizing for the few cases where we need to.
Ok, I'll match the new paradigm when I find it.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox