* Re: [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2012-10-04 20:10 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, Linux Kernel list
In-Reply-To: <CA+55aFxbzeNG=sAQvPcE56rEpAbACqM04m2s73BzXVgK+PCnaQ@mail.gmail.com>
On Thu, 2012-10-04 at 09:00 -0700, Linus Torvalds wrote:
> So this happens if you have "reverse merges" (ie you've pulled my
> tree, or some other tree I've pulled), and there is no longer a single
> clear common point that you started from. In that case, there is no
> simple diff for the "what has changed since that original point", and
> to get the diff for the merge you actually have to do the merge and
> check the end result. git-request-pull doesn't do that, it just
> assumes it's the simple case of some single common point.
That was more/less my guess. Thanks.
> The fact that you haven't seen it until now just means that you've
> generally done a good job at keeping your powerpc tree "clean" from
> other trees, and containing only your own work.
Heh, yeah I try to :-) In this specific case, this was a topic branch
from Bjorn which some pre-requisite patches to the generic PCI code that
Gavin did to allow us to get rid of some custom resource allocation
crap, so the "getting rid of" had a dependency on that topic branch.
Unfortunately, Bjorn had also based that branch on top of some larger
cleanup patch so I ended up pulling that as well from him, which tripped
the whole thing.
Cheers,
Ben.
^ permalink raw reply
* [GIT PULL] Disintegrate UAPI for powerpc
From: David Howells @ 2012-10-04 19:51 UTC (permalink / raw)
To: benh; +Cc: dhowells, linuxppc-dev, linux-kernel
Can you merge the following branch into the powerpc tree please.
This is to complete part of the UAPI disintegration for which the preparatory
patches were pulled recently.
Note that there are some fixup patches which are at the base of the branch
aimed at you, plus all arches get the asm-generic branch merged in too.
The following changes since commit 612a9aab56a93533e76e3ad91642db7033e03b69:
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux (2012-10-03 23:29:23 -0700)
are available in the git repository at:
git://git.infradead.org/users/dhowells/linux-headers.git disintegrate-powerpc
for you to fetch changes up to d4b1059feb6486ae0800e936b9dd5fd4e05b9d0c:
UAPI: (Scripted) Disintegrate arch/powerpc/include/asm (2012-10-04 18:21:17 +0100)
----------------------------------------------------------------
David Howells (6):
UAPI: Fix the guards on various asm/unistd.h files
UAPI: Split compound conditionals containing __KERNEL__ in Arm64
Merge remote-tracking branch 'c6x/for-linux-next' into uapi-prep
UAPI: Fix conditional header installation handling (notably kvm_para.h on m68k)
UAPI: (Scripted) Disintegrate include/asm-generic
UAPI: (Scripted) Disintegrate arch/powerpc/include/asm
Mark Salter (2):
c6x: make dsk6455 the default config
c6x: remove c6x signal.h
arch/arm64/include/asm/hwcap.h | 4 +-
arch/arm64/include/asm/stat.h | 4 +-
arch/arm64/include/asm/unistd.h | 8 +-
arch/arm64/include/asm/unistd32.h | 4 -
arch/c6x/Makefile | 2 +
arch/c6x/include/asm/Kbuild | 1 +
arch/c6x/include/asm/signal.h | 17 -
arch/c6x/include/asm/unistd.h | 4 -
arch/hexagon/include/asm/unistd.h | 5 -
arch/openrisc/include/asm/unistd.h | 5 -
arch/powerpc/include/asm/Kbuild | 35 -
arch/powerpc/include/asm/bootx.h | 123 +--
arch/powerpc/include/asm/cputable.h | 35 +-
arch/powerpc/include/asm/elf.h | 311 +-------
arch/powerpc/include/asm/kvm_para.h | 70 +-
arch/powerpc/include/asm/mman.h | 27 +-
arch/powerpc/include/asm/nvram.h | 55 +-
arch/powerpc/include/asm/ptrace.h | 242 +-----
arch/powerpc/include/asm/signal.h | 143 +---
arch/powerpc/include/asm/spu_info.h | 29 +-
arch/powerpc/include/asm/swab.h | 15 +-
arch/powerpc/include/asm/termios.h | 69 +-
arch/powerpc/include/asm/types.h | 30 +-
arch/powerpc/include/asm/unistd.h | 374 +--------
arch/powerpc/include/uapi/asm/Kbuild | 41 +
arch/powerpc/include/{ => uapi}/asm/auxvec.h | 0
arch/powerpc/include/{ => uapi}/asm/bitsperlong.h | 0
arch/powerpc/include/uapi/asm/bootx.h | 132 ++++
arch/powerpc/include/{ => uapi}/asm/byteorder.h | 0
arch/powerpc/include/uapi/asm/cputable.h | 36 +
arch/powerpc/include/uapi/asm/elf.h | 307 ++++++++
arch/powerpc/include/{ => uapi}/asm/errno.h | 0
arch/powerpc/include/{ => uapi}/asm/fcntl.h | 0
arch/powerpc/include/{ => uapi}/asm/ioctl.h | 0
arch/powerpc/include/{ => uapi}/asm/ioctls.h | 0
arch/powerpc/include/{ => uapi}/asm/ipcbuf.h | 0
arch/powerpc/include/{ => uapi}/asm/kvm.h | 0
arch/powerpc/include/uapi/asm/kvm_para.h | 90 +++
arch/powerpc/include/{ => uapi}/asm/linkage.h | 0
arch/powerpc/include/uapi/asm/mman.h | 31 +
arch/powerpc/include/{ => uapi}/asm/msgbuf.h | 0
arch/powerpc/include/uapi/asm/nvram.h | 62 ++
arch/powerpc/include/{ => uapi}/asm/param.h | 0
arch/powerpc/include/{ => uapi}/asm/poll.h | 0
arch/powerpc/include/{ => uapi}/asm/posix_types.h | 0
arch/powerpc/include/{ => uapi}/asm/ps3fb.h | 0
arch/powerpc/include/uapi/asm/ptrace.h | 259 ++++++
arch/powerpc/include/{ => uapi}/asm/resource.h | 0
arch/powerpc/include/{ => uapi}/asm/seccomp.h | 0
arch/powerpc/include/{ => uapi}/asm/sembuf.h | 0
arch/powerpc/include/{ => uapi}/asm/setup.h | 0
arch/powerpc/include/{ => uapi}/asm/shmbuf.h | 0
arch/powerpc/include/{ => uapi}/asm/sigcontext.h | 0
arch/powerpc/include/{ => uapi}/asm/siginfo.h | 0
arch/powerpc/include/uapi/asm/signal.h | 145 ++++
arch/powerpc/include/{ => uapi}/asm/socket.h | 0
arch/powerpc/include/{ => uapi}/asm/sockios.h | 0
arch/powerpc/include/uapi/asm/spu_info.h | 53 ++
arch/powerpc/include/{ => uapi}/asm/stat.h | 0
arch/powerpc/include/{ => uapi}/asm/statfs.h | 0
arch/powerpc/include/uapi/asm/swab.h | 23 +
arch/powerpc/include/{ => uapi}/asm/termbits.h | 0
arch/powerpc/include/uapi/asm/termios.h | 76 ++
arch/powerpc/include/uapi/asm/types.h | 40 +
arch/powerpc/include/{ => uapi}/asm/ucontext.h | 0
arch/powerpc/include/uapi/asm/unistd.h | 380 +++++++++
arch/score/include/asm/unistd.h | 5 -
arch/tile/include/asm/unistd.h | 5 -
arch/unicore32/include/asm/unistd.h | 4 -
include/asm-generic/Kbuild | 35 -
include/asm-generic/bitsperlong.h | 13 +-
include/asm-generic/int-l64.h | 26 +-
include/asm-generic/int-ll64.h | 31 +-
include/asm-generic/ioctl.h | 95 +--
include/asm-generic/kvm_para.h | 5 +-
include/asm-generic/param.h | 17 +-
include/asm-generic/resource.h | 66 +-
include/asm-generic/siginfo.h | 297 +------
include/asm-generic/signal.h | 117 +--
include/asm-generic/statfs.h | 81 +-
include/asm-generic/termios.h | 49 +-
include/asm-generic/unistd.h | 911 +---------------------
include/linux/Kbuild | 9 +-
include/uapi/asm-generic/Kbuild | 35 +
include/{ => uapi}/asm-generic/auxvec.h | 0
include/uapi/asm-generic/bitsperlong.h | 15 +
include/{ => uapi}/asm-generic/errno-base.h | 0
include/{ => uapi}/asm-generic/errno.h | 0
include/{ => uapi}/asm-generic/fcntl.h | 0
include/uapi/asm-generic/int-l64.h | 34 +
include/uapi/asm-generic/int-ll64.h | 39 +
include/uapi/asm-generic/ioctl.h | 98 +++
include/{ => uapi}/asm-generic/ioctls.h | 0
include/{ => uapi}/asm-generic/ipcbuf.h | 0
include/{ => uapi}/asm-generic/mman-common.h | 0
include/{ => uapi}/asm-generic/mman.h | 0
include/{ => uapi}/asm-generic/msgbuf.h | 0
include/uapi/asm-generic/param.h | 19 +
include/{ => uapi}/asm-generic/poll.h | 0
include/{ => uapi}/asm-generic/posix_types.h | 0
include/uapi/asm-generic/resource.h | 68 ++
include/{ => uapi}/asm-generic/sembuf.h | 0
include/{ => uapi}/asm-generic/setup.h | 0
include/{ => uapi}/asm-generic/shmbuf.h | 0
include/{ => uapi}/asm-generic/shmparam.h | 0
include/uapi/asm-generic/siginfo.h | 298 +++++++
include/{ => uapi}/asm-generic/signal-defs.h | 0
include/uapi/asm-generic/signal.h | 123 +++
include/{ => uapi}/asm-generic/socket.h | 0
include/{ => uapi}/asm-generic/sockios.h | 0
include/{ => uapi}/asm-generic/stat.h | 0
include/uapi/asm-generic/statfs.h | 83 ++
include/{ => uapi}/asm-generic/swab.h | 0
include/{ => uapi}/asm-generic/termbits.h | 0
include/uapi/asm-generic/termios.h | 50 ++
include/{ => uapi}/asm-generic/types.h | 0
include/{ => uapi}/asm-generic/ucontext.h | 0
include/uapi/asm-generic/unistd.h | 902 +++++++++++++++++++++
security/apparmor/Makefile | 2 +-
119 files changed, 3498 insertions(+), 3321 deletions(-)
delete mode 100644 arch/c6x/include/asm/signal.h
rename arch/powerpc/include/{ => uapi}/asm/auxvec.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/bitsperlong.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/bootx.h
rename arch/powerpc/include/{ => uapi}/asm/byteorder.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/cputable.h
create mode 100644 arch/powerpc/include/uapi/asm/elf.h
rename arch/powerpc/include/{ => uapi}/asm/errno.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/fcntl.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/ioctl.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/ioctls.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/ipcbuf.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/kvm.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/kvm_para.h
rename arch/powerpc/include/{ => uapi}/asm/linkage.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/mman.h
rename arch/powerpc/include/{ => uapi}/asm/msgbuf.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/nvram.h
rename arch/powerpc/include/{ => uapi}/asm/param.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/poll.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/posix_types.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/ps3fb.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/ptrace.h
rename arch/powerpc/include/{ => uapi}/asm/resource.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/seccomp.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/sembuf.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/setup.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/shmbuf.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/sigcontext.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/siginfo.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/signal.h
rename arch/powerpc/include/{ => uapi}/asm/socket.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/sockios.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/spu_info.h
rename arch/powerpc/include/{ => uapi}/asm/stat.h (100%)
rename arch/powerpc/include/{ => uapi}/asm/statfs.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/swab.h
rename arch/powerpc/include/{ => uapi}/asm/termbits.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/termios.h
create mode 100644 arch/powerpc/include/uapi/asm/types.h
rename arch/powerpc/include/{ => uapi}/asm/ucontext.h (100%)
create mode 100644 arch/powerpc/include/uapi/asm/unistd.h
rename include/{ => uapi}/asm-generic/auxvec.h (100%)
create mode 100644 include/uapi/asm-generic/bitsperlong.h
rename include/{ => uapi}/asm-generic/errno-base.h (100%)
rename include/{ => uapi}/asm-generic/errno.h (100%)
rename include/{ => uapi}/asm-generic/fcntl.h (100%)
create mode 100644 include/uapi/asm-generic/int-l64.h
create mode 100644 include/uapi/asm-generic/int-ll64.h
create mode 100644 include/uapi/asm-generic/ioctl.h
rename include/{ => uapi}/asm-generic/ioctls.h (100%)
rename include/{ => uapi}/asm-generic/ipcbuf.h (100%)
create mode 100644 include/uapi/asm-generic/kvm_para.h
rename include/{ => uapi}/asm-generic/mman-common.h (100%)
rename include/{ => uapi}/asm-generic/mman.h (100%)
rename include/{ => uapi}/asm-generic/msgbuf.h (100%)
create mode 100644 include/uapi/asm-generic/param.h
rename include/{ => uapi}/asm-generic/poll.h (100%)
rename include/{ => uapi}/asm-generic/posix_types.h (100%)
create mode 100644 include/uapi/asm-generic/resource.h
rename include/{ => uapi}/asm-generic/sembuf.h (100%)
rename include/{ => uapi}/asm-generic/setup.h (100%)
rename include/{ => uapi}/asm-generic/shmbuf.h (100%)
rename include/{ => uapi}/asm-generic/shmparam.h (100%)
create mode 100644 include/uapi/asm-generic/siginfo.h
rename include/{ => uapi}/asm-generic/signal-defs.h (100%)
create mode 100644 include/uapi/asm-generic/signal.h
rename include/{ => uapi}/asm-generic/socket.h (100%)
rename include/{ => uapi}/asm-generic/sockios.h (100%)
rename include/{ => uapi}/asm-generic/stat.h (100%)
create mode 100644 include/uapi/asm-generic/statfs.h
rename include/{ => uapi}/asm-generic/swab.h (100%)
rename include/{ => uapi}/asm-generic/termbits.h (100%)
create mode 100644 include/uapi/asm-generic/termios.h
rename include/{ => uapi}/asm-generic/types.h (100%)
rename include/{ => uapi}/asm-generic/ucontext.h (100%)
create mode 100644 include/uapi/asm-generic/unistd.h
.
^ permalink raw reply
* RE: [PATCH 3/5] rapidio: run discovery as an asynchronous process
From: Bounine, Alexandre @ 2012-10-04 19:08 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <20121003152953.79aecece.akpm@linux-foundation.org>
On Wed, October 03, 2012 6:30 PM
Andrew Morton <akpm@linux-foundation.org> wrote:
>=20
> On Wed, 3 Oct 2012 15:18:41 -0400
> Alexandre Bounine <alexandre.bounine@idt.com> wrote:
>=20
> > ...
> >
> > +static void __devinit disc_work_handler(struct work_struct *_work)
> > +{
> > + struct rio_disc_work *work =3D container_of(_work,
> > + struct rio_disc_work, work);
>=20
> There's a nice simple way to avoid such ugliness:
>=20
> --- a/drivers/rapidio/rio.c~rapidio-run-discovery-as-an-asynchronous-
> process-fix
> +++ a/drivers/rapidio/rio.c
> @@ -1269,9 +1269,9 @@ struct rio_disc_work {
>=20
> static void __devinit disc_work_handler(struct work_struct *_work)
> {
> - struct rio_disc_work *work =3D container_of(_work,
> - struct rio_disc_work, work);
> + struct rio_disc_work *work;
>=20
> + work =3D container_of(_work, struct rio_disc_work, work);
> pr_debug("RIO: discovery work for mport %d %s\n",
> work->mport->id, work->mport->name);
> rio_disc_mport(work->mport);
> _
>=20
Thank you for the fix. Will avoid that ugliness in the future.
> > + pr_debug("RIO: discovery work for mport %d %s\n",
> > + work->mport->id, work->mport->name);
> > + rio_disc_mport(work->mport);
> > +
> > + kfree(work);
> > +}
> > +
> > int __devinit rio_init_mports(void)
> > {
> > struct rio_mport *port;
> > + struct rio_disc_work *work;
> > + int no_disc =3D 0;
> >
> > list_for_each_entry(port, &rio_mports, node) {
> > if (port->host_deviceid >=3D 0)
> > rio_enum_mport(port);
> > - else
> > - rio_disc_mport(port);
> > + else if (!no_disc) {
> > + if (!rio_wq) {
> > + rio_wq =3D alloc_workqueue("riodisc", 0, 0);
> > + if (!rio_wq) {
> > + pr_err("RIO: unable allocate rio_wq\n");
> > + no_disc =3D 1;
> > + continue;
> > + }
> > + }
> > +
> > + work =3D kzalloc(sizeof *work, GFP_KERNEL);
> > + if (!work) {
> > + pr_err("RIO: no memory for work struct\n");
> > + no_disc =3D 1;
> > + continue;
> > + }
> > +
> > + work->mport =3D port;
> > + INIT_WORK(&work->work, disc_work_handler);
> > + queue_work(rio_wq, &work->work);
> > + }
> > + }
>=20
> I'm having a lot of trouble with `no_disc'. afacit what it does is to
> cease running async discovery for any remaining devices if the
> workqueue
> allocation failed (vaguely reasonable) or if the allocation of a single
> work item failed (incomprehensible).
>=20
> But if we don't run discovery, the subsystem is permanently busted for
> at least some devices, isn't it?
This is correct. We are considering ways to restart discovery
process later but it is not applicable now.
>=20
> And this code is basically untestable unless the programmer does
> deliberate fault injection, which makes it pretty much unmaintainable.
>=20
> So... if I haven't totally misunderstood, I suggest a rethink is in
> order?
>
I will review and simplify. Probably, just try to allocate all required
resources ahead of port list scan. Simple and safe.
=20
> > + if (rio_wq) {
> > + pr_debug("RIO: flush discovery workqueue\n");
> > + flush_workqueue(rio_wq);
> > + pr_debug("RIO: flush discovery workqueue finished\n");
> > + destroy_workqueue(rio_wq);
> > }
^ permalink raw reply
* RE: [PATCH v2] PPC: Do not make the entire heap executable
From: Jason Gunthorpe @ 2012-10-04 18:12 UTC (permalink / raw)
To: linux-kernel, Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <20120930232619.GE30637@obsidianresearch.com>
On PPC the ELF PLT sections look like this:
[17] .sbss NOBITS 0002aff8 01aff8 000014 00 WA 0 0 4
[18] .plt NOBITS 0002b00c 01aff8 000084 00 WAX 0 0 4
[19] .bss NOBITS 0002b090 01aff8 0000a4 00 WA 0 0 4
Which results in an ELF load header:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x019c70 0x00029c70 0x00029c70 0x01388 0x014c4 RWE 0x10000
This is all correct, the load region containing the PLT is marked as
executable. Note that the PLT starts at 0002b00c but the file mapping ends at
0002aff8, so the PLT falls in the 0 fill section described by the load header,
and after a page boundary.
Unfortunately the generic ELF loader ignores the X bit in the load headers
when it creates the 0 filled non-file backed mappings. It assumes all of these
mappings are RW BSS sections, which is not the case for PPC.
Teach the ELF loader to check the X bit in the relevant load header and
create 0 filled anonymous mappings that are executable if the load header
requests that.
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
arch/powerpc/include/asm/page.h | 10 +--------
arch/powerpc/include/asm/page_32.h | 2 -
arch/powerpc/include/asm/page_64.h | 4 ---
fs/binfmt_elf.c | 41 +++++++++++++++++++++++++++++-------
4 files changed, 34 insertions(+), 23 deletions(-)
Some more testing found a bug, updated patch incase anyone wants
to try it.
Changes in v2:
- In load_elf_interp last_bss can become < elf_bss when vm_brk is
called. In the unpatched kernel this results in something like
0xFFFFFF00 being passed into vm_brk as the len, which rounds up to
0 and does nothing, but vm_mmap returns an error.. glibc 2.19
triggered this case due to the ld.so layout, eglibc 2.13 didn't.
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index f072e97..61e46fc 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -215,15 +215,7 @@ extern long long virt_phys_offset;
#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET + MEMORY_START)
#endif
-/*
- * Unfortunately the PLT is in the BSS in the PPC32 ELF ABI,
- * and needs to be executable. This means the whole heap ends
- * up being executable.
- */
-#define VM_DATA_DEFAULT_FLAGS32 (VM_READ | VM_WRITE | VM_EXEC | \
- VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#define VM_DATA_DEFAULT_FLAGS64 (VM_READ | VM_WRITE | \
+#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#ifdef __powerpc64__
diff --git a/arch/powerpc/include/asm/page_32.h b/arch/powerpc/include/asm/page_32.h
index 68d73b2..aaae5a6 100644
--- a/arch/powerpc/include/asm/page_32.h
+++ b/arch/powerpc/include/asm/page_32.h
@@ -7,8 +7,6 @@
#endif
#endif
-#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
-
#ifdef CONFIG_NOT_COHERENT_CACHE
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#endif
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index fed85e6..615d88b 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -136,10 +136,6 @@ do { \
#endif /* !CONFIG_HUGETLB_PAGE */
-#define VM_DATA_DEFAULT_FLAGS \
- (is_32bit_task() ? \
- VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
-
/*
* This is the default if a program doesn't have a PT_GNU_STACK
* program header entry. The PPC64 ELF ABI has a non executable stack
diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c
index 1b52956..c26b40d 100644
--- a/fs/binfmt_elf.c
+++ b/fs/binfmt_elf.c
@@ -76,13 +76,20 @@ static struct linux_binfmt elf_format = {
#define BAD_ADDR(x) ((unsigned long)(x) >= TASK_SIZE)
-static int set_brk(unsigned long start, unsigned long end)
+static int set_brk(unsigned long start, unsigned long end, int prot)
{
start = ELF_PAGEALIGN(start);
end = ELF_PAGEALIGN(end);
if (end > start) {
unsigned long addr;
- addr = vm_brk(start, end - start);
+ /* Map the non-file portion of the last load header. If the
+ header is requesting these pages to be executeable then
+ we have to honour that, otherwise assume they are bss. */
+ if (prot & PROT_EXEC)
+ addr = vm_mmap(0, start, end - start, prot,
+ MAP_PRIVATE | MAP_FIXED, 0);
+ else
+ addr = vm_brk(start, end - start);
if (BAD_ADDR(addr))
return addr;
}
@@ -381,6 +388,7 @@ static unsigned long load_elf_interp(struct elfhdr *interp_elf_ex,
unsigned long load_addr = 0;
int load_addr_set = 0;
unsigned long last_bss = 0, elf_bss = 0;
+ int bss_prot = 0;
unsigned long error = ~0UL;
unsigned long total_size;
int retval, i, size;
@@ -489,8 +497,10 @@ static unsigned long load_elf_interp(struct elfhdr *interp_elf_ex,
* elf_bss and last_bss is the bss section.
*/
k = load_addr + eppnt->p_memsz + eppnt->p_vaddr;
- if (k > last_bss)
+ if (k > last_bss) {
last_bss = k;
+ bss_prot = elf_prot;
+ }
}
}
@@ -509,8 +519,19 @@ static unsigned long load_elf_interp(struct elfhdr *interp_elf_ex,
/* What we have mapped so far */
elf_bss = ELF_PAGESTART(elf_bss + ELF_MIN_ALIGN - 1);
- /* Map the last of the bss segment */
- error = vm_brk(elf_bss, last_bss - elf_bss);
+ if (last_bss > elf_bss) {
+ /* Map the non-file portion of the last load
+ header. If the header is requesting these pages to
+ be executeable then we have to honour that,
+ otherwise assume they are bss. */
+ if ((bss_prot & PROT_EXEC) && last_bss > elf_bss)
+ error = vm_mmap(0, elf_bss,
+ ELF_PAGEALIGN(last_bss - elf_bss),
+ bss_prot, MAP_PRIVATE | MAP_FIXED, 0);
+ else
+ error = vm_brk(elf_bss, last_bss - elf_bss);
+ }
+
if (BAD_ADDR(error))
goto out_close;
}
@@ -560,6 +581,7 @@ static int load_elf_binary(struct linux_binprm *bprm, struct pt_regs *regs)
unsigned long error;
struct elf_phdr *elf_ppnt, *elf_phdata;
unsigned long elf_bss, elf_brk;
+ int bss_prot = 0;
int retval, i;
unsigned int size;
unsigned long elf_entry;
@@ -750,7 +772,8 @@ static int load_elf_binary(struct linux_binprm *bprm, struct pt_regs *regs)
before this one. Map anonymous pages, if needed,
and clear the area. */
retval = set_brk(elf_bss + load_bias,
- elf_brk + load_bias);
+ elf_brk + load_bias,
+ bss_prot);
if (retval) {
send_sig(SIGKILL, current, 0);
goto out_free_dentry;
@@ -852,8 +875,10 @@ static int load_elf_binary(struct linux_binprm *bprm, struct pt_regs *regs)
if (end_data < k)
end_data = k;
k = elf_ppnt->p_vaddr + elf_ppnt->p_memsz;
- if (k > elf_brk)
+ if (k > elf_brk) {
+ bss_prot = elf_prot;
elf_brk = k;
+ }
}
loc->elf_ex.e_entry += load_bias;
@@ -869,7 +894,7 @@ static int load_elf_binary(struct linux_binprm *bprm, struct pt_regs *regs)
* mapping in the interpreter, to make sure it doesn't wind
* up getting placed where the bss needs to go.
*/
- retval = set_brk(elf_bss, elf_brk);
+ retval = set_brk(elf_bss, elf_brk, bss_prot);
if (retval) {
send_sig(SIGKILL, current, 0);
goto out_free_dentry;
--
1.7.5.4
^ permalink raw reply related
* RE: [PATCH 1/5] rapidio: fix blocking wait for discovery ready
From: Bounine, Alexandre @ 2012-10-04 17:20 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <20121003152001.665c9373.akpm@linux-foundation.org>
On Wed, October 03, 2012 6:20 PM
Andrew Morton <akpm@linux-foundation.org> wrote:
>=20
> On Wed, 3 Oct 2012 15:18:39 -0400
> Alexandre Bounine <alexandre.bounine@idt.com> wrote:
>=20
> > Fix blocking wait loop in the RapidIO discovery routine to avoid
> > warning dumps about stalled CPU on x86 platforms.
> >
> > ...
> >
> > + to_end =3D jiffies + CONFIG_RAPIDIO_DISC_TIMEOUT * HZ;
> > + while (time_before(jiffies, to_end)) {
> > + if (rio_enum_complete(mport))
> > + goto enum_done;
> > +
> schedule_timeout_uninterruptible(msecs_to_jiffies(10));
>=20
> I think a simple msleep(10) would suffice here?
>=20
Agree, same thing but looks simpler. Will update.
^ permalink raw reply
* Re: [PATCH] PPC: Correct the tophys/tovirt macros
From: Jason Gunthorpe @ 2012-10-04 17:08 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1349349544.4260.24.camel@pasglop>
On Thu, Oct 04, 2012 at 09:19:04PM +1000, Benjamin Herrenschmidt wrote:
> On Sun, 2012-09-30 at 17:28 -0600, Jason Gunthorpe wrote:
> > asm/page.h discusses the calculation for v2p and p2v, it should be:
> > va = pa + KERNELBASE - PHYSICAL_START
> > which is the same as:
> > va = pa + LOAD_OFFSET
> >
> > tophys/tovirt were using PAGE_OFFSET, which as page.h says, is almost
> > always the same thing.
> >
> > Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
>
> It's a bit gross tho in that KERNEL_BASE, PHYSICAL_START and LOAD_OFFSET
> are about where the kernel is linked/running, and while the value ends
> up happening to also be the p->v offset (and indeed not by accident), it
> makes the code less clear and more confusing.
Yes, I found the three names confusing.. However LOAD_OFFSET is the
name that include/asm-generic/vmlinux.lds.h and many arch's use for
P2V translation in the linker script, so at least there is some
precedent.
> I don't have the bandwidth to revisit all that, but I really think that
> whole are area where PAGE_OFFSET doesn't map 0 needs revisiting.
Something like that is also outside my scope.. This patch does fix a
bug I hit when CONFIG_PHYSICAL_START is used, are there problems with
it in other cases?
FWIW, this is part of a larger work that makes CONFIG_PHYSICAL_START
work on PPC404, which is not yet clean enough to post:
https://github.com/jgunthorpe/linux/commit/90df2d247c9db5d39c32dbbada0815f15d7b3be7
Regards,
Jason
^ permalink raw reply
* RE: [RFC][PATCH 1/3] iommu/fsl: Store iommu domain information pointer in archdata.
From: Sethi Varun-B16395 @ 2012-10-04 16:30 UTC (permalink / raw)
To: Kumar Gala
Cc: joerg.roedel@amd.com, iommu@lists.linux-foundation.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <5BDB4D18-CB0D-4EBA-B38F-A278B7C00A61@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Wednesday, September 19, 2012 7:20 PM
> To: Sethi Varun-B16395
> Cc: iommu@lists.linux-foundation.org; joerg.roedel@amd.com; linux-
> kernel@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Sethi Varun-B16395
> Subject: Re: [RFC][PATCH 1/3] iommu/fsl: Store iommu domain information
> pointer in archdata.
>=20
>=20
> On Sep 19, 2012, at 8:17 AM, <b16395@freescale.com>
> <b16395@freescale.com> wrote:
>=20
> > From: Varun Sethi <Varun.Sethi@freescale.com>
> >
> > Add a new field in the device (powerpc) archdata structure for storing
> > iommu domain information pointer. This pointer is stored when the
> > device is attached to a particular domain.
> >
> > Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> > ---
> > arch/powerpc/include/asm/device.h | 4 ++++
> > 1 files changed, 4 insertions(+), 0 deletions(-)
>=20
> Not too familiar, but what does the IBM Server IOMMU do for iommu_domain?
>
[Sethi Varun-B16395] I am not sure if the IBM iommu driver implements the i=
ommu
API.
-Varun
=20
^ permalink raw reply
* RE: [PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes required by fsl PAMU driver.
From: Sethi Varun-B16395 @ 2012-10-04 16:22 UTC (permalink / raw)
To: Kumar Gala
Cc: joerg.roedel@amd.com, iommu@lists.linux-foundation.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <43F13A8A-BF97-427C-8736-8F2E55B7A3D1@kernel.crashing.org>
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Thursday, October 04, 2012 6:47 PM
> To: Sethi Varun-B16395
> Cc: joerg.roedel@amd.com; iommu@lists.linux-foundation.org; linuxppc-
> dev@lists.ozlabs.org; linux-kernel@vger.kernel.org; Sethi Varun-B16395
> Subject: Re: [PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes
> required by fsl PAMU driver.
>=20
>=20
> On Oct 4, 2012, at 6:56 AM, <b16395@freescale.com> <b16395@freescale.com>
> wrote:
>=20
> > From: Varun Sethi <Varun.Sethi@freescale.com>
> >
> > Added the following domain attributes required by FSL PAMU driver:
> > 1. Subwindows field added to the iommu domain geometry attribute.
> > 2. Added new iommu stash attribute, which allows setting of the
> > LIODN specific stash id parameter through IOMMU API.
> > 3. Added an attribute for enabling/disabling DMA to a particular
> > memory window.
> >
> > Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> > ---
> > include/linux/iommu.h | 35 +++++++++++++++++++++++++++++++++++
> > 1 files changed, 35 insertions(+), 0 deletions(-)
> >
> > diff --git a/include/linux/iommu.h b/include/linux/iommu.h index
> > f3b99e1..62e22f0 100644
> > --- a/include/linux/iommu.h
> > +++ b/include/linux/iommu.h
> > @@ -44,6 +44,33 @@ struct iommu_domain_geometry {
> > dma_addr_t aperture_start; /* First address that can be mapped
> */
> > dma_addr_t aperture_end; /* Last address that can be mapped
> */
> > bool force_aperture; /* DMA only allowed in mappable range?
> */
> > +
> > + /* The subwindows field indicates number of DMA subwindows
> supported
> > + * by the geometry. Following is the interpretation of
> > + * values for this field:
> > + * 0 : This implies that the supported geometry size is 1 MB
> > + * with each subwindow size being 4KB. Thus number of
> subwindows
> > + * being =3D 1MB/4KB =3D 256.
> > + * 1 : Only one DMA window i.e. no subwindows.
> > + * value other than 0 or 1 would indicate actual number of
> subwindows.
> > + */
> > + u32 subwindows;
> > +};
> > +
> > +/* cache stash targets */
> > +#define L1_CACHE 1
> > +#define L2_CACHE 2
> > +#define L3_CACHE 3
>=20
> These names are way to generic for being exposed to user space
Will fix naming to IOMMU_ATTR_CACHE_L1 etc.
-Varun
^ permalink raw reply
* Re: [git pull] Please pull powerpc.git merge branch
From: Linus Torvalds @ 2012-10-04 16:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Linux Kernel list
In-Reply-To: <1349339900.4260.10.camel@pasglop>
On Thu, Oct 4, 2012 at 1:38 AM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
>
> The following changes since commit 271fd03a3013b106ccc178d54219c1be0c9759b7:
>
> powerpc/powernv: I/O and memory alignment for P2P bridges (2012-09-11 16:59:47 -0600)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
Hmm. There's nothing there.
Did you mean for me to pull some branch/tag you didn't mention?
Linus
^ permalink raw reply
* Re: [git pull] Please pull powerpc.git merge branch
From: Linus Torvalds @ 2012-10-04 16:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Linux Kernel list
In-Reply-To: <1349339900.4260.10.camel@pasglop>
On Thu, Oct 4, 2012 at 1:38 AM, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
>
> First, however, a note about the pull request details ... the diffstat looks
> completely on crack, any idea what's up ? It sees piles of files modified
> in various other archs & generic code but I see no patch in that branch
> that touches any of them.
So this happens if you have "reverse merges" (ie you've pulled my
tree, or some other tree I've pulled), and there is no longer a single
clear common point that you started from. In that case, there is no
simple diff for the "what has changed since that original point", and
to get the diff for the merge you actually have to do the merge and
check the end result. git-request-pull doesn't do that, it just
assumes it's the simple case of some single common point.
The fact that you haven't seen it until now just means that you've
generally done a good job at keeping your powerpc tree "clean" from
other trees, and containing only your own work.
Linus
^ permalink raw reply
* Re: [PATCH 3/3 v2] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
From: Kumar Gala @ 2012-10-04 13:20 UTC (permalink / raw)
To: <b16395@freescale.com>
Cc: joerg.roedel, iommu, linuxppc-dev, linux-kernel, Varun Sethi
In-Reply-To: <1349351808-7156-4-git-send-email-b16395@freescale.com>
On Oct 4, 2012, at 6:56 AM, <b16395@freescale.com> =
<b16395@freescale.com> wrote:
> From: Varun Sethi <Varun.Sethi@freescale.com>
>=20
> Following is a brief description of the PAMU hardware:
> PAMU determines what action to take and whether to authorize the =
action on the basis
> of the memory address, a Logical IO Device Number (LIODN), and PAACT =
table (logically)
> indexed by LIODN and address. Hardware devices which need to access =
memory must provide
> an LIODN in addition to the memory address.
>=20
> Peripheral Access Authorization and Control Tables (PAACTs) are the =
primary data structures
> used by PAMU. A PAACT is a table of peripheral access authorization =
and control entries (PAACE).
> Each PAACE defines the range of I/O bus address space that is =
accessible by the LIOD and the
> associated access capabilities.
>=20
> There are two types of PAACTs: primary PAACT (PPAACT) and secondary =
PAACT (SPAACT). A given physical
> I/O device may be able to act as one or more independent logical I/O =
devices (LIODs). Each such
> logical I/O device is assigned an identifier called logical I/O device =
number (LIODN). A LIOD is
> allocated a contiguous portion of the I/O bus address space called the =
DSA window for performing
> DSA operations. The DSA window may optionally be divided into multiple =
sub-windows, each of which
> may be used to map to a region in system storage space. The first =
sub-window is referred to
> as the primary sub-window and the remaining are called secondary =
sub-windows.
>=20
> This patch provides the PAMU driver (fsl_pamu.c) and the corresponding =
IOMMU API implementation
> (fsl_pamu_domain.c). The PAMU hardware driver (fsl_pamu.c) has been =
derived from the work done
> by Ashish Kalra and Timur Tabi (timur@freescale.com).
>=20
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> ---
I'm not seeing any of the comments I made addressed.
What changed in this version?
- k=
^ permalink raw reply
* Re: [PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes required by fsl PAMU driver.
From: Kumar Gala @ 2012-10-04 13:17 UTC (permalink / raw)
To: <b16395@freescale.com>
Cc: joerg.roedel, iommu, linuxppc-dev, linux-kernel, Varun Sethi
In-Reply-To: <1349351808-7156-3-git-send-email-b16395@freescale.com>
On Oct 4, 2012, at 6:56 AM, <b16395@freescale.com> =
<b16395@freescale.com> wrote:
> From: Varun Sethi <Varun.Sethi@freescale.com>
>=20
> Added the following domain attributes required by FSL PAMU driver:
> 1. Subwindows field added to the iommu domain geometry attribute.
> 2. Added new iommu stash attribute, which allows setting of the
> LIODN specific stash id parameter through IOMMU API.
> 3. Added an attribute for enabling/disabling DMA to a particular
> memory window.
>=20
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> ---
> include/linux/iommu.h | 35 +++++++++++++++++++++++++++++++++++
> 1 files changed, 35 insertions(+), 0 deletions(-)
>=20
> diff --git a/include/linux/iommu.h b/include/linux/iommu.h
> index f3b99e1..62e22f0 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
> @@ -44,6 +44,33 @@ struct iommu_domain_geometry {
> dma_addr_t aperture_start; /* First address that can be mapped =
*/
> dma_addr_t aperture_end; /* Last address that can be mapped =
*/
> bool force_aperture; /* DMA only allowed in mappable =
range? */
> +
> + /* The subwindows field indicates number of DMA subwindows =
supported
> + * by the geometry. Following is the interpretation of
> + * values for this field:
> + * 0 : This implies that the supported geometry size is 1 MB
> + * with each subwindow size being 4KB. Thus number of =
subwindows
> + * being =3D 1MB/4KB =3D 256.
> + * 1 : Only one DMA window i.e. no subwindows.
> + * value other than 0 or 1 would indicate actual number of =
subwindows.
> + */
> + u32 subwindows;
> +};
> +
> +/* cache stash targets */
> +#define L1_CACHE 1
> +#define L2_CACHE 2
> +#define L3_CACHE 3
These names are way to generic for being exposed to user space
> +
> +/* This attribute corresponds to IOMMUs capable of generating
> + * a stash transaction. A stash transaction is typically a
> + * hardware initiated prefetch of data from memory to cache.
> + * This attribute allows configuring stashig specific parameters
> + * in the IOMMU hardware.
> + */
> +struct iommu_stash_attribute {
> + u32 cpu; /* cpu number */
> + u32 cache; /* cache to stash to: L1,L2,L3 */
> };
>=20
> struct iommu_domain {
> @@ -60,6 +87,14 @@ struct iommu_domain {
> enum iommu_attr {
> DOMAIN_ATTR_MAX,
> DOMAIN_ATTR_GEOMETRY,
> + /* Set the IOMMU hardware stashing
> + * parameters.
> + */
> + DOMAIN_ATTR_STASH,
> + /* Explicity enable/disable DMA for a
> + * particular memory window.
> + */
> + DOMAIN_ATTR_ENABLE,
> };
>=20
> #ifdef CONFIG_IOMMU_API
> --=20
> 1.7.4.1
>=20
>=20
> --
> To unsubscribe from this list: send the line "unsubscribe =
linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* Re: PCI device not working
From: Kumar Gala @ 2012-10-04 13:14 UTC (permalink / raw)
To: Davide Viti; +Cc: linuxppc-dev
In-Reply-To: <11976036.82651349353479389.JavaMail.defaultUser@defaultHost>
On Oct 4, 2012, at 7:24 AM, Davide Viti wrote:
> Hi,
> it turns out that if define CONFIG_PCI_NOSCAN in u-boot (as per [1]), =
the=20
> devide behind the second controller is detected by the Linux kernel.
>=20
> Would=20
> you suggest any particular patch I should apply to fix this (I'm using =
kernel=20
> 2.6.34)
>=20
> thanx alot in advance
> Davide
>=20
> [1] http://permalink.gmane.org/gmane.
> linux.ports.ppc.embedded/20140
My suggestion would be to try and dump all the controller registers =
between the case that works and doesn't and compare. There's some minor =
setting difference that I'm guessing is causing issues.
- k
>=20
>> ----Messaggio originale----
>> Da:=20
> zinosat@tiscali.it
>> Data: 28/09/2012 16.48
>> A: <galak@kernel.crashing.org>
>> Cc:=20
> <linuxppc-dev@lists.ozlabs.org>
>> Ogg: R: Re: PCI device not working
>>=20
>> Hi=20
> Kumar,
>>=20
>>>=20
>>> It was, can you figure out in u-boot what exact config read on=20
>=20
>> the bus would return the correct thing.
>>>=20
>>> The fact that when we probe the=20
>=20
>> device at 0001:03 we should get back something like =
cfg_data=3D0xabba1b65
>>>=20
>>=20
>=20
>> here=20
>> follow some details about what is going on inside u-boot; verbosity=20=
> increases=20
>> from [1] to [3]
>>=20
>> [1] PCI printouts when the board come up
>> [2]=20
> output of "pci=20
>> [0-3] long" u-boot command
>> [3] same as [1] but with debug=20
> print inside=20
>> indirect_read_config_##size() [drivers/pci/pci_indirect.c]
>>=20
>> if=20
> you were curious=20
>> about our u-boot board settings, please refer to:
>> http:
> //www.mail-archive.
>> com/linuxppc-dev@lists.ozlabs.org/msg62007.html
>>=20
>> thanx=20
> alot,
>> Davide
>>=20
>>=20
>>=20
>> *************
>> * [1] *
>> *************
>> PCIE1=20
> used as Root Complex (base=20
>> addr ffe09000)
>> Scanning PCI bus 01
>=20
>> 01 00 1b65 abba =20
>> 0280 00
>> cfg_addr:ffe09000 cfg_data:
> ffe09004 indirect_type:0
>>=20
>> PCIE1 on bus 00 - 01
>>=20
>>=20
>> PCIE2 used as=20
> Root Complex (base addr ffe0a000)
>>=20
>> Scanning PCI bus 03
>=20
>> 03 00 1b65 abba 0280 00
>>=20
>> cfg_addr:ffe0a000 cfg_data:
> ffe0a004 indirect_type:0
>> PCIE2 on bus 02 - 03
>>=20
>>=20
>> *************
>> * =20
> [2] *
>> *************
>>=20
>> =3D> pci 0 long
>> Scanning PCI devices=20
>> on bus 0
>>=20
>=20
>> Found PCI device 00.00.00:
>> vendor ID =3D 0x1957
>>=20
>> device=20
> ID =3D 0x0100
>> command register =3D 0x0006
>>=20
>=20
>> status register =3D 0x0010
>> revision ID =3D 0x11
>>=20
>=20
>> class code =3D 0x0b (Processor)
>> sub class code=20
> =3D =20
>> 0x20
>> programming interface =3D 0x00
>> cache line=20
> =3D 0x08
>>=20
>> latency time =3D 0x00
>> header type=20
> =3D 0x01
>>=20
>> BIST =3D 0x00
>> base address=20
> 0 =3D 0xfff00000
>>=20
>> base address 1 =3D 0x00000000
>>=20
> primary bus number =3D 0x00
>>=20
>> secondary bus number =3D 0x01
>>=20
> subordinate bus number =3D 0x01
>>=20
>> secondary latency timer =3D 0x00
>>=20
> IO base =3D 0x00
>> IO=20
>> limit =3D 0x00
>>=20
> secondary status =3D 0x0000
>> memory=20
>> base =3D 0xa000
>=20
>> memory limit =3D 0xa000
>> prefetch=20
>> memory base =3D =20
> 0x1001
>> prefetch memory limit =3D 0x0001
>> prefetch=20
>> memory base upper=20
> =3D 0x00000000
>> prefetch memory limit upper =3D 0x00000000
>> IO=20
>> base upper 16=20
> bits =3D 0x0000
>> IO limit upper 16 bits =3D 0x0000
>>=20
>> expansion ROM=20
> base address =3D 0x00000000
>> interrupt line =3D 0x00
>>=20
>> interrupt=20
> pin =3D 0x00
>> bridge control =3D 0x0000
>>=20
>> =3D>=20
>> pci 1=20
> long
>> Scanning PCI devices on bus 1
>>=20
>> Found PCI device 01.00.00:kk
>> vendor=20
>=20
>> ID =3D 0x1b65
>> device ID =3D 0xabba
>>=20
> command=20
>> register =3D 0x0006
>> status register =3D 0x0010
>=20
>> revision=20
>> ID =3D 0x01
>> class code =3D 0x02=20
> (Network=20
>> controller)
>> sub class code =3D 0x80
>> programming=20
> interface=20
>> =3D 0x00
>> cache line =3D 0x08
>> latency time=20
>=20
>> =3D 0x00
>> header type =3D 0x00
>> BIST=20
>=20
>> =3D 0x00
>> base address 0 =3D 0xa0000000
>>=20
> base=20
>> address 1 =3D 0xa0010000
>> base address 2 =3D =20
> 0x00000000
>>=20
>> base address 3 =3D 0x00000000
>> base address 4=20
> =3D =20
>> 0x00000000
>> base address 5 =3D 0x00000000
>>=20
> cardBus CIS pointer=20
>> =3D 0x00000000
>> sub system vendor ID =3D =20
> 0x0000
>> sub system ID=20
>> =3D 0x0000
>> expansion ROM base address=20
> =3D 0x00000000
>> interrupt=20
>> line =3D 0x00
>> interrupt pin=20
> =3D 0x01
>> min Grant=20
>> =3D 0x00
>> max Latency=20
> =3D 0x00
>>=20
>> =3D> pci 2 long
>>=20
>> Scanning PCI devices on bus 2
>>=20
>=20
>> Found PCI device 02.00.00:
>> vendor ID=20
>> =3D 0x1957
>> device=20
> ID =3D 0x0100
>> command=20
>> register =3D 0x0006
>>=20
> status register =3D 0x0010
>> revision=20
>> ID =3D 0x11
>>=20
> class code =3D 0x0b (Processor)
>>=20
>> sub class code=20
> =3D 0x20
>> programming interface =3D 0x00
>> cache=20
>> line=20
> =3D 0x08
>> latency time =3D 0x00
>> header type=20
>=20
>> =3D 0x01
>> BIST =3D 0x00
>> base address=20
> 0=20
>> =3D 0xfff00000
>> base address 1 =3D 0x00000000
>>=20
> primary=20
>> bus number =3D 0x00
>> secondary bus number =3D 0x01
>>=20
> subordinate=20
>> bus number =3D 0x01
>> secondary latency timer =3D 0x00
>>=20
> IO base=20
>> =3D 0x00
>> IO limit =3D 0x00
>>=20
> secondary=20
>> status =3D 0x0000
>> memory base =3D 0xb000
>=20
>> memory=20
>> limit =3D 0xb000
>> prefetch memory base =3D =20
> 0x1001
>> prefetch=20
>> memory limit =3D 0x0001
>> prefetch memory base upper=20
> =3D 0x00000000
>>=20
>> prefetch memory limit upper =3D 0x00000000
>> IO base upper 16=20
> bits =3D 0x0000
>>=20
>> IO limit upper 16 bits =3D 0x0000
>> expansion ROM=20
> base address =3D =20
>> 0x00000000
>> interrupt line =3D 0x00
>> interrupt=20
> pin =3D =20
>> 0x00
>> bridge control =3D 0x0000
>>=20
>> =3D> pci 3=20
> long
>> Scanning PCI devices=20
>> on bus 3
>>=20
>> Found PCI device 03.00.00:
>> vendor=20
> ID =3D 0x1b65
>>=20
>> device ID =3D 0xabba
>>=20
> command register =3D 0x0006
>>=20
>> status register =3D 0x0010
>=20
>> revision ID =3D 0x01
>>=20
>> class code =3D 0x02=20
> (Network controller)
>> sub class code=20
>> =3D 0x80
>> programming=20
> interface =3D 0x00
>> cache line=20
>> =3D 0x08
>> latency time=20
> =3D 0x00
>> header type=20
>> =3D 0x00
>> BIST=20
> =3D 0x00
>> base address 0=20
>> =3D 0xb0000000
>>=20
> base address 1 =3D 0xb0010000
>> base=20
>> address 2 =3D =20
> 0x00000000
>> base address 3 =3D 0x00000000
>>=20
>> base address 4=20
> =3D 0x00000000
>> base address 5 =3D =20
>> 0x00000000
>>=20
> cardBus CIS pointer =3D 0x00000000
>> sub system vendor ID=20
>> =3D =20
> 0x0000
>> sub system ID =3D 0x0000
>> expansion ROM base=20
>> address=20
> =3D 0x00000000
>> interrupt line =3D 0x00
>> interrupt pin=20
>=20
>> =3D 0x01
>> min Grant =3D 0x00
>> max Latency=20
>=20
>> =3D 0x00
>>=20
>>=20
>> *************
>> * [3] *
>> *************
>>=20
>>=20
> PCIE1=20
>> used as Root Complex (base addr ffe09000)
>> b=3D0 d=3D0 f=3D0 (fbusno=3D0=20
> itype=3D0=20
>> cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D10 mask=3D0
>> ...
>=20
>> Scanning=20
>> PCI bus 01
>> b=3D1 d=3D0 f=3D0 (fbusno=3D0 itype=3D0=20
> cfg_adr=3Dffe09000 cfg_data=3Dffe09004)=20
>> ofs=3De mask=3D3
>> ...
>> b=3D1 d=3D0 f=3D0 (fbusno=3D0=20
> itype=3D0 cfg_adr=3Dffe09000=20
>> cfg_data=3Dffe09004) ofs=3D3c mask=3D3
>> 01 00 =20
> 1b65 abba 0280 00
>> b=3D1 d=3D1=20
>> f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000=20
> cfg_data=3Dffe09004) ofs=3De mask=3D3
>> b=3D1 d=3D1=20
>> f=3D0 (fbusno=3D0 itype=3D0=20
> cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D0 mask=3D2
>> ...
>> b=3D0=20
>> d=3D0 f=3D0 (fbusno=3D0=20
> itype=3D0 cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D9 mask=3D3
>>=20
>> PCIE1 on bus 00=20
> - 01
>>=20
>> PCIE2 used as Root Complex (base addr ffe0a000)
>> b=3D0=20
>> d=3D0 f=3D0=20
> (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D10 =
mask=3D0
>> b=3D0=20
>> d=3D0=20
> f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) =
ofs=3D10 mask=3D0
>> ...
>>=20
>=20
>> b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 =
cfg_data=3Dffe0a004) ofs=3D9 mask=3D3
>=20
>>=20
>> Scanning PCI bus 03
>> b=3D1 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
>=20
>> cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3De mask=3D3
>> b=3D1 d=3D0 f=3D0 (fbusno=3D2=20
> itype=3D0=20
>> cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D0 mask=3D2
>> ...
>> b=3D1 d=3D0 f=3D0=20
> (fbusno=3D2=20
>> itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D3c mask=3D3
>>=20
> 03 00 1b65 =20
>> abba 0280 00
>> cfg_addr:ffe0a000 cfg_data:ffe0a004 =20
> indirect_type:0
>>=20
>> b=3D1 d=3D1 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000=20
> cfg_data=3Dffe0a004) ofs=3De mask=3D3
>>=20
>> ...
>> b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
> cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D9=20
>> mask=3D3
>> PCIE2 on bus 02 - 03
>>=20
>=20
>>=20
>>=20
>> Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico =
vale pi=F9=20
> di uno spot in TV. Per ogni nuovo abbonato 30 =80 di premio per te e =
per lui! Un=20
> amico al mese e parli e navighi sempre gratis: =
http://freelosophy.tiscali.it/
>=20
>=20
>=20
> Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico vale =
pi=F9 di uno spot in TV. Per ogni nuovo abbonato 30 =80 di premio per te =
e per lui! Un amico al mese e parli e navighi sempre gratis: =
http://freelosophy.tiscali.it/
^ permalink raw reply
* R: Re: PCI device not working
From: Davide Viti @ 2012-10-04 12:24 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
Hi,
it turns out that if define CONFIG_PCI_NOSCAN in u-boot (as per [1]), the=
=20
devide behind the second controller is detected by the Linux kernel.
Would=20
you suggest any particular patch I should apply to fix this (I'm using kern=
el=20
2.6.34)
thanx alot in advance
Davide
[1] http://permalink.gmane.org/gmane.
linux.ports.ppc.embedded/20140
>----Messaggio originale----
>Da:=20
zinosat@tiscali.it
>Data: 28/09/2012 16.48
>A: <galak@kernel.crashing.org>
>Cc:=20
<linuxppc-dev@lists.ozlabs.org>
>Ogg: R: Re: PCI device not working
>
>Hi=20
Kumar,
>
>>
>>It was, can you figure out in u-boot what exact config read on=20
>the bus would return the correct thing.
>>
>>The fact that when we probe the=20
>device at 0001:03 we should get back something like cfg_data=3D0xabba1b65
>>
>
>here=20
>follow some details about what is going on inside u-boot; verbosity=20
increases=20
>from [1] to [3]
>
> [1] PCI printouts when the board come up
> [2]=20
output of "pci=20
>[0-3] long" u-boot command
> [3] same as [1] but with debug=20
print inside=20
>indirect_read_config_##size() [drivers/pci/pci_indirect.c]
>
>if=20
you were curious=20
>about our u-boot board settings, please refer to:
>http:
//www.mail-archive.
>com/linuxppc-dev@lists.ozlabs.org/msg62007.html
>
>thanx=20
alot,
>Davide
>
>
>
>*************
>* [1] *
>*************
> PCIE1=20
used as Root Complex (base=20
>addr ffe09000)
> Scanning PCI bus 01
> 01 00 1b65 abba =20
>0280 00
> cfg_addr:ffe09000 cfg_data:
ffe09004 indirect_type:0
> =20
>PCIE1 on bus 00 - 01
>
>
> PCIE2 used as=20
Root Complex (base addr ffe0a000)
>
> Scanning PCI bus 03
> 03 00 1b65 abba 0280 00
> =20
>cfg_addr:ffe0a000 cfg_data:
ffe0a004 indirect_type:0
> PCIE2 on bus 02 - 03
>
>
>*************
>* =20
[2] *
>*************
>
>=3D> pci 0 long
>Scanning PCI devices=20
>on bus 0
>
>Found PCI device 00.00.00:
> vendor ID =3D 0x1957
> =20
>device=20
ID =3D 0x0100
> command register =3D 0x0006
> =20
>status register =3D 0x0010
> revision ID =3D 0x11
> =20
>class code =3D 0x0b (Processor)
> sub class code=20
=3D =20
>0x20
> programming interface =3D 0x00
> cache line=20
=3D 0x08
>
> latency time =3D 0x00
> header type=20
=3D 0x01
> =20
>BIST =3D 0x00
> base address=20
0 =3D 0xfff00000
> =20
>base address 1 =3D 0x00000000
> =20
primary bus number =3D 0x00
> =20
>secondary bus number =3D 0x01
> =20
subordinate bus number =3D 0x01
> =20
>secondary latency timer =3D 0x00
> =20
IO base =3D 0x00
> IO=20
>limit =3D 0x00
> =20
secondary status =3D 0x0000
> memory=20
>base =3D 0xa000
> memory limit =3D 0xa000
> prefetch=20
>memory base =3D =20
0x1001
> prefetch memory limit =3D 0x0001
> prefetch=20
>memory base upper=20
=3D 0x00000000
> prefetch memory limit upper =3D 0x00000000
> IO=20
>base upper 16=20
bits =3D 0x0000
> IO limit upper 16 bits =3D 0x0000
> =20
>expansion ROM=20
base address =3D 0x00000000
> interrupt line =3D 0x00
> =20
>interrupt=20
pin =3D 0x00
> bridge control =3D 0x0000
>
>=3D>=20
>pci 1=20
long
>Scanning PCI devices on bus 1
>
>Found PCI device 01.00.00:kk
> vendor=20
>ID =3D 0x1b65
> device ID =3D 0xabba
> =20
command=20
>register =3D 0x0006
> status register =3D 0x0010
> revision=20
>ID =3D 0x01
> class code =3D 0x02=20
(Network=20
>controller)
> sub class code =3D 0x80
> programming=20
interface=20
>=3D 0x00
> cache line =3D 0x08
> latency time=20
>=3D 0x00
> header type =3D 0x00
> BIST=20
>=3D 0x00
> base address 0 =3D 0xa0000000
> =20
base=20
>address 1 =3D 0xa0010000
> base address 2 =3D =20
0x00000000
>
> base address 3 =3D 0x00000000
> base address 4=20
=3D =20
>0x00000000
> base address 5 =3D 0x00000000
> =20
cardBus CIS pointer=20
>=3D 0x00000000
> sub system vendor ID =3D =20
0x0000
> sub system ID=20
>=3D 0x0000
> expansion ROM base address=20
=3D 0x00000000
> interrupt=20
>line =3D 0x00
> interrupt pin=20
=3D 0x01
> min Grant=20
>=3D 0x00
> max Latency=20
=3D 0x00
>
>=3D> pci 2 long
>
>Scanning PCI devices on bus 2
>
>Found PCI device 02.00.00:
> vendor ID=20
>=3D 0x1957
> device=20
ID =3D 0x0100
> command=20
>register =3D 0x0006
> =20
status register =3D 0x0010
> revision=20
>ID =3D 0x11
> =20
class code =3D 0x0b (Processor)
> =20
>sub class code=20
=3D 0x20
> programming interface =3D 0x00
> cache=20
>line=20
=3D 0x08
> latency time =3D 0x00
> header type=20
>=3D 0x01
> BIST =3D 0x00
> base address=20
0=20
>=3D 0xfff00000
> base address 1 =3D 0x00000000
> =20
primary=20
>bus number =3D 0x00
> secondary bus number =3D 0x01
> =20
subordinate=20
>bus number =3D 0x01
> secondary latency timer =3D 0x00
> =20
IO base=20
>=3D 0x00
> IO limit =3D 0x00
> =20
secondary=20
>status =3D 0x0000
> memory base =3D 0xb000
> memory=20
>limit =3D 0xb000
> prefetch memory base =3D =20
0x1001
> prefetch=20
>memory limit =3D 0x0001
> prefetch memory base upper=20
=3D 0x00000000
> =20
>prefetch memory limit upper =3D 0x00000000
> IO base upper 16=20
bits =3D 0x0000
>
> IO limit upper 16 bits =3D 0x0000
> expansion ROM=20
base address =3D =20
>0x00000000
> interrupt line =3D 0x00
> interrupt=20
pin =3D =20
>0x00
> bridge control =3D 0x0000
>
>=3D> pci 3=20
long
>Scanning PCI devices=20
>on bus 3
>
>Found PCI device 03.00.00:
> vendor=20
ID =3D 0x1b65
> =20
>device ID =3D 0xabba
> =20
command register =3D 0x0006
> =20
>status register =3D 0x0010
> revision ID =3D 0x01
> =20
>class code =3D 0x02=20
(Network controller)
> sub class code=20
>=3D 0x80
> programming=20
interface =3D 0x00
> cache line=20
>=3D 0x08
> latency time=20
=3D 0x00
> header type=20
>=3D 0x00
> BIST=20
=3D 0x00
> base address 0=20
>=3D 0xb0000000
> =20
base address 1 =3D 0xb0010000
> base=20
>address 2 =3D =20
0x00000000
> base address 3 =3D 0x00000000
>
> base address 4=20
=3D 0x00000000
> base address 5 =3D =20
>0x00000000
> =20
cardBus CIS pointer =3D 0x00000000
> sub system vendor ID=20
>=3D =20
0x0000
> sub system ID =3D 0x0000
> expansion ROM base=20
>address=20
=3D 0x00000000
> interrupt line =3D 0x00
> interrupt pin=20
>=3D 0x01
> min Grant =3D 0x00
> max Latency=20
>=3D 0x00
>
>
>*************
>* [3] *
>*************
>
> =20
PCIE1=20
>used as Root Complex (base addr ffe09000)
>b=3D0 d=3D0 f=3D0 (fbusno=3D0=20
itype=3D0=20
>cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D10 mask=3D0
>...
> Scanning=20
>PCI bus 01
>b=3D1 d=3D0 f=3D0 (fbusno=3D0 itype=3D0=20
cfg_adr=3Dffe09000 cfg_data=3Dffe09004)=20
>ofs=3De mask=3D3
>...
>b=3D1 d=3D0 f=3D0 (fbusno=3D0=20
itype=3D0 cfg_adr=3Dffe09000=20
>cfg_data=3Dffe09004) ofs=3D3c mask=3D3
> 01 00 =20
1b65 abba 0280 00
>b=3D1 d=3D1=20
>f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000=20
cfg_data=3Dffe09004) ofs=3De mask=3D3
>b=3D1 d=3D1=20
>f=3D0 (fbusno=3D0 itype=3D0=20
cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D0 mask=3D2
>...
>b=3D0=20
>d=3D0 f=3D0 (fbusno=3D0=20
itype=3D0 cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D9 mask=3D3
> =20
>PCIE1 on bus 00=20
- 01
>
> PCIE2 used as Root Complex (base addr ffe0a000)
>b=3D0=20
>d=3D0 f=3D0=20
(fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D10 mask=
=3D0
>b=3D0=20
>d=3D0=20
f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D1=
0 mask=3D0
>...
>
>b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0=
a004) ofs=3D9 mask=3D3
>
> Scanning PCI bus 03
>b=3D1 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
>cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3De mask=3D3
>b=3D1 d=3D0 f=3D0 (fbusno=3D2=20
itype=3D0=20
>cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D0 mask=3D2
>...
>b=3D1 d=3D0 f=3D0=20
(fbusno=3D2=20
>itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D3c mask=3D3
> =20
03 00 1b65 =20
>abba 0280 00
> cfg_addr:ffe0a000 cfg_data:ffe0a004 =20
indirect_type:0
>
>b=3D1 d=3D1 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000=20
cfg_data=3Dffe0a004) ofs=3De mask=3D3
>
>...
>b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D9=20
>mask=3D3
> PCIE2 on bus 02 - 03
>
>
>
>Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico vale pi=
=C3=B9=20
di uno spot in TV. Per ogni nuovo abbonato 30 =E2=82=AC di premio per te e =
per lui! Un=20
amico al mese e parli e navighi sempre gratis: http://freelosophy.tiscali.i=
t/
Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico vale pi=
=C3=B9 di uno spot in TV. Per ogni nuovo abbonato 30 =E2=82=AC di premio pe=
r te e per lui! Un amico al mese e parli e navighi sempre gratis: http://fr=
eelosophy.tiscali.it/
^ permalink raw reply
* [PATCH 3/3 v2] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
From: b16395 @ 2012-10-04 11:56 UTC (permalink / raw)
To: joerg.roedel, iommu, linuxppc-dev, linux-kernel; +Cc: Varun Sethi
In-Reply-To: <1349351808-7156-1-git-send-email-b16395@freescale.com>
From: Varun Sethi <Varun.Sethi@freescale.com>
Following is a brief description of the PAMU hardware:
PAMU determines what action to take and whether to authorize the action on the basis
of the memory address, a Logical IO Device Number (LIODN), and PAACT table (logically)
indexed by LIODN and address. Hardware devices which need to access memory must provide
an LIODN in addition to the memory address.
Peripheral Access Authorization and Control Tables (PAACTs) are the primary data structures
used by PAMU. A PAACT is a table of peripheral access authorization and control entries (PAACE).
Each PAACE defines the range of I/O bus address space that is accessible by the LIOD and the
associated access capabilities.
There are two types of PAACTs: primary PAACT (PPAACT) and secondary PAACT (SPAACT). A given physical
I/O device may be able to act as one or more independent logical I/O devices (LIODs). Each such
logical I/O device is assigned an identifier called logical I/O device number (LIODN). A LIOD is
allocated a contiguous portion of the I/O bus address space called the DSA window for performing
DSA operations. The DSA window may optionally be divided into multiple sub-windows, each of which
may be used to map to a region in system storage space. The first sub-window is referred to
as the primary sub-window and the remaining are called secondary sub-windows.
This patch provides the PAMU driver (fsl_pamu.c) and the corresponding IOMMU API implementation
(fsl_pamu_domain.c). The PAMU hardware driver (fsl_pamu.c) has been derived from the work done
by Ashish Kalra and Timur Tabi (timur@freescale.com).
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
---
drivers/iommu/Kconfig | 8 +
drivers/iommu/Makefile | 1 +
drivers/iommu/fsl_pamu.c | 1060 +++++++++++++++++++++++++++++++++++++++
drivers/iommu/fsl_pamu.h | 401 +++++++++++++++
drivers/iommu/fsl_pamu_domain.c | 1013 +++++++++++++++++++++++++++++++++++++
drivers/iommu/fsl_pamu_domain.h | 96 ++++
6 files changed, 2579 insertions(+), 0 deletions(-)
create mode 100644 drivers/iommu/fsl_pamu.c
create mode 100644 drivers/iommu/fsl_pamu.h
create mode 100644 drivers/iommu/fsl_pamu_domain.c
create mode 100644 drivers/iommu/fsl_pamu_domain.h
diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig
index e39f9db..79b36f7 100644
--- a/drivers/iommu/Kconfig
+++ b/drivers/iommu/Kconfig
@@ -17,6 +17,14 @@ config OF_IOMMU
def_bool y
depends on OF
+config FSL_PAMU
+ bool "Freescale IOMMU support"
+ depends on E500
+ select IOMMU_API
+ select GENERIC_ALLOCATOR
+ help
+ Freescale PAMU support.
+
# MSM IOMMU support
config MSM_IOMMU
bool "MSM IOMMU Support"
diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile
index 14a4d5f..a565ebe 100644
--- a/drivers/iommu/Makefile
+++ b/drivers/iommu/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
obj-$(CONFIG_EXYNOS_IOMMU) += exynos-iommu.o
+obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o
diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c
new file mode 100644
index 0000000..9e3080c
--- /dev/null
+++ b/drivers/iommu/fsl_pamu.c
@@ -0,0 +1,1060 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/iommu.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/of_platform.h>
+#include <linux/bootmem.h>
+#include <linux/genalloc.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+
+#include "fsl_pamu.h"
+
+#define PAMUBYPENR 0x604
+
+/* define indexes for each operation mapping scenario */
+#define OMI_QMAN 0x00
+#define OMI_FMAN 0x01
+#define OMI_QMAN_PRIV 0x02
+#define OMI_CAAM 0x03
+
+static paace_t *ppaact = NULL;
+static paace_t *spaact = NULL;
+static struct ome *omt = NULL;
+unsigned int max_subwindow_count;
+
+struct gen_pool *spaace_pool;
+
+static paace_t *pamu_get_ppaace(int liodn)
+{
+ if (!ppaact) {
+ pr_err("PPAACT doesn't exist\n");
+ return NULL;
+ }
+
+ return &ppaact[liodn];
+}
+
+/** Sets validation bit of PACCE
+ *
+ * @parm[in] liodn PAACT index for desired PAACE
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+int pamu_enable_liodn(int liodn)
+{
+ paace_t *ppaace;
+
+ ppaace = pamu_get_ppaace(liodn);
+ if (!ppaace)
+ return -ENOENT;
+
+ if (!get_bf(ppaace->addr_bitfields, PPAACE_AF_WSE)) {
+ pr_err("liodn %d not configured\n", liodn);
+ return -EINVAL;
+ }
+
+ /* Ensure that all other stores to the ppaace complete first */
+ mb();
+
+ ppaace->addr_bitfields |= PAACE_V_VALID;
+ mb();
+
+ return 0;
+}
+
+/** Clears validation bit of PACCE
+ *
+ * @parm[in] liodn PAACT index for desired PAACE
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+int pamu_disable_liodn(int liodn)
+{
+ paace_t *ppaace;
+
+ ppaace = pamu_get_ppaace(liodn);
+ if (!ppaace)
+ return -ENOENT;
+
+ set_bf(ppaace->addr_bitfields, PAACE_AF_V, PAACE_V_INVALID);
+ mb();
+
+ return 0;
+}
+
+
+static unsigned int map_addrspace_size_to_wse(phys_addr_t addrspace_size)
+{
+ BUG_ON((addrspace_size & (addrspace_size - 1)));
+
+ /* window size is 2^(WSE+1) bytes */
+ return __ffs(addrspace_size >> PAMU_PAGE_SHIFT) + PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(u32 subwindow_cnt)
+{
+ /* window count is 2^(WCE+1) bytes */
+ return __ffs(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(paace_t *ppaace)
+{
+ set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+
+ set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(paace_t *spaace)
+{
+ set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+ set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+static paace_t *pamu_get_spaace(u32 fspi_index, u32 wnum)
+{
+ return &spaact[fspi_index + wnum];
+}
+
+static unsigned long pamu_get_fspi_and_allocate(u32 subwin_cnt)
+{
+ unsigned long spaace_addr;
+
+ spaace_addr = gen_pool_alloc(spaace_pool, subwin_cnt * sizeof(paace_t));
+ if (!spaace_addr)
+ return ULONG_MAX;
+
+ return (spaace_addr - (unsigned long)spaact) / (sizeof(paace_t));
+}
+
+void pamu_free_subwins(int liodn)
+{
+ paace_t *ppaace;
+ u32 subwin_cnt, size;
+
+ ppaace = pamu_get_ppaace(liodn);
+ if (!ppaace)
+ return;
+
+ if (get_bf(ppaace->addr_bitfields, PPAACE_AF_MW)) {
+ subwin_cnt = 1UL << (get_bf(ppaace->impl_attr, PAACE_IA_WCE) + 1);
+ size = (subwin_cnt - 1) * sizeof(paace_t);
+ gen_pool_free(spaace_pool, (unsigned long)&spaact[ppaace->fspi], size);
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);
+ }
+}
+
+/* Function used for updating stash destination for the coresspong LIODN.
+ */
+int pamu_update_paace_stash(int liodn, u32 subwin, u32 value)
+{
+ paace_t *paace;
+
+ paace = pamu_get_ppaace(liodn);
+ if (!paace) {
+ return -ENOENT;
+ }
+ if (subwin) {
+ paace = pamu_get_spaace(paace->fspi, subwin - 1);
+ if (!paace) {
+ return -ENOENT;
+ }
+ }
+ set_bf(paace->impl_attr, PAACE_IA_CID, value);
+
+ return 0;
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn Logical IO device number
+ * @param[in] win_addr starting address of DSA window
+ * @param[in] win-size size of DSA window
+ * @param[in] omi Operation mapping index -- if ~omi == 0 then omi not defined
+ * @param[in] rpn real (true physical) page number
+ * @param[in] stashid cache stash id for associated cpu -- if ~stashid == 0 then
+ * stashid not defined
+ * @param[in] snoopid snoop id for hardware coherency -- if ~snoopid == 0 then
+ * snoopid not defined
+ * @param[in] subwin_cnt number of sub-windows
+ * @param[in] prot window permissions
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size,
+ u32 omi, unsigned long rpn, u32 snoopid, u32 stashid,
+ u32 subwin_cnt, int prot)
+{
+ paace_t *ppaace;
+ unsigned long fspi;
+
+ if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE) {
+ pr_err("window size too small or not a power of two %llx\n", win_size);
+ return -EINVAL;
+ }
+
+ if (win_addr & (win_size - 1)) {
+ pr_err("window address is not aligned with window size\n");
+ return -EINVAL;
+ }
+
+ ppaace = pamu_get_ppaace(liodn);
+ if (!ppaace) {
+ return -ENOENT;
+ }
+
+ /* window size is 2^(WSE+1) bytes */
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE,
+ map_addrspace_size_to_wse(win_size));
+
+ pamu_setup_default_xfer_to_host_ppaace(ppaace);
+
+ ppaace->wbah = win_addr >> (PAMU_PAGE_SHIFT + 20);
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL,
+ (win_addr >> PAMU_PAGE_SHIFT));
+
+ /* set up operation mapping if it's configured */
+ if (omi < OME_NUMBER_ENTRIES) {
+ set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+ ppaace->op_encode.index_ot.omi = omi;
+ } else if (~omi != 0) {
+ pr_err("bad operation mapping index: %d\n", omi);
+ return -EINVAL;
+ }
+
+ /* configure stash id */
+ if (~stashid != 0)
+ set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid);
+
+ /* configure snoop id */
+ if (~snoopid != 0)
+ ppaace->domain_attr.to_host.snpid = snoopid;
+
+ if (subwin_cnt) {
+ /* The first entry is in the primary PAACE instead */
+ fspi = pamu_get_fspi_and_allocate(subwin_cnt - 1);
+ if (fspi == ULONG_MAX) {
+ pr_err("spaace indexes exhausted\n");
+ return -EINVAL;
+ }
+
+ /* window count is 2^(WCE+1) bytes */
+ set_bf(ppaace->impl_attr, PAACE_IA_WCE,
+ map_subwindow_cnt_to_wce(subwin_cnt));
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1);
+ ppaace->fspi = fspi;
+ } else {
+ set_bf(ppaace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
+ ppaace->twbah = rpn >> 20;
+ set_bf(ppaace->win_bitfields, PAACE_WIN_TWBAL, rpn);
+ set_bf(ppaace->addr_bitfields, PAACE_AF_AP, prot);
+ set_bf(ppaace->impl_attr, PAACE_IA_WCE, 0);
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0);
+ }
+ mb();
+
+ return 0;
+}
+
+/** Sets up SPAACE entry for specified subwindow
+ *
+ * @param[in] liodn Logical IO device number
+ * @param[in] subwin_cnt number of sub-windows associated with dma-window
+ * @param[in] subwin_addr starting address of subwindow
+ * @param[in] subwin_size size of subwindow
+ * @param[in] omi Operation mapping index
+ * @param[in] rpn real (true physical) page number
+ * @param[in] snoopid snoop id for hardware coherency -- if ~snoopid == 0 then
+ * snoopid not defined
+ * @param[in] stashid cache stash id for associated cpu
+ * @param[in] enable enable/disable subwindow after reconfiguration
+ * @param[in] prot sub window permissions
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin_addr,
+ phys_addr_t subwin_size, u32 omi, unsigned long rpn,
+ u32 snoopid, u32 stashid, int enable, int prot)
+{
+ paace_t *paace;
+ unsigned long fspi;
+
+ /* setup sub-windows */
+ if (!subwin_cnt) {
+ pr_err("Invalid subwindow count\n");
+ return -EINVAL;
+ }
+
+ paace = pamu_get_ppaace(liodn);
+ if (subwin_addr > 0 && paace) {
+ fspi = paace->fspi;
+ paace = pamu_get_spaace(fspi, subwin_addr - 1);
+
+ if (paace && !(paace->addr_bitfields & PAACE_V_VALID)) {
+ pamu_setup_default_xfer_to_host_spaace(paace);
+ set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn);
+ }
+ }
+
+ if (!paace)
+ return -ENOENT;
+
+ if (!enable && prot == PAACE_AP_PERMS_DENIED) {
+ if (subwin_addr > 0)
+ set_bf(paace->addr_bitfields, PAACE_AF_V,
+ PAACE_V_INVALID);
+ else
+ set_bf(paace->addr_bitfields, PAACE_AF_AP,
+ prot);
+ mb();
+ return 0;
+ }
+
+ if (subwin_size & (subwin_size - 1) || subwin_size < PAMU_PAGE_SIZE) {
+ pr_err("subwindow size out of range, or not a power of 2\n");
+ return -EINVAL;
+ }
+
+ if (rpn == ULONG_MAX) {
+ pr_err("real page number out of range\n");
+ return -EINVAL;
+ }
+
+ /* window size is 2^(WSE+1) bytes */
+ set_bf(paace->win_bitfields, PAACE_WIN_SWSE,
+ map_addrspace_size_to_wse(subwin_size));
+
+ set_bf(paace->impl_attr, PAACE_IA_ATM, PAACE_ATM_WINDOW_XLATE);
+ paace->twbah = rpn >> 20;
+ set_bf(paace->win_bitfields, PAACE_WIN_TWBAL, rpn);
+ set_bf(paace->addr_bitfields, PAACE_AF_AP, prot);
+
+ /* configure snoop id */
+ if (~snoopid != 0)
+ paace->domain_attr.to_host.snpid = snoopid;
+
+ /* set up operation mapping if it's configured */
+ if (omi < OME_NUMBER_ENTRIES) {
+ set_bf(paace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+ paace->op_encode.index_ot.omi = omi;
+ } else if (~omi != 0) {
+ pr_err("bad operation mapping index: %d\n", omi);
+ return -EINVAL;
+ }
+
+ if (~stashid != 0)
+ set_bf(paace->impl_attr, PAACE_IA_CID, stashid);
+
+ smp_wmb();
+
+ if (enable)
+ paace->addr_bitfields |= PAACE_V_VALID;
+
+ mb();
+
+ return 0;
+}
+
+void get_ome_index(u32 *omi_index, struct device *dev)
+{
+ if (of_device_is_compatible(dev->of_node, "fsl,qman-portal"))
+ *omi_index = OMI_QMAN;
+ if (of_device_is_compatible(dev->of_node, "fsl,qman"))
+ *omi_index = OMI_QMAN_PRIV;
+}
+
+u32 get_stash_id(u32 stash_dest_hint, u32 vcpu)
+{
+ const u32 *prop;
+ struct device_node *node;
+ u32 cache_level;
+ int len;
+
+ /* Fastpath, exit early if L3/CPC cache is target for stashing */
+ if (stash_dest_hint == L3_CACHE) {
+ node = of_find_compatible_node(NULL, NULL,
+ "fsl,p4080-l3-cache-controller");
+ if (node) {
+ prop = of_get_property(node, "cache-stash-id", 0);
+ if (!prop) {
+ pr_err("missing cache-stash-id at %s\n", node->full_name);
+ of_node_put(node);
+ return ~(u32)0;
+ }
+ of_node_put(node);
+ return be32_to_cpup(prop);
+ }
+ return ~(u32)0;
+ }
+
+ for_each_node_by_type(node, "cpu") {
+ prop = of_get_property(node, "reg", &len);
+ if (be32_to_cpup(prop) == vcpu)
+ break;
+ }
+
+ /* find the hwnode that represents the cache */
+ for (cache_level = L1_CACHE; cache_level <= L3_CACHE; cache_level++) {
+ if (stash_dest_hint == cache_level) {
+ prop = of_get_property(node, "cache-stash-id", 0);
+ if (!prop) {
+ pr_err("missing cache-stash-id at %s\n", node->full_name);
+ of_node_put(node);
+ return ~(u32)0;
+ }
+ of_node_put(node);
+ return be32_to_cpup(prop);
+ }
+
+ prop = of_get_property(node, "next-level-cache", 0);
+ if (!prop) {
+ pr_err("can't find next-level-cache at %s\n",
+ node->full_name);
+ of_node_put(node);
+ return ~(u32)0; /* can't traverse any further */
+ }
+ of_node_put(node);
+
+ /* advance to next node in cache hierarchy */
+ node = of_find_node_by_phandle(*prop);
+ if (!node) {
+ pr_err("bad cpu reference %d\n", vcpu);
+ return ~(u32)0;
+ }
+ }
+
+ pr_err("stash dest not found for %d on vcpu %d\n",
+ stash_dest_hint, vcpu);
+ return ~(u32)0;
+}
+
+#define QMAN_PAACE 1
+#define QMAN_PORTAL_PAACE 2
+#define BMAN_PAACE 3
+
+static void setup_qbman_paace(paace_t *ppaace, int paace_type)
+{
+ switch(paace_type) {
+ case QMAN_PAACE:
+ set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+ ppaace->op_encode.index_ot.omi = OMI_QMAN_PRIV;
+ /* setup QMAN Private data stashing for the L3 cache */
+ set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(L3_CACHE, 0));
+ set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ 0);
+ break;
+ case QMAN_PORTAL_PAACE:
+ set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+ ppaace->op_encode.index_ot.omi = OMI_QMAN;
+ /*Set DQRR and Frame stashing for the L3 cache */
+ set_bf(ppaace->impl_attr, PAACE_IA_CID, get_stash_id(L3_CACHE, 0));
+ break;
+ case BMAN_PAACE:
+ set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ 0);
+ break;
+ }
+}
+
+static void setup_omt(struct ome *omt)
+{
+ struct ome *ome;
+
+ /* Configure OMI_QMAN */
+ ome = &omt[OMI_QMAN];
+
+ ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READ;
+ ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
+ ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
+ ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSAO;
+
+ ome->moe[IOE_DIRECT0_IDX] = EOE_VALID | EOE_LDEC;
+ ome->moe[IOE_DIRECT1_IDX] = EOE_VALID | EOE_LDECPE;
+
+ /* Configure OMI_FMAN */
+ ome = &omt[OMI_FMAN];
+ ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READI;
+ ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
+
+ /* Configure OMI_QMAN private */
+ ome = &omt[OMI_QMAN_PRIV];
+ ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READ;
+ ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
+ ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
+ ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
+
+ /* Configure OMI_CAAM */
+ ome = &omt[OMI_CAAM];
+ ome->moe[IOE_READ_IDX] = EOE_VALID | EOE_READI;
+ ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WRITE;
+}
+
+int setup_one_pamu(unsigned long pamu_reg_base, unsigned long pamu_reg_size,
+ phys_addr_t ppaact_phys, phys_addr_t spaact_phys,
+ phys_addr_t omt_phys)
+{
+ u32 *pc;
+ struct pamu_mmap_regs *pamu_regs;
+ u32 pc3_val;
+
+ pc3_val = in_be32((u32 *)(pamu_reg_base + PAMU_PC3));
+ max_subwindow_count = 1 << (1 + PAMU_PC3_MWCE(pc3_val));
+
+ pc = (u32 *) (pamu_reg_base + PAMU_PC);
+ pamu_regs = (struct pamu_mmap_regs *)
+ (pamu_reg_base + PAMU_MMAP_REGS_BASE);
+
+ /* set up pointers to corenet control blocks */
+
+ out_be32(&pamu_regs->ppbah, ((u64)ppaact_phys) >> 32);
+ out_be32(&pamu_regs->ppbal, ppaact_phys);
+ ppaact_phys = ppaact_phys + PAACT_SIZE;
+ out_be32(&pamu_regs->pplah, ((u64)ppaact_phys) >> 32);
+ out_be32(&pamu_regs->pplal, ppaact_phys);
+
+ out_be32(&pamu_regs->spbah, ((u64)spaact_phys) >> 32);
+ out_be32(&pamu_regs->spbal, spaact_phys);
+ spaact_phys = spaact_phys + SPAACT_SIZE;
+ out_be32(&pamu_regs->splah, ((u64)spaact_phys) >> 32);
+ out_be32(&pamu_regs->splal, spaact_phys);
+
+ out_be32(&pamu_regs->obah, ((u64)omt_phys) >> 32);
+ out_be32(&pamu_regs->obal, omt_phys);
+ omt_phys = omt_phys + OMT_SIZE;
+ out_be32(&pamu_regs->olah, ((u64)omt_phys) >> 32);
+ out_be32(&pamu_regs->olal, omt_phys);
+
+ /*
+ * set PAMU enable bit,
+ * allow ppaact & omt to be cached
+ * & enable PAMU access violation interrupts.
+ */
+
+ out_be32((u32 *)(pamu_reg_base + PAMU_PICS),
+ PAMU_ACCESS_VIOLATION_ENABLE);
+ out_be32(pc, PAMU_PC_PE | PAMU_PC_OCE | PAMU_PC_SPCC | PAMU_PC_PPCC);
+ return 0;
+}
+
+static void __init setup_liodns(void)
+{
+ int i, len;
+ paace_t *ppaace;
+ struct device_node *node = NULL;
+ const u32 *prop;
+
+ for_each_node_with_property(node, "fsl,liodn") {
+ prop = of_get_property(node, "fsl,liodn", &len);
+ for (i = 0; i < len / sizeof(u32); i++) {
+ int liodn;
+
+ liodn = be32_to_cpup(&prop[i]);
+ ppaace = pamu_get_ppaace(liodn);
+ pamu_setup_default_xfer_to_host_ppaace(ppaace);
+ /* window size is 2^(WSE+1) bytes */
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, 35);
+ ppaace->wbah = 0;
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, 0);
+ set_bf(ppaace->impl_attr, PAACE_IA_ATM,
+ PAACE_ATM_NO_XLATE);
+ set_bf(ppaace->addr_bitfields, PAACE_AF_AP,
+ PAACE_AP_PERMS_ALL);
+ if (of_device_is_compatible(node, "fsl,qman-portal"))
+ setup_qbman_paace(ppaace, QMAN_PORTAL_PAACE);
+ if (of_device_is_compatible(node, "fsl,qman"))
+ setup_qbman_paace(ppaace, QMAN_PAACE);
+ if (of_device_is_compatible(node, "fsl,bman"))
+ setup_qbman_paace(ppaace, BMAN_PAACE);
+ mb();
+ pamu_enable_liodn(liodn);
+ }
+ }
+}
+
+irqreturn_t pamu_av_isr(int irq, void *arg)
+{
+ panic("FSL_PAMU: access violation interrupt\n");
+ /* NOTREACHED */
+
+ return IRQ_HANDLED;
+}
+
+#define LAWAR_EN 0x80000000
+#define LAWAR_TARGET_MASK 0x0FF00000
+#define LAWAR_TARGET_SHIFT 20
+#define LAWAR_SIZE_MASK 0x0000003F
+#define LAWAR_CSDID_MASK 0x000FF000
+#define LAWAR_CSDID_SHIFT 12
+
+#define LAW_SIZE_4K 0xb
+
+struct ccsr_law {
+ u32 lawbarh; /* LAWn base address high */
+ u32 lawbarl; /* LAWn base address low */
+ u32 lawar; /* LAWn attributes */
+ u32 reserved;
+};
+
+#define make64(high, low) (((u64)(high) << 32) | (low))
+
+/*
+ * Create a coherence subdomain for a given memory block.
+ */
+static int __init create_csd(phys_addr_t phys, size_t size, u32 csd_port_id)
+{
+ struct device_node *np;
+ const __be32 *iprop;
+ void __iomem *lac = NULL; /* Local Access Control registers */
+ struct ccsr_law __iomem *law;
+ void __iomem *ccm = NULL;
+ u32 __iomem *csdids;
+ unsigned int i, num_laws, num_csds;
+ u32 law_target = 0;
+ u32 csd_id = 0;
+ int ret = 0;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,corenet-law");
+ if (!np)
+ return -ENODEV;
+
+ iprop = of_get_property(np, "fsl,num-laws", NULL);
+ if (!iprop) {
+ ret = -ENODEV;
+ goto error;
+ }
+
+ num_laws = be32_to_cpup(iprop);
+ if (!num_laws) {
+ ret = -ENODEV;
+ goto error;
+ }
+
+ lac = of_iomap(np, 0);
+ if (!lac) {
+ ret = -ENODEV;
+ goto error;
+ }
+
+ /* LAW registers are at offset 0xC00 */
+ law = lac + 0xC00;
+
+ of_node_put(np);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,corenet-cf");
+ if (!np) {
+ ret = -ENODEV;
+ goto error;
+ }
+
+ iprop = of_get_property(np, "fsl,ccf-num-csdids", NULL);
+ if (!iprop) {
+ ret = -ENODEV;
+ goto error;
+ }
+
+ num_csds = be32_to_cpup(iprop);
+ if (!num_csds) {
+ ret = -ENODEV;
+ goto error;
+ }
+
+ ccm = of_iomap(np, 0);
+ if (!ccm) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ /* The undocumented CSDID registers are at offset 0x600 */
+ csdids = ccm + 0x600;
+
+ of_node_put(np);
+ np = NULL;
+
+ /* Find an unused coherence subdomain ID */
+ for (csd_id = 0; csd_id < num_csds; csd_id++) {
+ if (!csdids[csd_id])
+ break;
+ }
+
+ /* Store the Port ID in the (undocumented) proper CIDMRxx register */
+ csdids[csd_id] = csd_port_id;
+
+ /* Find the DDR LAW that maps to our buffer. */
+ for (i = 0; i < num_laws; i++) {
+ if (law[i].lawar & LAWAR_EN) {
+ phys_addr_t law_start, law_end;
+
+ law_start = make64(law[i].lawbarh, law[i].lawbarl);
+ law_end = law_start +
+ (2ULL << (law[i].lawar & LAWAR_SIZE_MASK));
+
+ if (law_start <= phys && phys < law_end) {
+ law_target = law[i].lawar & LAWAR_TARGET_MASK;
+ break;
+ }
+ }
+ }
+
+ if (i == 0 || i == num_laws) {
+ /* This should never happen*/
+ ret = -ENOENT;
+ goto error;
+ }
+
+ /* Find a free LAW entry */
+ while (law[--i].lawar & LAWAR_EN) {
+ if (i == 0) {
+ /* No higher priority LAW slots available */
+ ret = -ENOENT;
+ goto error;
+ }
+ }
+
+ law[i].lawbarh = upper_32_bits(phys);
+ law[i].lawbarl = lower_32_bits(phys);
+ wmb();
+ law[i].lawar = LAWAR_EN | law_target | (csd_id << LAWAR_CSDID_SHIFT) |
+ (LAW_SIZE_4K + get_order(size));
+ wmb();
+
+error:
+ if (ccm)
+ iounmap(ccm);
+
+ if (lac)
+ iounmap(lac);
+
+ if (np)
+ of_node_put(np);
+
+ return ret;
+}
+
+/*
+ * Table of SVRs and the corresponding PORT_ID values.
+ *
+ * All future CoreNet-enabled SOCs will have this erratum fixed, so this table
+ * should never need to be updated. SVRs are guaranteed to be unique, so
+ * there is no worry that a future SOC will inadvertently have one of these
+ * values.
+ */
+static const struct {
+ u32 svr;
+ u32 port_id;
+} port_id_map[] = {
+ {0x82100010, 0xFF000000}, /* P2040 1.0 */
+ {0x82100011, 0xFF000000}, /* P2040 1.1 */
+ {0x82100110, 0xFF000000}, /* P2041 1.0 */
+ {0x82100111, 0xFF000000}, /* P2041 1.1 */
+ {0x82110310, 0xFF000000}, /* P3041 1.0 */
+ {0x82110311, 0xFF000000}, /* P3041 1.1 */
+ {0x82010020, 0xFFF80000}, /* P4040 2.0 */
+ {0x82000020, 0xFFF80000}, /* P4080 2.0 */
+ {0x82210010, 0xFC000000}, /* P5010 1.0 */
+ {0x82210020, 0xFC000000}, /* P5010 2.0 */
+ {0x82200010, 0xFC000000}, /* P5020 1.0 */
+ {0x82050010, 0xFF800000}, /* P5021 1.0 */
+ {0x82040010, 0xFF800000}, /* P5040 1.0 */
+};
+
+#define SVR_SECURITY 0x80000 /* The Security (E) bit */
+
+static int __init fsl_pamu_probe(struct platform_device *pdev)
+{
+ void __iomem *pamu_regs = NULL;
+ void __iomem *guts_regs = NULL;
+ u32 pamubypenr, pamu_counter;
+ unsigned long pamu_reg_off;
+ unsigned long pamu_reg_base;
+ struct device_node *guts_node;
+ u64 size;
+ struct page *p;
+ int ret = 0;
+ int irq;
+ phys_addr_t ppaact_phys;
+ phys_addr_t spaact_phys;
+ phys_addr_t omt_phys;
+ size_t mem_size = 0;
+ unsigned int order = 0;
+ u32 csd_port_id = 0;
+ unsigned i;
+ /*
+ * enumerate all PAMUs and allocate and setup PAMU tables
+ * for each of them,
+ * NOTE : All PAMUs share the same LIODN tables.
+ */
+
+ pamu_regs = of_iomap(pdev->dev.of_node, 0);
+ if (!pamu_regs) {
+ dev_err(&pdev->dev, "ioremap of PAMU node failed\n");
+ return -ENOMEM;
+ }
+ of_get_address(pdev->dev.of_node, 0, &size, NULL);
+
+ irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+ if (irq == NO_IRQ) {
+ dev_warn(&pdev->dev, "no interrupts listed in PAMU node\n");
+ goto error;
+ }
+
+ ret = request_irq(irq, pamu_av_isr, IRQF_DISABLED, "pamu", NULL);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "error %i installing ISR for irq %i\n",
+ ret, irq);
+ goto error;
+ }
+
+ guts_node = of_find_compatible_node(NULL, NULL,
+ "fsl,qoriq-device-config-1.0");
+ if (!guts_node) {
+ dev_err(&pdev->dev, "could not find GUTS node %s\n",
+ pdev->dev.of_node->full_name);
+ ret = -ENODEV;
+ goto error;
+ }
+
+ guts_regs = of_iomap(guts_node, 0);
+ of_node_put(guts_node);
+ if (!guts_regs) {
+ dev_err(&pdev->dev, "ioremap of GUTS node failed\n");
+ ret = -ENODEV;
+ goto error;
+ }
+
+ /*
+ * To simplify the allocation of a coherency domain, we allocate the
+ * PAACT and the OMT in the same memory buffer. Unfortunately, this
+ * wastes more memory compared to allocating the buffers separately.
+ */
+
+ /* Determine how much memory we need */
+ mem_size = (PAGE_SIZE << get_order(PAACT_SIZE)) +
+ (PAGE_SIZE << get_order(SPAACT_SIZE)) +
+ (PAGE_SIZE << get_order(OMT_SIZE));
+ order = get_order(mem_size);
+
+ p = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
+ if (!p) {
+ dev_err(&pdev->dev, "unable to allocate PAACT/SPAACT/OMT block\n");
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ ppaact = page_address(p);
+ ppaact_phys = page_to_phys(p);
+
+ /* Make sure the memory is naturally aligned */
+ if (ppaact_phys & ((PAGE_SIZE << order) - 1)) {
+ dev_err(&pdev->dev, "PAACT/OMT block is unaligned\n");
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ spaact = (void *)ppaact + (PAGE_SIZE << get_order(PAACT_SIZE));
+ omt = (void *)spaact + (PAGE_SIZE << get_order(SPAACT_SIZE));
+
+ dev_dbg(&pdev->dev, "ppaact virt=%p phys=0x%llx\n", ppaact,
+ (unsigned long long) ppaact_phys);
+
+ /* Check to see if we need to implement the work-around on this SOC */
+
+ /* Determine the Port ID for our coherence subdomain */
+ for (i = 0; i < ARRAY_SIZE(port_id_map); i++) {
+ if (port_id_map[i].svr == (mfspr(SPRN_SVR) & ~SVR_SECURITY)) {
+ csd_port_id = port_id_map[i].port_id;
+ dev_dbg(&pdev->dev, "found matching SVR %08x\n",
+ port_id_map[i].svr);
+ break;
+ }
+ }
+
+ if (csd_port_id) {
+ dev_dbg(&pdev->dev, "creating coherency subdomain at address "
+ "0x%llx, size %zu, port id 0x%08x", ppaact_phys,
+ mem_size, csd_port_id);
+
+ ret = create_csd(ppaact_phys, mem_size, csd_port_id);
+ if (ret) {
+ dev_err(&pdev->dev, "could not create coherence "
+ "subdomain\n");
+ return ret;
+ }
+ }
+
+ spaact_phys = virt_to_phys(spaact);
+ omt_phys = virt_to_phys(omt);
+
+ spaace_pool = gen_pool_create(ilog2(sizeof(paace_t)), -1);
+ if (!spaace_pool) {
+ ret = -ENOMEM;
+ pr_err("PAMU : failed to allocate spaace gen pool\n");
+ goto error;
+ }
+
+ ret = gen_pool_add(spaace_pool, (unsigned long)spaact, SPAACT_SIZE, -1);
+ if (ret)
+ goto error_genpool;
+
+ pamubypenr = in_be32(guts_regs + PAMUBYPENR);
+
+ for (pamu_reg_off = 0, pamu_counter = 0x80000000; pamu_reg_off < size;
+ pamu_reg_off += PAMU_OFFSET, pamu_counter >>= 1) {
+
+ pamu_reg_base = (unsigned long) pamu_regs + pamu_reg_off;
+ setup_one_pamu(pamu_reg_base, pamu_reg_off, ppaact_phys,
+ spaact_phys, omt_phys);
+ /* Disable PAMU bypass for this PAMU */
+ pamubypenr &= ~pamu_counter;
+ }
+
+ setup_omt(omt);
+
+ /* Enable all relevant PAMU(s) */
+ out_be32(guts_regs + PAMUBYPENR, pamubypenr);
+
+ iounmap(pamu_regs);
+ iounmap(guts_regs);
+
+ /* Enable DMA for the LIODNs in the device tree*/
+
+ setup_liodns();
+
+ return 0;
+
+error_genpool:
+ gen_pool_destroy(spaace_pool);
+
+error:
+ if (irq != NO_IRQ)
+ free_irq(irq, 0);
+
+ if (pamu_regs)
+ iounmap(pamu_regs);
+
+ if (guts_regs)
+ iounmap(guts_regs);
+
+ if (ppaact)
+ free_pages((unsigned long)ppaact, order);
+
+ ppaact = NULL;
+
+ return ret;
+}
+
+static const struct of_device_id fsl_of_pamu_ids[] = {
+ {
+ .compatible = "fsl,p4080-pamu",
+ },
+ {
+ .compatible = "fsl,pamu",
+ },
+ {},
+};
+
+static struct platform_driver fsl_of_pamu_driver = {
+ .driver = {
+ .name = "fsl-of-pamu",
+ .owner = THIS_MODULE,
+ },
+ .probe = fsl_pamu_probe,
+};
+
+static __init int fsl_pamu_init(void)
+{
+ struct platform_device *pdev = NULL;
+ struct device_node *np;
+ int ret;
+
+ /*
+ * The normal OF process calls the probe function at some
+ * indeterminate later time, after most drivers have loaded. This is
+ * too late for us, because PAMU clients (like the Qman driver)
+ * depend on PAMU being initialized early.
+ *
+ * So instead, we "manually" call our probe function by creating the
+ * platform devices ourselves.
+ */
+
+ /*
+ * We assume that there is only one PAMU node in the device tree. A
+ * single PAMU node represents all of the PAMU devices in the SOC
+ * already. Everything else already makes that assumption, and the
+ * binding for the PAMU nodes doesn't allow for any parent-child
+ * relationships anyway. In other words, support for more than one
+ * PAMU node would require significant changes to a lot of code.
+ */
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,pamu");
+ if (!np) {
+ pr_err("fsl-pamu: could not find a PAMU node\n");
+ return -ENODEV;
+ }
+
+ ret = platform_driver_register(&fsl_of_pamu_driver);
+ if (ret) {
+ pr_err("fsl-pamu: could not register driver (err=%i)\n", ret);
+ goto error_driver_register;
+ }
+
+ pdev = platform_device_alloc("fsl-of-pamu", 0);
+ if (!pdev) {
+ pr_err("fsl-pamu: could not allocate device %s\n",
+ np->full_name);
+ ret = -ENOMEM;
+ goto error_device_alloc;
+ }
+ pdev->dev.of_node = of_node_get(np);
+
+ ret = pamu_domain_init();
+ if (ret)
+ goto error_device_add;
+
+ ret = platform_device_add(pdev);
+ if (ret) {
+ pr_err("fsl-pamu: could not add device %s (err=%i)\n",
+ np->full_name, ret);
+ goto error_device_add;
+ }
+
+ return 0;
+
+error_device_add:
+ of_node_put(pdev->dev.of_node);
+ pdev->dev.of_node = NULL;
+
+ platform_device_put(pdev);
+
+error_device_alloc:
+ platform_driver_unregister(&fsl_of_pamu_driver);
+
+error_driver_register:
+ of_node_put(np);
+
+ return ret;
+}
+subsys_initcall(fsl_pamu_init);
diff --git a/drivers/iommu/fsl_pamu.h b/drivers/iommu/fsl_pamu.h
new file mode 100644
index 0000000..81eb9af
--- /dev/null
+++ b/drivers/iommu/fsl_pamu.h
@@ -0,0 +1,401 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef __FSL_PAMU_H
+#define __FSL_PAMU_H
+
+
+/* Bit Field macros
+ * v = bit field variable; m = mask, m##_SHIFT = shift, x = value to load
+ */
+#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << (m##_SHIFT)) & (m)))
+#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT))
+
+/* PAMU CCSR space */
+#define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
+#define PAMU_PE 0x40000000 /* enable PAMU */
+
+/* PAMU_OFFSET to the next pamu space in ccsr */
+#define PAMU_OFFSET 0x1000
+
+#define PAMU_MMAP_REGS_BASE 0
+
+struct pamu_mmap_regs {
+ u32 ppbah;
+ u32 ppbal;
+ u32 pplah;
+ u32 pplal;
+ u32 spbah;
+ u32 spbal;
+ u32 splah;
+ u32 splal;
+ u32 obah;
+ u32 obal;
+ u32 olah;
+ u32 olal;
+};
+
+/* PAMU Error Registers */
+#define PAMU_POES1 0x0040
+#define PAMU_POES2 0x0044
+#define PAMU_POEAH 0x0048
+#define PAMU_POEAL 0x004C
+#define PAMU_AVS1 0x0050
+#define PAMU_AVS1_AV 0x1
+#define PAMU_AVS1_OTV 0x6
+#define PAMU_AVS1_APV 0x78
+#define PAMU_AVS1_WAV 0x380
+#define PAMU_AVS1_LAV 0x1c00
+#define PAMU_AVS1_GCV 0x2000
+#define PAMU_AVS1_PDV 0x4000
+#define PAMU_AV_MASK (PAMU_AVS1_AV | PAMU_AVS1_OTV | PAMU_AVS1_APV | PAMU_AVS1_WAV \
+ | PAMU_AVS1_LAV | PAMU_AVS1_GCV | PAMU_AVS1_PDV)
+#define PAMU_AVS1_LIODN_SHIFT 16
+#define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400
+
+#define PAMU_AVS2 0x0054
+#define PAMU_AVAH 0x0058
+#define PAMU_AVAL 0x005C
+#define PAMU_EECTL 0x0060
+#define PAMU_EEDIS 0x0064
+#define PAMU_EEINTEN 0x0068
+#define PAMU_EEDET 0x006C
+#define PAMU_EEATTR 0x0070
+#define PAMU_EEAHI 0x0074
+#define PAMU_EEALO 0x0078
+#define PAMU_EEDHI 0X007C
+#define PAMU_EEDLO 0x0080
+#define PAMU_EECC 0x0084
+
+/* PAMU Revision Registers */
+#define PAMU_PR1 0x0BF8
+#define PAMU_PR2 0x0BFC
+
+/* PAMU Capabilities Registers */
+#define PAMU_PC1 0x0C00
+#define PAMU_PC2 0x0C04
+#define PAMU_PC3 0x0C08
+#define PAMU_PC4 0x0C0C
+
+/* PAMU Control Register */
+#define PAMU_PC 0x0C10
+
+/* PAMU control defs */
+#define PAMU_CONTROL 0x0C10
+#define PAMU_PC_PGC 0x80000000 /* 1 = PAMU Gate Closed : block all
+peripheral access, 0 : may allow peripheral access */
+
+#define PAMU_PC_PE 0x40000000 /* 0 = PAMU disabled, 1 = PAMU enabled */
+#define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */
+#define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */
+#define PAMU_PC_OCE 0x00001000 /* OMT cache enable */
+
+#define PAMU_PFA1 0x0C14
+#define PAMU_PFA2 0x0C18
+
+#define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf)
+
+/* PAMU Interrupt control and Status Register */
+#define PAMU_PICS 0x0C1C
+#define PAMU_ACCESS_VIOLATION_STAT 0x8
+#define PAMU_ACCESS_VIOLATION_ENABLE 0x4
+
+/* PAMU Debug Registers */
+#define PAMU_PD1 0x0F00
+#define PAMU_PD2 0x0F04
+#define PAMU_PD3 0x0F08
+#define PAMU_PD4 0x0F0C
+
+#define PAACE_AP_PERMS_DENIED 0x0
+#define PAACE_AP_PERMS_QUERY 0x1
+#define PAACE_AP_PERMS_UPDATE 0x2
+#define PAACE_AP_PERMS_ALL 0x3
+
+#define PAACE_DD_TO_HOST 0x0
+#define PAACE_DD_TO_IO 0x1
+#define PAACE_PT_PRIMARY 0x0
+#define PAACE_PT_SECONDARY 0x1
+#define PAACE_V_INVALID 0x0
+#define PAACE_V_VALID 0x1
+#define PAACE_MW_SUBWINDOWS 0x1
+
+#define PAACE_WSE_4K 0xB
+#define PAACE_WSE_8K 0xC
+#define PAACE_WSE_16K 0xD
+#define PAACE_WSE_32K 0xE
+#define PAACE_WSE_64K 0xF
+#define PAACE_WSE_128K 0x10
+#define PAACE_WSE_256K 0x11
+#define PAACE_WSE_512K 0x12
+#define PAACE_WSE_1M 0x13
+#define PAACE_WSE_2M 0x14
+#define PAACE_WSE_4M 0x15
+#define PAACE_WSE_8M 0x16
+#define PAACE_WSE_16M 0x17
+#define PAACE_WSE_32M 0x18
+#define PAACE_WSE_64M 0x19
+#define PAACE_WSE_128M 0x1A
+#define PAACE_WSE_256M 0x1B
+#define PAACE_WSE_512M 0x1C
+#define PAACE_WSE_1G 0x1D
+#define PAACE_WSE_2G 0x1E
+#define PAACE_WSE_4G 0x1F
+
+#define PAACE_DID_PCI_EXPRESS_1 0x00
+#define PAACE_DID_PCI_EXPRESS_2 0x01
+#define PAACE_DID_PCI_EXPRESS_3 0x02
+#define PAACE_DID_PCI_EXPRESS_4 0x03
+#define PAACE_DID_LOCAL_BUS 0x04
+#define PAACE_DID_SRIO 0x0C
+#define PAACE_DID_MEM_1 0x10
+#define PAACE_DID_MEM_2 0x11
+#define PAACE_DID_MEM_3 0x12
+#define PAACE_DID_MEM_4 0x13
+#define PAACE_DID_MEM_1_2 0x14
+#define PAACE_DID_MEM_3_4 0x15
+#define PAACE_DID_MEM_1_4 0x16
+#define PAACE_DID_BM_SW_PORTAL 0x18
+#define PAACE_DID_PAMU 0x1C
+#define PAACE_DID_CAAM 0x21
+#define PAACE_DID_QM_SW_PORTAL 0x3C
+#define PAACE_DID_CORE0_INST 0x80
+#define PAACE_DID_CORE0_DATA 0x81
+#define PAACE_DID_CORE1_INST 0x82
+#define PAACE_DID_CORE1_DATA 0x83
+#define PAACE_DID_CORE2_INST 0x84
+#define PAACE_DID_CORE2_DATA 0x85
+#define PAACE_DID_CORE3_INST 0x86
+#define PAACE_DID_CORE3_DATA 0x87
+#define PAACE_DID_CORE4_INST 0x88
+#define PAACE_DID_CORE4_DATA 0x89
+#define PAACE_DID_CORE5_INST 0x8A
+#define PAACE_DID_CORE5_DATA 0x8B
+#define PAACE_DID_CORE6_INST 0x8C
+#define PAACE_DID_CORE6_DATA 0x8D
+#define PAACE_DID_CORE7_INST 0x8E
+#define PAACE_DID_CORE7_DATA 0x8F
+#define PAACE_DID_BROADCAST 0xFF
+
+#define PAACE_ATM_NO_XLATE 0x00
+#define PAACE_ATM_WINDOW_XLATE 0x01
+#define PAACE_ATM_PAGE_XLATE 0x02
+#define PAACE_ATM_WIN_PG_XLATE \
+ ( PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE )
+#define PAACE_OTM_NO_XLATE 0x00
+#define PAACE_OTM_IMMEDIATE 0x01
+#define PAACE_OTM_INDEXED 0x02
+#define PAACE_OTM_RESERVED 0x03
+
+#define PAACE_M_COHERENCE_REQ 0x01
+
+#define PAACE_PID_0 0x0
+#define PAACE_PID_1 0x1
+#define PAACE_PID_2 0x2
+#define PAACE_PID_3 0x3
+#define PAACE_PID_4 0x4
+#define PAACE_PID_5 0x5
+#define PAACE_PID_6 0x6
+#define PAACE_PID_7 0x7
+
+#define PAACE_TCEF_FORMAT0_8B 0x00
+#define PAACE_TCEF_FORMAT1_RSVD 0x01
+
+#define PAACE_NUMBER_ENTRIES 0xFF
+
+#define OME_NUMBER_ENTRIES 16
+
+#define SPAACE_NUMBER_ENTRIES 0x8000
+
+/* PAACE Bit Field Defines */
+#define PPAACE_AF_WBAL 0xfffff000
+#define PPAACE_AF_WBAL_SHIFT 12
+#define PPAACE_AF_WSE 0x00000fc0
+#define PPAACE_AF_WSE_SHIFT 6
+#define PPAACE_AF_MW 0x00000020
+#define PPAACE_AF_MW_SHIFT 5
+
+#define SPAACE_AF_LIODN 0xffff0000
+#define SPAACE_AF_LIODN_SHIFT 16
+
+#define PAACE_AF_AP 0x00000018
+#define PAACE_AF_AP_SHIFT 3
+#define PAACE_AF_DD 0x00000004
+#define PAACE_AF_DD_SHIFT 2
+#define PAACE_AF_PT 0x00000002
+#define PAACE_AF_PT_SHIFT 1
+#define PAACE_AF_V 0x00000001
+#define PAACE_AF_V_SHIFT 0
+
+#define PAACE_DA_HOST_CR 0x80
+#define PAACE_DA_HOST_CR_SHIFT 7
+
+#define PAACE_IA_CID 0x00FF0000
+#define PAACE_IA_CID_SHIFT 16
+#define PAACE_IA_WCE 0x000000F0
+#define PAACE_IA_WCE_SHIFT 4
+#define PAACE_IA_ATM 0x0000000C
+#define PAACE_IA_ATM_SHIFT 2
+#define PAACE_IA_OTM 0x00000003
+#define PAACE_IA_OTM_SHIFT 0
+
+#define PAACE_WIN_TWBAL 0xfffff000
+#define PAACE_WIN_TWBAL_SHIFT 12
+#define PAACE_WIN_SWSE 0x00000fc0
+#define PAACE_WIN_SWSE_SHIFT 6
+
+/* PAMU Data Structures */
+/* primary / secondary paact structure */
+typedef struct paace_t {
+ /* PAACE Offset 0x00 */
+ u32 wbah; /* only valid for Primary PAACE */
+ u32 addr_bitfields; /* See P/S PAACE_AF_* */
+
+ /* PAACE Offset 0x08 */
+ /* Interpretation of first 32 bits dependent on DD above */
+ union {
+ struct {
+ /* Destination ID, see PAACE_DID_* defines */
+ u8 did;
+ /* Partition ID */
+ u8 pid;
+ /* Snoop ID */
+ u8 snpid;
+ /* coherency_required : 1 reserved : 7 */
+ u8 coherency_required; /* See PAACE_DA_* */
+ } to_host;
+ struct {
+ /* Destination ID, see PAACE_DID_* defines */
+ u8 did;
+ u8 reserved1;
+ u16 reserved2;
+ } to_io;
+ } domain_attr;
+
+ /* Implementation attributes + window count + address & operation translation modes */
+ u32 impl_attr; /* See PAACE_IA_* */
+
+ /* PAACE Offset 0x10 */
+ /* Translated window base address */
+ u32 twbah;
+ u32 win_bitfields; /* See PAACE_WIN_* */
+
+ /* PAACE Offset 0x18 */
+ /* first secondary paace entry */
+ u32 fspi; /* only valid for Primary PAACE */
+ union {
+ struct {
+ u8 ioea;
+ u8 moea;
+ u8 ioeb;
+ u8 moeb;
+ } immed_ot;
+ struct {
+ u16 reserved;
+ u16 omi;
+ } index_ot;
+ } op_encode;
+
+ /* PAACE Offsets 0x20-0x38 */
+ u32 reserved[8]; /* not currently implemented */
+} paace_t;
+
+/* OME : Operation mapping entry
+ * MOE : Mapped Operation Encodings
+ * The operation mapping table is table containing operation mapping entries (OME).
+ * The index of a particular OME is programmed in the PAACE entry for translation
+ * in bound I/O operations corresponding to an LIODN. The OMT is used for translation
+ * specifically in case of the indexed translation mode. Each OME contains a 128
+ * byte mapped operation encoding (MOE), where each byte represents an MOE.
+ */
+#define NUM_MOE 128
+struct ome {
+ u8 moe[NUM_MOE];
+} __attribute__((packed));
+
+#define PAACT_SIZE (sizeof(paace_t) * PAACE_NUMBER_ENTRIES)
+#define OMT_SIZE (sizeof(struct ome) * OME_NUMBER_ENTRIES)
+#define SPAACT_SIZE (sizeof(paace_t) * SPAACE_NUMBER_ENTRIES)
+
+#define PAMU_PAGE_SHIFT 12
+#define PAMU_PAGE_SIZE 4096ULL
+
+#define IOE_READ 0x00
+#define IOE_READ_IDX 0x00
+#define IOE_WRITE 0x81
+#define IOE_WRITE_IDX 0x01
+#define IOE_EREAD0 0x82 /* Enhanced read type 0 */
+#define IOE_EREAD0_IDX 0x02 /* Enhanced read type 0 */
+#define IOE_EWRITE0 0x83 /* Enhanced write type 0 */
+#define IOE_EWRITE0_IDX 0x03 /* Enhanced write type 0 */
+#define IOE_DIRECT0 0x84 /* Directive type 0 */
+#define IOE_DIRECT0_IDX 0x04 /* Directive type 0 */
+#define IOE_EREAD1 0x85 /* Enhanced read type 1 */
+#define IOE_EREAD1_IDX 0x05 /* Enhanced read type 1 */
+#define IOE_EWRITE1 0x86 /* Enhanced write type 1 */
+#define IOE_EWRITE1_IDX 0x06 /* Enhanced write type 1 */
+#define IOE_DIRECT1 0x87 /* Directive type 1 */
+#define IOE_DIRECT1_IDX 0x07 /* Directive type 1 */
+#define IOE_RAC 0x8c /* Read with Atomic clear */
+#define IOE_RAC_IDX 0x0c /* Read with Atomic clear */
+#define IOE_RAS 0x8d /* Read with Atomic set */
+#define IOE_RAS_IDX 0x0d /* Read with Atomic set */
+#define IOE_RAD 0x8e /* Read with Atomic decrement */
+#define IOE_RAD_IDX 0x0e /* Read with Atomic decrement */
+#define IOE_RAI 0x8f /* Read with Atomic increment */
+#define IOE_RAI_IDX 0x0f /* Read with Atomic increment */
+
+#define EOE_READ 0x00
+#define EOE_WRITE 0x01
+#define EOE_RAC 0x0c /* Read with Atomic clear */
+#define EOE_RAS 0x0d /* Read with Atomic set */
+#define EOE_RAD 0x0e /* Read with Atomic decrement */
+#define EOE_RAI 0x0f /* Read with Atomic increment */
+#define EOE_LDEC 0x10 /* Load external cache */
+#define EOE_LDECL 0x11 /* Load external cache with stash lock */
+#define EOE_LDECPE 0x12 /* Load external cache with preferred exclusive */
+#define EOE_LDECPEL 0x13 /* Load external cache with preferred exclusive and lock */
+#define EOE_LDECFE 0x14 /* Load external cache with forced exclusive */
+#define EOE_LDECFEL 0x15 /* Load external cache with forced exclusive and lock */
+#define EOE_RSA 0x16 /* Read with stash allocate */
+#define EOE_RSAU 0x17 /* Read with stash allocate and unlock */
+#define EOE_READI 0x18 /* Read with invalidate */
+#define EOE_RWNITC 0x19 /* Read with no intention to cache */
+#define EOE_WCI 0x1a /* Write cache inhibited */
+#define EOE_WWSA 0x1b /* Write with stash allocate */
+#define EOE_WWSAL 0x1c /* Write with stash allocate and lock */
+#define EOE_WWSAO 0x1d /* Write with stash allocate only */
+#define EOE_WWSAOL 0x1e /* Write with stash allocate only and lock */
+#define EOE_VALID 0x80
+
+/* Function prototypes */
+int pamu_domain_init(void);
+int pamu_enable_liodn(int liodn);
+int pamu_disable_liodn(int liodn);
+void pamu_free_subwins(int liodn);
+int pamu_config_ppaace(int liodn, phys_addr_t win_addr, phys_addr_t win_size,
+ u32 omi, unsigned long rpn, u32 snoopid, uint32_t stashid,
+ u32 subwin_cnt, int prot);
+int pamu_config_spaace(int liodn, u32 subwin_cnt, u32 subwin_addr,
+ phys_addr_t subwin_size, u32 omi, unsigned long rpn,
+ uint32_t snoopid, u32 stashid, int enable, int prot);
+
+u32 get_stash_id(u32 stash_dest_hint, u32 vcpu);
+void get_ome_index(u32 *omi_index, struct device *dev);
+int pamu_update_paace_stash(int liodn, u32 subwin, u32 value);
+
+#endif /* __FSL_PAMU_H */
diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c
new file mode 100644
index 0000000..d4a7b94
--- /dev/null
+++ b/drivers/iommu/fsl_pamu_domain.c
@@ -0,0 +1,1013 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Author: Varun Sethi <varun.sethi@freescale.com>
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/iommu.h>
+#include <linux/notifier.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/of_platform.h>
+#include <linux/bootmem.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+
+#include "fsl_pamu_domain.h"
+
+#define FSL_PAMU_PGSIZES (~0xFFFUL)
+
+/* global spinlock that needs to be held while
+ * configuring PAMU.
+ */
+DEFINE_SPINLOCK(iommu_lock);
+
+struct kmem_cache *fsl_pamu_domain_cache;
+struct kmem_cache *iommu_devinfo_cache;
+DEFINE_SPINLOCK(device_domain_lock);
+
+static inline void *alloc_devinfo_mem(void)
+{
+ return kmem_cache_alloc(iommu_devinfo_cache, GFP_KERNEL);
+}
+
+static inline void free_devinfo_mem(void *vaddr)
+{
+ kmem_cache_free(iommu_devinfo_cache, vaddr);
+}
+
+static inline int iommu_devinfo_cache_init(void)
+{
+ int ret = 0;
+
+ iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
+ sizeof(struct device_domain_info),
+ 0,
+ SLAB_HWCACHE_ALIGN,
+ NULL);
+ if (!iommu_devinfo_cache) {
+ pr_err("Couldn't create devinfo cache\n");
+ ret = -ENOMEM;
+ }
+
+ return ret;
+}
+
+static inline void *alloc_domain_mem(void)
+{
+ return kmem_cache_alloc(fsl_pamu_domain_cache, GFP_KERNEL);
+}
+
+static void free_domain_mem(void *vaddr)
+{
+ kmem_cache_free(fsl_pamu_domain_cache, vaddr);
+}
+
+static inline int iommu_domain_cache_init(void)
+{
+ int ret = 0;
+
+ fsl_pamu_domain_cache = kmem_cache_create("fsl_pamu_domain",
+ sizeof(struct fsl_dma_domain),
+ 0,
+ SLAB_HWCACHE_ALIGN,
+
+ NULL);
+ if (!fsl_pamu_domain_cache) {
+ pr_err("Couldn't create fsl iommu_domain cache\n");
+ ret = -ENOMEM;
+ }
+
+ return ret;
+}
+
+int __init iommu_init_mempool(void)
+{
+ int ret;
+
+ ret = iommu_domain_cache_init();
+ if (ret)
+ return ret;
+
+ ret = iommu_devinfo_cache_init();
+ if (!ret)
+ return ret;
+
+ kmem_cache_destroy(fsl_pamu_domain_cache);
+
+ return 0;
+}
+
+
+static int reconfig_win(int liodn, struct fsl_dma_domain *domain)
+{
+ int ret;
+
+ spin_lock(&iommu_lock);
+ ret = pamu_config_ppaace(liodn, domain->mapped_iova,
+ domain->mapped_size,
+ -1,
+ domain->paddr >> PAMU_PAGE_SHIFT,
+ domain->snoop_id, domain->stash_id,
+ 0, domain->prot);
+ spin_unlock(&iommu_lock);
+ if (ret) {
+ pr_err("PAMU PAACE configuration failed for liodn %d\n",
+ liodn);
+ }
+ return ret;
+}
+
+static void update_domain_subwin(struct fsl_dma_domain *dma_domain,
+ unsigned long iova, size_t size,
+ phys_addr_t paddr, int prot, int status)
+{
+ struct iommu_domain *domain = dma_domain->iommu_domain;
+ u32 subwin_cnt = dma_domain->subwin_cnt;
+ dma_addr_t geom_size = dma_domain->geom_size;
+ u32 subwin_size;
+ u32 mapped_subwin;
+ u32 mapped_subwin_cnt;
+ struct dma_subwindow *sub_win_ptr;
+ int i;
+
+ subwin_size = geom_size >> ilog2(subwin_cnt);
+ mapped_subwin = (iova - domain->geometry.aperture_start)
+ >> ilog2(subwin_size);
+ sub_win_ptr = &dma_domain->sub_win_arr[mapped_subwin];
+ mapped_subwin_cnt = (size < subwin_size) ? 1 :
+ size >> ilog2(subwin_size);
+ for (i = 0; i < mapped_subwin_cnt; i++) {
+ if (status) {
+ sub_win_ptr[i].paddr = paddr;
+ sub_win_ptr[i].size = (size < subwin_size) ?
+ size : subwin_size;
+ paddr += subwin_size;
+ sub_win_ptr[i].iova = iova;
+ iova += subwin_size;
+ }
+ sub_win_ptr[i].valid = status;
+ sub_win_ptr[i].prot = prot;
+ }
+
+ dma_domain->mapped_subwin = mapped_subwin;
+ dma_domain->mapped_subwin_cnt = mapped_subwin_cnt;
+}
+
+static int reconfig_subwin(int liodn, struct fsl_dma_domain *dma_domain)
+{
+ u32 subwin_cnt = dma_domain->subwin_cnt;
+ int ret = 0;
+ u32 mapped_subwin;
+ u32 mapped_subwin_cnt;
+ struct dma_subwindow *sub_win_ptr;
+ unsigned long rpn;
+ int i;
+
+ mapped_subwin = dma_domain->mapped_subwin;
+ mapped_subwin_cnt = dma_domain->mapped_subwin_cnt;
+ sub_win_ptr = &dma_domain->sub_win_arr[mapped_subwin];
+
+ for (i = 0; i < mapped_subwin_cnt; i++) {
+ rpn = sub_win_ptr[i].paddr >> PAMU_PAGE_SHIFT,
+
+ spin_lock(&iommu_lock);
+ ret = pamu_config_spaace(liodn, subwin_cnt, mapped_subwin,
+ sub_win_ptr[i].size,
+ -1,
+ rpn, dma_domain->snoop_id,
+ dma_domain->stash_id,
+ (mapped_subwin == 0 &&
+ !dma_domain->enabled) ?
+ 0 : sub_win_ptr[i].valid,
+ sub_win_ptr[i].prot);
+ spin_unlock(&iommu_lock);
+ if (ret) {
+ pr_err("PAMU SPAACE configuration failed for liodn %d\n",liodn);
+ return ret;
+ }
+ mapped_subwin++;
+ }
+
+ return ret;
+}
+
+static phys_addr_t get_phys_addr(struct fsl_dma_domain *dma_domain, unsigned long iova)
+{
+ u32 subwin_cnt = dma_domain->subwin_cnt;
+
+ if (subwin_cnt) {
+ int i;
+ struct dma_subwindow *sub_win_ptr =
+ &dma_domain->sub_win_arr[0];
+
+ for (i = 0; i < subwin_cnt; i++) {
+ if (sub_win_ptr[i].valid &&
+ iova >= sub_win_ptr[i].iova &&
+ iova < (sub_win_ptr[i].iova +
+ sub_win_ptr[i].size - 1))
+ return (sub_win_ptr[i].paddr + (iova &
+ (sub_win_ptr[i].size - 1)));
+ }
+ } else {
+ return (dma_domain->paddr + (iova & (dma_domain->mapped_size - 1)));
+ }
+
+ return 0;
+}
+
+static int map_liodn(int liodn, struct fsl_dma_domain *dma_domain)
+{
+ u32 subwin_cnt = dma_domain->subwin_cnt;
+ unsigned long rpn;
+ int ret = 0, i;
+
+ if (subwin_cnt) {
+ struct dma_subwindow *sub_win_ptr =
+ &dma_domain->sub_win_arr[0];
+ for (i = 0; i < subwin_cnt; i++) {
+ if (sub_win_ptr[i].valid) {
+ rpn = sub_win_ptr[i].paddr >>
+ PAMU_PAGE_SHIFT,
+ spin_lock(&iommu_lock);
+ ret = pamu_config_spaace(liodn, subwin_cnt, i,
+ sub_win_ptr[i].size,
+ -1,
+ rpn,
+ dma_domain->snoop_id,
+ dma_domain->stash_id,
+ (i > 0) ? 1 : 0,
+ sub_win_ptr[i].prot);
+ spin_unlock(&iommu_lock);
+ if (ret) {
+ pr_err("PAMU SPAACE configuration failed for liodn %d\n",
+ liodn);
+ return ret;
+ }
+ }
+ }
+ } else {
+
+ rpn = dma_domain->paddr >> PAMU_PAGE_SHIFT;
+ spin_lock(&iommu_lock);
+ ret = pamu_config_ppaace(liodn, dma_domain->mapped_iova,
+ dma_domain->mapped_size,
+ -1,
+ rpn,
+ dma_domain->snoop_id, dma_domain->stash_id,
+ 0, dma_domain->prot);
+ spin_unlock(&iommu_lock);
+ if (ret) {
+ pr_err("PAMU PAACE configuration failed for liodn %d\n",
+ liodn);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static int update_liodn(int liodn, struct fsl_dma_domain *dma_domain)
+{
+ int ret;
+
+ if (dma_domain->subwin_cnt) {
+ ret = reconfig_subwin(liodn, dma_domain);
+ if (ret)
+ pr_err("Subwindow reconfiguration failed for liodn %d\n", liodn);
+ } else {
+ ret = reconfig_win(liodn, dma_domain);
+ if (ret)
+ pr_err("Window reconfiguration failed for liodn %d\n", liodn);
+ }
+
+ return ret;
+}
+
+static int update_liodn_stash(int liodn, struct fsl_dma_domain *dma_domain,
+ u32 val)
+{
+ int ret = 0, i;
+
+ spin_lock(&iommu_lock);
+ if (!dma_domain->subwin_cnt) {
+ ret = pamu_update_paace_stash(liodn, 0, val);
+ if (ret) {
+ pr_err("Failed to update PAACE field for liodn %d\n ", liodn);
+ spin_unlock(&iommu_lock);
+ return ret;
+ }
+ } else {
+ for (i = 0; i < dma_domain->subwin_cnt; i++) {
+ ret = pamu_update_paace_stash(liodn, i, val);
+ if (ret) {
+ pr_err("Failed to update SPAACE %d field for liodn %d\n ", i, liodn);
+ spin_unlock(&iommu_lock);
+ return ret;
+ }
+ }
+ }
+ spin_unlock(&iommu_lock);
+
+ return ret;
+}
+
+static int configure_liodn(int liodn, struct device *dev,
+ struct fsl_dma_domain *dma_domain,
+ struct iommu_domain_geometry *geom_attr,
+ u32 subwin_cnt)
+{
+ phys_addr_t window_addr, window_size;
+ phys_addr_t subwin_size;
+ int ret = 0, i;
+ u32 omi_index = -1;
+
+ /* Configure the omi_index at the geometry setup time.
+ * This is a static value which depends on the type of
+ * device and would not change thereafter.
+ */
+ get_ome_index(&omi_index, dev);
+
+ window_addr = geom_attr->aperture_start;
+ window_size = geom_attr->aperture_end - geom_attr->aperture_start;
+
+ spin_lock(&iommu_lock);
+ ret = pamu_disable_liodn(liodn);
+ if (!ret)
+ ret = pamu_config_ppaace(liodn, window_addr, window_size, omi_index,
+ 0, dma_domain->snoop_id,
+ dma_domain->stash_id, subwin_cnt, 0);
+ spin_unlock(&iommu_lock);
+ if (ret) {
+ pr_err("PAMU PAACE configuration failed for liodn %d\n", liodn);
+ return ret;
+ }
+
+ if (subwin_cnt) {
+ subwin_size = window_size >> ilog2(subwin_cnt);
+ for (i = 0; i < subwin_cnt; i++) {
+ spin_lock(&iommu_lock);
+ ret = pamu_config_spaace(liodn, subwin_cnt, i, subwin_size,
+ omi_index, 0,
+ dma_domain->snoop_id,
+ dma_domain->stash_id, 0, 0);
+ spin_unlock(&iommu_lock);
+ if (ret) {
+ pr_err("PAMU SPAACE configuration failed for liodn %d\n", liodn);
+ return ret;
+ }
+ }
+ }
+
+ return ret;
+}
+
+static int check_size(u64 size, unsigned long iova)
+{
+ if ((size & (size - 1)) || size < PAMU_PAGE_SIZE) {
+ pr_err("%s: size too small or not a power of two\n", __func__);
+ return -EINVAL;
+ }
+
+ if (iova & (size - 1)) {
+ pr_err("%s: address is not aligned with window size\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static inline int check_size_align(u64 size, u64 subwin_size)
+{
+ return ((size < subwin_size) ? ((size & (size - 1)) ||
+ size < PAMU_PAGE_SIZE) :
+ (size & (subwin_size -1)));
+}
+
+
+static struct fsl_dma_domain *iommu_alloc_dma_domain(void)
+{
+ struct fsl_dma_domain *domain;
+
+ domain = alloc_domain_mem();
+ if (!domain)
+ return NULL;
+
+ memset(domain, 0, sizeof(struct fsl_dma_domain));
+
+ domain->stash_id = -1;
+ domain->snoop_id = -1;
+
+ INIT_LIST_HEAD(&domain->devices);
+
+ spin_lock_init(&domain->domain_lock);
+
+ return domain;
+}
+
+static struct fsl_dma_domain *find_domain(struct device *dev)
+{
+ struct device_domain_info *info = NULL;
+
+ info = dev->archdata.iommu_domain;
+ if (info)
+ return info->domain;
+ return NULL;
+}
+
+static void detach_domain(struct device *dev, struct fsl_dma_domain *dma_domain)
+{
+ struct device_domain_info *info;
+ struct list_head *entry, *tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dma_domain->domain_lock, flags);
+ if (!list_empty(&dma_domain->devices)) {
+ list_for_each_safe(entry, tmp, &dma_domain->devices) {
+ info = list_entry(entry, struct device_domain_info, link);
+ if (info->dev == dev) {
+ list_del(&info->link);
+ spin_lock(&iommu_lock);
+ pamu_disable_liodn(info->liodn);
+ spin_unlock(&iommu_lock);
+ dev->archdata.iommu_domain = NULL;
+ free_devinfo_mem(info);
+ }
+ }
+ }
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+}
+
+static void attach_domain(struct fsl_dma_domain *dma_domain, int liodn, struct device *dev)
+{
+ struct device_domain_info *info;
+ struct fsl_dma_domain *old_domain;
+
+ spin_lock(&device_domain_lock);
+ /* Check here if the device is already attached to domain or not.
+ * If the device is already attached to a domain detach it.
+ */
+ old_domain = find_domain(dev);
+ if (old_domain && old_domain != dma_domain)
+ detach_domain(dev, old_domain);
+
+ info = alloc_devinfo_mem();
+
+ info->dev = dev;
+ info->liodn = liodn;
+ info->domain = dma_domain;
+
+ list_add(&info->link, &dma_domain->devices);
+ /* In case of devices with multiple LIODNs just store
+ * the info for the first LIODN as all
+ * LIODNs share the same domain
+ */
+ if (old_domain && old_domain != dma_domain)
+ dev->archdata.iommu_domain = info;
+ spin_unlock(&device_domain_lock);
+
+}
+
+static phys_addr_t fsl_pamu_iova_to_phys(struct iommu_domain *domain,
+ unsigned long iova)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+
+ if ((iova < domain->geometry.aperture_start) ||
+ iova > (domain->geometry.aperture_end))
+ return 0;
+
+ return get_phys_addr(dma_domain, iova);
+}
+
+static int fsl_pamu_domain_has_cap(struct iommu_domain *domain,
+ unsigned long cap)
+{
+ if (cap == IOMMU_CAP_CACHE_COHERENCY)
+ return 1;
+
+ return 0;
+}
+
+static void destroy_domain(struct fsl_dma_domain *dma_domain)
+{
+ struct device_domain_info *info;
+
+ while (!list_empty(&dma_domain->devices)) {
+ info = list_entry(dma_domain->devices.next,
+ struct device_domain_info, link);
+ list_del(&info->link);
+ spin_lock(&iommu_lock);
+ if (dma_domain->subwin_cnt)
+ pamu_free_subwins(info->liodn);
+ pamu_disable_liodn(info->liodn);
+ spin_unlock(&iommu_lock);
+ spin_lock(&device_domain_lock);
+ info->dev->archdata.iommu_domain = NULL;
+ free_devinfo_mem(info);
+ spin_unlock(&device_domain_lock);
+ }
+}
+
+static void fsl_pamu_domain_destroy(struct iommu_domain *domain)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+
+ domain->priv = NULL;
+
+ destroy_domain(dma_domain);
+
+ dma_domain->enabled = 0;
+ dma_domain->valid = 0;
+ dma_domain->mapped = 0;
+
+ free_domain_mem(dma_domain);
+}
+
+static int fsl_pamu_domain_init(struct iommu_domain *domain)
+{
+ struct fsl_dma_domain *dma_domain;
+
+ dma_domain = iommu_alloc_dma_domain();
+ if (!dma_domain) {
+ pr_err("dma_domain allocation failed\n");
+ return -ENOMEM;
+ }
+ domain->priv = dma_domain;
+ dma_domain->iommu_domain = domain;
+ /* defaul geometry = 1MB */
+ domain->geometry.aperture_start = 0;
+ domain->geometry.aperture_end = 0x100000;
+ domain->geometry.subwindows = 0;
+ domain->geometry.force_aperture = true;
+
+ return 0;
+}
+
+static int configure_domain(struct fsl_dma_domain *dma_domain,
+ struct iommu_domain_geometry *geom_attr,
+ u32 subwin_cnt)
+{
+ struct device_domain_info *info;
+ int ret = 0;
+
+ list_for_each_entry(info, &dma_domain->devices, link) {
+ ret = configure_liodn(info->liodn, info->dev, dma_domain,
+ geom_attr, subwin_cnt);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
+static int update_domain_stash(struct fsl_dma_domain *dma_domain, u32 val)
+{
+ struct device_domain_info *info;
+ int ret = 0;
+
+ list_for_each_entry(info, &dma_domain->devices, link) {
+ ret = update_liodn_stash(info->liodn, dma_domain, val);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
+static int update_domain_mapping(struct fsl_dma_domain *domain)
+{
+ struct device_domain_info *info;
+ int ret = 0;
+
+ list_for_each_entry(info, &domain->devices, link) {
+ ret = update_liodn(info->liodn, domain);
+ if (ret)
+ break;
+ }
+ return ret;
+}
+
+static int fsl_pamu_map(struct iommu_domain *domain,
+ unsigned long iova, phys_addr_t paddr,
+ size_t size, int iommu_prot)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+ struct iommu_domain_geometry *geom_attr = &domain->geometry;
+ int prot = 0;
+ unsigned long flags;
+ int ret = 0;
+
+
+ if (iommu_prot & IOMMU_READ)
+ prot |= PAACE_AP_PERMS_QUERY;
+ if (iommu_prot & IOMMU_WRITE)
+ prot |= PAACE_AP_PERMS_UPDATE;
+
+ spin_lock_irqsave(&dma_domain->domain_lock, flags);
+ if (dma_domain->valid) {
+ if (dma_domain->subwin_cnt) {
+ u32 align_check, subwin_size;
+ dma_addr_t geom_size = dma_domain->geom_size;
+
+ subwin_size = geom_size >> ilog2(dma_domain->subwin_cnt);
+ align_check = check_size(subwin_size, iova) ||
+ check_size_align(size, subwin_size);
+ if ((iova >= geom_attr->aperture_start &&
+ iova < geom_attr->aperture_end - 1 &&
+ size <= geom_size) &&
+ !align_check) {
+ update_domain_subwin(dma_domain, iova, size, paddr, prot, 1);
+ } else {
+ pr_err("Mismatch between geometry and mapping\n");
+ ret = -EINVAL;
+ }
+ } else {
+ ret = check_size(size, iova);
+ if (!ret && !dma_domain->enabled) {
+ dma_domain->mapped_iova = iova;
+ dma_domain->mapped_size = size;
+ dma_domain->paddr = paddr;
+ dma_domain->prot = prot;
+ } else {
+ pr_err("Can't create mapping, %s\n",
+ (ret) ? "Invalid size" : "DMA enabled");
+ ret = ret ? ret : -EBUSY;
+ }
+ }
+
+ if (!ret) {
+ ret = update_domain_mapping(dma_domain);
+ if (!ret)
+ dma_domain->mapped = 1;
+ }
+ } else {
+ pr_err("Set domain geometry before creating the mapping\n");
+ ret = -ENODEV;
+ }
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+
+ return ret;
+}
+
+static size_t fsl_pamu_unmap(struct iommu_domain *domain, unsigned long iova, size_t size)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+ struct iommu_domain_geometry *geom_attr = &domain->geometry;
+ size_t ret = size;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dma_domain->domain_lock, flags);
+ if (dma_domain->valid && dma_domain->mapped) {
+ if (dma_domain->subwin_cnt) {
+ u32 align_check, subwin_size;
+ dma_addr_t geom_size = dma_domain->geom_size;
+
+ subwin_size = geom_size >> ilog2(dma_domain->subwin_cnt);
+ align_check = check_size(subwin_size, iova) ||
+ check_size_align(size, subwin_size);
+ if ((iova >= geom_attr->aperture_start &&
+ iova < geom_attr->aperture_end - 1 &&
+ size <= geom_size) &&
+ !align_check) {
+ update_domain_subwin(dma_domain, iova, size, 0,
+ PAACE_AP_PERMS_DENIED, 0);
+ } else {
+ pr_err("Invalid address/size alignment\n");
+ ret = -EINVAL;
+ }
+ } else {
+ if (!dma_domain->enabled) {
+ u64 max_addr, unmap_range;
+ size_t domain_size;
+ unsigned long domain_iova;
+
+ unmap_range = iova + size;
+ domain_iova = dma_domain->mapped_iova;
+ domain_size = dma_domain->mapped_size;
+ max_addr = domain_iova + domain_size;
+
+ if ((domain_iova != iova &&
+ (max_addr < unmap_range ||
+ max_addr > unmap_range)) ||
+ size > domain_size ||
+ iova < domain_iova) {
+ pr_err("Invalid size/address parameters for unmap\n");
+ ret = -EINVAL;
+ } else {
+ domain_size -= size;
+ if (iova == domain_iova)
+ domain_iova += size;
+ ret = check_size(domain_size, domain_iova);
+ if (!ret) {
+ dma_domain->mapped_iova = domain_iova;
+ dma_domain->mapped_size = domain_size;
+ if (!domain_size)
+ dma_domain->mapped = 0;
+ }
+ }
+ } else {
+ pr_err("Can't update mapping with DMA enabled\n");
+ ret = -EBUSY;
+ }
+ }
+ if (ret == size)
+ update_domain_mapping(dma_domain);
+ } else {
+ pr_err("Can't unmap an invalid domain\n");
+ ret = -ENODEV;
+ }
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+
+ return ret;
+}
+
+static int handle_attach_device(struct fsl_dma_domain *dma_domain,
+ struct device *dev, const u32 *liodn,
+ int num)
+{
+ unsigned long flags;
+ struct iommu_domain *domain = dma_domain->iommu_domain;
+ int ret = 0;
+ int i;
+
+ spin_lock_irqsave(&dma_domain->domain_lock, flags);
+ for (i = 0; i < num; i++) {
+ attach_domain(dma_domain, liodn[i], dev);
+ if (dma_domain->valid) {
+ ret = configure_liodn(liodn[i], dev, dma_domain,
+ &domain->geometry,
+ dma_domain->subwin_cnt);
+ if (ret)
+ break;
+ if (dma_domain->mapped) {
+ ret = map_liodn(liodn[i], dma_domain);
+ if (ret)
+ break;
+ }
+ }
+ }
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+
+ return ret;
+}
+
+static int fsl_pamu_attach_device(struct iommu_domain *domain,
+ struct device *dev)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+ const u32 *prop;
+ u32 prop_cnt;
+ int len, ret = 0;
+
+ prop = of_get_property(dev->of_node, "fsl,liodn", &len);
+ if (prop) {
+ prop_cnt = len / sizeof(u32);
+ ret = handle_attach_device(dma_domain, dev,
+ prop, prop_cnt);
+ } else {
+ pr_err("missing fsl,liodn property at %s\n",
+ dev->of_node->full_name);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static void fsl_pamu_detach_device(struct iommu_domain *domain,
+ struct device *dev)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+ const u32 *prop;
+ int len;
+
+ prop = of_get_property(dev->of_node, "fsl,liodn", &len);
+ if (prop)
+ detach_domain(dev, dma_domain);
+ else
+ pr_err("missing fsl,liodn property at %s\n",
+ dev->of_node->full_name);
+}
+
+static int get_subwin_cnt(dma_addr_t geom_size, u32 subwin, u32 *subwin_cnt)
+{
+
+ switch (subwin) {
+ case 0:
+ /* We can't support geometry size > 1MB*/
+ if (geom_size != 1024 * 1024)
+ return 0;
+ *subwin_cnt = 256;
+ break;
+ case 1:
+ /* No subwindows only a single PAMU window */
+ *subwin_cnt = 0;
+ break;
+ default:
+ if (subwin > max_subwindow_count ||
+ (subwin & (subwin - 1)))
+ return 0;
+ *subwin_cnt = subwin;
+ }
+ return 1;
+}
+
+static int configure_domain_geometry(struct iommu_domain *domain, void *data)
+{
+ int ret = 0;
+ struct iommu_domain_geometry *geom_attr = data;
+ struct fsl_dma_domain *dma_domain = domain->priv;
+ dma_addr_t geom_size;
+ u32 subwin_cnt;
+ unsigned long flags;
+
+ geom_size = geom_attr->aperture_end - geom_attr->aperture_start;
+
+ if (check_size(geom_size, geom_attr->aperture_start) ||
+ !geom_attr->force_aperture ||
+ !get_subwin_cnt(geom_size, geom_attr->subwindows,
+ &subwin_cnt)) {
+ pr_err("Invalid PAMU geometry attributes\n");
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&dma_domain->domain_lock, flags);
+ if (dma_domain->enabled) {
+ pr_err("Can't set geometry attributes as domain is active\n");
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+ return -EBUSY;
+ }
+ ret = configure_domain(dma_domain, geom_attr, subwin_cnt);
+ if (!ret) {
+ if (subwin_cnt) {
+ if (dma_domain->sub_win_arr)
+ kfree(dma_domain->sub_win_arr);
+ dma_domain->sub_win_arr = kmalloc(sizeof(struct dma_subwindow) *
+ subwin_cnt, GFP_KERNEL);
+ if (!dma_domain->sub_win_arr) {
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+ return -ENOMEM;
+ }
+ }
+ memcpy(&domain->geometry, geom_attr,
+ sizeof(struct iommu_domain_geometry));
+ dma_domain->geom_size = geom_size;
+ dma_domain->subwin_cnt = subwin_cnt;
+ dma_domain->valid = 1;
+ }
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+
+ return ret;
+}
+
+static int configure_domain_stash(struct fsl_dma_domain *dma_domain, void *data)
+{
+ struct iommu_stash_attribute *stash_attr = data;
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&dma_domain->domain_lock, flags);
+
+ memcpy(&dma_domain->dma_stash, stash_attr,
+ sizeof(struct iommu_stash_attribute));
+
+ dma_domain->stash_id = get_stash_id(stash_attr->cache,
+ stash_attr->cpu);
+ if (dma_domain->stash_id == ~(u32)0) {
+ pr_err("Invalid stash attributes\n");
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+ return -EINVAL;
+ }
+
+ ret = update_domain_stash(dma_domain, dma_domain->stash_id);
+
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+
+ return ret;
+}
+
+static int configure_domain_dma_state(struct fsl_dma_domain *dma_domain, int enable)
+{
+ struct device_domain_info *info;
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&dma_domain->domain_lock, flags);
+
+ if (enable && !dma_domain->mapped) {
+ pr_err("Can't enable DMA domain without valid mapping\n");
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+ return -ENODEV;
+ }
+
+ dma_domain->enabled = enable;
+ if (!list_empty(&dma_domain->devices)) {
+ list_for_each_entry(info, &dma_domain->devices,
+ link) {
+ ret = (enable) ? pamu_enable_liodn(info->liodn):
+ pamu_disable_liodn(info->liodn);
+ if (ret)
+ pr_err("Unable to set dma state for liodn %d",
+ info->liodn);
+ }
+ }
+ spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
+
+ return 0;
+}
+
+int fsl_pamu_set_domain_attr(struct iommu_domain *domain,
+ enum iommu_attr attr_type, void *data)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+ int ret = 0;
+
+
+ switch(attr_type) {
+ case DOMAIN_ATTR_GEOMETRY:
+ ret = configure_domain_geometry(domain, data);
+ break;
+ case DOMAIN_ATTR_STASH:
+ ret = configure_domain_stash(dma_domain, data);
+ break;
+ case DOMAIN_ATTR_ENABLE:
+ ret = configure_domain_dma_state(dma_domain, *(int *)data);
+ break;
+ default:
+ pr_err("Unsupported attribute type\n");
+ ret = -EINVAL;
+ break;
+ };
+
+ return ret;
+}
+
+int fsl_pamu_get_domain_attr(struct iommu_domain *domain,
+ enum iommu_attr attr_type, void *data)
+{
+ struct fsl_dma_domain *dma_domain = domain->priv;
+ int ret = 0;
+
+
+ switch(attr_type) {
+ case DOMAIN_ATTR_STASH:
+ memcpy((struct iommu_stash_attribute *) data, &dma_domain->dma_stash,
+ sizeof(struct iommu_stash_attribute));
+ break;
+ case DOMAIN_ATTR_ENABLE:
+ *(int *)data = dma_domain->enabled;
+ break;
+ default:
+ pr_err("Unsupported attribute type\n");
+ ret = -EINVAL;
+ break;
+ };
+
+ return ret;
+}
+
+static struct iommu_ops fsl_pamu_ops = {
+ .domain_init = fsl_pamu_domain_init,
+ .domain_destroy = fsl_pamu_domain_destroy,
+ .attach_dev = fsl_pamu_attach_device,
+ .detach_dev = fsl_pamu_detach_device,
+ .map = fsl_pamu_map,
+ .unmap = fsl_pamu_unmap,
+ .iova_to_phys = fsl_pamu_iova_to_phys,
+ .domain_has_cap = fsl_pamu_domain_has_cap,
+ .domain_set_attr = fsl_pamu_set_domain_attr,
+ .domain_get_attr = fsl_pamu_get_domain_attr,
+ .pgsize_bitmap = FSL_PAMU_PGSIZES,
+};
+
+int pamu_domain_init()
+{
+ int ret = 0;
+
+ ret = iommu_init_mempool();
+ if (ret)
+ return ret;
+
+ bus_set_iommu(&platform_bus_type, &fsl_pamu_ops);
+
+ return ret;
+}
diff --git a/drivers/iommu/fsl_pamu_domain.h b/drivers/iommu/fsl_pamu_domain.h
new file mode 100644
index 0000000..840e5b6
--- /dev/null
+++ b/drivers/iommu/fsl_pamu_domain.h
@@ -0,0 +1,96 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef __FSL_PAMU_DOMAIN_H
+#define __FSL_PAMU_DOMAIN_H
+
+#include "fsl_pamu.h"
+
+struct dma_subwindow {
+ unsigned long iova;
+ phys_addr_t paddr;
+ size_t size;
+ int valid;
+ int prot;
+};
+
+struct fsl_dma_domain {
+ /* mapped_iova and mapped_size are used in case there are
+ * no subwindows associated with the domain. These are
+ * updated on each iommu_map/iommu_unmap call. Based
+ * on these values the corresponding PPAACE entry is
+ * updated.
+ */
+ unsigned long mapped_iova;
+ size_t mapped_size;
+ /* physical address mapping */
+ u64 paddr;
+ /* mapped_subwin/mapped_subwin_cnt are only valid if
+ * the domain geometry has subwindows. These fields
+ * are updated on each iommu_map/iommu_unmap call.
+ * Based on these values the corresponding SPAACE
+ * entries are updated.
+ */
+ u32 mapped_subwin;
+ u32 mapped_subwin_cnt;
+ /* Access permission associated with the domain */
+ int prot;
+ /* number of subwindows assocaited with this domain */
+ u32 subwin_cnt;
+ /* sub_win_arr contains information of the configured
+ * subwindows for a domain.
+ */
+ struct dma_subwindow *sub_win_arr;
+ /* list of devices associated with the domain */
+ struct list_head devices;
+ /* dma_domain states:
+ * valid - Geometry attribute has been configured.
+ * mapped - A particular mapping has been created
+ * within the configured geometry. Domain has to
+ * be in the valid state before any DMA mapping
+ * can be created in it.
+ * enabled - DMA has been enabled for the given
+ * domain. This translates to setting of the
+ * valid bit for the primary PAACE in the PAMU
+ * PAACT table. Domain should be valid and have
+ * a valid mapping before DMA can be enabled for it.
+ *
+ */
+ int valid;
+ int mapped;
+ int enabled;
+ /* stash_id obtained from the stash attribute details */
+ u32 stash_id;
+ struct iommu_stash_attribute dma_stash;
+ u32 snoop_id;
+ dma_addr_t geom_size;
+ struct iommu_domain *iommu_domain;
+ spinlock_t domain_lock;
+};
+
+/* domain-device relationship */
+struct device_domain_info {
+ struct list_head link; /* link to domain siblings */
+ struct device *dev;
+ u32 liodn;
+ struct fsl_dma_domain *domain; /* pointer to domain */
+};
+
+extern unsigned int max_subwindow_count;
+
+#endif /* __FSL_PAMU_DOMAIN_H */
--
1.7.4.1
^ permalink raw reply related
* [PATCH 2/3 v2] iommu/fsl: Add iommu domain attributes required by fsl PAMU driver.
From: b16395 @ 2012-10-04 11:56 UTC (permalink / raw)
To: joerg.roedel, iommu, linuxppc-dev, linux-kernel; +Cc: Varun Sethi
In-Reply-To: <1349351808-7156-1-git-send-email-b16395@freescale.com>
From: Varun Sethi <Varun.Sethi@freescale.com>
Added the following domain attributes required by FSL PAMU driver:
1. Subwindows field added to the iommu domain geometry attribute.
2. Added new iommu stash attribute, which allows setting of the
LIODN specific stash id parameter through IOMMU API.
3. Added an attribute for enabling/disabling DMA to a particular
memory window.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
---
include/linux/iommu.h | 35 +++++++++++++++++++++++++++++++++++
1 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index f3b99e1..62e22f0 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -44,6 +44,33 @@ struct iommu_domain_geometry {
dma_addr_t aperture_start; /* First address that can be mapped */
dma_addr_t aperture_end; /* Last address that can be mapped */
bool force_aperture; /* DMA only allowed in mappable range? */
+
+ /* The subwindows field indicates number of DMA subwindows supported
+ * by the geometry. Following is the interpretation of
+ * values for this field:
+ * 0 : This implies that the supported geometry size is 1 MB
+ * with each subwindow size being 4KB. Thus number of subwindows
+ * being = 1MB/4KB = 256.
+ * 1 : Only one DMA window i.e. no subwindows.
+ * value other than 0 or 1 would indicate actual number of subwindows.
+ */
+ u32 subwindows;
+};
+
+/* cache stash targets */
+#define L1_CACHE 1
+#define L2_CACHE 2
+#define L3_CACHE 3
+
+/* This attribute corresponds to IOMMUs capable of generating
+ * a stash transaction. A stash transaction is typically a
+ * hardware initiated prefetch of data from memory to cache.
+ * This attribute allows configuring stashig specific parameters
+ * in the IOMMU hardware.
+ */
+struct iommu_stash_attribute {
+ u32 cpu; /* cpu number */
+ u32 cache; /* cache to stash to: L1,L2,L3 */
};
struct iommu_domain {
@@ -60,6 +87,14 @@ struct iommu_domain {
enum iommu_attr {
DOMAIN_ATTR_MAX,
DOMAIN_ATTR_GEOMETRY,
+ /* Set the IOMMU hardware stashing
+ * parameters.
+ */
+ DOMAIN_ATTR_STASH,
+ /* Explicity enable/disable DMA for a
+ * particular memory window.
+ */
+ DOMAIN_ATTR_ENABLE,
};
#ifdef CONFIG_IOMMU_API
--
1.7.4.1
^ permalink raw reply related
* [PATCH 0/3 v2] iommu/fsl: Freescale PAMU driver and IOMMU API implementation.
From: b16395 @ 2012-10-04 11:56 UTC (permalink / raw)
To: joerg.roedel, iommu, linuxppc-dev, linux-kernel; +Cc: Varun Sethi
From: Varun Sethi <Varun.Sethi@freescale.com>
This patchset provides the Freescale PAMU (Peripheral Access Management Unit) driver
and the corresponding IOMMU API implementation. PAMU is the IOMMU present on Freescale
QorIQ platforms. PAMU can authorize memory access, remap the memory address, and remap
the I/O transaction type.
This set consists of the following patches:
1. Addition of new field in the device (powerpc) archdata structure for storing iommu domain information
pointer. This pointer is stored when the device is attached to a particular iommu domain.
2. Addition of domain attributes required by the PAMU driver IOMMU API.
3. PAMU driver and IOMMU API implementation.
This patch set is based on the next branch of the iommu git tree maintained by Joerg.
Varun Sethi (3):
Store iommu domain information pointer in archdata.
Add iommu domain attributes required by fsl PAMU driver.
FSL PAMU driver and IOMMU API implementation.
arch/powerpc/include/asm/device.h | 4 +
drivers/iommu/Kconfig | 7 +
drivers/iommu/Makefile | 1 +
drivers/iommu/fsl_pamu.c | 1033 +++++++++++++++++++++++++++++++++++++
drivers/iommu/fsl_pamu.h | 377 ++++++++++++++
drivers/iommu/fsl_pamu_domain.c | 990 +++++++++++++++++++++++++++++++++++
drivers/iommu/fsl_pamu_domain.h | 94 ++++
drivers/iommu/fsl_pamu_proto.h | 49 ++
include/linux/iommu.h | 30 ++
9 files changed, 2585 insertions(+), 0 deletions(-)
create mode 100644 drivers/iommu/fsl_pamu.c
create mode 100644 drivers/iommu/fsl_pamu.h
create mode 100644 drivers/iommu/fsl_pamu_domain.c
create mode 100644 drivers/iommu/fsl_pamu_domain.h
create mode 100644 drivers/iommu/fsl_pamu_proto.h
--
1.7.4.1
^ permalink raw reply
* [PATCH 1/3 v2] iommu/fsl: Store iommu domain information pointer in archdata.
From: b16395 @ 2012-10-04 11:56 UTC (permalink / raw)
To: joerg.roedel, iommu, linuxppc-dev, linux-kernel; +Cc: Varun Sethi
In-Reply-To: <1349351808-7156-1-git-send-email-b16395@freescale.com>
From: Varun Sethi <Varun.Sethi@freescale.com>
Add a new field in the device (powerpc) archdata structure for storing iommu domain
information pointer. This pointer is stored when the device is attached to a particular
domain.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
---
arch/powerpc/include/asm/device.h | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index 77e97dd..6dc79fe 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -28,6 +28,10 @@ struct dev_archdata {
void *iommu_table_base;
} dma_data;
+ /* IOMMU domain information pointer. This would be set
+ * when this device is attached to an iommu_domain.
+ */
+ void *iommu_domain;
#ifdef CONFIG_SWIOTLB
dma_addr_t max_direct_dma_addr;
#endif
--
1.7.4.1
^ permalink raw reply related
* Re: [PATCH] PPC: Correct the tophys/tovirt macros
From: Benjamin Herrenschmidt @ 2012-10-04 11:19 UTC (permalink / raw)
To: Jason Gunthorpe; +Cc: linuxppc-dev
In-Reply-To: <20120930232847.GG30637@obsidianresearch.com>
On Sun, 2012-09-30 at 17:28 -0600, Jason Gunthorpe wrote:
> asm/page.h discusses the calculation for v2p and p2v, it should be:
> va = pa + KERNELBASE - PHYSICAL_START
> which is the same as:
> va = pa + LOAD_OFFSET
>
> tophys/tovirt were using PAGE_OFFSET, which as page.h says, is almost
> always the same thing.
>
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
It's a bit gross tho in that KERNEL_BASE, PHYSICAL_START and LOAD_OFFSET
are about where the kernel is linked/running, and while the value ends
up happening to also be the p->v offset (and indeed not by accident), it
makes the code less clear and more confusing.
I think the main issue is that we did things wrong when implementing
non-0 based setups. PAGE_OFFSET should have remained what its name
implies which is the offset between p and v.
I don't have the bandwidth to revisit all that, but I really think that
whole are area where PAGE_OFFSET doesn't map 0 needs revisiting.
Ben.
> ---
> arch/powerpc/include/asm/ppc_asm.h | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
> index ea2a86e..44edc3a 100644
> --- a/arch/powerpc/include/asm/ppc_asm.h
> +++ b/arch/powerpc/include/asm/ppc_asm.h
> @@ -461,14 +461,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
> #define fromreal(rd) tovirt(rd,rd)
>
> #define tophys(rd,rs) \
> -0: addis rd,rs,-PAGE_OFFSET@h; \
> +0: addis rd,rs,-LOAD_OFFSET@h; \
> .section ".vtop_fixup","aw"; \
> .align 1; \
> .long 0b; \
> .previous
>
> #define tovirt(rd,rs) \
> -0: addis rd,rs,PAGE_OFFSET@h; \
> +0: addis rd,rs,LOAD_OFFSET@h; \
> .section ".ptov_fixup","aw"; \
> .align 1; \
> .long 0b; \
^ permalink raw reply
* Re: [PATCH] PPC: Enable the Watchdog vector for 405
From: Benjamin Herrenschmidt @ 2012-10-04 11:05 UTC (permalink / raw)
To: Jason Gunthorpe; +Cc: linuxppc-dev
In-Reply-To: <20120930232723.GF30637@obsidianresearch.com>
On Sun, 2012-09-30 at 17:27 -0600, Jason Gunthorpe wrote:
> diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
> index 4989661..7edd7b1 100644
> --- a/arch/powerpc/kernel/head_40x.S
> +++ b/arch/powerpc/kernel/head_40x.S
> @@ -431,29 +431,19 @@ label:
>
> /* 0x1000 - Programmable Interval Timer (PIT) Exception */
> START_EXCEPTION(0x1000, Decrementer)
> - NORMAL_EXCEPTION_PROLOG
> - lis r0,TSR_PIS@h
> - mtspr SPRN_TSR,r0 /* Clear the PIT exception */
> - addi r3,r1,STACK_FRAME_OVERHEAD
> - EXC_XFER_LITE(0x1000, timer_interrupt)
> + b pit_longer
Looks like you indeed have no choice but move it down, though I dislike
the label name :-)
Look at how we do a similar thing in exceptions-64.S, we basically just
don't use START_EXCEPTION at that location. We put a .=xxxx and a
branch, and use the real exception name at the target label.
Or just name it "pit_exception" if you want to keep things simple. I
just don't like "pit_longer" :-)
> -#if 0
> /* NOTE:
> - * FIT and WDT handlers are not implemented yet.
> + * FIT handler is not implemented yet.
> */
Any reason to comment that out ? Better off also branching out of line
to a stub similar to the PIT one that then calls unknown_exception. That
way if it triggers by accident, you'll get a clean trace.
> /* 0x1010 - Fixed Interval Timer (FIT) Exception
> */
> - STND_EXCEPTION(0x1010, FITException, unknown_exception)
> +// STND_EXCEPTION(0x1010, FITException, unknown_exception)
>
> /* 0x1020 - Watchdog Timer (WDT) Exception
> */
> -#ifdef CONFIG_BOOKE_WDT
> CRITICAL_EXCEPTION(0x1020, WDTException, WatchdogException)
> -#else
> - CRITICAL_EXCEPTION(0x1020, WDTException, unknown_exception)
> -#endif
> -#endif
Move it out of line too please. When a given vector "slot" gets crowded,
I prefer moving everything in it out of line to keep things consistent.
> /* 0x1100 - Data TLB Miss Exception
> * As the name implies, translation is not in the MMU, so search the
> @@ -738,6 +728,16 @@ label:
> (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
> NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
>
> + /* Programmable Interval Timer (PIT) Exception. The PIT runs into
> + the space reserved for other exceptions, so we branch down
> + to here. */
> +pit_longer:
> + NORMAL_EXCEPTION_PROLOG
> + lis r0,TSR_PIS@h
> + mtspr SPRN_TSR,r0 /* Clear the PIT exception */
> + addi r3,r1,STACK_FRAME_OVERHEAD
> + EXC_XFER_LITE(0x1000, timer_interrupt)
> +
> /*
> * The other Data TLB exceptions bail out to this point
> * if they can't resolve the lightweight TLB fault.
> diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
> index ae0843f..0701ec1 100644
> --- a/arch/powerpc/kernel/traps.c
> +++ b/arch/powerpc/kernel/traps.c
> @@ -1514,7 +1514,7 @@ void unrecoverable_exception(struct pt_regs *regs)
> die("Unrecoverable exception", regs, SIGABRT);
> }
>
> -#ifdef CONFIG_BOOKE_WDT
> +#if defined(CONFIG_BOOKE_WDT) | defined(CONFIG_40x)
> /*
> * Default handler for a Watchdog exception,
> * spins until a reboot occurs
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc/iommu: Fix multiple issues with IOMMU pools code
From: Alexander Graf @ 2012-10-04 10:54 UTC (permalink / raw)
To: Anton Blanchard
Cc: linux-nfs, Jan Kara, Nishanth Aravamudan, linuxppc-dev, LKML List,
J. Bruce Fields, skinsbursky, bfields, Linus Torvalds
In-Reply-To: <20121004145710.2cf95dcd@kryten>
Hi Anton,
On 04.10.2012, at 06:57, Anton Blanchard wrote:
>
> Hi Alex,
>
> Looks to be a preempt issue with the iommu pools code. I did find a
> couple more bugs along the way too.
>
> Anton
> --
>
> There are a number of issues in the recent IOMMU pools code:
>
> - On a preempt kernel we might switch CPUs in the middle of building
> a scatter gather list. When this happens the handle hint passed in
> no longer falls within the local CPU's pool. Check for this and
> fall back to the pool hint.
>
> - We were missing a spin_unlock/spin_lock in one spot where we
> switch pools.
>
> - We need to provide locking around dart_tlb_invalidate_all and
> dart_tlb_invalidate_one now that the global lock is gone.
>
> Reported-by: Alexander Graf <agraf@suse.de>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
>
> There is still an issue with the lazy u3 flushing, but I wanted
> to get this out for testing.
Yup. It fixes the nfs problem on my U4 based machine.
Tested-by: Alexander Graf <agraf@suse.de>
Alex
^ permalink raw reply
* [git pull] Please pull powerpc.git merge branch
From: Benjamin Herrenschmidt @ 2012-10-04 8:38 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev list, Linux Kernel list
Hi Linus !
A couple of days late on my expectations due to chasing a nasty regression,
and here is the powerpc batch for 3.7.
First, however, a note about the pull request details ... the diffstat looks
completely on crack, any idea what's up ? It sees piles of files modified
in various other archs & generic code but I see no patch in that branch
that touches any of them.
Example:
arch/alpha/Kconfig | 2 +
But if I do:
git log linus/master..next arch/alpha/Kconfig
I get (as expected) and empty output.
It could be an artifact of me including a branch from Bjorn with some PCI
work on which I had a dependency and which you already merged earlier that
is confusing git request-pull, not sure, I don't have time to investigate that now :-)
Now some highlights in addition to the usual batch of fixes:
- 64TB address space support for 64-bit processes by Aneesh Kumar
- Gavin Shan did a major cleanup & re-organization of our EEH support code
(IBM fancy PCI error handling & recovery infrastructure) which paves the way
for supporting different platform backends, along with some rework of the
PCIe code for the PowerNV platform in order to remove home made resource
allocations and instead use the generic code (which is possible after some
small improvements to it done by Gavin).
- Uprobes support by Ananth N Mavinakayanahalli
- A pile of embedded updates from Freescale folks, including new SoC and
board supports, more KVM stuff including preparing for 64-bit BookE KVM
support, ePAPR 1.1 updates, etc...
Cheers,
Ben.
The following changes since commit 271fd03a3013b106ccc178d54219c1be0c9759b7:
powerpc/powernv: I/O and memory alignment for P2P bridges (2012-09-11 16:59:47 -0600)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
for you to fetch changes up to d900bd7366463fd96a907b2c212242e2b68b27d8:
powerpc/iommu: Fix multiple issues with IOMMU pools code (2012-10-04 18:03:20 +1000)
----------------------------------------------------------------
Alexey Kardashevskiy (1):
powerpc/iommu: Add ppc_md.tce_get() callback for use by VFIO
Ananth N Mavinakayanahalli (4):
powerpc: Consolidate {k,u}probe definitions
powerpc: Add trap_nr to thread_struct
powerpc: Uprobes port to powerpc
powerpc/kprobes: Rename opcode_t in probes.h to ppc_opcode_t
Anatolij Gustschin (3):
powerpc/mpc5200: add dts files for ifm camera machines
dt/misc: add bindings documentation for ifm camera sensor interface
powerpc/mpc52xx_lpbfifo: optionally defer fifo transfer start
Aneesh Kumar K.V (12):
powerpc/mm: Replace open coded CONTEXT_BITS value
powerpc/mm: Use hpt_va to compute virtual address
powerpc/mm: Simplify hpte_decode
powerpc/mm: Convert virtual address to vpn
powerpc/mm: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE
powerpc/mm: Increase the slice range to 64TB
powerpc/mm: Use the required number of VSID bits in slbmte
powerpc/mm: Use 32bit array for slb cache
powerpc/mm: Add 64TB support
powerpc/mm: Update VSID allocation documentation
powerpc/mm: Make some of the PGTABLE_RANGE dependency explicit
powerpc/eeh: Don't release eeh_mutex in eeh_phb_pe_get
Anton Blanchard (2):
powerpc/pseries: Round up MSI-X requests
powerpc/iommu: Fix multiple issues with IOMMU pools code
Benjamin Herrenschmidt (7):
hvc_console: Better kernel console support
hvc_vio: Improve registration of udbg backend
Merge branch 'merge' into next
Merge remote-tracking branch 'pci/pci/gavin-window-alignment' into next
Merge remote-tracking branch 'kumar/next' into next
Merge remote-tracking branch 'agust/next' into next
Merge remote-tracking branch 'kumar/next' into next
Bharat Bhushan (1):
powerpc: Remove unused __get_user64() and __put_user64()
Bjorn Helgaas (1):
Merge commit 'v3.6-rc5' into pci/gavin-window-alignment
Carl E. Love (1):
powerpc/oprofile: Fix marked events support on Power7+ not set.
Chunhe Lan (1):
powerpc/85xx: Enable USB support in p1023rds_defconfig
Gavin Shan (36):
powerpc/pci: Save P2P bridge resource if possible
powerpc/eeh: Move EEH initialization around
powerpc/eeh: Use slab to allocate eeh devices
powerpc/eeh: More logs for EEH initialization
powerpc/eeh: Introduce eeh_pe struct
powerpc/eeh: Introduce global mutex
powerpc/eeh: Create PEs for PHBs
powerpc/eeh: Search PE based on requirement
powerpc/eeh: Create PEs duing EEH initialization
powerpc/eeh: Remove PE at appropriate time
powerpc/eeh: Build EEH event based on PE
powerpc/eeh: Trace EEH state based on PE
powerpc/eeh: Trace error based on PE from beginning
powerpc/eeh: Make EEH operations based on PE
powerpc/eeh: Device bars restore based on PE
powerpc/eeh: I/O enable and log retrival based on PE
powerpc/eeh: Do reset based on PE
powerpc/eeh: Make EEH handler PE sensitive
powerpc/eeh: Handle EEH error based on PE
powerpc/eeh: Move stats to PE
powerpc/eeh: Probe mode support
powerpc/eeh: Trace eeh device from I/O cache
powerpc/eeh: Cleanup on EEH PCI address cache
powerpc/powernv: Create bus sensitive PEs
powerpc/powernv: PE list based on creation order
powerpc/powernv: I/O and MMIO resource assignment for PEs
powerpc/powernv: Initialize DMA for PEs
powerpc/powernv: Skip check on PE if necessary
powerpc/powernv: Fix overrunning segment tracing array
powerpc/powernv: Using PCI core to do resource assignment
powerpc/powernv: Remove unused functions
powerpc/eeh: Introduce EEH_PE_INVALID type PE
powerpc/eeh: Remove EEH PE for normal PCI hotplug
powerpc/eeh: Global mutex to protect PE tree
powerpc/eeh: Lock module while handling EEH event
powerpc/eeh: Fix crash on converting OF node to edev
Jia Hongtao (4):
powerpc/swiotlb: Enable at early stage and disable if not necessary
powerpc: add adt7461 thermal monitor support to applicable boards
powerpc/fsl-pci: Unify pci/pcie initialization code
powerpc/fsl-pci: fix warning when CONFIG_SWIOTLB is disabled
Joe MacDonald (1):
powerpc/mm: Match variable types to API
Kim Phillips (1):
powerpc/85xx: add Freescale P5040 SOC and SEC v5.2 device trees
Li Zhong (1):
powerpc/trace: Fix interrupt tracepoints vs. RCU
Matthew McClintock (1):
powerpc: Fix build dependencies for c files requiring libfdt.h
Michael Ellerman (23):
powerpc: Remove remaining iSeries chunks
powerpc/crypto: Remove users of virt_to_abs() and phys_to_abs() in nx crypto driver
IB/ehca: Don't use phys_to_abs(), it's a nop
powerpc/mm: Replace abs_to_virt() with __va()
powerpc/pasemi: Remove uses of virt_to_abs() and abs_to_virt()
powerpc/dart: Remove uses of virt_to_abs() and abs_to_virt()
IB/ehca: Remove uses of virt_to_abs() and abs_to_virt()
drivers/macintosh/smu.c: Replace abs_to_virt() with __va()
ehea: Remove uses of virt_to_abs() and abs_to_virt()
powerpc/kernel: Remove uses of abs_to_virt() and virt_to_abs()
powerpc/pseries: Remove uses of abs_to_virt() and virt_to_abs()
powerpc/mm: Remove uses of abs_to_virt() and virt_to_abs()
powerpc/ps3: Replace virt_to_abs() with __pa()
powerpc: Remove phys_to_abs() now all users have been removed
powerpc: Remove abs_to_virt() now all users have been fixed
powerpc: Remove virt_to_abs() now all users have been fixed
powerpc: Remove all includes of <asm/abs_addr.h>
powerpc: Remove <asm/abs_addr.h>
powerpc: Rename 64-bit PVR constants to PVR_foo
powerpc: Initialise paca.data_offset with poison
powerpc: Add an xmon command to dump one or all pacas
powerpc: Set paca->data_offset = 0 for boot cpu
powerpc: Remove tlb batching hack for nighthawk
Michael Neuling (7):
powerpc: Pack arch_hw_breakpoint to avoid holes in struct
powerpc: Use consistent name info for arch_hw_breakpoint
powerpc: Use the XDABR hcall
powerpc: Rework set_dabr so it can take a DABRX value as well
powerpc: Dynamically calculate the dabrx based on kernel/user/hypervisor
powerpc: cleanup old DABRX #defines
powerpc: Add denormalisation exception handling for POWER6/7
Mihai Caraman (6):
powerpc/booke64: Fix machine check handler to use the right prolog
powerpc/booke64: Use GSRR registers in Guest Doorbell interrupts
powerpc/booke64: Add DO_KVM kernel hooks
powerpc/booke64: Eemove mfspr srr1 duplicate in exception prolog
powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int
powerpc: Restore VDSO information on critical exception om BookE
Minghuan Lian (1):
powerpc/fsl-pci: use 'Header Type' to identify PCIE mode
Nishanth Aravamudan (1):
powerpc: Fix VMX fix for memcpy case
Olivia Yin (3):
powerpc/e500v2: Add Power ISA properties to comply with ePAPR 1.1
powerpc/e500mc: Add Power ISA properties to comply with ePAPR 1.1
powerpc/e5500: Add Power ISA properties to comply with ePAPR 1.1
Paul Gortmaker (1):
powerpc: Option FB_FSL_DIU is not really optional for mpc512x
Prabhakar Kushwaha (4):
powerpc: Update Integrated Flash controller device tree bindings
powerpc/mpc85xx: Add new ext fields to Integrated FLash Controller
powerpc/mpc85xx: Update interrupt handling for IFC controller
driver/mtd:IFC NAND:Initialise internal SRAM before any write
Richard Weinberger (1):
powerpc: 512x: Fix mpc5121_clk_get()
Roy Zang (2):
powerpc/pci: Add IP revision register define for Freescale PCIe controller
powerpc/pci: Use PCIe IP block revision register instead of compatible
Scott Wood (1):
powerpc/mm: Fix typo in PTRS_PER_PUD
Shaohui Xie (1):
powerpc/p5040: fix dtb build warning of p5040ds.dtb
Suzuki Poulose (2):
powerpc: Change memory_limit from phys_addr_t to unsigned long long
powerpc: Export memory limit via device tree
Tang Yuantian (1):
powerpc/85xx: L2sram - Add compatible string to the device id list
Tiejun Chen (3):
powerpc/kprobe: Introduce a new thread flag
powerpc/kprobe: Complete kprobe and migrate exception frame
powerpc/kprobe: Don't emulate store when kprobe stwu r1
Timur Tabi (4):
powerpc/85xx: remove P1020RDB and P2020RDB CAMP device trees
powerpc/fsl-pci: add fsl,qoriq-pcie-v2.4 compatible string
powerpc/85xx: Add support for P5040DS board
powerpc/85xx: introduce support for the Freescale / iVeia P1022RDK
Varun Sethi (6):
powerpc/mpic: finish supporting timer group B on Freescale chips
powepc/booke: Separate out E.HV check and ivor setup code.
powerpc/booke: Merge the 32 bit e5500/e500mc cpu setup code.
powerpc/booke: Separate out restore_e5500/setup_e5500 routines.
powerpc/booke: Add CPU_FTR_EMB_HV check for e5500.
powerpc/mpic: FSL MPIC error interrupt support.
Wang Dongsheng (1):
powerpc/8544ds: add partition table for norflash
Zhao Chenhui (5):
powerpc/85xx: Replace epapr spin table macros/defines with a struct
powerpc/smp: add generic_set_cpu_up() to set cpu_state as CPU_UP_PREPARE
powerpc/85xx: implement hardware timebase sync
powerpc/85xx: add HOTPLUG_CPU support
powerpc/smp: Do not disable IPI interrupts during suspend
sukadev@linux.vnet.ibm.com (2):
powerpc: Define Power7+ PV constant PV_POWER7p
powerpc/perf: Sample only if SIAR-Valid bit is set in P7+
Documentation/ABI/testing/sysfs-bus-pci | 12 +
.../ABI/testing/sysfs-platform-ideapad-laptop | 11 +
Documentation/DocBook/filesystems.tmpl | 4 +-
Documentation/DocBook/media/v4l/vidioc-g-tuner.xml | 2 +-
Documentation/block/00-INDEX | 10 +-
Documentation/block/cfq-iosched.txt | 77 +
Documentation/block/queue-sysfs.txt | 64 +
Documentation/devicetree/bindings/misc/ifm-csi.txt | 41 +
.../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 8 +-
.../devicetree/bindings/powerpc/fsl/ifc.txt | 9 +-
.../devicetree/bindings/regulator/tps6586x.txt | 12 +-
Documentation/feature-removal-schedule.txt | 2 +-
Documentation/filesystems/Locking | 2 -
Documentation/filesystems/porting | 5 +-
Documentation/filesystems/vfat.txt | 11 +
Documentation/filesystems/vfs.txt | 4 -
Documentation/laptops/laptop-mode.txt | 12 +-
Documentation/networking/netconsole.txt | 19 +-
Documentation/pinctrl.txt | 6 +-
Documentation/security/Yama.txt | 14 +-
Documentation/sysctl/vm.txt | 14 +-
Documentation/vm/hugetlbpage.txt | 10 +-
Documentation/w1/slaves/w1_therm | 2 +
Documentation/watchdog/src/watchdog-test.c | 2 +-
MAINTAINERS | 70 +-
Makefile | 2 +-
arch/alpha/Kconfig | 2 +
arch/alpha/include/asm/atomic.h | 4 +-
arch/alpha/include/asm/fpu.h | 2 +
arch/alpha/include/asm/ptrace.h | 5 +-
arch/alpha/include/asm/socket.h | 2 +
arch/alpha/include/asm/uaccess.h | 34 +-
arch/alpha/include/asm/unistd.h | 4 +-
arch/alpha/include/asm/word-at-a-time.h | 55 +
arch/alpha/kernel/alpha_ksyms.c | 3 -
arch/alpha/kernel/entry.S | 161 --
arch/alpha/kernel/osf_sys.c | 49 +
arch/alpha/kernel/process.c | 19 +
arch/alpha/kernel/systbls.S | 4 +-
arch/alpha/lib/Makefile | 2 -
arch/alpha/lib/ev6-strncpy_from_user.S | 424 -----
arch/alpha/lib/ev67-strlen_user.S | 107 --
arch/alpha/lib/strlen_user.S | 91 --
arch/alpha/lib/strncpy_from_user.S | 339 ----
arch/alpha/mm/fault.c | 36 +-
arch/alpha/oprofile/common.c | 1 +
arch/arm/Kconfig | 9 +-
arch/arm/boot/dts/am33xx.dtsi | 5 +
arch/arm/boot/dts/at91sam9g25ek.dts | 2 +-
arch/arm/boot/dts/imx23.dtsi | 52 +-
arch/arm/boot/dts/imx27-3ds.dts | 2 +-
arch/arm/boot/dts/imx27.dtsi | 6 +
arch/arm/boot/dts/imx28.dtsi | 74 +-
arch/arm/boot/dts/imx51-babbage.dts | 6 +-
arch/arm/boot/dts/imx51.dtsi | 4 +
arch/arm/boot/dts/imx53-ard.dts | 22 +-
arch/arm/boot/dts/imx53.dtsi | 7 +
arch/arm/boot/dts/imx6q-sabrelite.dts | 1 +
arch/arm/boot/dts/imx6q.dtsi | 7 +
arch/arm/boot/dts/kirkwood-iconnect.dts | 6 +-
arch/arm/boot/dts/twl6030.dtsi | 3 +
arch/arm/configs/armadillo800eva_defconfig | 2 +-
arch/arm/configs/imx_v6_v7_defconfig | 1 +
arch/arm/configs/mxs_defconfig | 1 -
arch/arm/configs/tct_hammer_defconfig | 2 +-
arch/arm/configs/u8500_defconfig | 1 +
arch/arm/include/asm/dma-mapping.h | 7 +
arch/arm/include/asm/pgtable.h | 40 +-
arch/arm/include/asm/sched_clock.h | 2 +
arch/arm/kernel/sched_clock.c | 24 +
arch/arm/kernel/topology.c | 2 +-
arch/arm/lib/Makefile | 23 +-
arch/arm/lib/io-readsw-armv3.S | 106 ++
arch/arm/lib/io-writesw-armv3.S | 126 ++
arch/arm/lib/uaccess.S | 564 +++++++
arch/arm/mach-at91/at91rm9200_time.c | 2 +-
arch/arm/mach-at91/at91sam9260_devices.c | 6 +-
arch/arm/mach-at91/at91sam9261_devices.c | 6 +-
arch/arm/mach-at91/at91sam9263_devices.c | 10 +-
arch/arm/mach-at91/at91sam9g45_devices.c | 6 +-
arch/arm/mach-at91/at91sam9rl_devices.c | 6 +-
arch/arm/mach-at91/clock.c | 12 +
arch/arm/mach-davinci/board-neuros-osd2.c | 39 -
arch/arm/mach-dove/common.c | 3 +-
arch/arm/mach-exynos/mach-origen.c | 7 +
arch/arm/mach-exynos/mach-smdkv310.c | 7 +
arch/arm/mach-exynos/pm_domains.c | 2 +-
arch/arm/mach-gemini/irq.c | 1 +
arch/arm/mach-imx/Makefile | 10 +-
arch/arm/mach-imx/clk-imx27.c | 8 +-
arch/arm/mach-imx/clk-imx31.c | 2 +-
arch/arm/mach-imx/clk-imx51-imx53.c | 1 +
arch/arm/mach-imx/clk-imx6q.c | 8 +-
arch/arm/mach-imx/{head-v7.S => headsmp.S} | 0
arch/arm/mach-imx/hotplug.c | 23 +-
arch/arm/mach-imx/mach-imx6q.c | 4 +-
arch/arm/mach-integrator/core.c | 1 +
arch/arm/mach-integrator/integrator_ap.c | 2 +-
arch/arm/mach-kirkwood/Makefile.boot | 7 +-
arch/arm/mach-kirkwood/common.c | 11 +-
arch/arm/mach-kirkwood/db88f6281-bp-setup.c | 1 +
arch/arm/mach-mmp/sram.c | 2 +-
arch/arm/mach-mv78xx0/addr-map.c | 2 +-
arch/arm/mach-mv78xx0/common.c | 6 +-
arch/arm/mach-mxs/Kconfig | 6 -
arch/arm/mach-mxs/Makefile | 3 +-
arch/arm/mach-omap2/Kconfig | 3 +-
arch/arm/mach-omap2/board-igep0020.c | 2 +
arch/arm/mach-omap2/board-omap3evm.c | 1 +
arch/arm/mach-omap2/common-board-devices.c | 11 -
arch/arm/mach-omap2/common-board-devices.h | 1 -
arch/arm/mach-omap2/cpuidle44xx.c | 3 +-
arch/arm/mach-omap2/mux.h | 1 -
arch/arm/mach-omap2/opp4xxx_data.c | 2 +-
arch/arm/mach-omap2/pm34xx.c | 19 +-
arch/arm/mach-omap2/sleep44xx.S | 8 +-
arch/arm/mach-omap2/twl-common.c | 1 +
arch/arm/mach-orion5x/common.c | 3 +-
arch/arm/mach-pxa/raumfeld.c | 2 +-
arch/arm/mach-s3c24xx/Kconfig | 4 +-
arch/arm/mach-s3c24xx/include/mach/dma.h | 3 +-
arch/arm/mach-sa1100/leds-hackkit.c | 1 +
arch/arm/mach-shmobile/board-armadillo800eva.c | 13 +-
arch/arm/mach-shmobile/board-mackerel.c | 3 +-
arch/arm/mach-shmobile/board-marzen.c | 2 +-
arch/arm/mach-shmobile/intc-sh73a0.c | 4 +-
arch/arm/mach-tegra/board-harmony-power.c | 32 +-
arch/arm/mach-ux500/Kconfig | 1 -
arch/arm/mach-ux500/board-mop500-msp.c | 10 +-
arch/arm/mach-ux500/board-mop500.c | 4 +
arch/arm/mm/dma-mapping.c | 126 +-
arch/arm/mm/flush.c | 2 -
arch/arm/mm/tlb-v7.S | 6 +-
arch/arm/plat-omap/dmtimer.c | 6 +-
arch/arm/plat-omap/include/plat/cpu.h | 3 +-
arch/arm/plat-omap/include/plat/multi.h | 9 +
arch/arm/plat-omap/include/plat/uncompress.h | 4 +-
arch/arm/plat-orion/common.c | 8 +-
arch/arm/plat-orion/include/plat/common.h | 6 +-
arch/arm/plat-s3c24xx/dma.c | 2 +-
arch/arm/plat-samsung/Kconfig | 3 +-
arch/arm/plat-samsung/devs.c | 29 +-
arch/arm/plat-samsung/include/plat/hdmi.h | 16 +
arch/arm/plat-samsung/pm.c | 2 +-
arch/arm/vfp/vfpmodule.c | 2 +
arch/blackfin/kernel/setup.c | 1 -
arch/c6x/Kconfig | 1 +
arch/c6x/include/asm/cache.h | 16 +-
arch/ia64/configs/generic_defconfig | 1 -
arch/ia64/configs/gensparse_defconfig | 1 -
arch/ia64/kernel/acpi.c | 5 +-
arch/m68k/Kconfig | 13 +-
arch/m68k/Kconfig.cpu | 19 +-
arch/m68k/apollo/config.c | 16 +-
arch/m68k/include/asm/Kbuild | 25 +
arch/m68k/include/asm/MC68332.h | 152 --
arch/m68k/include/asm/apollodma.h | 248 ---
arch/m68k/include/asm/apollohw.h | 2 +-
arch/m68k/include/asm/bitsperlong.h | 1 -
arch/m68k/include/asm/cputime.h | 6 -
arch/m68k/include/asm/delay.h | 2 +-
arch/m68k/include/asm/device.h | 7 -
arch/m68k/include/asm/emergency-restart.h | 6 -
arch/m68k/include/asm/errno.h | 6 -
arch/m68k/include/asm/futex.h | 6 -
arch/m68k/include/asm/ioctl.h | 1 -
arch/m68k/include/asm/ipcbuf.h | 1 -
arch/m68k/include/asm/irq_regs.h | 1 -
arch/m68k/include/asm/kdebug.h | 1 -
arch/m68k/include/asm/kmap_types.h | 6 -
arch/m68k/include/asm/kvm_para.h | 1 -
arch/m68k/include/asm/local.h | 6 -
arch/m68k/include/asm/local64.h | 1 -
arch/m68k/include/asm/mac_mouse.h | 23 -
arch/m68k/include/asm/mcfmbus.h | 77 -
arch/m68k/include/asm/mman.h | 1 -
arch/m68k/include/asm/mutex.h | 9 -
arch/m68k/include/asm/percpu.h | 6 -
arch/m68k/include/asm/resource.h | 6 -
arch/m68k/include/asm/sbus.h | 45 -
arch/m68k/include/asm/scatterlist.h | 6 -
arch/m68k/include/asm/sections.h | 8 -
arch/m68k/include/asm/shm.h | 31 -
arch/m68k/include/asm/siginfo.h | 6 -
arch/m68k/include/asm/statfs.h | 6 -
arch/m68k/include/asm/topology.h | 6 -
arch/m68k/include/asm/types.h | 22 -
arch/m68k/include/asm/unaligned.h | 4 +-
arch/m68k/include/asm/xor.h | 1 -
arch/m68k/kernel/setup_no.c | 11 +-
arch/m68k/kernel/sys_m68k.c | 8 +-
arch/m68k/kernel/vmlinux-nommu.lds | 2 -
arch/m68k/kernel/vmlinux-std.lds | 2 -
arch/m68k/kernel/vmlinux-sun3.lds | 2 -
arch/m68k/lib/muldi3.c | 2 +-
arch/m68k/mm/init_mm.c | 2 +-
arch/m68k/mm/init_no.c | 2 +-
arch/m68k/platform/68328/head-de2.S | 8 +-
arch/m68k/platform/68328/head-pilot.S | 10 +-
arch/m68k/platform/68328/head-ram.S | 4 +-
arch/m68k/platform/68328/head-rom.S | 6 +-
arch/m68k/platform/68360/head-ram.S | 6 +-
arch/m68k/platform/68360/head-rom.S | 8 +-
arch/m68k/platform/coldfire/head.S | 10 +-
arch/m68k/sun3/prom/init.c | 48 +-
arch/microblaze/include/asm/sections.h | 4 -
arch/microblaze/kernel/microblaze_ksyms.c | 3 -
arch/microblaze/kernel/setup.c | 4 +-
arch/microblaze/kernel/vmlinux.lds.S | 1 -
arch/mips/Kconfig | 1 +
arch/mips/alchemy/board-mtx1.c | 2 +
arch/mips/ath79/dev-usb.c | 2 +
arch/mips/ath79/gpio.c | 6 +-
arch/mips/bcm63xx/dev-spi.c | 4 +
arch/mips/cavium-octeon/octeon-irq.c | 89 +-
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 3 +-
.../include/asm/mach-ath79/cpu-feature-overrides.h | 1 -
.../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 2 +
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 13 +-
arch/mips/include/asm/mach-cavium-octeon/irq.h | 10 +-
arch/mips/include/asm/module.h | 1 +
arch/mips/include/asm/r4k-timer.h | 8 +-
arch/mips/kernel/module.c | 43 +-
arch/mips/kernel/smp.c | 4 +-
arch/mips/kernel/sync-r4k.c | 26 +-
arch/mips/mti-malta/malta-pci.c | 13 -
arch/mips/pci/pci-ar724x.c | 22 +
arch/parisc/include/asm/atomic.h | 4 +-
arch/parisc/kernel/process.c | 2 +-
arch/parisc/kernel/sys_parisc.c | 8 +-
arch/powerpc/Kconfig | 17 +-
arch/powerpc/boot/Makefile | 1 +
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi | 58 +
arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi | 52 +
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi | 59 +
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 7 +
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 3 +
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 320 ++++
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 114 ++
arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi | 118 ++
arch/powerpc/boot/dts/mpc8536ds.dtsi | 4 +
arch/powerpc/boot/dts/mpc8540ads.dts | 2 +
arch/powerpc/boot/dts/mpc8541cds.dts | 2 +
arch/powerpc/boot/dts/mpc8544ds.dts | 4 +-
arch/powerpc/boot/dts/mpc8544ds.dtsi | 39 +
arch/powerpc/boot/dts/mpc8555cds.dts | 2 +
arch/powerpc/boot/dts/mpc8560ads.dts | 2 +
arch/powerpc/boot/dts/o2d.dts | 47 +
arch/powerpc/boot/dts/o2d.dtsi | 139 ++
arch/powerpc/boot/dts/o2d300.dts | 52 +
arch/powerpc/boot/dts/o2dnt2.dts | 48 +
arch/powerpc/boot/dts/o2i.dts | 33 +
arch/powerpc/boot/dts/o2mnt.dts | 33 +
arch/powerpc/boot/dts/o3dnt.dts | 48 +
arch/powerpc/boot/dts/p1020rdb_camp_core0.dts | 63 -
arch/powerpc/boot/dts/p1020rdb_camp_core1.dts | 141 --
arch/powerpc/boot/dts/p1022ds.dtsi | 4 +
arch/powerpc/boot/dts/p1022rdk.dts | 188 +++
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts | 67 -
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts | 125 --
arch/powerpc/boot/dts/p2041rdb.dts | 4 +
arch/powerpc/boot/dts/p3041ds.dts | 4 +
arch/powerpc/boot/dts/p4080ds.dts | 4 +
arch/powerpc/boot/dts/p5020ds.dts | 4 +
arch/powerpc/boot/dts/p5040ds.dts | 207 +++
arch/powerpc/configs/85xx/p1023rds_defconfig | 37 +-
arch/powerpc/configs/corenet32_smp_defconfig | 30 +-
arch/powerpc/configs/corenet64_smp_defconfig | 2 +
arch/powerpc/configs/g5_defconfig | 103 +-
arch/powerpc/configs/mpc83xx_defconfig | 18 +-
arch/powerpc/configs/mpc85xx_defconfig | 34 +-
arch/powerpc/configs/mpc85xx_smp_defconfig | 33 +-
arch/powerpc/configs/ppc64_defconfig | 1 +
arch/powerpc/configs/pseries_defconfig | 1 +
arch/powerpc/include/asm/abs_addr.h | 56 -
arch/powerpc/include/asm/cacheflush.h | 2 +
arch/powerpc/include/asm/cputable.h | 2 -
arch/powerpc/include/asm/debug.h | 2 +-
arch/powerpc/include/asm/eeh.h | 141 +-
arch/powerpc/include/asm/eeh_event.h | 6 +-
arch/powerpc/include/asm/exception-64e.h | 6 +-
arch/powerpc/include/asm/fsl_guts.h | 2 +
arch/powerpc/include/asm/fsl_ifc.h | 14 +-
arch/powerpc/include/asm/hvcall.h | 5 -
arch/powerpc/include/asm/hw_breakpoint.h | 9 +-
arch/powerpc/include/asm/kprobes.h | 15 +-
arch/powerpc/include/asm/kvm_book3s.h | 2 +-
arch/powerpc/include/asm/kvm_book3s_asm.h | 1 -
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/asm/kvm_ppc.h | 12 +
arch/powerpc/include/asm/machdep.h | 9 +-
arch/powerpc/include/asm/mmu-hash64.h | 169 +-
arch/powerpc/include/asm/mmu.h | 9 +
arch/powerpc/include/asm/mpc52xx.h | 2 +
arch/powerpc/include/asm/mpic.h | 19 +
arch/powerpc/include/asm/mpic_msgr.h | 1 +
arch/powerpc/include/asm/paca.h | 3 +-
arch/powerpc/include/asm/page_64.h | 10 +-
arch/powerpc/include/asm/pci-bridge.h | 11 +
arch/powerpc/include/asm/perf_event_server.h | 1 +
arch/powerpc/include/asm/pgtable-ppc64-4k.h | 4 +-
arch/powerpc/include/asm/pgtable-ppc64-64k.h | 2 +-
arch/powerpc/include/asm/pgtable-ppc64.h | 19 +-
arch/powerpc/include/asm/pgtable.h | 10 +-
arch/powerpc/include/asm/ppc-opcode.h | 3 +
arch/powerpc/include/asm/ppc-pci.h | 20 +-
arch/powerpc/include/asm/probes.h | 42 +
arch/powerpc/include/asm/processor.h | 7 +-
arch/powerpc/include/asm/pte-hash64-64k.h | 18 +-
arch/powerpc/include/asm/reg.h | 54 +-
arch/powerpc/include/asm/setup.h | 2 +-
arch/powerpc/include/asm/smp.h | 2 +
arch/powerpc/include/asm/sparsemem.h | 4 +-
arch/powerpc/include/asm/swiotlb.h | 6 +
arch/powerpc/include/asm/thread_info.h | 7 +-
arch/powerpc/include/asm/tlbflush.h | 7 +-
arch/powerpc/include/asm/uaccess.h | 11 -
arch/powerpc/include/asm/uprobes.h | 54 +
arch/powerpc/kernel/Makefile | 1 +
arch/powerpc/kernel/asm-offsets.c | 3 +-
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 74 +-
arch/powerpc/kernel/cputable.c | 4 +
arch/powerpc/kernel/dbell.c | 2 +
arch/powerpc/kernel/dma-iommu.c | 9 +-
arch/powerpc/kernel/dma-swiotlb.c | 22 +-
arch/powerpc/kernel/dma.c | 3 +-
arch/powerpc/kernel/entry_32.S | 47 +-
arch/powerpc/kernel/entry_64.S | 58 +-
arch/powerpc/kernel/exceptions-64e.S | 212 ++-
arch/powerpc/kernel/exceptions-64s.S | 130 +-
arch/powerpc/kernel/fadump.c | 3 +-
arch/powerpc/kernel/head_fsl_booke.S | 46 +-
arch/powerpc/kernel/hw_breakpoint.c | 27 +-
arch/powerpc/kernel/ibmebus.c | 1 -
arch/powerpc/kernel/idle_power7.S | 2 +
arch/powerpc/kernel/iommu.c | 5 +-
arch/powerpc/kernel/irq.c | 8 +-
arch/powerpc/kernel/kgdb.c | 27 +-
arch/powerpc/kernel/machine_kexec.c | 14 +-
arch/powerpc/kernel/paca.c | 1 +
arch/powerpc/kernel/pci-common.c | 16 +-
arch/powerpc/kernel/process.c | 28 +-
arch/powerpc/kernel/prom.c | 4 +-
arch/powerpc/kernel/prom_init.c | 2 +-
arch/powerpc/kernel/ptrace.c | 3 +
arch/powerpc/kernel/rtas_flash.c | 7 +-
arch/powerpc/kernel/rtas_pci.c | 5 +-
arch/powerpc/kernel/setup_64.c | 2 +
arch/powerpc/kernel/signal.c | 8 +-
arch/powerpc/kernel/smp.c | 25 +-
arch/powerpc/kernel/syscalls.c | 8 +-
arch/powerpc/kernel/sysfs.c | 10 +
arch/powerpc/kernel/time.c | 15 +-
arch/powerpc/kernel/traps.c | 4 +-
arch/powerpc/kernel/uprobes.c | 184 +++
arch/powerpc/kernel/vdso.c | 4 +-
arch/powerpc/kernel/vio.c | 1 -
arch/powerpc/kvm/book3s_32_mmu_host.c | 11 +-
arch/powerpc/kvm/book3s_64_mmu_host.c | 19 +-
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 14 +-
arch/powerpc/kvm/e500_tlb.c | 11 +-
arch/powerpc/kvm/trace.h | 14 +-
arch/powerpc/lib/code-patching.c | 2 +-
arch/powerpc/lib/copyuser_power7.S | 35 +-
arch/powerpc/lib/memcpy_power7.S | 8 +-
arch/powerpc/lib/sstep.c | 36 +-
arch/powerpc/mm/fault.c | 1 +
arch/powerpc/mm/hash_low_64.S | 97 +-
arch/powerpc/mm/hash_native_64.c | 192 +--
arch/powerpc/mm/hash_utils_64.c | 48 +-
arch/powerpc/mm/hugetlbpage-hash64.c | 15 +-
arch/powerpc/mm/init_64.c | 1 -
arch/powerpc/mm/mem.c | 6 +-
arch/powerpc/mm/mmu_context_hash64.c | 10 +-
arch/powerpc/mm/numa.c | 7 +-
arch/powerpc/mm/pgtable_64.c | 13 +-
arch/powerpc/mm/slb_low.S | 62 +-
arch/powerpc/mm/slice.c | 112 +-
arch/powerpc/mm/stab.c | 3 +-
arch/powerpc/mm/subpage-prot.c | 6 +-
arch/powerpc/mm/tlb_hash64.c | 11 +-
arch/powerpc/mm/tlb_low_64e.S | 18 +-
arch/powerpc/oprofile/op_model_power4.c | 116 +-
arch/powerpc/perf/core-book3s.c | 48 +-
arch/powerpc/perf/power7-pmu.c | 3 +
arch/powerpc/platforms/44x/currituck.c | 10 +-
arch/powerpc/platforms/512x/Kconfig | 1 +
arch/powerpc/platforms/512x/clock.c | 6 +-
arch/powerpc/platforms/512x/mpc512x_shared.c | 6 -
arch/powerpc/platforms/52xx/mpc5200_simple.c | 1 +
arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c | 35 +-
arch/powerpc/platforms/85xx/Kconfig | 21 +
arch/powerpc/platforms/85xx/Makefile | 2 +
arch/powerpc/platforms/85xx/common.c | 10 +
arch/powerpc/platforms/85xx/corenet_ds.c | 38 +-
arch/powerpc/platforms/85xx/ge_imp3a.c | 62 +-
arch/powerpc/platforms/85xx/mpc8536_ds.c | 36 +-
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 11 +-
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 44 +-
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 15 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 40 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 30 +-
arch/powerpc/platforms/85xx/p1010rdb.c | 14 +-
arch/powerpc/platforms/85xx/p1022_ds.c | 36 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 167 ++
arch/powerpc/platforms/85xx/p1023_rds.c | 9 +-
arch/powerpc/platforms/85xx/p2041_rdb.c | 2 +-
arch/powerpc/platforms/85xx/p3041_ds.c | 2 +-
arch/powerpc/platforms/85xx/p4080_ds.c | 2 +-
arch/powerpc/platforms/85xx/p5020_ds.c | 2 +-
arch/powerpc/platforms/85xx/p5040_ds.c | 89 ++
arch/powerpc/platforms/85xx/qemu_e500.c | 5 +-
arch/powerpc/platforms/85xx/sbc8548.c | 21 +-
arch/powerpc/platforms/85xx/smp.c | 220 ++-
arch/powerpc/platforms/85xx/socrates.c | 11 +-
arch/powerpc/platforms/85xx/stx_gp3.c | 13 +-
arch/powerpc/platforms/85xx/tqm85xx.c | 21 +-
arch/powerpc/platforms/85xx/xes_mpc85xx.c | 56 +-
arch/powerpc/platforms/86xx/gef_ppc9a.c | 12 +-
arch/powerpc/platforms/86xx/gef_sbc310.c | 13 +-
arch/powerpc/platforms/86xx/gef_sbc610.c | 12 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 21 +-
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 42 +-
arch/powerpc/platforms/86xx/sbc8641d.c | 14 +-
arch/powerpc/platforms/cell/beat.c | 4 +-
arch/powerpc/platforms/cell/beat.h | 2 +-
arch/powerpc/platforms/cell/beat_htab.c | 45 +-
arch/powerpc/platforms/pasemi/iommu.c | 6 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 695 +++------
arch/powerpc/platforms/powernv/pci-p5ioc2.c | 1 -
arch/powerpc/platforms/powernv/pci.c | 7 +-
arch/powerpc/platforms/powernv/pci.h | 21 +-
arch/powerpc/platforms/powernv/smp.c | 10 +-
arch/powerpc/platforms/ps3/htab.c | 22 +-
arch/powerpc/platforms/ps3/setup.c | 10 +-
arch/powerpc/platforms/pseries/Makefile | 5 +-
arch/powerpc/platforms/pseries/eeh.c | 543 ++-----
arch/powerpc/platforms/pseries/eeh_cache.c | 59 +-
arch/powerpc/platforms/pseries/eeh_dev.c | 14 +-
arch/powerpc/platforms/pseries/eeh_driver.c | 310 ++--
arch/powerpc/platforms/pseries/eeh_event.c | 54 +-
arch/powerpc/platforms/pseries/eeh_pe.c | 652 ++++++++
arch/powerpc/platforms/pseries/eeh_pseries.c | 247 ++-
arch/powerpc/platforms/pseries/eeh_sysfs.c | 9 -
arch/powerpc/platforms/pseries/iommu.c | 12 +-
arch/powerpc/platforms/pseries/lpar.c | 77 +-
arch/powerpc/platforms/pseries/msi.c | 26 +-
arch/powerpc/platforms/pseries/pci.c | 2 +-
arch/powerpc/platforms/pseries/pci_dlpar.c | 32 +-
arch/powerpc/platforms/pseries/setup.c | 22 +-
arch/powerpc/sysdev/Makefile | 2 +-
arch/powerpc/sysdev/dart_iommu.c | 19 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 10 +
arch/powerpc/sysdev/fsl_ifc.c | 20 +-
arch/powerpc/sysdev/fsl_mpic_err.c | 149 ++
arch/powerpc/sysdev/fsl_pci.c | 154 +-
arch/powerpc/sysdev/fsl_pci.h | 20 +-
arch/powerpc/sysdev/mpic.c | 102 +-
arch/powerpc/sysdev/mpic.h | 22 +
arch/powerpc/sysdev/mpic_msgr.c | 3 +
arch/powerpc/sysdev/xics/icp-hv.c | 6 +-
arch/powerpc/xmon/xmon.c | 195 ++-
arch/s390/Kconfig | 1 +
arch/s390/include/asm/elf.h | 3 +-
arch/s390/include/asm/posix_types.h | 3 +-
arch/s390/include/asm/smp.h | 1 +
arch/s390/include/asm/sparsemem.h | 2 -
arch/s390/include/asm/syscall.h | 10 +
arch/s390/kernel/compat_linux.c | 2 -
arch/s390/kernel/compat_wrapper.S | 4 +-
arch/s390/kernel/ptrace.c | 7 +-
arch/s390/kernel/sys_s390.c | 9 +-
arch/sh/drivers/dma/dma-sh.c | 2 +-
arch/sh/include/asm/sections.h | 1 -
arch/sh/include/cpu-sh2a/cpu/sh7269.h | 36 +-
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c | 195 ++-
arch/sh/kernel/setup.c | 2 +-
arch/sh/kernel/sh_ksyms_32.c | 1 -
arch/sh/kernel/vmlinux.lds.S | 1 -
arch/sh/lib/mcount.S | 8 +-
arch/sparc/kernel/sys_sparc_64.c | 10 +-
arch/sparc/mm/init_64.c | 28 +-
arch/um/os-Linux/time.c | 2 +-
arch/x86/Kconfig | 2 +-
arch/x86/Makefile | 4 +
arch/x86/boot/Makefile | 2 +-
arch/x86/include/asm/mce.h | 8 +
arch/x86/include/asm/perf_event.h | 11 +-
arch/x86/include/asm/spinlock.h | 3 +-
arch/x86/kernel/acpi/sleep.c | 4 -
arch/x86/kernel/acpi/sleep.h | 2 -
arch/x86/kernel/acpi/wakeup_32.S | 4 +-
arch/x86/kernel/acpi/wakeup_64.S | 4 +-
arch/x86/kernel/alternative.c | 4 +-
arch/x86/kernel/apic/io_apic.c | 14 +-
arch/x86/kernel/cpu/common.c | 2 +
arch/x86/kernel/cpu/mcheck/mce-severity.c | 7 -
arch/x86/kernel/cpu/mcheck/mce.c | 43 +-
arch/x86/kernel/cpu/perf_event.c | 89 +-
arch/x86/kernel/cpu/perf_event.h | 20 +
arch/x86/kernel/cpu/perf_event_amd_ibs.c | 4 +-
arch/x86/kernel/cpu/perf_event_intel.c | 10 +-
arch/x86/kernel/cpu/perf_event_intel_ds.c | 7 +-
arch/x86/kernel/cpu/perf_event_intel_uncore.c | 253 +--
arch/x86/kernel/cpu/perf_event_intel_uncore.h | 48 +-
arch/x86/kernel/irq.c | 3 +-
arch/x86/kernel/kdebugfs.c | 6 +-
arch/x86/kernel/microcode_amd.c | 7 +-
arch/x86/kvm/emulate.c | 30 +-
arch/x86/kvm/i8259.c | 17 +
arch/x86/kvm/mmu.c | 13 +-
arch/x86/kvm/vmx.c | 20 +-
arch/x86/kvm/x86.c | 9 +-
arch/x86/mm/hugetlbpage.c | 21 +-
arch/x86/mm/pageattr.c | 10 +-
arch/x86/mm/srat.c | 15 +-
arch/x86/platform/efi/efi.c | 30 +-
arch/x86/realmode/rm/Makefile | 2 +-
arch/x86/syscalls/syscall_64.tbl | 8 +-
arch/x86/xen/enlighten.c | 118 +-
arch/x86/xen/mmu.c | 2 +-
arch/x86/xen/p2m.c | 94 ++
arch/x86/xen/setup.c | 9 +-
arch/x86/xen/suspend.c | 2 +-
arch/x86/xen/xen-ops.h | 2 +-
block/blk-lib.c | 41 +-
block/blk-merge.c | 117 +-
block/genhd.c | 2 +-
drivers/acpi/ac.c | 4 +
drivers/acpi/acpica/achware.h | 12 +-
drivers/acpi/acpica/hwesleep.c | 19 +-
drivers/acpi/acpica/hwsleep.c | 20 +-
drivers/acpi/acpica/hwxfsleep.c | 22 +-
drivers/acpi/acpica/tbxface.c | 1 +
drivers/acpi/battery.c | 2 +
drivers/acpi/button.c | 4 +
drivers/acpi/fan.c | 4 +
drivers/acpi/numa.c | 12 +-
drivers/acpi/pci_root.c | 11 +-
drivers/acpi/power.c | 4 +
drivers/acpi/processor_driver.c | 2 +-
drivers/acpi/sbs.c | 2 +
drivers/acpi/sleep.c | 75 +-
drivers/acpi/sysfs.c | 4 +-
drivers/acpi/thermal.c | 4 +
drivers/ata/Kconfig | 2 +-
drivers/ata/ahci.c | 8 +
drivers/ata/ahci.h | 1 +
drivers/ata/ata_piix.c | 8 +
drivers/ata/libahci.c | 3 +-
drivers/ata/libata-acpi.c | 15 +-
drivers/ata/libata-core.c | 3 +-
drivers/ata/pata_atiixp.c | 16 +
drivers/atm/iphase.c | 2 +-
drivers/base/core.c | 9 +-
drivers/base/dma-contiguous.c | 2 +-
drivers/base/power/clock_ops.c | 3 +-
drivers/base/power/common.c | 4 +-
drivers/base/power/runtime.c | 13 +-
drivers/bcma/host_pci.c | 1 +
drivers/bcma/sprom.c | 4 +-
drivers/block/cciss_scsi.c | 11 +-
drivers/block/drbd/drbd_bitmap.c | 15 +-
drivers/block/drbd/drbd_int.h | 1 +
drivers/block/drbd/drbd_main.c | 32 +-
drivers/block/drbd/drbd_nl.c | 4 +-
drivers/block/drbd/drbd_req.c | 36 +-
drivers/bluetooth/ath3k.c | 2 +
drivers/bluetooth/btusb.c | 2 +
drivers/char/agp/intel-agp.h | 40 +-
drivers/char/agp/intel-gtt.c | 107 +-
drivers/char/hw_random/omap-rng.c | 2 +-
drivers/char/tpm/tpm_tis.c | 2 +
drivers/clocksource/cs5535-clockevt.c | 4 +-
drivers/cpufreq/omap-cpufreq.c | 4 +-
drivers/cpufreq/pcc-cpufreq.c | 1 +
drivers/cpuidle/coupled.c | 14 +-
drivers/crypto/caam/jr.c | 10 +-
drivers/crypto/hifn_795x.c | 4 +-
drivers/crypto/nx/nx.c | 17 +-
drivers/dma/imx-dma.c | 36 +-
drivers/dma/tegra20-apb-dma.c | 18 +-
drivers/edac/mpc85xx_edac.c | 43 +-
drivers/extcon/extcon_gpio.c | 3 +-
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-em.c | 6 +-
drivers/gpio/gpio-langwell.c | 7 +-
drivers/gpio/gpio-msic.c | 2 +-
drivers/gpio/gpio-mxc.c | 5 +-
drivers/gpio/gpio-pxa.c | 30 +-
drivers/gpio/gpio-rdc321x.c | 1 +
drivers/gpio/gpio-samsung.c | 14 +-
drivers/gpio/gpio-sch.c | 3 +-
drivers/gpio/gpiolib-of.c | 2 +-
drivers/gpu/drm/Kconfig | 1 +
drivers/gpu/drm/drm_crtc.c | 2 +-
drivers/gpu/drm/drm_edid.c | 3 +
drivers/gpu/drm/drm_edid_load.c | 8 +-
drivers/gpu/drm/drm_modes.c | 3 -
drivers/gpu/drm/drm_proc.c | 4 +-
drivers/gpu/drm/gma500/psb_intel_display.c | 3 +
drivers/gpu/drm/i915/i915_drv.c | 31 +-
drivers/gpu/drm/i915/i915_gem.c | 8 +-
drivers/gpu/drm/i915/i915_gem_context.c | 1 -
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 20 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +-
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c | 12 +
drivers/gpu/drm/i915/intel_crt.c | 36 +-
drivers/gpu/drm/i915/intel_display.c | 24 +-
drivers/gpu/drm/i915/intel_dp.c | 14 +-
drivers/gpu/drm/i915/intel_drv.h | 22 +-
drivers/gpu/drm/i915/intel_i2c.c | 10 +-
drivers/gpu/drm/i915/intel_lvds.c | 8 +
drivers/gpu/drm/i915/intel_modes.c | 31 +-
drivers/gpu/drm/i915/intel_panel.c | 15 +-
drivers/gpu/drm/i915/intel_pm.c | 21 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 48 +-
drivers/gpu/drm/i915/intel_sdvo.c | 6 +-
drivers/gpu/drm/i915/intel_sprite.c | 4 +-
drivers/gpu/drm/mgag200/mgag200_mode.c | 12 +-
drivers/gpu/drm/nouveau/nouveau_acpi.c | 6 -
drivers/gpu/drm/nouveau/nouveau_i2c.c | 2 +-
drivers/gpu/drm/nouveau/nouveau_state.c | 7 +-
drivers/gpu/drm/nouveau/nv84_fifo.c | 9 +
drivers/gpu/drm/nouveau/nvc0_pm.c | 2 +-
drivers/gpu/drm/nouveau/nvd0_display.c | 2 +-
drivers/gpu/drm/nouveau/nve0_fifo.c | 37 +-
drivers/gpu/drm/radeon/atombios_crtc.c | 81 +-
drivers/gpu/drm/radeon/atombios_dp.c | 29 +-
drivers/gpu/drm/radeon/atombios_encoders.c | 140 +-
drivers/gpu/drm/radeon/evergreen.c | 71 +-
drivers/gpu/drm/radeon/evergreen_cs.c | 13 +-
drivers/gpu/drm/radeon/evergreend.h | 2 +
drivers/gpu/drm/radeon/ni.c | 14 +-
drivers/gpu/drm/radeon/r600.c | 20 +
drivers/gpu/drm/radeon/r600_cs.c | 196 ++-
drivers/gpu/drm/radeon/r600d.h | 28 +
drivers/gpu/drm/radeon/radeon.h | 27 +-
drivers/gpu/drm/radeon/radeon_asic.h | 10 +-
drivers/gpu/drm/radeon/radeon_atombios.c | 51 +-
drivers/gpu/drm/radeon/radeon_atpx_handler.c | 56 +-
drivers/gpu/drm/radeon/radeon_bios.c | 138 +-
drivers/gpu/drm/radeon/radeon_combios.c | 57 +-
drivers/gpu/drm/radeon/radeon_cs.c | 32 +-
drivers/gpu/drm/radeon/radeon_cursor.c | 6 +-
drivers/gpu/drm/radeon/radeon_device.c | 6 +-
drivers/gpu/drm/radeon/radeon_drv.c | 7 +-
drivers/gpu/drm/radeon/radeon_gart.c | 26 +-
drivers/gpu/drm/radeon/radeon_gem.c | 13 +-
drivers/gpu/drm/radeon/radeon_kms.c | 35 +-
drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 4 +
drivers/gpu/drm/radeon/radeon_mode.h | 1 +
drivers/gpu/drm/radeon/radeon_object.c | 9 +-
drivers/gpu/drm/radeon/radeon_ring.c | 1 +
drivers/gpu/drm/radeon/reg_srcs/r600 | 9 -
drivers/gpu/drm/radeon/rv515.c | 13 -
drivers/gpu/drm/radeon/si.c | 35 +-
drivers/gpu/drm/radeon/sid.h | 3 +
drivers/gpu/drm/udl/Kconfig | 1 +
drivers/gpu/drm/udl/udl_gem.c | 2 +-
drivers/gpu/drm/udl/udl_modeset.c | 3 +-
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 6 +-
drivers/gpu/vga/vga_switcheroo.c | 61 +-
drivers/hid/hid-core.c | 8 +-
drivers/hid/hid-logitech-dj.c | 4 +-
drivers/hid/usbhid/hid-quirks.c | 1 +
drivers/hwmon/asus_atk0110.c | 6 +
drivers/hwmon/coretemp.c | 2 +-
drivers/hwmon/w83627hf.c | 2 +-
drivers/i2c/busses/i2c-diolan-u2c.c | 1 +
drivers/i2c/busses/i2c-nomadik.c | 28 +-
drivers/i2c/busses/i2c-omap.c | 2 +-
drivers/i2c/busses/i2c-tegra.c | 2 +-
drivers/ide/ide-pm.c | 4 +-
drivers/idle/intel_idle.c | 3 +-
drivers/iio/frequency/adf4350.c | 24 +-
drivers/iio/light/adjd_s311.c | 7 +-
drivers/iio/light/lm3533-als.c | 4 +-
drivers/infiniband/core/ucma.c | 2 +-
drivers/infiniband/hw/amso1100/c2_rnic.c | 2 +-
drivers/infiniband/hw/cxgb3/iwch_cm.c | 2 +-
drivers/infiniband/hw/ehca/ehca_cq.c | 2 +-
drivers/infiniband/hw/ehca/ehca_eq.c | 2 +-
drivers/infiniband/hw/ehca/ehca_mrmw.c | 45 +-
drivers/infiniband/hw/ehca/ehca_qp.c | 6 +-
drivers/infiniband/hw/ehca/ehca_reqs.c | 2 +-
drivers/infiniband/hw/ehca/ehca_tools.h | 1 -
drivers/infiniband/hw/ehca/hcp_if.c | 12 +-
drivers/infiniband/hw/ehca/ipz_pt_fn.c | 2 +-
drivers/infiniband/hw/mlx4/mad.c | 16 +-
drivers/infiniband/hw/mlx4/main.c | 5 +-
drivers/infiniband/hw/mlx4/qp.c | 6 +-
drivers/infiniband/hw/ocrdma/ocrdma_main.c | 16 +-
drivers/infiniband/hw/qib/qib_iba7322.c | 4 +-
drivers/infiniband/hw/qib/qib_sd7220.c | 2 +-
drivers/infiniband/ulp/ipoib/ipoib_cm.c | 3 +
drivers/infiniband/ulp/ipoib/ipoib_main.c | 2 +-
drivers/infiniband/ulp/srp/ib_srp.c | 87 +-
drivers/infiniband/ulp/srpt/ib_srpt.c | 2 +-
drivers/input/keyboard/imx_keypad.c | 3 +
drivers/input/serio/i8042-x86ia64io.h | 14 +
drivers/input/tablet/wacom_wac.c | 6 +-
drivers/input/touchscreen/edt-ft5x06.c | 2 +-
drivers/input/touchscreen/eeti_ts.c | 21 +-
drivers/iommu/amd_iommu.c | 25 +-
drivers/iommu/amd_iommu_init.c | 8 +-
drivers/iommu/exynos-iommu.c | 6 +-
drivers/iommu/intel-iommu.c | 26 +-
drivers/iommu/intel_irq_remapping.c | 18 +-
drivers/iommu/tegra-smmu.c | 17 +-
drivers/isdn/isdnloop/isdnloop.c | 12 -
drivers/isdn/mISDN/layer2.c | 2 +-
drivers/leds/led-triggers.c | 2 +-
drivers/leds/leds-lp8788.c | 2 +-
drivers/leds/leds-renesas-tpu.c | 2 +-
drivers/macintosh/smu.c | 3 +-
drivers/md/md.c | 9 +-
drivers/md/raid10.c | 30 +-
drivers/md/raid10.h | 2 +-
drivers/media/dvb/siano/smsusb.c | 2 +-
drivers/media/radio/radio-shark.c | 151 +-
drivers/media/radio/radio-shark2.c | 137 +-
drivers/media/radio/si470x/radio-si470x-common.c | 3 +
drivers/media/radio/si470x/radio-si470x-i2c.c | 5 +-
drivers/media/radio/si470x/radio-si470x-usb.c | 2 +-
drivers/media/rc/Kconfig | 1 +
drivers/media/video/gspca/jl2005bcd.c | 2 +-
drivers/media/video/gspca/spca506.c | 2 +-
drivers/media/video/mem2mem_testdev.c | 2 +-
drivers/media/video/mx1_camera.c | 4 +-
drivers/media/video/mx2_camera.c | 47 +-
drivers/media/video/mx3_camera.c | 22 +-
drivers/media/video/soc_camera.c | 3 +-
drivers/media/video/soc_mediabus.c | 6 +
drivers/media/video/uvc/uvc_queue.c | 1 +
drivers/media/video/v4l2-ioctl.c | 10 +-
drivers/mfd/Kconfig | 3 +-
drivers/mfd/asic3.c | 1 +
drivers/mfd/ezx-pcap.c | 2 +-
drivers/misc/mei/interrupt.c | 2 +-
drivers/misc/mei/main.c | 27 +
drivers/misc/sgi-xp/xpc_uv.c | 84 +-
drivers/misc/ti-st/st_ll.c | 2 +-
drivers/mmc/card/block.c | 26 +-
drivers/mmc/host/atmel-mci.c | 6 +-
drivers/mmc/host/bfin_sdh.c | 7 -
drivers/mmc/host/dw_mmc.c | 85 +-
drivers/mmc/host/mxs-mmc.c | 14 +-
drivers/mmc/host/omap.c | 14 +-
drivers/mmc/host/sdhci-esdhc.h | 6 +-
drivers/mtd/maps/uclinux.c | 5 +-
drivers/mtd/nand/Kconfig | 2 +-
drivers/mtd/nand/fsl_ifc_nand.c | 56 +-
drivers/mtd/nand/omap2.c | 7 +-
drivers/mtd/ubi/vtbl.c | 4 +-
drivers/net/appletalk/cops.c | 4 +-
drivers/net/appletalk/ltpc.c | 4 +-
drivers/net/bonding/bond_main.c | 12 +-
drivers/net/can/sja1000/sja1000_platform.c | 4 +-
drivers/net/can/softing/softing_fw.c | 7 +-
drivers/net/cris/eth_v10.c | 2 +-
drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 5 +-
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 4 +
drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h | 4 +-
.../net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c | 2 -
drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 85 +-
drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c | 1 +
drivers/net/ethernet/cirrus/cs89x0.c | 10 +-
drivers/net/ethernet/emulex/benet/be_cmds.c | 6 +-
drivers/net/ethernet/emulex/benet/be_main.c | 4 +-
.../net/ethernet/freescale/fs_enet/mii-bitbang.c | 4 +-
drivers/net/ethernet/freescale/fs_enet/mii-fec.c | 8 +-
drivers/net/ethernet/freescale/gianfar.c | 2 +-
drivers/net/ethernet/ibm/ehea/ehea.h | 1 -
drivers/net/ethernet/ibm/ehea/ehea_phyp.c | 12 +-
drivers/net/ethernet/ibm/ehea/ehea_qmr.c | 14 +-
drivers/net/ethernet/intel/e1000e/82571.c | 10 +-
drivers/net/ethernet/intel/e1000e/e1000.h | 1 +
drivers/net/ethernet/intel/e1000e/netdev.c | 84 +-
drivers/net/ethernet/intel/igb/e1000_82575.c | 16 +-
drivers/net/ethernet/intel/igb/e1000_regs.h | 8 +-
drivers/net/ethernet/intel/igb/igb_ethtool.c | 28 +-
drivers/net/ethernet/intel/igb/igb_main.c | 19 +-
drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c | 3 +-
drivers/net/ethernet/mellanox/mlx4/en_rx.c | 4 +-
drivers/net/ethernet/mellanox/mlx4/en_tx.c | 17 +-
drivers/net/ethernet/mellanox/mlx4/icm.c | 9 +-
drivers/net/ethernet/mellanox/mlx4/icm.h | 2 +-
drivers/net/ethernet/mellanox/mlx4/main.c | 3 -
drivers/net/ethernet/mellanox/mlx4/mcg.c | 4 +-
drivers/net/ethernet/mellanox/mlx4/mlx4.h | 4 +-
drivers/net/ethernet/mellanox/mlx4/mlx4_en.h | 1 -
drivers/net/ethernet/mellanox/mlx4/mr.c | 27 +-
drivers/net/ethernet/mellanox/mlx4/profile.c | 4 +-
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drivers/net/ethernet/nxp/lpc_eth.c | 13 -
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net/ipv6/esp6.c | 6 +-
net/ipv6/proc.c | 4 +-
net/ipv6/tcp_ipv6.c | 29 +-
net/ipv6/xfrm6_policy.c | 8 +
net/l2tp/l2tp_core.c | 3 +-
net/l2tp/l2tp_core.h | 1 +
net/l2tp/l2tp_ip6.c | 1 +
net/llc/af_llc.c | 8 +-
net/llc/llc_input.c | 21 +-
net/llc/llc_station.c | 29 +-
net/mac80211/mesh.c | 3 +
net/mac80211/mlme.c | 2 +
net/mac80211/scan.c | 3 +-
net/mac80211/tx.c | 38 +-
net/netfilter/ipvs/ip_vs_ctl.c | 5 +-
net/netfilter/nf_conntrack_core.c | 16 +-
net/netfilter/nf_conntrack_expect.c | 29 +-
net/netfilter/nf_conntrack_netlink.c | 10 +-
net/netfilter/nf_conntrack_sip.c | 92 +-
net/netfilter/nfnetlink_log.c | 6 +-
net/netlink/af_netlink.c | 6 +-
net/packet/af_packet.c | 12 +-
net/sched/act_gact.c | 14 +-
net/sched/act_ipt.c | 7 +-
net/sched/act_mirred.c | 11 +-
net/sched/act_pedit.c | 5 +-
net/sched/act_simple.c | 5 +-
net/sched/sch_qfq.c | 95 +-
net/socket.c | 5 +-
net/sunrpc/svc_xprt.c | 10 +-
net/sunrpc/svcsock.c | 2 +-
net/unix/af_unix.c | 4 +-
net/wireless/core.c | 5 +
net/wireless/core.h | 1 +
net/wireless/reg.c | 19 +-
net/wireless/util.c | 2 +-
net/xfrm/xfrm_policy.c | 2 +
net/xfrm/xfrm_state.c | 25 +-
scripts/Makefile.fwinst | 2 +-
scripts/checkpatch.pl | 3 +-
scripts/decodecode | 2 +-
scripts/kernel-doc | 1 +
scripts/link-vmlinux.sh | 2 +-
security/yama/yama_lsm.c | 43 +-
sound/arm/pxa2xx-ac97.c | 4 +-
sound/atmel/abdac.c | 3 +-
sound/atmel/ac97c.c | 14 +-
sound/core/sgbuf.c | 2 +-
sound/drivers/aloop.c | 2 +-
sound/drivers/dummy.c | 2 +-
sound/drivers/pcsp/pcsp.c | 4 +-
sound/isa/als100.c | 2 +-
sound/oss/sb_audio.c | 4 +-
sound/pci/cs46xx/cs46xx_lib.c | 2 +-
sound/pci/ctxfi/ctatc.c | 4 +-
sound/pci/emu10k1/memory.c | 5 +-
sound/pci/hda/hda_auto_parser.c | 5 +-
sound/pci/hda/hda_beep.c | 29 +-
sound/pci/hda/hda_codec.c | 83 +-
sound/pci/hda/hda_codec.h | 2 +
sound/pci/hda/hda_intel.c | 9 +
sound/pci/hda/hda_proc.c | 2 +-
sound/pci/hda/patch_ca0132.c | 174 +--
sound/pci/hda/patch_conexant.c | 6 -
sound/pci/hda/patch_hdmi.c | 12 +-
sound/pci/hda/patch_realtek.c | 8 +-
sound/pci/hda/patch_sigmatel.c | 13 +-
sound/pci/hda/patch_via.c | 8 +
sound/pci/lx6464es/lx6464es.c | 2 +
sound/pci/rme9652/hdspm.c | 2 +-
sound/pci/sis7019.c | 5 +-
sound/ppc/powermac.c | 2 +-
sound/ppc/snd_ps3.c | 1 +
sound/soc/blackfin/bf6xx-sport.c | 7 +
sound/soc/codecs/ab8500-codec.c | 4 +
sound/soc/codecs/ad1980.c | 1 +
sound/soc/codecs/mc13783.c | 2 +
sound/soc/codecs/sgtl5000.c | 3 +-
sound/soc/codecs/stac9766.c | 1 +
sound/soc/codecs/wm5102.c | 25 +-
sound/soc/codecs/wm5110.c | 12 +
sound/soc/codecs/wm8962.c | 18 +-
sound/soc/codecs/wm8994.c | 17 +-
sound/soc/codecs/wm9712.c | 22 +-
sound/soc/codecs/wm9713.c | 1 +
sound/soc/davinci/davinci-mcasp.c | 10 +-
sound/soc/fsl/imx-ssi.c | 5 +-
sound/soc/mxs/Kconfig | 2 +-
sound/soc/mxs/mxs-saif.c | 24 +
sound/soc/omap/mcbsp.c | 2 +-
sound/soc/omap/omap-mcbsp.c | 1 +
sound/soc/omap/omap-pcm.c | 1 +
sound/soc/samsung/pcm.c | 2 +-
sound/soc/soc-core.c | 12 +-
sound/soc/soc-jack.c | 2 +-
sound/soc/tegra/tegra_alc5632.c | 2 +-
sound/soc/tegra/tegra_wm8903.c | 10 +-
sound/soc/ux500/ux500_msp_dai.c | 2 +-
sound/soc/ux500/ux500_msp_i2s.c | 2 +-
sound/soc/ux500/ux500_msp_i2s.h | 2 +-
sound/usb/card.c | 4 +-
sound/usb/endpoint.c | 24 +-
sound/usb/endpoint.h | 3 +-
sound/usb/pcm.c | 61 +-
tools/perf/Makefile | 7 +-
tools/perf/builtin-record.c | 4 +-
tools/perf/builtin-report.c | 5 +-
tools/perf/builtin-test.c | 19 +-
tools/perf/builtin-top.c | 23 +-
tools/perf/util/event.h | 3 -
tools/perf/util/evlist.c | 7 +
tools/perf/util/evlist.h | 3 +
tools/perf/util/evsel.c | 15 +-
tools/perf/util/evsel.h | 10 +-
tools/perf/util/header.c | 9 +
tools/perf/util/intlist.c | 101 ++
tools/perf/util/intlist.h | 75 +
tools/perf/util/parse-events-test.c | 12 +-
tools/perf/util/parse-options.c | 3 +
tools/perf/util/python-ext-sources | 2 +
tools/perf/util/python.c | 6 +-
tools/perf/util/rblist.c | 107 ++
tools/perf/util/rblist.h | 47 +
tools/perf/util/session.c | 48 +-
tools/perf/util/session.h | 24 +-
tools/perf/util/strlist.c | 130 +-
tools/perf/util/strlist.h | 11 +-
tools/perf/util/symbol.c | 14 +-
tools/perf/util/target.c | 2 +-
virt/kvm/kvm_main.c | 7 +-
1408 files changed, 19410 insertions(+), 11578 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/ifm-csi.txt
create mode 100644 arch/alpha/include/asm/word-at-a-time.h
delete mode 100644 arch/alpha/lib/ev6-strncpy_from_user.S
delete mode 100644 arch/alpha/lib/ev67-strlen_user.S
delete mode 100644 arch/alpha/lib/strlen_user.S
delete mode 100644 arch/alpha/lib/strncpy_from_user.S
create mode 100644 arch/arm/lib/io-readsw-armv3.S
create mode 100644 arch/arm/lib/io-writesw-armv3.S
create mode 100644 arch/arm/lib/uaccess.S
rename arch/arm/mach-imx/{head-v7.S => headsmp.S} (100%)
create mode 100644 arch/arm/plat-samsung/include/plat/hdmi.h
delete mode 100644 arch/m68k/include/asm/MC68332.h
delete mode 100644 arch/m68k/include/asm/apollodma.h
delete mode 100644 arch/m68k/include/asm/bitsperlong.h
delete mode 100644 arch/m68k/include/asm/cputime.h
delete mode 100644 arch/m68k/include/asm/device.h
delete mode 100644 arch/m68k/include/asm/emergency-restart.h
delete mode 100644 arch/m68k/include/asm/errno.h
delete mode 100644 arch/m68k/include/asm/futex.h
delete mode 100644 arch/m68k/include/asm/ioctl.h
delete mode 100644 arch/m68k/include/asm/ipcbuf.h
delete mode 100644 arch/m68k/include/asm/irq_regs.h
delete mode 100644 arch/m68k/include/asm/kdebug.h
delete mode 100644 arch/m68k/include/asm/kmap_types.h
delete mode 100644 arch/m68k/include/asm/kvm_para.h
delete mode 100644 arch/m68k/include/asm/local.h
delete mode 100644 arch/m68k/include/asm/local64.h
delete mode 100644 arch/m68k/include/asm/mac_mouse.h
delete mode 100644 arch/m68k/include/asm/mcfmbus.h
delete mode 100644 arch/m68k/include/asm/mman.h
delete mode 100644 arch/m68k/include/asm/mutex.h
delete mode 100644 arch/m68k/include/asm/percpu.h
delete mode 100644 arch/m68k/include/asm/resource.h
delete mode 100644 arch/m68k/include/asm/sbus.h
delete mode 100644 arch/m68k/include/asm/scatterlist.h
delete mode 100644 arch/m68k/include/asm/sections.h
delete mode 100644 arch/m68k/include/asm/shm.h
delete mode 100644 arch/m68k/include/asm/siginfo.h
delete mode 100644 arch/m68k/include/asm/statfs.h
delete mode 100644 arch/m68k/include/asm/topology.h
delete mode 100644 arch/m68k/include/asm/types.h
delete mode 100644 arch/m68k/include/asm/xor.h
create mode 100644 arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/e500v2_power_isa.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
create mode 100644 arch/powerpc/boot/dts/o2d.dts
create mode 100644 arch/powerpc/boot/dts/o2d.dtsi
create mode 100644 arch/powerpc/boot/dts/o2d300.dts
create mode 100644 arch/powerpc/boot/dts/o2dnt2.dts
create mode 100644 arch/powerpc/boot/dts/o2i.dts
create mode 100644 arch/powerpc/boot/dts/o2mnt.dts
create mode 100644 arch/powerpc/boot/dts/o3dnt.dts
delete mode 100644 arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
delete mode 100644 arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
create mode 100644 arch/powerpc/boot/dts/p1022rdk.dts
delete mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
delete mode 100644 arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
create mode 100644 arch/powerpc/boot/dts/p5040ds.dts
delete mode 100644 arch/powerpc/include/asm/abs_addr.h
create mode 100644 arch/powerpc/include/asm/probes.h
create mode 100644 arch/powerpc/include/asm/uprobes.h
create mode 100644 arch/powerpc/kernel/uprobes.c
create mode 100644 arch/powerpc/platforms/85xx/p1022_rdk.c
create mode 100644 arch/powerpc/platforms/85xx/p5040_ds.c
create mode 100644 arch/powerpc/platforms/pseries/eeh_pe.c
create mode 100644 arch/powerpc/sysdev/fsl_mpic_err.c
create mode 100644 drivers/vhost/Kconfig.tcm
create mode 100644 drivers/vhost/tcm_vhost.c
create mode 100644 drivers/vhost/tcm_vhost.h
create mode 100644 tools/perf/util/intlist.c
create mode 100644 tools/perf/util/intlist.h
create mode 100644 tools/perf/util/rblist.c
create mode 100644 tools/perf/util/rblist.h
^ permalink raw reply
* Re: [RFC v9 PATCH 16/21] memory-hotplug: free memmap of sparse-vmemmap
From: Yasuaki Ishimatsu @ 2012-10-04 6:26 UTC (permalink / raw)
To: Ni zhan Chen
Cc: linux-s390, linux-ia64, Wen Congyang, len.brown, linux-acpi,
linux-sh, x86, linux-kernel, cmetcalf, linux-mm, paulus,
minchan.kim, kosaki.motohiro, rientjes, sparclinux, cl,
linuxppc-dev, akpm, liuj97
In-Reply-To: <506A6BDC.3010400@gmail.com>
Hi Chen,
Sorry for late reply.
2012/10/02 13:21, Ni zhan Chen wrote:
> On 09/05/2012 05:25 PM, wency@cn.fujitsu.com wrote:
>> From: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
>>
>> All pages of virtual mapping in removed memory cannot be freed, since some pages
>> used as PGD/PUD includes not only removed memory but also other memory. So the
>> patch checks whether page can be freed or not.
>>
>> How to check whether page can be freed or not?
>> 1. When removing memory, the page structs of the revmoved memory are filled
>> with 0FD.
>> 2. All page structs are filled with 0xFD on PT/PMD, PT/PMD can be cleared.
>> In this case, the page used as PT/PMD can be freed.
>>
>> Applying patch, __remove_section() of CONFIG_SPARSEMEM_VMEMMAP is integrated
>> into one. So __remove_section() of CONFIG_SPARSEMEM_VMEMMAP is deleted.
>>
>> Note: vmemmap_kfree() and vmemmap_free_bootmem() are not implemented for ia64,
>> ppc, s390, and sparc.
>>
>> CC: David Rientjes <rientjes@google.com>
>> CC: Jiang Liu <liuj97@gmail.com>
>> CC: Len Brown <len.brown@intel.com>
>> CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> CC: Paul Mackerras <paulus@samba.org>
>> CC: Christoph Lameter <cl@linux.com>
>> Cc: Minchan Kim <minchan.kim@gmail.com>
>> CC: Andrew Morton <akpm@linux-foundation.org>
>> CC: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
>> CC: Wen Congyang <wency@cn.fujitsu.com>
>> Signed-off-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
>> ---
>> arch/ia64/mm/discontig.c | 8 +++
>> arch/powerpc/mm/init_64.c | 8 +++
>> arch/s390/mm/vmem.c | 8 +++
>> arch/sparc/mm/init_64.c | 8 +++
>> arch/x86/mm/init_64.c | 119 +++++++++++++++++++++++++++++++++++++++++++++
>> include/linux/mm.h | 2 +
>> mm/memory_hotplug.c | 17 +------
>> mm/sparse.c | 5 +-
>> 8 files changed, 158 insertions(+), 17 deletions(-)
>>
>> diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
>> index 33943db..0d23b69 100644
>> --- a/arch/ia64/mm/discontig.c
>> +++ b/arch/ia64/mm/discontig.c
>> @@ -823,6 +823,14 @@ int __meminit vmemmap_populate(struct page *start_page,
>> return vmemmap_populate_basepages(start_page, size, node);
>> }
>> +void vmemmap_kfree(struct page *memmap, unsigned long nr_pages)
>> +{
>> +}
>> +
>> +void vmemmap_free_bootmem(struct page *memmap, unsigned long nr_pages)
>> +{
>> +}
>> +
>> void register_page_bootmem_memmap(unsigned long section_nr,
>> struct page *start_page, unsigned long size)
>> {
>> diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
>> index 3690c44..835a2b3 100644
>> --- a/arch/powerpc/mm/init_64.c
>> +++ b/arch/powerpc/mm/init_64.c
>> @@ -299,6 +299,14 @@ int __meminit vmemmap_populate(struct page *start_page,
>> return 0;
>> }
>> +void vmemmap_kfree(struct page *memmap, unsigned long nr_pages)
>> +{
>> +}
>> +
>> +void vmemmap_free_bootmem(struct page *memmap, unsigned long nr_pages)
>> +{
>> +}
>> +
>> void register_page_bootmem_memmap(unsigned long section_nr,
>> struct page *start_page, unsigned long size)
>> {
>> diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
>> index eda55cd..4b42b0b 100644
>> --- a/arch/s390/mm/vmem.c
>> +++ b/arch/s390/mm/vmem.c
>> @@ -227,6 +227,14 @@ out:
>> return ret;
>> }
>> +void vmemmap_kfree(struct page *memmap, unsigned long nr_pages)
>> +{
>> +}
>> +
>> +void vmemmap_free_bootmem(struct page *memmap, unsigned long nr_pages)
>> +{
>> +}
>> +
>> void register_page_bootmem_memmap(unsigned long section_nr,
>> struct page *start_page, unsigned long size)
>> {
>> diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
>> index add1cc7..1384826 100644
>> --- a/arch/sparc/mm/init_64.c
>> +++ b/arch/sparc/mm/init_64.c
>> @@ -2078,6 +2078,14 @@ void __meminit vmemmap_populate_print_last(void)
>> }
>> }
>> +void vmemmap_kfree(struct page *memmap, unsigned long nr_pages)
>> +{
>> +}
>> +
>> +void vmemmap_free_bootmem(struct page *memmap, unsigned long nr_pages)
>> +{
>> +}
>> +
>> void register_page_bootmem_memmap(unsigned long section_nr,
>> struct page *start_page, unsigned long size)
>> {
>> diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
>> index 0075592..4e8f8a4 100644
>> --- a/arch/x86/mm/init_64.c
>> +++ b/arch/x86/mm/init_64.c
>> @@ -1138,6 +1138,125 @@ vmemmap_populate(struct page *start_page, unsigned long size, int node)
>> return 0;
>> }
>> +#define PAGE_INUSE 0xFD
>> +
>> +unsigned long find_and_clear_pte_page(unsigned long addr, unsigned long end,
>> + struct page **pp, int *page_size)
>> +{
>> + pgd_t *pgd;
>> + pud_t *pud;
>> + pmd_t *pmd;
>> + pte_t *pte;
>> + void *page_addr;
>> + unsigned long next;
>> +
>> + *pp = NULL;
>> +
>> + pgd = pgd_offset_k(addr);
>> + if (pgd_none(*pgd))
>> + return pgd_addr_end(addr, end);
>> +
>> + pud = pud_offset(pgd, addr);
>> + if (pud_none(*pud))
>> + return pud_addr_end(addr, end);
>> +
>> + if (!cpu_has_pse) {
>> + next = (addr + PAGE_SIZE) & PAGE_MASK;
>> + pmd = pmd_offset(pud, addr);
>> + if (pmd_none(*pmd))
>> + return next;
>> +
>> + pte = pte_offset_kernel(pmd, addr);
>> + if (pte_none(*pte))
>> + return next;
>> +
>> + *page_size = PAGE_SIZE;
>> + *pp = pte_page(*pte);
>> + } else {
>> + next = pmd_addr_end(addr, end);
>> +
>> + pmd = pmd_offset(pud, addr);
>> + if (pmd_none(*pmd))
>> + return next;
>> +
>> + *page_size = PMD_SIZE;
>> + *pp = pmd_page(*pmd);
>> + }
>> +
>> + /*
>> + * Removed page structs are filled with 0xFD.
>> + */
>> + memset((void *)addr, PAGE_INUSE, next - addr);
>> +
>> + page_addr = page_address(*pp);
>> +
>> + /*
>> + * Check the page is filled with 0xFD or not.
>> + * memchr_inv() returns the address. In this case, we cannot
>> + * clear PTE/PUD entry, since the page is used by other.
>> + * So we cannot also free the page.
>> + *
>> + * memchr_inv() returns NULL. In this case, we can clear
>> + * PTE/PUD entry, since the page is not used by other.
>> + * So we can also free the page.
>> + */
>> + if (memchr_inv(page_addr, PAGE_INUSE, *page_size)) {
>> + *pp = NULL;
>> + return next;
>> + }
>> +
>
> Hi Yasuaki,
>
> why call memchr_inv check after memset, this time the page can always be filled with 0xFD.
The page is not always filled with 0xFD. find_and_clear_pte_page()
is calld in each section. So the function fills the page
section size/sizeof(page) byte with 0xFD one time. Thus if section size is
small, the page is filled with 0xFD.
Thanks,
Yasuaki Ishimatsu
>> + if (!cpu_has_pse)
>> + pte_clear(&init_mm, addr, pte);
>> + else
>> + pmd_clear(pmd);
>> +
>> + return next;
>> +}
>> +
>> +void vmemmap_kfree(struct page *memmap, unsigned long nr_pages)
>> +{
>> + unsigned long addr = (unsigned long)memmap;
>> + unsigned long end = (unsigned long)(memmap + nr_pages);
>> + unsigned long next;
>> + struct page *page;
>> + int page_size;
>> +
>> + for (; addr < end; addr = next) {
>> + page = NULL;
>> + page_size = 0;
>> + next = find_and_clear_pte_page(addr, end, &page, &page_size);
>> + if (!page)
>> + continue;
>> +
>> + free_pages((unsigned long)page_address(page),
>> + get_order(page_size));
>> + __flush_tlb_one(addr);
>> + }
>> +}
>> +
>> +void vmemmap_free_bootmem(struct page *memmap, unsigned long nr_pages)
>> +{
>> + unsigned long addr = (unsigned long)memmap;
>> + unsigned long end = (unsigned long)(memmap + nr_pages);
>> + unsigned long next;
>> + struct page *page;
>> + int page_size;
>> + unsigned long magic;
>> +
>> + for (; addr < end; addr = next) {
>> + page = NULL;
>> + page_size = 0;
>> + next = find_and_clear_pte_page(addr, end, &page, &page_size);
>> + if (!page)
>> + continue;
>> +
>> + magic = (unsigned long) page->lru.next;
>> + if (magic == SECTION_INFO)
>> + put_page_bootmem(page);
>> + flush_tlb_kernel_range(addr, end);
>> + }
>> +}
>> +
>> void register_page_bootmem_memmap(unsigned long section_nr,
>> struct page *start_page, unsigned long size)
>> {
>> diff --git a/include/linux/mm.h b/include/linux/mm.h
>> index c607913..fb0d1fc 100644
>> --- a/include/linux/mm.h
>> +++ b/include/linux/mm.h
>> @@ -1620,6 +1620,8 @@ int vmemmap_populate(struct page *start_page, unsigned long pages, int node);
>> void vmemmap_populate_print_last(void);
>> void register_page_bootmem_memmap(unsigned long section_nr, struct page *map,
>> unsigned long size);
>> +void vmemmap_kfree(struct page *memmpa, unsigned long nr_pages);
>> +void vmemmap_free_bootmem(struct page *memmpa, unsigned long nr_pages);
>> enum mf_flags {
>> MF_COUNT_INCREASED = 1 << 0,
>> diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
>> index 647a7f2..c54922c 100644
>> --- a/mm/memory_hotplug.c
>> +++ b/mm/memory_hotplug.c
>> @@ -308,19 +308,6 @@ static int __meminit __add_section(int nid, struct zone *zone,
>> return register_new_memory(nid, __pfn_to_section(phys_start_pfn));
>> }
>> -#ifdef CONFIG_SPARSEMEM_VMEMMAP
>> -static int __remove_section(struct zone *zone, struct mem_section *ms)
>> -{
>> - int ret = -EINVAL;
>> -
>> - if (!valid_section(ms))
>> - return ret;
>> -
>> - ret = unregister_memory_section(ms);
>> -
>> - return ret;
>> -}
>> -#else
>> static int __remove_section(struct zone *zone, struct mem_section *ms)
>> {
>> unsigned long flags;
>> @@ -337,9 +324,9 @@ static int __remove_section(struct zone *zone, struct mem_section *ms)
>> pgdat_resize_lock(pgdat, &flags);
>> sparse_remove_one_section(zone, ms);
>> pgdat_resize_unlock(pgdat, &flags);
>> - return 0;
>> +
>> + return ret;
>> }
>> -#endif
>> /*
>> * Reasonably generic function for adding memory. It is
>> diff --git a/mm/sparse.c b/mm/sparse.c
>> index fac95f2..ab9d755 100644
>> --- a/mm/sparse.c
>> +++ b/mm/sparse.c
>> @@ -613,12 +613,13 @@ static inline struct page *kmalloc_section_memmap(unsigned long pnum, int nid,
>> /* This will make the necessary allocations eventually. */
>> return sparse_mem_map_populate(pnum, nid);
>> }
>> -static void __kfree_section_memmap(struct page *memmap, unsigned long nr_pages)
>> +static void __kfree_section_memmap(struct page *page, unsigned long nr_pages)
>> {
>> - return; /* XXX: Not implemented yet */
>> + vmemmap_kfree(page, nr_pages);
>> }
>> static void free_map_bootmem(struct page *page, unsigned long nr_pages)
>> {
>> + vmemmap_free_bootmem(page, nr_pages);
>> }
>> #else
>> static struct page *__kmalloc_section_memmap(unsigned long nr_pages)
>
^ permalink raw reply
* memory-hotplug : suppres "Trying to free nonexistent resource <XXXXXXXXXXXXXXXX-YYYYYYYYYYYYYYYY>" warning
From: Yasuaki Ishimatsu @ 2012-10-04 5:31 UTC (permalink / raw)
To: x86, linux-mm, linux-kernel, linuxppc-dev, linux-acpi
Cc: len.brown, wency, paulus, minchan.kim, kosaki.motohiro, rientjes,
cl, akpm, liuj97
When our x86 box calls __remove_pages(), release_mem_region() shows
many warnings. And x86 box cannot unregister iomem_resource.
"Trying to free nonexistent resource <XXXXXXXXXXXXXXXX-YYYYYYYYYYYYYYYY>"
release_mem_region() has been changed as called in each PAGES_PER_SECTION
chunk since applying a patch(de7f0cba96786c). Because powerpc registers
iomem_resource in each PAGES_PER_SECTION chunk. But when I hot add memory
on x86 box, iomem_resource is register in each _CRS not PAGES_PER_SECTION
chunk. So x86 box unregisters iomem_resource.
The patch fixes the problem.
CC: David Rientjes <rientjes@google.com>
CC: Jiang Liu <liuj97@gmail.com>
CC: Len Brown <len.brown@intel.com>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Paul Mackerras <paulus@samba.org>
CC: Christoph Lameter <cl@linux.com>
Cc: Minchan Kim <minchan.kim@gmail.com>
CC: Andrew Morton <akpm@linux-foundation.org>
CC: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
CC: Wen Congyang <wency@cn.fujitsu.com>
Signed-off-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>
---
arch/powerpc/platforms/pseries/hotplug-memory.c | 13 +++++++++----
mm/memory_hotplug.c | 4 ++--
2 files changed, 11 insertions(+), 6 deletions(-)
Index: linux-3.6/arch/powerpc/platforms/pseries/hotplug-memory.c
===================================================================
--- linux-3.6.orig/arch/powerpc/platforms/pseries/hotplug-memory.c 2012-10-04 14:22:59.833520792 +0900
+++ linux-3.6/arch/powerpc/platforms/pseries/hotplug-memory.c 2012-10-04 14:23:05.150521411 +0900
@@ -77,7 +77,8 @@ static int pseries_remove_memblock(unsig
{
unsigned long start, start_pfn;
struct zone *zone;
- int ret;
+ int i, ret;
+ int sections_to_remove;
start_pfn = base >> PAGE_SHIFT;
@@ -97,9 +98,13 @@ static int pseries_remove_memblock(unsig
* to sysfs "state" file and we can't remove sysfs entries
* while writing to it. So we have to defer it to here.
*/
- ret = __remove_pages(zone, start_pfn, memblock_size >> PAGE_SHIFT);
- if (ret)
- return ret;
+ sections_to_remove = (memblock_size >> PAGE_SHIFT) / PAGES_PER_SECTION;
+ for (i = 0; i < sections_to_remove; i++) {
+ unsigned long pfn = start_pfn + i * PAGES_PER_SECTION;
+ ret = __remove_pages(zone, start_pfn, PAGES_PER_SECTION);
+ if (ret)
+ return ret;
+ }
/*
* Update memory regions for memory remove
Index: linux-3.6/mm/memory_hotplug.c
===================================================================
--- linux-3.6.orig/mm/memory_hotplug.c 2012-10-04 14:22:59.829520788 +0900
+++ linux-3.6/mm/memory_hotplug.c 2012-10-04 14:23:25.860527278 +0900
@@ -362,11 +362,11 @@ int __remove_pages(struct zone *zone, un
BUG_ON(phys_start_pfn & ~PAGE_SECTION_MASK);
BUG_ON(nr_pages % PAGES_PER_SECTION);
+ release_mem_region(phys_start_pfn << PAGE_SHIFT, nr_pages * PAGE_SIZE);
+
sections_to_remove = nr_pages / PAGES_PER_SECTION;
for (i = 0; i < sections_to_remove; i++) {
unsigned long pfn = phys_start_pfn + i*PAGES_PER_SECTION;
- release_mem_region(pfn << PAGE_SHIFT,
- PAGES_PER_SECTION << PAGE_SHIFT);
ret = __remove_section(zone, __pfn_to_section(pfn));
if (ret)
break;
^ permalink raw reply
* [PATCH] powerpc/iommu: Fix multiple issues with IOMMU pools code
From: Anton Blanchard @ 2012-10-04 4:57 UTC (permalink / raw)
To: Alexander Graf
Cc: linux-nfs, Jan Kara, Nishanth Aravamudan, linuxppc-dev, LKML List,
J. Bruce Fields, skinsbursky, bfields, Linus Torvalds
In-Reply-To: <E141CA01-F58C-47B1-8ED5-A314D1DEC968@suse.de>
Hi Alex,
Looks to be a preempt issue with the iommu pools code. I did find a
couple more bugs along the way too.
Anton
--
There are a number of issues in the recent IOMMU pools code:
- On a preempt kernel we might switch CPUs in the middle of building
a scatter gather list. When this happens the handle hint passed in
no longer falls within the local CPU's pool. Check for this and
fall back to the pool hint.
- We were missing a spin_unlock/spin_lock in one spot where we
switch pools.
- We need to provide locking around dart_tlb_invalidate_all and
dart_tlb_invalidate_one now that the global lock is gone.
Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anton Blanchard <anton@samba.org>
---
There is still an issue with the lazy u3 flushing, but I wanted
to get this out for testing.
Index: b/arch/powerpc/kernel/iommu.c
===================================================================
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -215,7 +215,8 @@ static unsigned long iommu_range_alloc(s
spin_lock_irqsave(&(pool->lock), flags);
again:
- if ((pass == 0) && handle && *handle)
+ if ((pass == 0) && handle && *handle &&
+ (*handle >= pool->start) && (*handle < pool->end))
start = *handle;
else
start = pool->hint;
@@ -236,7 +237,9 @@ again:
* but on second pass, start at 0 in pool 0.
*/
if ((start & mask) >= limit || pass > 0) {
+ spin_unlock(&(pool->lock));
pool = &(tbl->pools[0]);
+ spin_lock(&(pool->lock));
start = pool->start;
} else {
start &= mask;
Index: b/arch/powerpc/sysdev/dart_iommu.c
===================================================================
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -74,11 +74,16 @@ static int dart_is_u4;
#define DBG(...)
+static DEFINE_SPINLOCK(invalidate_lock);
+
static inline void dart_tlb_invalidate_all(void)
{
unsigned long l = 0;
unsigned int reg, inv_bit;
unsigned long limit;
+ unsigned long flags;
+
+ spin_lock_irqsave(&invalidate_lock, flags);
DBG("dart: flush\n");
@@ -111,12 +116,17 @@ retry:
panic("DART: TLB did not flush after waiting a long "
"time. Buggy U3 ?");
}
+
+ spin_unlock_irqrestore(&invalidate_lock, flags);
}
static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
{
unsigned int reg;
unsigned int l, limit;
+ unsigned long flags;
+
+ spin_lock_irqsave(&invalidate_lock, flags);
reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
(bus_rpn & DART_CNTL_U4_IONE_MASK);
@@ -138,6 +148,8 @@ wait_more:
panic("DART: TLB did not flush after waiting a long "
"time. Buggy U4 ?");
}
+
+ spin_unlock_irqrestore(&invalidate_lock, flags);
}
static void dart_flush(struct iommu_table *tbl)
^ permalink raw reply
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