* [PATCH 03/14] powerpc: Remove unessessary 0x3000 location enforcement
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
This removes the large gap between 0x1800 and 0x3000.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/exceptions-64s.S | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 29cf7b1..de02964 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -311,12 +311,14 @@ denorm_exception_hv:
#ifdef CONFIG_CBE_RAS
STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal)
KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1802)
+#else
+ . = 0x1800
#endif /* CONFIG_CBE_RAS */
- . = 0x3000
/*** Out of line interrupts support ***/
+ .align 7
/* moved from 0x200 */
machine_check_pSeries:
.globl machine_check_fwnmi
--
1.7.9.5
^ permalink raw reply related
* [PATCH 04/14] powerpc: Make load_hander handle upto 64k offset
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
If we change load_hander() to use an ori instead of addi, we can load handlers
upto 64k away provided we are still 64k aligned.
---
arch/powerpc/include/asm/exception-64s.h | 3 ++-
arch/powerpc/kernel/exceptions-64s.S | 4 ++--
arch/powerpc/kernel/setup_64.c | 5 +++++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index a43c147..9258daa 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -55,7 +55,8 @@
* word.
*/
#define LOAD_HANDLER(reg, label) \
- addi reg,reg,(label)-_stext; /* virt addr of handler ... */
+ /* Handlers must be within 64K of kbase, which must be 64k aligned */ \
+ ori reg,reg,(label)-_stext; /* virt addr of handler ... */
/* Exception register prefixes */
#define EXC_HV H
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index de02964..0969b7f 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -585,8 +585,8 @@ __end_interrupts:
* Code from here down to __end_handlers is invoked from the
* exception prologs above. Because the prologs assemble the
* addresses of these handlers using the LOAD_HANDLER macro,
- * which uses an addi instruction, these handlers must be in
- * the first 32k of the kernel image.
+ * which uses an ori instruction, these handlers must be in
+ * the first 64k of the kernel image.
*/
/*** Common interrupt handlers ***/
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index efb6a41..6da881b 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -601,6 +601,11 @@ void __init setup_arch(char **cmdline_p)
kvm_linear_init();
+ /* Interrupt code needs to be 64K-aligned */
+ if ((unsigned long)_stext & 0xffff)
+ panic("Kernelbase not 64K-aligned (0x%lx)!\n",
+ (unsigned long)_stext);
+
ppc64_boot_msg(0x15, "Setup Done");
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH 05/14] powerpc: Turn syscall handler into macros
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
This turns the syscall handler into macros as we are going to want to reuse
them again later.
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/exceptions-64s.S | 63 +++++++++++++++++++++-------------
1 file changed, 40 insertions(+), 23 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 0969b7f..85b3c7e 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -25,6 +25,43 @@
* 0x7000 - 0x7fff : FWNMI data area
* 0x8000 - : Early init and support code
*/
+ /* Syscall routine is used twice, in reloc-off and reloc-on paths */
+#define SYSCALL_PSERIES_1 \
+BEGIN_FTR_SECTION \
+ cmpdi r0,0x1ebe ; \
+ beq- 1f ; \
+END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
+ mr r9,r13 ; \
+ GET_PACA(r13) ; \
+ mfspr r11,SPRN_SRR0 ; \
+0:
+
+#define SYSCALL_PSERIES_2_RFID \
+ mfspr r12,SPRN_SRR1 ; \
+ ld r10,PACAKBASE(r13) ; \
+ LOAD_HANDLER(r10, system_call_entry) ; \
+ mtspr SPRN_SRR0,r10 ; \
+ ld r10,PACAKMSR(r13) ; \
+ mtspr SPRN_SRR1,r10 ; \
+ rfid ; \
+ b . ; /* prevent speculative execution */
+
+#define SYSCALL_PSERIES_3 \
+ /* Fast LE/BE switch system call */ \
+1: mfspr r12,SPRN_SRR1 ; \
+ xori r12,r12,MSR_LE ; \
+ mtspr SPRN_SRR1,r12 ; \
+ rfid ; /* return to userspace */ \
+ b . ; \
+2: mfspr r12,SPRN_SRR1 ; \
+ andi. r12,r12,MSR_PR ; \
+ bne 0b ; \
+ mtspr SPRN_SRR0,r3 ; \
+ mtspr SPRN_SRR1,r4 ; \
+ mtspr SPRN_SDR1,r5 ; \
+ rfid ; \
+ b . ; /* prevent speculative execution */
+
/*
* This is the start of the interrupt handlers for pSeries
@@ -207,31 +244,11 @@ system_call_pSeries:
KVMTEST(0xc00)
GET_SCRATCH0(r13)
#endif
-BEGIN_FTR_SECTION
- cmpdi r0,0x1ebe
- beq- 1f
-END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
- mr r9,r13
- GET_PACA(r13)
- mfspr r11,SPRN_SRR0
- mfspr r12,SPRN_SRR1
- ld r10,PACAKBASE(r13)
- LOAD_HANDLER(r10, system_call_entry)
- mtspr SPRN_SRR0,r10
- ld r10,PACAKMSR(r13)
- mtspr SPRN_SRR1,r10
- rfid
- b . /* prevent speculative execution */
-
+ SYSCALL_PSERIES_1
+ SYSCALL_PSERIES_2_RFID
+ SYSCALL_PSERIES_3
KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
-/* Fast LE/BE switch system call */
-1: mfspr r12,SPRN_SRR1
- xori r12,r12,MSR_LE
- mtspr SPRN_SRR1,r12
- rfid /* return to userspace */
- b .
-
STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step)
KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xd00)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 06/14] powerpc: Add new macros needed for relocation on exceptions
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
POWER8/v2.07 allows exceptions to be taken with the MMU still on.
A new set of exception vectors is added at 0xc000_0000_0000_4xxx. When the HW
takes us here, MSR IR/DR will be set already and we no longer need a costly
RFID to turn the MMU back on again.
The original 0x0 based exception vectors remain for when the HW can't leave the
MMU on. Examples of this are when we can't trust the current the MMU mappings,
like when we are changing from guest to hypervisor (HV 0 -> 1) or when the MMU
was off already. In these cases the HW will take us to the original 0x0 based
exception vectors with the MMU off as before.
The below macros are copies of the macros used at the 0x0 offset but modified
to handle the MMU being on. In these macros we use the link register to jump
to the secondary handlers rather than using RFID (RFID was also use to turn on
the MMU).
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/exception-64s.h | 90 ++++++++++++++++++++++++++++++
arch/powerpc/kernel/exceptions-64s.S | 25 +++++++++
2 files changed, 115 insertions(+)
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 9258daa..10787d3 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -48,6 +48,35 @@
#define EX_LR 72
#define EX_CFAR 80
+#ifdef CONFIG_RELOCATABLE
+#define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
+ ld r12,PACAKBASE(r13); /* get high part of &label */ \
+ mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
+ LOAD_HANDLER(r12,label); \
+ mtlr r12; \
+ mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
+ li r10,MSR_RI; \
+ mtmsrd r10,1; /* Set RI (EE=0) */ \
+ blr;
+#else
+/* If not relocatable, we can jump directly -- and save messing with LR */
+#define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \
+ mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \
+ mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \
+ li r10,MSR_RI; \
+ mtmsrd r10,1; /* Set RI (EE=0) */ \
+ b label;
+#endif
+
+/*
+ * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on
+ * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which
+ * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr.
+ */
+#define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \
+ EXCEPTION_PROLOG_1(area, extra, vec); \
+ EXCEPTION_RELON_PROLOG_PSERIES_1(label, h)
+
/*
* We're short on space and time in the exception prolog, so we can't
* use the normal SET_REG_IMMEDIATE macro. Normally we just need the
@@ -62,6 +91,22 @@
#define EXC_HV H
#define EXC_STD
+#if defined(CONFIG_RELOCATABLE)
+/*
+ * If we support interrupts with relocation on AND we're a relocatable
+ * kernel, we need to use LR to get to the 2nd level handler. So, save/restore
+ * it when required.
+ */
+#define SAVE_LR(reg, area) mflr reg ; std reg,area+EX_LR(r13)
+#define GET_LR(reg, area) ld reg,area+EX_LR(r13)
+#define RESTORE_LR(reg, area) ld reg,area+EX_LR(r13) ; mtlr reg
+#else
+/* ...else LR is unused and in register. */
+#define SAVE_LR(reg, area)
+#define GET_LR(reg, area) mflr reg
+#define RESTORE_LR(reg, area)
+#endif
+
#define __EXCEPTION_PROLOG_1(area, extra, vec) \
GET_PACA(r13); \
std r9,area+EX_R9(r13); /* save r9 - r12 */ \
@@ -233,6 +278,26 @@ label##_hv: \
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
EXC_HV, KVMTEST, vec)
+#define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \
+ . = loc; \
+ .globl label##_relon_pSeries; \
+label##_relon_pSeries: \
+ HMT_MEDIUM; \
+ /* No guest interrupts come through here */ \
+ SET_SCRATCH0(r13); /* save r13 */ \
+ EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
+ EXC_STD, KVMTEST_PR, vec)
+
+#define STD_RELON_EXCEPTION_HV(loc, vec, label) \
+ . = loc; \
+ .globl label##_relon_hv; \
+label##_relon_hv: \
+ HMT_MEDIUM; \
+ /* No guest interrupts come through here */ \
+ SET_SCRATCH0(r13); /* save r13 */ \
+ EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
+ EXC_HV, KVMTEST, vec)
+
/* This associate vector numbers with bits in paca->irq_happened */
#define SOFTEN_VALUE_0x500 PACA_IRQ_EE
#define SOFTEN_VALUE_0x502 PACA_IRQ_EE
@@ -258,6 +323,9 @@ label##_hv: \
KVMTEST(vec); \
_SOFTEN_TEST(EXC_STD, vec)
+#define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec)
+#define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec)
+
#define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \
HMT_MEDIUM; \
SET_SCRATCH0(r13); /* save r13 */ \
@@ -280,6 +348,28 @@ label##_hv: \
_MASKABLE_EXCEPTION_PSERIES(vec, label, \
EXC_HV, SOFTEN_TEST_HV)
+#define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
+ HMT_MEDIUM; \
+ SET_SCRATCH0(r13); /* save r13 */ \
+ __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \
+ EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, h);
+#define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \
+ __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra)
+
+#define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \
+ . = loc; \
+ .globl label##_relon_pSeries; \
+label##_relon_pSeries: \
+ _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
+ EXC_STD, SOFTEN_NOTEST_PR)
+
+#define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \
+ . = loc; \
+ .globl label##_relon_hv; \
+label##_relon_hv: \
+ _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \
+ EXC_HV, SOFTEN_NOTEST_HV)
+
/*
* Our exception common code can be passed various "additions"
* to specify the behaviour of interrupts, whether to kick the
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 85b3c7e..4dc1a04 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -62,6 +62,31 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
rfid ; \
b . ; /* prevent speculative execution */
+#if defined(CONFIG_RELOCATABLE)
+ /*
+ * We can't branch directly; in the direct case we use LR
+ * and system_call_entry restores LR. (We thus need to move
+ * LR to r10 in the RFID case too.)
+ */
+#define SYSCALL_PSERIES_2_DIRECT \
+ mflr r10 ; \
+ ld r12,PACAKBASE(r13) ; \
+ LOAD_HANDLER(r12, system_call_entry_direct) ; \
+ mtlr r12 ; \
+ mfspr r12,SPRN_SRR1 ; \
+ /* Re-use of r13... No spare regs to do this */ \
+ li r13,MSR_RI ; \
+ mtmsrd r13,1 ; \
+ GET_PACA(r13) ; /* get r13 back */ \
+ blr ;
+#else
+ /* We can branch directly */
+#define SYSCALL_PSERIES_2_DIRECT \
+ mfspr r12,SPRN_SRR1 ; \
+ li r10,MSR_RI ; \
+ mtmsrd r10,1 ; /* Set RI (EE=0) */ \
+ b system_call_entry_direct ;
+#endif
/*
* This is the start of the interrupt handlers for pSeries
--
1.7.9.5
^ permalink raw reply related
* [PATCH 07/14] powerpc: Add relocation on exception vector handlers
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
POWER8/v2.07 allows exceptions to be taken with the MMU still on.
A new set of exception vectors is added at 0xc000_0000_0000_4xxx. When the HW
takes us here, MSR IR/DR will be set already and we no longer need a costly
RFID to turn the MMU back on again.
The original 0x0 based exception vectors remain for when the HW can't leave the
MMU on. Examples of this are when we can't trust the current the MMU mappings,
like when we are changing from guest to hypervisor (HV 0 -> 1) or when the MMU
was off already. In these cases the HW will take us to the original 0x0 based
exception vectors with the MMU off as before.
This uses the new macros added previously too implement these new execption
vectors at 0xc000_0000_0000_4xxx. We exit these exception vectors using
mflr/blr (rather than mtspr SSR0/RFID), since we don't need the costly MMU
switch anymore.
This moves the __end_interrupts marker down past these new 0x4000 vectors since
they will need to be copied down to 0x0 when the kernel is not at 0x0.
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/exception-64s.h | 4 +-
arch/powerpc/kernel/exceptions-64s.S | 180 ++++++++++++++++++++++++++++--
arch/powerpc/kernel/head_64.S | 3 +-
3 files changed, 177 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 10787d3..ad708dd 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -115,6 +115,7 @@
mfspr r10,SPRN_CFAR; \
std r10,area+EX_CFAR(r13); \
END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
+ SAVE_LR(r10, area); \
mfcr r9; \
extra(vec); \
std r11,area+EX_R11(r13); \
@@ -215,6 +216,7 @@ do_kvm_##n: \
sth r1,PACA_TRAP_SAVE(r13); \
std r3,area+EX_R3(r13); \
addi r3,r13,area; /* r3 -> where regs are saved*/ \
+ RESTORE_LR(r1, area); \
b bad_stack; \
3: std r9,_CCR(r1); /* save CR in stackframe */ \
std r11,_NIP(r1); /* save SRR0 in stackframe */ \
@@ -240,8 +242,8 @@ do_kvm_##n: \
ld r10,area+EX_CFAR(r13); \
std r10,ORIG_GPR3(r1); \
END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
+ GET_LR(r9,area); /* Get LR, later save to stack */ \
ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
- mflr r9; /* save LR in stackframe */ \
std r9,_LINK(r1); \
mfctr r10; /* save CTR in stackframe */ \
std r10,_CTR(r1); \
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 4dc1a04..fb95747 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -19,11 +19,13 @@
/*
* We layout physical memory as follows:
* 0x0000 - 0x00ff : Secondary processor spin code
- * 0x0100 - 0x2fff : pSeries Interrupt prologs
- * 0x3000 - 0x5fff : interrupt support common interrupt prologs
- * 0x6000 - 0x6fff : Initial (CPU0) segment table
+ * 0x0100 - 0x17ff : pSeries Interrupt prologs
+ * 0x1800 - 0x4000 : interrupt support common interrupt prologs
+ * 0x4000 - 0x5fff : pSeries interrupts with IR=1,DR=1
+ * 0x6000 - 0x6fff : more interrupt support including for IR=1,DR=1
* 0x7000 - 0x7fff : FWNMI data area
- * 0x8000 - : Early init and support code
+ * 0x8000 - 0x8fff : Initial (CPU0) segment table
+ * 0x9000 - : Early init and support code
*/
/* Syscall routine is used twice, in reloc-off and reloc-on paths */
#define SYSCALL_PSERIES_1 \
@@ -619,10 +621,6 @@ slb_miss_user_pseries:
b . /* prevent spec. execution */
#endif /* __DISABLED__ */
- .align 7
- .globl __end_interrupts
-__end_interrupts:
-
/*
* Code from here down to __end_handlers is invoked from the
* exception prologs above. Because the prologs assemble the
@@ -673,7 +671,158 @@ machine_check_common:
STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
#endif /* CONFIG_CBE_RAS */
+ /*
+ * Relocation-on interrupts: A subset of the interrupts can be delivered
+ * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
+ * it. Addresses are the same as the original interrupt addresses, but
+ * offset by 0xc000000000004000.
+ * It's impossible to receive interrupts below 0x300 via this mechanism.
+ * KVM: None of these traps are from the guest ; anything that escalated
+ * to HV=1 from HV=0 is delivered via real mode handlers.
+ */
+
+ /*
+ * This uses the standard macro, since the original 0x300 vector
+ * only has extra guff for STAB-based processors -- which never
+ * come here.
+ */
+ STD_RELON_EXCEPTION_PSERIES(0x4300, 0x300, data_access)
+ . = 0x4380
+ .globl data_access_slb_relon_pSeries
+data_access_slb_relon_pSeries:
+ HMT_MEDIUM
+ SET_SCRATCH0(r13)
+ EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
+ std r3,PACA_EXSLB+EX_R3(r13)
+ mfspr r3,SPRN_DAR
+ mfspr r12,SPRN_SRR1
+#ifndef CONFIG_RELOCATABLE
+ b .slb_miss_realmode
+#else
+ /*
+ * We can't just use a direct branch to .slb_miss_realmode
+ * because the distance from here to there depends on where
+ * the kernel ends up being put.
+ */
+ mfctr r11
+ ld r10,PACAKBASE(r13)
+ LOAD_HANDLER(r10, .slb_miss_realmode)
+ mtctr r10
+ bctr
+#endif
+
+ STD_RELON_EXCEPTION_PSERIES(0x4400, 0x400, instruction_access)
+ . = 0x4480
+ .globl instruction_access_slb_relon_pSeries
+instruction_access_slb_relon_pSeries:
+ HMT_MEDIUM
+ SET_SCRATCH0(r13)
+ EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
+ std r3,PACA_EXSLB+EX_R3(r13)
+ mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
+ mfspr r12,SPRN_SRR1
+#ifndef CONFIG_RELOCATABLE
+ b .slb_miss_realmode
+#else
+ mfctr r11
+ ld r10,PACAKBASE(r13)
+ LOAD_HANDLER(r10, .slb_miss_realmode)
+ mtctr r10
+ bctr
+#endif
+
+ . = 0x4500
+ .globl hardware_interrupt_relon_pSeries;
+ .globl hardware_interrupt_relon_hv;
+hardware_interrupt_relon_pSeries:
+hardware_interrupt_relon_hv:
+ BEGIN_FTR_SECTION
+ _MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV)
+ FTR_SECTION_ELSE
+ _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR)
+ ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_206)
+ STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment)
+ STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check)
+ STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable)
+ MASKABLE_RELON_EXCEPTION_PSERIES(0x4900, 0x900, decrementer)
+ STD_RELON_EXCEPTION_PSERIES(0x4980, 0x980, hdecrementer)
+ STD_RELON_EXCEPTION_PSERIES(0x4b00, 0xb00, trap_0b)
+
+ . = 0x4c00
+ .globl system_call_relon_pSeries
+system_call_relon_pSeries:
+ HMT_MEDIUM
+ SYSCALL_PSERIES_1
+ SYSCALL_PSERIES_2_DIRECT
+ SYSCALL_PSERIES_3
+
+ STD_RELON_EXCEPTION_PSERIES(0x4d00, 0xd00, single_step)
+
+ . = 0x4e00
+ b h_data_storage_relon_hv
+
+ . = 0x4e20
+ b h_instr_storage_relon_hv
+
+ . = 0x4e40
+ b emulation_assist_relon_hv
+
+ . = 0x4e50
+ b hmi_exception_relon_hv
+
+ . = 0x4e60
+ b hmi_exception_relon_hv
+
+ /* For when we support the doorbell interrupt:
+ STD_RELON_EXCEPTION_HYPERVISOR(0x4e80, 0xe80, doorbell_hyper)
+ */
+
+performance_monitor_relon_pSeries_1:
+ . = 0x4f00
+ b performance_monitor_relon_pSeries
+
+altivec_unavailable_relon_pSeries_1:
+ . = 0x4f20
+ b altivec_unavailable_relon_pSeries
+
+vsx_unavailable_relon_pSeries_1:
+ . = 0x4f40
+ b vsx_unavailable_relon_pSeries
+
+#ifdef CONFIG_CBE_RAS
+ STD_RELON_EXCEPTION_HV(0x5200, 0x1202, cbe_system_error)
+#endif /* CONFIG_CBE_RAS */
+ STD_RELON_EXCEPTION_PSERIES(0x5300, 0x1300, instruction_breakpoint)
+#ifdef CONFIG_PPC_DENORMALISATION
+ . = 0x5500
+ b denorm_exception_hv
+#endif
+#ifdef CONFIG_CBE_RAS
+ STD_RELON_EXCEPTION_HV(0x5600, 0x1602, cbe_maintenance)
+#else
+#ifdef CONFIG_HVC_SCOM
+ STD_RELON_EXCEPTION_HV(0x5600, 0x1600, maintence_interrupt)
+ KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1600)
+#endif /* CONFIG_HVC_SCOM */
+#endif /* CONFIG_CBE_RAS */
+ STD_RELON_EXCEPTION_PSERIES(0x5700, 0x1700, altivec_assist)
+#ifdef CONFIG_CBE_RAS
+ STD_RELON_EXCEPTION_HV(0x5800, 0x1802, cbe_thermal)
+#endif /* CONFIG_CBE_RAS */
+
+ /* Other future vectors */
+ .align 7
+ .globl __end_interrupts
+__end_interrupts:
+
.align 7
+system_call_entry_direct:
+#if defined(CONFIG_RELOCATABLE)
+ /* The first level prologue may have used LR to get here, saving
+ * orig in r10. To save hacking/ifdeffing common code, restore here.
+ */
+ mtlr r10
+#endif
system_call_entry:
b system_call_common
@@ -1196,6 +1345,21 @@ _GLOBAL(do_stab_bolted)
rfid
b . /* prevent speculative execution */
+
+ /* Equivalents to the above handlers for relocation-on interrupt vectors */
+ STD_RELON_EXCEPTION_HV(., 0xe00, h_data_storage)
+ KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe00)
+ STD_RELON_EXCEPTION_HV(., 0xe20, h_instr_storage)
+ KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe20)
+ STD_RELON_EXCEPTION_HV(., 0xe40, emulation_assist)
+ KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe40)
+ STD_RELON_EXCEPTION_HV(., 0xe60, hmi_exception)
+ KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe60)
+
+ STD_RELON_EXCEPTION_PSERIES(., 0xf00, performance_monitor)
+ STD_RELON_EXCEPTION_PSERIES(., 0xf20, altivec_unavailable)
+ STD_RELON_EXCEPTION_PSERIES(., 0xf40, vsx_unavailable)
+
#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
/*
* Data area reserved for FWNMI option.
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 58bddee..d5a4efe 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -432,7 +432,8 @@ _STATIC(__after_prom_start)
cmplwi cr0,r7,1
bne 3f
- li r5,__end_interrupts - _stext /* just copy interrupts */
+ /* just copy interrupts */
+ LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext)
b 5f
3:
#endif
--
1.7.9.5
^ permalink raw reply related
* [PATCH 08/14] powerpc: Move initial mfspr LPCR out of __init_LPCR
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
We want to change what's initially set in the LPCR, so start by taking the move
from LPCR out of the function and into the caller.
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/cpu_setup_power.S | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index a92101d..52dd033 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -27,6 +27,7 @@ _GLOBAL(__setup_cpu_power7)
beqlr
li r0,0
mtspr SPRN_LPID,r0
+ mfspr r3,SPRN_LPCR
bl __init_LPCR
bl __init_TLB
mtlr r11
@@ -39,6 +40,7 @@ _GLOBAL(__restore_cpu_power7)
beqlr
li r0,0
mtspr SPRN_LPID,r0
+ mfspr r3,SPRN_LPCR
bl __init_LPCR
bl __init_TLB
mtlr r11
@@ -51,6 +53,7 @@ _GLOBAL(__setup_cpu_power8)
beqlr
li r0,0
mtspr SPRN_LPID,r0
+ mfspr r3,SPRN_LPCR
bl __init_LPCR
bl __init_TLB
mtlr r11
@@ -63,6 +66,7 @@ _GLOBAL(__restore_cpu_power8)
beqlr
li r0,0
mtspr SPRN_LPID,r0
+ mfspr r3,SPRN_LPCR
bl __init_LPCR
bl __init_TLB
mtlr r11
@@ -81,6 +85,7 @@ __init_hvmode_206:
__init_LPCR:
/* Setup a sane LPCR:
+ * Called with initial LPCR in R3
*
* LPES = 0b01 (HSRR0/1 used for 0x500)
* PECE = 0b111
@@ -91,7 +96,6 @@ __init_LPCR:
*
* Other bits untouched for now
*/
- mfspr r3,SPRN_LPCR
li r5,1
rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 09/14] powerpc: Setup relocation on exceptions for bare metal systems
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
This turns on MMU on execptions via AIL field in the LPCR.
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/reg.h | 2 ++
arch/powerpc/kernel/cpu_setup_power.S | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 7b44a6e..886ab8e 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -249,6 +249,8 @@
#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
#define LPCR_RMLS_SH (63-37)
#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
+#define LPCR_AIL_0 0x00000000 /* MMU off IRQ location 0x0 */
+#define LPCR_AIL_3 0x01800000 /* MMU on IRQ location 0xc00...4xxx */
#define LPCR_PECE 0x00007000 /* powersave exit cause enable */
#define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */
#define LPCR_PECE1 0x00002000 /* decrementer can cause exit */
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index 52dd033..57cf140 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -54,6 +54,7 @@ _GLOBAL(__setup_cpu_power8)
li r0,0
mtspr SPRN_LPID,r0
mfspr r3,SPRN_LPCR
+ oris r3, r3, LPCR_AIL_3@h
bl __init_LPCR
bl __init_TLB
mtlr r11
@@ -67,6 +68,7 @@ _GLOBAL(__restore_cpu_power8)
li r0,0
mtspr SPRN_LPID,r0
mfspr r3,SPRN_LPCR
+ oris r3, r3, LPCR_AIL_3@h
bl __init_LPCR
bl __init_TLB
mtlr r11
--
1.7.9.5
^ permalink raw reply related
* [PATCH 10/14] powerpc: Add set_mode hcall
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
From: Ian Munsie <imunsie@au1.ibm.com>
This new hcall in POWER8 is used to set various resource mode registers.
eg. it can set address translation mode on interrupt (note: partition wide
scope)
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/firmware.h | 4 +++-
arch/powerpc/include/asm/hvcall.h | 3 ++-
arch/powerpc/platforms/pseries/firmware.c | 1 +
arch/powerpc/platforms/pseries/plpar_wrappers.h | 6 ++++++
4 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index ad0b751..973cc3b 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -49,6 +49,7 @@
#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
#define FW_FEATURE_OPAL ASM_CONST(0x0000000010000000)
#define FW_FEATURE_OPALv2 ASM_CONST(0x0000000020000000)
+#define FW_FEATURE_SET_MODE ASM_CONST(0x0000000040000000)
#ifndef __ASSEMBLY__
@@ -62,7 +63,8 @@ enum {
FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
- FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO,
+ FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO |
+ FW_FEATURE_SET_MODE,
FW_FEATURE_PSERIES_ALWAYS = 0,
FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2,
FW_FEATURE_POWERNV_ALWAYS = 0,
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index 7a86706..a3d26d8 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -267,7 +267,8 @@
#define H_RANDOM 0x300
#define H_COP 0x304
#define H_GET_MPP_X 0x314
-#define MAX_HCALL_OPCODE H_GET_MPP_X
+#define H_SET_MODE 0x31C
+#define MAX_HCALL_OPCODE H_SET_MODE
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/platforms/pseries/firmware.c b/arch/powerpc/platforms/pseries/firmware.c
index 0b0eff0..7b56118 100644
--- a/arch/powerpc/platforms/pseries/firmware.c
+++ b/arch/powerpc/platforms/pseries/firmware.c
@@ -56,6 +56,7 @@ firmware_features_table[FIRMWARE_MAX_FEATURES] = {
{FW_FEATURE_MULTITCE, "hcall-multi-tce"},
{FW_FEATURE_SPLPAR, "hcall-splpar"},
{FW_FEATURE_VPHN, "hcall-vphn"},
+ {FW_FEATURE_SET_MODE, "hcall-set-mode"},
};
/* Build up the firmware features bitmask using the contents of
diff --git a/arch/powerpc/platforms/pseries/plpar_wrappers.h b/arch/powerpc/platforms/pseries/plpar_wrappers.h
index 13e8cc4..44ad214 100644
--- a/arch/powerpc/platforms/pseries/plpar_wrappers.h
+++ b/arch/powerpc/platforms/pseries/plpar_wrappers.h
@@ -273,4 +273,10 @@ static inline long plpar_put_term_char(unsigned long termno, unsigned long len,
lbuf[1]);
}
+/* Set various resource mode parameters */
+static inline long plpar_set_mode(unsigned long mflags, unsigned long resource,
+ unsigned long value1, unsigned long value2)
+{
+ return plpar_hcall_norets(H_SET_MODE, mflags, resource, value1, value2);
+}
#endif /* _PSERIES_PLPAR_WRAPPERS_H */
--
1.7.9.5
^ permalink raw reply related
* [PATCH 10/12] powerpc: Move get_longbusy_msecs into hvcall.h and remove duplicate function
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
From: Ian Munsie <imunsie@au1.ibm.com>
I am going to use this in the next patch, better to have this code in
one place rather than three.
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/hvcall.h | 20 ++++++++++++++++++++
drivers/infiniband/hw/ehca/hcp_if.c | 20 --------------------
drivers/net/ethernet/ibm/ehea/ehea_phyp.h | 20 --------------------
3 files changed, 20 insertions(+), 40 deletions(-)
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index a3d26d8..0975e5c 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -356,6 +356,26 @@ struct hvcall_mpp_x_data {
int h_get_mpp_x(struct hvcall_mpp_x_data *mpp_x_data);
+static inline unsigned int get_longbusy_msecs(int longbusy_rc)
+{
+ switch (longbusy_rc) {
+ case H_LONG_BUSY_ORDER_1_MSEC:
+ return 1;
+ case H_LONG_BUSY_ORDER_10_MSEC:
+ return 10;
+ case H_LONG_BUSY_ORDER_100_MSEC:
+ return 100;
+ case H_LONG_BUSY_ORDER_1_SEC:
+ return 1000;
+ case H_LONG_BUSY_ORDER_10_SEC:
+ return 10000;
+ case H_LONG_BUSY_ORDER_100_SEC:
+ return 100000;
+ default:
+ return 1;
+ }
+}
+
#ifdef CONFIG_PPC_PSERIES
extern int CMO_PrPSP;
extern int CMO_SecPSP;
diff --git a/drivers/infiniband/hw/ehca/hcp_if.c b/drivers/infiniband/hw/ehca/hcp_if.c
index 2d41d04..89517ff 100644
--- a/drivers/infiniband/hw/ehca/hcp_if.c
+++ b/drivers/infiniband/hw/ehca/hcp_if.c
@@ -90,26 +90,6 @@
static DEFINE_SPINLOCK(hcall_lock);
-static u32 get_longbusy_msecs(int longbusy_rc)
-{
- switch (longbusy_rc) {
- case H_LONG_BUSY_ORDER_1_MSEC:
- return 1;
- case H_LONG_BUSY_ORDER_10_MSEC:
- return 10;
- case H_LONG_BUSY_ORDER_100_MSEC:
- return 100;
- case H_LONG_BUSY_ORDER_1_SEC:
- return 1000;
- case H_LONG_BUSY_ORDER_10_SEC:
- return 10000;
- case H_LONG_BUSY_ORDER_100_SEC:
- return 100000;
- default:
- return 1;
- }
-}
-
static long ehca_plpar_hcall_norets(unsigned long opcode,
unsigned long arg1,
unsigned long arg2,
diff --git a/drivers/net/ethernet/ibm/ehea/ehea_phyp.h b/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
index 8364815..99b6c2a 100644
--- a/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
+++ b/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
@@ -39,26 +39,6 @@
* hcp_* - structures, variables and functions releated to Hypervisor Calls
*/
-static inline u32 get_longbusy_msecs(int long_busy_ret_code)
-{
- switch (long_busy_ret_code) {
- case H_LONG_BUSY_ORDER_1_MSEC:
- return 1;
- case H_LONG_BUSY_ORDER_10_MSEC:
- return 10;
- case H_LONG_BUSY_ORDER_100_MSEC:
- return 100;
- case H_LONG_BUSY_ORDER_1_SEC:
- return 1000;
- case H_LONG_BUSY_ORDER_10_SEC:
- return 10000;
- case H_LONG_BUSY_ORDER_100_SEC:
- return 100000;
- default:
- return 1;
- }
-}
-
/* Number of pages which can be registered at once by H_REGISTER_HEA_RPAGES */
#define EHEA_MAX_RPAGE 512
--
1.7.9.5
^ permalink raw reply related
* [PATCH 11/14] powerpc: Add wrappers to enable/disable relocation on exceptions
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
From: Ian Munsie <imunsie@au1.ibm.com>
These wrappers hide the parameters that have to be passed to H_SET_MODE
to enable/disable relocation on during exceptions.
As noted in the comments, since these have partition wide scope, they
may take some time to complete and must be periodically retried until
H_SUCCESS is returned.
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/platforms/pseries/plpar_wrappers.h | 25 +++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/plpar_wrappers.h b/arch/powerpc/platforms/pseries/plpar_wrappers.h
index 44ad214..e6cc34a 100644
--- a/arch/powerpc/platforms/pseries/plpar_wrappers.h
+++ b/arch/powerpc/platforms/pseries/plpar_wrappers.h
@@ -279,4 +279,29 @@ static inline long plpar_set_mode(unsigned long mflags, unsigned long resource,
{
return plpar_hcall_norets(H_SET_MODE, mflags, resource, value1, value2);
}
+
+/*
+ * Enable relocation on exceptions on this partition
+ *
+ * Note: this call has a partition wide scope and can take a while to complete.
+ * If it returns H_LONG_BUSY_* it should be retried periodically until it
+ * returns H_SUCCESS.
+ */
+static inline long enable_reloc_on_exceptions(void)
+{
+ /* mflags = 3: Exceptions at 0xC000000000004000 */
+ return plpar_set_mode(3, 3, 0, 0);
+}
+
+/*
+ * Disable relocation on exceptions on this partition
+ *
+ * Note: this call has a partition wide scope and can take a while to complete.
+ * If it returns H_LONG_BUSY_* it should be retried periodically until it
+ * returns H_SUCCESS.
+ */
+static inline long disable_reloc_on_exceptions(void) {
+ return plpar_set_mode(0, 3, 0, 0);
+}
+
#endif /* _PSERIES_PLPAR_WRAPPERS_H */
--
1.7.9.5
^ permalink raw reply related
* [PATCH 12/14] powerpc: Move get_longbusy_msecs into hvcall.h and remove duplicate function
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
From: Ian Munsie <imunsie@au1.ibm.com>
I am going to use this in the next patch, better to have this code in
one place rather than three.
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/include/asm/hvcall.h | 20 ++++++++++++++++++++
drivers/infiniband/hw/ehca/hcp_if.c | 20 --------------------
drivers/net/ethernet/ibm/ehea/ehea_phyp.h | 20 --------------------
3 files changed, 20 insertions(+), 40 deletions(-)
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index a3d26d8..0975e5c 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -356,6 +356,26 @@ struct hvcall_mpp_x_data {
int h_get_mpp_x(struct hvcall_mpp_x_data *mpp_x_data);
+static inline unsigned int get_longbusy_msecs(int longbusy_rc)
+{
+ switch (longbusy_rc) {
+ case H_LONG_BUSY_ORDER_1_MSEC:
+ return 1;
+ case H_LONG_BUSY_ORDER_10_MSEC:
+ return 10;
+ case H_LONG_BUSY_ORDER_100_MSEC:
+ return 100;
+ case H_LONG_BUSY_ORDER_1_SEC:
+ return 1000;
+ case H_LONG_BUSY_ORDER_10_SEC:
+ return 10000;
+ case H_LONG_BUSY_ORDER_100_SEC:
+ return 100000;
+ default:
+ return 1;
+ }
+}
+
#ifdef CONFIG_PPC_PSERIES
extern int CMO_PrPSP;
extern int CMO_SecPSP;
diff --git a/drivers/infiniband/hw/ehca/hcp_if.c b/drivers/infiniband/hw/ehca/hcp_if.c
index 2d41d04..89517ff 100644
--- a/drivers/infiniband/hw/ehca/hcp_if.c
+++ b/drivers/infiniband/hw/ehca/hcp_if.c
@@ -90,26 +90,6 @@
static DEFINE_SPINLOCK(hcall_lock);
-static u32 get_longbusy_msecs(int longbusy_rc)
-{
- switch (longbusy_rc) {
- case H_LONG_BUSY_ORDER_1_MSEC:
- return 1;
- case H_LONG_BUSY_ORDER_10_MSEC:
- return 10;
- case H_LONG_BUSY_ORDER_100_MSEC:
- return 100;
- case H_LONG_BUSY_ORDER_1_SEC:
- return 1000;
- case H_LONG_BUSY_ORDER_10_SEC:
- return 10000;
- case H_LONG_BUSY_ORDER_100_SEC:
- return 100000;
- default:
- return 1;
- }
-}
-
static long ehca_plpar_hcall_norets(unsigned long opcode,
unsigned long arg1,
unsigned long arg2,
diff --git a/drivers/net/ethernet/ibm/ehea/ehea_phyp.h b/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
index 8364815..99b6c2a 100644
--- a/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
+++ b/drivers/net/ethernet/ibm/ehea/ehea_phyp.h
@@ -39,26 +39,6 @@
* hcp_* - structures, variables and functions releated to Hypervisor Calls
*/
-static inline u32 get_longbusy_msecs(int long_busy_ret_code)
-{
- switch (long_busy_ret_code) {
- case H_LONG_BUSY_ORDER_1_MSEC:
- return 1;
- case H_LONG_BUSY_ORDER_10_MSEC:
- return 10;
- case H_LONG_BUSY_ORDER_100_MSEC:
- return 100;
- case H_LONG_BUSY_ORDER_1_SEC:
- return 1000;
- case H_LONG_BUSY_ORDER_10_SEC:
- return 10000;
- case H_LONG_BUSY_ORDER_100_SEC:
- return 100000;
- default:
- return 1;
- }
-}
-
/* Number of pages which can be registered at once by H_REGISTER_HEA_RPAGES */
#define EHEA_MAX_RPAGE 512
--
1.7.9.5
^ permalink raw reply related
* [PATCH 13/14] powerpc: Enable relocation on during exceptions at boot
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
From: Ian Munsie <imunsie@au1.ibm.com>
We currently do this synchronously at boot from setup_arch. On a large
system this could hypothetically take a little while to complete, so
currently we will give up if we are asked to wait for more than a second
in total.
If we actually start hitting that timeout in practice we can always move
this code into a kernel thread to take care of it in the background.
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
---
arch/powerpc/platforms/pseries/setup.c | 38 ++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index e3cb7ae..4c4adc0 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -367,6 +367,36 @@ static void pSeries_idle(void)
}
}
+/*
+ * Enable relocation on during exceptions. This has partition wide scope and
+ * may take a while to complete, if it takes longer than one second we will
+ * just give up rather than wasting any more time on this - if that turns out
+ * to ever be a problem in practice we can move this into a kernel thread to
+ * finish off the process later in boot.
+ */
+static int __init pSeries_enable_reloc_on_exc(void)
+{
+ long rc;
+ unsigned int delay, total_delay = 0;
+
+ while (1) {
+ rc = enable_reloc_on_exceptions();
+ if (!H_IS_LONG_BUSY(rc))
+ return rc;
+
+ delay = get_longbusy_msecs(rc);
+ total_delay += delay;
+ if (total_delay > 1000) {
+ pr_warn("Warning: Giving up waiting to enable "
+ "relocation on exceptions (%u msec)!\n",
+ total_delay);
+ return rc;
+ }
+
+ mdelay(delay);
+ }
+}
+
static void __init pSeries_setup_arch(void)
{
panic_timeout = 10;
@@ -402,6 +432,14 @@ static void __init pSeries_setup_arch(void)
ppc_md.enable_pmcs = pseries_lpar_enable_pmcs;
else
ppc_md.enable_pmcs = power4_enable_pmcs;
+
+ if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
+ long rc;
+ if ((rc = pSeries_enable_reloc_on_exc()) != H_SUCCESS) {
+ pr_warn("Unable to enable relocation on exceptions: "
+ "%ld\n", rc);
+ }
+ }
}
static int __init pSeries_init_panel(void)
--
1.7.9.5
^ permalink raw reply related
* [PATCH 14/14] powerpc: Disable relocation on exceptions when kexecing
From: Michael Neuling @ 2012-11-09 6:19 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Michael Neuling, linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
From: Ian Munsie <imunsie@au1.ibm.com>
Since we don't know if they new kernel we are kexecing into has been
built to support relocation on exceptions, we disable them before we
kexec.
We do NOT disable them if we are execing a kdump kernel, because we
want to change as little state as possible and it is likely that we are
execing ourselves and will be able to handle them anyway.
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/platforms/pseries/setup.c | 33 ++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 4c4adc0..47d2a7e 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -40,6 +40,7 @@
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/cpuidle.h>
+#include <linux/kexec.h>
#include <asm/mmu.h>
#include <asm/processor.h>
@@ -397,6 +398,35 @@ static int __init pSeries_enable_reloc_on_exc(void)
}
}
+#ifdef CONFIG_KEXEC
+static long pSeries_disable_reloc_on_exc(void)
+{
+ long rc;
+
+ while (1) {
+ rc = disable_reloc_on_exceptions();
+ if (!H_IS_LONG_BUSY(rc))
+ return rc;
+ mdelay(get_longbusy_msecs(rc));
+ }
+}
+
+static void pSeries_machine_kexec(struct kimage *image)
+{
+ long rc;
+
+ if (firmware_has_feature(FW_FEATURE_SET_MODE) &&
+ (image->type != KEXEC_TYPE_CRASH)) {
+ rc = pSeries_disable_reloc_on_exc();
+ if (rc != H_SUCCESS)
+ pr_warning("Warning: Failed to disable relocation on "
+ "exceptions: %ld\n", rc);
+ }
+
+ default_machine_kexec(image);
+}
+#endif
+
static void __init pSeries_setup_arch(void)
{
panic_timeout = 10;
@@ -697,4 +727,7 @@ define_machine(pseries) {
.progress = rtas_progress,
.system_reset_exception = pSeries_system_reset_exception,
.machine_check_exception = pSeries_machine_check_exception,
+#ifdef CONFIG_KEXEC
+ .machine_kexec = pSeries_machine_kexec,
+#endif
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH] powerpc/pseries: Update ibm, architecture.vec for PAPR 2.7/POWER8
From: Michael Neuling @ 2012-11-09 6:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linuxppc-dev
In-Reply-To: <1351661656-6986-4-git-send-email-mikey@neuling.org>
Update ibm,architecture.vec for POWER8 and allows us to support more
than one parition per core.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
v2: Missed some bits in the original post..
arch/powerpc/kernel/prom_init.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index cb6c123..9ffb542 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -671,6 +671,7 @@ static void __init early_cmdline_parse(void)
#define OV1_PPC_2_04 0x08 /* set if we support PowerPC 2.04 */
#define OV1_PPC_2_05 0x04 /* set if we support PowerPC 2.05 */
#define OV1_PPC_2_06 0x02 /* set if we support PowerPC 2.06 */
+#define OV1_PPC_2_07 0x01 /* set if we support PowerPC 2.07 */
/* Option vector 2: Open Firmware options supported */
#define OV2_REAL_MODE 0x20 /* set if we want OF in real mode */
@@ -707,6 +708,7 @@ static void __init early_cmdline_parse(void)
#define OV5_PFO_HW_RNG 0x80 /* PFO Random Number Generator */
#define OV5_PFO_HW_842 0x40 /* PFO Compression Accelerator */
#define OV5_PFO_HW_ENCR 0x20 /* PFO Encryption Accelerator */
+#define OV5_SUB_PROCESSORS 0x01 /* 1,2,or 4 Sub-Processors supported */
/* Option Vector 6: IBM PAPR hints */
#define OV6_LINUX 0x02 /* Linux is our OS */
@@ -719,6 +721,8 @@ static unsigned char ibm_architecture_vec[] = {
W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */
W(0xffff0000), W(0x003e0000), /* POWER6 */
W(0xffff0000), W(0x003f0000), /* POWER7 */
+ W(0xffff0000), W(0x004b0000), /* POWER8 */
+ W(0xffffffff), W(0x0f000004), /* all 2.07-compliant */
W(0xffffffff), W(0x0f000003), /* all 2.06-compliant */
W(0xffffffff), W(0x0f000002), /* all 2.05-compliant */
W(0xfffffffe), W(0x0f000001), /* all 2.04-compliant and earlier */
@@ -728,7 +732,7 @@ static unsigned char ibm_architecture_vec[] = {
3 - 2, /* length */
0, /* don't ignore, don't halt */
OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
- OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06,
+ OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07,
/* option vector 2: Open Firmware options supported */
34 - 2, /* length */
@@ -755,7 +759,7 @@ static unsigned char ibm_architecture_vec[] = {
OV4_MIN_ENT_CAP, /* minimum VP entitled capacity */
/* option vector 5: PAPR/OF options */
- 18 - 2, /* length */
+ 19 - 2, /* length */
0, /* don't ignore, don't halt */
OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES | OV5_DRCONF_MEMORY |
OV5_DONATE_DEDICATE_CPU | OV5_MSI,
@@ -776,6 +780,7 @@ static unsigned char ibm_architecture_vec[] = {
0,
0,
OV5_PFO_HW_RNG | OV5_PFO_HW_ENCR | OV5_PFO_HW_842,
+ OV5_SUB_PROCESSORS,
/* option vector 6: IBM PAPR hints */
4 - 2, /* length */
0,
--
1.7.9.5
^ permalink raw reply related
* [PATCH] powerpc: Add POWER8 architected mode to cputable
From: Michael Neuling @ 2012-11-09 6:26 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1351661656-6986-4-git-send-email-mikey@neuling.org>
A PVR of 0x0F000004 means we are arch v2.07 complicate ie, POWER8.
Signed-off-by: Michael Neuling <mikey@neuling.org>
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 216ff84..75a3d71 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -435,6 +435,21 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_restore = __restore_cpu_power7,
.platform = "power7",
},
+ { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
+ .pvr_mask = 0xffffffff,
+ .pvr_value = 0x0f000004,
+ .cpu_name = "POWER8 (architected)",
+ .cpu_features = CPU_FTRS_POWER8,
+ .cpu_user_features = COMMON_USER_POWER8,
+ .mmu_features = MMU_FTRS_POWER8,
+ .icache_bsize = 128,
+ .dcache_bsize = 128,
+ .oprofile_type = PPC_OPROFILE_POWER4,
+ .oprofile_cpu_type = "ppc64/ibm-compat-v1",
+ .cpu_setup = __setup_cpu_power8,
+ .cpu_restore = __restore_cpu_power8,
+ .platform = "power8",
+ },
{ /* Power7 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x003f0000,
^ permalink raw reply related
* Re: [PATCH 00/14] powerpc: Add support for POWER8 relocation on exceptions
From: Gabriel Paubert @ 2012-11-09 8:58 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-1-git-send-email-mikey@neuling.org>
On Fri, Nov 09, 2012 at 05:18:58PM +1100, Michael Neuling wrote:
> This set of patches adds support for taking exceptions with the MMU on which is
> supported by POWER8.
>
> A new set of exception vectors is added at 0xc000_0000_0000_4xxx. When the HW
> takes us here, MSR IR/DR will be set already and we no longer need a costly
> RFID to turn the MMU back on again.
>
> The original 0x0 based exception vectors remain for when the HW can't leave the
> MMU on. Examples of this are when we can't trust the current the MMU mappings,
^^^
Extra "the" (here and in a couple of patches).
Can't do much more since I don't have any hardware past G5, but the series
looks nice and avoiding transient excursions to real mode is a good thing.
Gabriel
> like when we are changing from guest to hypervisor (HV 0 -> 1) or when the MMU
> was off already. In these cases the HW will take us to the original 0x0 based
> exception vectors with the MMU off as before.
>
> The core of these patches were originally written by Matt Evans.
>
> Ian Munsie (5):
> powerpc: Add set_mode hcall
> powerpc: Add wrappers to enable/disable relocation on exceptions
> powerpc: Move get_longbusy_msecs into hvcall.h and remove duplicate
> function
> powerpc: Enable relocation on during exceptions at boot
> powerpc: Disable relocation on exceptions when kexecing
>
> Michael Neuling (9):
> powerpc: Add POWER8 architected mode to cputable
> powerpc: Whitespace changes in exception64s.S
> powerpc: Remove unessessary 0x3000 location enforcement
> powerpc: Make load_hander handle upto 64k offset
> powerpc: Turn syscall handler into macros
> powerpc: Add new macros needed for relocation on exceptions
> powerpc: Add relocation on exception vector handlers
> powerpc: Move initial mfspr LPCR out of __init_LPCR
> powerpc: Setup relocation on exceptions for bare metal systems
>
> arch/powerpc/include/asm/exception-64s.h | 97 ++++++-
> arch/powerpc/include/asm/firmware.h | 4 +-
> arch/powerpc/include/asm/hvcall.h | 23 +-
> arch/powerpc/include/asm/reg.h | 2 +
> arch/powerpc/kernel/cpu_setup_power.S | 8 +-
> arch/powerpc/kernel/cputable.c | 15 ++
> arch/powerpc/kernel/exceptions-64s.S | 306 +++++++++++++++++++----
> arch/powerpc/kernel/head_64.S | 3 +-
> arch/powerpc/kernel/setup_64.c | 5 +
> arch/powerpc/platforms/pseries/firmware.c | 1 +
> arch/powerpc/platforms/pseries/plpar_wrappers.h | 36 +++
> arch/powerpc/platforms/pseries/setup.c | 71 ++++++
> drivers/infiniband/hw/ehca/hcp_if.c | 20 --
> drivers/net/ethernet/ibm/ehea/ehea_phyp.h | 20 --
> 14 files changed, 516 insertions(+), 95 deletions(-)
>
> --
> 1.7.9.5
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH] powerpc: Add POWER8 architected mode to cputable
From: Gabriel Paubert @ 2012-11-09 8:47 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev
In-Reply-To: <30282.1352442402@neuling.org>
On Fri, Nov 09, 2012 at 05:26:42PM +1100, Michael Neuling wrote:
> A PVR of 0x0F000004 means we are arch v2.07 complicate ie, POWER8.
Huh?
s/complicate/compliant/ ?
Also ie has to be written with dots (i.e.).
Gabriel
>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
>
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
> index 216ff84..75a3d71 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -435,6 +435,21 @@ static struct cpu_spec __initdata cpu_specs[] = {
> .cpu_restore = __restore_cpu_power7,
> .platform = "power7",
> },
> + { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
> + .pvr_mask = 0xffffffff,
> + .pvr_value = 0x0f000004,
> + .cpu_name = "POWER8 (architected)",
> + .cpu_features = CPU_FTRS_POWER8,
> + .cpu_user_features = COMMON_USER_POWER8,
> + .mmu_features = MMU_FTRS_POWER8,
> + .icache_bsize = 128,
> + .dcache_bsize = 128,
> + .oprofile_type = PPC_OPROFILE_POWER4,
> + .oprofile_cpu_type = "ppc64/ibm-compat-v1",
> + .cpu_setup = __setup_cpu_power8,
> + .cpu_restore = __restore_cpu_power8,
> + .platform = "power8",
> + },
> { /* Power7 */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003f0000,
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH 12/14] powerpc: Move get_longbusy_msecs into hvcall.h and remove duplicate function
From: Stephen Rothwell @ 2012-11-09 9:26 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <1352441953-29096-14-git-send-email-mikey@neuling.org>
[-- Attachment #1: Type: text/plain, Size: 788 bytes --]
Hi Mikey,
On Fri, 9 Nov 2012 17:19:11 +1100 Michael Neuling <mikey@neuling.org> wrote:
>
> From: Ian Munsie <imunsie@au1.ibm.com>
>
> I am going to use this in the next patch, better to have this code in
> one place rather than three.
>
> Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
> ---
> arch/powerpc/include/asm/hvcall.h | 20 ++++++++++++++++++++
> drivers/infiniband/hw/ehca/hcp_if.c | 20 --------------------
> drivers/net/ethernet/ibm/ehea/ehea_phyp.h | 20 --------------------
> 3 files changed, 20 insertions(+), 40 deletions(-)
This is identical to patch 10/14 ...
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* Re: [PATCH 12/14] powerpc: Move get_longbusy_msecs into hvcall.h and remove duplicate function
From: Michael Neuling @ 2012-11-09 9:49 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <20121109202655.3a2b2876b97b39c581a36637@canb.auug.org.au>
Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> Hi Mikey,
>
> On Fri, 9 Nov 2012 17:19:11 +1100 Michael Neuling <mikey@neuling.org> wrote:
> >
> > From: Ian Munsie <imunsie@au1.ibm.com>
> >
> > I am going to use this in the next patch, better to have this code in
> > one place rather than three.
> >
> > Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
> > Signed-off-by: Michael Neuling <mikey@neuling.org>
> > ---
> > arch/powerpc/include/asm/hvcall.h | 20 ++++++++++++++++++++
> > drivers/infiniband/hw/ehca/hcp_if.c | 20 --------------------
> > drivers/net/ethernet/ibm/ehea/ehea_phyp.h | 20 --------------------
> > 3 files changed, 20 insertions(+), 40 deletions(-)
>
> This is identical to patch 10/14 ...
Actually, it's the same as 10/12. Looks like i didn't clear out my send
directory correctly.
10/14 is correct.
Thanks,
Mikey
^ permalink raw reply
* Re: [PATCH 00/14] powerpc: Add support for POWER8 relocation on exceptions
From: Michael Neuling @ 2012-11-09 9:51 UTC (permalink / raw)
To: Gabriel Paubert; +Cc: linuxppc-dev, Ian Munsie, Matt Evans
In-Reply-To: <20121109085815.GB13221@visitor2.iram.es>
> > This set of patches adds support for taking exceptions with the MMU on which is
> > supported by POWER8.
> >
> > A new set of exception vectors is added at 0xc000_0000_0000_4xxx. When the HW
> > takes us here, MSR IR/DR will be set already and we no longer need a costly
> > RFID to turn the MMU back on again.
> >
> > The original 0x0 based exception vectors remain for when the HW can't leave the
> > MMU on. Examples of this are when we can't trust the current the MMU mappings,
> ^^^
> Extra "the" (here and in a couple of patches).
Thanks, I'll fix.
> Can't do much more since I don't have any hardware past G5, but the
> series looks nice and avoiding transient excursions to real mode is a
> good thing.
Thanks.
Mikey
^ permalink raw reply
* Re: [PATCH] powerpc: Add POWER8 architected mode to cputable
From: Michael Neuling @ 2012-11-09 9:56 UTC (permalink / raw)
To: Gabriel Paubert; +Cc: linuxppc-dev
In-Reply-To: <20121109084708.GA13221@visitor2.iram.es>
> On Fri, Nov 09, 2012 at 05:26:42PM +1100, Michael Neuling wrote:
> > A PVR of 0x0F000004 means we are arch v2.07 complicate ie, POWER8.
>
> Huh?
>
> s/complicate/compliant/ ?
Yes, compliant. Thanks
> Also ie has to be written with dots (i.e.).
Thanks.
Mikey
^ permalink raw reply
* Re: perf: POWER-event translation questions
From: Stephane Eranian @ 2012-11-09 10:26 UTC (permalink / raw)
To: Sukadev Bhattiprolu
Cc: Peter Zijlstra, Robert Richter, Anton Blanchard, LKML,
linuxppc-dev, Ingo Molnar, Paul Mackerras,
Arnaldo Carvalho de Melo
In-Reply-To: <20121108011035.GA20670@us.ibm.com>
On Thu, Nov 8, 2012 at 2:10 AM, Sukadev Bhattiprolu
<sukadev@linux.vnet.ibm.com> wrote:
>
>
> Looking for feedback on this prototype for making POWER-specific event
> translations available in sysfs. It is based on the patchset:
>
> https://lkml.org/lkml/2012/11/7/402
>
> which makes the translations for _generic_ events in POWER available in sysfs:
>
> Since this is in POWER7 specific code I am assigning the names given in the
> POWER7 CPU spec for now.
>
> I had earlier tried mapping these events to generic names outside sysfs:
>
> Power7 name Generic name
>
> cmpl-stall-fxu stalled-cycles-fixed-point
> cmpl-stall-lsu stalled-cycles-load-store
> cmpl-stall-ifu stalled-cycles-instruction-fetch
> cmpl-stall-bru stalled-cycles-branch-unit
>
> But like Stephane Eranian pointed out mapping such events across architectures
> can be confusing.
>
> Another challenge I suspect we will have is the extremely long generic names
> we could end up with as the events get more specific.
>
> 1. Can we have more than one name for an event ? i.e two sysfs entries,
> eg: 'cmpl-stall-fxu' and 'stalled-cycles-fixed-point' for an event ?
>
Yes, you can. What is really used is the content of the file and two files
can have the same content.
> 2. Can we allow hyphens in the {name} token (please see my change to
> util/parse-events.l below). With this change, I can run:
>
The current code does not support this but Andi fixed that in his HSW patch
and I use it for the PEBS-LL patch series as well.
> perf stat -e cpu/cmplu-stall-bru /tmp/nop
>
> without any changes to the user level tool (parse-events.l) I have
> tested some common cases, not sure if it will break something :-)
>
> If we are going to create generic or arch specific sysfs entries in
> /sys/bus/event_source/devices/cpu/events, do we need to add corresponding
> entry in tools/perf/util/parse-events.l ?
>
Shouldn't be necessary. perf should grab those events automatically from sysfs.
As per Jiri, the hardcoded tables are only used to support backward
compatibility
for kernels without sysfs event entries.
> Sukadev
>
> ---
> arch/powerpc/perf/power7-pmu.c | 13 +++++++++++++
> tools/perf/util/parse-events.l | 2 +-
> 2 files changed, 14 insertions(+), 1 deletions(-)
>
> diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
> index aa9f588..9f46abc 100644
> --- a/arch/powerpc/perf/power7-pmu.c
> +++ b/arch/powerpc/perf/power7-pmu.c
> @@ -303,6 +303,10 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
> #define PM_LD_MISS_L1 0x400f0
> #define PM_BRU_FIN 0x10068
> #define PM_BRU_MPRED 0x400f6
> +#define PM_CMPLU_STALL_FXU 0x20014
> +#define PM_CMPLU_STALL_LSU 0x20012
> +#define PM_CMPLU_STALL_IFU 0x4004c
> +#define PM_CMPLU_STALL_BRU 0x4004e
>
> static int power7_generic_events[] = {
> [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
> @@ -369,6 +373,11 @@ EVENT_ATTR(cache-misses, LD_MISS_L1);
> EVENT_ATTR(branch-instructions, BRU_FIN);
> EVENT_ATTR(branch-misses, BRU_MPRED);
>
> +EVENT_ATTR(cmplu-stall-fxu, CMPLU_STALL_FXU);
> +EVENT_ATTR(cmplu-stall-lsu, CMPLU_STALL_LSU);
> +EVENT_ATTR(cmplu-stall-ifu, CMPLU_STALL_IFU);
> +EVENT_ATTR(cmplu-stall-bru, CMPLU_STALL_BRU);
> +
> static struct attribute *power7_events_attr[] = {
> EVENT_PTR(CYC),
> EVENT_PTR(GCT_NOSLOT_CYC),
> @@ -378,6 +387,10 @@ static struct attribute *power7_events_attr[] = {
> EVENT_PTR(LD_MISS_L1),
> EVENT_PTR(BRU_FIN),
> EVENT_PTR(BRU_MPRED),
> + EVENT_PTR(CMPLU_STALL_FXU),
> + EVENT_PTR(CMPLU_STALL_LSU),
> + EVENT_PTR(CMPLU_STALL_IFU),
> + EVENT_PTR(CMPLU_STALL_BRU),
> NULL,
> };
>
> diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l
> index c87efc1..1967bb2 100644
> --- a/tools/perf/util/parse-events.l
> +++ b/tools/perf/util/parse-events.l
> @@ -80,7 +80,7 @@ event [^,{}/]+
> num_dec [0-9]+
> num_hex 0x[a-fA-F0-9]+
> num_raw_hex [a-fA-F0-9]+
> -name [a-zA-Z_*?][a-zA-Z0-9_*?]*
> +name [-a-zA-Z_*?][-a-zA-Z0-9_*?]*
> modifier_event [ukhpGH]{1,8}
> modifier_bp [rwx]{1,3}
>
> --
> 1.7.1
>
^ permalink raw reply
* Hijacking CPU_FTR_VSX for BGQ QPX
From: Jimi Xenidis @ 2012-11-09 17:43 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Michael Neuling; +Cc: linuxppc-dev
The CPU_FTR_* values are pretty tight (a few bits left) yes I need to =
save and restore the QPX registers.
There are 32 QPX registers, each 32 bytes in size, it is otherwise =
managed by the FPSCR and MSR[FP]
I was thinking that I could hijack the VSX, since there is no plan to =
add it to embedded yet.
I could be explicit or create an alieas fo the same bit, but the basic =
effect (after increasing the save area size) would be something like the =
diff below.
Thoughts?
-jx
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index de36955..adb08af 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -25,14 +25,24 @@
#include <asm/asm-offsets.h>
#include <asm/ptrace.h>
=20
-#ifdef CONFIG_VSX
+#if defined (CONFIG_VSX) && defined(CONFIG_BGQ)
+# error "This code depends on CONFIG_VSX and CONFIG_BGQ being exclusive
+#elif defined (CONFIG_VSX)
+# define _REST_32VSRS(n,c,base) REST_32VSRS(n,c,base)
+# define _SAVE_32VSRS(n,c,base) SAVE_32VSRS(n,c,base)
+#elif defined(CONFIG_BGQ)
+# define _REST_32VSRS(n,c,base) REST_32QRS(n,c,base)
+# define _SAVE_32VSRS(n,c,base) SAVE_32QRS(n,c,base)
+#endif
+
+#if defined (CONFIG_VSX) || defined(CONFIG_BGQ)
#define REST_32FPVSRS(n,c,base) =
\
BEGIN_FTR_SECTION =
\
b 2f; =
\
END_FTR_SECTION_IFSET(CPU_FTR_VSX); =
\
REST_32FPRS(n,base); =
\
b 3f; =
\
-2: REST_32VSRS(n,c,base); =
\
+2: _REST_32VSRS(n,c,base); =
\
3:
=20
#define SAVE_32FPVSRS(n,c,base) =
\
@@ -41,7 +51,7 @@ BEGIN_FTR_SECTION =
\
END_FTR_SECTION_IFSET(CPU_FTR_VSX); =
\
SAVE_32FPRS(n,base); =
\
b 3f; =
\
-2: SAVE_32VSRS(n,c,base); =
\
+2: _SAVE_32VSRS(n,c,base); =
\
3:
#else
#define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
^ permalink raw reply related
* Re: Hijacking CPU_FTR_VSX for BGQ QPX
From: Benjamin Herrenschmidt @ 2012-11-09 19:57 UTC (permalink / raw)
To: Jimi Xenidis; +Cc: Michael Neuling, linuxppc-dev
In-Reply-To: <29970ED2-02E3-45F5-96FD-B4270385E3ED@pobox.com>
On Fri, 2012-11-09 at 11:43 -0600, Jimi Xenidis wrote:
> The CPU_FTR_* values are pretty tight (a few bits left) yes I need to save and restore the QPX registers.
> There are 32 QPX registers, each 32 bytes in size, it is otherwise managed by the FPSCR and MSR[FP]
>
> I was thinking that I could hijack the VSX, since there is no plan to add it to embedded yet.
> I could be explicit or create an alieas fo the same bit, but the basic effect (after increasing the save area size) would be something like the diff below.
> Thoughts?
Don't. Use a different bit, we can always split the mask again if
needed, move more bits to mmu_features etc...
> -#ifdef CONFIG_VSX
> +#if defined (CONFIG_VSX) && defined(CONFIG_BGQ)
> +# error "This code depends on CONFIG_VSX and CONFIG_BGQ being exclusive
> +#elif defined (CONFIG_VSX)
> +# define _REST_32VSRS(n,c,base) REST_32VSRS(n,c,base)
> +# define _SAVE_32VSRS(n,c,base) SAVE_32VSRS(n,c,base)
> +#elif defined(CONFIG_BGQ)
Make a CONFIG_PPC_QPX or something like that specifically for the QPX
stuff that you can then "select" from CONFIG_PPC_BGQ (don't do just
CONFIG_BGQ).
And don't just "hijack" stuff like that, it should be a runtime option,
so add a new set etc... it should be possible to build a kernel that
boots on a BGQ or a hypothetical BookE chip with VSX.
> +# define _REST_32VSRS(n,c,base) REST_32QRS(n,c,base)
> +# define _SAVE_32VSRS(n,c,base) SAVE_32QRS(n,c,base)
> +#endif
> +
> +#if defined (CONFIG_VSX) || defined(CONFIG_BGQ)
> #define REST_32FPVSRS(n,c,base) \
> BEGIN_FTR_SECTION \
> b 2f; \
> END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
> REST_32FPRS(n,base); \
> b 3f; \
> -2: REST_32VSRS(n,c,base); \
> +2: _REST_32VSRS(n,c,base); \
> 3:
>
> #define SAVE_32FPVSRS(n,c,base) \
> @@ -41,7 +51,7 @@ BEGIN_FTR_SECTION \
> END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
> SAVE_32FPRS(n,base); \
> b 3f; \
> -2: SAVE_32VSRS(n,c,base); \
> +2: _SAVE_32VSRS(n,c,base); \
> 3:
> #else
> #define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
Cheers,
Ben.
^ permalink raw reply
* Re: Hijacking CPU_FTR_VSX for BGQ QPX
From: Michael Neuling @ 2012-11-10 4:33 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1352491029.23412.3.camel@pasglop>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> On Fri, 2012-11-09 at 11:43 -0600, Jimi Xenidis wrote:
> > The CPU_FTR_* values are pretty tight (a few bits left) yes I need to save and restore the QPX registers.
> > There are 32 QPX registers, each 32 bytes in size, it is otherwise managed by the FPSCR and MSR[FP]
> >
> > I was thinking that I could hijack the VSX, since there is no plan to add it to embedded yet.
> > I could be explicit or create an alieas fo the same bit, but the basic effect (after increasing the save area size) would be something like the diff below.
> > Thoughts?
>
> Don't. Use a different bit, we can always split the mask again if
> needed, move more bits to mmu_features etc...
>
> > -#ifdef CONFIG_VSX
> > +#if defined (CONFIG_VSX) && defined(CONFIG_BGQ)
> > +# error "This code depends on CONFIG_VSX and CONFIG_BGQ being exclusive
> > +#elif defined (CONFIG_VSX)
> > +# define _REST_32VSRS(n,c,base) REST_32VSRS(n,c,base)
> > +# define _SAVE_32VSRS(n,c,base) SAVE_32VSRS(n,c,base)
> > +#elif defined(CONFIG_BGQ)
>
> Make a CONFIG_PPC_QPX or something like that specifically for the QPX
> stuff that you can then "select" from CONFIG_PPC_BGQ (don't do just
> CONFIG_BGQ).
>
> And don't just "hijack" stuff like that, it should be a runtime option,
> so add a new set etc... it should be possible to build a kernel that
> boots on a BGQ or a hypothetical BookE chip with VSX.
Yeah both bluegene and VSX are designed for HPC, so it's not completely
crazy that someone would put them together.
Also, we need to fix the CPU FTR issue. With PPR (Haren's stuff) and
POWER8 we are going to blow CPU FTRs pretty soon anyway. This just adds
to that.
Mikey
>
> > +# define _REST_32VSRS(n,c,base) REST_32QRS(n,c,base)
> > +# define _SAVE_32VSRS(n,c,base) SAVE_32QRS(n,c,base)
> > +#endif
> > +
> > +#if defined (CONFIG_VSX) || defined(CONFIG_BGQ)
> > #define REST_32FPVSRS(n,c,base) \
> > BEGIN_FTR_SECTION \
> > b 2f; \
> > END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
> > REST_32FPRS(n,base); \
> > b 3f; \
> > -2: REST_32VSRS(n,c,base); \
> > +2: _REST_32VSRS(n,c,base); \
> > 3:
> >
> > #define SAVE_32FPVSRS(n,c,base) \
> > @@ -41,7 +51,7 @@ BEGIN_FTR_SECTION \
> > END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
> > SAVE_32FPRS(n,base); \
> > b 3f; \
> > -2: SAVE_32VSRS(n,c,base); \
> > +2: _SAVE_32VSRS(n,c,base); \
> > 3:
> > #else
> > #define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
>
> Cheers,
> Ben.
>
>
^ permalink raw reply
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